From: Mario Limonciello <mario.limonciello@amd.com>
To: Alex Deucher <alexander.deucher@amd.com>, <linux-kernel@vger.kernel.org>
Cc: Javier Martinez Canillas <javierm@redhat.com>,
Carlos Soriano Sanchez <csoriano@redhat.com>,
<amd-gfx@lists.freedesktop.org>,
<dri-devel@lists.freedesktop.org>,
David Airlie <airlied@gmail.com>,
"Daniel Vetter" <daniel@ffwll.ch>, <christian.koenig@amd.com>,
Lazar Lijo <Lijo.Lazar@amd.com>,
Mario Limonciello <mario.limonciello@amd.com>,
"Pan, Xinhui" <Xinhui.Pan@amd.com>
Subject: [PATCH v6 11/45] drm/amd: Load MES microcode during early_init
Date: Wed, 4 Jan 2023 21:42:45 -0600 [thread overview]
Message-ID: <20230105034327.1439-12-mario.limonciello@amd.com> (raw)
In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com>
Add an early_init phase to MES for fetching and validating microcode
from the filesystem.
If MES microcode is required but not available during early init, the
firmware framebuffer will have already been released and the screen will
freeze.
Move the request for MES microcode into the early_init phase
so that if it's not available, early_init will fail.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 65 +++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 1 +
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 97 +++++--------------------
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 88 +++++-----------------
4 files changed, 100 insertions(+), 151 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 0c546245793b..dd8f35234507 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -21,6 +21,8 @@
*
*/
+#include <linux/firmware.h>
+
#include "amdgpu_mes.h"
#include "amdgpu.h"
#include "soc15_common.h"
@@ -1423,3 +1425,66 @@ int amdgpu_mes_self_test(struct amdgpu_device *adev)
kfree(vm);
return 0;
}
+
+int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe)
+{
+ const struct mes_firmware_header_v1_0 *mes_hdr;
+ struct amdgpu_firmware_info *info;
+ char ucode_prefix[30];
+ char fw_name[40];
+ int r;
+
+ amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes%s.bin",
+ ucode_prefix,
+ pipe == AMDGPU_MES_SCHED_PIPE ? "" : "1");
+ r = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev);
+ if (r)
+ goto out;
+
+ r = amdgpu_ucode_validate(adev->mes.fw[pipe]);
+ if (r)
+ goto out;
+
+ mes_hdr = (const struct mes_firmware_header_v1_0 *)
+ adev->mes.fw[pipe]->data;
+ adev->mes.uc_start_addr[pipe] =
+ le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) |
+ ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32);
+ adev->mes.data_start_addr[pipe] =
+ le32_to_cpu(mes_hdr->mes_data_start_addr_lo) |
+ ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32);
+
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ int ucode, ucode_data;
+
+ if (pipe == AMDGPU_MES_SCHED_PIPE) {
+ ucode = AMDGPU_UCODE_ID_CP_MES;
+ ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA;
+ } else {
+ ucode = AMDGPU_UCODE_ID_CP_MES1;
+ ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA;
+ }
+
+ info = &adev->firmware.ucode[ucode];
+ info->ucode_id = ucode;
+ info->fw = adev->mes.fw[pipe];
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes),
+ PAGE_SIZE);
+
+ info = &adev->firmware.ucode[ucode_data];
+ info->ucode_id = ucode_data;
+ info->fw = adev->mes.fw[pipe];
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes),
+ PAGE_SIZE);
+ }
+
+ return 0;
+
+out:
+ release_firmware(adev->mes.fw[pipe]);
+ adev->mes.fw[pipe] = NULL;
+ return r;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index 97c05d08a551..547ec35691fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -306,6 +306,7 @@ struct amdgpu_mes_funcs {
int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs);
+int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe);
int amdgpu_mes_init(struct amdgpu_device *adev);
void amdgpu_mes_fini(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 614394118a53..9c5ff8b7c202 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -379,82 +379,6 @@ static const struct amdgpu_mes_funcs mes_v10_1_funcs = {
.resume_gang = mes_v10_1_resume_gang,
};
-static int mes_v10_1_init_microcode(struct amdgpu_device *adev,
- enum admgpu_mes_pipe pipe)
-{
- const char *chip_name;
- char fw_name[30];
- int err;
- const struct mes_firmware_header_v1_0 *mes_hdr;
- struct amdgpu_firmware_info *info;
-
- switch (adev->ip_versions[GC_HWIP][0]) {
- case IP_VERSION(10, 1, 10):
- chip_name = "navi10";
- break;
- case IP_VERSION(10, 3, 0):
- chip_name = "sienna_cichlid";
- break;
- default:
- BUG();
- }
-
- if (pipe == AMDGPU_MES_SCHED_PIPE)
- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin",
- chip_name);
- else
- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin",
- chip_name);
-
- err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev);
- if (err)
- return err;
-
- err = amdgpu_ucode_validate(adev->mes.fw[pipe]);
- if (err) {
- release_firmware(adev->mes.fw[pipe]);
- adev->mes.fw[pipe] = NULL;
- return err;
- }
-
- mes_hdr = (const struct mes_firmware_header_v1_0 *)
- adev->mes.fw[pipe]->data;
- adev->mes.uc_start_addr[pipe] =
- le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) |
- ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32);
- adev->mes.data_start_addr[pipe] =
- le32_to_cpu(mes_hdr->mes_data_start_addr_lo) |
- ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32);
-
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
- int ucode, ucode_data;
-
- if (pipe == AMDGPU_MES_SCHED_PIPE) {
- ucode = AMDGPU_UCODE_ID_CP_MES;
- ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA;
- } else {
- ucode = AMDGPU_UCODE_ID_CP_MES1;
- ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA;
- }
-
- info = &adev->firmware.ucode[ucode];
- info->ucode_id = ucode;
- info->fw = adev->mes.fw[pipe];
- adev->firmware.fw_size +=
- ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes),
- PAGE_SIZE);
-
- info = &adev->firmware.ucode[ucode_data];
- info->ucode_id = ucode_data;
- info->fw = adev->mes.fw[pipe];
- adev->firmware.fw_size +=
- ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes),
- PAGE_SIZE);
- }
-
- return 0;
-}
-
static void mes_v10_1_free_microcode(struct amdgpu_device *adev,
enum admgpu_mes_pipe pipe)
{
@@ -1019,10 +943,6 @@ static int mes_v10_1_sw_init(void *handle)
if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
continue;
- r = mes_v10_1_init_microcode(adev, pipe);
- if (r)
- return r;
-
r = mes_v10_1_allocate_eop_buf(adev, pipe);
if (r)
return r;
@@ -1229,6 +1149,22 @@ static int mes_v10_1_resume(void *handle)
return amdgpu_mes_resume(adev);
}
+static int mes_v10_0_early_init(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int pipe, r;
+
+ for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
+ if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
+ continue;
+ r = amdgpu_mes_init_microcode(adev, pipe);
+ if (r)
+ return r;
+ }
+
+ return 0;
+}
+
static int mes_v10_0_late_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1241,6 +1177,7 @@ static int mes_v10_0_late_init(void *handle)
static const struct amd_ip_funcs mes_v10_1_ip_funcs = {
.name = "mes_v10_1",
+ .early_init = mes_v10_0_early_init,
.late_init = mes_v10_0_late_init,
.sw_init = mes_v10_1_sw_init,
.sw_fini = mes_v10_1_sw_fini,
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 970b066b37bb..3af77a32baac 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -459,73 +459,6 @@ static const struct amdgpu_mes_funcs mes_v11_0_funcs = {
.misc_op = mes_v11_0_misc_op,
};
-static int mes_v11_0_init_microcode(struct amdgpu_device *adev,
- enum admgpu_mes_pipe pipe)
-{
- char fw_name[30];
- char ucode_prefix[30];
- int err;
- const struct mes_firmware_header_v1_0 *mes_hdr;
- struct amdgpu_firmware_info *info;
-
- amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
-
- if (pipe == AMDGPU_MES_SCHED_PIPE)
- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin",
- ucode_prefix);
- else
- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin",
- ucode_prefix);
-
- err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev);
- if (err)
- return err;
-
- err = amdgpu_ucode_validate(adev->mes.fw[pipe]);
- if (err) {
- release_firmware(adev->mes.fw[pipe]);
- adev->mes.fw[pipe] = NULL;
- return err;
- }
-
- mes_hdr = (const struct mes_firmware_header_v1_0 *)
- adev->mes.fw[pipe]->data;
- adev->mes.uc_start_addr[pipe] =
- le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) |
- ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32);
- adev->mes.data_start_addr[pipe] =
- le32_to_cpu(mes_hdr->mes_data_start_addr_lo) |
- ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32);
-
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
- int ucode, ucode_data;
-
- if (pipe == AMDGPU_MES_SCHED_PIPE) {
- ucode = AMDGPU_UCODE_ID_CP_MES;
- ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA;
- } else {
- ucode = AMDGPU_UCODE_ID_CP_MES1;
- ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA;
- }
-
- info = &adev->firmware.ucode[ucode];
- info->ucode_id = ucode;
- info->fw = adev->mes.fw[pipe];
- adev->firmware.fw_size +=
- ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes),
- PAGE_SIZE);
-
- info = &adev->firmware.ucode[ucode_data];
- info->ucode_id = ucode_data;
- info->fw = adev->mes.fw[pipe];
- adev->firmware.fw_size +=
- ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes),
- PAGE_SIZE);
- }
-
- return 0;
-}
-
static void mes_v11_0_free_microcode(struct amdgpu_device *adev,
enum admgpu_mes_pipe pipe)
{
@@ -1100,10 +1033,6 @@ static int mes_v11_0_sw_init(void *handle)
if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
continue;
- r = mes_v11_0_init_microcode(adev, pipe);
- if (r)
- return r;
-
r = mes_v11_0_allocate_eop_buf(adev, pipe);
if (r)
return r;
@@ -1338,6 +1267,22 @@ static int mes_v11_0_resume(void *handle)
return amdgpu_mes_resume(adev);
}
+static int mes_v11_0_early_init(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int pipe, r;
+
+ for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
+ if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
+ continue;
+ r = amdgpu_mes_init_microcode(adev, pipe);
+ if (r)
+ return r;
+ }
+
+ return 0;
+}
+
static int mes_v11_0_late_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1352,6 +1297,7 @@ static int mes_v11_0_late_init(void *handle)
static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
.name = "mes_v11_0",
+ .early_init = mes_v11_0_early_init,
.late_init = mes_v11_0_late_init,
.sw_init = mes_v11_0_sw_init,
.sw_fini = mes_v11_0_sw_fini,
--
2.34.1
next prev parent reply other threads:[~2023-01-05 3:45 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-05 3:42 [PATCH v6 00/45] Recover from failure to probe GPU Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 01/45] drm/amd: Delay removal of the firmware framebuffer Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 02/45] drm/amd: Add a legacy mapping to "amdgpu_ucode_ip_version_decode" Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 03/45] drm/amd: Convert SMUv11 microcode to use `amdgpu_ucode_ip_version_decode` Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 04/45] drm/amd: Convert SMUv13 " Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 05/45] drm/amd: Add a new helper for loading/validating microcode Mario Limonciello
2023-01-05 5:07 ` Lazar, Lijo
2023-01-05 5:23 ` Mario Limonciello
2023-01-05 5:29 ` Lazar, Lijo
2023-01-05 5:37 ` Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 06/45] drm/amd: Use `amdgpu_ucode_request` helper for SDMA Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 07/45] drm/amd: Convert SDMA to use `amdgpu_ucode_ip_version_decode` Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 08/45] drm/amd: Make SDMA firmware load failures less noisy Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 09/45] drm/amd: Use `amdgpu_ucode_*` helpers for VCN Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 10/45] drm/amd: Load VCN microcode during early_init Mario Limonciello
2023-01-05 3:42 ` Mario Limonciello [this message]
2023-01-05 3:42 ` [PATCH v6 12/45] drm/amd: Use `amdgpu_ucode_*` helpers for MES Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 13/45] drm/amd: Remove superfluous assignment for `adev->mes.adev` Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 14/45] drm/amd: Use `amdgpu_ucode_*` helpers for GFX9 Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 15/45] drm/amd: Load GFX9 microcode during early_init Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 16/45] drm/amd: Use `amdgpu_ucode_*` helpers for GFX10 Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 17/45] drm/amd: Load GFX10 microcode during early_init Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 18/45] drm/amd: Use `amdgpu_ucode_*` helpers for GFX11 Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 19/45] drm/amd: Load GFX11 microcode during early_init Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 20/45] drm/amd: Parse both v1 and v2 TA microcode headers using same function Mario Limonciello
2023-01-05 13:22 ` Lazar, Lijo
2023-01-05 16:04 ` Limonciello, Mario
2023-01-05 3:42 ` [PATCH v6 21/45] drm/amd: Avoid BUG() for case of SRIOV missing IP version Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 22/45] drm/amd: Load PSP microcode during early_init Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 23/45] drm/amd: Use `amdgpu_ucode_*` helpers for PSP Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 24/45] drm/amd/display: Load DMUB microcode during early_init Mario Limonciello
2023-01-05 3:42 ` [PATCH v6 25/45] drm/amd: Use `amdgpu_ucode_release` helper for DMUB Mario Limonciello
2023-01-05 17:17 ` Harry Wentland
2023-01-05 3:43 ` [PATCH v6 26/45] drm/amd: Use `amdgpu_ucode_*` helpers for SMU Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 27/45] drm/amd: Load SMU microcode during early_init Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 28/45] drm/amd: Optimize SRIOV switch/case for PSP microcode load Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 29/45] drm/amd: Use `amdgpu_ucode_*` helpers for GFX6 Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 30/45] drm/amd: Use `amdgpu_ucode_*` helpers for GFX7 Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 31/45] drm/amd: Use `amdgpu_ucode_*` helpers for GFX8 Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 32/45] drm/amd: Use `amdgpu_ucode_*` helpers for GMC6 Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 33/45] drm/amd: Use `amdgpu_ucode_*` helpers for GMC7 Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 34/45] drm/amd: Use `amdgpu_ucode_*` helpers for GMC8 Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 35/45] drm/amd: Use `amdgpu_ucode_*` helpers for SDMA2.4 Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 36/45] drm/amd: Use `amdgpu_ucode_*` helpers for SDMA3.0 Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 37/45] drm/amd: Use `amdgpu_ucode_*` helpers for SDMA on CIK Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 38/45] drm/amd: Use `amdgpu_ucode_*` helpers for UVD Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 39/45] drm/amd: Use `amdgpu_ucode_*` helpers for VCE Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 40/45] drm/amd: Use `amdgpu_ucode_*` helpers for CGS Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 41/45] drm/amd: Use `amdgpu_ucode_*` helpers for GPU info bin Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 42/45] drm/amd: Use `amdgpu_ucode_*` helpers for DMCU Mario Limonciello
2023-01-05 17:18 ` Harry Wentland
2023-01-05 3:43 ` [PATCH v6 43/45] drm/amd: Use `amdgpu_ucode_release` helper for powerplay Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 44/45] drm/amd: Use `amdgpu_ucode_release` helper for si Mario Limonciello
2023-01-05 3:43 ` [PATCH v6 45/45] drm/amd: make amdgpu_ucode_validate static Mario Limonciello
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