* [PATCH 2/5] arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes
2023-05-15 17:21 [PATCH 1/5] arm64: dts: ti: k3-j721e-beagleboneai64: Fix mailbox node status Andrew Davis
@ 2023-05-15 17:21 ` Andrew Davis
2023-05-16 16:22 ` Verma, Achal
2023-05-15 17:21 ` [PATCH 3/5] arm64: dts: ti: k3-j721e: Enable PCIe nodes at the board level Andrew Davis
` (4 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Andrew Davis @ 2023-05-15 17:21 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Robert Nelson
Cc: linux-arm-kernel, devicetree, linux-kernel, Andrew Davis
These nodes are example nodes for the PCIe controller in "endpoint" mode.
By default the controller is in "root complex" mode and there is already a
DT node for the same.
Examples should go in the bindings or other documentation.
Remove this node.
Signed-off-by: Andrew Davis <afd@ti.com>
---
.../boot/dts/ti/k3-j721e-beagleboneai64.dts | 24 ------
.../dts/ti/k3-j721e-common-proc-board.dts | 25 ------
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 82 -------------------
arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 24 ------
4 files changed, 155 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
index 8a62ac263b89..d77eeff0d81d 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
@@ -892,35 +892,11 @@ &pcie2_rc {
status = "disabled";
};
-&pcie0_ep {
- status = "disabled";
- phys = <&serdes0_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <1>;
-};
-
-&pcie1_ep {
- status = "disabled";
- phys = <&serdes1_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <2>;
-};
-
-&pcie2_ep {
- /* Unused */
- status = "disabled";
-};
-
&pcie3_rc {
/* Unused */
status = "disabled";
};
-&pcie3_ep {
- /* Unused */
- status = "disabled";
-};
-
&icssg0_mdio {
/* Unused */
status = "disabled";
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 7db0603125aa..87b7263f6547 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -840,35 +840,10 @@ &pcie2_rc {
num-lanes = <2>;
};
-&pcie0_ep {
- phys = <&serdes0_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <1>;
- status = "disabled";
-};
-
-&pcie1_ep {
- phys = <&serdes1_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <2>;
- status = "disabled";
-};
-
-&pcie2_ep {
- phys = <&serdes2_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <2>;
- status = "disabled";
-};
-
&pcie3_rc {
status = "disabled";
};
-&pcie3_ep {
- status = "disabled";
-};
-
&icssg0_mdio {
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 10c8a5fb4ee2..e39f6d1e8d40 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -816,26 +816,6 @@ pcie0_rc: pcie@2900000 {
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
};
- pcie0_ep: pcie-ep@2900000 {
- compatible = "ti,j721e-pcie-ep";
- reg = <0x00 0x02900000 0x00 0x1000>,
- <0x00 0x02907000 0x00 0x400>,
- <0x00 0x0d000000 0x00 0x00800000>,
- <0x00 0x10000000 0x00 0x08000000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "mem";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
- max-link-speed = <3>;
- num-lanes = <2>;
- power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 239 1>;
- clock-names = "fck";
- max-functions = /bits/ 8 <6>;
- max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
- dma-coherent;
- };
-
pcie1_rc: pcie@2910000 {
compatible = "ti,j721e-pcie-host";
reg = <0x00 0x02910000 0x00 0x1000>,
@@ -864,26 +844,6 @@ pcie1_rc: pcie@2910000 {
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
};
- pcie1_ep: pcie-ep@2910000 {
- compatible = "ti,j721e-pcie-ep";
- reg = <0x00 0x02910000 0x00 0x1000>,
- <0x00 0x02917000 0x00 0x400>,
- <0x00 0x0d800000 0x00 0x00800000>,
- <0x00 0x18000000 0x00 0x08000000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "mem";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
- max-link-speed = <3>;
- num-lanes = <2>;
- power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 240 1>;
- clock-names = "fck";
- max-functions = /bits/ 8 <6>;
- max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
- dma-coherent;
- };
-
pcie2_rc: pcie@2920000 {
compatible = "ti,j721e-pcie-host";
reg = <0x00 0x02920000 0x00 0x1000>,
@@ -912,26 +872,6 @@ pcie2_rc: pcie@2920000 {
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
};
- pcie2_ep: pcie-ep@2920000 {
- compatible = "ti,j721e-pcie-ep";
- reg = <0x00 0x02920000 0x00 0x1000>,
- <0x00 0x02927000 0x00 0x400>,
- <0x00 0x0e000000 0x00 0x00800000>,
- <0x44 0x00000000 0x00 0x08000000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "mem";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
- max-link-speed = <3>;
- num-lanes = <2>;
- power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 241 1>;
- clock-names = "fck";
- max-functions = /bits/ 8 <6>;
- max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
- dma-coherent;
- };
-
pcie3_rc: pcie@2930000 {
compatible = "ti,j721e-pcie-host";
reg = <0x00 0x02930000 0x00 0x1000>,
@@ -960,28 +900,6 @@ pcie3_rc: pcie@2930000 {
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
};
- pcie3_ep: pcie-ep@2930000 {
- compatible = "ti,j721e-pcie-ep";
- reg = <0x00 0x02930000 0x00 0x1000>,
- <0x00 0x02937000 0x00 0x400>,
- <0x00 0x0e800000 0x00 0x00800000>,
- <0x44 0x10000000 0x00 0x08000000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "mem";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
- max-link-speed = <3>;
- num-lanes = <2>;
- power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 242 1>;
- clock-names = "fck";
- max-functions = /bits/ 8 <6>;
- max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
- dma-coherent;
- #address-cells = <2>;
- #size-cells = <2>;
- };
-
serdes_wiz4: wiz@5050000 {
compatible = "ti,am64-wiz-10g";
#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index f650a7fd66b4..07d3282a583b 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -896,35 +896,11 @@ &pcie2_rc {
status = "disabled";
};
-&pcie0_ep {
- status = "disabled";
- phys = <&serdes0_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <1>;
-};
-
-&pcie1_ep {
- status = "disabled";
- phys = <&serdes1_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <2>;
-};
-
-&pcie2_ep {
- /* Unused */
- status = "disabled";
-};
-
&pcie3_rc {
/* Unused */
status = "disabled";
};
-&pcie3_ep {
- /* Unused */
- status = "disabled";
-};
-
&icssg0_mdio {
status = "disabled";
};
--
2.39.2
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 2/5] arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes
2023-05-15 17:21 ` [PATCH 2/5] arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes Andrew Davis
@ 2023-05-16 16:22 ` Verma, Achal
2023-05-16 16:27 ` Andrew Davis
0 siblings, 1 reply; 12+ messages in thread
From: Verma, Achal @ 2023-05-16 16:22 UTC (permalink / raw)
To: Andrew Davis, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Rob Herring, Krzysztof Kozlowski, Robert Nelson
Cc: linux-arm-kernel, devicetree, linux-kernel, Achal Verma
On 5/15/2023 10:51 PM, Andrew Davis wrote:
> These nodes are example nodes for the PCIe controller in "endpoint" mode.
> By default the controller is in "root complex" mode and there is already a
> DT node for the same.
>
> Examples should go in the bindings or other documentation.
>
> Remove this node.
How we will support EP from now onwards, using overlays ?
Regards,
Achal Verma
>
> Signed-off-by: Andrew Davis <afd@ti.com>
> ---
> .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 24 ------
> .../dts/ti/k3-j721e-common-proc-board.dts | 25 ------
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 82 -------------------
> arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 24 ------
> 4 files changed, 155 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> index 8a62ac263b89..d77eeff0d81d 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> @@ -892,35 +892,11 @@ &pcie2_rc {
> status = "disabled";
> };
>
> -&pcie0_ep {
> - status = "disabled";
> - phys = <&serdes0_pcie_link>;
> - phy-names = "pcie-phy";
> - num-lanes = <1>;
> -};
> -
> -&pcie1_ep {
> - status = "disabled";
> - phys = <&serdes1_pcie_link>;
> - phy-names = "pcie-phy";
> - num-lanes = <2>;
> -};
> -
> -&pcie2_ep {
> - /* Unused */
> - status = "disabled";
> -};
> -
> &pcie3_rc {
> /* Unused */
> status = "disabled";
> };
>
> -&pcie3_ep {
> - /* Unused */
> - status = "disabled";
> -};
> -
> &icssg0_mdio {
> /* Unused */
> status = "disabled";
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> index 7db0603125aa..87b7263f6547 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> @@ -840,35 +840,10 @@ &pcie2_rc {
> num-lanes = <2>;
> };
>
> -&pcie0_ep {
> - phys = <&serdes0_pcie_link>;
> - phy-names = "pcie-phy";
> - num-lanes = <1>;
> - status = "disabled";
> -};
> -
> -&pcie1_ep {
> - phys = <&serdes1_pcie_link>;
> - phy-names = "pcie-phy";
> - num-lanes = <2>;
> - status = "disabled";
> -};
> -
> -&pcie2_ep {
> - phys = <&serdes2_pcie_link>;
> - phy-names = "pcie-phy";
> - num-lanes = <2>;
> - status = "disabled";
> -};
> -
> &pcie3_rc {
> status = "disabled";
> };
>
> -&pcie3_ep {
> - status = "disabled";
> -};
> -
> &icssg0_mdio {
> status = "disabled";
> };
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index 10c8a5fb4ee2..e39f6d1e8d40 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -816,26 +816,6 @@ pcie0_rc: pcie@2900000 {
> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
> };
>
> - pcie0_ep: pcie-ep@2900000 {
> - compatible = "ti,j721e-pcie-ep";
> - reg = <0x00 0x02900000 0x00 0x1000>,
> - <0x00 0x02907000 0x00 0x400>,
> - <0x00 0x0d000000 0x00 0x00800000>,
> - <0x00 0x10000000 0x00 0x08000000>;
> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
> - interrupt-names = "link_state";
> - interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
> - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
> - max-link-speed = <3>;
> - num-lanes = <2>;
> - power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
> - clocks = <&k3_clks 239 1>;
> - clock-names = "fck";
> - max-functions = /bits/ 8 <6>;
> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
> - dma-coherent;
> - };
> -
> pcie1_rc: pcie@2910000 {
> compatible = "ti,j721e-pcie-host";
> reg = <0x00 0x02910000 0x00 0x1000>,
> @@ -864,26 +844,6 @@ pcie1_rc: pcie@2910000 {
> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
> };
>
> - pcie1_ep: pcie-ep@2910000 {
> - compatible = "ti,j721e-pcie-ep";
> - reg = <0x00 0x02910000 0x00 0x1000>,
> - <0x00 0x02917000 0x00 0x400>,
> - <0x00 0x0d800000 0x00 0x00800000>,
> - <0x00 0x18000000 0x00 0x08000000>;
> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
> - interrupt-names = "link_state";
> - interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
> - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
> - max-link-speed = <3>;
> - num-lanes = <2>;
> - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
> - clocks = <&k3_clks 240 1>;
> - clock-names = "fck";
> - max-functions = /bits/ 8 <6>;
> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
> - dma-coherent;
> - };
> -
> pcie2_rc: pcie@2920000 {
> compatible = "ti,j721e-pcie-host";
> reg = <0x00 0x02920000 0x00 0x1000>,
> @@ -912,26 +872,6 @@ pcie2_rc: pcie@2920000 {
> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
> };
>
> - pcie2_ep: pcie-ep@2920000 {
> - compatible = "ti,j721e-pcie-ep";
> - reg = <0x00 0x02920000 0x00 0x1000>,
> - <0x00 0x02927000 0x00 0x400>,
> - <0x00 0x0e000000 0x00 0x00800000>,
> - <0x44 0x00000000 0x00 0x08000000>;
> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
> - interrupt-names = "link_state";
> - interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
> - ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
> - max-link-speed = <3>;
> - num-lanes = <2>;
> - power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
> - clocks = <&k3_clks 241 1>;
> - clock-names = "fck";
> - max-functions = /bits/ 8 <6>;
> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
> - dma-coherent;
> - };
> -
> pcie3_rc: pcie@2930000 {
> compatible = "ti,j721e-pcie-host";
> reg = <0x00 0x02930000 0x00 0x1000>,
> @@ -960,28 +900,6 @@ pcie3_rc: pcie@2930000 {
> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
> };
>
> - pcie3_ep: pcie-ep@2930000 {
> - compatible = "ti,j721e-pcie-ep";
> - reg = <0x00 0x02930000 0x00 0x1000>,
> - <0x00 0x02937000 0x00 0x400>,
> - <0x00 0x0e800000 0x00 0x00800000>,
> - <0x44 0x10000000 0x00 0x08000000>;
> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
> - interrupt-names = "link_state";
> - interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
> - ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
> - max-link-speed = <3>;
> - num-lanes = <2>;
> - power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
> - clocks = <&k3_clks 242 1>;
> - clock-names = "fck";
> - max-functions = /bits/ 8 <6>;
> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
> - dma-coherent;
> - #address-cells = <2>;
> - #size-cells = <2>;
> - };
> -
> serdes_wiz4: wiz@5050000 {
> compatible = "ti,am64-wiz-10g";
> #address-cells = <1>;
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> index f650a7fd66b4..07d3282a583b 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> @@ -896,35 +896,11 @@ &pcie2_rc {
> status = "disabled";
> };
>
> -&pcie0_ep {
> - status = "disabled";
> - phys = <&serdes0_pcie_link>;
> - phy-names = "pcie-phy";
> - num-lanes = <1>;
> -};
> -
> -&pcie1_ep {
> - status = "disabled";
> - phys = <&serdes1_pcie_link>;
> - phy-names = "pcie-phy";
> - num-lanes = <2>;
> -};
> -
> -&pcie2_ep {
> - /* Unused */
> - status = "disabled";
> -};
> -
> &pcie3_rc {
> /* Unused */
> status = "disabled";
> };
>
> -&pcie3_ep {
> - /* Unused */
> - status = "disabled";
> -};
> -
> &icssg0_mdio {
> status = "disabled";
> };
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 2/5] arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes
2023-05-16 16:22 ` Verma, Achal
@ 2023-05-16 16:27 ` Andrew Davis
2023-06-05 14:54 ` Verma, Achal
0 siblings, 1 reply; 12+ messages in thread
From: Andrew Davis @ 2023-05-16 16:27 UTC (permalink / raw)
To: Verma, Achal, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Rob Herring, Krzysztof Kozlowski, Robert Nelson
Cc: linux-arm-kernel, devicetree, linux-kernel
On 5/16/23 11:22 AM, Verma, Achal wrote:
>
>
> On 5/15/2023 10:51 PM, Andrew Davis wrote:
>> These nodes are example nodes for the PCIe controller in "endpoint" mode.
>> By default the controller is in "root complex" mode and there is already a
>> DT node for the same.
>>
>> Examples should go in the bindings or other documentation.
>>
>> Remove this node.
> How we will support EP from now onwards, using overlays ?
>
They are already disabled, how do you support them today?
Andrew
> Regards,
> Achal Verma
>>
>> Signed-off-by: Andrew Davis <afd@ti.com>
>> ---
>> .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 24 ------
>> .../dts/ti/k3-j721e-common-proc-board.dts | 25 ------
>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 82 -------------------
>> arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 24 ------
>> 4 files changed, 155 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>> index 8a62ac263b89..d77eeff0d81d 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>> @@ -892,35 +892,11 @@ &pcie2_rc {
>> status = "disabled";
>> };
>> -&pcie0_ep {
>> - status = "disabled";
>> - phys = <&serdes0_pcie_link>;
>> - phy-names = "pcie-phy";
>> - num-lanes = <1>;
>> -};
>> -
>> -&pcie1_ep {
>> - status = "disabled";
>> - phys = <&serdes1_pcie_link>;
>> - phy-names = "pcie-phy";
>> - num-lanes = <2>;
>> -};
>> -
>> -&pcie2_ep {
>> - /* Unused */
>> - status = "disabled";
>> -};
>> -
>> &pcie3_rc {
>> /* Unused */
>> status = "disabled";
>> };
>> -&pcie3_ep {
>> - /* Unused */
>> - status = "disabled";
>> -};
>> -
>> &icssg0_mdio {
>> /* Unused */
>> status = "disabled";
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>> index 7db0603125aa..87b7263f6547 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>> @@ -840,35 +840,10 @@ &pcie2_rc {
>> num-lanes = <2>;
>> };
>> -&pcie0_ep {
>> - phys = <&serdes0_pcie_link>;
>> - phy-names = "pcie-phy";
>> - num-lanes = <1>;
>> - status = "disabled";
>> -};
>> -
>> -&pcie1_ep {
>> - phys = <&serdes1_pcie_link>;
>> - phy-names = "pcie-phy";
>> - num-lanes = <2>;
>> - status = "disabled";
>> -};
>> -
>> -&pcie2_ep {
>> - phys = <&serdes2_pcie_link>;
>> - phy-names = "pcie-phy";
>> - num-lanes = <2>;
>> - status = "disabled";
>> -};
>> -
>> &pcie3_rc {
>> status = "disabled";
>> };
>> -&pcie3_ep {
>> - status = "disabled";
>> -};
>> -
>> &icssg0_mdio {
>> status = "disabled";
>> };
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> index 10c8a5fb4ee2..e39f6d1e8d40 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> @@ -816,26 +816,6 @@ pcie0_rc: pcie@2900000 {
>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>> };
>> - pcie0_ep: pcie-ep@2900000 {
>> - compatible = "ti,j721e-pcie-ep";
>> - reg = <0x00 0x02900000 0x00 0x1000>,
>> - <0x00 0x02907000 0x00 0x400>,
>> - <0x00 0x0d000000 0x00 0x00800000>,
>> - <0x00 0x10000000 0x00 0x08000000>;
>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>> - interrupt-names = "link_state";
>> - interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
>> - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
>> - max-link-speed = <3>;
>> - num-lanes = <2>;
>> - power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
>> - clocks = <&k3_clks 239 1>;
>> - clock-names = "fck";
>> - max-functions = /bits/ 8 <6>;
>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>> - dma-coherent;
>> - };
>> -
>> pcie1_rc: pcie@2910000 {
>> compatible = "ti,j721e-pcie-host";
>> reg = <0x00 0x02910000 0x00 0x1000>,
>> @@ -864,26 +844,6 @@ pcie1_rc: pcie@2910000 {
>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>> };
>> - pcie1_ep: pcie-ep@2910000 {
>> - compatible = "ti,j721e-pcie-ep";
>> - reg = <0x00 0x02910000 0x00 0x1000>,
>> - <0x00 0x02917000 0x00 0x400>,
>> - <0x00 0x0d800000 0x00 0x00800000>,
>> - <0x00 0x18000000 0x00 0x08000000>;
>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>> - interrupt-names = "link_state";
>> - interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
>> - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>> - max-link-speed = <3>;
>> - num-lanes = <2>;
>> - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>> - clocks = <&k3_clks 240 1>;
>> - clock-names = "fck";
>> - max-functions = /bits/ 8 <6>;
>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>> - dma-coherent;
>> - };
>> -
>> pcie2_rc: pcie@2920000 {
>> compatible = "ti,j721e-pcie-host";
>> reg = <0x00 0x02920000 0x00 0x1000>,
>> @@ -912,26 +872,6 @@ pcie2_rc: pcie@2920000 {
>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>> };
>> - pcie2_ep: pcie-ep@2920000 {
>> - compatible = "ti,j721e-pcie-ep";
>> - reg = <0x00 0x02920000 0x00 0x1000>,
>> - <0x00 0x02927000 0x00 0x400>,
>> - <0x00 0x0e000000 0x00 0x00800000>,
>> - <0x44 0x00000000 0x00 0x08000000>;
>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>> - interrupt-names = "link_state";
>> - interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
>> - ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
>> - max-link-speed = <3>;
>> - num-lanes = <2>;
>> - power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
>> - clocks = <&k3_clks 241 1>;
>> - clock-names = "fck";
>> - max-functions = /bits/ 8 <6>;
>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>> - dma-coherent;
>> - };
>> -
>> pcie3_rc: pcie@2930000 {
>> compatible = "ti,j721e-pcie-host";
>> reg = <0x00 0x02930000 0x00 0x1000>,
>> @@ -960,28 +900,6 @@ pcie3_rc: pcie@2930000 {
>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>> };
>> - pcie3_ep: pcie-ep@2930000 {
>> - compatible = "ti,j721e-pcie-ep";
>> - reg = <0x00 0x02930000 0x00 0x1000>,
>> - <0x00 0x02937000 0x00 0x400>,
>> - <0x00 0x0e800000 0x00 0x00800000>,
>> - <0x44 0x10000000 0x00 0x08000000>;
>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>> - interrupt-names = "link_state";
>> - interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
>> - ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
>> - max-link-speed = <3>;
>> - num-lanes = <2>;
>> - power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
>> - clocks = <&k3_clks 242 1>;
>> - clock-names = "fck";
>> - max-functions = /bits/ 8 <6>;
>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>> - dma-coherent;
>> - #address-cells = <2>;
>> - #size-cells = <2>;
>> - };
>> -
>> serdes_wiz4: wiz@5050000 {
>> compatible = "ti,am64-wiz-10g";
>> #address-cells = <1>;
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>> index f650a7fd66b4..07d3282a583b 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>> @@ -896,35 +896,11 @@ &pcie2_rc {
>> status = "disabled";
>> };
>> -&pcie0_ep {
>> - status = "disabled";
>> - phys = <&serdes0_pcie_link>;
>> - phy-names = "pcie-phy";
>> - num-lanes = <1>;
>> -};
>> -
>> -&pcie1_ep {
>> - status = "disabled";
>> - phys = <&serdes1_pcie_link>;
>> - phy-names = "pcie-phy";
>> - num-lanes = <2>;
>> -};
>> -
>> -&pcie2_ep {
>> - /* Unused */
>> - status = "disabled";
>> -};
>> -
>> &pcie3_rc {
>> /* Unused */
>> status = "disabled";
>> };
>> -&pcie3_ep {
>> - /* Unused */
>> - status = "disabled";
>> -};
>> -
>> &icssg0_mdio {
>> status = "disabled";
>> };
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 2/5] arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes
2023-05-16 16:27 ` Andrew Davis
@ 2023-06-05 14:54 ` Verma, Achal
2023-06-05 15:17 ` Andrew Davis
0 siblings, 1 reply; 12+ messages in thread
From: Verma, Achal @ 2023-06-05 14:54 UTC (permalink / raw)
To: Andrew Davis, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Rob Herring, Krzysztof Kozlowski, Robert Nelson
Cc: linux-arm-kernel, devicetree, linux-kernel, achal Verma
On 5/16/2023 9:57 PM, Andrew Davis wrote:
> On 5/16/23 11:22 AM, Verma, Achal wrote:
>>
>>
>> On 5/15/2023 10:51 PM, Andrew Davis wrote:
>>> These nodes are example nodes for the PCIe controller in "endpoint"
>>> mode.
>>> By default the controller is in "root complex" mode and there is
>>> already a
>>> DT node for the same.
>>>
>>> Examples should go in the bindings or other documentation.
>>>
>>> Remove this node.
>> How we will support EP from now onwards, using overlays ?
>>
>
> They are already disabled, how do you support them today?
As of now we edit the DTS (disable RC node and enable EP mode) but
now we have to delete RC node and add EP node and build DTBS which
looks like quite a work.
Regards,
Achal Verma
>
> Andrew
>
>> Regards,
>> Achal Verma
>>>
>>> Signed-off-by: Andrew Davis <afd@ti.com>
>>> ---
>>> .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 24 ------
>>> .../dts/ti/k3-j721e-common-proc-board.dts | 25 ------
>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 82 -------------------
>>> arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 24 ------
>>> 4 files changed, 155 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>> b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>> index 8a62ac263b89..d77eeff0d81d 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>> @@ -892,35 +892,11 @@ &pcie2_rc {
>>> status = "disabled";
>>> };
>>> -&pcie0_ep {
>>> - status = "disabled";
>>> - phys = <&serdes0_pcie_link>;
>>> - phy-names = "pcie-phy";
>>> - num-lanes = <1>;
>>> -};
>>> -
>>> -&pcie1_ep {
>>> - status = "disabled";
>>> - phys = <&serdes1_pcie_link>;
>>> - phy-names = "pcie-phy";
>>> - num-lanes = <2>;
>>> -};
>>> -
>>> -&pcie2_ep {
>>> - /* Unused */
>>> - status = "disabled";
>>> -};
>>> -
>>> &pcie3_rc {
>>> /* Unused */
>>> status = "disabled";
>>> };
>>> -&pcie3_ep {
>>> - /* Unused */
>>> - status = "disabled";
>>> -};
>>> -
>>> &icssg0_mdio {
>>> /* Unused */
>>> status = "disabled";
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>>> b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>>> index 7db0603125aa..87b7263f6547 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>>> @@ -840,35 +840,10 @@ &pcie2_rc {
>>> num-lanes = <2>;
>>> };
>>> -&pcie0_ep {
>>> - phys = <&serdes0_pcie_link>;
>>> - phy-names = "pcie-phy";
>>> - num-lanes = <1>;
>>> - status = "disabled";
>>> -};
>>> -
>>> -&pcie1_ep {
>>> - phys = <&serdes1_pcie_link>;
>>> - phy-names = "pcie-phy";
>>> - num-lanes = <2>;
>>> - status = "disabled";
>>> -};
>>> -
>>> -&pcie2_ep {
>>> - phys = <&serdes2_pcie_link>;
>>> - phy-names = "pcie-phy";
>>> - num-lanes = <2>;
>>> - status = "disabled";
>>> -};
>>> -
>>> &pcie3_rc {
>>> status = "disabled";
>>> };
>>> -&pcie3_ep {
>>> - status = "disabled";
>>> -};
>>> -
>>> &icssg0_mdio {
>>> status = "disabled";
>>> };
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> index 10c8a5fb4ee2..e39f6d1e8d40 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> @@ -816,26 +816,6 @@ pcie0_rc: pcie@2900000 {
>>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>>> };
>>> - pcie0_ep: pcie-ep@2900000 {
>>> - compatible = "ti,j721e-pcie-ep";
>>> - reg = <0x00 0x02900000 0x00 0x1000>,
>>> - <0x00 0x02907000 0x00 0x400>,
>>> - <0x00 0x0d000000 0x00 0x00800000>,
>>> - <0x00 0x10000000 0x00 0x08000000>;
>>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>>> - interrupt-names = "link_state";
>>> - interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
>>> - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
>>> - max-link-speed = <3>;
>>> - num-lanes = <2>;
>>> - power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
>>> - clocks = <&k3_clks 239 1>;
>>> - clock-names = "fck";
>>> - max-functions = /bits/ 8 <6>;
>>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>>> - dma-coherent;
>>> - };
>>> -
>>> pcie1_rc: pcie@2910000 {
>>> compatible = "ti,j721e-pcie-host";
>>> reg = <0x00 0x02910000 0x00 0x1000>,
>>> @@ -864,26 +844,6 @@ pcie1_rc: pcie@2910000 {
>>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>>> };
>>> - pcie1_ep: pcie-ep@2910000 {
>>> - compatible = "ti,j721e-pcie-ep";
>>> - reg = <0x00 0x02910000 0x00 0x1000>,
>>> - <0x00 0x02917000 0x00 0x400>,
>>> - <0x00 0x0d800000 0x00 0x00800000>,
>>> - <0x00 0x18000000 0x00 0x08000000>;
>>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>>> - interrupt-names = "link_state";
>>> - interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
>>> - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>>> - max-link-speed = <3>;
>>> - num-lanes = <2>;
>>> - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>>> - clocks = <&k3_clks 240 1>;
>>> - clock-names = "fck";
>>> - max-functions = /bits/ 8 <6>;
>>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>>> - dma-coherent;
>>> - };
>>> -
>>> pcie2_rc: pcie@2920000 {
>>> compatible = "ti,j721e-pcie-host";
>>> reg = <0x00 0x02920000 0x00 0x1000>,
>>> @@ -912,26 +872,6 @@ pcie2_rc: pcie@2920000 {
>>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>>> };
>>> - pcie2_ep: pcie-ep@2920000 {
>>> - compatible = "ti,j721e-pcie-ep";
>>> - reg = <0x00 0x02920000 0x00 0x1000>,
>>> - <0x00 0x02927000 0x00 0x400>,
>>> - <0x00 0x0e000000 0x00 0x00800000>,
>>> - <0x44 0x00000000 0x00 0x08000000>;
>>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>>> - interrupt-names = "link_state";
>>> - interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
>>> - ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
>>> - max-link-speed = <3>;
>>> - num-lanes = <2>;
>>> - power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
>>> - clocks = <&k3_clks 241 1>;
>>> - clock-names = "fck";
>>> - max-functions = /bits/ 8 <6>;
>>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>>> - dma-coherent;
>>> - };
>>> -
>>> pcie3_rc: pcie@2930000 {
>>> compatible = "ti,j721e-pcie-host";
>>> reg = <0x00 0x02930000 0x00 0x1000>,
>>> @@ -960,28 +900,6 @@ pcie3_rc: pcie@2930000 {
>>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>>> };
>>> - pcie3_ep: pcie-ep@2930000 {
>>> - compatible = "ti,j721e-pcie-ep";
>>> - reg = <0x00 0x02930000 0x00 0x1000>,
>>> - <0x00 0x02937000 0x00 0x400>,
>>> - <0x00 0x0e800000 0x00 0x00800000>,
>>> - <0x44 0x10000000 0x00 0x08000000>;
>>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>>> - interrupt-names = "link_state";
>>> - interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
>>> - ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
>>> - max-link-speed = <3>;
>>> - num-lanes = <2>;
>>> - power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
>>> - clocks = <&k3_clks 242 1>;
>>> - clock-names = "fck";
>>> - max-functions = /bits/ 8 <6>;
>>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>>> - dma-coherent;
>>> - #address-cells = <2>;
>>> - #size-cells = <2>;
>>> - };
>>> -
>>> serdes_wiz4: wiz@5050000 {
>>> compatible = "ti,am64-wiz-10g";
>>> #address-cells = <1>;
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>>> b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>>> index f650a7fd66b4..07d3282a583b 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>>> @@ -896,35 +896,11 @@ &pcie2_rc {
>>> status = "disabled";
>>> };
>>> -&pcie0_ep {
>>> - status = "disabled";
>>> - phys = <&serdes0_pcie_link>;
>>> - phy-names = "pcie-phy";
>>> - num-lanes = <1>;
>>> -};
>>> -
>>> -&pcie1_ep {
>>> - status = "disabled";
>>> - phys = <&serdes1_pcie_link>;
>>> - phy-names = "pcie-phy";
>>> - num-lanes = <2>;
>>> -};
>>> -
>>> -&pcie2_ep {
>>> - /* Unused */
>>> - status = "disabled";
>>> -};
>>> -
>>> &pcie3_rc {
>>> /* Unused */
>>> status = "disabled";
>>> };
>>> -&pcie3_ep {
>>> - /* Unused */
>>> - status = "disabled";
>>> -};
>>> -
>>> &icssg0_mdio {
>>> status = "disabled";
>>> };
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 2/5] arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes
2023-06-05 14:54 ` Verma, Achal
@ 2023-06-05 15:17 ` Andrew Davis
2023-06-05 16:06 ` Verma, Achal
0 siblings, 1 reply; 12+ messages in thread
From: Andrew Davis @ 2023-06-05 15:17 UTC (permalink / raw)
To: Verma, Achal, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Rob Herring, Krzysztof Kozlowski, Robert Nelson
Cc: linux-arm-kernel, devicetree, linux-kernel
On 6/5/23 9:54 AM, Verma, Achal wrote:
>
>
> On 5/16/2023 9:57 PM, Andrew Davis wrote:
>> On 5/16/23 11:22 AM, Verma, Achal wrote:
>>>
>>>
>>> On 5/15/2023 10:51 PM, Andrew Davis wrote:
>>>> These nodes are example nodes for the PCIe controller in "endpoint" mode.
>>>> By default the controller is in "root complex" mode and there is already a
>>>> DT node for the same.
>>>>
>>>> Examples should go in the bindings or other documentation.
>>>>
>>>> Remove this node.
>>> How we will support EP from now onwards, using overlays ?
>>>
>>
>> They are already disabled, how do you support them today?
> As of now we edit the DTS (disable RC node and enable EP mode) but
> now we have to delete RC node and add EP node and build DTBS which
> looks like quite a work.
>
I'd argue having to use a different node with a different compatible
to switch PCIe modes was not correct to begin with, it should have
been a property flag. Or even better, the modes should have been
switchable without modifying DTB at all.
Since it was chosen to put hardware configuration in DT, you'll have
to live with the problems that causes. My point it the same, examples
of how to do something do not belong in the DT files. Put the example
nodes in the documentation somewhere, then you can copy paste from that.
Andrew
> Regards,
> Achal Verma
>
>>
>> Andrew
>>
>>> Regards,
>>> Achal Verma
>>>>
>>>> Signed-off-by: Andrew Davis <afd@ti.com>
>>>> ---
>>>> .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 24 ------
>>>> .../dts/ti/k3-j721e-common-proc-board.dts | 25 ------
>>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 82 -------------------
>>>> arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 24 ------
>>>> 4 files changed, 155 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>>> index 8a62ac263b89..d77eeff0d81d 100644
>>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>>> @@ -892,35 +892,11 @@ &pcie2_rc {
>>>> status = "disabled";
>>>> };
>>>> -&pcie0_ep {
>>>> - status = "disabled";
>>>> - phys = <&serdes0_pcie_link>;
>>>> - phy-names = "pcie-phy";
>>>> - num-lanes = <1>;
>>>> -};
>>>> -
>>>> -&pcie1_ep {
>>>> - status = "disabled";
>>>> - phys = <&serdes1_pcie_link>;
>>>> - phy-names = "pcie-phy";
>>>> - num-lanes = <2>;
>>>> -};
>>>> -
>>>> -&pcie2_ep {
>>>> - /* Unused */
>>>> - status = "disabled";
>>>> -};
>>>> -
>>>> &pcie3_rc {
>>>> /* Unused */
>>>> status = "disabled";
>>>> };
>>>> -&pcie3_ep {
>>>> - /* Unused */
>>>> - status = "disabled";
>>>> -};
>>>> -
>>>> &icssg0_mdio {
>>>> /* Unused */
>>>> status = "disabled";
>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>>>> index 7db0603125aa..87b7263f6547 100644
>>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>>>> @@ -840,35 +840,10 @@ &pcie2_rc {
>>>> num-lanes = <2>;
>>>> };
>>>> -&pcie0_ep {
>>>> - phys = <&serdes0_pcie_link>;
>>>> - phy-names = "pcie-phy";
>>>> - num-lanes = <1>;
>>>> - status = "disabled";
>>>> -};
>>>> -
>>>> -&pcie1_ep {
>>>> - phys = <&serdes1_pcie_link>;
>>>> - phy-names = "pcie-phy";
>>>> - num-lanes = <2>;
>>>> - status = "disabled";
>>>> -};
>>>> -
>>>> -&pcie2_ep {
>>>> - phys = <&serdes2_pcie_link>;
>>>> - phy-names = "pcie-phy";
>>>> - num-lanes = <2>;
>>>> - status = "disabled";
>>>> -};
>>>> -
>>>> &pcie3_rc {
>>>> status = "disabled";
>>>> };
>>>> -&pcie3_ep {
>>>> - status = "disabled";
>>>> -};
>>>> -
>>>> &icssg0_mdio {
>>>> status = "disabled";
>>>> };
>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>> index 10c8a5fb4ee2..e39f6d1e8d40 100644
>>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>> @@ -816,26 +816,6 @@ pcie0_rc: pcie@2900000 {
>>>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>>>> };
>>>> - pcie0_ep: pcie-ep@2900000 {
>>>> - compatible = "ti,j721e-pcie-ep";
>>>> - reg = <0x00 0x02900000 0x00 0x1000>,
>>>> - <0x00 0x02907000 0x00 0x400>,
>>>> - <0x00 0x0d000000 0x00 0x00800000>,
>>>> - <0x00 0x10000000 0x00 0x08000000>;
>>>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>>>> - interrupt-names = "link_state";
>>>> - interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
>>>> - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
>>>> - max-link-speed = <3>;
>>>> - num-lanes = <2>;
>>>> - power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
>>>> - clocks = <&k3_clks 239 1>;
>>>> - clock-names = "fck";
>>>> - max-functions = /bits/ 8 <6>;
>>>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>>>> - dma-coherent;
>>>> - };
>>>> -
>>>> pcie1_rc: pcie@2910000 {
>>>> compatible = "ti,j721e-pcie-host";
>>>> reg = <0x00 0x02910000 0x00 0x1000>,
>>>> @@ -864,26 +844,6 @@ pcie1_rc: pcie@2910000 {
>>>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>>>> };
>>>> - pcie1_ep: pcie-ep@2910000 {
>>>> - compatible = "ti,j721e-pcie-ep";
>>>> - reg = <0x00 0x02910000 0x00 0x1000>,
>>>> - <0x00 0x02917000 0x00 0x400>,
>>>> - <0x00 0x0d800000 0x00 0x00800000>,
>>>> - <0x00 0x18000000 0x00 0x08000000>;
>>>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>>>> - interrupt-names = "link_state";
>>>> - interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
>>>> - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>>>> - max-link-speed = <3>;
>>>> - num-lanes = <2>;
>>>> - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>>>> - clocks = <&k3_clks 240 1>;
>>>> - clock-names = "fck";
>>>> - max-functions = /bits/ 8 <6>;
>>>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>>>> - dma-coherent;
>>>> - };
>>>> -
>>>> pcie2_rc: pcie@2920000 {
>>>> compatible = "ti,j721e-pcie-host";
>>>> reg = <0x00 0x02920000 0x00 0x1000>,
>>>> @@ -912,26 +872,6 @@ pcie2_rc: pcie@2920000 {
>>>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>>>> };
>>>> - pcie2_ep: pcie-ep@2920000 {
>>>> - compatible = "ti,j721e-pcie-ep";
>>>> - reg = <0x00 0x02920000 0x00 0x1000>,
>>>> - <0x00 0x02927000 0x00 0x400>,
>>>> - <0x00 0x0e000000 0x00 0x00800000>,
>>>> - <0x44 0x00000000 0x00 0x08000000>;
>>>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>>>> - interrupt-names = "link_state";
>>>> - interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
>>>> - ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
>>>> - max-link-speed = <3>;
>>>> - num-lanes = <2>;
>>>> - power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
>>>> - clocks = <&k3_clks 241 1>;
>>>> - clock-names = "fck";
>>>> - max-functions = /bits/ 8 <6>;
>>>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>>>> - dma-coherent;
>>>> - };
>>>> -
>>>> pcie3_rc: pcie@2930000 {
>>>> compatible = "ti,j721e-pcie-host";
>>>> reg = <0x00 0x02930000 0x00 0x1000>,
>>>> @@ -960,28 +900,6 @@ pcie3_rc: pcie@2930000 {
>>>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>>>> };
>>>> - pcie3_ep: pcie-ep@2930000 {
>>>> - compatible = "ti,j721e-pcie-ep";
>>>> - reg = <0x00 0x02930000 0x00 0x1000>,
>>>> - <0x00 0x02937000 0x00 0x400>,
>>>> - <0x00 0x0e800000 0x00 0x00800000>,
>>>> - <0x44 0x10000000 0x00 0x08000000>;
>>>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>>>> - interrupt-names = "link_state";
>>>> - interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
>>>> - ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
>>>> - max-link-speed = <3>;
>>>> - num-lanes = <2>;
>>>> - power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
>>>> - clocks = <&k3_clks 242 1>;
>>>> - clock-names = "fck";
>>>> - max-functions = /bits/ 8 <6>;
>>>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>>>> - dma-coherent;
>>>> - #address-cells = <2>;
>>>> - #size-cells = <2>;
>>>> - };
>>>> -
>>>> serdes_wiz4: wiz@5050000 {
>>>> compatible = "ti,am64-wiz-10g";
>>>> #address-cells = <1>;
>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>>>> index f650a7fd66b4..07d3282a583b 100644
>>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>>>> @@ -896,35 +896,11 @@ &pcie2_rc {
>>>> status = "disabled";
>>>> };
>>>> -&pcie0_ep {
>>>> - status = "disabled";
>>>> - phys = <&serdes0_pcie_link>;
>>>> - phy-names = "pcie-phy";
>>>> - num-lanes = <1>;
>>>> -};
>>>> -
>>>> -&pcie1_ep {
>>>> - status = "disabled";
>>>> - phys = <&serdes1_pcie_link>;
>>>> - phy-names = "pcie-phy";
>>>> - num-lanes = <2>;
>>>> -};
>>>> -
>>>> -&pcie2_ep {
>>>> - /* Unused */
>>>> - status = "disabled";
>>>> -};
>>>> -
>>>> &pcie3_rc {
>>>> /* Unused */
>>>> status = "disabled";
>>>> };
>>>> -&pcie3_ep {
>>>> - /* Unused */
>>>> - status = "disabled";
>>>> -};
>>>> -
>>>> &icssg0_mdio {
>>>> status = "disabled";
>>>> };
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 2/5] arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes
2023-06-05 15:17 ` Andrew Davis
@ 2023-06-05 16:06 ` Verma, Achal
0 siblings, 0 replies; 12+ messages in thread
From: Verma, Achal @ 2023-06-05 16:06 UTC (permalink / raw)
To: Andrew Davis, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Rob Herring, Krzysztof Kozlowski, Robert Nelson
Cc: linux-arm-kernel, devicetree, linux-kernel
On 6/5/2023 8:47 PM, Andrew Davis wrote:
> On 6/5/23 9:54 AM, Verma, Achal wrote:
>>
>>
>> On 5/16/2023 9:57 PM, Andrew Davis wrote:
>>> On 5/16/23 11:22 AM, Verma, Achal wrote:
>>>>
>>>>
>>>> On 5/15/2023 10:51 PM, Andrew Davis wrote:
>>>>> These nodes are example nodes for the PCIe controller in "endpoint"
>>>>> mode.
>>>>> By default the controller is in "root complex" mode and there is
>>>>> already a
>>>>> DT node for the same.
>>>>>
>>>>> Examples should go in the bindings or other documentation.
>>>>>
>>>>> Remove this node.
>>>> How we will support EP from now onwards, using overlays ?
>>>>
>>>
>>> They are already disabled, how do you support them today?
>> As of now we edit the DTS (disable RC node and enable EP mode) but
>> now we have to delete RC node and add EP node and build DTBS which
>> looks like quite a work.
>>
>
> I'd argue having to use a different node with a different compatible
> to switch PCIe modes was not correct to begin with, it should have
> been a property flag. Or even better, the modes should have been
> switchable without modifying DTB at all.
>
> Since it was chosen to put hardware configuration in DT, you'll have
> to live with the problems that causes. My point it the same, examples
> of how to do something do not belong in the DT files. Put the example
> nodes in the documentation somewhere, then you can copy paste from that.
>
ok agree.
Later, have to device someway to make it quicker.
Thanks,
Achal Verma
> Andrew
>
>> Regards,
>> Achal Verma
>>
>>>
>>> Andrew
>>>
>>>> Regards,
>>>> Achal Verma
>>>>>
>>>>> Signed-off-by: Andrew Davis <afd@ti.com>
>>>>> ---
>>>>> .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 24 ------
>>>>> .../dts/ti/k3-j721e-common-proc-board.dts | 25 ------
>>>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 82
>>>>> -------------------
>>>>> arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 24 ------
>>>>> 4 files changed, 155 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>>>> b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>>>> index 8a62ac263b89..d77eeff0d81d 100644
>>>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>>>> @@ -892,35 +892,11 @@ &pcie2_rc {
>>>>> status = "disabled";
>>>>> };
>>>>> -&pcie0_ep {
>>>>> - status = "disabled";
>>>>> - phys = <&serdes0_pcie_link>;
>>>>> - phy-names = "pcie-phy";
>>>>> - num-lanes = <1>;
>>>>> -};
>>>>> -
>>>>> -&pcie1_ep {
>>>>> - status = "disabled";
>>>>> - phys = <&serdes1_pcie_link>;
>>>>> - phy-names = "pcie-phy";
>>>>> - num-lanes = <2>;
>>>>> -};
>>>>> -
>>>>> -&pcie2_ep {
>>>>> - /* Unused */
>>>>> - status = "disabled";
>>>>> -};
>>>>> -
>>>>> &pcie3_rc {
>>>>> /* Unused */
>>>>> status = "disabled";
>>>>> };
>>>>> -&pcie3_ep {
>>>>> - /* Unused */
>>>>> - status = "disabled";
>>>>> -};
>>>>> -
>>>>> &icssg0_mdio {
>>>>> /* Unused */
>>>>> status = "disabled";
>>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>>>>> b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>>>>> index 7db0603125aa..87b7263f6547 100644
>>>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>>>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>>>>> @@ -840,35 +840,10 @@ &pcie2_rc {
>>>>> num-lanes = <2>;
>>>>> };
>>>>> -&pcie0_ep {
>>>>> - phys = <&serdes0_pcie_link>;
>>>>> - phy-names = "pcie-phy";
>>>>> - num-lanes = <1>;
>>>>> - status = "disabled";
>>>>> -};
>>>>> -
>>>>> -&pcie1_ep {
>>>>> - phys = <&serdes1_pcie_link>;
>>>>> - phy-names = "pcie-phy";
>>>>> - num-lanes = <2>;
>>>>> - status = "disabled";
>>>>> -};
>>>>> -
>>>>> -&pcie2_ep {
>>>>> - phys = <&serdes2_pcie_link>;
>>>>> - phy-names = "pcie-phy";
>>>>> - num-lanes = <2>;
>>>>> - status = "disabled";
>>>>> -};
>>>>> -
>>>>> &pcie3_rc {
>>>>> status = "disabled";
>>>>> };
>>>>> -&pcie3_ep {
>>>>> - status = "disabled";
>>>>> -};
>>>>> -
>>>>> &icssg0_mdio {
>>>>> status = "disabled";
>>>>> };
>>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>>> b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>>> index 10c8a5fb4ee2..e39f6d1e8d40 100644
>>>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>>> @@ -816,26 +816,6 @@ pcie0_rc: pcie@2900000 {
>>>>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>>>>> };
>>>>> - pcie0_ep: pcie-ep@2900000 {
>>>>> - compatible = "ti,j721e-pcie-ep";
>>>>> - reg = <0x00 0x02900000 0x00 0x1000>,
>>>>> - <0x00 0x02907000 0x00 0x400>,
>>>>> - <0x00 0x0d000000 0x00 0x00800000>,
>>>>> - <0x00 0x10000000 0x00 0x08000000>;
>>>>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>>>>> - interrupt-names = "link_state";
>>>>> - interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
>>>>> - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
>>>>> - max-link-speed = <3>;
>>>>> - num-lanes = <2>;
>>>>> - power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
>>>>> - clocks = <&k3_clks 239 1>;
>>>>> - clock-names = "fck";
>>>>> - max-functions = /bits/ 8 <6>;
>>>>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>>>>> - dma-coherent;
>>>>> - };
>>>>> -
>>>>> pcie1_rc: pcie@2910000 {
>>>>> compatible = "ti,j721e-pcie-host";
>>>>> reg = <0x00 0x02910000 0x00 0x1000>,
>>>>> @@ -864,26 +844,6 @@ pcie1_rc: pcie@2910000 {
>>>>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>>>>> };
>>>>> - pcie1_ep: pcie-ep@2910000 {
>>>>> - compatible = "ti,j721e-pcie-ep";
>>>>> - reg = <0x00 0x02910000 0x00 0x1000>,
>>>>> - <0x00 0x02917000 0x00 0x400>,
>>>>> - <0x00 0x0d800000 0x00 0x00800000>,
>>>>> - <0x00 0x18000000 0x00 0x08000000>;
>>>>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>>>>> - interrupt-names = "link_state";
>>>>> - interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
>>>>> - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>>>>> - max-link-speed = <3>;
>>>>> - num-lanes = <2>;
>>>>> - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>>>>> - clocks = <&k3_clks 240 1>;
>>>>> - clock-names = "fck";
>>>>> - max-functions = /bits/ 8 <6>;
>>>>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>>>>> - dma-coherent;
>>>>> - };
>>>>> -
>>>>> pcie2_rc: pcie@2920000 {
>>>>> compatible = "ti,j721e-pcie-host";
>>>>> reg = <0x00 0x02920000 0x00 0x1000>,
>>>>> @@ -912,26 +872,6 @@ pcie2_rc: pcie@2920000 {
>>>>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>>>>> };
>>>>> - pcie2_ep: pcie-ep@2920000 {
>>>>> - compatible = "ti,j721e-pcie-ep";
>>>>> - reg = <0x00 0x02920000 0x00 0x1000>,
>>>>> - <0x00 0x02927000 0x00 0x400>,
>>>>> - <0x00 0x0e000000 0x00 0x00800000>,
>>>>> - <0x44 0x00000000 0x00 0x08000000>;
>>>>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>>>>> - interrupt-names = "link_state";
>>>>> - interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
>>>>> - ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
>>>>> - max-link-speed = <3>;
>>>>> - num-lanes = <2>;
>>>>> - power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
>>>>> - clocks = <&k3_clks 241 1>;
>>>>> - clock-names = "fck";
>>>>> - max-functions = /bits/ 8 <6>;
>>>>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>>>>> - dma-coherent;
>>>>> - };
>>>>> -
>>>>> pcie3_rc: pcie@2930000 {
>>>>> compatible = "ti,j721e-pcie-host";
>>>>> reg = <0x00 0x02930000 0x00 0x1000>,
>>>>> @@ -960,28 +900,6 @@ pcie3_rc: pcie@2930000 {
>>>>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>>>>> };
>>>>> - pcie3_ep: pcie-ep@2930000 {
>>>>> - compatible = "ti,j721e-pcie-ep";
>>>>> - reg = <0x00 0x02930000 0x00 0x1000>,
>>>>> - <0x00 0x02937000 0x00 0x400>,
>>>>> - <0x00 0x0e800000 0x00 0x00800000>,
>>>>> - <0x44 0x10000000 0x00 0x08000000>;
>>>>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>>>>> - interrupt-names = "link_state";
>>>>> - interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
>>>>> - ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
>>>>> - max-link-speed = <3>;
>>>>> - num-lanes = <2>;
>>>>> - power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
>>>>> - clocks = <&k3_clks 242 1>;
>>>>> - clock-names = "fck";
>>>>> - max-functions = /bits/ 8 <6>;
>>>>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>>>>> - dma-coherent;
>>>>> - #address-cells = <2>;
>>>>> - #size-cells = <2>;
>>>>> - };
>>>>> -
>>>>> serdes_wiz4: wiz@5050000 {
>>>>> compatible = "ti,am64-wiz-10g";
>>>>> #address-cells = <1>;
>>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>>>>> b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>>>>> index f650a7fd66b4..07d3282a583b 100644
>>>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>>>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>>>>> @@ -896,35 +896,11 @@ &pcie2_rc {
>>>>> status = "disabled";
>>>>> };
>>>>> -&pcie0_ep {
>>>>> - status = "disabled";
>>>>> - phys = <&serdes0_pcie_link>;
>>>>> - phy-names = "pcie-phy";
>>>>> - num-lanes = <1>;
>>>>> -};
>>>>> -
>>>>> -&pcie1_ep {
>>>>> - status = "disabled";
>>>>> - phys = <&serdes1_pcie_link>;
>>>>> - phy-names = "pcie-phy";
>>>>> - num-lanes = <2>;
>>>>> -};
>>>>> -
>>>>> -&pcie2_ep {
>>>>> - /* Unused */
>>>>> - status = "disabled";
>>>>> -};
>>>>> -
>>>>> &pcie3_rc {
>>>>> /* Unused */
>>>>> status = "disabled";
>>>>> };
>>>>> -&pcie3_ep {
>>>>> - /* Unused */
>>>>> - status = "disabled";
>>>>> -};
>>>>> -
>>>>> &icssg0_mdio {
>>>>> status = "disabled";
>>>>> };
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/5] arm64: dts: ti: k3-j721e: Enable PCIe nodes at the board level
2023-05-15 17:21 [PATCH 1/5] arm64: dts: ti: k3-j721e-beagleboneai64: Fix mailbox node status Andrew Davis
2023-05-15 17:21 ` [PATCH 2/5] arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes Andrew Davis
@ 2023-05-15 17:21 ` Andrew Davis
2023-05-15 17:21 ` [PATCH 4/5] arm64: dts: ti: k3-am64: Enable Mailbox " Andrew Davis
` (3 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Andrew Davis @ 2023-05-15 17:21 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Robert Nelson
Cc: linux-arm-kernel, devicetree, linux-kernel, Andrew Davis
PCIe nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended with a SerDes PHY.
And usually only one of the two modes can be used at a time as they
share a SerDes link.
As the PHY and mode is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the PCIe nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
---
.../boot/dts/ti/k3-j721e-beagleboneai64.dts | 16 +---------------
.../boot/dts/ti/k3-j721e-common-proc-board.dts | 7 +++----
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 4 ++++
arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 12 ++----------
4 files changed, 10 insertions(+), 29 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
index d77eeff0d81d..be0c5431119e 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
@@ -872,12 +872,8 @@ serdes1_pcie_link: phy@0 {
};
};
-&pcie0_rc {
- /* Unused */
- status = "disabled";
-};
-
&pcie1_rc {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pcie1_rst_pins_default>;
phys = <&serdes1_pcie_link>;
@@ -887,16 +883,6 @@ &pcie1_rc {
reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>;
};
-&pcie2_rc {
- /* Unused */
- status = "disabled";
-};
-
-&pcie3_rc {
- /* Unused */
- status = "disabled";
-};
-
&icssg0_mdio {
/* Unused */
status = "disabled";
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 87b7263f6547..975a5161eb96 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -820,6 +820,7 @@ &mhdp {
};
&pcie0_rc {
+ status = "okay";
reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
@@ -827,6 +828,7 @@ &pcie0_rc {
};
&pcie1_rc {
+ status = "okay";
reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
phys = <&serdes1_pcie_link>;
phy-names = "pcie-phy";
@@ -834,16 +836,13 @@ &pcie1_rc {
};
&pcie2_rc {
+ status = "okay";
reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
phys = <&serdes2_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
};
-&pcie3_rc {
- status = "disabled";
-};
-
&icssg0_mdio {
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index e39f6d1e8d40..18f4661d37bf 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -814,6 +814,7 @@ pcie0_rc: pcie@2900000 {
ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
<0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
};
pcie1_rc: pcie@2910000 {
@@ -842,6 +843,7 @@ pcie1_rc: pcie@2910000 {
ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
<0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
};
pcie2_rc: pcie@2920000 {
@@ -870,6 +872,7 @@ pcie2_rc: pcie@2920000 {
ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
<0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
};
pcie3_rc: pcie@2930000 {
@@ -898,6 +901,7 @@ pcie3_rc: pcie@2930000 {
ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
<0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
};
serdes_wiz4: wiz@5050000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index 07d3282a583b..66a8559b3755 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -872,6 +872,7 @@ serdes1_pcie_link: phy@0 {
};
&pcie0_rc {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ekey_reset_pins_default>;
reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>;
@@ -882,6 +883,7 @@ &pcie0_rc {
};
&pcie1_rc {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mkey_reset_pins_default>;
reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>;
@@ -891,16 +893,6 @@ &pcie1_rc {
num-lanes = <2>;
};
-&pcie2_rc {
- /* Unused */
- status = "disabled";
-};
-
-&pcie3_rc {
- /* Unused */
- status = "disabled";
-};
-
&icssg0_mdio {
status = "disabled";
};
--
2.39.2
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 4/5] arm64: dts: ti: k3-am64: Enable Mailbox nodes at the board level
2023-05-15 17:21 [PATCH 1/5] arm64: dts: ti: k3-j721e-beagleboneai64: Fix mailbox node status Andrew Davis
2023-05-15 17:21 ` [PATCH 2/5] arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes Andrew Davis
2023-05-15 17:21 ` [PATCH 3/5] arm64: dts: ti: k3-j721e: Enable PCIe nodes at the board level Andrew Davis
@ 2023-05-15 17:21 ` Andrew Davis
2023-05-15 17:21 ` [PATCH 5/5] arm64: dts: ti: k3-j721e: Enable MDIO " Andrew Davis
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Andrew Davis @ 2023-05-15 17:21 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Robert Nelson
Cc: linux-arm-kernel, devicetree, linux-kernel, Andrew Davis
Mailbox nodes defined in the top-level AM64x SoC dtsi files are incomplete
and may not be functional unless they are extended with a chosen interrupt
and connection to a remote processor.
As the remote processors depend on memory nodes which are only known at
the board integration level, these nodes should only be enabled when
provided with the above information.
Disable the Mailbox nodes in the dtsi files and only enable the ones that
are actually used on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 6 +++++
.../boot/dts/ti/k3-am64-phycore-som.dtsi | 24 -------------------
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 18 +++++---------
arch/arm64/boot/dts/ti/k3-am642-sk.dts | 18 +++++---------
4 files changed, 18 insertions(+), 48 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 5e8036f32d79..a474232fba0e 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -676,6 +676,7 @@ mailbox0_cluster2: mailbox@29020000 {
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster3: mailbox@29030000 {
@@ -686,6 +687,7 @@ mailbox0_cluster3: mailbox@29030000 {
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster4: mailbox@29040000 {
@@ -696,6 +698,7 @@ mailbox0_cluster4: mailbox@29040000 {
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster5: mailbox@29050000 {
@@ -706,6 +709,7 @@ mailbox0_cluster5: mailbox@29050000 {
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster6: mailbox@29060000 {
@@ -715,6 +719,7 @@ mailbox0_cluster6: mailbox@29060000 {
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster7: mailbox@29070000 {
@@ -724,6 +729,7 @@ mailbox0_cluster7: mailbox@29070000 {
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
main_r5fss0: r5fss@78000000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
index 8dfb6301b17d..7c2e26ef726c 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
@@ -160,30 +160,6 @@ &cpsw_port2 {
status = "disabled";
};
-&mailbox0_cluster2 {
- status = "disabled";
-};
-
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
-&mailbox0_cluster4 {
- status = "disabled";
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 39feea78a084..a8f5be51de8f 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -475,6 +475,8 @@ flash@0 {
};
&mailbox0_cluster2 {
+ status = "okay";
+
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@@ -486,11 +488,9 @@ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
};
};
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
&mailbox0_cluster4 {
+ status = "okay";
+
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@@ -502,21 +502,15 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
};
};
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
&mailbox0_cluster6 {
+ status = "okay";
+
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 2e2d40da360a..97414898c5c0 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -494,6 +494,8 @@ flash@0 {
};
&mailbox0_cluster2 {
+ status = "okay";
+
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@@ -505,11 +507,9 @@ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
};
};
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
&mailbox0_cluster4 {
+ status = "okay";
+
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@@ -521,21 +521,15 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
};
};
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
&mailbox0_cluster6 {
+ status = "okay";
+
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
--
2.39.2
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 5/5] arm64: dts: ti: k3-j721e: Enable MDIO nodes at the board level
2023-05-15 17:21 [PATCH 1/5] arm64: dts: ti: k3-j721e-beagleboneai64: Fix mailbox node status Andrew Davis
` (2 preceding siblings ...)
2023-05-15 17:21 ` [PATCH 4/5] arm64: dts: ti: k3-am64: Enable Mailbox " Andrew Davis
@ 2023-05-15 17:21 ` Andrew Davis
2023-05-16 13:51 ` [PATCH 1/5] arm64: dts: ti: k3-j721e-beagleboneai64: Fix mailbox node status Nishanth Menon
2023-06-15 10:30 ` Vignesh Raghavendra
5 siblings, 0 replies; 12+ messages in thread
From: Andrew Davis @ 2023-05-15 17:21 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Robert Nelson
Cc: linux-arm-kernel, devicetree, linux-kernel, Andrew Davis
MDIO nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended with a pinmux.
As the attached PHY is only known about at the board integration level,
these nodes should only be enabled when provided with this information.
Disable the MDIO nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 10 ----------
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 --------
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 8 --------
4 files changed, 2 insertions(+), 26 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
index be0c5431119e..a7b686cab3e6 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
@@ -883,16 +883,6 @@ &pcie1_rc {
reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>;
};
-&icssg0_mdio {
- /* Unused */
- status = "disabled";
-};
-
-&icssg1_mdio {
- /* Unused */
- status = "disabled";
-};
-
&ufs_wrapper {
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 975a5161eb96..68afc3cedfd8 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -843,14 +843,6 @@ &pcie2_rc {
num-lanes = <2>;
};
-&icssg0_mdio {
- status = "disabled";
-};
-
-&icssg1_mdio {
- status = "disabled";
-};
-
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 18f4661d37bf..65d087cf8cd9 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -2013,6 +2013,7 @@ icssg0_mdio: mdio@32400 {
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
@@ -2154,6 +2155,7 @@ icssg1_mdio: mdio@32400 {
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index 66a8559b3755..94bf5057f363 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -893,14 +893,6 @@ &pcie1_rc {
num-lanes = <2>;
};
-&icssg0_mdio {
- status = "disabled";
-};
-
-&icssg1_mdio {
- status = "disabled";
-};
-
&ufs_wrapper {
status = "disabled";
};
--
2.39.2
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/5] arm64: dts: ti: k3-j721e-beagleboneai64: Fix mailbox node status
2023-05-15 17:21 [PATCH 1/5] arm64: dts: ti: k3-j721e-beagleboneai64: Fix mailbox node status Andrew Davis
` (3 preceding siblings ...)
2023-05-15 17:21 ` [PATCH 5/5] arm64: dts: ti: k3-j721e: Enable MDIO " Andrew Davis
@ 2023-05-16 13:51 ` Nishanth Menon
2023-06-15 10:30 ` Vignesh Raghavendra
5 siblings, 0 replies; 12+ messages in thread
From: Nishanth Menon @ 2023-05-16 13:51 UTC (permalink / raw)
To: Andrew Davis
Cc: Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Robert Nelson, linux-arm-kernel, devicetree,
linux-kernel
On 12:21-20230515, Andrew Davis wrote:
> Mailbox nodes are now disabled by default. The BeagleBoard AI64 DT
> addition went in at around the same time and must have missed that
> change so the mailboxes are not re-enabled. Do that here.
Uggh. thanks.
>
> Fixes: fae14a1cb8dd ("arm64: dts: ti: Add k3-j721e-beagleboneai64")
> Signed-off-by: Andrew Davis <afd@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> index 37c24b077b6a..8a62ac263b89 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> @@ -936,6 +936,7 @@ &ufs_wrapper {
> };
>
> &mailbox0_cluster0 {
> + status = "okay";
> interrupts = <436>;
>
> mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
> @@ -950,6 +951,7 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
> };
>
> &mailbox0_cluster1 {
> + status = "okay";
> interrupts = <432>;
>
> mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
> @@ -964,6 +966,7 @@ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
> };
>
> &mailbox0_cluster2 {
> + status = "okay";
> interrupts = <428>;
>
> mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
> @@ -978,6 +981,7 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
> };
>
> &mailbox0_cluster3 {
> + status = "okay";
> interrupts = <424>;
>
> mbox_c66_0: mbox-c66-0 {
> @@ -992,6 +996,7 @@ mbox_c66_1: mbox-c66-1 {
> };
>
> &mailbox0_cluster4 {
> + status = "okay";
> interrupts = <420>;
>
> mbox_c71_0: mbox-c71-0 {
> --
> 2.39.2
>
Reviewed-by: Nishanth Menon <nm@ti.com>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/5] arm64: dts: ti: k3-j721e-beagleboneai64: Fix mailbox node status
2023-05-15 17:21 [PATCH 1/5] arm64: dts: ti: k3-j721e-beagleboneai64: Fix mailbox node status Andrew Davis
` (4 preceding siblings ...)
2023-05-16 13:51 ` [PATCH 1/5] arm64: dts: ti: k3-j721e-beagleboneai64: Fix mailbox node status Nishanth Menon
@ 2023-06-15 10:30 ` Vignesh Raghavendra
5 siblings, 0 replies; 12+ messages in thread
From: Vignesh Raghavendra @ 2023-06-15 10:30 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Rob Herring, Krzysztof Kozlowski,
Robert Nelson, Andrew Davis
Cc: Vignesh Raghavendra, linux-arm-kernel, devicetree, linux-kernel
Hi Andrew Davis,
On Mon, 15 May 2023 12:21:33 -0500, Andrew Davis wrote:
> Mailbox nodes are now disabled by default. The BeagleBoard AI64 DT
> addition went in at around the same time and must have missed that
> change so the mailboxes are not re-enabled. Do that here.
>
>
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/5] arm64: dts: ti: k3-j721e-beagleboneai64: Fix mailbox node status
commit: 155e7635ed1f3814d94d12556a3a0fed41d05b76
[2/5] arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes
commit: a0cfd88d4a8a1106e9de5c3b03e68efe9e6249ec
[3/5] arm64: dts: ti: k3-j721e: Enable PCIe nodes at the board level
commit: 731c6deda85ffcac3629bea757a806306e335618
[4/5] arm64: dts: ti: k3-am64: Enable Mailbox nodes at the board level
commit: 91f983ff7039fa2ff8ef153e118eec6d60f55e45
[5/5] arm64: dts: ti: k3-j721e: Enable MDIO nodes at the board level
commit: b0efb45d126ee914bafca37a582ae6574560dd25
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh
^ permalink raw reply [flat|nested] 12+ messages in thread