From: Luo Jie <quic_luoj@quicinc.com>
To: <andersson@kernel.org>, <agross@kernel.org>,
<konrad.dybcio@linaro.org>, <mturquette@baylibre.com>,
<sboyd@kernel.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
<catalin.marinas@arm.com>, <will@kernel.org>,
<p.zabel@pengutronix.de>
Cc: <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<quic_srichara@quicinc.com>, Luo Jie <quic_luoj@quicinc.com>
Subject: [PATCH v1 1/4] clk: qcom: branch: Add clk_branch2_qca8k_ops
Date: Wed, 9 Aug 2023 16:00:44 +0800 [thread overview]
Message-ID: <20230809080047.19877-2-quic_luoj@quicinc.com> (raw)
In-Reply-To: <20230809080047.19877-1-quic_luoj@quicinc.com>
Add the clk_branch2_qca8k_ops for supporting clock controller
where the hardware register is accessed by MDIO bus, and the
spin clock can't be used because of sleep during the MDIO
operation.
The clock is enabled by the .prepare instead of .enable when
the clk_branch2_qca8k_ops is used.
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
drivers/clk/qcom/clk-branch.c | 8 ++++++++
drivers/clk/qcom/clk-branch.h | 2 ++
2 files changed, 10 insertions(+)
diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c
index fc4735f74f0f..d07f2677c877 100644
--- a/drivers/clk/qcom/clk-branch.c
+++ b/drivers/clk/qcom/clk-branch.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/kernel.h>
@@ -153,3 +154,10 @@ const struct clk_ops clk_branch_simple_ops = {
.is_enabled = clk_is_enabled_regmap,
};
EXPORT_SYMBOL_GPL(clk_branch_simple_ops);
+
+const struct clk_ops clk_branch2_qca8k_ops = {
+ .prepare = clk_branch2_enable,
+ .unprepare = clk_branch2_disable,
+ .is_prepared = clk_is_enabled_regmap,
+};
+EXPORT_SYMBOL_GPL(clk_branch2_qca8k_ops);
diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h
index 0cf800b9d08d..37b092bf4d79 100644
--- a/drivers/clk/qcom/clk-branch.h
+++ b/drivers/clk/qcom/clk-branch.h
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2013, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */
#ifndef __QCOM_CLK_BRANCH_H__
#define __QCOM_CLK_BRANCH_H__
@@ -85,6 +86,7 @@ extern const struct clk_ops clk_branch_ops;
extern const struct clk_ops clk_branch2_ops;
extern const struct clk_ops clk_branch_simple_ops;
extern const struct clk_ops clk_branch2_aon_ops;
+extern const struct clk_ops clk_branch2_qca8k_ops;
#define to_clk_branch(_hw) \
container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
--
2.17.1
next prev parent reply other threads:[~2023-08-09 8:01 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-09 8:00 [PATCH v1 0/4] add clock controller of qca8386/qca8084 Luo Jie
2023-08-09 8:00 ` Luo Jie [this message]
2023-08-09 16:56 ` [PATCH v1 1/4] clk: qcom: branch: Add clk_branch2_qca8k_ops Konrad Dybcio
2023-08-10 3:46 ` Jie Luo
2023-08-09 8:00 ` [PATCH v1 2/4] dt-bindings: clock: add qca8386/qca8084 clock and reset definitions Luo Jie
2023-08-09 15:34 ` Krzysztof Kozlowski
2023-08-10 3:51 ` Jie Luo
2023-08-09 8:00 ` [PATCH v1 3/4] clk: qcom: add clock controller driver for qca8386/qca8084 Luo Jie
2023-08-09 15:38 ` Krzysztof Kozlowski
2023-08-10 4:44 ` Jie Luo
2023-08-09 16:57 ` Konrad Dybcio
2023-08-10 4:48 ` Jie Luo
2023-08-09 8:00 ` [PATCH v1 4/4] arm64: defconfig: Enable qca8k nss clock controller Luo Jie
2023-08-09 15:40 ` Krzysztof Kozlowski
2023-08-10 4:50 ` Jie Luo
2023-08-09 15:32 ` [PATCH v1 0/4] add clock controller of qca8386/qca8084 Krzysztof Kozlowski
2023-08-10 4:51 ` Jie Luo
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