From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: linux-pci@vger.kernel.org, "Bjorn Helgaas" <helgaas@kernel.org>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Lukas Wunner" <lukas@wunner.de>,
"Alexandru Gagniuc" <mr.nuke.me@gmail.com>,
"Dennis Dalessandro" <dennis.dalessandro@cornelisnetworks.com>,
"Jason Gunthorpe" <jgg@ziepe.ca>,
"Leon Romanovsky" <leon@kernel.org>,
linux-rdma@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: "Krishna chaitanya chundru" <quic_krichai@quicinc.com>,
"Srinivas Pandruvada" <srinivas.pandruvada@linux.intel.com>,
"Alex Deucher" <alexdeucher@gmail.com>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Subject: [PATCH 04/10] drm/IB/hfi1: Use RMW accessors for changing LNKCTL2
Date: Thu, 17 Aug 2023 15:17:02 +0300 [thread overview]
Message-ID: <20230817121708.53213-5-ilpo.jarvinen@linux.intel.com> (raw)
In-Reply-To: <20230817121708.53213-1-ilpo.jarvinen@linux.intel.com>
Don't assume that only the driver would be accessing LNKCTL2. In the
case of upstream (parent), the driver does not even own the device it's
changing the registers for.
Use RMW capability accessors which do proper locking to avoid losing
concurrent updates to the register value. This change is also useful as
a cleanup.
Suggested-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
---
drivers/infiniband/hw/hfi1/pcie.c | 30 ++++++++----------------------
1 file changed, 8 insertions(+), 22 deletions(-)
diff --git a/drivers/infiniband/hw/hfi1/pcie.c b/drivers/infiniband/hw/hfi1/pcie.c
index 08732e1ac966..60a177f52eb5 100644
--- a/drivers/infiniband/hw/hfi1/pcie.c
+++ b/drivers/infiniband/hw/hfi1/pcie.c
@@ -1212,14 +1212,11 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd)
(u32)lnkctl2);
/* only write to parent if target is not as high as ours */
if ((lnkctl2 & PCI_EXP_LNKCTL2_TLS) < target_vector) {
- lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS;
- lnkctl2 |= target_vector;
- dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__,
- (u32)lnkctl2);
- ret = pcie_capability_write_word(parent,
- PCI_EXP_LNKCTL2, lnkctl2);
+ ret = pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL2,
+ PCI_EXP_LNKCTL2_TLS,
+ target_vector);
if (ret) {
- dd_dev_err(dd, "Unable to write to PCI config\n");
+ dd_dev_err(dd, "Unable to change PCI target speed\n");
return_error = 1;
goto done;
}
@@ -1228,22 +1225,11 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd)
}
dd_dev_info(dd, "%s: setting target link speed\n", __func__);
- ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2);
+ ret = pcie_capability_clear_and_set_word(dd->pcidev, PCI_EXP_LNKCTL2,
+ PCI_EXP_LNKCTL2_TLS,
+ target_vector);
if (ret) {
- dd_dev_err(dd, "Unable to read from PCI config\n");
- return_error = 1;
- goto done;
- }
-
- dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__,
- (u32)lnkctl2);
- lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS;
- lnkctl2 |= target_vector;
- dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__,
- (u32)lnkctl2);
- ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2);
- if (ret) {
- dd_dev_err(dd, "Unable to write to PCI config\n");
+ dd_dev_err(dd, "Unable to change PCI target speed\n");
return_error = 1;
goto done;
}
--
2.30.2
next prev parent reply other threads:[~2023-08-17 12:18 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-17 12:16 [PATCH 00/10] Add PCIe Bandwidth Controller Ilpo Järvinen
2023-08-17 12:16 ` [PATCH 01/10] PCI: Protect Link Control 2 Register with RMW locking Ilpo Järvinen
2023-08-17 12:17 ` [PATCH 02/10] drm/radeon: Use RMW accessors for changing LNKCTL2 Ilpo Järvinen
2023-08-17 12:17 ` [PATCH 03/10] drm/amdgpu: " Ilpo Järvinen
2023-08-17 12:17 ` Ilpo Järvinen [this message]
2023-08-17 12:17 ` [PATCH 05/10] PCI: Store all PCIe Supported Link Speeds Ilpo Järvinen
2023-08-17 12:17 ` [PATCH 06/10] PCI: Cache PCIe device's Supported Speed Vector Ilpo Järvinen
2023-08-17 12:17 ` [PATCH 07/10] PCI/LINK: Re-add BW notification portdrv as PCIe BW controller Ilpo Järvinen
2023-08-17 12:17 ` [PATCH 08/10] PCI/bwctrl: Add "controller" part into PCIe bwctrl Ilpo Järvinen
2023-08-17 12:17 ` [PATCH 09/10] thermal: Add PCIe cooling driver Ilpo Järvinen
2023-08-23 19:47 ` Rafael J. Wysocki
2023-08-17 12:17 ` [PATCH 10/10] selftests/pcie_bwctrl: Create selftests Ilpo Järvinen
2023-09-04 6:26 ` [PATCH 00/10] Add PCIe Bandwidth Controller Krishna Chaitanya Chundru
2023-09-04 11:16 ` Ilpo Järvinen
2023-09-11 13:21 ` Krishna Chaitanya Chundru
2023-09-11 15:47 ` Ilpo Järvinen
2023-09-11 16:14 ` srinivas pandruvada
2023-09-12 12:52 ` Ilpo Järvinen
2023-09-12 17:45 ` srinivas pandruvada
2023-09-12 18:08 ` srinivas pandruvada
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