From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: linux-pci@vger.kernel.org, "Bjorn Helgaas" <helgaas@kernel.org>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Lukas Wunner" <lukas@wunner.de>,
"Alexandru Gagniuc" <mr.nuke.me@gmail.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-kernel@vger.kernel.org
Cc: "Krishna chaitanya chundru" <quic_krichai@quicinc.com>,
"Srinivas Pandruvada" <srinivas.pandruvada@linux.intel.com>,
"Alex Deucher" <alexdeucher@gmail.com>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Subject: [PATCH 06/10] PCI: Cache PCIe device's Supported Speed Vector
Date: Thu, 17 Aug 2023 15:17:04 +0300 [thread overview]
Message-ID: <20230817121708.53213-7-ilpo.jarvinen@linux.intel.com> (raw)
In-Reply-To: <20230817121708.53213-1-ilpo.jarvinen@linux.intel.com>
The Supported Link Speeds Vector in the Link Capabilities Register 2
corresponds to the bus below on Root Ports and Downstream Ports,
whereas it corresponds to the bus above on Upstream Ports and
Endpoints. Only the former is currently cached in pcie_bus_speeds in
the struct pci_bus. The link speeds that are supported is the
intersection of these two.
Store the device's Supported Link Speeds Vector into the struct pci_bus
when the Function 0 is enumerated (the Multi-Function Devices must have
same speeds the same for all Functions) to be easily able to calculate
the intersection of Supported Link Speeds.
Suggested-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
---
drivers/pci/probe.c | 10 ++++++++++
drivers/pci/remove.c | 2 ++
include/linux/pci.h | 1 +
3 files changed, 13 insertions(+)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 586d44b5ed7a..56d32297deb0 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2564,6 +2564,7 @@ static void pci_set_msi_domain(struct pci_dev *dev)
void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
{
+ u8 dev_speeds = 0;
int ret;
pci_configure_device(dev);
@@ -2590,11 +2591,20 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
pci_init_capabilities(dev);
+ if (pci_is_pcie(dev) && PCI_FUNC(dev->devfn) == 0) {
+ u32 linkcap, linkcap2;
+
+ pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &linkcap);
+ pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &linkcap2);
+ dev_speeds = pcie_get_supported_speeds(linkcap, linkcap2);
+ }
/*
* Add the device to our list of discovered devices
* and the bus list for fixup functions, etc.
*/
down_write(&pci_bus_sem);
+ if (dev_speeds)
+ bus->pcie_dev_speeds = dev_speeds;
list_add_tail(&dev->bus_list, &bus->devices);
up_write(&pci_bus_sem);
diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c
index d68aee29386b..7e80831467a8 100644
--- a/drivers/pci/remove.c
+++ b/drivers/pci/remove.c
@@ -35,6 +35,8 @@ static void pci_destroy_dev(struct pci_dev *dev)
device_del(&dev->dev);
down_write(&pci_bus_sem);
+ if (pci_is_pcie(dev) && PCI_FUNC(dev->devfn) == 0)
+ dev->bus->pcie_dev_speeds = 0;
list_del(&dev->bus_list);
up_write(&pci_bus_sem);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index d14d92bb7eba..8bfc8895f671 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -665,6 +665,7 @@ struct pci_bus {
unsigned char max_bus_speed; /* enum pci_bus_speed */
unsigned char cur_bus_speed; /* enum pci_bus_speed */
u8 pcie_bus_speeds;/* Supported Link Speeds Vector (+ reserved 0 at LSB) */
+ u8 pcie_dev_speeds;/* Device's Supported Link Speeds Vector (+ 0 at LSB) */
#ifdef CONFIG_PCI_DOMAINS_GENERIC
int domain_nr;
#endif
--
2.30.2
next prev parent reply other threads:[~2023-08-17 12:18 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-17 12:16 [PATCH 00/10] Add PCIe Bandwidth Controller Ilpo Järvinen
2023-08-17 12:16 ` [PATCH 01/10] PCI: Protect Link Control 2 Register with RMW locking Ilpo Järvinen
2023-08-17 12:17 ` [PATCH 02/10] drm/radeon: Use RMW accessors for changing LNKCTL2 Ilpo Järvinen
2023-08-17 12:17 ` [PATCH 03/10] drm/amdgpu: " Ilpo Järvinen
2023-08-17 12:17 ` [PATCH 04/10] drm/IB/hfi1: " Ilpo Järvinen
2023-08-17 12:17 ` [PATCH 05/10] PCI: Store all PCIe Supported Link Speeds Ilpo Järvinen
2023-08-17 12:17 ` Ilpo Järvinen [this message]
2023-08-17 12:17 ` [PATCH 07/10] PCI/LINK: Re-add BW notification portdrv as PCIe BW controller Ilpo Järvinen
2023-08-17 12:17 ` [PATCH 08/10] PCI/bwctrl: Add "controller" part into PCIe bwctrl Ilpo Järvinen
2023-08-17 12:17 ` [PATCH 09/10] thermal: Add PCIe cooling driver Ilpo Järvinen
2023-08-23 19:47 ` Rafael J. Wysocki
2023-08-17 12:17 ` [PATCH 10/10] selftests/pcie_bwctrl: Create selftests Ilpo Järvinen
2023-09-04 6:26 ` [PATCH 00/10] Add PCIe Bandwidth Controller Krishna Chaitanya Chundru
2023-09-04 11:16 ` Ilpo Järvinen
2023-09-11 13:21 ` Krishna Chaitanya Chundru
2023-09-11 15:47 ` Ilpo Järvinen
2023-09-11 16:14 ` srinivas pandruvada
2023-09-12 12:52 ` Ilpo Järvinen
2023-09-12 17:45 ` srinivas pandruvada
2023-09-12 18:08 ` srinivas pandruvada
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