From: Linhua Xu <Linhua.xu@unisoc.com>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Orson Zhai <orsonzhai@gmail.com>,
Baolin Wang <baolin.wang@linux.alibaba.com>,
Chunyan Zhang <zhang.lyra@gmail.com>,
<linux-kernel@vger.kernel.org>, <linux-gpio@vger.kernel.org>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
lh xu <xulh0829@gmail.com>, Linhua Xu <Linhua.Xu@unisoc.com>,
Zhirong Qiu <zhirong.qiu@unisoc.com>,
Xiongpeng Wu <xiongpeng.wu@unisoc.com>
Subject: [PATCH V2 5/6] pinctrl: sprd: Increase the range of register values
Date: Fri, 8 Sep 2023 13:51:45 +0800 [thread overview]
Message-ID: <20230908055146.18347-6-Linhua.xu@unisoc.com> (raw)
In-Reply-To: <20230908055146.18347-1-Linhua.xu@unisoc.com>
From: Linhua Xu <Linhua.Xu@unisoc.com>
As the UNISOC pin controller version iterates, more registers are required
to meet new functional requirements. Thus modify them.
Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
---
drivers/pinctrl/sprd/pinctrl-sprd.h | 30 +++++++++++++++--------------
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.h b/drivers/pinctrl/sprd/pinctrl-sprd.h
index a696f81ce663..5357874186fd 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd.h
+++ b/drivers/pinctrl/sprd/pinctrl-sprd.h
@@ -7,30 +7,32 @@
#ifndef __PINCTRL_SPRD_H__
#define __PINCTRL_SPRD_H__
+#include <linux/bits.h>
+
struct platform_device;
-#define NUM_OFFSET (20)
-#define TYPE_OFFSET (16)
-#define BIT_OFFSET (8)
-#define WIDTH_OFFSET (4)
+#define NUM_OFFSET 22
+#define TYPE_OFFSET 18
+#define BIT_OFFSET 10
+#define WIDTH_OFFSET 6
#define SPRD_PIN_INFO(num, type, offset, width, reg) \
- (((num) & 0xFFF) << NUM_OFFSET | \
- ((type) & 0xF) << TYPE_OFFSET | \
- ((offset) & 0xFF) << BIT_OFFSET | \
- ((width) & 0xF) << WIDTH_OFFSET | \
- ((reg) & 0xF))
+ (((num) & GENMASK(10, 0)) << NUM_OFFSET | \
+ ((type) & GENMASK(3, 0)) << TYPE_OFFSET | \
+ ((offset) & GENMASK(7, 0)) << BIT_OFFSET | \
+ ((width) & GENMASK(3, 0)) << WIDTH_OFFSET | \
+ ((reg) & GENMASK(5, 0)))
#define SPRD_PINCTRL_PIN(pin) SPRD_PINCTRL_PIN_DATA(pin, #pin)
#define SPRD_PINCTRL_PIN_DATA(a, b) \
{ \
.name = b, \
- .num = (((a) >> NUM_OFFSET) & 0xfff), \
- .type = (((a) >> TYPE_OFFSET) & 0xf), \
- .bit_offset = (((a) >> BIT_OFFSET) & 0xff), \
- .bit_width = ((a) >> WIDTH_OFFSET & 0xf), \
- .reg = ((a) & 0xf) \
+ .num = (((a) & GENMASK(31, 22)) >> NUM_OFFSET), \
+ .type = (((a) & GENMASK(21, 18)) >> TYPE_OFFSET), \
+ .bit_offset = (((a) & GENMASK(17, 10)) >> BIT_OFFSET), \
+ .bit_width = (((a) & GENMASK(9, 6)) >> WIDTH_OFFSET), \
+ .reg = ((a) & GENMASK(5, 0)) \
}
enum pin_type {
--
2.17.1
next prev parent reply other threads:[~2023-09-08 5:52 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-08 5:51 [PATCH V2 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linhua Xu
2023-09-08 5:51 ` [PATCH V2 1/6] pinctrl: sprd: Modify the probe function parameters Linhua Xu
2023-09-11 9:46 ` Andy Shevchenko
2023-09-12 8:13 ` Baolin Wang
2023-09-08 5:51 ` [PATCH V2 2/6] pinctrl: sprd: Fix the incorrect mask and shift definition Linhua Xu
2023-09-11 9:50 ` Andy Shevchenko
2023-09-12 8:28 ` Baolin Wang
2023-11-13 13:50 ` Linus Walleij
2023-09-08 5:51 ` [PATCH V2 3/6] pinctrl: sprd: Modify pull-up parameters Linhua Xu
2023-09-11 9:51 ` Andy Shevchenko
2023-09-12 8:22 ` Baolin Wang
2023-09-08 5:51 ` [PATCH V2 4/6] pinctrl: sprd: Add pinctrl support for UMS512 Linhua Xu
2023-09-09 1:56 ` kernel test robot
2023-09-11 9:53 ` Andy Shevchenko
2023-09-08 5:51 ` Linhua Xu [this message]
2023-09-11 9:55 ` [PATCH V2 5/6] pinctrl: sprd: Increase the range of register values Andy Shevchenko
2023-09-12 8:37 ` Baolin Wang
[not found] ` <CAPjKKSrs9X2msnDg=9rC8H57Dq8FPd7SWyBsr2MCwL0FMNkHPA@mail.gmail.com>
2023-10-26 2:57 ` Baolin Wang
2023-09-08 5:51 ` [PATCH V2 6/6] pinctrl: sprd: Add pinctrl support for UMS9621 Linhua Xu
2023-09-11 9:56 ` Andy Shevchenko
2023-09-11 13:41 ` [PATCH V2 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linus Walleij
2023-09-12 8:40 ` Baolin Wang
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