* [PATCH 1/2] RISC-V: Detect and Enable Svadu Extension Support [not found] <20230915082701.3643-1-yongxuan.wang@sifive.com> @ 2023-09-15 8:26 ` Yong-Xuan Wang 2023-09-15 8:45 ` Conor Dooley 2023-09-15 8:26 ` [PATCH 2/2] RISC-V: KVM: Add Svadu Extension Support for Guest/VM Yong-Xuan Wang 1 sibling, 1 reply; 4+ messages in thread From: Yong-Xuan Wang @ 2023-09-15 8:26 UTC (permalink / raw) To: linux-riscv, kvm-riscv Cc: greentime.hu, vincent.chen, tjytimi, alex, Yong-Xuan Wang, Paul Walmsley, Palmer Dabbelt, Albert Ou, Anup Patel, Guo Ren, Andrew Jones, Conor Dooley, wchen, Heiko Stuebner, Jisheng Zhang, Andrew Morton, Alexandre Ghiti, Kemeng Shi, David Hildenbrand, Sergey Matyukevich, Matthew Wilcox (Oracle), Charlie Jenkins, Qinglin Pan, Rick Edgecombe, Evan Green, Sunil V L, linux-kernel We detect Svadu extension support from DTB and add arch_has_hw_pte_young() to enable optimization in MGLRU and __wp_page_copy_user() if Svadu extension is available. Signed-off-by: Jinyu Tang <tjytimi@163.com> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> --- arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/pgtable.h | 6 ++++++ arch/riscv/kernel/cpufeature.c | 1 + 4 files changed, 9 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 777cb8299551..10648b372a2a 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -194,6 +194,7 @@ /* xENVCFG flags */ #define ENVCFG_STCE (_AC(1, ULL) << 63) #define ENVCFG_PBMTE (_AC(1, ULL) << 62) +#define ENVCFG_HADE (_AC(1, ULL) << 61) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) #define ENVCFG_CBIE_SHIFT 4 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b7b58258f6c7..1013661d6516 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -58,6 +58,7 @@ #define RISCV_ISA_EXT_ZICSR 40 #define RISCV_ISA_EXT_ZIFENCEI 41 #define RISCV_ISA_EXT_ZIHPM 42 +#define RISCV_ISA_EXT_SVADU 43 #define RISCV_ISA_EXT_MAX 64 diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index b2ba3f79cfe9..f3d077dff8ac 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -629,6 +629,12 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot) return __pgprot(prot); } +#define arch_has_hw_pte_young arch_has_hw_pte_young +static inline bool arch_has_hw_pte_young(void) +{ + return riscv_has_extension_likely(RISCV_ISA_EXT_SVADU); +} + /* * THP functions */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1cfbba65d11a..ead378c04991 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -178,6 +178,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), + __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), -- 2.17.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] RISC-V: Detect and Enable Svadu Extension Support 2023-09-15 8:26 ` [PATCH 1/2] RISC-V: Detect and Enable Svadu Extension Support Yong-Xuan Wang @ 2023-09-15 8:45 ` Conor Dooley 2023-09-20 3:49 ` Yong-Xuan Wang 0 siblings, 1 reply; 4+ messages in thread From: Conor Dooley @ 2023-09-15 8:45 UTC (permalink / raw) To: Yong-Xuan Wang Cc: linux-riscv, kvm-riscv, greentime.hu, vincent.chen, tjytimi, alex, Paul Walmsley, Palmer Dabbelt, Albert Ou, Anup Patel, Guo Ren, Andrew Jones, wchen, Heiko Stuebner, Jisheng Zhang, Andrew Morton, Alexandre Ghiti, Kemeng Shi, David Hildenbrand, Sergey Matyukevich, Matthew Wilcox (Oracle), Charlie Jenkins, Qinglin Pan, Rick Edgecombe, Evan Green, Sunil V L, linux-kernel [-- Attachment #1: Type: text/plain, Size: 2946 bytes --] On Fri, Sep 15, 2023 at 08:26:57AM +0000, Yong-Xuan Wang wrote: > We detect Svadu extension support from DTB and add arch_has_hw_pte_young() > to enable optimization in MGLRU and __wp_page_copy_user() if Svadu > extension is available. > > Signed-off-by: Jinyu Tang <tjytimi@163.com> You're either missing a From: or a Co-developed-by: tag here. > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> > --- > arch/riscv/include/asm/csr.h | 1 + > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/include/asm/pgtable.h | 6 ++++++ > arch/riscv/kernel/cpufeature.c | 1 + > 4 files changed, 9 insertions(+) > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index 777cb8299551..10648b372a2a 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -194,6 +194,7 @@ > /* xENVCFG flags */ > #define ENVCFG_STCE (_AC(1, ULL) << 63) > #define ENVCFG_PBMTE (_AC(1, ULL) << 62) > +#define ENVCFG_HADE (_AC(1, ULL) << 61) > #define ENVCFG_CBZE (_AC(1, UL) << 7) > #define ENVCFG_CBCFE (_AC(1, UL) << 6) > #define ENVCFG_CBIE_SHIFT 4 > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index b7b58258f6c7..1013661d6516 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -58,6 +58,7 @@ > #define RISCV_ISA_EXT_ZICSR 40 > #define RISCV_ISA_EXT_ZIFENCEI 41 > #define RISCV_ISA_EXT_ZIHPM 42 > +#define RISCV_ISA_EXT_SVADU 43 > > #define RISCV_ISA_EXT_MAX 64 > > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > index b2ba3f79cfe9..f3d077dff8ac 100644 > --- a/arch/riscv/include/asm/pgtable.h > +++ b/arch/riscv/include/asm/pgtable.h > @@ -629,6 +629,12 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot) > return __pgprot(prot); > } > > +#define arch_has_hw_pte_young arch_has_hw_pte_young > +static inline bool arch_has_hw_pte_young(void) > +{ > + return riscv_has_extension_likely(RISCV_ISA_EXT_SVADU); No hardware currently has this, why is it likely? > +} > + > /* > * THP functions > */ > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 1cfbba65d11a..ead378c04991 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -178,6 +178,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), > + __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU), This needs to be documented in riscv/extensions.yaml. Thanks, Conor. > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), > -- > 2.17.1 > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] RISC-V: Detect and Enable Svadu Extension Support 2023-09-15 8:45 ` Conor Dooley @ 2023-09-20 3:49 ` Yong-Xuan Wang 0 siblings, 0 replies; 4+ messages in thread From: Yong-Xuan Wang @ 2023-09-20 3:49 UTC (permalink / raw) To: Conor Dooley Cc: linux-riscv, kvm-riscv, greentime.hu, vincent.chen, tjytimi, alex, Paul Walmsley, Palmer Dabbelt, Albert Ou, Anup Patel, Guo Ren, Andrew Jones, wchen, Heiko Stuebner, Jisheng Zhang, Andrew Morton, Alexandre Ghiti, Kemeng Shi, David Hildenbrand, Sergey Matyukevich, Matthew Wilcox (Oracle), Charlie Jenkins, Qinglin Pan, Rick Edgecombe, Evan Green, Sunil V L, linux-kernel Hi Conor, On Fri, Sep 15, 2023 at 4:45 PM Conor Dooley <conor.dooley@microchip.com> wrote: > > On Fri, Sep 15, 2023 at 08:26:57AM +0000, Yong-Xuan Wang wrote: > > We detect Svadu extension support from DTB and add arch_has_hw_pte_young() > > to enable optimization in MGLRU and __wp_page_copy_user() if Svadu > > extension is available. > > > > Signed-off-by: Jinyu Tang <tjytimi@163.com> > > You're either missing a From: or a Co-developed-by: tag here. > > > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> > > --- > > arch/riscv/include/asm/csr.h | 1 + > > arch/riscv/include/asm/hwcap.h | 1 + > > arch/riscv/include/asm/pgtable.h | 6 ++++++ > > arch/riscv/kernel/cpufeature.c | 1 + > > 4 files changed, 9 insertions(+) > > > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > > index 777cb8299551..10648b372a2a 100644 > > --- a/arch/riscv/include/asm/csr.h > > +++ b/arch/riscv/include/asm/csr.h > > @@ -194,6 +194,7 @@ > > /* xENVCFG flags */ > > #define ENVCFG_STCE (_AC(1, ULL) << 63) > > #define ENVCFG_PBMTE (_AC(1, ULL) << 62) > > +#define ENVCFG_HADE (_AC(1, ULL) << 61) > > #define ENVCFG_CBZE (_AC(1, UL) << 7) > > #define ENVCFG_CBCFE (_AC(1, UL) << 6) > > #define ENVCFG_CBIE_SHIFT 4 > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > > index b7b58258f6c7..1013661d6516 100644 > > --- a/arch/riscv/include/asm/hwcap.h > > +++ b/arch/riscv/include/asm/hwcap.h > > @@ -58,6 +58,7 @@ > > #define RISCV_ISA_EXT_ZICSR 40 > > #define RISCV_ISA_EXT_ZIFENCEI 41 > > #define RISCV_ISA_EXT_ZIHPM 42 > > +#define RISCV_ISA_EXT_SVADU 43 > > > > #define RISCV_ISA_EXT_MAX 64 > > > > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > > index b2ba3f79cfe9..f3d077dff8ac 100644 > > --- a/arch/riscv/include/asm/pgtable.h > > +++ b/arch/riscv/include/asm/pgtable.h > > @@ -629,6 +629,12 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot) > > return __pgprot(prot); > > } > > > > +#define arch_has_hw_pte_young arch_has_hw_pte_young > > +static inline bool arch_has_hw_pte_young(void) > > +{ > > + return riscv_has_extension_likely(RISCV_ISA_EXT_SVADU); > > No hardware currently has this, why is it likely? > > > +} > > + > > /* > > * THP functions > > */ > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 1cfbba65d11a..ead378c04991 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -178,6 +178,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > > __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), > > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > > __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), > > + __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU), > > This needs to be documented in riscv/extensions.yaml. > Thank you! I will update these in v2 patch. Regards, Yong-Xuan > Thanks, > Conor. > > > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), > > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), > > -- > > 2.17.1 > > ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/2] RISC-V: KVM: Add Svadu Extension Support for Guest/VM [not found] <20230915082701.3643-1-yongxuan.wang@sifive.com> 2023-09-15 8:26 ` [PATCH 1/2] RISC-V: Detect and Enable Svadu Extension Support Yong-Xuan Wang @ 2023-09-15 8:26 ` Yong-Xuan Wang 1 sibling, 0 replies; 4+ messages in thread From: Yong-Xuan Wang @ 2023-09-15 8:26 UTC (permalink / raw) To: linux-riscv, kvm-riscv Cc: greentime.hu, vincent.chen, tjytimi, alex, Yong-Xuan Wang, Anup Patel, Atish Patra, Paul Walmsley, Palmer Dabbelt, Albert Ou, kvm, linux-kernel We extend the KVM ISA extension ONE_REG interface to allow VMM tools to detect and enable Svadu extension for Guest/VM. Also set the HADE bit in henvcfg CSR if Svadu extension is available for Guest/VM. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu.c | 3 +++ arch/riscv/kvm/vcpu_onereg.c | 1 + 3 files changed, 5 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 992c5e407104..3c7a6c762d0f 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -131,6 +131,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZICSR, KVM_RISCV_ISA_EXT_ZIFENCEI, KVM_RISCV_ISA_EXT_ZIHPM, + KVM_RISCV_ISA_EXT_SVADU, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 82229db1ce73..91b92a1f4e33 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -487,6 +487,9 @@ static void kvm_riscv_vcpu_update_config(const unsigned long *isa) if (riscv_isa_extension_available(isa, ZICBOZ)) henvcfg |= ENVCFG_CBZE; + if (riscv_isa_extension_available(isa, SVADU)) + henvcfg |= ENVCFG_HADE; + csr_write(CSR_HENVCFG, henvcfg); #ifdef CONFIG_32BIT csr_write(CSR_HENVCFGH, henvcfg >> 32); diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 1b7e9fa265cb..211915dad677 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -36,6 +36,7 @@ static const unsigned long kvm_isa_ext_arr[] = { /* Multi letter extensions (alphabetically sorted) */ KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVADU), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), -- 2.17.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-09-20 3:49 UTC | newest]
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[not found] <20230915082701.3643-1-yongxuan.wang@sifive.com>
2023-09-15 8:26 ` [PATCH 1/2] RISC-V: Detect and Enable Svadu Extension Support Yong-Xuan Wang
2023-09-15 8:45 ` Conor Dooley
2023-09-20 3:49 ` Yong-Xuan Wang
2023-09-15 8:26 ` [PATCH 2/2] RISC-V: KVM: Add Svadu Extension Support for Guest/VM Yong-Xuan Wang
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