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From: Bhavya Kapoor <b-kapoor@ti.com>
To: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
Cc: <conor+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
	<robh+dt@kernel.org>, <kristo@kernel.org>, <vigneshr@ti.com>,
	<nm@ti.com>, <b-kapoor@ti.com>
Subject: [PATCH 1/3] arm64: dts: ti: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode
Date: Fri, 1 Dec 2023 13:50:43 +0530	[thread overview]
Message-ID: <20231201082045.790478-2-b-kapoor@ti.com> (raw)
In-Reply-To: <20231201082045.790478-1-b-kapoor@ti.com>

DDR52 speed mode is enabled for eMMC in J7200 but its Itap Delay Value
is not present in the device tree. Thus, add Itap Delay Value for eMMC
High Speed DDR which is DDR52 speed mode for J7200 SoC according to
datasheet for J7200.

[+] Refer to : section 7.9.5.16.1 MMCSD0 - eMMC Interface,  in
	J7200 datasheet
- https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf

Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 264913f83287..39ce465c8e00 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -647,6 +647,7 @@ main_sdhci0: mmc@4f80000 {
 		ti,otap-del-sel-hs400 = <0x5>;
 		ti,itap-del-sel-legacy = <0x10>;
 		ti,itap-del-sel-mmc-hs = <0xa>;
+		ti,itap-del-sel-ddr52 = <0x3>;
 		ti,strobe-sel = <0x77>;
 		ti,clkbuf-sel = <0x7>;
 		ti,trm-icp = <0x8>;
-- 
2.34.1


  reply	other threads:[~2023-12-01  8:21 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-01  8:20 [PATCH 0/3] arm64: dts: ti: Add Itap Delay Value For High Speed DDR Bhavya Kapoor
2023-12-01  8:20 ` Bhavya Kapoor [this message]
2023-12-05 19:22   ` [PATCH 1/3] arm64: dts: ti: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode Judith Mendez
2023-12-01  8:20 ` [PATCH 2/3] arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 " Bhavya Kapoor
2023-12-05 19:24   ` Judith Mendez
2023-12-01  8:20 ` [PATCH 3/3] arm64: dts: ti: k3-j784s4-main: " Bhavya Kapoor
2023-12-05 19:25   ` Judith Mendez
2023-12-05 18:31 ` [PATCH 0/3] arm64: dts: ti: Add Itap Delay Value For High Speed DDR Kumar, Udit
2023-12-14 11:07   ` Bhavya Kapoor
2023-12-14 15:00     ` Kumar, Udit
2023-12-15 17:21 ` Nishanth Menon

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