* [PATCH v3 1/4] RISC-V: Detect and Enable Svadu Extension Support
[not found] <20231102120129.11261-1-yongxuan.wang@sifive.com>
@ 2023-11-02 12:01 ` Yong-Xuan Wang
2023-12-13 14:53 ` Andrew Jones
2023-11-02 12:01 ` [PATCH v3 2/4] dt-bindings: riscv: Add Svadu Entry Yong-Xuan Wang
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: Yong-Xuan Wang @ 2023-11-02 12:01 UTC (permalink / raw)
To: linux-riscv, kvm-riscv
Cc: greentime.hu, vincent.chen, tjytimi, alex, conor.dooley, ajones,
Yong-Xuan Wang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Guo Ren, Daniel Henrique Barboza, Heiko Stuebner,
Jisheng Zhang, Andrew Morton, Alexandre Ghiti, Kemeng Shi,
David Hildenbrand, Charlie Jenkins, Sergey Matyukevich,
Matthew Wilcox (Oracle),
Qinglin Pan, Rick Edgecombe, Evan Green, Sunil V L, linux-kernel
Svadu is a RISC-V extension for hardware updating of PTE A/D bits.
In this patch we detect Svadu extension support from DTB and
add arch_has_hw_pte_young() to enable optimization in MGLRU and
__wp_page_copy_user() if Svadu extension is available.
Co-developed-by: Jinyu Tang <tjytimi@163.com>
Signed-off-by: Jinyu Tang <tjytimi@163.com>
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/include/asm/csr.h | 1 +
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/pgtable.h | 6 ++++++
arch/riscv/kernel/cpufeature.c | 1 +
4 files changed, 9 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 777cb8299551..e6935fd48c0c 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -194,6 +194,7 @@
/* xENVCFG flags */
#define ENVCFG_STCE (_AC(1, ULL) << 63)
#define ENVCFG_PBMTE (_AC(1, ULL) << 62)
+#define ENVCFG_ADUE (_AC(1, ULL) << 61)
#define ENVCFG_CBZE (_AC(1, UL) << 7)
#define ENVCFG_CBCFE (_AC(1, UL) << 6)
#define ENVCFG_CBIE_SHIFT 4
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index b7b58258f6c7..1013661d6516 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -58,6 +58,7 @@
#define RISCV_ISA_EXT_ZICSR 40
#define RISCV_ISA_EXT_ZIFENCEI 41
#define RISCV_ISA_EXT_ZIHPM 42
+#define RISCV_ISA_EXT_SVADU 43
#define RISCV_ISA_EXT_MAX 64
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index b2ba3f79cfe9..028b700cd27b 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -629,6 +629,12 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
return __pgprot(prot);
}
+#define arch_has_hw_pte_young arch_has_hw_pte_young
+static inline bool arch_has_hw_pte_young(void)
+{
+ return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU);
+}
+
/*
* THP functions
*/
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 1cfbba65d11a..ead378c04991 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -178,6 +178,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
+ __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU),
__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v3 1/4] RISC-V: Detect and Enable Svadu Extension Support
2023-11-02 12:01 ` [PATCH v3 1/4] RISC-V: Detect and Enable Svadu Extension Support Yong-Xuan Wang
@ 2023-12-13 14:53 ` Andrew Jones
0 siblings, 0 replies; 6+ messages in thread
From: Andrew Jones @ 2023-12-13 14:53 UTC (permalink / raw)
To: Yong-Xuan Wang
Cc: linux-riscv, kvm-riscv, greentime.hu, vincent.chen, tjytimi,
alex, conor.dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Guo Ren, Daniel Henrique Barboza, Heiko Stuebner,
Jisheng Zhang, Andrew Morton, Alexandre Ghiti, Kemeng Shi,
David Hildenbrand, Charlie Jenkins, Sergey Matyukevich,
Matthew Wilcox (Oracle),
Qinglin Pan, Rick Edgecombe, Evan Green, Sunil V L, linux-kernel
On Thu, Nov 02, 2023 at 12:01:22PM +0000, Yong-Xuan Wang wrote:
> Svadu is a RISC-V extension for hardware updating of PTE A/D bits.
>
> In this patch we detect Svadu extension support from DTB and
> add arch_has_hw_pte_young() to enable optimization in MGLRU and
> __wp_page_copy_user() if Svadu extension is available.
>
> Co-developed-by: Jinyu Tang <tjytimi@163.com>
> Signed-off-by: Jinyu Tang <tjytimi@163.com>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> arch/riscv/include/asm/csr.h | 1 +
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/include/asm/pgtable.h | 6 ++++++
> arch/riscv/kernel/cpufeature.c | 1 +
> 4 files changed, 9 insertions(+)
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 777cb8299551..e6935fd48c0c 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -194,6 +194,7 @@
> /* xENVCFG flags */
> #define ENVCFG_STCE (_AC(1, ULL) << 63)
> #define ENVCFG_PBMTE (_AC(1, ULL) << 62)
> +#define ENVCFG_ADUE (_AC(1, ULL) << 61)
> #define ENVCFG_CBZE (_AC(1, UL) << 7)
> #define ENVCFG_CBCFE (_AC(1, UL) << 6)
> #define ENVCFG_CBIE_SHIFT 4
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index b7b58258f6c7..1013661d6516 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -58,6 +58,7 @@
> #define RISCV_ISA_EXT_ZICSR 40
> #define RISCV_ISA_EXT_ZIFENCEI 41
> #define RISCV_ISA_EXT_ZIHPM 42
> +#define RISCV_ISA_EXT_SVADU 43
>
> #define RISCV_ISA_EXT_MAX 64
>
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index b2ba3f79cfe9..028b700cd27b 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -629,6 +629,12 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
> return __pgprot(prot);
> }
>
> +#define arch_has_hw_pte_young arch_has_hw_pte_young
> +static inline bool arch_has_hw_pte_young(void)
> +{
> + return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU);
> +}
> +
> /*
> * THP functions
> */
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 1cfbba65d11a..ead378c04991 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -178,6 +178,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
> __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
> + __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU),
> __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
> __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> --
> 2.17.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 2/4] dt-bindings: riscv: Add Svadu Entry
[not found] <20231102120129.11261-1-yongxuan.wang@sifive.com>
2023-11-02 12:01 ` [PATCH v3 1/4] RISC-V: Detect and Enable Svadu Extension Support Yong-Xuan Wang
@ 2023-11-02 12:01 ` Yong-Xuan Wang
2023-11-02 12:01 ` [PATCH v3 3/4] RISC-V: KVM: Add Svadu Extension Support for Guest/VM Yong-Xuan Wang
2023-11-02 12:01 ` [PATCH v3 4/4] KVM: riscv: selftests: Add Svadu Extension to get-reg-list testt Yong-Xuan Wang
3 siblings, 0 replies; 6+ messages in thread
From: Yong-Xuan Wang @ 2023-11-02 12:01 UTC (permalink / raw)
To: linux-riscv, kvm-riscv
Cc: greentime.hu, vincent.chen, tjytimi, alex, conor.dooley, ajones,
Yong-Xuan Wang, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, devicetree,
linux-kernel
Add an entry for the Svadu extension to the riscv,isa-extensions property.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index cc1f546fdbdc..b5a0aed0165b 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -147,6 +147,12 @@ properties:
ratified at commit 3f9ed34 ("Add ability to manually trigger
workflow. (#2)") of riscv-time-compare.
+ - const: svadu
+ description: |
+ The standard Svadu supervisor-level extension for hardware updating
+ of PTE A/D bits as frozen at commit b65e07c ("move to Frozen
+ state") of riscv-svadu.
+
- const: svinval
description:
The standard Svinval supervisor-level extension for fine-grained
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v3 3/4] RISC-V: KVM: Add Svadu Extension Support for Guest/VM
[not found] <20231102120129.11261-1-yongxuan.wang@sifive.com>
2023-11-02 12:01 ` [PATCH v3 1/4] RISC-V: Detect and Enable Svadu Extension Support Yong-Xuan Wang
2023-11-02 12:01 ` [PATCH v3 2/4] dt-bindings: riscv: Add Svadu Entry Yong-Xuan Wang
@ 2023-11-02 12:01 ` Yong-Xuan Wang
2023-11-02 12:01 ` [PATCH v3 4/4] KVM: riscv: selftests: Add Svadu Extension to get-reg-list testt Yong-Xuan Wang
3 siblings, 0 replies; 6+ messages in thread
From: Yong-Xuan Wang @ 2023-11-02 12:01 UTC (permalink / raw)
To: linux-riscv, kvm-riscv
Cc: greentime.hu, vincent.chen, tjytimi, alex, conor.dooley, ajones,
Yong-Xuan Wang, Anup Patel, Atish Patra, Paul Walmsley,
Palmer Dabbelt, Albert Ou, kvm, linux-kernel
We extend the KVM ISA extension ONE_REG interface to allow VMM
tools to detect and enable Svadu extension for Guest/VM.
Also set the ADUE bit in henvcfg CSR if Svadu extension is
available for Guest/VM.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu.c | 3 +++
arch/riscv/kvm/vcpu_onereg.c | 1 +
3 files changed, 5 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 992c5e407104..3c7a6c762d0f 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -131,6 +131,7 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_ZICSR,
KVM_RISCV_ISA_EXT_ZIFENCEI,
KVM_RISCV_ISA_EXT_ZIHPM,
+ KVM_RISCV_ISA_EXT_SVADU,
KVM_RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 82229db1ce73..c95a3447eb50 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -487,6 +487,9 @@ static void kvm_riscv_vcpu_update_config(const unsigned long *isa)
if (riscv_isa_extension_available(isa, ZICBOZ))
henvcfg |= ENVCFG_CBZE;
+ if (riscv_isa_extension_available(isa, SVADU))
+ henvcfg |= ENVCFG_ADUE;
+
csr_write(CSR_HENVCFG, henvcfg);
#ifdef CONFIG_32BIT
csr_write(CSR_HENVCFGH, henvcfg >> 32);
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index b7e0e03c69b1..2b7c7592e273 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -36,6 +36,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
/* Multi letter extensions (alphabetically sorted) */
KVM_ISA_EXT_ARR(SSAIA),
KVM_ISA_EXT_ARR(SSTC),
+ KVM_ISA_EXT_ARR(SVADU),
KVM_ISA_EXT_ARR(SVINVAL),
KVM_ISA_EXT_ARR(SVNAPOT),
KVM_ISA_EXT_ARR(SVPBMT),
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v3 4/4] KVM: riscv: selftests: Add Svadu Extension to get-reg-list testt
[not found] <20231102120129.11261-1-yongxuan.wang@sifive.com>
` (2 preceding siblings ...)
2023-11-02 12:01 ` [PATCH v3 3/4] RISC-V: KVM: Add Svadu Extension Support for Guest/VM Yong-Xuan Wang
@ 2023-11-02 12:01 ` Yong-Xuan Wang
2023-12-13 14:59 ` Andrew Jones
3 siblings, 1 reply; 6+ messages in thread
From: Yong-Xuan Wang @ 2023-11-02 12:01 UTC (permalink / raw)
To: linux-riscv, kvm-riscv
Cc: greentime.hu, vincent.chen, tjytimi, alex, conor.dooley, ajones,
Yong-Xuan Wang, Paolo Bonzini, Shuah Khan, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Anup Patel, Atish Patra, Haibo Xu,
kvm, linux-kselftest, linux-kernel
Update the get-reg-list test to test the Svadu Extension is available
for guest OS.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
---
.../testing/selftests/kvm/riscv/get-reg-list.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
index 9f99ea42f45f..972538d76f48 100644
--- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
+++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
@@ -49,6 +49,7 @@ bool filter_reg(__u64 reg)
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR:
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI:
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM:
+ case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVADU:
return true;
/* AIA registers are always available when Ssaia can't be disabled */
case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect):
@@ -340,6 +341,7 @@ static const char *isa_ext_id_to_str(__u64 id)
"KVM_RISCV_ISA_EXT_ZICSR",
"KVM_RISCV_ISA_EXT_ZIFENCEI",
"KVM_RISCV_ISA_EXT_ZIHPM",
+ "KVM_RISCV_ISA_EXT_SVADU",
};
if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) {
@@ -700,6 +702,10 @@ static __u64 fp_d_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_D,
};
+static __u64 svadu_regs[] = {
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVADU,
+};
+
#define BASE_SUBLIST \
{"base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), \
.skips_set = base_skips_set, .skips_set_n = ARRAY_SIZE(base_skips_set),}
@@ -739,6 +745,9 @@ static __u64 fp_d_regs[] = {
#define FP_D_REGS_SUBLIST \
{"fp_d", .feature = KVM_RISCV_ISA_EXT_D, .regs = fp_d_regs, \
.regs_n = ARRAY_SIZE(fp_d_regs),}
+#define SVADU_REGS_SUBLIST \
+ {"svadu", .feature = KVM_RISCV_ISA_EXT_SVADU, .regs = svadu_regs, \
+ .regs_n = ARRAY_SIZE(svadu_regs),}
static struct vcpu_reg_list h_config = {
.sublists = {
@@ -876,6 +885,14 @@ static struct vcpu_reg_list fp_d_config = {
},
};
+static struct vcpu_reg_list svadu_config = {
+ .sublists = {
+ BASE_SUBLIST,
+ SVADU_REGS_SUBLIST,
+ {0},
+ },
+};
+
struct vcpu_reg_list *vcpu_configs[] = {
&h_config,
&zicbom_config,
@@ -894,5 +911,6 @@ struct vcpu_reg_list *vcpu_configs[] = {
&aia_config,
&fp_f_config,
&fp_d_config,
+ &svadu_config,
};
int vcpu_configs_n = ARRAY_SIZE(vcpu_configs);
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v3 4/4] KVM: riscv: selftests: Add Svadu Extension to get-reg-list testt
2023-11-02 12:01 ` [PATCH v3 4/4] KVM: riscv: selftests: Add Svadu Extension to get-reg-list testt Yong-Xuan Wang
@ 2023-12-13 14:59 ` Andrew Jones
0 siblings, 0 replies; 6+ messages in thread
From: Andrew Jones @ 2023-12-13 14:59 UTC (permalink / raw)
To: Yong-Xuan Wang
Cc: linux-riscv, kvm-riscv, greentime.hu, vincent.chen, tjytimi,
alex, conor.dooley, Paolo Bonzini, Shuah Khan, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Anup Patel, Atish Patra, Haibo Xu,
kvm, linux-kselftest, linux-kernel
On Thu, Nov 02, 2023 at 12:01:25PM +0000, Yong-Xuan Wang wrote:
> Update the get-reg-list test to test the Svadu Extension is available
> for guest OS.
>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
> .../testing/selftests/kvm/riscv/get-reg-list.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index 9f99ea42f45f..972538d76f48 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -49,6 +49,7 @@ bool filter_reg(__u64 reg)
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR:
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI:
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM:
> + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVADU:
> return true;
> /* AIA registers are always available when Ssaia can't be disabled */
> case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect):
> @@ -340,6 +341,7 @@ static const char *isa_ext_id_to_str(__u64 id)
> "KVM_RISCV_ISA_EXT_ZICSR",
> "KVM_RISCV_ISA_EXT_ZIFENCEI",
> "KVM_RISCV_ISA_EXT_ZIHPM",
> + "KVM_RISCV_ISA_EXT_SVADU",
> };
>
> if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) {
> @@ -700,6 +702,10 @@ static __u64 fp_d_regs[] = {
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_D,
> };
>
> +static __u64 svadu_regs[] = {
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVADU,
> +};
> +
> #define BASE_SUBLIST \
> {"base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), \
> .skips_set = base_skips_set, .skips_set_n = ARRAY_SIZE(base_skips_set),}
> @@ -739,6 +745,9 @@ static __u64 fp_d_regs[] = {
> #define FP_D_REGS_SUBLIST \
> {"fp_d", .feature = KVM_RISCV_ISA_EXT_D, .regs = fp_d_regs, \
> .regs_n = ARRAY_SIZE(fp_d_regs),}
> +#define SVADU_REGS_SUBLIST \
> + {"svadu", .feature = KVM_RISCV_ISA_EXT_SVADU, .regs = svadu_regs, \
> + .regs_n = ARRAY_SIZE(svadu_regs),}
>
> static struct vcpu_reg_list h_config = {
> .sublists = {
> @@ -876,6 +885,14 @@ static struct vcpu_reg_list fp_d_config = {
> },
> };
>
> +static struct vcpu_reg_list svadu_config = {
> + .sublists = {
> + BASE_SUBLIST,
> + SVADU_REGS_SUBLIST,
> + {0},
> + },
> +};
> +
> struct vcpu_reg_list *vcpu_configs[] = {
> &h_config,
> &zicbom_config,
> @@ -894,5 +911,6 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &aia_config,
> &fp_f_config,
> &fp_d_config,
> + &svadu_config,
> };
> int vcpu_configs_n = ARRAY_SIZE(vcpu_configs);
> --
> 2.17.1
>
We should rebase this on [1] since it changes sublist management.
[1] https://lore.kernel.org/all/20231128145357.413321-2-apatel@ventanamicro.com/
Thanks,
drew
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