[PATCH 0/2] arm64/fp: Initialise all bits in vector control registers to known values

[PATCH 0/2] arm64/fp: Initialise all bits in vector control registers to known values

[Mark Brown]

We currently do read/modify/write sequences whenever we update fields in
ZCR_EL1 and SMCR_EL1 so fields we are not explicitly handling will not
be initialised to known values, fix this.  The EL2 registers are already
fully configured.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
Mark Brown (2):
      arm64/sve: Ensure that all fields in ZCR_EL1 are set to known values
      arm64/sme: Ensure that all fields in SMCR_EL1 are set to known values

 arch/arm64/kernel/fpsimd.c | 5 +++++
 1 file changed, 5 insertions(+)
---
base-commit: 54be6c6c5ae8e0d93a6c4641cb7528eb0b6ba478
change-id: 20240212-arm64-fp-init-vec-cr-018449327500

Best regards,
-- 
Mark Brown <broonie@kernel.org>

[PATCH 1/2] arm64/sve: Ensure that all fields in ZCR_EL1 are set to known values

[Mark Brown]

At present nothing in our CPU initialisation code ever sets unknown fields
in ZCR_EL1 to known values, all updates to ZCR_EL1 are read/modify/write
sequences for LEN. All the unknown fields are RES0, explicitly initialise
them as such to avoid future surprises.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/kernel/fpsimd.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index a5dc6f764195..cc3c9ad877a8 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -1134,6 +1134,8 @@ void cpu_enable_sve(const struct arm64_cpu_capabilities *__always_unused p)
 {
 	write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_ZEN_EL1EN, CPACR_EL1);
 	isb();
+
+	write_sysreg_s(0, SYS_ZCR_EL1);
 }
 
 void __init sve_setup(void)

-- 
2.30.2

[PATCH 2/2] arm64/sme: Ensure that all fields in SMCR_EL1 are set to known values

[Mark Brown]

At present nothing in our CPU initialisation code ever sets unknown fields
in SMCR_EL1 to known values, all updates to SMCR_EL1 are read/modify/write
sequences. All the unknown fields are RES0, explicitly initialise them as
such to avoid future surprises.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/kernel/fpsimd.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index cc3c9ad877a8..f96907b813fa 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -1247,6 +1247,9 @@ void cpu_enable_sme(const struct arm64_cpu_capabilities *__always_unused p)
 	write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_SMEN_EL1EN, CPACR_EL1);
 	isb();
 
+	/* Ensure all bits in SMCR are set to known values */
+	write_sysreg_s(0, SYS_SMCR_EL1);
+
 	/* Allow EL0 to access TPIDR2 */
 	write_sysreg(read_sysreg(SCTLR_EL1) | SCTLR_ELx_ENTP2, SCTLR_EL1);
 	isb();

-- 
2.30.2

Re: [PATCH 0/2] arm64/fp: Initialise all bits in vector control registers to known values

[Catalin Marinas]

On Tue, 13 Feb 2024 15:32:44 +0000, Mark Brown wrote:
> We currently do read/modify/write sequences whenever we update fields in
> ZCR_EL1 and SMCR_EL1 so fields we are not explicitly handling will not
> be initialised to known values, fix this.  The EL2 registers are already
> fully configured.
> 
> 

Applied to arm64 (for-next/misc), thanks!

[1/2] arm64/sve: Ensure that all fields in ZCR_EL1 are set to known values
      https://git.kernel.org/arm64/c/2f0090549b64
[2/2] arm64/sme: Ensure that all fields in SMCR_EL1 are set to known values
      https://git.kernel.org/arm64/c/93576e349887

-- 
Catalin