From: Andy Chiu <andy.chiu@sifive.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Andy Chiu <andy.chiu@sifive.com>,
Vincent Chen <vincent.chen@sifive.com>,
Heiko Stuebner <heiko@sntech.de>,
Conor Dooley <conor.dooley@microchip.com>,
Conor Dooley <conor@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Jonathan Corbet <corbet@lwn.net>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Palmer Dabbelt <palmer@rivosinc.com>,
Greentime Hu <greentime.hu@sifive.com>,
Guo Ren <guoren@kernel.org>,
devicetree@vger.kernel.org, linux-doc@vger.kernel.org
Subject: [PATCH v3 5/7] dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description
Date: Mon, 18 Mar 2024 18:39:58 +0800 [thread overview]
Message-ID: <20240318-zve-detection-v3-5-e12d42107fa8@sifive.com> (raw)
In-Reply-To: <20240318-zve-detection-v3-0-e12d42107fa8@sifive.com>
Add description for Zve32x Zve32f Zve64x Zve64f Zve64d ISA extensions.
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
Changelog v3:
- Correct extension names and their order (Stefan)
Changelog v2:
- new patch since v2
---
.../devicetree/bindings/riscv/extensions.yaml | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 468c646247aa..cfed80ad5540 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -381,6 +381,36 @@ properties:
instructions, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
+ - const: zve32f
+ description:
+ The standard Zve32f extension for embedded processors, as ratified
+ in commit 6f702a2 ("Vector extensions are now ratified") of
+ riscv-v-spec.
+
+ - const: zve32x
+ description:
+ The standard Zve32x extension for embedded processors, as ratified
+ in commit 6f702a2 ("Vector extensions are now ratified") of
+ riscv-v-spec.
+
+ - const: zve64d
+ description:
+ The standard Zve64d extension for embedded processors, as ratified
+ in commit 6f702a2 ("Vector extensions are now ratified") of
+ riscv-v-spec.
+
+ - const: zve64f
+ description:
+ The standard Zve64f extension for embedded processors, as ratified
+ in commit 6f702a2 ("Vector extensions are now ratified") of
+ riscv-v-spec.
+
+ - const: zve64x
+ description:
+ The standard Zve64x extension for embedded processors, as ratified
+ in commit 6f702a2 ("Vector extensions are now ratified") of
+ riscv-v-spec.
+
- const: zvfh
description:
The standard Zvfh extension for vectored half-precision
--
2.44.0.rc2
next prev parent reply other threads:[~2024-03-18 10:40 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-18 10:39 [PATCH v3 0/7] Support Zve32[xf] and Zve64[xfd] Vector subextensions Andy Chiu
2024-03-18 10:39 ` [PATCH v3 1/7] riscv: vector: add a comment when calling riscv_setup_vsize() Andy Chiu
2024-03-18 10:39 ` [PATCH v3 2/7] riscv: smp: fail booting up smp if inconsistent vlen is detected Andy Chiu
2024-03-20 9:26 ` [External] " yunhui cui
2024-03-18 10:39 ` [PATCH v3 3/7] riscv: cpufeature: call match_isa_ext() for single-letter extensions Andy Chiu
2024-03-18 10:39 ` [PATCH v3 4/7] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection Andy Chiu
2024-03-18 10:39 ` Andy Chiu [this message]
2024-03-18 10:39 ` [PATCH v3 6/7] riscv: hwprobe: add zve Vector subextensions into hwprobe interface Andy Chiu
2024-03-18 10:40 ` [PATCH v3 7/7] riscv: vector: adjust minimum Vector requirement to ZVE32X Andy Chiu
2024-03-18 17:32 ` kernel test robot
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240318-zve-detection-v3-5-e12d42107fa8@sifive.com \
--to=andy.chiu@sifive.com \
--cc=aou@eecs.berkeley.edu \
--cc=conor.dooley@microchip.com \
--cc=conor@kernel.org \
--cc=corbet@lwn.net \
--cc=devicetree@vger.kernel.org \
--cc=greentime.hu@sifive.com \
--cc=guoren@kernel.org \
--cc=heiko@sntech.de \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=palmer@rivosinc.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=vincent.chen@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®