From: kernel test robot <lkp@intel.com>
To: Andy Chiu <andy.chiu@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Vincent Chen <vincent.chen@sifive.com>,
Heiko Stuebner <heiko@sntech.de>,
Conor Dooley <conor.dooley@microchip.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Jonathan Corbet <corbet@lwn.net>
Cc: oe-kbuild-all@lists.linux.dev, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org,
Greentime Hu <greentime.hu@sifive.com>,
Guo Ren <guoren@kernel.org>,
devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
Joel Granados <j.granados@samsung.com>
Subject: Re: [PATCH v3 7/7] riscv: vector: adjust minimum Vector requirement to ZVE32X
Date: Tue, 19 Mar 2024 01:32:34 +0800 [thread overview]
Message-ID: <202403190142.8MfCnioh-lkp@intel.com> (raw)
In-Reply-To: <20240318-zve-detection-v3-7-e12d42107fa8@sifive.com>
Hi Andy,
kernel test robot noticed the following build errors:
[auto build test ERROR on 099dbac6e90c620d8ce0bbf75bbdc94da1feb4fb]
url: https://github.com/intel-lab-lkp/linux/commits/Andy-Chiu/riscv-vector-add-a-comment-when-calling-riscv_setup_vsize/20240318-184348
base: 099dbac6e90c620d8ce0bbf75bbdc94da1feb4fb
patch link: https://lore.kernel.org/r/20240318-zve-detection-v3-7-e12d42107fa8%40sifive.com
patch subject: [PATCH v3 7/7] riscv: vector: adjust minimum Vector requirement to ZVE32X
config: riscv-allnoconfig (https://download.01.org/0day-ci/archive/20240319/202403190142.8MfCnioh-lkp@intel.com/config)
compiler: riscv64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240319/202403190142.8MfCnioh-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202403190142.8MfCnioh-lkp@intel.com/
All errors (new ones prefixed by >>):
arch/riscv/kernel/process.c: In function 'arch_release_task_struct':
>> arch/riscv/kernel/process.c:181:24: error: 'ZVE32X' undeclared (first use in this function)
181 | if (has_vector(ZVE32X))
| ^~~~~~
arch/riscv/kernel/process.c:181:24: note: each undeclared identifier is reported only once for each function it appears in
arch/riscv/kernel/process.c: In function 'copy_thread':
arch/riscv/kernel/process.c:228:24: error: 'ZVE32X' undeclared (first use in this function)
228 | if (has_vector(ZVE32X))
| ^~~~~~
--
arch/riscv/kernel/signal.c: In function 'restore_sigcontext':
>> arch/riscv/kernel/signal.c:191:41: error: 'ZVE32X' undeclared (first use in this function)
191 | if (!has_vector(ZVE32X) || !riscv_v_vstate_query(regs) ||
| ^~~~~~
arch/riscv/kernel/signal.c:191:41: note: each undeclared identifier is reported only once for each function it appears in
arch/riscv/kernel/signal.c: In function 'get_rt_frame_size':
arch/riscv/kernel/signal.c:213:24: error: 'ZVE32X' undeclared (first use in this function)
213 | if (has_vector(ZVE32X)) {
| ^~~~~~
arch/riscv/kernel/signal.c: In function 'setup_sigcontext':
arch/riscv/kernel/signal.c:286:24: error: 'ZVE32X' undeclared (first use in this function)
286 | if (has_vector(ZVE32X) && riscv_v_vstate_query(regs))
| ^~~~~~
--
arch/riscv/kernel/sys_hwprobe.c: In function 'hwprobe_isa_ext0':
>> arch/riscv/kernel/sys_hwprobe.c:72:24: error: 'v' undeclared (first use in this function)
72 | if (has_vector(v))
| ^
arch/riscv/kernel/sys_hwprobe.c:72:24: note: each undeclared identifier is reported only once for each function it appears in
>> arch/riscv/kernel/sys_hwprobe.c:119:32: error: 'ZVE32X' undeclared (first use in this function)
119 | if (has_vector(ZVE32X)) {
| ^~~~~~
--
In file included from kernel/sched/core.c:78:
kernel/sched/core.c: In function 'context_switch':
>> arch/riscv/include/asm/switch_to.h:81:24: error: 'ZVE32X' undeclared (first use in this function)
81 | if (has_vector(ZVE32X)) \
| ^~~~~~
kernel/sched/core.c:5400:9: note: in expansion of macro 'switch_to'
5400 | switch_to(prev, next, prev);
| ^~~~~~~~~
arch/riscv/include/asm/switch_to.h:81:24: note: each undeclared identifier is reported only once for each function it appears in
81 | if (has_vector(ZVE32X)) \
| ^~~~~~
kernel/sched/core.c:5400:9: note: in expansion of macro 'switch_to'
5400 | switch_to(prev, next, prev);
| ^~~~~~~~~
vim +/ZVE32X +181 arch/riscv/kernel/process.c
177
178 void arch_release_task_struct(struct task_struct *tsk)
179 {
180 /* Free the vector context of datap. */
> 181 if (has_vector(ZVE32X))
182 riscv_v_thread_free(tsk);
183 }
184
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
prev parent reply other threads:[~2024-03-18 17:33 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-18 10:39 [PATCH v3 0/7] Support Zve32[xf] and Zve64[xfd] Vector subextensions Andy Chiu
2024-03-18 10:39 ` [PATCH v3 1/7] riscv: vector: add a comment when calling riscv_setup_vsize() Andy Chiu
2024-03-18 10:39 ` [PATCH v3 2/7] riscv: smp: fail booting up smp if inconsistent vlen is detected Andy Chiu
2024-03-20 9:26 ` [External] " yunhui cui
2024-03-18 10:39 ` [PATCH v3 3/7] riscv: cpufeature: call match_isa_ext() for single-letter extensions Andy Chiu
2024-03-18 10:39 ` [PATCH v3 4/7] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection Andy Chiu
2024-03-18 10:39 ` [PATCH v3 5/7] dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description Andy Chiu
2024-03-18 10:39 ` [PATCH v3 6/7] riscv: hwprobe: add zve Vector subextensions into hwprobe interface Andy Chiu
2024-03-18 10:40 ` [PATCH v3 7/7] riscv: vector: adjust minimum Vector requirement to ZVE32X Andy Chiu
2024-03-18 17:32 ` kernel test robot [this message]
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