From: Josh Poimboeuf <jpoimboe@kernel.org>
To: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org,
Linus Torvalds <torvalds@linux-foundation.org>,
Daniel Sneddon <daniel.sneddon@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Alexandre Chartre <alexandre.chartre@oracle.com>,
Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
Peter Zijlstra <peterz@infradead.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Sean Christopherson <seanjc@google.com>,
Andrew Cooper <andrew.cooper3@citrix.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Nikolay Borisov <nik.borisov@suse.com>,
KP Singh <kpsingh@kernel.org>, Waiman Long <longman@redhat.com>,
Borislav Petkov <bp@alien8.de>
Subject: Re: [PATCH 5/7] x86/bugs: Only harden syscalls when needed
Date: Thu, 11 Apr 2024 20:57:40 -0700 [thread overview]
Message-ID: <20240412035740.ojgvlqahqlm2umsx@treble> (raw)
In-Reply-To: <20240412001522.3zp2mzked4ksglkl@desk>
On Thu, Apr 11, 2024 at 05:15:22PM -0700, Pawan Gupta wrote:
> > + * Do either a direct or an indirect call, depending on whether indirect calls
> > + * are considered safe.
> > + */
> > +#define __do_syscall(table, func_direct, nr, regs) \
> > +({ \
> > + unsigned long __rax, __rdi, __rsi; \
> > + \
> > + asm_inline volatile( \
> > + ALTERNATIVE("call " __stringify(func_direct) "\n\t", \
> > + ANNOTATE_RETPOLINE_SAFE \
> > + "call *%[func_ptr]\n\t", \
>
> This will likely not insert the lfence before the indirect call in
> spectre_v2=eibrs,lfence mode. As X86_FEATURE_INDIRECT_SAFE is not
> cleared when eIBRS is enabled, this will not be converted to direct
> call.
Hm, I think the problem here is that SPECTRE_V2_EIBRS_LFENCE confusingly
sets X86_FEATURE_RETPOLINE. So the following bit unintentionally takes
effect:
/* Retpoline mitigates against BHI unless the CPU has RRSBA behavior */
if (cpu_feature_enabled(X86_FEATURE_RETPOLINE)) {
spec_ctrl_disable_kernel_rrsba();
if (rrsba_disabled)
return;
}
If RRSBA gets disabled (which is likely), bhi_select_mitigation()
returns early and X86_FEATURE_INDIRECT_SAFE doesn't get cleared.
"LFENCE; CALL" is most definitely not a retpoline, so it's weird for
SPECTRE_V2_EIBRS_LFENCE to be setting X86_FEATURE_RETPOLINE. We should
fix that.
Honestly, I think SPECTRE_V2_EIBRS_LFENCE is obsolete anyway. It was
originally intended to be a BHI mitigation, but the real-world
benchmarks I've seen are showing it to be quite a bit slower than the
actual BHI mitigations.
Plus it's only a partial fix because the speculative window after the
branch can still be big enough to do multiple loads.
For similar reasons I'm thinking we should also remove the non-eIBRS
version (SPECTRE_V2_LFENCE).
I'll make some patches to do that, with warnings printed if somebody
tries to use them. They can just fall back to the (more secure and
generally faster) defaults.
> [...]
> > @@ -1720,6 +1744,7 @@ static void __init spectre_v2_select_mitigation(void)
> >
> > case SPECTRE_V2_CMD_RETPOLINE_LFENCE:
> > pr_err(SPECTRE_V2_LFENCE_MSG);
> > + setup_clear_cpu_cap(X86_FEATURE_INDIRECT_SAFE);
>
> I don't know if it intentional, this seems to be the duplicate of
> X86_FEATURE_INDIRECT_SAFE clear later in SPECTRE_V2_LFENCE mode. Also it
> seems a bit odd to do this here in SPECTRE_V2_CMD handling.
Yeah, I accidentally left that in from an earlier implementation. It's
harmless but I'll clean that up too with a new patch unless Ingo wants
to remove that line.
--
Josh
next prev parent reply other threads:[~2024-04-12 3:57 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-11 5:40 [PATCH 0/7] x86/bugs: BHI fixes / improvements Josh Poimboeuf
2024-04-11 5:40 ` [PATCH 1/7] x86/bugs: BHI documentation fixes Josh Poimboeuf
2024-04-11 6:21 ` Nikolay Borisov
2024-04-11 8:40 ` [tip: x86/urgent] x86/bugs: Fix BHI documentation tip-bot2 for Josh Poimboeuf
2024-04-11 5:40 ` [PATCH 2/7] x86/bugs: Cache the value of MSR_IA32_ARCH_CAPABILITIES Josh Poimboeuf
2024-04-11 6:22 ` Nikolay Borisov
2024-04-11 7:32 ` [PATCH 2b/7] x86/bugs: Rename various 'ia32_cap' variables to 'x86_arch_cap_msr' Ingo Molnar
2024-04-11 8:40 ` [tip: x86/urgent] x86/bugs: Cache the value of MSR_IA32_ARCH_CAPABILITIES tip-bot2 for Josh Poimboeuf
2024-04-11 8:40 ` [tip: x86/urgent] x86/bugs: Rename various 'ia32_cap' variables to 'x86_arch_cap_msr' tip-bot2 for Ingo Molnar
2024-04-11 5:40 ` [PATCH 3/7] x86/bugs: Fix BHI handling of RRSBA Josh Poimboeuf
2024-04-11 8:40 ` [tip: x86/urgent] " tip-bot2 for Josh Poimboeuf
2024-04-11 10:02 ` [PATCH 3/7] " Andrew Cooper
2024-04-11 15:34 ` Josh Poimboeuf
2024-04-11 5:40 ` [PATCH 4/7] x86/bugs: Clarify that syscall hardening isn't a BHI mitigation Josh Poimboeuf
2024-04-11 8:40 ` [tip: x86/urgent] " tip-bot2 for Josh Poimboeuf
2024-04-11 5:40 ` [PATCH 5/7] x86/bugs: Only harden syscalls when needed Josh Poimboeuf
2024-04-11 6:20 ` Nikolay Borisov
2024-04-11 15:08 ` Josh Poimboeuf
2024-04-11 8:40 ` [tip: x86/urgent] " tip-bot2 for Josh Poimboeuf
2024-04-11 10:06 ` [PATCH 5/7] " Andrew Cooper
2024-04-11 15:38 ` Josh Poimboeuf
2024-04-12 10:24 ` Andrew Cooper
2024-04-12 0:15 ` Pawan Gupta
2024-04-12 3:57 ` Josh Poimboeuf [this message]
2024-04-12 4:17 ` Josh Poimboeuf
2024-04-12 5:20 ` Josh Poimboeuf
2024-04-12 10:36 ` Andrew Cooper
2024-04-12 20:24 ` Josh Poimboeuf
2024-04-12 5:27 ` Pawan Gupta
2024-04-12 10:07 ` Ingo Molnar
2024-04-12 6:28 ` Pawan Gupta
2024-04-12 6:37 ` Pawan Gupta
2024-04-11 5:40 ` [PATCH 6/7] x86/bugs: Remove CONFIG_BHI_MITIGATION_AUTO and spectre_bhi=auto Josh Poimboeuf
2024-04-11 6:23 ` Nikolay Borisov
2024-04-11 8:40 ` [tip: x86/urgent] " tip-bot2 for Josh Poimboeuf
2024-04-12 10:12 ` tip-bot2 for Josh Poimboeuf
2024-04-11 5:40 ` [PATCH 7/7] x86/bugs: Replace CONFIG_SPECTRE_BHI_{ON,OFF} with CONFIG_MITIGATION_SPECTRE_BHI Josh Poimboeuf
2024-04-11 7:48 ` Ingo Molnar
2024-04-11 8:18 ` Ingo Molnar
2024-04-17 5:35 ` Reinette Chatre
2024-04-11 15:24 ` Josh Poimboeuf
2024-04-11 8:40 ` [tip: x86/urgent] " tip-bot2 for Josh Poimboeuf
2024-04-12 10:12 ` tip-bot2 for Josh Poimboeuf
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