From: Jim Quinlan <james.quinlan@broadcom.com>
To: linux-pci@vger.kernel.org,
Nicolas Saenz Julienne <nsaenz@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Cyril Brulebois <kibi@debian.org>,
Stanimir Varbanov <svarbanov@suse.de>,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com,
james.quinlan@broadcom.com
Cc: "Florian Fainelli" <florian.fainelli@broadcom.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM
BCM2711/BCM2835 ARM ARCHITECTURE),
linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM
BCM2711/BCM2835 ARM ARCHITECTURE),
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v5 12/12] PCI: brcmstb: Enable 7712 SOCs
Date: Wed, 31 Jul 2024 18:28:26 -0400 [thread overview]
Message-ID: <20240731222831.14895-13-james.quinlan@broadcom.com> (raw)
In-Reply-To: <20240731222831.14895-1-james.quinlan@broadcom.com>
The Broadcom STB 7712 is the sibling chip of the RPi 5 (2712).
It has one PCIe controller with a single port, supports gen2
and one lane only. The current revision of the chip is "C0"
or "C1".
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Reviewed-by: Stanimir Varbanov <svarbanov@suse.de>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
---
drivers/pci/controller/pcie-brcmstb.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 4623b70f9ad8..44b323a13357 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -1202,6 +1202,10 @@ static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;
u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */
+ /* 7712 does not have this (RGR1) timer */
+ if (pcie->soc_base == BCM7712)
+ return;
+
/* Each unit in timeout register is 1/216,000,000 seconds */
writel(216 * timeout_us, pcie->base + REG_OFFSET);
}
@@ -1673,6 +1677,13 @@ static const int pcie_offsets_bmips_7425[] = {
[PCIE_INTR2_CPU_BASE] = 0x4300,
};
+static const int pcie_offset_bcm7712[] = {
+ [EXT_CFG_INDEX] = 0x9000,
+ [EXT_CFG_DATA] = 0x9004,
+ [PCIE_HARD_DEBUG] = 0x4304,
+ [PCIE_INTR2_CPU_BASE] = 0x4400,
+};
+
static const struct pcie_cfg_data generic_cfg = {
.offsets = pcie_offsets,
.soc_base = GENERIC,
@@ -1738,6 +1749,14 @@ static const struct pcie_cfg_data bcm7216_cfg = {
.num_inbound_wins = 3,
};
+static const struct pcie_cfg_data bcm7712_cfg = {
+ .offsets = pcie_offset_bcm7712,
+ .perst_set = brcm_pcie_perst_set_7278,
+ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
+ .soc_base = BCM7712,
+ .num_inbound_wins = 10,
+};
+
static const struct of_device_id brcm_pcie_match[] = {
{ .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
{ .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
@@ -1747,6 +1766,7 @@ static const struct of_device_id brcm_pcie_match[] = {
{ .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
{ .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
{ .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
+ { .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg },
{},
};
--
2.17.1
next prev parent reply other threads:[~2024-07-31 22:28 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-31 22:28 [PATCH v5 00/12] PCI: brcnstb: Enable STB 7712 SOC Jim Quinlan
2024-07-31 22:28 ` [PATCH v5 01/12] dt-bindings: PCI: Cleanup of brcmstb YAML and add 7712 SoC Jim Quinlan
2024-08-01 16:35 ` Florian Fainelli
2024-08-02 6:43 ` Krzysztof Kozlowski
2024-08-12 22:07 ` Jim Quinlan
2024-08-13 8:27 ` Krzysztof Kozlowski
2024-08-14 17:35 ` Jim Quinlan
2024-08-14 18:05 ` Krzysztof Kozlowski
2024-07-31 22:28 ` [PATCH v5 02/12] dt-bindings: PCI: brcmstb: Add 7712 SoC description Jim Quinlan
2024-08-01 16:36 ` Florian Fainelli
2024-08-02 7:18 ` Krzysztof Kozlowski
2024-07-31 22:28 ` [PATCH v5 03/12] PCI: brcmstb: Use common error handling code in brcm_pcie_probe() Jim Quinlan
2024-08-01 16:37 ` Florian Fainelli
2024-08-07 2:52 ` Manivannan Sadhasivam
2024-08-12 20:12 ` Jim Quinlan
2024-08-07 2:54 ` Manivannan Sadhasivam
2024-08-13 16:45 ` Stanimir Varbanov
2024-08-13 17:06 ` James Quinlan
2024-07-31 22:28 ` [PATCH v5 04/12] PCI: brcmstb: Use bridge reset if available Jim Quinlan
2024-08-01 16:37 ` Florian Fainelli
2024-08-07 2:59 ` Manivannan Sadhasivam
2024-08-09 11:16 ` Stanimir Varbanov
2024-08-12 15:13 ` Jim Quinlan
2024-08-12 15:46 ` Jim Quinlan
2024-08-12 22:28 ` Stanimir Varbanov
2024-08-13 15:46 ` James Quinlan
2024-07-31 22:28 ` [PATCH v5 05/12] PCI: brcmstb: Use swinit " Jim Quinlan
2024-08-01 16:37 ` Florian Fainelli
2024-08-07 3:03 ` Manivannan Sadhasivam
2024-08-12 17:54 ` Jim Quinlan
2024-08-09 9:53 ` Stanimir Varbanov
2024-08-12 13:43 ` Jim Quinlan
2024-08-12 15:57 ` Manivannan Sadhasivam
2024-08-12 22:05 ` Stanimir Varbanov
2024-07-31 22:28 ` [PATCH v5 06/12] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific Jim Quinlan
2024-07-31 22:28 ` [PATCH v5 07/12] PCI: brcmstb: Remove two unused constants from driver Jim Quinlan
2024-07-31 22:28 ` [PATCH v5 08/12] PCI: brcmstb: Don't conflate the reset rescal with phy ctrl Jim Quinlan
2024-08-07 3:05 ` Manivannan Sadhasivam
2024-07-31 22:28 ` [PATCH v5 09/12] PCI: brcmstb: Refactor for chips with many regular inbound windows Jim Quinlan
2024-08-01 16:39 ` Florian Fainelli
2024-08-06 22:58 ` Stanimir Varbanov
2024-08-07 14:04 ` Manivannan Sadhasivam
2024-08-07 14:16 ` Florian Fainelli
2024-08-07 15:03 ` Manivannan Sadhasivam
2024-08-12 19:14 ` Jim Quinlan
2024-07-31 22:28 ` [PATCH v5 10/12] PCI: brcmstb: Check return value of all reset_control_xxx calls Jim Quinlan
2024-08-07 14:11 ` Manivannan Sadhasivam
2024-08-12 18:20 ` Jim Quinlan
2024-07-31 22:28 ` [PATCH v5 11/12] PCI: brcmstb: Change field name from 'type' to 'soc_base' Jim Quinlan
2024-08-01 16:34 ` Florian Fainelli
2024-07-31 22:28 ` Jim Quinlan [this message]
2024-08-07 14:12 ` [PATCH v5 12/12] PCI: brcmstb: Enable 7712 SOCs Manivannan Sadhasivam
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