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From: Florian Fainelli <florian.fainelli@broadcom.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
	Jim Quinlan <james.quinlan@broadcom.com>
Cc: linux-pci@vger.kernel.org,
	"Nicolas Saenz Julienne" <nsaenz@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Cyril Brulebois" <kibi@debian.org>,
	"Stanimir Varbanov" <svarbanov@suse.de>,
	"Krzysztof Kozlowski" <krzk@kernel.org>,
	bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
	<linux-rpi-kernel@lists.infradead.org>,
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
	<linux-arm-kernel@lists.infradead.org>,
	"open list" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v5 09/12] PCI: brcmstb: Refactor for chips with many regular inbound windows
Date: Wed, 7 Aug 2024 07:16:44 -0700	[thread overview]
Message-ID: <c32a28f3-aa64-4e89-a8f7-acfaed8ac090@broadcom.com> (raw)
In-Reply-To: <20240807140401.GJ3412@thinkpad>



On 8/7/2024 7:04 AM, Manivannan Sadhasivam wrote:
> On Wed, Jul 31, 2024 at 06:28:23PM -0400, Jim Quinlan wrote:
>> Provide support for new chips with multiple inbound windows while
>> keeping the legacy support for the older chips.
>>
>> In existing chips there are three inbound windows with fixed purposes: the
>> first was for mapping SoC internal registers, the second was for memory,
>> and the third was for memory but with the endian swapped.  Typically, only
>> one window was used.
>>
>> Complicating the inbound window usage was the fact that the PCIe HW would
>> do a baroque internal mapping of system memory, and concatenate the regions
>> of multiple memory controllers.
>>
>> Newer chips such as the 7712 and Cable Modem SOCs take a step forward and
>> drop the internal mapping while providing for multiple inbound windows.
>> This works in concert with the dma-ranges property, where each provided
>> range becomes an inbound window.
>>
>> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
>> ---

[snip]

>> +static void set_inbound_win_registers(struct brcm_pcie *pcie,
>> +				      const struct inbound_win *inbound_wins,
>> +				      int num_inbound_wins)
>> +{
>> +	void __iomem *base = pcie->base;
>> +	int i;
>> +
>> +	for (i = 1; i <= num_inbound_wins; i++) {
>> +		u64 pci_offset = inbound_wins[i].pci_offset;
>> +		u64 cpu_addr = inbound_wins[i].cpu_addr;
>> +		u64 size = inbound_wins[i].size;
>> +		u32 reg_offset = brcm_bar_reg_offset(i);
>> +		u32 tmp = lower_32_bits(pci_offset);
>> +
>> +		u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(size),
>> +				  PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK);
>> +
>> +		/* Write low */
>> +		writel(tmp, base + reg_offset);
> 
> Can you use writel_relaxed() instead? Here and below. I don't see a necessity to
> use the barrier that comes with non-relaxed version of writel.

Out of curiosity what is the reasoning here for asking to use 
writel_relaxed(), this is not a hot path, this is a configuration path 
anyway. I am not certain clear on the implication of using 
writel_relaxed() on systems like 7712/2712 where the busing is different 
from the other STB chips.
-- 
Florian


  reply	other threads:[~2024-08-07 14:16 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-31 22:28 [PATCH v5 00/12] PCI: brcnstb: Enable STB 7712 SOC Jim Quinlan
2024-07-31 22:28 ` [PATCH v5 01/12] dt-bindings: PCI: Cleanup of brcmstb YAML and add 7712 SoC Jim Quinlan
2024-08-01 16:35   ` Florian Fainelli
2024-08-02  6:43   ` Krzysztof Kozlowski
2024-08-12 22:07     ` Jim Quinlan
2024-08-13  8:27       ` Krzysztof Kozlowski
2024-08-14 17:35         ` Jim Quinlan
2024-08-14 18:05           ` Krzysztof Kozlowski
2024-07-31 22:28 ` [PATCH v5 02/12] dt-bindings: PCI: brcmstb: Add 7712 SoC description Jim Quinlan
2024-08-01 16:36   ` Florian Fainelli
2024-08-02  7:18   ` Krzysztof Kozlowski
2024-07-31 22:28 ` [PATCH v5 03/12] PCI: brcmstb: Use common error handling code in brcm_pcie_probe() Jim Quinlan
2024-08-01 16:37   ` Florian Fainelli
2024-08-07  2:52   ` Manivannan Sadhasivam
2024-08-12 20:12     ` Jim Quinlan
2024-08-07  2:54   ` Manivannan Sadhasivam
2024-08-13 16:45   ` Stanimir Varbanov
2024-08-13 17:06     ` James Quinlan
2024-07-31 22:28 ` [PATCH v5 04/12] PCI: brcmstb: Use bridge reset if available Jim Quinlan
2024-08-01 16:37   ` Florian Fainelli
2024-08-07  2:59   ` Manivannan Sadhasivam
2024-08-09 11:16   ` Stanimir Varbanov
2024-08-12 15:13     ` Jim Quinlan
2024-08-12 15:46     ` Jim Quinlan
2024-08-12 22:28       ` Stanimir Varbanov
2024-08-13 15:46         ` James Quinlan
2024-07-31 22:28 ` [PATCH v5 05/12] PCI: brcmstb: Use swinit " Jim Quinlan
2024-08-01 16:37   ` Florian Fainelli
2024-08-07  3:03   ` Manivannan Sadhasivam
2024-08-12 17:54     ` Jim Quinlan
2024-08-09  9:53   ` Stanimir Varbanov
2024-08-12 13:43     ` Jim Quinlan
2024-08-12 15:57       ` Manivannan Sadhasivam
2024-08-12 22:05       ` Stanimir Varbanov
2024-07-31 22:28 ` [PATCH v5 06/12] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific Jim Quinlan
2024-07-31 22:28 ` [PATCH v5 07/12] PCI: brcmstb: Remove two unused constants from driver Jim Quinlan
2024-07-31 22:28 ` [PATCH v5 08/12] PCI: brcmstb: Don't conflate the reset rescal with phy ctrl Jim Quinlan
2024-08-07  3:05   ` Manivannan Sadhasivam
2024-07-31 22:28 ` [PATCH v5 09/12] PCI: brcmstb: Refactor for chips with many regular inbound windows Jim Quinlan
2024-08-01 16:39   ` Florian Fainelli
2024-08-06 22:58   ` Stanimir Varbanov
2024-08-07 14:04   ` Manivannan Sadhasivam
2024-08-07 14:16     ` Florian Fainelli [this message]
2024-08-07 15:03       ` Manivannan Sadhasivam
2024-08-12 19:14     ` Jim Quinlan
2024-07-31 22:28 ` [PATCH v5 10/12] PCI: brcmstb: Check return value of all reset_control_xxx calls Jim Quinlan
2024-08-07 14:11   ` Manivannan Sadhasivam
2024-08-12 18:20     ` Jim Quinlan
2024-07-31 22:28 ` [PATCH v5 11/12] PCI: brcmstb: Change field name from 'type' to 'soc_base' Jim Quinlan
2024-08-01 16:34   ` Florian Fainelli
2024-07-31 22:28 ` [PATCH v5 12/12] PCI: brcmstb: Enable 7712 SOCs Jim Quinlan
2024-08-07 14:12   ` Manivannan Sadhasivam

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