From: Charlie Jenkins <charlie@rivosinc.com>
To: "Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Clément Léger" <cleger@rivosinc.com>,
"Evan Green" <evan@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>
Cc: Palmer Dabbelt <palmer@rivosinc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org,
Charlie Jenkins <charlie@rivosinc.com>,
Jesse Taube <jesse@rivosinc.com>,
stable@vger.kernel.org,
Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v10 0/6] RISC-V: Detect and report speed of unaligned vector accesses
Date: Thu, 17 Oct 2024 12:00:17 -0700 [thread overview]
Message-ID: <20241017-jesse_unaligned_vector-v10-0-5b33500160f8@rivosinc.com> (raw)
Adds support for detecting and reporting the speed of unaligned vector
accesses on RISC-V CPUs. Adds vec_misaligned_speed key to the hwprobe
adds Zicclsm to cpufeature and fixes the check for scalar unaligned
emulated all CPUs. The vec_misaligned_speed key keeps the same format
as the scalar unaligned access speed key.
This set does not emulate unaligned vector accesses on CPUs that do not
support them. Only reports if userspace can run them and speed of
unaligned vector accesses if supported.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Signed-off-by: Jesse Taube <jesse@rivosinc.com>
---
Changes in V6:
Added ("RISC-V: Scalar unaligned access emulated on hotplug CPUs")
Changes in V8:
Dropped Zicclsm
s/RISCV_HWPROBE_VECTOR_MISALIGNED/RISCV_HWPROBE_MISALIGNED_VECTOR/g
to match RISCV_HWPROBE_MISALIGNED_SCALAR_*
Rebased onto palmer/fixes (32d5f7add080a936e28ab4142bfeea6b06999789)
Changes in V9:
Missed a RISCV_HWPROBE_VECTOR_MISALIGNED...
Changes in V10:
- I sent on behalf of Jesse
- Remove v0 from clobber args in inline asm and leave comment
---
Jesse Taube (6):
RISC-V: Check scalar unaligned access on all CPUs
RISC-V: Scalar unaligned access emulated on hotplug CPUs
RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED
RISC-V: Detect unaligned vector accesses supported
RISC-V: Report vector unaligned access speed hwprobe
RISC-V: hwprobe: Document unaligned vector perf key
Documentation/arch/riscv/hwprobe.rst | 16 +++
arch/riscv/Kconfig | 58 ++++++++++-
arch/riscv/include/asm/cpufeature.h | 10 +-
arch/riscv/include/asm/entry-common.h | 11 --
arch/riscv/include/asm/hwprobe.h | 2 +-
arch/riscv/include/asm/vector.h | 2 +
arch/riscv/include/uapi/asm/hwprobe.h | 5 +
arch/riscv/kernel/Makefile | 3 +-
arch/riscv/kernel/copy-unaligned.h | 5 +
arch/riscv/kernel/fpu.S | 4 +-
arch/riscv/kernel/sys_hwprobe.c | 41 ++++++++
arch/riscv/kernel/traps_misaligned.c | 139 +++++++++++++++++++++++--
arch/riscv/kernel/unaligned_access_speed.c | 156 +++++++++++++++++++++++++++--
arch/riscv/kernel/vec-copy-unaligned.S | 58 +++++++++++
arch/riscv/kernel/vector.c | 2 +-
15 files changed, 474 insertions(+), 38 deletions(-)
---
base-commit: 98f7e32f20d28ec452afb208f9cffc08448a2652
change-id: 20240920-jesse_unaligned_vector-7083fd28659c
--
- Charlie
next reply other threads:[~2024-10-17 19:00 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-17 19:00 Charlie Jenkins [this message]
2024-10-17 19:00 ` [PATCH v10 1/6] RISC-V: Check scalar unaligned access on all CPUs Charlie Jenkins
2024-10-17 19:00 ` [PATCH v10 2/6] RISC-V: Scalar unaligned access emulated on hotplug CPUs Charlie Jenkins
2024-10-17 19:00 ` [PATCH v10 3/6] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED Charlie Jenkins
2024-10-17 19:00 ` [PATCH v10 4/6] RISC-V: Detect unaligned vector accesses supported Charlie Jenkins
2024-10-18 23:48 ` Jesse T
2024-10-17 19:00 ` [PATCH v10 5/6] RISC-V: Report vector unaligned access speed hwprobe Charlie Jenkins
2024-10-17 19:00 ` [PATCH v10 6/6] RISC-V: hwprobe: Document unaligned vector perf key Charlie Jenkins
2024-10-24 17:50 ` [PATCH v10 0/6] RISC-V: Detect and report speed of unaligned vector accesses patchwork-bot+linux-riscv
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