[PATCH] KVM: selftests: Use data load to trigger LLC references/misses in Intel PMU

[PATCH] KVM: selftests: Use data load to trigger LLC references/misses in Intel PMU

[Sean Christopherson]

In the PMU counters test, add a data load in the measured loop and target
the data with CLFLUSH{OPT} in order to (try to) guarantee the loop
generates LLC misses and fills.  Per the SDM, some hardware prefetchers
are allowed to omit relevant PMU events, and Emerald Rapids (and possibly
Sapphire Rapids) appears to have gained an instruction prefetcher that
bypasses event counts.  E.g. the test will consistently fail on EMR CPUs,
but then pass with seemingly benign changes to the code.

  The event count includes speculation and cache line fills due to the
  first-level cache hardware prefetcher, but may exclude cache line fills
  due to other hardware-prefetchers.

Generate a data load as a last ditch effort to preserve the (minimal) test
coverage for LLC references and misses.

Cc: Maxim Levitsky <mlevitsk@redhat.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
---

As alluded to in the changelog, if the test continues to be flaky after this,
I'm inclined to remove the checks for LLC references/misses.

 tools/testing/selftests/kvm/x86_64/pmu_counters_test.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c
index 698cb36989db..b05e262f9011 100644
--- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c
+++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c
@@ -17,7 +17,7 @@
  * Number of instructions in each loop. 1 CLFLUSH/CLFLUSHOPT/NOP, 1 MFENCE,
  * 1 LOOP.
  */
-#define NUM_INSNS_PER_LOOP		3
+#define NUM_INSNS_PER_LOOP		4
 
 /*
  * Number of "extra" instructions that will be counted, i.e. the number of
@@ -162,13 +162,14 @@ do {										\
 			     "1:\n\t"						\
 			     clflush "\n\t"					\
 			     "mfence\n\t"					\
+			     "mov %[m], %%eax\n\t"				\
 			     FEP "loop 1b\n\t"					\
 			     FEP "mov %%edi, %%ecx\n\t"				\
 			     FEP "xor %%eax, %%eax\n\t"				\
 			     FEP "xor %%edx, %%edx\n\t"				\
 			     "wrmsr\n\t"					\
 			     :: "a"((uint32_t)_value), "d"(_value >> 32),	\
-				"c"(_msr), "D"(_msr)				\
+				"c"(_msr), "D"(_msr), [m]"m"(kvm_pmu_version)	\
 	);									\
 } while (0)
 
@@ -177,9 +178,9 @@ do {										\
 	wrmsr(pmc_msr, 0);							\
 										\
 	if (this_cpu_has(X86_FEATURE_CLFLUSHOPT))				\
-		GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflushopt .", FEP);	\
+		GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflushopt %[m]", FEP);	\
 	else if (this_cpu_has(X86_FEATURE_CLFLUSH))				\
-		GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflush .", FEP);	\
+		GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflush  %[m]", FEP);	\
 	else									\
 		GUEST_MEASURE_EVENT(_ctrl_msr, _value, "nop", FEP);		\
 										\

base-commit: 4d911c7abee56771b0219a9fbf0120d06bdc9c14
-- 
2.47.0.338.g60cca15819-goog

Re: [PATCH] KVM: selftests: Use data load to trigger LLC references/misses in Intel PMU

[Sean Christopherson]

On Wed, 27 Nov 2024 15:56:27 -0800, Sean Christopherson wrote:
> In the PMU counters test, add a data load in the measured loop and target
> the data with CLFLUSH{OPT} in order to (try to) guarantee the loop
> generates LLC misses and fills.  Per the SDM, some hardware prefetchers
> are allowed to omit relevant PMU events, and Emerald Rapids (and possibly
> Sapphire Rapids) appears to have gained an instruction prefetcher that
> bypasses event counts.  E.g. the test will consistently fail on EMR CPUs,
> but then pass with seemingly benign changes to the code.
> 
> [...]

Applied to kvm-x86 selftests, thanks!

[1/1] KVM: selftests: Use data load to trigger LLC references/misses in Intel PMU
      https://github.com/kvm-x86/linux/commit/7803339fa929

--
https://github.com/kvm-x86/linux/tree/next