From: David Laight <david.laight.linux@gmail.com>
To: Alexander Usyskin <alexander.usyskin@intel.com>
Cc: "Miquel Raynal" <miquel.raynal@bootlin.com>,
"Richard Weinberger" <richard@nod.at>,
"Vignesh Raghavendra" <vigneshr@ti.com>,
"Lucas De Marchi" <lucas.demarchi@intel.com>,
"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Jani Nikula" <jani.nikula@linux.intel.com>,
"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
"Tvrtko Ursulin" <tursulin@ursulin.net>,
"Karthik Poosa" <karthik.poosa@intel.com>,
"Reuven Abliyev" <reuven.abliyev@intel.com>,
"Oren Weil" <oren.jer.weil@intel.com>,
linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 06/11] mtd: intel-dg: align 64bit read and write
Date: Wed, 1 Jan 2025 16:41:19 +0000 [thread overview]
Message-ID: <20250101164119.000d2bd4@dsl-u17-10> (raw)
In-Reply-To: <20250101153925.865703-7-alexander.usyskin@intel.com>
On Wed, 1 Jan 2025 17:39:20 +0200
Alexander Usyskin <alexander.usyskin@intel.com> wrote:
> GSC NVM controller HW errors on quad access overlapping 1K border.
> Align 64bit read and write to avoid readq/writeq over 1K border.
>
> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/mtd/devices/mtd-intel-dg.c | 35 ++++++++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/drivers/mtd/devices/mtd-intel-dg.c b/drivers/mtd/devices/mtd-intel-dg.c
> index 76ef7198fff8..230bf444b7fe 100644
> --- a/drivers/mtd/devices/mtd-intel-dg.c
> +++ b/drivers/mtd/devices/mtd-intel-dg.c
> @@ -238,6 +238,24 @@ static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 region,
> len_s -= to_shift;
> }
>
> + if (!IS_ALIGNED(to, sizeof(u64)) &&
> + ((to ^ (to + len_s)) & GENMASK(31, 10))) {
I'm sure that should be (to + len_s - 1).
Using GENMASK(31, 10) completely fails to indicate what is being tested.
> + /*
> + * Workaround reads/writes across 1k-aligned addresses
> + * (start u32 before 1k, end u32 after)
> + * as this fails on hardware.
> + */
> + u32 data;
> +
> + memcpy(&data, &buf[0], sizeof(u32));
get_unaligned_u32()
> + idg_nvm_write32(nvm, to, data);
> + if (idg_nvm_error(nvm))
> + return -EIO;
> + buf += sizeof(u32);
> + to += sizeof(u32);
> + len_s -= sizeof(u32);
> + }
It isn't at all obvious why copying 4 bytes helps.
Indeed, if 'to' is 1023 and 'len_s' is 2 it goes terribly wrong.
David
> +
> len8 = ALIGN_DOWN(len_s, sizeof(u64));
> for (i = 0; i < len8; i += sizeof(u64)) {
> u64 data;
> @@ -295,6 +313,23 @@ static ssize_t idg_read(struct intel_dg_nvm *nvm, u8 region,
> from += from_shift;
> }
>
> + if (!IS_ALIGNED(from, sizeof(u64)) &&
> + ((from ^ (from + len_s)) & GENMASK(31, 10))) {
> + /*
> + * Workaround reads/writes across 1k-aligned addresses
> + * (start u32 before 1k, end u32 after)
> + * as this fails on hardware.
> + */
> + u32 data = idg_nvm_read32(nvm, from);
> +
> + if (idg_nvm_error(nvm))
> + return -EIO;
> + memcpy(&buf[0], &data, sizeof(data));
> + len_s -= sizeof(u32);
> + buf += sizeof(u32);
> + from += sizeof(u32);
> + }
> +
> len8 = ALIGN_DOWN(len_s, sizeof(u64));
> for (i = 0; i < len8; i += sizeof(u64)) {
> u64 data = idg_nvm_read64(nvm, from + i);
next prev parent reply other threads:[~2025-01-01 16:41 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-01 15:39 [PATCH v4 00/11] mtd: add driver for Intel discrete graphics Alexander Usyskin
2025-01-01 15:39 ` [PATCH v4 01/11] mtd: core: always create master device Alexander Usyskin
2025-01-06 10:46 ` Miquel Raynal
2025-01-06 11:03 ` Usyskin, Alexander
2025-01-14 14:05 ` Usyskin, Alexander
2025-01-15 19:22 ` Miquel Raynal
2025-01-15 22:30 ` Richard Weinberger
2025-01-16 6:54 ` Usyskin, Alexander
2025-01-17 22:27 ` Richard Weinberger
2025-01-19 7:30 ` Usyskin, Alexander
2025-01-01 15:39 ` [PATCH v4 02/11] mtd: add driver for intel graphics non-volatile memory device Alexander Usyskin
2025-01-02 10:32 ` Christophe JAILLET
2025-01-02 13:20 ` Usyskin, Alexander
2025-01-01 15:39 ` [PATCH v4 03/11] mtd: intel-dg: implement region enumeration Alexander Usyskin
2025-01-02 10:37 ` Christophe JAILLET
2025-01-02 10:49 ` Usyskin, Alexander
2025-01-01 15:39 ` [PATCH v4 04/11] mtd: intel-dg: implement access functions Alexander Usyskin
2025-01-01 15:39 ` [PATCH v4 05/11] mtd: intel-dg: register with mtd Alexander Usyskin
2025-01-01 15:39 ` [PATCH v4 06/11] mtd: intel-dg: align 64bit read and write Alexander Usyskin
2025-01-01 16:41 ` David Laight [this message]
2025-01-01 21:16 ` David Laight
2025-01-02 13:56 ` Usyskin, Alexander
2025-01-01 15:39 ` [PATCH v4 07/11] mtd: intel-dg: wake card on operations Alexander Usyskin
2025-01-29 21:51 ` Rodrigo Vivi
2025-02-11 5:32 ` Poosa, Karthik
2025-02-12 14:15 ` Usyskin, Alexander
2025-01-01 15:39 ` [PATCH v4 08/11] drm/i915/nvm: add nvm device for discrete graphics Alexander Usyskin
2025-01-01 15:39 ` [PATCH v4 09/11] drm/i915/nvm: add support for access mode Alexander Usyskin
2025-01-01 15:39 ` [PATCH v4 10/11] drm/xe/nvm: add on-die non-volatile memory device Alexander Usyskin
2025-01-29 21:36 ` Rodrigo Vivi
2025-01-01 15:39 ` [PATCH v4 11/11] drm/xe/nvm: add support for access mode Alexander Usyskin
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