From: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
To: <linux-kernel@vger.kernel.org>
Cc: <bp@alien8.de>, <tglx@linutronix.de>, <mingo@redhat.com>,
<dave.hansen@linux.intel.com>, <Thomas.Lendacky@amd.com>,
<nikunj@amd.com>, <Santosh.Shukla@amd.com>,
<Vasant.Hegde@amd.com>, <Suravee.Suthikulpanit@amd.com>,
<David.Kaplan@amd.com>, <x86@kernel.org>, <hpa@zytor.com>,
<peterz@infradead.org>, <seanjc@google.com>,
<pbonzini@redhat.com>, <kvm@vger.kernel.org>,
<kirill.shutemov@linux.intel.com>, <huibo.wang@amd.com>,
<naveen.rao@amd.com>, <francescolavra.fl@gmail.com>
Subject: [PATCH v5 17/20] x86/apic: Add kexec support for Secure AVIC
Date: Tue, 29 Apr 2025 11:40:01 +0530 [thread overview]
Message-ID: <20250429061004.205839-18-Neeraj.Upadhyay@amd.com> (raw)
In-Reply-To: <20250429061004.205839-1-Neeraj.Upadhyay@amd.com>
Add a apic->teardown() callback to disable Secure AVIC before
rebooting into the new kernel. This ensures that the new
kernel does not access the old APIC backing page which was
allocated by the previous kernel. Such accesses can happen
if there are any APIC accesses done during guest boot before
Secure AVIC driver probe is done by the new kernel (as Secure
AVIC would have remained enabled in the Secure AVIC control
msr).
Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
---
Changes since v4:
- No change.
arch/x86/coco/sev/core.c | 23 +++++++++++++++++++++++
arch/x86/include/asm/apic.h | 1 +
arch/x86/include/asm/sev.h | 2 ++
arch/x86/kernel/apic/apic.c | 3 +++
arch/x86/kernel/apic/x2apic_savic.c | 8 ++++++++
5 files changed, 37 insertions(+)
diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c
index 4cc8c4361b97..2dccfe411b14 100644
--- a/arch/x86/coco/sev/core.c
+++ b/arch/x86/coco/sev/core.c
@@ -1083,6 +1083,29 @@ enum es_result savic_register_gpa(u64 gpa)
return res;
}
+enum es_result savic_unregister_gpa(u64 *gpa)
+{
+ struct ghcb_state state;
+ struct es_em_ctxt ctxt;
+ enum es_result res;
+ struct ghcb *ghcb;
+
+ guard(irqsave)();
+
+ ghcb = __sev_get_ghcb(&state);
+ vc_ghcb_invalidate(ghcb);
+
+ ghcb_set_rax(ghcb, SVM_VMGEXIT_SAVIC_SELF_GPA);
+ res = sev_es_ghcb_hv_call(ghcb, &ctxt, SVM_VMGEXIT_SAVIC,
+ SVM_VMGEXIT_SAVIC_UNREGISTER_GPA, 0);
+ if (gpa && res == ES_OK)
+ *gpa = ghcb->save.rbx;
+
+ __sev_put_ghcb(&state);
+
+ return res;
+}
+
static void snp_register_per_cpu_ghcb(void)
{
struct sev_es_runtime_data *data;
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index c359cce60b22..37317d914c05 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -306,6 +306,7 @@ struct apic {
/* Probe, setup and smpboot functions */
int (*probe)(void);
void (*setup)(void);
+ void (*teardown)(void);
int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
void (*init_apic_ldr)(void);
diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h
index fab71d311135..feeff8418bb7 100644
--- a/arch/x86/include/asm/sev.h
+++ b/arch/x86/include/asm/sev.h
@@ -521,6 +521,7 @@ int snp_svsm_vtpm_send_command(u8 *buffer);
void __init snp_secure_tsc_prepare(void);
void __init snp_secure_tsc_init(void);
enum es_result savic_register_gpa(u64 gpa);
+enum es_result savic_unregister_gpa(u64 *gpa);
u64 savic_ghcb_msr_read(u32 reg);
void savic_ghcb_msr_write(u32 reg, u64 value);
@@ -574,6 +575,7 @@ static inline int snp_svsm_vtpm_send_command(u8 *buffer) { return -ENODEV; }
static inline void __init snp_secure_tsc_prepare(void) { }
static inline void __init snp_secure_tsc_init(void) { }
static inline enum es_result savic_register_gpa(u64 gpa) { return ES_UNSUPPORTED; }
+static inline enum es_result savic_unregister_gpa(u64 *gpa) { return ES_UNSUPPORTED; }
static inline void savic_ghcb_msr_write(u32 reg, u64 value) { }
static inline u64 savic_ghcb_msr_read(u32 reg) { return 0; }
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 88e4bddff5ba..e33a25ebd694 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1169,6 +1169,9 @@ void disable_local_APIC(void)
if (!apic_accessible())
return;
+ if (apic->teardown)
+ apic->teardown();
+
apic_soft_disable();
#ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2apic_savic.c
index c517abdae314..7ba296ba26e3 100644
--- a/arch/x86/kernel/apic/x2apic_savic.c
+++ b/arch/x86/kernel/apic/x2apic_savic.c
@@ -333,6 +333,13 @@ static void init_apic_page(void)
set_reg(APIC_ID, apic_id);
}
+static void savic_teardown(void)
+{
+ /* Disable Secure AVIC */
+ native_wrmsr(MSR_AMD64_SECURE_AVIC_CONTROL, 0, 0);
+ savic_unregister_gpa(NULL);
+}
+
static void savic_setup(void)
{
void *backing_page;
@@ -419,6 +426,7 @@ static struct apic apic_x2apic_savic __ro_after_init = {
.probe = savic_probe,
.acpi_madt_oem_check = savic_acpi_madt_oem_check,
.setup = savic_setup,
+ .teardown = savic_teardown,
.dest_mode_logical = false,
--
2.34.1
next prev parent reply other threads:[~2025-04-29 6:17 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-29 6:09 [PATCH v5 00/20] AMD: Add Secure AVIC Guest Support Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 01/20] KVM: x86: Move find_highest_vector() to a common header Neeraj Upadhyay
2025-04-29 14:42 ` Sean Christopherson
2025-04-29 18:09 ` Neeraj Upadhyay
2025-05-07 10:38 ` Borislav Petkov
2025-05-07 11:39 ` Neeraj Upadhyay
2025-06-10 6:32 ` Neeraj Upadhyay
2025-06-10 16:12 ` Sean Christopherson
2025-04-29 6:09 ` [PATCH v5 02/20] x86: apic: Move apic_update_irq_cfg() calls to apic_update_vector() Neeraj Upadhyay
2025-05-07 8:08 ` Thomas Gleixner
2025-04-29 6:09 ` [PATCH v5 03/20] x86/apic: Add new driver for Secure AVIC Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 04/20] x86/apic: Initialize Secure AVIC APIC backing page Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 05/20] x86/apic: Populate .read()/.write() callbacks of Secure AVIC driver Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 06/20] x86/apic: Initialize APIC ID for Secure AVIC Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 07/20] x86/apic: Add update_vector() callback for apic drivers Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 08/20] x86/apic: Add update_vector() callback for Secure AVIC Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 09/20] x86/apic: Add support to send IPI " Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 10/20] x86/apic: Support LAPIC timer " Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 11/20] x86/sev: Initialize VGIF for secondary VCPUs " Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 12/20] x86/apic: Add support to send NMI IPI " Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 13/20] x86/apic: Allow NMI to be injected from hypervisor " Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 14/20] x86/sev: Enable NMI support " Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 15/20] x86/apic: Read and write LVT* APIC registers from HV for SAVIC guests Neeraj Upadhyay
2025-04-29 6:10 ` [PATCH v5 16/20] x86/apic: Handle EOI writes for Secure AVIC guests Neeraj Upadhyay
2025-04-29 6:10 ` Neeraj Upadhyay [this message]
2025-04-29 6:10 ` [PATCH v5 18/20] x86/apic: Enable Secure AVIC in Control MSR Neeraj Upadhyay
2025-04-29 6:10 ` [PATCH v5 19/20] x86/sev: Prevent SECURE_AVIC_CONTROL MSR interception for Secure AVIC guests Neeraj Upadhyay
2025-04-29 6:10 ` [PATCH v5 20/20] x86/sev: Indicate SEV-SNP guest supports Secure AVIC Neeraj Upadhyay
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