From: Shubhi Garg <shgarg@nvidia.com>
To: <jonathanh@nvidia.com>, <lee@kernel.org>, <robh@kernel.org>,
<krzk@kernel.org>, <alexandre.belloni@bootlin.com>,
<thierry.reding@gmail.com>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: Shubhi Garg <shgarg@nvidia.com>
Subject: [PATCH V2 1/6] dt-bindings: mfd: add bindings for NVIDIA VRS PSEQ
Date: Tue, 20 May 2025 09:08:27 +0000 [thread overview]
Message-ID: <20250520090832.3564104-2-shgarg@nvidia.com> (raw)
In-Reply-To: <20250520090832.3564104-1-shgarg@nvidia.com>
Add bindings for NVIDIA VRS (Voltage Regulator Specification) power
sequencer device. NVIDIA VRS PSEQ controls ON/OFF and suspend/resume
power sequencing of system power rails on Tegra234 SoC. This device
also provides 32kHz RTC support with backup battery for system timing.
Signed-off-by: Shubhi Garg <shgarg@nvidia.com>
---
v2:
- fixed copyrights
- updated description with RTC information
- added status node in dtb node example
.../bindings/mfd/nvidia,vrs-pseq.yaml | 60 +++++++++++++++++++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml
diff --git a/Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml b/Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml
new file mode 100644
index 000000000000..676a29d4e1fa
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/nvidia,vrs-pseq.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Voltage Regulator Specification Power Sequencer
+
+maintainers:
+ - Shubhi Garg <shgarg@nvidia.com>
+
+description:
+ NVIDIA Voltage Regulator Specification Power Sequencer device controls
+ ON/OFF and suspend/resume power sequencing of system power rails for NVIDIA
+ SoCs. It provides 32kHz RTC clock support with backup battery for system
+ timing. The device also acts as an interrupt controller for managing
+ interrupts from the VRS power sequencer.
+
+properties:
+ compatible:
+ const: nvidia,vrs-pseq
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+ description:
+ The first cell is the IRQ number, the second cell is the trigger type.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - "#interrupt-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vrs@3c {
+ compatible = "nvidia,vrs-pseq";
+ reg = <0x3c>;
+ interrupt-parent = <&pmc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
--
2.43.0
next prev parent reply other threads:[~2025-05-20 9:08 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-20 9:08 [PATCH V2 0/6] Add NVIDIA VRS PSEQ support Shubhi Garg
2025-05-20 9:08 ` Shubhi Garg [this message]
2025-05-21 9:09 ` [PATCH V2 1/6] dt-bindings: mfd: add bindings for NVIDIA VRS PSEQ Krzysztof Kozlowski
2025-05-20 9:08 ` [PATCH V2 2/6] arm64: tegra: Add device-tree node for NVVRS PSEQ Shubhi Garg
2025-05-20 9:08 ` [PATCH V2 3/6] mfd: nvvrs: add NVVRS PSEQ MFD driver Shubhi Garg
2025-05-21 9:12 ` Krzysztof Kozlowski
2025-05-20 9:08 ` [PATCH V2 4/6] rtc: nvvrs: add NVIDIA VRS PSEQ RTC device driver Shubhi Garg
2025-05-21 9:14 ` Krzysztof Kozlowski
2025-06-02 14:47 ` Jon Hunter
2025-05-20 9:08 ` [PATCH V2 5/6] arm64: defconfig: enable NVIDIA VRS PSEQ Shubhi Garg
2025-05-20 9:12 ` Krzysztof Kozlowski
2025-05-20 9:08 ` [PATCH V2 6/6] MAINTAINERS: Add NVIDIA VRS PSEQ driver entry Shubhi Garg
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