From: Shubhi Garg <shgarg@nvidia.com>
To: <jonathanh@nvidia.com>, <lee@kernel.org>, <robh@kernel.org>,
<krzk@kernel.org>, <alexandre.belloni@bootlin.com>,
<thierry.reding@gmail.com>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: Shubhi Garg <shgarg@nvidia.com>
Subject: [PATCH V2 2/6] arm64: tegra: Add device-tree node for NVVRS PSEQ
Date: Tue, 20 May 2025 09:08:28 +0000 [thread overview]
Message-ID: <20250520090832.3564104-3-shgarg@nvidia.com> (raw)
In-Reply-To: <20250520090832.3564104-1-shgarg@nvidia.com>
Add NVIDIA VRS Power Sequencer device tree node for Tegra234 P3701 and
P3767 platforms. Assign VRS RTC as primary RTC (rtc0).
Signed-off-by: Shubhi Garg <shgarg@nvidia.com>
---
v2:
- added alias to assign VRS RTC to rtc0
- removed status node from VRS DTB node
arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi | 11 +++++++++++
arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi | 15 +++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi
index 9086a0d010e5..b36df0c0c498 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi
@@ -8,6 +8,7 @@ / {
aliases {
mmc0 = "/bus@0/mmc@3460000";
mmc1 = "/bus@0/mmc@3400000";
+ rtc0 = "/bpmp/i2c/vrs@3c";
};
bus@0 {
@@ -170,6 +171,16 @@ bpmp {
i2c {
status = "okay";
+ vrs@3c {
+ compatible = "nvidia,vrs-pseq";
+ reg = <0x3c>;
+ interrupt-parent = <&pmc>;
+ /* VRS Wake ID is 24 */
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
thermal-sensor@4c {
compatible = "ti,tmp451";
status = "okay";
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi
index 84db7132e8fc..feae098033fc 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi
@@ -7,6 +7,7 @@ / {
aliases {
mmc0 = "/bus@0/mmc@3400000";
+ rtc0 = "/bpmp/i2c/vrs@3c";
};
bus@0 {
@@ -121,6 +122,20 @@ pmc@c360000 {
};
};
+ bpmp {
+ i2c {
+ vrs@3c {
+ compatible = "nvidia,vrs-pseq";
+ reg = <0x3c>;
+ interrupt-parent = <&pmc>;
+ /* VRS Wake ID is 24 */
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+ };
+
vdd_5v0_sys: regulator-vdd-5v0-sys {
compatible = "regulator-fixed";
regulator-name = "VDD_5V0_SYS";
--
2.43.0
next prev parent reply other threads:[~2025-05-20 9:08 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-20 9:08 [PATCH V2 0/6] Add NVIDIA VRS PSEQ support Shubhi Garg
2025-05-20 9:08 ` [PATCH V2 1/6] dt-bindings: mfd: add bindings for NVIDIA VRS PSEQ Shubhi Garg
2025-05-21 9:09 ` Krzysztof Kozlowski
2025-05-20 9:08 ` Shubhi Garg [this message]
2025-05-20 9:08 ` [PATCH V2 3/6] mfd: nvvrs: add NVVRS PSEQ MFD driver Shubhi Garg
2025-05-21 9:12 ` Krzysztof Kozlowski
2025-05-20 9:08 ` [PATCH V2 4/6] rtc: nvvrs: add NVIDIA VRS PSEQ RTC device driver Shubhi Garg
2025-05-21 9:14 ` Krzysztof Kozlowski
2025-06-02 14:47 ` Jon Hunter
2025-05-20 9:08 ` [PATCH V2 5/6] arm64: defconfig: enable NVIDIA VRS PSEQ Shubhi Garg
2025-05-20 9:12 ` Krzysztof Kozlowski
2025-05-20 9:08 ` [PATCH V2 6/6] MAINTAINERS: Add NVIDIA VRS PSEQ driver entry Shubhi Garg
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