From: Leo Yan <leo.yan@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
Anshuman Khandual <anshuman.khandual@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Leo Yan <leo.yan@arm.com>
Subject: [PATCH v4 01/10] coresight: tmc: Support atclk
Date: Fri, 27 Jun 2025 12:51:47 +0100 [thread overview]
Message-ID: <20250627-arm_cs_fix_clock_v4-v4-1-0ce0009c38f8@arm.com> (raw)
In-Reply-To: <20250627-arm_cs_fix_clock_v4-v4-0-0ce0009c38f8@arm.com>
The atclk is an optional clock for the CoreSight TMC, but the driver
misses to initialize it. In most cases, TMC shares the atclk clock with
other CoreSight components. Since these components enable the clock
before the TMC device is initialized, the TMC continues properly,
which is why we don’t observe any lockup issues.
This change enables atclk in probe of the TMC driver. Given the clock
is optional, it is possible to return NULL if the clock does not exist.
IS_ERR() is tolerant for this case.
Dynamically disable and enable atclk during suspend and resume. The
clock pointers will never be error values if the driver has successfully
probed, and the case of a NULL pointer case will be handled by the clock
core layer. The driver data is always valid after probe. Therefore,
remove the related checks. Also in the resume flow adds error handling.
Fixes: bc4bf7fe98da ("coresight-tmc: add CoreSight TMC driver")
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
---
drivers/hwtracing/coresight/coresight-tmc-core.c | 22 +++++++++++++++++-----
drivers/hwtracing/coresight/coresight-tmc.h | 2 ++
2 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
index 88afb16bb6bec395ba535155228d176250f38625..0b5e7635a084d226619e69189a2ecbaff754ec43 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-core.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
@@ -789,6 +789,10 @@ static int __tmc_probe(struct device *dev, struct resource *res)
struct coresight_desc desc = { 0 };
struct coresight_dev_list *dev_list = NULL;
+ drvdata->atclk = devm_clk_get_optional_enabled(dev, "atclk");
+ if (IS_ERR(drvdata->atclk))
+ return PTR_ERR(drvdata->atclk);
+
ret = -ENOMEM;
/* Validity for the resource is already checked by the AMBA core */
@@ -1020,18 +1024,26 @@ static int tmc_runtime_suspend(struct device *dev)
{
struct tmc_drvdata *drvdata = dev_get_drvdata(dev);
- if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
- clk_disable_unprepare(drvdata->pclk);
+ clk_disable_unprepare(drvdata->atclk);
+ clk_disable_unprepare(drvdata->pclk);
+
return 0;
}
static int tmc_runtime_resume(struct device *dev)
{
struct tmc_drvdata *drvdata = dev_get_drvdata(dev);
+ int ret;
- if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
- clk_prepare_enable(drvdata->pclk);
- return 0;
+ ret = clk_prepare_enable(drvdata->pclk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(drvdata->atclk);
+ if (ret)
+ clk_disable_unprepare(drvdata->pclk);
+
+ return ret;
}
#endif
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 6541a27a018e6c3da8685e2e1c93b228d44e66fc..cbb4ba43915855a8acbb9205167e87185c9a8c6c 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -210,6 +210,7 @@ struct tmc_resrv_buf {
/**
* struct tmc_drvdata - specifics associated to an TMC component
+ * @atclk: optional clock for the core parts of the TMC.
* @pclk: APB clock if present, otherwise NULL
* @base: memory mapped base address for this component.
* @csdev: component vitals needed by the framework.
@@ -244,6 +245,7 @@ struct tmc_resrv_buf {
* Used by ETR/ETF.
*/
struct tmc_drvdata {
+ struct clk *atclk;
struct clk *pclk;
void __iomem *base;
struct coresight_device *csdev;
--
2.34.1
next prev parent reply other threads:[~2025-06-27 11:52 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-27 11:51 [PATCH v4 00/10] coresight: Fix and improve clock usage Leo Yan
2025-06-27 11:51 ` Leo Yan [this message]
2025-06-27 13:27 ` [PATCH v4 01/10] coresight: tmc: Support atclk Yeoreum Yun
2025-06-27 13:49 ` Yeoreum Yun
2025-06-27 13:59 ` Leo Yan
2025-06-27 11:51 ` [PATCH v4 02/10] coresight: catu: " Leo Yan
2025-06-27 11:51 ` [PATCH v4 03/10] coresight: etm4x: " Leo Yan
2025-06-27 11:51 ` [PATCH v4 04/10] coresight: Appropriately disable programming clocks Leo Yan
2025-07-21 9:15 ` Suzuki K Poulose
2025-07-21 10:48 ` Leo Yan
2025-07-21 11:40 ` Suzuki K Poulose
2025-07-21 13:59 ` Leo Yan
2025-07-22 13:25 ` Suzuki K Poulose
[not found] ` <daece566-2cca-71dd-d21a-80dadad2c71b@huawei.com>
2025-07-23 10:23 ` Leo Yan
2025-06-27 11:51 ` [PATCH v4 05/10] coresight: Appropriately disable trace bus clocks Leo Yan
2025-07-21 9:20 ` Suzuki K Poulose
2025-07-21 13:42 ` Leo Yan
2025-06-27 11:51 ` [PATCH v4 06/10] coresight: Avoid enable programming clock duplicately Leo Yan
2025-06-27 11:51 ` [PATCH v4 07/10] coresight: Consolidate clock enabling Leo Yan
2025-06-30 5:37 ` Anshuman Khandual
2025-06-27 11:51 ` [PATCH v4 08/10] coresight: Refactor driver data allocation Leo Yan
2025-06-30 5:47 ` Anshuman Khandual
2025-06-27 11:51 ` [PATCH v4 09/10] coresight: Make clock sequence consistent Leo Yan
2025-06-27 11:51 ` [PATCH v4 10/10] coresight: Refactor runtime PM Leo Yan
2025-06-27 13:50 ` [PATCH v4 00/10] coresight: Fix and improve clock usage Yeoreum Yun
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