From: Leo Yan <leo.yan@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
Anshuman Khandual <anshuman.khandual@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Leo Yan <leo.yan@arm.com>
Subject: [PATCH v4 09/10] coresight: Make clock sequence consistent
Date: Fri, 27 Jun 2025 12:51:55 +0100 [thread overview]
Message-ID: <20250627-arm_cs_fix_clock_v4-v4-9-0ce0009c38f8@arm.com> (raw)
In-Reply-To: <20250627-arm_cs_fix_clock_v4-v4-0-0ce0009c38f8@arm.com>
Since atclk is enabled after pclk during the probe phase, this commit
maintains the same sequence for the runtime resume flow.
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
---
drivers/hwtracing/coresight/coresight-funnel.c | 6 +++---
drivers/hwtracing/coresight/coresight-replicator.c | 6 +++---
drivers/hwtracing/coresight/coresight-stm.c | 6 +++---
drivers/hwtracing/coresight/coresight-tpiu.c | 6 +++---
4 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c
index 02e0dc678a32c3b1f32fc955bf8871142e3412e1..9dcfc5ce8845d9e01bb956dddab0d64de51ec397 100644
--- a/drivers/hwtracing/coresight/coresight-funnel.c
+++ b/drivers/hwtracing/coresight/coresight-funnel.c
@@ -297,11 +297,11 @@ static int funnel_runtime_resume(struct device *dev)
{
struct funnel_drvdata *drvdata = dev_get_drvdata(dev);
- if (drvdata && !IS_ERR(drvdata->atclk))
- clk_prepare_enable(drvdata->atclk);
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
clk_prepare_enable(drvdata->pclk);
+
+ if (drvdata && !IS_ERR(drvdata->atclk))
+ clk_prepare_enable(drvdata->atclk);
return 0;
}
#endif
diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c
index f1bbd12e63e0c130f945d8df34fb2334bd21336f..e53095603b0c0419bc96a66b23d15bb54e75e634 100644
--- a/drivers/hwtracing/coresight/coresight-replicator.c
+++ b/drivers/hwtracing/coresight/coresight-replicator.c
@@ -335,11 +335,11 @@ static int replicator_runtime_resume(struct device *dev)
{
struct replicator_drvdata *drvdata = dev_get_drvdata(dev);
- if (drvdata && !IS_ERR(drvdata->atclk))
- clk_prepare_enable(drvdata->atclk);
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
clk_prepare_enable(drvdata->pclk);
+
+ if (drvdata && !IS_ERR(drvdata->atclk))
+ clk_prepare_enable(drvdata->atclk);
return 0;
}
#endif
diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c
index a931282ec0eaf1b2a5db8ccc8f21789441cd634d..ed68d8280b1945f38d1294a5b5f557a614c90c94 100644
--- a/drivers/hwtracing/coresight/coresight-stm.c
+++ b/drivers/hwtracing/coresight/coresight-stm.c
@@ -969,11 +969,11 @@ static int stm_runtime_resume(struct device *dev)
{
struct stm_drvdata *drvdata = dev_get_drvdata(dev);
- if (drvdata && !IS_ERR(drvdata->atclk))
- clk_prepare_enable(drvdata->atclk);
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
clk_prepare_enable(drvdata->pclk);
+
+ if (drvdata && !IS_ERR(drvdata->atclk))
+ clk_prepare_enable(drvdata->atclk);
return 0;
}
#endif
diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c
index 5e47d761e1c4e99072eeb492c1eac7dd4285a591..1c5c2a82971490888c45508c68b516ab7dbf3eeb 100644
--- a/drivers/hwtracing/coresight/coresight-tpiu.c
+++ b/drivers/hwtracing/coresight/coresight-tpiu.c
@@ -218,11 +218,11 @@ static int tpiu_runtime_resume(struct device *dev)
{
struct tpiu_drvdata *drvdata = dev_get_drvdata(dev);
- if (drvdata && !IS_ERR(drvdata->atclk))
- clk_prepare_enable(drvdata->atclk);
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
clk_prepare_enable(drvdata->pclk);
+
+ if (drvdata && !IS_ERR(drvdata->atclk))
+ clk_prepare_enable(drvdata->atclk);
return 0;
}
#endif
--
2.34.1
next prev parent reply other threads:[~2025-06-27 11:52 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-27 11:51 [PATCH v4 00/10] coresight: Fix and improve clock usage Leo Yan
2025-06-27 11:51 ` [PATCH v4 01/10] coresight: tmc: Support atclk Leo Yan
2025-06-27 13:27 ` Yeoreum Yun
2025-06-27 13:49 ` Yeoreum Yun
2025-06-27 13:59 ` Leo Yan
2025-06-27 11:51 ` [PATCH v4 02/10] coresight: catu: " Leo Yan
2025-06-27 11:51 ` [PATCH v4 03/10] coresight: etm4x: " Leo Yan
2025-06-27 11:51 ` [PATCH v4 04/10] coresight: Appropriately disable programming clocks Leo Yan
2025-07-21 9:15 ` Suzuki K Poulose
2025-07-21 10:48 ` Leo Yan
2025-07-21 11:40 ` Suzuki K Poulose
2025-07-21 13:59 ` Leo Yan
2025-07-22 13:25 ` Suzuki K Poulose
[not found] ` <daece566-2cca-71dd-d21a-80dadad2c71b@huawei.com>
2025-07-23 10:23 ` Leo Yan
2025-06-27 11:51 ` [PATCH v4 05/10] coresight: Appropriately disable trace bus clocks Leo Yan
2025-07-21 9:20 ` Suzuki K Poulose
2025-07-21 13:42 ` Leo Yan
2025-06-27 11:51 ` [PATCH v4 06/10] coresight: Avoid enable programming clock duplicately Leo Yan
2025-06-27 11:51 ` [PATCH v4 07/10] coresight: Consolidate clock enabling Leo Yan
2025-06-30 5:37 ` Anshuman Khandual
2025-06-27 11:51 ` [PATCH v4 08/10] coresight: Refactor driver data allocation Leo Yan
2025-06-30 5:47 ` Anshuman Khandual
2025-06-27 11:51 ` Leo Yan [this message]
2025-06-27 11:51 ` [PATCH v4 10/10] coresight: Refactor runtime PM Leo Yan
2025-06-27 13:50 ` [PATCH v4 00/10] coresight: Fix and improve clock usage Yeoreum Yun
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