* [PATCH] EDAC/amd64: Add support for AMD family 1Ah-based newer models
@ 2025-07-22 19:27 Avadhut Naik
2025-07-24 13:24 ` Yazen Ghannam
0 siblings, 1 reply; 3+ messages in thread
From: Avadhut Naik @ 2025-07-22 19:27 UTC (permalink / raw)
To: linux-edac; +Cc: bp, yazen.ghannam, linux-kernel, avadnaik
Add support for family 1Ah-based models 50h-57h, 90h-9Fh, A0h-AFh, and
C0h-C7h.
Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
---
drivers/edac/amd64_edac.c | 20 ++++++++++++++++++++
drivers/edac/amd64_edac.h | 2 +-
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 07f1e9dc1ca7..06ae6750ca14 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3923,6 +3923,26 @@ static int per_family_init(struct amd64_pvt *pvt)
pvt->ctl_name = "F1Ah_M40h";
pvt->flags.zn_regs_v2 = 1;
break;
+ case 0x50 ... 0x57:
+ pvt->ctl_name = "F1Ah_M50h";
+ pvt->max_mcs = 16;
+ pvt->flags.zn_regs_v2 = 1;
+ break;
+ case 0x90 ... 0x9f:
+ pvt->ctl_name = "F1Ah_M90h";
+ pvt->max_mcs = 8;
+ pvt->flags.zn_regs_v2 = 1;
+ break;
+ case 0xa0 ... 0xaf:
+ pvt->ctl_name = "F1Ah_MA0h";
+ pvt->max_mcs = 8;
+ pvt->flags.zn_regs_v2 = 1;
+ break;
+ case 0xc0 ... 0xc7:
+ pvt->ctl_name = "F1Ah_MC0h";
+ pvt->max_mcs = 16;
+ pvt->flags.zn_regs_v2 = 1;
+ break;
}
break;
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 17228d07de4c..d70b8a8d0b09 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -96,7 +96,7 @@
/* Hardware limit on ChipSelect rows per MC and processors per system */
#define NUM_CHIPSELECTS 8
#define DRAM_RANGES 8
-#define NUM_CONTROLLERS 12
+#define NUM_CONTROLLERS 16
#define ON true
#define OFF false
base-commit: 1fb0ddddf5d139089675b86702933cbca992b4d4
--
2.43.0
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] EDAC/amd64: Add support for AMD family 1Ah-based newer models
2025-07-22 19:27 [PATCH] EDAC/amd64: Add support for AMD family 1Ah-based newer models Avadhut Naik
@ 2025-07-24 13:24 ` Yazen Ghannam
2025-07-24 18:42 ` Naik, Avadhut
0 siblings, 1 reply; 3+ messages in thread
From: Yazen Ghannam @ 2025-07-24 13:24 UTC (permalink / raw)
To: Avadhut Naik; +Cc: linux-edac, bp, linux-kernel, avadnaik
On Tue, Jul 22, 2025 at 07:27:31PM +0000, Avadhut Naik wrote:
> Add support for family 1Ah-based models 50h-57h, 90h-9Fh, A0h-AFh, and
> C0h-C7h.
>
> Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
> ---
> drivers/edac/amd64_edac.c | 20 ++++++++++++++++++++
> drivers/edac/amd64_edac.h | 2 +-
> 2 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
> index 07f1e9dc1ca7..06ae6750ca14 100644
> --- a/drivers/edac/amd64_edac.c
> +++ b/drivers/edac/amd64_edac.c
> @@ -3923,6 +3923,26 @@ static int per_family_init(struct amd64_pvt *pvt)
> pvt->ctl_name = "F1Ah_M40h";
> pvt->flags.zn_regs_v2 = 1;
> break;
> + case 0x50 ... 0x57:
> + pvt->ctl_name = "F1Ah_M50h";
> + pvt->max_mcs = 16;
> + pvt->flags.zn_regs_v2 = 1;
> + break;
> + case 0x90 ... 0x9f:
> + pvt->ctl_name = "F1Ah_M90h";
> + pvt->max_mcs = 8;
> + pvt->flags.zn_regs_v2 = 1;
> + break;
> + case 0xa0 ... 0xaf:
> + pvt->ctl_name = "F1Ah_MA0h";
> + pvt->max_mcs = 8;
> + pvt->flags.zn_regs_v2 = 1;
> + break;
> + case 0xc0 ... 0xc7:
> + pvt->ctl_name = "F1Ah_MC0h";
> + pvt->max_mcs = 16;
These last three groups have extra tabs. Please align them with the
other lines.
> + pvt->flags.zn_regs_v2 = 1;
> + break;
> }
> break;
>
> diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
> index 17228d07de4c..d70b8a8d0b09 100644
> --- a/drivers/edac/amd64_edac.h
> +++ b/drivers/edac/amd64_edac.h
> @@ -96,7 +96,7 @@
> /* Hardware limit on ChipSelect rows per MC and processors per system */
> #define NUM_CHIPSELECTS 8
> #define DRAM_RANGES 8
> -#define NUM_CONTROLLERS 12
> +#define NUM_CONTROLLERS 16
The "legacy sysfs interface" needs an update too. I don't know if folks
still actively use it, but it hasn't been totally removed yet.
See this commit as an example:
25836ce1df82 ("EDAC/mc_sysfs: Increase legacy channel support to 12")
Thanks,
Yazen
^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH] EDAC/amd64: Add support for AMD family 1Ah-based newer models
2025-07-24 13:24 ` Yazen Ghannam
@ 2025-07-24 18:42 ` Naik, Avadhut
0 siblings, 0 replies; 3+ messages in thread
From: Naik, Avadhut @ 2025-07-24 18:42 UTC (permalink / raw)
To: Yazen Ghannam; +Cc: linux-edac, bp, linux-kernel, Avadhut Naik
On 7/24/2025 08:24, Yazen Ghannam wrote:
> On Tue, Jul 22, 2025 at 07:27:31PM +0000, Avadhut Naik wrote:
>> Add support for family 1Ah-based models 50h-57h, 90h-9Fh, A0h-AFh, and
>> C0h-C7h.
>>
>> Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
>> ---
>> drivers/edac/amd64_edac.c | 20 ++++++++++++++++++++
>> drivers/edac/amd64_edac.h | 2 +-
>> 2 files changed, 21 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
>> index 07f1e9dc1ca7..06ae6750ca14 100644
>> --- a/drivers/edac/amd64_edac.c
>> +++ b/drivers/edac/amd64_edac.c
>> @@ -3923,6 +3923,26 @@ static int per_family_init(struct amd64_pvt *pvt)
>> pvt->ctl_name = "F1Ah_M40h";
>> pvt->flags.zn_regs_v2 = 1;
>> break;
>> + case 0x50 ... 0x57:
>> + pvt->ctl_name = "F1Ah_M50h";
>> + pvt->max_mcs = 16;
>> + pvt->flags.zn_regs_v2 = 1;
>> + break;
>> + case 0x90 ... 0x9f:
>> + pvt->ctl_name = "F1Ah_M90h";
>> + pvt->max_mcs = 8;
>> + pvt->flags.zn_regs_v2 = 1;
>> + break;
>> + case 0xa0 ... 0xaf:
>> + pvt->ctl_name = "F1Ah_MA0h";
>> + pvt->max_mcs = 8;
>> + pvt->flags.zn_regs_v2 = 1;
>> + break;
>> + case 0xc0 ... 0xc7:
>> + pvt->ctl_name = "F1Ah_MC0h";
>> + pvt->max_mcs = 16;
>
> These last three groups have extra tabs. Please align them with the
> other lines.
>
Yes, will do!
>> + pvt->flags.zn_regs_v2 = 1;
>> + break;
>> }
>> break;
>>
>> diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
>> index 17228d07de4c..d70b8a8d0b09 100644
>> --- a/drivers/edac/amd64_edac.h
>> +++ b/drivers/edac/amd64_edac.h
>> @@ -96,7 +96,7 @@
>> /* Hardware limit on ChipSelect rows per MC and processors per system */
>> #define NUM_CHIPSELECTS 8
>> #define DRAM_RANGES 8
>> -#define NUM_CONTROLLERS 12
>> +#define NUM_CONTROLLERS 16
>
> The "legacy sysfs interface" needs an update too. I don't know if folks
> still actively use it, but it hasn't been totally removed yet.
>
> See this commit as an example:
> 25836ce1df82 ("EDAC/mc_sysfs: Increase legacy channel support to 12")
>
Okay. Will update the sysfs interface too!
> Thanks,
> Yazen
--
Thanks,
Avadhut Naik
^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-07-22 19:27 [PATCH] EDAC/amd64: Add support for AMD family 1Ah-based newer models Avadhut Naik
2025-07-24 13:24 ` Yazen Ghannam
2025-07-24 18:42 ` Naik, Avadhut
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