From: K Prateek Nayak <kprateek.nayak@amd.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>, <x86@kernel.org>
Cc: Naveen rao <naveen.rao@amd.com>,
Sairaj Kodilkar <sarunkod@amd.com>,
"H. Peter Anvin" <hpa@zytor.com>,
"Peter Zijlstra (Intel)" <peterz@infradead.org>,
"Xin Li (Intel)" <xin@zytor.com>,
Pawan Gupta <pawan.kumar.gupta@linux.intel.com>,
<linux-kernel@vger.kernel.org>, <kvm@vger.kernel.org>,
Mario Limonciello <mario.limonciello@amd.com>,
"Gautham R. Shenoy" <gautham.shenoy@amd.com>,
Babu Moger <babu.moger@amd.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
K Prateek Nayak <kprateek.nayak@amd.com>
Subject: [PATCH v3 1/4] x86/msr-index: Define AMD64_CPUID_FN_EXT MSR
Date: Mon, 18 Aug 2025 06:04:32 +0000 [thread overview]
Message-ID: <20250818060435.2452-2-kprateek.nayak@amd.com> (raw)
In-Reply-To: <20250818060435.2452-1-kprateek.nayak@amd.com>
Explicitly define the AMD64_CPUID_FN_EXT MSR used to toggle the extended
features. Also define and use the bits necessary an old TOPOEXT fixup on
AMD Family 0x15 processors.
No functional changes intended.
Signed-off-by: K Prateek Nayak <kprateek.nayak@amd.com>
---
Changelog v2..v3:
o New patch.
Note: The definition of MSR_AMD64_CPUID_FN_EXT_TOPOEXT_ENABLED crosses
the 100 column limit and results in a checkpatch warning.
msr-index.h contains a couple more examples where the definitions with
very explicit naming crosses 100 columns and I've decided to retain the
same despite the warning.
If this needs to be changed, please let me know and I'll address it in
the next version.
---
arch/x86/include/asm/msr-index.h | 5 +++++
arch/x86/kernel/cpu/topology_amd.c | 7 ++++---
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 2d5595bdfa27..7931f9b3250b 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -630,6 +630,11 @@
#define MSR_AMD_PPIN 0xc00102f1
#define MSR_AMD64_CPUID_FN_7 0xc0011002
#define MSR_AMD64_CPUID_FN_1 0xc0011004
+
+#define MSR_AMD64_CPUID_FN_EXT 0xc0011005
+#define MSR_AMD64_CPUID_FN_EXT_TOPOEXT_ENABLED_BIT 54
+#define MSR_AMD64_CPUID_FN_EXT_TOPOEXT_ENABLED BIT_ULL(MSR_AMD64_CPUID_FN_EXT_TOPOEXT_ENABLED_BIT)
+
#define MSR_AMD64_LS_CFG 0xc0011020
#define MSR_AMD64_DC_CFG 0xc0011022
#define MSR_AMD64_TW_CFG 0xc0011023
diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topology_amd.c
index 843b1655ab45..bb00dc6433eb 100644
--- a/arch/x86/kernel/cpu/topology_amd.c
+++ b/arch/x86/kernel/cpu/topology_amd.c
@@ -158,11 +158,12 @@ static void topoext_fixup(struct topo_scan *tscan)
c->x86 != 0x15 || c->x86_model < 0x10 || c->x86_model > 0x6f)
return;
- if (msr_set_bit(0xc0011005, 54) <= 0)
+ if (msr_set_bit(MSR_AMD64_CPUID_FN_EXT,
+ MSR_AMD64_CPUID_FN_EXT_TOPOEXT_ENABLED_BIT) <= 0)
return;
- rdmsrq(0xc0011005, msrval);
- if (msrval & BIT_64(54)) {
+ rdmsrq(MSR_AMD64_CPUID_FN_EXT, msrval);
+ if (msrval & MSR_AMD64_CPUID_FN_EXT_TOPOEXT_ENABLED) {
set_cpu_cap(c, X86_FEATURE_TOPOEXT);
pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
}
--
2.34.1
next prev parent reply other threads:[~2025-08-18 6:05 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-18 6:04 [PATCH v3 0/4] x86/cpu/topology: Work around the nuances of virtualization on AMD/Hygon K Prateek Nayak
2025-08-18 6:04 ` K Prateek Nayak [this message]
2025-08-18 6:04 ` [PATCH v3 2/4] x86/cpu/topology: Use initial APICID from XTOPOEXT on AMD/HYGON K Prateek Nayak
2025-08-18 6:04 ` [PATCH v3 3/4] x86/cpu/topology: Always try cpu_parse_topology_ext() on AMD/Hygon K Prateek Nayak
2025-08-18 6:04 ` [PATCH v3 4/4] x86/cpu/topology: Check for X86_FEATURE_XTOPOLOGY instead of passing has_topoext K Prateek Nayak
2025-08-24 13:38 ` Thomas Gleixner
2025-08-24 14:55 ` Thomas Gleixner
2025-08-25 4:05 ` K Prateek Nayak
2025-08-19 11:34 ` [PATCH v3 0/4] x86/cpu/topology: Work around the nuances of virtualization on AMD/Hygon Borislav Petkov
2025-08-19 14:28 ` K Prateek Nayak
2025-08-19 21:24 ` Borislav Petkov
2025-08-20 8:11 ` Naveen N Rao
2025-08-20 8:59 ` Borislav Petkov
2025-08-20 9:12 ` K Prateek Nayak
2025-08-20 9:28 ` Borislav Petkov
2025-08-20 9:59 ` Gautham R. Shenoy
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250818060435.2452-2-kprateek.nayak@amd.com \
--to=kprateek.nayak@amd.com \
--cc=babu.moger@amd.com \
--cc=bp@alien8.de \
--cc=dave.hansen@linux.intel.com \
--cc=gautham.shenoy@amd.com \
--cc=hpa@zytor.com \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mario.limonciello@amd.com \
--cc=mingo@redhat.com \
--cc=naveen.rao@amd.com \
--cc=pawan.kumar.gupta@linux.intel.com \
--cc=pbonzini@redhat.com \
--cc=peterz@infradead.org \
--cc=sarunkod@amd.com \
--cc=seanjc@google.com \
--cc=suravee.suthikulpanit@amd.com \
--cc=tglx@linutronix.de \
--cc=x86@kernel.org \
--cc=xin@zytor.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®