From: Terry Bowman <terry.bowman@amd.com>
To: <dave@stgolabs.net>, <jonathan.cameron@huawei.com>,
<dave.jiang@intel.com>, <alison.schofield@intel.com>,
<dan.j.williams@intel.com>, <bhelgaas@google.com>,
<shiju.jose@huawei.com>, <ming.li@zohomail.com>,
<Smita.KoralahalliChannabasappa@amd.com>, <rrichter@amd.com>,
<dan.carpenter@linaro.org>, <PradeepVineshReddy.Kodamati@amd.com>,
<lukas@wunner.de>, <Benjamin.Cheatham@amd.com>,
<sathyanarayanan.kuppuswamy@linux.intel.com>,
<linux-cxl@vger.kernel.org>, <alucerop@amd.com>,
<ira.weiny@intel.com>
Cc: <linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>
Subject: [PATCH v11 23/23] CXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup
Date: Tue, 26 Aug 2025 20:35:38 -0500 [thread overview]
Message-ID: <20250827013539.903682-24-terry.bowman@amd.com> (raw)
In-Reply-To: <20250827013539.903682-1-terry.bowman@amd.com>
During CXL device cleanup the CXL PCIe Port device interrupts remain
enabled. This potentially allows unnecessary interrupt processing on
behalf of the CXL errors while the device is destroyed.
Disable CXL protocol errors by setting the CXL devices' AER mask register.
Introduce pci_aer_mask_internal_errors() similar to pci_aer_unmask_internal_errors().
Introduce cxl_mask_proto_interrupts() to call pci_aer_mask_internal_errors().
Add calls to cxl_mask_proto_interrupts() within CXL Port teardown for CXL
Root Ports, CXL Downstream Switch Ports, CXL Upstream Switch Ports, and CXL
Endpoints. Follow the same "bottom-up" approach used during CXL Port
teardown.
Implement cxl_mask_proto_interrupts() in a header file to avoid introducing
Kconfig ifdefs in cxl/core/port.c.
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
Changes in v10->v11:
- Removed guard() cxl_mask_proto_interrupts(). RP was blocking during
testing. (Terry)
---
drivers/cxl/core/core.h | 2 ++
drivers/cxl/core/port.c | 6 ++++++
drivers/cxl/core/ras.c | 8 ++++++++
drivers/pci/pcie/cxl_aer.c | 21 +++++++++++++++++++++
include/linux/aer.h | 2 ++
5 files changed, 39 insertions(+)
diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index 7e66fbb07b8a..385bfd38b778 100644
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -157,6 +157,7 @@ void cxl_cor_error_detected(struct device *dev);
pci_ers_result_t cxl_error_detected(struct device *dev);
void cxl_port_cor_error_detected(struct device *dev);
pci_ers_result_t cxl_port_error_detected(struct device *dev);
+void cxl_mask_proto_interrupts(struct device *dev);
#else
static inline int cxl_ras_init(void)
{
@@ -186,6 +187,7 @@ static inline pci_ers_result_t cxl_port_error_detected(struct device *dev)
{
return PCI_ERS_RESULT_NONE;
}
+static inline void cxl_mask_proto_interrupts(struct device *dev) { }
#endif // CONFIG_CXL_RAS
int cxl_gpf_port_setup(struct cxl_dport *dport);
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 085c8620a797..bb326dc95d5f 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1428,6 +1428,9 @@ EXPORT_SYMBOL_NS_GPL(cxl_endpoint_autoremove, "CXL");
*/
static void delete_switch_port(struct cxl_port *port)
{
+ cxl_mask_proto_interrupts(port->uport_dev);
+ cxl_mask_proto_interrupts(port->parent_dport->dport_dev);
+
devm_release_action(port->dev.parent, cxl_unlink_parent_dport, port);
devm_release_action(port->dev.parent, cxl_unlink_uport, port);
devm_release_action(port->dev.parent, unregister_port, port);
@@ -1441,6 +1444,7 @@ static void reap_dports(struct cxl_port *port)
device_lock_assert(&port->dev);
xa_for_each(&port->dports, index, dport) {
+ cxl_mask_proto_interrupts(dport->dport_dev);
devm_release_action(&port->dev, cxl_dport_unlink, dport);
devm_release_action(&port->dev, cxl_dport_remove, dport);
devm_kfree(&port->dev, dport);
@@ -1471,6 +1475,8 @@ static void cxl_detach_ep(void *data)
{
struct cxl_memdev *cxlmd = data;
+ cxl_mask_proto_interrupts(cxlmd->cxlds->dev);
+
for (int i = cxlmd->depth - 1; i >= 1; i--) {
struct cxl_port *port, *parent_port;
struct detach_ctx ctx = {
diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
index 90ea0dfb942f..564144c2d23f 100644
--- a/drivers/cxl/core/ras.c
+++ b/drivers/cxl/core/ras.c
@@ -137,6 +137,14 @@ static void cxl_unmask_proto_interrupts(struct device *dev)
pci_aer_unmask_internal_errors(pdev);
}
+void cxl_mask_proto_interrupts(struct device *dev)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+
+ pci_aer_mask_internal_errors(pdev);
+}
+EXPORT_SYMBOL_NS_GPL(cxl_mask_proto_interrupts, "CXL");
+
#ifdef CONFIG_CXL_RCH_RAS
static void cxl_dport_map_rch_aer(struct cxl_dport *dport)
{
diff --git a/drivers/pci/pcie/cxl_aer.c b/drivers/pci/pcie/cxl_aer.c
index 6eeff0b78b47..2de2d9e7934b 100644
--- a/drivers/pci/pcie/cxl_aer.c
+++ b/drivers/pci/pcie/cxl_aer.c
@@ -46,6 +46,27 @@ void pci_aer_unmask_internal_errors(struct pci_dev *dev)
}
EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, "CXL");
+/**
+ * pci_aer_mask_internal_errors - mask internal errors
+ * @dev: pointer to the pcie_dev data structure
+ *
+ * Masks internal errors in the Uncorrectable and Correctable Error
+ * Mask registers.
+ *
+ * Note: AER must be enabled and supported by the device which must be
+ * checked in advance, e.g. with pcie_aer_is_native().
+ */
+void pci_aer_mask_internal_errors(struct pci_dev *dev)
+{
+ int aer = dev->aer_cap;
+
+ pci_clear_and_set_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,
+ 0, PCI_ERR_UNC_INTN);
+ pci_clear_and_set_config_dword(dev, aer + PCI_ERR_COR_MASK,
+ 0, PCI_ERR_COR_INTERNAL);
+}
+EXPORT_SYMBOL_NS_GPL(pci_aer_mask_internal_errors, "CXL");
+
bool cxl_error_is_native(struct pci_dev *dev)
{
struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
diff --git a/include/linux/aer.h b/include/linux/aer.h
index 4e2fc55f2497..82264221ad09 100644
--- a/include/linux/aer.h
+++ b/include/linux/aer.h
@@ -83,12 +83,14 @@ void cxl_register_proto_err_work(struct work_struct *work);
void cxl_unregister_proto_err_work(void);
bool cxl_error_is_native(struct pci_dev *dev);
void pci_aer_unmask_internal_errors(struct pci_dev *dev);
+void pci_aer_mask_internal_errors(struct pci_dev *dev);
#else
static inline int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *wd) { return 0; }
static inline void cxl_register_proto_err_work(struct work_struct *work) { }
static inline void cxl_unregister_proto_err_work(void) { }
static inline bool cxl_error_is_native(struct pci_dev *dev) { return false; }
static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { }
+static inline void pci_aer_mask_internal_errors(struct pci_dev *dev) { }
#endif
void pci_print_aer(struct pci_dev *dev, int aer_severity,
--
2.51.0.rc2.21.ge5ab6b3e5a
next prev parent reply other threads:[~2025-08-27 1:40 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-27 1:35 [PATCH v11 00/23] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2025-08-27 1:35 ` [PATCH v11 01/23] cxl: Remove ifdef blocks of CONFIG_PCIEAER_CXL from core/pci.c Terry Bowman
2025-08-27 1:35 ` [PATCH v11 02/23] CXL/AER: Remove CONFIG_PCIEAER_CXL and replace with CONFIG_CXL_RAS Terry Bowman
2025-08-29 15:24 ` Jonathan Cameron
2025-08-29 18:16 ` Sathyanarayanan Kuppuswamy
2025-08-27 1:35 ` [PATCH v11 03/23] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Terry Bowman
2025-08-28 15:28 ` Dave Jiang
2025-08-27 1:35 ` [PATCH v11 04/23] cxl/pci: Remove unnecessary CXL RCH " Terry Bowman
2025-08-28 8:35 ` Alejandro Lucero Palau
2025-08-28 17:32 ` Dave Jiang
2025-08-27 1:35 ` [PATCH v11 05/23] cxl: Move CXL driver RCH error handling into CONFIG_CXL_RCH_RAS conditional block Terry Bowman
2025-08-28 8:57 ` Alejandro Lucero Palau
2025-09-10 16:43 ` Bowman, Terry
2025-08-29 15:33 ` Jonathan Cameron
2025-09-11 17:48 ` Bowman, Terry
2025-09-11 19:41 ` Dave Jiang
2025-09-15 13:32 ` Bowman, Terry
2025-08-27 1:35 ` [PATCH v11 06/23] CXL/AER: Introduce rch_aer.c into AER driver for handling CXL RCH errors Terry Bowman
2025-08-28 20:53 ` Dave Jiang
2025-08-29 8:39 ` Lukas Wunner
2025-09-10 17:01 ` Bowman, Terry
2025-09-10 17:26 ` Dave Jiang
2025-09-12 13:59 ` Bowman, Terry
2025-09-12 19:09 ` Lukas Wunner
2025-09-10 16:56 ` Bowman, Terry
2025-09-10 12:43 ` Jonathan Cameron
2025-08-27 1:35 ` [PATCH v11 07/23] CXL/PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h Terry Bowman
2025-08-27 14:51 ` Lukas Wunner
2025-08-29 15:42 ` Jonathan Cameron
2025-08-29 15:47 ` Jonathan Cameron
2025-08-28 21:07 ` Dave Jiang
2025-09-10 18:11 ` Bowman, Terry
2025-09-10 20:06 ` Dave Jiang
2025-08-27 1:35 ` [PATCH v11 08/23] PCI/CXL: Introduce pcie_is_cxl() Terry Bowman
2025-08-28 8:18 ` Alejandro Lucero Palau
2025-09-10 16:24 ` Bowman, Terry
2025-09-11 3:48 ` Lukas Wunner
2025-09-10 13:10 ` Jonathan Cameron
2025-08-27 1:35 ` [PATCH v11 09/23] PCI/AER: Report CXL or PCIe bus error type in trace logging Terry Bowman
2025-08-27 7:37 ` Lukas Wunner
2025-09-10 15:26 ` Bowman, Terry
2025-09-10 15:33 ` Lukas Wunner
2025-09-11 5:07 ` Lukas Wunner
2025-08-27 1:35 ` [PATCH v11 10/23] CXL/AER: Update PCI class code check to use FIELD_GET() Terry Bowman
2025-08-29 16:03 ` Jonathan Cameron
2025-09-11 18:18 ` Bowman, Terry
2025-08-27 1:35 ` [PATCH v11 11/23] cxl/pci: Update RAS handler interfaces to also support CXL Ports Terry Bowman
2025-08-27 1:35 ` [PATCH v11 12/23] cxl/pci: Log message if RAS registers are unmapped Terry Bowman
2025-08-27 1:35 ` [PATCH v11 13/23] cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports Terry Bowman
2025-08-27 11:55 ` Shiju Jose
2025-08-29 16:06 ` Jonathan Cameron
2025-08-27 1:35 ` [PATCH v11 14/23] cxl/pci: Update cxl_handle_cor_ras() to return early if no RAS errors Terry Bowman
2025-08-27 1:35 ` [PATCH v11 15/23] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2025-08-28 23:05 ` Dave Jiang
2025-09-10 18:40 ` Bowman, Terry
2025-08-27 1:35 ` [PATCH v11 16/23] cxl/pci: Introduce CXL Endpoint protocol error handlers Terry Bowman
2025-08-27 7:48 ` Lukas Wunner
2025-09-10 13:23 ` Jonathan Cameron
2025-08-27 1:35 ` [PATCH v11 17/23] CXL/AER: Introduce cxl_aer.c into AER driver for forwarding CXL errors Terry Bowman
2025-08-27 7:56 ` Lukas Wunner
2025-08-27 1:35 ` [PATCH v11 18/23] PCI/AER: Dequeue forwarded CXL error Terry Bowman
2025-08-29 0:43 ` Dave Jiang
2025-08-29 7:10 ` Lukas Wunner
2025-09-16 15:18 ` Bowman, Terry
2025-09-11 14:33 ` Bowman, Terry
2025-09-11 15:41 ` Dave Jiang
2025-09-11 16:47 ` Bowman, Terry
2025-09-11 19:45 ` Dave Jiang
2025-09-10 13:29 ` Jonathan Cameron
2025-08-27 1:35 ` [PATCH v11 19/23] CXL/PCI: Introduce CXL Port protocol error handlers Terry Bowman
2025-08-30 0:17 ` Dave Jiang
2025-08-27 1:35 ` [PATCH v11 20/23] CXL/PCI: Export and rename merge_result() to pci_ers_merge_result() Terry Bowman
2025-08-27 8:04 ` Lukas Wunner
2025-09-10 15:57 ` Bowman, Terry
2025-09-11 3:44 ` Lukas Wunner
2025-08-27 12:19 ` kernel test robot
2025-08-27 1:35 ` [PATCH v11 21/23] CXL/PCI: Introduce CXL uncorrectable protocol error recovery Terry Bowman
2025-09-03 22:30 ` Dave Jiang
2025-09-11 19:19 ` Bowman, Terry
2025-09-11 19:48 ` Dave Jiang
2025-09-10 13:33 ` Jonathan Cameron
2025-08-27 1:35 ` [PATCH v11 22/23] CXL/PCI: Enable CXL protocol errors during CXL Port probe Terry Bowman
2025-09-03 23:23 ` Dave Jiang
2025-08-27 1:35 ` Terry Bowman [this message]
2025-09-10 15:07 ` [PATCH v11 23/23] CXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup Gregory Price
2025-09-11 20:19 ` Bowman, Terry
2025-08-29 0:07 ` [PATCH v11 00/23] Enable CXL PCIe Port Protocol Error handling and logging Dave Jiang
2025-09-23 3:29 ` Gregory Price
2025-09-23 9:21 ` Srinivasulu Thanneeru
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