From: Yaroslav Bolyukin <iam@lach.pw>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>
Cc: "Harry Wentland" <harry.wentland@amd.com>,
"Leo Li" <sunpeng.li@amd.com>,
"Rodrigo Siqueira" <siqueira@igalia.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Wayne Lin" <Wayne.Lin@amd.com>,
amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org,
"Yaroslav Bolyukin" <iam@lach.pw>
Subject: [PATCH v5 3/7] drm/edid: MSO should only be used for non-eDP displays
Date: Fri, 17 Oct 2025 18:27:32 +0200 [thread overview]
Message-ID: <20251017162736.45368-4-iam@lach.pw> (raw)
In-Reply-To: <20251017162736.45368-1-iam@lach.pw>
As per DisplayID v2.1a spec:
If Offset 06h[2:0] is programmed to 001b (External DisplayPort), this field shallbe cleared to 00b (Not supported).
Ref: https://lore.kernel.org/lkml/3abc1087618c822e5676e67a3ec2e64e506dc5ec@intel.com/
Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
---
drivers/gpu/drm/drm_displayid_internal.h | 4 +++
drivers/gpu/drm/drm_edid.c | 36 +++++++++++++++---------
2 files changed, 27 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
index 957dd0619f5c..cf02647b41b4 100644
--- a/drivers/gpu/drm/drm_displayid_internal.h
+++ b/drivers/gpu/drm/drm_displayid_internal.h
@@ -142,9 +142,13 @@ struct displayid_formula_timing_block {
struct displayid_formula_timings_9 timings[];
} __packed;
+#define DISPLAYID_VESA_DP_TYPE GENMASK(2, 0)
#define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0)
#define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5)
+#define DISPLAYID_VESA_DP_TYPE_EDP 0
+#define DISPLAYID_VESA_DP_TYPE_DP 1
+
struct displayid_vesa_vendor_specific_block {
struct displayid_block base;
u8 oui[3];
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 725ae5f9d160..13df2854617c 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -6530,6 +6530,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
struct displayid_vesa_vendor_specific_block *vesa =
(struct displayid_vesa_vendor_specific_block *)block;
struct drm_display_info *info = &connector->display_info;
+ int dp_type;
if (block->num_bytes < 3) {
drm_dbg_kms(connector->dev,
@@ -6548,20 +6549,29 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
return;
}
- switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
- default:
- drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
+ dp_type = FIELD_GET(DISPLAYID_VESA_DP_TYPE, vesa->data_structure_type);
+ if (dp_type > 1) {
+ drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved dp type value\n",
connector->base.id, connector->name);
- fallthrough;
- case 0:
- info->mso_stream_count = 0;
- break;
- case 1:
- info->mso_stream_count = 2; /* 2 or 4 links */
- break;
- case 2:
- info->mso_stream_count = 4; /* 4 links */
- break;
+ }
+
+ /* MSO is not supported for eDP */
+ if (dp_type != DISPLAYID_VESA_DP_TYPE_EDP) {
+ switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
+ default:
+ drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
+ connector->base.id, connector->name);
+ fallthrough;
+ case 0:
+ info->mso_stream_count = 0;
+ break;
+ case 1:
+ info->mso_stream_count = 2; /* 2 or 4 links */
+ break;
+ case 2:
+ info->mso_stream_count = 4; /* 4 links */
+ break;
+ }
}
if (info->mso_stream_count) {
--
2.51.0
next prev parent reply other threads:[~2025-10-17 16:28 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-17 16:27 [PATCH v5 0/7] DisplayID DSC passthrough timing support Yaroslav Bolyukin
2025-10-17 16:27 ` [PATCH v5 1/7] drm/edid: rename VESA block parsing functions to more generic name Yaroslav Bolyukin
2025-10-17 16:27 ` [PATCH v5 2/7] drm/edid: prepare for VESA vendor-specific data block extension Yaroslav Bolyukin
2025-10-17 16:27 ` Yaroslav Bolyukin [this message]
2025-10-17 16:27 ` [PATCH v5 4/7] drm/edid: parse DSC DPP passthru support flag for mode VII timings Yaroslav Bolyukin
2025-10-17 16:27 ` [PATCH v5 5/7] drm/edid: for consistency, use mask everywhere for block rev parsing Yaroslav Bolyukin
2025-10-17 16:27 ` [PATCH v5 6/7] drm/edid: parse DRM VESA dsc bpp target Yaroslav Bolyukin
2025-10-17 16:27 ` [PATCH v5 7/7] drm/amd: use fixed dsc bits-per-pixel from edid Yaroslav Bolyukin
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