From: Yaroslav Bolyukin <iam@lach.pw>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>
Cc: "Harry Wentland" <harry.wentland@amd.com>,
"Leo Li" <sunpeng.li@amd.com>,
"Rodrigo Siqueira" <siqueira@igalia.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Wayne Lin" <Wayne.Lin@amd.com>,
amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org,
"Yaroslav Bolyukin" <iam@lach.pw>
Subject: [PATCH v5 4/7] drm/edid: parse DSC DPP passthru support flag for mode VII timings
Date: Fri, 17 Oct 2025 18:27:33 +0200 [thread overview]
Message-ID: <20251017162736.45368-5-iam@lach.pw> (raw)
In-Reply-To: <20251017162736.45368-1-iam@lach.pw>
Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
---
drivers/gpu/drm/drm_displayid_internal.h | 2 ++
drivers/gpu/drm/drm_edid.c | 12 ++++++++----
include/drm/drm_modes.h | 10 ++++++++++
3 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
index cf02647b41b4..8ea20b1c6921 100644
--- a/drivers/gpu/drm/drm_displayid_internal.h
+++ b/drivers/gpu/drm/drm_displayid_internal.h
@@ -97,6 +97,7 @@ struct displayid_header {
u8 ext_count;
} __packed;
+#define DISPLAYID_BLOCK_REV GENMASK(2, 0)
struct displayid_block {
u8 tag;
u8 rev;
@@ -125,6 +126,7 @@ struct displayid_detailed_timings_1 {
__le16 vsw;
} __packed;
+#define DISPLAYID_BLOCK_PASSTHROUGH_TIMINGS_SUPPORT BIT(3)
struct displayid_detailed_timing_block {
struct displayid_block base;
struct displayid_detailed_timings_1 timings[];
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 13df2854617c..a1dc4331c4cb 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -6789,8 +6789,8 @@ static void update_display_info(struct drm_connector *connector,
}
static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
- const struct displayid_detailed_timings_1 *timings,
- bool type_7)
+ const struct displayid_block *block,
+ const struct displayid_detailed_timings_1 *timings)
{
struct drm_display_mode *mode;
unsigned int pixel_clock = (timings->pixel_clock[0] |
@@ -6806,11 +6806,16 @@ static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *d
unsigned int vsync_width = le16_to_cpu(timings->vsw) + 1;
bool hsync_positive = le16_to_cpu(timings->hsync) & (1 << 15);
bool vsync_positive = le16_to_cpu(timings->vsync) & (1 << 15);
+ bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
mode = drm_mode_create(dev);
if (!mode)
return NULL;
+ if (type_7 && FIELD_GET(DISPLAYID_BLOCK_REV, block->rev) >= 1)
+ mode->dsc_passthrough_timings_support =
+ !!(block->rev & DISPLAYID_BLOCK_PASSTHROUGH_TIMINGS_SUPPORT);
+
/* resolution is kHz for type VII, and 10 kHz for type I */
mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
mode->hdisplay = hactive;
@@ -6843,7 +6848,6 @@ static int add_displayid_detailed_1_modes(struct drm_connector *connector,
int num_timings;
struct drm_display_mode *newmode;
int num_modes = 0;
- bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
/* blocks must be multiple of 20 bytes length */
if (block->num_bytes % 20)
return 0;
@@ -6852,7 +6856,7 @@ static int add_displayid_detailed_1_modes(struct drm_connector *connector,
for (i = 0; i < num_timings; i++) {
struct displayid_detailed_timings_1 *timings = &det->timings[i];
- newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
+ newmode = drm_mode_displayid_detailed(connector->dev, block, timings);
if (!newmode)
continue;
diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h
index b9bb92e4b029..312e5c03af9a 100644
--- a/include/drm/drm_modes.h
+++ b/include/drm/drm_modes.h
@@ -417,6 +417,16 @@ struct drm_display_mode {
*/
enum hdmi_picture_aspect picture_aspect_ratio;
+ /**
+ * @dsc_passthrough_timing_support:
+ *
+ * Indicates whether this mode timing descriptor is supported
+ * with specific target DSC bits per pixel only.
+ *
+ * VESA vendor-specific data block shall exist with the relevant
+ * DSC bits per pixel declaration when this flag is set to true.
+ */
+ bool dsc_passthrough_timings_support;
};
/**
--
2.51.0
next prev parent reply other threads:[~2025-10-17 16:28 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-17 16:27 [PATCH v5 0/7] DisplayID DSC passthrough timing support Yaroslav Bolyukin
2025-10-17 16:27 ` [PATCH v5 1/7] drm/edid: rename VESA block parsing functions to more generic name Yaroslav Bolyukin
2025-10-17 16:27 ` [PATCH v5 2/7] drm/edid: prepare for VESA vendor-specific data block extension Yaroslav Bolyukin
2025-10-17 16:27 ` [PATCH v5 3/7] drm/edid: MSO should only be used for non-eDP displays Yaroslav Bolyukin
2025-10-17 16:27 ` Yaroslav Bolyukin [this message]
2025-10-17 16:27 ` [PATCH v5 5/7] drm/edid: for consistency, use mask everywhere for block rev parsing Yaroslav Bolyukin
2025-10-17 16:27 ` [PATCH v5 6/7] drm/edid: parse DRM VESA dsc bpp target Yaroslav Bolyukin
2025-10-17 16:27 ` [PATCH v5 7/7] drm/amd: use fixed dsc bits-per-pixel from edid Yaroslav Bolyukin
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