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From: Yaroslav Bolyukin <iam@lach.pw>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Thomas Zimmermann" <tzimmermann@suse.de>,
	"David Airlie" <airlied@gmail.com>,
	"Simona Vetter" <simona@ffwll.ch>
Cc: "Harry Wentland" <harry.wentland@amd.com>,
	"Leo Li" <sunpeng.li@amd.com>,
	"Rodrigo Siqueira" <siqueira@igalia.com>,
	"Alex Deucher" <alexander.deucher@amd.com>,
	"Christian König" <christian.koenig@amd.com>,
	"Wayne Lin" <Wayne.Lin@amd.com>,
	amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	dri-devel@lists.freedesktop.org,
	"Yaroslav Bolyukin" <iam@lach.pw>
Subject: [PATCH v5 5/7] drm/edid: for consistency, use mask everywhere for block rev parsing
Date: Fri, 17 Oct 2025 18:27:34 +0200	[thread overview]
Message-ID: <20251017162736.45368-6-iam@lach.pw> (raw)
In-Reply-To: <20251017162736.45368-1-iam@lach.pw>

Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
---
 drivers/gpu/drm/drm_displayid_internal.h | 1 +
 drivers/gpu/drm/drm_edid.c               | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
index 8ea20b1c6921..38f9d628e2d6 100644
--- a/drivers/gpu/drm/drm_displayid_internal.h
+++ b/drivers/gpu/drm/drm_displayid_internal.h
@@ -139,6 +139,7 @@ struct displayid_formula_timings_9 {
 	u8 vrefresh;
 } __packed;
 
+#define DISPLAYID_BLOCK_DESCRIPTOR_PAYLOAD_BYTES	GENMASK(6, 4)
 struct displayid_formula_timing_block {
 	struct displayid_block base;
 	struct displayid_formula_timings_9 timings[];
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index a1dc4331c4cb..4fa39989e446 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -6903,7 +6903,8 @@ static int add_displayid_formula_modes(struct drm_connector *connector,
 	struct drm_display_mode *newmode;
 	int num_modes = 0;
 	bool type_10 = block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING;
-	int timing_size = 6 + ((formula_block->base.rev & 0x70) >> 4);
+	int timing_size = 6 +
+		FIELD_GET(DISPLAYID_BLOCK_DESCRIPTOR_PAYLOAD_BYTES, formula_block->base.rev);
 
 	/* extended blocks are not supported yet */
 	if (timing_size != 6)
-- 
2.51.0


  parent reply	other threads:[~2025-10-17 16:28 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-17 16:27 [PATCH v5 0/7] DisplayID DSC passthrough timing support Yaroslav Bolyukin
2025-10-17 16:27 ` [PATCH v5 1/7] drm/edid: rename VESA block parsing functions to more generic name Yaroslav Bolyukin
2025-10-17 16:27 ` [PATCH v5 2/7] drm/edid: prepare for VESA vendor-specific data block extension Yaroslav Bolyukin
2025-10-17 16:27 ` [PATCH v5 3/7] drm/edid: MSO should only be used for non-eDP displays Yaroslav Bolyukin
2025-10-17 16:27 ` [PATCH v5 4/7] drm/edid: parse DSC DPP passthru support flag for mode VII timings Yaroslav Bolyukin
2025-10-17 16:27 ` Yaroslav Bolyukin [this message]
2025-10-17 16:27 ` [PATCH v5 6/7] drm/edid: parse DRM VESA dsc bpp target Yaroslav Bolyukin
2025-10-17 16:27 ` [PATCH v5 7/7] drm/amd: use fixed dsc bits-per-pixel from edid Yaroslav Bolyukin

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