From: Harshal Dev <harshal.dev@oss.qualcomm.com>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Val Packett <val@packett.cool>,
Stephan Gerhold <stephan.gerhold@linaro.org>,
Abel Vesa <abel.vesa@linaro.org>,
Udit Tiwari <quic_utiwari@quicinc.com>,
Neeraj Soni <quic_neersoni@quicinc.com>,
Harshal Dev <harshal.dev@oss.qualcomm.com>
Subject: [PATCH v3] arm64: dts: qcom: x1e80100: Add crypto engine
Date: Thu, 27 Nov 2025 15:13:55 +0530 [thread overview]
Message-ID: <20251127-crypto_dt_node_x1e80100-v3-1-29722003fe83@oss.qualcomm.com> (raw)
On X Elite, there is a crypto engine IP block similar to ones found on
SM8x50 platforms.
Describe the crypto engine and its BAM.
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
---
The dt-binding schema update for the x1e80100 compatible is here
(already merged):
https://lore.kernel.org/all/20250213-dt-bindings-qcom-qce-x1e80100-v1-1-d17ef73a1c12@linaro.org/
---
Changes in v3:
- Fixed num-channels and qcom,num-ees properties by updating them to 20 and 4 respectively.
- Link to v2: https://lore.kernel.org/all/20250221-x1e80100-crypto-v2-1-413ecf68dcd7@linaro.org
Changes in v2:
- Added EE and channels numbers in BAM node, like Stephan suggested.
- Added v1.7.4 compatible as well.
- Link to v1: https://lore.kernel.org/r/20250213-x1e80100-crypto-v1-1-f93afdd4025a@linaro.org
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 51576d9c935d..a1cadcce98e1 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3033,6 +3033,30 @@ usb_1_ss2_qmpphy_dp_in: endpoint {
};
};
+ cryptobam: dma-controller@1dc4000 {
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+ reg = <0x0 0x01dc4000 0x0 0x28000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&apps_smmu 0x480 0x0000>,
+ <&apps_smmu 0x481 0x0000>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ num-channels = <20>;
+ qcom,num-ees = <4>;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce";
+ reg = <0x0 0x01dfa000 0x0 0x6000>;
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x480 0x0000>,
+ <&apps_smmu 0x481 0x0000>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "memory";
+ };
+
cnoc_main: interconnect@1500000 {
compatible = "qcom,x1e80100-cnoc-main";
reg = <0 0x01500000 0 0x14400>;
---
base-commit: 765e56e41a5af2d456ddda6cbd617b9d3295ab4e
change-id: 20251127-crypto_dt_node_x1e80100-bcb1a2837b56
Best regards,
--
Harshal Dev <harshal.dev@oss.qualcomm.com>
next reply other threads:[~2025-11-27 9:44 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-27 9:43 Harshal Dev [this message]
2025-12-04 13:44 ` Konrad Dybcio
2025-12-05 10:28 ` Harshal Dev
2025-12-05 10:32 ` Konrad Dybcio
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