Re: [PATCH v3] arm64: dts: qcom: x1e80100: Add crypto engine

[Harshal Dev <harshal.dev@oss.qualcomm.com>]

Hi Konrad,

On 12/4/2025 7:14 PM, Konrad Dybcio wrote:
> On 11/27/25 10:43 AM, Harshal Dev wrote:
>> On X Elite, there is a crypto engine IP block similar to ones found on
>> SM8x50 platforms.
>>
>> Describe the crypto engine and its BAM.
>>
>> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
>> ---
>> The dt-binding schema update for the x1e80100 compatible is here
>> (already merged):
>>
>> https://lore.kernel.org/all/20250213-dt-bindings-qcom-qce-x1e80100-v1-1-d17ef73a1c12@linaro.org/
>> ---
>> Changes in v3:
>> - Fixed num-channels and qcom,num-ees properties by updating them to 20 and 4 respectively.
>> - Link to v2: https://lore.kernel.org/all/20250221-x1e80100-crypto-v2-1-413ecf68dcd7@linaro.org
>> Changes in v2:
>> - Added EE and channels numbers in BAM node, like Stephan suggested.
>> - Added v1.7.4 compatible as well.
>> - Link to v1: https://lore.kernel.org/r/20250213-x1e80100-crypto-v1-1-f93afdd4025a@linaro.org
>> ---
>>  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 24 ++++++++++++++++++++++++
>>  1 file changed, 24 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> index 51576d9c935d..a1cadcce98e1 100644
>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> @@ -3033,6 +3033,30 @@ usb_1_ss2_qmpphy_dp_in: endpoint {
>>  			};
>>  		};
>>  
>> +		cryptobam: dma-controller@1dc4000 {
>> +			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
>> +			reg = <0x0 0x01dc4000 0x0 0x28000>;
>> +			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
>> +			#dma-cells = <1>;
>> +			iommus = <&apps_smmu 0x480 0x0000>,
>> +				 <&apps_smmu 0x481 0x0000>;
> 
> Just 0x0 is good

Acknowledge.

> 
>> +			qcom,ee = <0>;
>> +			qcom,controlled-remotely;
>> +			num-channels = <20>;
>> +			qcom,num-ees = <4>;
>> +		};
>> +
>> +		crypto: crypto@1dfa000 {
>> +			compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce";
>> +			reg = <0x0 0x01dfa000 0x0 0x6000>;
>> +			dmas = <&cryptobam 4>, <&cryptobam 5>;
>> +			dma-names = "rx", "tx";
> 
> one a line, please

I did not quite get this comment, could you please clarify a bit more? :)

> 
>> +			iommus = <&apps_smmu 0x480 0x0000>,
>> +				 <&apps_smmu 0x481 0x0000>;
>> +			interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
> 
> 0 -> QCOM_ICC_TAG_ALWAYS

Acknowledge.

Regards,
Harshal

> 
> Konrad