[PATCH v1 0/2 RESEND] tegra: dsi: improvements for video mode ganged panels

[PATCH v1 0/2 RESEND] tegra: dsi: improvements for video mode ganged panels

[Svyatoslav Ryhel]

Expand SOL delay and packet parameters calculations to include video mode
ganged panels. At the moment only command mode ganged panels are supported.

Svyatoslav Ryhel (2):
  gpu/drm: tegra: dsi: make SOL delay calculation mode independent
  gpu/drm: tegra: dsi: calculate packet parameters for video mode

 drivers/gpu/drm/tegra/dsi.c | 54 ++++++++++++++++++-------------------
 1 file changed, 27 insertions(+), 27 deletions(-)

-- 
2.48.1

[PATCH v1 1/2 RESEND] gpu/drm: tegra: dsi: make SOL delay calculation mode independent

[Svyatoslav Ryhel]

Move SOL delay calculation outside of video mode conditions.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 drivers/gpu/drm/tegra/dsi.c | 41 +++++++++++++++----------------------
 1 file changed, 17 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index 924611061cfa..aab555a2eb68 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -560,11 +560,6 @@ static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
 		tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
 		tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
 		tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
-
-		/* set SOL delay (for non-burst mode only) */
-		tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
-
-		/* TODO: implement ganged mode */
 	} else {
 		u16 bytes;
 
@@ -586,28 +581,26 @@ static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
 		value = MIPI_DCS_WRITE_MEMORY_START << 8 |
 			MIPI_DCS_WRITE_MEMORY_CONTINUE;
 		tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
+	}
 
-		/* set SOL delay */
-		if (dsi->master || dsi->slave) {
-			unsigned long delay, bclk, bclk_ganged;
-			unsigned int lanes = state->lanes;
-
-			/* SOL to valid, valid to FIFO and FIFO write delay */
-			delay = 4 + 4 + 2;
-			delay = DIV_ROUND_UP(delay * mul, div * lanes);
-			/* FIFO read delay */
-			delay = delay + 6;
-
-			bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
-			bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
-			value = bclk - bclk_ganged + delay + 20;
-		} else {
-			/* TODO: revisit for non-ganged mode */
-			value = 8 * mul / div;
-		}
+	/* set SOL delay */
+	if (dsi->master || dsi->slave) {
+		unsigned long delay, bclk, bclk_ganged;
+		unsigned int lanes = state->lanes;
 
-		tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
+		/* SOL to valid, valid to FIFO and FIFO write delay */
+		delay = 4 + 4 + 2;
+		delay = DIV_ROUND_UP(delay * mul, div * lanes);
+		/* FIFO read delay */
+		delay = delay + 6;
+
+		bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
+		bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
+		value = bclk - bclk_ganged + delay + 20;
+	} else {
+		value = 8 * mul / div;
 	}
+	tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
 
 	if (dsi->slave) {
 		tegra_dsi_configure(dsi->slave, pipe, mode);
-- 
2.48.1

[PATCH v1 2/2 RESEND] gpu/drm: tegra: dsi: calculate packet parameters for video mode

[Svyatoslav Ryhel]

Calculate packet parameters for video mode same way it is done or
command mode, by halving timings plugged into equations.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 drivers/gpu/drm/tegra/dsi.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index aab555a2eb68..1ec3f03d2577 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -545,12 +545,19 @@ static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
 		/* horizontal back porch */
 		hbp = (mode->htotal - mode->hsync_end) * mul / div;
 
-		if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
-			hbp += hsw;
-
 		/* horizontal front porch */
 		hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
 
+		if (dsi->master || dsi->slave) {
+			hact /= 2;
+			hsw /= 2;
+			hbp /= 2;
+			hfp /= 2;
+		}
+
+		if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
+			hbp += hsw;
+
 		/* subtract packet overhead */
 		hsw -= 10;
 		hbp -= 14;
-- 
2.48.1

Re: [PATCH v1 0/2 RESEND] tegra: dsi: improvements for video mode ganged panels

[Mikko Perttunen]

On Thursday, December 4, 2025 3:14 PM Svyatoslav Ryhel wrote:
> Expand SOL delay and packet parameters calculations to include video mode
> ganged panels. At the moment only command mode ganged panels are supported.
> 
> Svyatoslav Ryhel (2):
>   gpu/drm: tegra: dsi: make SOL delay calculation mode independent
>   gpu/drm: tegra: dsi: calculate packet parameters for video mode
> 
>  drivers/gpu/drm/tegra/dsi.c | 54 ++++++++++++++++++-------------------
>  1 file changed, 27 insertions(+), 27 deletions(-)
> 
> 

I can see this series has been merged.

Mikko

Re: [PATCH v1 0/2 RESEND] tegra: dsi: improvements for video mode ganged panels

[Svyatoslav Ryhel]

чт, 15 січ. 2026 р. о 09:09 Mikko Perttunen <mperttunen@nvidia.com> пише:
>
> On Thursday, December 4, 2025 3:14 PM Svyatoslav Ryhel wrote:
> > Expand SOL delay and packet parameters calculations to include video mode
> > ganged panels. At the moment only command mode ganged panels are supported.
> >
> > Svyatoslav Ryhel (2):
> >   gpu/drm: tegra: dsi: make SOL delay calculation mode independent
> >   gpu/drm: tegra: dsi: calculate packet parameters for video mode
> >
> >  drivers/gpu/drm/tegra/dsi.c | 54 ++++++++++++++++++-------------------
> >  1 file changed, 27 insertions(+), 27 deletions(-)
> >
> >
>
> I can see this series has been merged.
>
> Mikko
>

I wasn't notified that this series was accepted, thank you for letting me know.