* [PATCH v1 1/2] dt-bindings: arm: cix: add OrangePi 6 Plus board
2025-12-19 9:54 [PATCH v1 0/2] Add OrangePi 6 Plus board Gary Yang
@ 2025-12-19 9:54 ` Gary Yang
2025-12-19 9:56 ` Krzysztof Kozlowski
2025-12-19 9:54 ` [PATCH v1 2/2] arm64: dts: cix: Add OrangePi 6 Plus board support Gary Yang
1 sibling, 1 reply; 4+ messages in thread
From: Gary Yang @ 2025-12-19 9:54 UTC (permalink / raw)
To: peter.chen, fugang.duan, robh, krzk+dt, conor+dt
Cc: linux-cix-kernel-upstream, linux-arm-kernel, devicetree,
linux-kernel, Gary Yang
OrangePi 6 Plus adopts CIX CD8180/CD8160 SoC,
built-in 12-core 64-bit processor + NPU processor,
integrated graphics processor, equipped with 16GB/32GB/64GB
LPDDR5, and provides two M.2 KEY-M interfaces 2280 for NVMe SSD,
as well as SPI FLASH and TF slots to meet the needs of fast
read/write and high-capacity storage;
Signed-off-by: Gary Yang <gary.yang@cixtech.com>
---
Documentation/devicetree/bindings/arm/cix.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cix.yaml b/Documentation/devicetree/bindings/arm/cix.yaml
index 114dab4bc4d2..92fb4ad7b5d8 100644
--- a/Documentation/devicetree/bindings/arm/cix.yaml
+++ b/Documentation/devicetree/bindings/arm/cix.yaml
@@ -21,6 +21,11 @@ properties:
- const: radxa,orion-o6
- const: cix,sky1
+ - description: OrangePi 6 Plus
+ items:
+ - const: OrangePi,6p
+ - const: cix,sky1
+
additionalProperties: true
...
--
2.49.0
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v1 2/2] arm64: dts: cix: Add OrangePi 6 Plus board support
2025-12-19 9:54 [PATCH v1 0/2] Add OrangePi 6 Plus board Gary Yang
2025-12-19 9:54 ` [PATCH v1 1/2] dt-bindings: arm: cix: add " Gary Yang
@ 2025-12-19 9:54 ` Gary Yang
1 sibling, 0 replies; 4+ messages in thread
From: Gary Yang @ 2025-12-19 9:54 UTC (permalink / raw)
To: peter.chen, fugang.duan, robh, krzk+dt, conor+dt
Cc: linux-cix-kernel-upstream, linux-arm-kernel, devicetree,
linux-kernel, Gary Yang
OrangePi 6 Plus adopts CIX CD8180/CD8160 SoC,
built-in 12-core 64-bit processor + NPU processor,
integrated graphics processor, equipped with 16GB/32GB/64GB
LPDDR5, and provides two M.2 KEY-M interfaces 2280 for NVMe SSD,
as well as SPI FLASH and TF slots to meet the needs of fast
read/write and high-capacity storage;
Signed-off-by: Gary Yang <gary.yang@cixtech.com>
---
arch/arm64/boot/dts/cix/Makefile | 1 +
arch/arm64/boot/dts/cix/sky1-xcp.dts | 83 ++++++++++++++++++++++++++++
2 files changed, 84 insertions(+)
create mode 100644 arch/arm64/boot/dts/cix/sky1-xcp.dts
diff --git a/arch/arm64/boot/dts/cix/Makefile b/arch/arm64/boot/dts/cix/Makefile
index ed3713982012..8a6c6fdc4ec0 100644
--- a/arch/arm64/boot/dts/cix/Makefile
+++ b/arch/arm64/boot/dts/cix/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_CIX) += sky1-orion-o6.dtb
+dtb-$(CONFIG_ARCH_CIX) += sky1-xcp.dtb
diff --git a/arch/arm64/boot/dts/cix/sky1-xcp.dts b/arch/arm64/boot/dts/cix/sky1-xcp.dts
new file mode 100644
index 000000000000..4350fbd6e780
--- /dev/null
+++ b/arch/arm64/boot/dts/cix/sky1-xcp.dts
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2025 Cix Technology Group Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "sky1.dtsi"
+#include "sky1-pinfunc.h"
+
+/ {
+ model = "OrangePi 6 Plus";
+ compatible = "OrangePi,6p", "cix,sky1";
+
+ aliases {
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x28000000>;
+ linux,cma-default;
+ };
+ };
+
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hog-cfg {
+ pins {
+ pinmux = <CIX_PAD_GPIO144_FUNC_GPIO144>,
+ <CIX_PAD_GPIO145_FUNC_GPIO145>,
+ <CIX_PAD_GPIO146_FUNC_GPIO146>,
+ <CIX_PAD_GPIO147_FUNC_GPIO147>;
+ bias-pull-down;
+ drive-strength = <8>;
+ };
+ };
+};
+
+&iomuxc_s5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog_s5>;
+
+ pinctrl_hog_s5: hog-s5-cfg {
+ pins {
+ pinmux = <CIX_PAD_GPIO014_FUNC_GPIO014>;
+ bias-pull-up;
+ drive-strength = <8>;
+
+ };
+ };
+};
+
+&pcie_x8_rc {
+ status = "okay";
+};
+
+&pcie_x2_rc {
+ status = "okay";
+};
+
+&pcie_x1_1_rc {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
--
2.49.0
^ permalink raw reply [flat|nested] 4+ messages in thread