* [PATCH v1 1/5] dt-bindings: hwmon: add altr,socfpga-hwmon.yaml binding
2025-12-16 6:49 [PATCH v1 0/5] hwmon: Add support for Altera SoCFPGA hardware monitoring muhammadamirulasyraf.mohamadjamian
@ 2025-12-16 6:49 ` muhammadamirulasyraf.mohamadjamian
2025-12-18 8:25 ` Krzysztof Kozlowski
2025-12-16 6:49 ` [PATCH v1 2/5] dt-bindings: firmware: svc: add hwmon property muhammadamirulasyraf.mohamadjamian
` (3 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: muhammadamirulasyraf.mohamadjamian @ 2025-12-16 6:49 UTC (permalink / raw)
To: Guenter Roeck, linux-hwmon, Dinh Nguyen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel,
Ang Tien Sung, Khairul Anuar Romli
From: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
The Altera SoCFPGA platform includes a hardware monitoring (hwmon) device
that reports voltage and temperature sensors critical for system stability
and safety. Without a proper device tree binding, the kernel and
userspace tools cannot correctly interpret or configure these sensors.
This binding provides a formal description of the device’s properties,
including the 'compatible' string for driver matching, voltage and
temperature parameters with scaling and threshold definitions. This enables
the kernel to correctly identify the device, interpret sensor data
accurately, and manage threshold-based events.
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Signed-off-by: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
---
.../bindings/hwmon/altr,socfpga-hwmon.yaml | 286 ++++++++++++++++++
MAINTAINERS | 7 +
2 files changed, 293 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml
diff --git a/Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml b/Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml
new file mode 100644
index 000000000000..b69611c8bc7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml
@@ -0,0 +1,286 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/altr,socfpga-hwmon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera Hardware monitor SOC FPGA
+
+maintainers:
+ - Ang Tien Sung <tiensung.ang@altera.com>
+ - Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
+
+description: |
+ The Altera SoC FPGA hardware monitor unit provides on-chip voltage and
+ temperature sensors. You can use these sensors to monitor external
+ voltages and on-chip operating conditions such as internal power rails
+ and on-chip junction temperatures.
+
+ The specific sensor configurations vary for each device family and
+ each device within a family does not offer all potential sensor
+ options. The information below attempts to illustrate the super set of
+ possible sensor options that are potentially available within each
+ device family, but the user should check the documentation for the
+ specific device they are using to verify which sensor options it
+ actually provides.
+
+ Stratix 10 Device Family
+
+ Stratix 10 Voltage Sensors
+
+ page 0, channel 2 = 0.8V VCC
+ page 0, channel 3 = 1.8V VCCIO_SDM
+ page 0, channel 6 = 0.9V VCCERAM
+
+ Stratix 10 Temperature Sensors
+
+ page 0, channel 0 = main die
+ page 0, channel 1 = tile bottom left
+ page 0, channel 2 = tile middle left
+ page 0, channel 3 = tile top left
+ page 0, channel 4 = tile bottom right
+ page 0, channel 5 = tile middle right
+ page 0, channel 6 = tile top right
+ page 0, channel 7 = hbm2 bottom
+ page 0, channel 8 = hbm2 top
+
+ Agilex Device Family
+
+ Agilex Voltage Sensors
+
+ page 0, channel 2 = 0.8V VCC
+ page 0, channel 3 = 1.8V VCCIO_SDM
+ page 0, channel 4 = 1.8V VCCPT
+ page 0, channel 5 = 1.2V VCCRCORE
+ page 0, channel 6 = 0.9V VCCH
+ page 0, channel 7 = 0.8V VCCL
+
+ Agilex Temperature Sensors
+
+ page 0, channel 0 = main die sdm max
+ page 0, channel 1 = main die sdm 1
+
+ page 1, channel 0 = main die corner bottom left max
+ page 1, channel 1 = main die corner bottom left 1
+ page 1, channel 2 = main die corner bottom left 2
+
+ page 2, channel 0 = main die corner top left max
+ page 2, channel 1 = main die corner top left 1
+ page 2, channel 2 = main die corner top left 2
+
+ page 3, channel 0 = main die corner bottom right max
+ page 3, channel 1 = main die corner bottom right 1
+ page 3, channel 2 = main die corner bottom right 2
+
+ page 4, channel 0 = main die corner top right max
+ page 4, channel 1 = main die corner top right 1
+ page 4, channel 2 = main die corner top right 2
+
+ page 5, channel 0 = tile die bottom left max
+ page 5, channel 1 = tile die bottom left 1
+ page 5, channel 6..2 = tile die bottom left 6..2 R-tile only
+ page 5, channel 5..2 = tile die bottom left 5..2 F-tile only
+ page 5, channel 4..2 = tile die bottom left 4..2 E-tile only
+
+ page 7, channel 0 = tile die top left max
+ page 7, channel 1 = tile die top left 1
+ page 7, channel 6..2 = tile die top left 6..2 R-tile only
+ page 7, channel 5..2 = tile die top left 5..2 F-tile only
+ page 7, channel 4..2 = tile die top left 4..2 E-tile only
+
+ page 8, channel 0 = tile die bottom right max
+ page 8, channel 1 = tile die bottom right 1
+ page 8, channel 6..2 = tile die bottom right 6..2 R-tile only
+ page 8, channel 5..2 = tile die bottom right 5..2 F-tile only
+ page 8, channel 4..2 = tile die bottom right 4..2 E-tile only
+
+ page 10, channel 0 = tile die top right max
+ page 10, channel 1 = tile die top right 1
+ page 10, channel 6..2 = tile die top right 6..2 R-tile only
+ page 10, channel 5..2 = tile die top right 5..2 F-tile only
+ page 10, channel 4..2 = tile die top right 4..2 E-tile only
+
+ N5X Device Family
+
+ N5X Voltage Sensors
+
+ page 0, channel 2 = 0.8V VDD
+ page 0, channel 3 = 0.8V VDD_SDM
+ page 0, channel 4 = 1.8V VCCADC
+ page 0, channel 5 = 1.8V VCCPD
+ page 0, channel 6 = 1.8V VCCIO_SDM
+ page 0, channel 7 = 0.8V VDD_HPS
+
+ N5X Temperature Sensors
+
+ page 0, channel 0 = main die
+
+properties:
+
+ compatible:
+ const: altr,socfpga-hwmon
+
+ temperature:
+ description:
+ The temperature node specifies mappings of temperature sensor diodes on
+ the SoC FPGA main die and tile die.
+ type: object
+ properties:
+ '#address-cells':
+ const: 1
+ '#size-cells':
+ const: 0
+ patternProperties:
+ "^input(@[0-9a-f]+)?$":
+ description:
+ The input node specifies each individual temperature sensor.
+ type: object
+ properties:
+ reg:
+ description:
+ The temperature sensor address format contains a page number and
+ a channel number to identify a specific temperature sensor. The
+ page number selects the region of the device that the sensor
+ resides. The channel number selects the temperature sensor diode
+ in the page. The page number is defined in the upper 16-bits of
+ the reg value while the channel number is defined in the lower
+ 16-bits of the reg value. Channel 0 is represented by the value 0
+ and channel 1 is represented by the value 1, and so on.
+ label:
+ description:
+ A label to describe the sensor.
+ required:
+ - reg
+ additionalProperties: false
+ required:
+ - '#address-cells'
+ - '#size-cells'
+ additionalProperties: false
+
+ voltage:
+ description:
+ The voltage node specifies mappings of voltage sensorson the SoC FPGA
+ analog to digital converter of the Secure Device Manager(SDM).
+ type: object
+ properties:
+ '#address-cells':
+ const: 1
+ '#size-cells':
+ const: 0
+ patternProperties:
+ "^input(@[0-9a-f]+)?$":
+ description:
+ The input node specifies each individual voltage sensor.
+ type: object
+ properties:
+ reg:
+ description:
+ The voltage sensor address format contains a channel number to
+ identify a specific voltage sensor. The channel number is defined
+ in the lower 16-bits of the reg value. Channel 0 is represented by
+ the value 0 and channel 1 is represented by the value 1, and so
+ on.
+ label:
+ description:
+ A label to describe the sensor.
+ required:
+ - reg
+ additionalProperties: false
+ required:
+ - '#address-cells'
+ - '#size-cells'
+ additionalProperties: false
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ temp_volt {
+ compatible = "altr,socfpga-hwmon";
+ voltage {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ input@2 {
+ label = "0.8V VCC";
+ reg = <2>;
+ };
+
+ input@3 {
+ label = "1.8V VCCIO_SDM";
+ reg = <3>;
+ };
+
+ input@4 {
+ label = "1.8V VCCPT";
+ reg = <4>;
+ };
+
+ input@5 {
+ label = "1.2V VCCCRCORE";
+ reg = <5>;
+ };
+
+ input@6 {
+ label = "0.9V VCCH";
+ reg = <6>;
+ };
+
+ input@7 {
+ label = "0.8V VCCL";
+ reg = <7>;
+ };
+ };
+
+ temperature {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ label = "Main Die SDM";
+ reg = <0x0>;
+ };
+
+ input@10001 {
+ label = "Main Die corner bottom left 1";
+ reg = <0x10001>;
+ };
+
+ input@10002 {
+ label = "Main Die corner bottom left 2";
+ reg = <0x10002>;
+ };
+
+ input@20001 {
+ label = "Main Die corner top left 1";
+ reg = <0x20001>;
+ };
+
+ input@20002 {
+ label = "Main Die corner top left 2";
+ reg = <0x20002>;
+ };
+
+ input@30001 {
+ label = "Main Die corner bottom right 1";
+ reg = <0x30001>;
+ };
+
+ input@30002 {
+ label = "Main Die corner bottom right 2";
+ reg = <0x30002>;
+ };
+
+ input@40001 {
+ label = "Main Die corner top right 1 HPS";
+ reg = <0x40001>;
+ };
+
+ input@40002 {
+ label = "Main Die corner top right 2";
+ reg = <0x40002>;
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 5b11839cba9d..8ac7fef4563a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -936,6 +936,13 @@ ALPS PS/2 TOUCHPAD DRIVER
R: Pali Rohár <pali@kernel.org>
F: drivers/input/mouse/alps.*
+ALTERA 64-BIT SOC FPGA HWMON DRIVER
+M: Ang Tien Sung <tiensung.ang@altera.com>
+M: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
+L: linux-hwmon@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml
+
ALTERA MAILBOX DRIVER
M: Tien Sung Ang <tiensung.ang@altera.com>
S: Maintained
--
2.43.7
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v1 1/5] dt-bindings: hwmon: add altr,socfpga-hwmon.yaml binding
2025-12-16 6:49 ` [PATCH v1 1/5] dt-bindings: hwmon: add altr,socfpga-hwmon.yaml binding muhammadamirulasyraf.mohamadjamian
@ 2025-12-18 8:25 ` Krzysztof Kozlowski
2025-12-18 9:57 ` Mohamad Jamian, Muhammad Amirul Asyraf
0 siblings, 1 reply; 13+ messages in thread
From: Krzysztof Kozlowski @ 2025-12-18 8:25 UTC (permalink / raw)
To: muhammadamirulasyraf.mohamadjamian
Cc: Guenter Roeck, linux-hwmon, Dinh Nguyen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel,
Ang Tien Sung, Khairul Anuar Romli
On Mon, Dec 15, 2025 at 10:49:22PM -0800, muhammadamirulasyraf.mohamadjamian@altera.com wrote:
> From: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
>
> The Altera SoCFPGA platform includes a hardware monitoring (hwmon) device
> that reports voltage and temperature sensors critical for system stability
> and safety. Without a proper device tree binding, the kernel and
> userspace tools cannot correctly interpret or configure these sensors.
>
> This binding provides a formal description of the device’s properties,
> including the 'compatible' string for driver matching, voltage and
> temperature parameters with scaling and threshold definitions. This enables
> the kernel to correctly identify the device, interpret sensor data
> accurately, and manage threshold-based events.
>
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> Signed-off-by: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
Please use consistent emails - this does not match sender.
> ---
> .../bindings/hwmon/altr,socfpga-hwmon.yaml | 286 ++++++++++++++++++
> MAINTAINERS | 7 +
> 2 files changed, 293 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml
>
> diff --git a/Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml b/Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml
> new file mode 100644
> index 000000000000..b69611c8bc7d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml
> @@ -0,0 +1,286 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/hwmon/altr,socfpga-hwmon.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Altera Hardware monitor SOC FPGA
"Monitor SoC"
> +
> +maintainers:
> + - Ang Tien Sung <tiensung.ang@altera.com>
> + - Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
> +
> +description: |
> + The Altera SoC FPGA hardware monitor unit provides on-chip voltage and
> + temperature sensors. You can use these sensors to monitor external
> + voltages and on-chip operating conditions such as internal power rails
> + and on-chip junction temperatures.
> +
> + The specific sensor configurations vary for each device family and
> + each device within a family does not offer all potential sensor
> + options. The information below attempts to illustrate the super set of
> + possible sensor options that are potentially available within each
> + device family, but the user should check the documentation for the
> + specific device they are using to verify which sensor options it
> + actually provides.
> +
> + Stratix 10 Device Family
> +
> + Stratix 10 Voltage Sensors
> +
> + page 0, channel 2 = 0.8V VCC
> + page 0, channel 3 = 1.8V VCCIO_SDM
> + page 0, channel 6 = 0.9V VCCERAM
> +
> + Stratix 10 Temperature Sensors
> +
> + page 0, channel 0 = main die
> + page 0, channel 1 = tile bottom left
> + page 0, channel 2 = tile middle left
> + page 0, channel 3 = tile top left
> + page 0, channel 4 = tile bottom right
> + page 0, channel 5 = tile middle right
> + page 0, channel 6 = tile top right
> + page 0, channel 7 = hbm2 bottom
> + page 0, channel 8 = hbm2 top
> +
> + Agilex Device Family
> +
> + Agilex Voltage Sensors
> +
> + page 0, channel 2 = 0.8V VCC
> + page 0, channel 3 = 1.8V VCCIO_SDM
> + page 0, channel 4 = 1.8V VCCPT
> + page 0, channel 5 = 1.2V VCCRCORE
> + page 0, channel 6 = 0.9V VCCH
> + page 0, channel 7 = 0.8V VCCL
> +
> + Agilex Temperature Sensors
> +
> + page 0, channel 0 = main die sdm max
> + page 0, channel 1 = main die sdm 1
> +
> + page 1, channel 0 = main die corner bottom left max
> + page 1, channel 1 = main die corner bottom left 1
> + page 1, channel 2 = main die corner bottom left 2
> +
> + page 2, channel 0 = main die corner top left max
> + page 2, channel 1 = main die corner top left 1
> + page 2, channel 2 = main die corner top left 2
> +
> + page 3, channel 0 = main die corner bottom right max
> + page 3, channel 1 = main die corner bottom right 1
> + page 3, channel 2 = main die corner bottom right 2
> +
> + page 4, channel 0 = main die corner top right max
> + page 4, channel 1 = main die corner top right 1
> + page 4, channel 2 = main die corner top right 2
> +
> + page 5, channel 0 = tile die bottom left max
> + page 5, channel 1 = tile die bottom left 1
> + page 5, channel 6..2 = tile die bottom left 6..2 R-tile only
> + page 5, channel 5..2 = tile die bottom left 5..2 F-tile only
> + page 5, channel 4..2 = tile die bottom left 4..2 E-tile only
> +
> + page 7, channel 0 = tile die top left max
> + page 7, channel 1 = tile die top left 1
> + page 7, channel 6..2 = tile die top left 6..2 R-tile only
> + page 7, channel 5..2 = tile die top left 5..2 F-tile only
> + page 7, channel 4..2 = tile die top left 4..2 E-tile only
> +
> + page 8, channel 0 = tile die bottom right max
> + page 8, channel 1 = tile die bottom right 1
> + page 8, channel 6..2 = tile die bottom right 6..2 R-tile only
> + page 8, channel 5..2 = tile die bottom right 5..2 F-tile only
> + page 8, channel 4..2 = tile die bottom right 4..2 E-tile only
> +
> + page 10, channel 0 = tile die top right max
> + page 10, channel 1 = tile die top right 1
> + page 10, channel 6..2 = tile die top right 6..2 R-tile only
> + page 10, channel 5..2 = tile die top right 5..2 F-tile only
> + page 10, channel 4..2 = tile die top right 4..2 E-tile only
> +
> + N5X Device Family
> +
> + N5X Voltage Sensors
> +
> + page 0, channel 2 = 0.8V VDD
> + page 0, channel 3 = 0.8V VDD_SDM
> + page 0, channel 4 = 1.8V VCCADC
> + page 0, channel 5 = 1.8V VCCPD
> + page 0, channel 6 = 1.8V VCCIO_SDM
> + page 0, channel 7 = 0.8V VDD_HPS
> +
> + N5X Temperature Sensors
> +
> + page 0, channel 0 = main die
> +
> +properties:
> +
No blank line
> + compatible:
> + const: altr,socfpga-hwmon
No, look at other bindings. You need soc specific compatibles.
> +
> + temperature:
> + description:
> + The temperature node specifies mappings of temperature sensor diodes on
> + the SoC FPGA main die and tile die.
> + type: object
> + properties:
> + '#address-cells':
> + const: 1
> + '#size-cells':
> + const: 0
> + patternProperties:
> + "^input(@[0-9a-f]+)?$":
> + description:
> + The input node specifies each individual temperature sensor.
> + type: object
> + properties:
> + reg:
> + description:
> + The temperature sensor address format contains a page number and
> + a channel number to identify a specific temperature sensor. The
> + page number selects the region of the device that the sensor
> + resides. The channel number selects the temperature sensor diode
> + in the page. The page number is defined in the upper 16-bits of
> + the reg value while the channel number is defined in the lower
> + 16-bits of the reg value. Channel 0 is represented by the value 0
> + and channel 1 is represented by the value 1, and so on.
> + label:
> + description:
> + A label to describe the sensor.
> + required:
> + - reg
> + additionalProperties: false
> + required:
> + - '#address-cells'
> + - '#size-cells'
> + additionalProperties: false
None of above is readable. Why are you sending completely different code
than what we have in the kernel?
> +
> + voltage:
> + description:
> + The voltage node specifies mappings of voltage sensorson the SoC FPGA
> + analog to digital converter of the Secure Device Manager(SDM).
> + type: object
> + properties:
> + '#address-cells':
> + const: 1
> + '#size-cells':
> + const: 0
> + patternProperties:
> + "^input(@[0-9a-f]+)?$":
> + description:
> + The input node specifies each individual voltage sensor.
> + type: object
> + properties:
> + reg:
> + description:
> + The voltage sensor address format contains a channel number to
> + identify a specific voltage sensor. The channel number is defined
> + in the lower 16-bits of the reg value. Channel 0 is represented by
> + the value 0 and channel 1 is represented by the value 1, and so
> + on.
> + label:
> + description:
> + A label to describe the sensor.
> + required:
> + - reg
> + additionalProperties: false
> + required:
> + - '#address-cells'
> + - '#size-cells'
> + additionalProperties: false
> +
> +required:
> + - compatible
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + temp_volt {
No, don't send us downstream code. Look at upstream how this is called.
Read carefully writing bindings and writing schema doc. You sent
something really needing internal review before posting.
It's another example of recently poor submissions from Altera. I am
getting tired of pointing out the same problem - you do not perform
internal review prior posting.
Is anyone from Altera going to respond on this? If not, I will just be
grumpy NAKing your patches, because such way you just waste community's
time.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v1 1/5] dt-bindings: hwmon: add altr,socfpga-hwmon.yaml binding
2025-12-18 8:25 ` Krzysztof Kozlowski
@ 2025-12-18 9:57 ` Mohamad Jamian, Muhammad Amirul Asyraf
0 siblings, 0 replies; 13+ messages in thread
From: Mohamad Jamian, Muhammad Amirul Asyraf @ 2025-12-18 9:57 UTC (permalink / raw)
To: Krzysztof Kozlowski, Mohamad Jamian, Muhammad Amirul Asyraf
Cc: Guenter Roeck, linux-hwmon, Dinh Nguyen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel, Ang,
Tien Sung, Romli, Khairul Anuar
On 18/12/2025 4:25 pm, Krzysztof Kozlowski wrote:
> On Mon, Dec 15, 2025 at 10:49:22PM -0800, muhammadamirulasyraf.mohamadjamian@altera.com wrote:
>> From: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
>>
>> The Altera SoCFPGA platform includes a hardware monitoring (hwmon) device
>> that reports voltage and temperature sensors critical for system stability
>> and safety. Without a proper device tree binding, the kernel and
>> userspace tools cannot correctly interpret or configure these sensors.
>>
>> This binding provides a formal description of the device’s properties,
>> including the 'compatible' string for driver matching, voltage and
>> temperature parameters with scaling and threshold definitions. This enables
>> the kernel to correctly identify the device, interpret sensor data
>> accurately, and manage threshold-based events.
>>
>> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>> Signed-off-by: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
>
> Please use consistent emails - this does not match sender.
>
>> ---
>> .../bindings/hwmon/altr,socfpga-hwmon.yaml | 286 ++++++++++++++++++
>> MAINTAINERS | 7 +
>> 2 files changed, 293 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml b/Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml
>> new file mode 100644
>> index 000000000000..b69611c8bc7d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml
>> @@ -0,0 +1,286 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/hwmon/altr,socfpga-hwmon.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Altera Hardware monitor SOC FPGA
>
> "Monitor SoC"
>
>> +
>> +maintainers:
>> + - Ang Tien Sung <tiensung.ang@altera.com>
>> + - Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
>> +
>> +description: |
>> + The Altera SoC FPGA hardware monitor unit provides on-chip voltage and
>> + temperature sensors. You can use these sensors to monitor external
>> + voltages and on-chip operating conditions such as internal power rails
>> + and on-chip junction temperatures.
>> +
>> + The specific sensor configurations vary for each device family and
>> + each device within a family does not offer all potential sensor
>> + options. The information below attempts to illustrate the super set of
>> + possible sensor options that are potentially available within each
>> + device family, but the user should check the documentation for the
>> + specific device they are using to verify which sensor options it
>> + actually provides.
>> +
>> + Stratix 10 Device Family
>> +
>> + Stratix 10 Voltage Sensors
>> +
>> + page 0, channel 2 = 0.8V VCC
>> + page 0, channel 3 = 1.8V VCCIO_SDM
>> + page 0, channel 6 = 0.9V VCCERAM
>> +
>> + Stratix 10 Temperature Sensors
>> +
>> + page 0, channel 0 = main die
>> + page 0, channel 1 = tile bottom left
>> + page 0, channel 2 = tile middle left
>> + page 0, channel 3 = tile top left
>> + page 0, channel 4 = tile bottom right
>> + page 0, channel 5 = tile middle right
>> + page 0, channel 6 = tile top right
>> + page 0, channel 7 = hbm2 bottom
>> + page 0, channel 8 = hbm2 top
>> +
>> + Agilex Device Family
>> +
>> + Agilex Voltage Sensors
>> +
>> + page 0, channel 2 = 0.8V VCC
>> + page 0, channel 3 = 1.8V VCCIO_SDM
>> + page 0, channel 4 = 1.8V VCCPT
>> + page 0, channel 5 = 1.2V VCCRCORE
>> + page 0, channel 6 = 0.9V VCCH
>> + page 0, channel 7 = 0.8V VCCL
>> +
>> + Agilex Temperature Sensors
>> +
>> + page 0, channel 0 = main die sdm max
>> + page 0, channel 1 = main die sdm 1
>> +
>> + page 1, channel 0 = main die corner bottom left max
>> + page 1, channel 1 = main die corner bottom left 1
>> + page 1, channel 2 = main die corner bottom left 2
>> +
>> + page 2, channel 0 = main die corner top left max
>> + page 2, channel 1 = main die corner top left 1
>> + page 2, channel 2 = main die corner top left 2
>> +
>> + page 3, channel 0 = main die corner bottom right max
>> + page 3, channel 1 = main die corner bottom right 1
>> + page 3, channel 2 = main die corner bottom right 2
>> +
>> + page 4, channel 0 = main die corner top right max
>> + page 4, channel 1 = main die corner top right 1
>> + page 4, channel 2 = main die corner top right 2
>> +
>> + page 5, channel 0 = tile die bottom left max
>> + page 5, channel 1 = tile die bottom left 1
>> + page 5, channel 6..2 = tile die bottom left 6..2 R-tile only
>> + page 5, channel 5..2 = tile die bottom left 5..2 F-tile only
>> + page 5, channel 4..2 = tile die bottom left 4..2 E-tile only
>> +
>> + page 7, channel 0 = tile die top left max
>> + page 7, channel 1 = tile die top left 1
>> + page 7, channel 6..2 = tile die top left 6..2 R-tile only
>> + page 7, channel 5..2 = tile die top left 5..2 F-tile only
>> + page 7, channel 4..2 = tile die top left 4..2 E-tile only
>> +
>> + page 8, channel 0 = tile die bottom right max
>> + page 8, channel 1 = tile die bottom right 1
>> + page 8, channel 6..2 = tile die bottom right 6..2 R-tile only
>> + page 8, channel 5..2 = tile die bottom right 5..2 F-tile only
>> + page 8, channel 4..2 = tile die bottom right 4..2 E-tile only
>> +
>> + page 10, channel 0 = tile die top right max
>> + page 10, channel 1 = tile die top right 1
>> + page 10, channel 6..2 = tile die top right 6..2 R-tile only
>> + page 10, channel 5..2 = tile die top right 5..2 F-tile only
>> + page 10, channel 4..2 = tile die top right 4..2 E-tile only
>> +
>> + N5X Device Family
>> +
>> + N5X Voltage Sensors
>> +
>> + page 0, channel 2 = 0.8V VDD
>> + page 0, channel 3 = 0.8V VDD_SDM
>> + page 0, channel 4 = 1.8V VCCADC
>> + page 0, channel 5 = 1.8V VCCPD
>> + page 0, channel 6 = 1.8V VCCIO_SDM
>> + page 0, channel 7 = 0.8V VDD_HPS
>> +
>> + N5X Temperature Sensors
>> +
>> + page 0, channel 0 = main die
>> +
>> +properties:
>> +
>
> No blank line
>
>> + compatible:
>> + const: altr,socfpga-hwmon
>
> No, look at other bindings. You need soc specific compatibles.
>
>> +
>> + temperature:
>> + description:
>> + The temperature node specifies mappings of temperature sensor diodes on
>> + the SoC FPGA main die and tile die.
>> + type: object
>> + properties:
>> + '#address-cells':
>> + const: 1
>> + '#size-cells':
>> + const: 0
>> + patternProperties:
>> + "^input(@[0-9a-f]+)?$":
>> + description:
>> + The input node specifies each individual temperature sensor.
>> + type: object
>> + properties:
>> + reg:
>> + description:
>> + The temperature sensor address format contains a page number and
>> + a channel number to identify a specific temperature sensor. The
>> + page number selects the region of the device that the sensor
>> + resides. The channel number selects the temperature sensor diode
>> + in the page. The page number is defined in the upper 16-bits of
>> + the reg value while the channel number is defined in the lower
>> + 16-bits of the reg value. Channel 0 is represented by the value 0
>> + and channel 1 is represented by the value 1, and so on.
>> + label:
>> + description:
>> + A label to describe the sensor.
>> + required:
>> + - reg
>> + additionalProperties: false
>> + required:
>> + - '#address-cells'
>> + - '#size-cells'
>> + additionalProperties: false
>
> None of above is readable. Why are you sending completely different code
> than what we have in the kernel?
>
>
>> +
>> + voltage:
>> + description:
>> + The voltage node specifies mappings of voltage sensorson the SoC FPGA
>> + analog to digital converter of the Secure Device Manager(SDM).
>> + type: object
>> + properties:
>> + '#address-cells':
>> + const: 1
>> + '#size-cells':
>> + const: 0
>> + patternProperties:
>> + "^input(@[0-9a-f]+)?$":
>> + description:
>> + The input node specifies each individual voltage sensor.
>> + type: object
>> + properties:
>> + reg:
>> + description:
>> + The voltage sensor address format contains a channel number to
>> + identify a specific voltage sensor. The channel number is defined
>> + in the lower 16-bits of the reg value. Channel 0 is represented by
>> + the value 0 and channel 1 is represented by the value 1, and so
>> + on.
>> + label:
>> + description:
>> + A label to describe the sensor.
>> + required:
>> + - reg
>> + additionalProperties: false
>> + required:
>> + - '#address-cells'
>> + - '#size-cells'
>> + additionalProperties: false
>> +
>> +required:
>> + - compatible
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + temp_volt {
>
> No, don't send us downstream code. Look at upstream how this is called.
>
> Read carefully writing bindings and writing schema doc. You sent
> something really needing internal review before posting.
>
> It's another example of recently poor submissions from Altera. I am
> getting tired of pointing out the same problem - you do not perform
> internal review prior posting.
>
> Is anyone from Altera going to respond on this? If not, I will just be
> grumpy NAKing your patches, because such way you just waste community's
> time.
>
> Best regards,
> Krzysztof
>
Thanks for the response,
Will rework the patches based on the feedback and send for internal
review before sending out the next version.
Regards,
Amirul
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v1 2/5] dt-bindings: firmware: svc: add hwmon property
2025-12-16 6:49 [PATCH v1 0/5] hwmon: Add support for Altera SoCFPGA hardware monitoring muhammadamirulasyraf.mohamadjamian
2025-12-16 6:49 ` [PATCH v1 1/5] dt-bindings: hwmon: add altr,socfpga-hwmon.yaml binding muhammadamirulasyraf.mohamadjamian
@ 2025-12-16 6:49 ` muhammadamirulasyraf.mohamadjamian
2025-12-18 8:26 ` Krzysztof Kozlowski
2025-12-16 6:49 ` [PATCH v1 3/5] hwmon: (altr-hwmon): Add initial support for SoCFPGA muhammadamirulasyraf.mohamadjamian
` (2 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: muhammadamirulasyraf.mohamadjamian @ 2025-12-16 6:49 UTC (permalink / raw)
To: Guenter Roeck, linux-hwmon, Dinh Nguyen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel,
Ang Tien Sung, Khairul Anuar Romli
From: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
Altera SoCFPGA support hardware monitor feature through mailbox. Hence,
hwmon property has to be added to the DT to enable the feature beside the
hwmon bindings and driver.
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Signed-off-by: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
---
.../devicetree/bindings/firmware/intel,stratix10-svc.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
index b42cfa78b28b..4767904c7b76 100644
--- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
+++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
@@ -62,6 +62,10 @@ properties:
$ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml
description: Optional child node for fpga manager to perform fabric configuration.
+ hwmon:
+ $ref: /schemas/hwmon/altr,socfpga-hwmon.yaml
+ description: Optional child node for hardware monitor to altera socfpga.
+
required:
- compatible
- method
--
2.43.7
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v1 2/5] dt-bindings: firmware: svc: add hwmon property
2025-12-16 6:49 ` [PATCH v1 2/5] dt-bindings: firmware: svc: add hwmon property muhammadamirulasyraf.mohamadjamian
@ 2025-12-18 8:26 ` Krzysztof Kozlowski
2025-12-18 9:57 ` Mohamad Jamian, Muhammad Amirul Asyraf
0 siblings, 1 reply; 13+ messages in thread
From: Krzysztof Kozlowski @ 2025-12-18 8:26 UTC (permalink / raw)
To: muhammadamirulasyraf.mohamadjamian
Cc: Guenter Roeck, linux-hwmon, Dinh Nguyen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel,
Ang Tien Sung, Khairul Anuar Romli
On Mon, Dec 15, 2025 at 10:49:23PM -0800, muhammadamirulasyraf.mohamadjamian@altera.com wrote:
> From: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
>
> Altera SoCFPGA support hardware monitor feature through mailbox. Hence,
> hwmon property has to be added to the DT to enable the feature beside the
> hwmon bindings and driver.
>
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> Signed-off-by: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
> ---
> .../devicetree/bindings/firmware/intel,stratix10-svc.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
> index b42cfa78b28b..4767904c7b76 100644
> --- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
> +++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
> @@ -62,6 +62,10 @@ properties:
> $ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml
> description: Optional child node for fpga manager to perform fabric configuration.
>
> + hwmon:
> + $ref: /schemas/hwmon/altr,socfpga-hwmon.yaml
This cannot be applied alone and you did not describe merging
dependencies anywhere.
Squash the patches or be explicit how this must be merged.
Other patches from Altera have exactly the same problem, so you keep
repeating the same.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1 2/5] dt-bindings: firmware: svc: add hwmon property
2025-12-18 8:26 ` Krzysztof Kozlowski
@ 2025-12-18 9:57 ` Mohamad Jamian, Muhammad Amirul Asyraf
0 siblings, 0 replies; 13+ messages in thread
From: Mohamad Jamian, Muhammad Amirul Asyraf @ 2025-12-18 9:57 UTC (permalink / raw)
To: Krzysztof Kozlowski, Mohamad Jamian, Muhammad Amirul Asyraf
Cc: Guenter Roeck, linux-hwmon, Dinh Nguyen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel, Ang,
Tien Sung, Romli, Khairul Anuar
On 18/12/2025 4:26 pm, Krzysztof Kozlowski wrote:
> On Mon, Dec 15, 2025 at 10:49:23PM -0800, muhammadamirulasyraf.mohamadjamian@altera.com wrote:
>> From: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
>>
>> Altera SoCFPGA support hardware monitor feature through mailbox. Hence,
>> hwmon property has to be added to the DT to enable the feature beside the
>> hwmon bindings and driver.
>>
>> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>> Signed-off-by: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
>> ---
>> .../devicetree/bindings/firmware/intel,stratix10-svc.yaml | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
>> index b42cfa78b28b..4767904c7b76 100644
>> --- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
>> +++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
>> @@ -62,6 +62,10 @@ properties:
>> $ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml
>> description: Optional child node for fpga manager to perform fabric configuration.
>>
>> + hwmon:
>> + $ref: /schemas/hwmon/altr,socfpga-hwmon.yaml
>
> This cannot be applied alone and you did not describe merging
> dependencies anywhere.
>
> Squash the patches or be explicit how this must be merged.
>
> Other patches from Altera have exactly the same problem, so you keep
> repeating the same.
>
>
> Best regards,
> Krzysztof
>
Will squash this with PATCH 1/5 for adding dt-binding.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v1 3/5] hwmon: (altr-hwmon): Add initial support for SoCFPGA
2025-12-16 6:49 [PATCH v1 0/5] hwmon: Add support for Altera SoCFPGA hardware monitoring muhammadamirulasyraf.mohamadjamian
2025-12-16 6:49 ` [PATCH v1 1/5] dt-bindings: hwmon: add altr,socfpga-hwmon.yaml binding muhammadamirulasyraf.mohamadjamian
2025-12-16 6:49 ` [PATCH v1 2/5] dt-bindings: firmware: svc: add hwmon property muhammadamirulasyraf.mohamadjamian
@ 2025-12-16 6:49 ` muhammadamirulasyraf.mohamadjamian
2025-12-18 8:29 ` Krzysztof Kozlowski
2025-12-22 11:34 ` kernel test robot
2025-12-16 6:49 ` [PATCH v1 4/5] arm64: dts: socfpga: stratix10: Add hwmon node muhammadamirulasyraf.mohamadjamian
2025-12-16 6:49 ` [PATCH v1 5/5] arm64: dts: socfpga: agilex: " muhammadamirulasyraf.mohamadjamian
4 siblings, 2 replies; 13+ messages in thread
From: muhammadamirulasyraf.mohamadjamian @ 2025-12-16 6:49 UTC (permalink / raw)
To: Guenter Roeck, linux-hwmon, Dinh Nguyen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel,
Ang Tien Sung, Khairul Anuar Romli
From: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
This patch introduces a new hardware monitoring (hwmon) driver for the
Altera SoCFPGA platform, enabling kernel support for monitoring voltage and
temperature sensors critical for device health and system stability.
Changes include:
- New driver implementation 'drivers/hwmon/altera-hwmon.c' providing sensor
reading and event handling capabilities tailored for SoCFPGA hardware.
- Build system integration by adding Kconfig and Makefile entries, allowing
users to enable the driver in kernel configuration.
- Documentation added in 'Documentation/hwmon/altera-hwmon.rst', detailing
driver features, usage instructions, device tree bindings, and
configuration options.
- Update to 'Documentation/hwmon/index.rst' to reference the new driver
documentation, improving discoverability and user guidance.
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Signed-off-by: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
---
Documentation/hwmon/altr-hwmon.rst | 32 +++
Documentation/hwmon/index.rst | 1 +
MAINTAINERS | 2 +
drivers/hwmon/Kconfig | 10 +
drivers/hwmon/Makefile | 1 +
drivers/hwmon/altr-hwmon.c | 427 +++++++++++++++++++++++++++++
6 files changed, 473 insertions(+)
create mode 100644 Documentation/hwmon/altr-hwmon.rst
create mode 100644 drivers/hwmon/altr-hwmon.c
diff --git a/Documentation/hwmon/altr-hwmon.rst b/Documentation/hwmon/altr-hwmon.rst
new file mode 100644
index 000000000000..3ef1ca0d1686
--- /dev/null
+++ b/Documentation/hwmon/altr-hwmon.rst
@@ -0,0 +1,32 @@
+.. SPDX-License-Identifier: GPL-2.0
+Kernel driver altr-hwmon
+=========================
+
+Supported chips:
+
+ * Intel N5X
+ * Stratix10
+ * Agilex
+ * Agilex5
+
+Contributor: Kris Chaplin <kris.chaplin@intel.com>
+ Khairul Anuar Romli <khairul.anuar.romli@altera.com>
+ Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
+
+Description
+-----------
+
+This driver supports hardware monitoring for 64-Bit SoC FPGA and eASIC devices
+based around the Secure Device Manager and Stratix 10 Service layer.
+
+The following sensor types are supported
+
+ * temperature
+ * voltage
+
+
+Usage Notes
+-----------
+
+The driver relies on a device tree node to enumerate support present on the
+specific device. See Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml for details of the device-tree node.
diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index 85d7a686883e..d37d4cbbe8b5 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -40,6 +40,7 @@ Hardware Monitoring Kernel Drivers
adt7470
adt7475
aht10
+ altr-hwmon
amc6821
aquacomputer_d5next
asb100
diff --git a/MAINTAINERS b/MAINTAINERS
index 8ac7fef4563a..01f776fdbf6f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -942,6 +942,8 @@ M: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@
L: linux-hwmon@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml
+F: Documentation/hwmon/altr-hwmon.rst
+F: drivers/hwmon/altr-hwmon.c
ALTERA MAILBOX DRIVER
M: Tien Sung Ang <tiensung.ang@altera.com>
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index d9bac1e3057b..4351725831d3 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -2122,6 +2122,16 @@ config SENSORS_SMSC47M192
This driver can also be built as a module. If so, the module
will be called smsc47m192.
+config SENSORS_ALTERA_SOCFPGA
+ tristate "Altera SoC FPGA Hardware monitoring features"
+ depends on INTEL_STRATIX10_SERVICE
+ help
+ If you say yes here you get support for the temperature and
+ voltage sensors of Altera SoC FPGA devices.
+
+ This driver can also be built as a module. If so, the module
+ will be called altera-hwmon
+
config SENSORS_SMSC47B397
tristate "SMSC LPC47B397-NC"
depends on HAS_IOPORT
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index eade8e3b1bde..4ae4726bd0cb 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -218,6 +218,7 @@ obj-$(CONFIG_SENSORS_SMPRO) += smpro-hwmon.o
obj-$(CONFIG_SENSORS_SMSC47B397)+= smsc47b397.o
obj-$(CONFIG_SENSORS_SMSC47M1) += smsc47m1.o
obj-$(CONFIG_SENSORS_SMSC47M192)+= smsc47m192.o
+obj-$(CONFIG_SENSORS_ALTERA_SOCFPGA) += altr-hwmon.o
obj-$(CONFIG_SENSORS_SPARX5) += sparx5-temp.o
obj-$(CONFIG_SENSORS_SPD5118) += spd5118.o
obj-$(CONFIG_SENSORS_STTS751) += stts751.o
diff --git a/drivers/hwmon/altr-hwmon.c b/drivers/hwmon/altr-hwmon.c
new file mode 100644
index 000000000000..beecfa8537a4
--- /dev/null
+++ b/drivers/hwmon/altr-hwmon.c
@@ -0,0 +1,427 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Altera SoC FPGA hardware monitoring driver
+ *
+ * Copyright (c) 2021 Intel Corporation. All rights reserved
+ * Copyright (c) 2025 Altera Corporation. All rights reserved
+ *
+ * Contributors:
+ * Kris Chaplin <kris.chaplin@intel.com>
+ * Ang Tien Sung <tiensung.ang@altera.com>
+ * Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
+ * Khairul Anuar Romli <khairul.anuar.romli@altera.com>
+ * Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
+ */
+
+#include <linux/arm-smccc.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/module.h>
+#include <linux/firmware/intel/stratix10-svc-client.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#define HWMON_TIMEOUT (msecs_to_jiffies(SVC_HWMON_REQUEST_TIMEOUT_MS))
+
+#define ETEMP_INACTIVE 0x80000000
+#define ETEMP_TOO_OLD 0x80000001
+#define ETEMP_NOT_PRESENT 0x80000002
+#define ETEMP_TIMEOUT 0x80000003
+#define ETEMP_CORRUPT 0x80000004
+#define ETEMP_BUSY 0x80000005
+#define ETEMP_NOT_INITIALIZED 0x800000FF
+
+#define ALTR_SOCFPGA_HWMON_MAXSENSORS 16
+#define ALTR_SOCFPGA_HWMON_TEMPERATURE "temperature"
+#define ALTR_SOCFPGA_HWMON_VOLTAGE "voltage"
+
+struct altr_socfpga_hwmon_priv {
+ struct stratix10_svc_chan *chan;
+ struct stratix10_svc_client client;
+ struct completion completion;
+ struct mutex lock; /* protect fpga mailbox access */
+ int temperature;
+ int voltage;
+ int temperature_channels;
+ int voltage_channels;
+ const char *altr_socfpga_volt_chan_names[ALTR_SOCFPGA_HWMON_MAXSENSORS];
+ const char *altr_socfpga_temp_chan_names[ALTR_SOCFPGA_HWMON_MAXSENSORS];
+ u32 altr_socfpga_volt_chan[ALTR_SOCFPGA_HWMON_MAXSENSORS];
+ u32 altr_socfpga_temp_chan[ALTR_SOCFPGA_HWMON_MAXSENSORS];
+};
+
+static umode_t altr_socfpga_is_visible(const void *dev,
+ enum hwmon_sensor_types type,
+ u32 attr, int chan)
+{
+ const struct altr_socfpga_hwmon_priv *priv = dev;
+
+ switch (type) {
+ case hwmon_temp:
+ if (chan < priv->temperature_channels)
+ return 0444;
+
+ return 0;
+ case hwmon_in:
+ if (chan < priv->voltage_channels)
+ return 0444;
+
+ return 0;
+
+ default:
+ return 0;
+ }
+}
+
+static void altr_socfpga_readtemp_smc_callback(struct stratix10_svc_client *client,
+ struct stratix10_svc_cb_data *data)
+{
+ struct altr_socfpga_hwmon_priv *priv = client->priv;
+ struct arm_smccc_res *res = (struct arm_smccc_res *)data->kaddr1;
+
+ if (data->status == BIT(SVC_STATUS_OK)) {
+ priv->temperature = res->a0;
+ } else {
+ dev_err(client->dev, "%s returned 0x%lX\n",
+ __func__, res->a0);
+ }
+
+ complete(&priv->completion);
+}
+
+static void altr_socfpga_readvolt_smc_callback(struct stratix10_svc_client *client,
+ struct stratix10_svc_cb_data *data)
+{
+ struct altr_socfpga_hwmon_priv *priv = client->priv;
+ struct arm_smccc_res *res = (struct arm_smccc_res *)data->kaddr1;
+
+ if (data->status == BIT(SVC_STATUS_OK)) {
+ priv->voltage = res->a0;
+ } else {
+ dev_err(client->dev, "%s returned 0x%lX\n",
+ __func__, res->a0);
+ }
+
+ complete(&priv->completion);
+}
+
+static int altr_socfpga_read(struct device *dev, enum hwmon_sensor_types type,
+ u32 attr, int chan, long *val)
+{
+ struct altr_socfpga_hwmon_priv *priv = dev_get_drvdata(dev);
+ struct stratix10_svc_client_msg msg;
+ int ret;
+
+ mutex_lock(&priv->lock);
+
+ reinit_completion(&priv->completion);
+
+ switch (type) {
+ case hwmon_temp:
+ if (chan > 15)
+ return -EOPNOTSUPP;
+
+ /* To support Page at upper word and channel at lower word */
+ msg.arg[0] = (((u64)1 << (priv->altr_socfpga_temp_chan[chan] & 0xFFFF))
+ + (priv->altr_socfpga_temp_chan[chan] & 0xFFF0000));
+ priv->client.receive_cb = altr_socfpga_readtemp_smc_callback;
+ msg.command = COMMAND_HWMON_READTEMP;
+
+ ret = stratix10_svc_send(priv->chan, &msg);
+ if (ret < 0)
+ goto status_done;
+
+ ret = wait_for_completion_interruptible_timeout(&priv->completion,
+ HWMON_TIMEOUT);
+
+ if (!ret) {
+ dev_err(priv->client.dev,
+ "timeout waiting for SMC call\n");
+ ret = -ETIMEDOUT;
+ goto status_done;
+ } else if (ret < 0) {
+ dev_err(priv->client.dev,
+ "error %d waiting for SMC call\n", ret);
+ goto status_done;
+ } else {
+ ret = 0;
+ }
+
+ *val = ((long)(priv->temperature)) * 1000 / 256;
+
+ switch (priv->temperature) {
+ case ETEMP_INACTIVE:
+ case ETEMP_NOT_PRESENT:
+ case ETEMP_CORRUPT:
+ case ETEMP_NOT_INITIALIZED:
+ ret = -EOPNOTSUPP;
+ break;
+
+ case ETEMP_TIMEOUT:
+ case ETEMP_BUSY:
+ case ETEMP_TOO_OLD:
+ ret = -EAGAIN;
+ break;
+ default:
+ ret = 0;
+ break;
+ }
+
+ break;
+
+ case hwmon_in: // Read voltage
+ if (chan > 15)
+ return -EOPNOTSUPP; // Channel outside of range
+
+ msg.arg[0] = ((u64)1 << priv->altr_socfpga_volt_chan[chan]);
+ priv->client.receive_cb = altr_socfpga_readvolt_smc_callback;
+ msg.command = COMMAND_HWMON_READVOLT;
+
+ ret = stratix10_svc_send(priv->chan, &msg);
+ if (ret < 0)
+ goto status_done;
+
+ ret = wait_for_completion_interruptible_timeout(&priv->completion,
+ HWMON_TIMEOUT);
+
+ if (!ret) {
+ dev_err(priv->client.dev,
+ "timeout waiting for SMC call\n");
+ ret = -ETIMEDOUT;
+ goto status_done;
+ } else if (ret < 0) {
+ dev_err(priv->client.dev,
+ "error %d waiting for SMC call\n", ret);
+ goto status_done;
+ } else {
+ ret = 0;
+ }
+
+ *val = ((long)(priv->voltage)) * 1000 / 65536;
+ ret = 0;
+ break;
+
+ default:
+ ret = -EOPNOTSUPP;
+ break;
+ }
+
+status_done:
+ stratix10_svc_done(priv->chan);
+ mutex_unlock(&priv->lock);
+ return ret;
+}
+
+static int altr_socfpga_read_string(struct device *dev,
+ enum hwmon_sensor_types type, u32 attr,
+ int chan, const char **str)
+{
+ struct altr_socfpga_hwmon_priv *priv = dev_get_drvdata(dev);
+
+ switch (type) {
+ case hwmon_in:
+ *str = priv->altr_socfpga_volt_chan_names[chan];
+ return 0;
+ case hwmon_temp:
+ *str = priv->altr_socfpga_temp_chan_names[chan];
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static const struct hwmon_ops altr_socfpga_hwmon_ops = {
+ .is_visible = altr_socfpga_is_visible,
+ .read = altr_socfpga_read,
+ .read_string = altr_socfpga_read_string,
+};
+
+static const struct hwmon_channel_info *altr_socfpga_hwmon_info[] = {
+ HWMON_CHANNEL_INFO(temp,
+ HWMON_T_INPUT | HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL),
+ HWMON_CHANNEL_INFO(in,
+ HWMON_I_INPUT | HWMON_I_LABEL, HWMON_I_INPUT | HWMON_I_LABEL,
+ HWMON_I_INPUT | HWMON_I_LABEL, HWMON_I_INPUT | HWMON_I_LABEL,
+ HWMON_I_INPUT | HWMON_I_LABEL, HWMON_I_INPUT | HWMON_I_LABEL,
+ HWMON_I_INPUT | HWMON_I_LABEL, HWMON_I_INPUT | HWMON_I_LABEL,
+ HWMON_I_INPUT | HWMON_I_LABEL, HWMON_I_INPUT | HWMON_I_LABEL,
+ HWMON_I_INPUT | HWMON_I_LABEL, HWMON_I_INPUT | HWMON_I_LABEL,
+ HWMON_I_INPUT | HWMON_I_LABEL, HWMON_I_INPUT | HWMON_I_LABEL,
+ HWMON_I_INPUT | HWMON_I_LABEL, HWMON_I_INPUT | HWMON_I_LABEL),
+ NULL
+};
+
+static const struct hwmon_chip_info altr_socfpga_hwmon_chip_info = {
+ .ops = &altr_socfpga_hwmon_ops,
+ .info = altr_socfpga_hwmon_info,
+};
+
+static int altr_socfpga_add_channel(struct device *dev, const char *type,
+ u32 val, const char *label,
+ struct altr_socfpga_hwmon_priv *priv)
+{
+ if (!strcmp(type, ALTR_SOCFPGA_HWMON_TEMPERATURE)) {
+ if (priv->temperature_channels >= ALTR_SOCFPGA_HWMON_MAXSENSORS) {
+ dev_warn(dev,
+ "Can't add temp node %s, too many channels",
+ label);
+ return 0;
+ }
+
+ priv->altr_socfpga_temp_chan_names[priv->temperature_channels] = label;
+ priv->altr_socfpga_temp_chan[priv->temperature_channels] = val;
+ priv->temperature_channels++;
+ return 0;
+ }
+
+ if (!strcmp(type, ALTR_SOCFPGA_HWMON_VOLTAGE)) {
+ if (priv->voltage_channels >= ALTR_SOCFPGA_HWMON_MAXSENSORS) {
+ dev_warn(dev,
+ "Can't add voltage node %s, too many channels",
+ label);
+ return 0;
+ }
+
+ priv->altr_socfpga_volt_chan_names[priv->voltage_channels] = label;
+ priv->altr_socfpga_volt_chan[priv->voltage_channels] = val;
+ priv->voltage_channels++;
+ return 0;
+ }
+
+ dev_warn(dev, "unsupported sensor type %s", type);
+ return 0;
+}
+
+static int altr_socfpga_probe_child_from_dt(struct device *dev,
+ struct device_node *child,
+ struct altr_socfpga_hwmon_priv *priv)
+{
+ u32 val;
+ int ret;
+ struct device_node *grandchild;
+ const char *label;
+ const char *type;
+
+ of_property_read_string(child, "name", &type);
+ for_each_child_of_node(child, grandchild) {
+ ret = of_property_read_u32(grandchild, "reg", &val);
+ if (ret) {
+ dev_err(dev, "missing reg property of %pOFn\n",
+ grandchild);
+ return ret;
+ }
+ ret = of_property_read_string(grandchild, "label", &label);
+ if (ret) {
+ dev_err(dev, "missing label propoerty of %pOFn\n",
+ grandchild);
+ return ret;
+ }
+
+ altr_socfpga_add_channel(dev, type, val, label, priv);
+ }
+
+ return 0;
+}
+
+static int altr_socfpga_probe_from_dt(struct device *dev,
+ struct altr_socfpga_hwmon_priv *priv)
+{
+ const struct device_node *np = dev->of_node;
+ struct device_node *child;
+ int ret;
+
+ /* Compatible with non-DT platforms */
+ if (!np)
+ return 0;
+
+ for_each_child_of_node(np, child) {
+ ret = altr_socfpga_probe_child_from_dt(dev, child, priv);
+ if (ret) {
+ of_node_put(child);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int altr_socfpga_hwmon_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device *hwmon_dev;
+ struct altr_socfpga_hwmon_priv *priv;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->client.dev = dev;
+ priv->client.receive_cb = NULL;
+ priv->client.priv = priv;
+ priv->temperature_channels = 0;
+ priv->voltage_channels = 0;
+
+ ret = altr_socfpga_probe_from_dt(dev, priv);
+ if (ret) {
+ dev_err(dev, "Unable to probe from device tree\n");
+ return ret;
+ }
+
+ mutex_init(&priv->lock);
+
+ priv->chan = stratix10_svc_request_channel_byname(&priv->client,
+ SVC_CLIENT_HWMON);
+ if (IS_ERR(priv->chan)) {
+ dev_err(dev, "couldn't get service channel %s defering probe...\n",
+ SVC_CLIENT_HWMON);
+ return -EPROBE_DEFER;
+ }
+
+ dev_info(dev, "Initialized %d temperature and %d voltage channels",
+ priv->temperature_channels, priv->voltage_channels);
+
+ hwmon_dev = devm_hwmon_device_register_with_info(dev, "altr_hwmon", priv,
+ &altr_socfpga_hwmon_chip_info,
+ NULL);
+
+ init_completion(&priv->completion);
+ platform_set_drvdata(pdev, priv);
+
+ return PTR_ERR_OR_ZERO(hwmon_dev);
+}
+
+static void altr_socfpga_hwmon_remove(struct platform_device *pdev)
+{
+ struct altr_socfpga_hwmon_priv *priv = platform_get_drvdata(pdev);
+
+ stratix10_svc_free_channel(priv->chan);
+}
+
+static const struct of_device_id altr_socfpga_of_match[] = {
+ { .compatible = "altr,socfpga-hwmon" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, altr_socfpga_of_match);
+
+static struct platform_driver altr_socfpga_hwmon_driver = {
+ .driver = {
+ .name = "altr-hwmon",
+ .of_match_table = altr_socfpga_of_match,
+ },
+ .probe = altr_socfpga_hwmon_probe,
+ .remove = altr_socfpga_hwmon_remove,
+};
+module_platform_driver(altr_socfpga_hwmon_driver);
+
+MODULE_AUTHOR("Altera Corporation");
+MODULE_DESCRIPTION("Altera SoC FPGA hardware monitoring features");
+MODULE_LICENSE("GPL");
--
2.43.7
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v1 3/5] hwmon: (altr-hwmon): Add initial support for SoCFPGA
2025-12-16 6:49 ` [PATCH v1 3/5] hwmon: (altr-hwmon): Add initial support for SoCFPGA muhammadamirulasyraf.mohamadjamian
@ 2025-12-18 8:29 ` Krzysztof Kozlowski
2025-12-18 9:57 ` Mohamad Jamian, Muhammad Amirul Asyraf
2025-12-22 11:34 ` kernel test robot
1 sibling, 1 reply; 13+ messages in thread
From: Krzysztof Kozlowski @ 2025-12-18 8:29 UTC (permalink / raw)
To: muhammadamirulasyraf.mohamadjamian
Cc: Guenter Roeck, linux-hwmon, Dinh Nguyen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel,
Ang Tien Sung, Khairul Anuar Romli
On Mon, Dec 15, 2025 at 10:49:24PM -0800, muhammadamirulasyraf.mohamadjamian@altera.com wrote:
> From: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
>
> This patch introduces a new hardware monitoring (hwmon) driver for the
> Altera SoCFPGA platform, enabling kernel support for monitoring voltage and
> temperature sensors critical for device health and system stability.
>
> Changes include:
> - New driver implementation 'drivers/hwmon/altera-hwmon.c' providing sensor
> reading and event handling capabilities tailored for SoCFPGA hardware.
>
> - Build system integration by adding Kconfig and Makefile entries, allowing
> users to enable the driver in kernel configuration.
>
> - Documentation added in 'Documentation/hwmon/altera-hwmon.rst', detailing
> driver features, usage instructions, device tree bindings, and
> configuration options.
>
> - Update to 'Documentation/hwmon/index.rst' to reference the new driver
> documentation, improving discoverability and user guidance.
>
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> Signed-off-by: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
> ---
> Documentation/hwmon/altr-hwmon.rst | 32 +++
> Documentation/hwmon/index.rst | 1 +
> MAINTAINERS | 2 +
> drivers/hwmon/Kconfig | 10 +
> drivers/hwmon/Makefile | 1 +
> drivers/hwmon/altr-hwmon.c | 427 +++++++++++++++++++++++++++++
> 6 files changed, 473 insertions(+)
> create mode 100644 Documentation/hwmon/altr-hwmon.rst
> create mode 100644 drivers/hwmon/altr-hwmon.c
>
> diff --git a/Documentation/hwmon/altr-hwmon.rst b/Documentation/hwmon/altr-hwmon.rst
> new file mode 100644
> index 000000000000..3ef1ca0d1686
> --- /dev/null
> +++ b/Documentation/hwmon/altr-hwmon.rst
> @@ -0,0 +1,32 @@
> +.. SPDX-License-Identifier: GPL-2.0
> +Kernel driver altr-hwmon
> +=========================
> +
> +Supported chips:
> +
> + * Intel N5X
> + * Stratix10
> + * Agilex
> + * Agilex5
> +
> +Contributor: Kris Chaplin <kris.chaplin@intel.com>
> + Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> + Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
> +
> +Description
> +-----------
> +
> +This driver supports hardware monitoring for 64-Bit SoC FPGA and eASIC devices
> +based around the Secure Device Manager and Stratix 10 Service layer.
> +
> +The following sensor types are supported
> +
> + * temperature
> + * voltage
> +
> +
> +Usage Notes
> +-----------
> +
> +The driver relies on a device tree node to enumerate support present on the
> +specific device. See Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml for details of the device-tree node.
> diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
> index 85d7a686883e..d37d4cbbe8b5 100644
> --- a/Documentation/hwmon/index.rst
> +++ b/Documentation/hwmon/index.rst
> @@ -40,6 +40,7 @@ Hardware Monitoring Kernel Drivers
> adt7470
> adt7475
> aht10
> + altr-hwmon
> amc6821
> aquacomputer_d5next
> asb100
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8ac7fef4563a..01f776fdbf6f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -942,6 +942,8 @@ M: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@
> L: linux-hwmon@vger.kernel.org
> S: Maintained
> F: Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml
> +F: Documentation/hwmon/altr-hwmon.rst
> +F: drivers/hwmon/altr-hwmon.c
>
> ALTERA MAILBOX DRIVER
> M: Tien Sung Ang <tiensung.ang@altera.com>
> diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
> index d9bac1e3057b..4351725831d3 100644
> --- a/drivers/hwmon/Kconfig
> +++ b/drivers/hwmon/Kconfig
> @@ -2122,6 +2122,16 @@ config SENSORS_SMSC47M192
> This driver can also be built as a module. If so, the module
> will be called smsc47m192.
>
> +config SENSORS_ALTERA_SOCFPGA
> + tristate "Altera SoC FPGA Hardware monitoring features"
> + depends on INTEL_STRATIX10_SERVICE
Why this cannot be compile tested?
...
> +static int altr_socfpga_probe_child_from_dt(struct device *dev,
> + struct device_node *child,
> + struct altr_socfpga_hwmon_priv *priv)
> +{
> + u32 val;
> + int ret;
> + struct device_node *grandchild;
> + const char *label;
> + const char *type;
> +
> + of_property_read_string(child, "name", &type);
> + for_each_child_of_node(child, grandchild) {
No, see my further comment.
> + ret = of_property_read_u32(grandchild, "reg", &val);
> + if (ret) {
> + dev_err(dev, "missing reg property of %pOFn\n",
> + grandchild);
> + return ret;
> + }
> + ret = of_property_read_string(grandchild, "label", &label);
> + if (ret) {
> + dev_err(dev, "missing label propoerty of %pOFn\n",
> + grandchild);
> + return ret;
> + }
> +
> + altr_socfpga_add_channel(dev, type, val, label, priv);
> + }
> +
> + return 0;
> +}
> +
> +static int altr_socfpga_probe_from_dt(struct device *dev,
> + struct altr_socfpga_hwmon_priv *priv)
> +{
> + const struct device_node *np = dev->of_node;
> + struct device_node *child;
> + int ret;
> +
> + /* Compatible with non-DT platforms */
> + if (!np)
> + return 0;
> +
> + for_each_child_of_node(np, child) {
> + ret = altr_socfpga_probe_child_from_dt(dev, child, priv);
> + if (ret) {
> + of_node_put(child);
Just use scoped. Please don't upstream old code, but take new drivers
and use them as your starting point. You just repeat issues we fixed or
old style we changed loong time ago.
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int altr_socfpga_hwmon_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device *hwmon_dev;
> + struct altr_socfpga_hwmon_priv *priv;
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->client.dev = dev;
> + priv->client.receive_cb = NULL;
> + priv->client.priv = priv;
> + priv->temperature_channels = 0;
> + priv->voltage_channels = 0;
> +
> + ret = altr_socfpga_probe_from_dt(dev, priv);
> + if (ret) {
> + dev_err(dev, "Unable to probe from device tree\n");
> + return ret;
No, syntax is return dev_err_probe
> + }
> +
> + mutex_init(&priv->lock);
> +
> + priv->chan = stratix10_svc_request_channel_byname(&priv->client,
> + SVC_CLIENT_HWMON);
> + if (IS_ERR(priv->chan)) {
> + dev_err(dev, "couldn't get service channel %s defering probe...\n",
> + SVC_CLIENT_HWMON);
No, you are now spamming the dmesg with useless deferrals. return
dev_err_probe
> + return -EPROBE_DEFER;
Why ignoring actual error?
> + }
> +
> + dev_info(dev, "Initialized %d temperature and %d voltage channels",
> + priv->temperature_channels, priv->voltage_channels);
Drop, pretty useless. Drivers are supposed to be silent on success.
> +
> + hwmon_dev = devm_hwmon_device_register_with_info(dev, "altr_hwmon", priv,
> + &altr_socfpga_hwmon_chip_info,
> + NULL);
> +
> + init_completion(&priv->completion);
> + platform_set_drvdata(pdev, priv);
> +
> + return PTR_ERR_OR_ZERO(hwmon_dev);
> +}
> +
> +static void altr_socfpga_hwmon_remove(struct platform_device *pdev)
> +{
> + struct altr_socfpga_hwmon_priv *priv = platform_get_drvdata(pdev);
> +
> + stratix10_svc_free_channel(priv->chan);
> +}
> +
> +static const struct of_device_id altr_socfpga_of_match[] = {
> + { .compatible = "altr,socfpga-hwmon" },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, altr_socfpga_of_match);
> +
> +static struct platform_driver altr_socfpga_hwmon_driver = {
> + .driver = {
> + .name = "altr-hwmon",
> + .of_match_table = altr_socfpga_of_match,
> + },
> + .probe = altr_socfpga_hwmon_probe,
> + .remove = altr_socfpga_hwmon_remove,
> +};
> +module_platform_driver(altr_socfpga_hwmon_driver);
> +
> +MODULE_AUTHOR("Altera Corporation");
> +MODULE_DESCRIPTION("Altera SoC FPGA hardware monitoring features");
> +MODULE_LICENSE("GPL");
> --
> 2.43.7
>
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v1 3/5] hwmon: (altr-hwmon): Add initial support for SoCFPGA
2025-12-18 8:29 ` Krzysztof Kozlowski
@ 2025-12-18 9:57 ` Mohamad Jamian, Muhammad Amirul Asyraf
0 siblings, 0 replies; 13+ messages in thread
From: Mohamad Jamian, Muhammad Amirul Asyraf @ 2025-12-18 9:57 UTC (permalink / raw)
To: Krzysztof Kozlowski, Mohamad Jamian, Muhammad Amirul Asyraf
Cc: Guenter Roeck, linux-hwmon, Dinh Nguyen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel, Ang,
Tien Sung, Romli, Khairul Anuar
On 18/12/2025 4:29 pm, Krzysztof Kozlowski wrote:
> On Mon, Dec 15, 2025 at 10:49:24PM -0800, muhammadamirulasyraf.mohamadjamian@altera.com wrote:
>> From: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
>>
>> This patch introduces a new hardware monitoring (hwmon) driver for the
>> Altera SoCFPGA platform, enabling kernel support for monitoring voltage and
>> temperature sensors critical for device health and system stability.
>>
>> Changes include:
>> - New driver implementation 'drivers/hwmon/altera-hwmon.c' providing sensor
>> reading and event handling capabilities tailored for SoCFPGA hardware.
>>
>> - Build system integration by adding Kconfig and Makefile entries, allowing
>> users to enable the driver in kernel configuration.
>>
>> - Documentation added in 'Documentation/hwmon/altera-hwmon.rst', detailing
>> driver features, usage instructions, device tree bindings, and
>> configuration options.
>>
>> - Update to 'Documentation/hwmon/index.rst' to reference the new driver
>> documentation, improving discoverability and user guidance.
>>
>> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>> Signed-off-by: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
>> ---
>> Documentation/hwmon/altr-hwmon.rst | 32 +++
>> Documentation/hwmon/index.rst | 1 +
>> MAINTAINERS | 2 +
>> drivers/hwmon/Kconfig | 10 +
>> drivers/hwmon/Makefile | 1 +
>> drivers/hwmon/altr-hwmon.c | 427 +++++++++++++++++++++++++++++
>> 6 files changed, 473 insertions(+)
>> create mode 100644 Documentation/hwmon/altr-hwmon.rst
>> create mode 100644 drivers/hwmon/altr-hwmon.c
>>
>> diff --git a/Documentation/hwmon/altr-hwmon.rst b/Documentation/hwmon/altr-hwmon.rst
>> new file mode 100644
>> index 000000000000..3ef1ca0d1686
>> --- /dev/null
>> +++ b/Documentation/hwmon/altr-hwmon.rst
>> @@ -0,0 +1,32 @@
>> +.. SPDX-License-Identifier: GPL-2.0
>> +Kernel driver altr-hwmon
>> +=========================
>> +
>> +Supported chips:
>> +
>> + * Intel N5X
>> + * Stratix10
>> + * Agilex
>> + * Agilex5
>> +
>> +Contributor: Kris Chaplin <kris.chaplin@intel.com>
>> + Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>> + Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
>> +
>> +Description
>> +-----------
>> +
>> +This driver supports hardware monitoring for 64-Bit SoC FPGA and eASIC devices
>> +based around the Secure Device Manager and Stratix 10 Service layer.
>> +
>> +The following sensor types are supported
>> +
>> + * temperature
>> + * voltage
>> +
>> +
>> +Usage Notes
>> +-----------
>> +
>> +The driver relies on a device tree node to enumerate support present on the
>> +specific device. See Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml for details of the device-tree node.
>> diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
>> index 85d7a686883e..d37d4cbbe8b5 100644
>> --- a/Documentation/hwmon/index.rst
>> +++ b/Documentation/hwmon/index.rst
>> @@ -40,6 +40,7 @@ Hardware Monitoring Kernel Drivers
>> adt7470
>> adt7475
>> aht10
>> + altr-hwmon
>> amc6821
>> aquacomputer_d5next
>> asb100
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 8ac7fef4563a..01f776fdbf6f 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -942,6 +942,8 @@ M: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@
>> L: linux-hwmon@vger.kernel.org
>> S: Maintained
>> F: Documentation/devicetree/bindings/hwmon/altr,socfpga-hwmon.yaml
>> +F: Documentation/hwmon/altr-hwmon.rst
>> +F: drivers/hwmon/altr-hwmon.c
>>
>> ALTERA MAILBOX DRIVER
>> M: Tien Sung Ang <tiensung.ang@altera.com>
>> diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
>> index d9bac1e3057b..4351725831d3 100644
>> --- a/drivers/hwmon/Kconfig
>> +++ b/drivers/hwmon/Kconfig
>> @@ -2122,6 +2122,16 @@ config SENSORS_SMSC47M192
>> This driver can also be built as a module. If so, the module
>> will be called smsc47m192.
>>
>> +config SENSORS_ALTERA_SOCFPGA
>> + tristate "Altera SoC FPGA Hardware monitoring features"
>> + depends on INTEL_STRATIX10_SERVICE
>
> Why this cannot be compile tested?
>
> ...
>
>
>> +static int altr_socfpga_probe_child_from_dt(struct device *dev,
>> + struct device_node *child,
>> + struct altr_socfpga_hwmon_priv *priv)
>> +{
>> + u32 val;
>> + int ret;
>> + struct device_node *grandchild;
>> + const char *label;
>> + const char *type;
>> +
>> + of_property_read_string(child, "name", &type);
>> + for_each_child_of_node(child, grandchild) {
>
> No, see my further comment.
>
>> + ret = of_property_read_u32(grandchild, "reg", &val);
>> + if (ret) {
>> + dev_err(dev, "missing reg property of %pOFn\n",
>> + grandchild);
>> + return ret;
>> + }
>> + ret = of_property_read_string(grandchild, "label", &label);
>> + if (ret) {
>> + dev_err(dev, "missing label propoerty of %pOFn\n",
>> + grandchild);
>> + return ret;
>> + }
>> +
>> + altr_socfpga_add_channel(dev, type, val, label, priv);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int altr_socfpga_probe_from_dt(struct device *dev,
>> + struct altr_socfpga_hwmon_priv *priv)
>> +{
>> + const struct device_node *np = dev->of_node;
>> + struct device_node *child;
>> + int ret;
>> +
>> + /* Compatible with non-DT platforms */
>> + if (!np)
>> + return 0;
>> +
>> + for_each_child_of_node(np, child) {
>> + ret = altr_socfpga_probe_child_from_dt(dev, child, priv);
>> + if (ret) {
>> + of_node_put(child);
>
> Just use scoped. Please don't upstream old code, but take new drivers
> and use them as your starting point. You just repeat issues we fixed or
> old style we changed loong time ago.
>
>
>> + return ret;
>> + }
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int altr_socfpga_hwmon_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct device *hwmon_dev;
>> + struct altr_socfpga_hwmon_priv *priv;
>> + int ret;
>> +
>> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
>> + if (!priv)
>> + return -ENOMEM;
>> +
>> + priv->client.dev = dev;
>> + priv->client.receive_cb = NULL;
>> + priv->client.priv = priv;
>> + priv->temperature_channels = 0;
>> + priv->voltage_channels = 0;
>> +
>> + ret = altr_socfpga_probe_from_dt(dev, priv);
>> + if (ret) {
>> + dev_err(dev, "Unable to probe from device tree\n");
>> + return ret;
>
> No, syntax is return dev_err_probe
>> + }
>> +
>> + mutex_init(&priv->lock);
>> +
>> + priv->chan = stratix10_svc_request_channel_byname(&priv->client,
>> + SVC_CLIENT_HWMON);
>> + if (IS_ERR(priv->chan)) {
>> + dev_err(dev, "couldn't get service channel %s defering probe...\n",
>> + SVC_CLIENT_HWMON);
>
> No, you are now spamming the dmesg with useless deferrals. return
> dev_err_probe
>
>
>> + return -EPROBE_DEFER;
>
>
> Why ignoring actual error?
>
>> + }
>> +
>> + dev_info(dev, "Initialized %d temperature and %d voltage channels",
>> + priv->temperature_channels, priv->voltage_channels);
>
> Drop, pretty useless. Drivers are supposed to be silent on success.
>
>
>> +
>> + hwmon_dev = devm_hwmon_device_register_with_info(dev, "altr_hwmon", priv,
>> + &altr_socfpga_hwmon_chip_info,
>> + NULL);
>> +
>> + init_completion(&priv->completion);
>> + platform_set_drvdata(pdev, priv);
>> +
>> + return PTR_ERR_OR_ZERO(hwmon_dev);
>> +}
>> +
>> +static void altr_socfpga_hwmon_remove(struct platform_device *pdev)
>> +{
>> + struct altr_socfpga_hwmon_priv *priv = platform_get_drvdata(pdev);
>> +
>> + stratix10_svc_free_channel(priv->chan);
>> +}
>> +
>> +static const struct of_device_id altr_socfpga_of_match[] = {
>> + { .compatible = "altr,socfpga-hwmon" },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, altr_socfpga_of_match);
>> +
>> +static struct platform_driver altr_socfpga_hwmon_driver = {
>> + .driver = {
>> + .name = "altr-hwmon",
>> + .of_match_table = altr_socfpga_of_match,
>> + },
>> + .probe = altr_socfpga_hwmon_probe,
>> + .remove = altr_socfpga_hwmon_remove,
>> +};
>> +module_platform_driver(altr_socfpga_hwmon_driver);
>> +
>> +MODULE_AUTHOR("Altera Corporation");
>> +MODULE_DESCRIPTION("Altera SoC FPGA hardware monitoring features");
>> +MODULE_LICENSE("GPL");
>> --
>> 2.43.7
>>
We will ovrehaul the patches based on new linux driver implementation as
starting point.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1 3/5] hwmon: (altr-hwmon): Add initial support for SoCFPGA
2025-12-16 6:49 ` [PATCH v1 3/5] hwmon: (altr-hwmon): Add initial support for SoCFPGA muhammadamirulasyraf.mohamadjamian
2025-12-18 8:29 ` Krzysztof Kozlowski
@ 2025-12-22 11:34 ` kernel test robot
1 sibling, 0 replies; 13+ messages in thread
From: kernel test robot @ 2025-12-22 11:34 UTC (permalink / raw)
To: muhammadamirulasyraf.mohamadjamian, Guenter Roeck, linux-hwmon,
Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
devicetree, linux-kernel, Ang Tien Sung, Khairul Anuar Romli
Cc: oe-kbuild-all
Hi,
kernel test robot noticed the following build warnings:
[auto build test WARNING on c6bb982894b51c0ebaf94bbeb55ccbd1d4145a22]
url: https://github.com/intel-lab-lkp/linux/commits/muhammadamirulasyraf-mohamadjamian-altera-com/dt-bindings-hwmon-add-altr-socfpga-hwmon-yaml-binding/20251216-145542
base: c6bb982894b51c0ebaf94bbeb55ccbd1d4145a22
patch link: https://lore.kernel.org/r/20251216064926.15817-4-muhammadamirulasyraf.mohamadjamian%40altera.com
patch subject: [PATCH v1 3/5] hwmon: (altr-hwmon): Add initial support for SoCFPGA
reproduce: (https://download.01.org/0day-ci/archive/20251222/202512221215.5HgD2pyk-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512221215.5HgD2pyk-lkp@intel.com/
All warnings (new ones prefixed by >>):
WARNING: No kernel-doc for file ./include/linux/hid_bpf.h
ERROR: Cannot find file ./include/linux/hid_bpf.h
WARNING: No kernel-doc for file ./include/linux/hid_bpf.h
ERROR: Cannot find file ./include/linux/hid.h
WARNING: No kernel-doc for file ./include/linux/hid.h
>> Documentation/hwmon/altr-hwmon.rst:2: WARNING: Explicit markup ends without a blank line; unexpected unindent. [docutils]
ERROR: Cannot find file ./include/linux/i2c-atr.h
WARNING: No kernel-doc for file ./include/linux/i2c-atr.h
ERROR: Cannot find file ./include/linux/mutex.h
ERROR: Cannot find file ./include/linux/mutex.h
WARNING: No kernel-doc for file ./include/linux/mutex.h
vim +2 Documentation/hwmon/altr-hwmon.rst
> 2 Kernel driver altr-hwmon
3 =========================
4
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v1 4/5] arm64: dts: socfpga: stratix10: Add hwmon node
2025-12-16 6:49 [PATCH v1 0/5] hwmon: Add support for Altera SoCFPGA hardware monitoring muhammadamirulasyraf.mohamadjamian
` (2 preceding siblings ...)
2025-12-16 6:49 ` [PATCH v1 3/5] hwmon: (altr-hwmon): Add initial support for SoCFPGA muhammadamirulasyraf.mohamadjamian
@ 2025-12-16 6:49 ` muhammadamirulasyraf.mohamadjamian
2025-12-16 6:49 ` [PATCH v1 5/5] arm64: dts: socfpga: agilex: " muhammadamirulasyraf.mohamadjamian
4 siblings, 0 replies; 13+ messages in thread
From: muhammadamirulasyraf.mohamadjamian @ 2025-12-16 6:49 UTC (permalink / raw)
To: Guenter Roeck, linux-hwmon, Dinh Nguyen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel,
Ang Tien Sung, Khairul Anuar Romli
From: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
The Stratix 10 SoCFPGA platform includes hardware monitoring capabilities
that require proper device tree description.
Currently, the Stratix 10 device tree lacks an hwmon node, preventing the
kernel from binding the corresponding hwmon driver and accessing sensor
data.
This hwmon node with the compatible string "altera,socfpga-hwmon" ensures
the hardware monitoring subsystem can be initialized correctly, enabling
accurate voltage and temperature monitoring.
Signed-off-by: Ang Tien Sung <tien.sung.ang@altera.com>
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Signed-off-by: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
---
.../boot/dts/altera/socfpga_stratix10.dtsi | 4 +++
.../dts/altera/socfpga_stratix10_socdk.dts | 31 +++++++++++++++++++
2 files changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 657e986e5dba..73eead7ffdbb 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -78,6 +78,10 @@ svc {
fpga_mgr: fpga-mgr {
compatible = "intel,stratix10-soc-fpga-mgr";
};
+
+ temp_volt: hwmon {
+ compatible = "altr,socfpga-hwmon";
+ };
};
};
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 58f776e411fc..63309001f1c5 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -197,3 +197,34 @@ root: partition@4200000 {
};
};
};
+
+&temp_volt {
+ voltage {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ input@2 {
+ label = "0.8V VCC";
+ reg = <2>;
+ };
+
+ input@3 {
+ label = "1.8V VCCIO_SDM";
+ reg = <3>;
+ };
+
+ input@6 {
+ label = "0.9V VCCERAM";
+ reg = <6>;
+ };
+ };
+
+ temperature {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ label = "Main Die SDM";
+ reg = <0x0>;
+ };
+ };
+};
--
2.43.7
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v1 5/5] arm64: dts: socfpga: agilex: Add hwmon node
2025-12-16 6:49 [PATCH v1 0/5] hwmon: Add support for Altera SoCFPGA hardware monitoring muhammadamirulasyraf.mohamadjamian
` (3 preceding siblings ...)
2025-12-16 6:49 ` [PATCH v1 4/5] arm64: dts: socfpga: stratix10: Add hwmon node muhammadamirulasyraf.mohamadjamian
@ 2025-12-16 6:49 ` muhammadamirulasyraf.mohamadjamian
4 siblings, 0 replies; 13+ messages in thread
From: muhammadamirulasyraf.mohamadjamian @ 2025-12-16 6:49 UTC (permalink / raw)
To: Guenter Roeck, linux-hwmon, Dinh Nguyen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel,
Ang Tien Sung, Khairul Anuar Romli
From: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
The Agilex SoCFPGA platform includes hardware monitoring capabilities that
require proper device tree description.
Currently, the Agilex device tree lacks an hwmon node, preventing the
kernel from binding the corresponding hwmon driver and accessing sensor
data.
This hwmon node with the compatible string "altera,socfpga-hwmon" ensures
the hardware monitoring subsystem can be initialized correctly, enabling
accurate voltage and temperature monitoring.
The node is added for Agilex OOBE Daughter Card, Agilex with NAND daughter
card and N5X.
Define the temperature sensor locations to demonstrate the maximum
temperature value rather than the individual diode values.
- arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
- arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
- arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
For N5X, only the main die sensor is present. Also, add Voltage Monitor
labels for the N5X device to align with the descriptions from the N5X
documentation.
- arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
Signed-off-by: Ang Tien Sung <tien.sung.ang@altera.com>
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Signed-off-by: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@altera.com>
---
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 ++
.../boot/dts/intel/socfpga_agilex_n6000.dts | 66 +++++++++++++++++++
.../boot/dts/intel/socfpga_agilex_socdk.dts | 66 +++++++++++++++++++
.../dts/intel/socfpga_agilex_socdk_nand.dts | 66 +++++++++++++++++++
.../boot/dts/intel/socfpga_n5x_socdk.dts | 46 +++++++++++++
5 files changed, 248 insertions(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index 0dfbafde8822..0e91a331da69 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -69,6 +69,10 @@ svc {
fpga_mgr: fpga-mgr {
compatible = "intel,agilex-soc-fpga-mgr";
};
+
+ temp_volt: hwmon {
+ compatible = "altr,socfpga-hwmon";
+ };
};
};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
index d22de06e9839..f45a76bff82a 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
@@ -64,3 +64,69 @@ &watchdog0 {
&fpga_mgr {
status = "disabled";
};
+
+&temp_volt {
+ voltage {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ input@2 {
+ label = "0.8V VCC";
+ reg = <2>;
+ };
+
+ input@3 {
+ label = "1.8V VCCIO_SDM";
+ reg = <3>;
+ };
+
+ input@4 {
+ label = "1.8V VCCPT";
+ reg = <4>;
+ };
+
+ input@5 {
+ label = "1.2V VCCCRCORE";
+ reg = <5>;
+ };
+
+ input@6 {
+ label = "0.9V VCCH";
+ reg = <6>;
+ };
+
+ input@7 {
+ label = "0.8V VCCL";
+ reg = <7>;
+ };
+ };
+
+ temperature {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ label = "Main Die SDM";
+ reg = <0x0>;
+ };
+
+ input@10000 {
+ label = "Main Die corner bottom left max";
+ reg = <0x10000>;
+ };
+
+ input@20000 {
+ label = "Main Die corner top left max";
+ reg = <0x20000>;
+ };
+
+ input@30000 {
+ label = "Main Die corner bottom right max";
+ reg = <0x30000>;
+ };
+
+ input@40000 {
+ label = "Main Die corner top right max";
+ reg = <0x40000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index 9ee312bae8d2..33b5286655ef 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -136,3 +136,69 @@ root: partition@4200000 {
};
};
};
+
+&temp_volt {
+ voltage {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ input@2 {
+ label = "0.8V VCC";
+ reg = <2>;
+ };
+
+ input@3 {
+ label = "1.8V VCCIO_SDM";
+ reg = <3>;
+ };
+
+ input@4 {
+ label = "1.8V VCCPT";
+ reg = <4>;
+ };
+
+ input@5 {
+ label = "1.2V VCCCRCORE";
+ reg = <5>;
+ };
+
+ input@6 {
+ label = "0.9V VCCH";
+ reg = <6>;
+ };
+
+ input@7 {
+ label = "0.8V VCCL";
+ reg = <7>;
+ };
+ };
+
+ temperature {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ label = "Main Die SDM";
+ reg = <0x0>;
+ };
+
+ input@10000 {
+ label = "Main Die corner bottom left max";
+ reg = <0x10000>;
+ };
+
+ input@20000 {
+ label = "Main Die corner top left max";
+ reg = <0x20000>;
+ };
+
+ input@30000 {
+ label = "Main Die corner bottom right max";
+ reg = <0x30000>;
+ };
+
+ input@40000 {
+ label = "Main Die corner top right max";
+ reg = <0x40000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
index 98900cb410dc..5246bf8b14b5 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
@@ -114,3 +114,69 @@ &usb0 {
&watchdog0 {
status = "okay";
};
+
+&temp_volt {
+ voltage {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ input@2 {
+ label = "0.8V VCC";
+ reg = <2>;
+ };
+
+ input@3 {
+ label = "1.8V VCCIO_SDM";
+ reg = <3>;
+ };
+
+ input@4 {
+ label = "1.8V VCCPT";
+ reg = <4>;
+ };
+
+ input@5 {
+ label = "1.2V VCCCRCORE";
+ reg = <5>;
+ };
+
+ input@6 {
+ label = "0.9V VCCH";
+ reg = <6>;
+ };
+
+ input@7 {
+ label = "0.8V VCCL";
+ reg = <7>;
+ };
+ };
+
+ temperature {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ label = "Main Die SDM";
+ reg = <0x0>;
+ };
+
+ input@10000 {
+ label = "Main Die corner bottom left max";
+ reg = <0x10000>;
+ };
+
+ input@20000 {
+ label = "Main Die corner top left max";
+ reg = <0x20000>;
+ };
+
+ input@30000 {
+ label = "Main Die corner bottom right max";
+ reg = <0x30000>;
+ };
+
+ input@40000 {
+ label = "Main Die corner top right max";
+ reg = <0x40000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
index 0034a4897220..5ca111c158c4 100644
--- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
@@ -126,3 +126,49 @@ &usb0 {
&watchdog0 {
status = "okay";
};
+
+&temp_volt {
+ voltage {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ input@2 {
+ label = "0.8V VDD";
+ reg = <2>;
+ };
+
+ input@3 {
+ label = "0.8V VDD_SDM";
+ reg = <3>;
+ };
+
+ input@4 {
+ label = "1.8V VCCADC";
+ reg = <4>;
+ };
+
+ input@5 {
+ label = "1.8V VCCPD";
+ reg = <5>;
+ };
+
+ input@6 {
+ label = "1.8V VCCIO_SDM";
+ reg = <6>;
+ };
+
+ input@7 {
+ label = "0.8V VDD_HPS";
+ reg = <7>;
+ };
+ };
+
+ temperature {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ label = "Main Die SDM";
+ reg = <0x0>;
+ };
+ };
+};
--
2.43.7
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