[PATCH v5 0/7] riscv: spacemit: Add SpacemiT K3 SoC and K3 Pico-ITX board

[PATCH v5 0/7] riscv: spacemit: Add SpacemiT K3 SoC and K3 Pico-ITX board

[Guodong Xu]

This series introduces basic support for the SpacemiT K3 SoC and the
K3 Pico-ITX evaluation board.

In v5, patches 6-9 (dt-bindings) have been dropped as they were accepted
by Conor and applied to riscv-dt-for-next.

The series has been rebased on linux-next tag: next-20260114.

The SpacemiT K3 is an SoC featuring 8 SpacemiT X100 RISC-V cores.
The X100 is a 4-issue, out-of-order core compliant with the RVA23
profile, targeting high-performance scenarios. [1]

The K3 Pico-ITX is an evaluation board built around the K3 SoC.

From an RVA23 profile compliance perspective, the X100 supports all
mandatory extensions required by RVA23U64 and RVA23S64.

Link: https://www.spacemit.com/en/spacemit-x100-core/ [1]

Changes in v5:
- Patch 1:
   Add Acked-by from Paul.
- Patch 5:
   Add Reviewed-by from Yixun, add Acked-by from Conor.
- Patch 6 (Patch 10 in v4):
   Update the copyright year to 2026.
   Update the commit message.
   Set M-mode maplic and mimsic status to "reserved".
   In maplic node, use riscv,delegation to match kernel binding. OpenSBI
    accepts both delegate and delgation, but the binding documents only
    riscv,delegation.
- Patch 7 (Patch 11 in v4):
   Update the commit message subject line.
   Remove the unused aliases.
   Update the copyright year to 2026.

- Link to v4: https://lore.kernel.org/r/20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com

Changes in v4:
- Patch 5:
   Adjust maintainers list in alphabetic order.
   Declare spacemit,k3-pico-itx as an enum, which could save future
    code change when adding new boards.
- Patch 10:
   Fix missing blank space after comma in simsic compatible.
   Add m-mode imsic and aplic nodes, per suggestion received from Samuel
    Holland.
   Adjust node properties order in nodes simsic, saplic, mimsic, maplic to
    follow the DTS coding style.

- Link to v3: https://lore.kernel.org/r/20260108-k3-basic-dt-v3-0-ed99eb4c3ad3@riscstar.com

Other Changes in v3 include:
- Patch 1:
   Acked-by: Krzysztof Kozlowski
- Patch 4:
   Acked-by: Krzysztof Kozlowski
- Dropped Patch 5 "dt-bindings: serial: 8250: add SpacemiT K3 UART compatible"
   as it has been applied to tty-next.

- Link to v2: https://lore.kernel.org/r/20251222-k3-basic-dt-v2-0-3af3f3cd0f8a@riscstar.com

Changes in v2:
- Patch 1:
   Fixed alphanumeric sorting order of compatible strings (swapped x100 and
     x60) as per Krzysztof's feedback.
   Update commit message with more information about X100 featurs per
     Yixun's feedback.
- Patch 4:
   Fixed the order to keep things alphabetically.
- Patch 6:
   Use "one blank space" between name and email address.
- Patch 7 ~ 11:
   New patches. Add description of RVA23 mandatory extensions into riscv
    binding YAML file.
- Patch 12 (Patch 7 in v1):
   Removed aliases node.
   Updated 'riscv,isa-extensions' with new extension strings available
- Patch 13 (Patch 8 in v1):
   Updated the memory address to the hardware truth.
   Added aliases node in board dts.
- Patch 1,2,3,5: Add Reviewed-by and Acked-by collected.

Link to v1: https://lore.kernel.org/r/20251216-k3-basic-dt-v1-0-a0d256c9dc92@riscstar.com

Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
Guodong Xu (7):
      dt-bindings: riscv: add SpacemiT X100 CPU compatible
      dt-bindings: timer: add SpacemiT K3 CLINT
      dt-bindings: interrupt-controller: add SpacemiT K3 APLIC
      dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC
      dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings
      riscv: dts: spacemit: add initial support for K3 SoC
      riscv: dts: spacemit: add K3 Pico-ITX board support

 .../bindings/interrupt-controller/riscv,aplic.yaml |   1 +
 .../interrupt-controller/riscv,imsics.yaml         |   1 +
 Documentation/devicetree/bindings/riscv/cpus.yaml  |   1 +
 .../devicetree/bindings/riscv/spacemit.yaml        |   5 +
 .../devicetree/bindings/timer/sifive,clint.yaml    |   1 +
 arch/riscv/boot/dts/spacemit/Makefile              |   1 +
 arch/riscv/boot/dts/spacemit/k3-pico-itx.dts       |  29 +
 arch/riscv/boot/dts/spacemit/k3.dtsi               | 590 +++++++++++++++++++++
 8 files changed, 629 insertions(+)
---
base-commit: 78ffa9bb137071c00eec2d4afc247ef92d5c0b90
change-id: 20251216-k3-basic-dt-cd9540061989

Best regards,
-- 
Guodong Xu <guodong@riscstar.com>

[PATCH v5 1/7] dt-bindings: riscv: add SpacemiT X100 CPU compatible

[Guodong Xu]

Add compatible string for the SpacemiT X100 core. [1]

The X100 is a 64-bit RVA23-compliant RISC-V core from SpacemiT. X100
supports the RISC-V vector and hypervisor extensions and all mandatory
extersions as required by the RVA23U64 and RVA23S64 profiles, per the
definition in 'RVA23 Profile, Version 1.0'. [2]

From a microarchieture viewpoint, the X100 features a 4-issue
out-of-order pipeline.

X100 is used in SpacemiT K3 SoC.

Acked-by: Paul Walmsley <pjw@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://www.spacemit.com/en/spacemit-x100-core/ [1]
Link: https://docs.riscv.org/reference/profiles/rva23/_attachments/rva23-profile.pdf [2]
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v5: Added Acked-by from Paul.
v4: No change.
v3: Added Acked-by from Krzysztof.
v2: Fixed alphanumeric sorting of compatible strings, put x100 before x60,
     as per Krzysztof's feedback.
    Added reviewed-by from Yixun and Heinrich.
    Updated the commit message to provide more information about X100.
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d733c0bd534f..5feeb2203050 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -61,6 +61,7 @@ properties:
               - sifive,u7
               - sifive,u74
               - sifive,u74-mc
+              - spacemit,x100
               - spacemit,x60
               - thead,c906
               - thead,c908

-- 
2.43.0

[PATCH v5 2/7] dt-bindings: timer: add SpacemiT K3 CLINT

[Guodong Xu]

Add compatible string for SpacemiT K3 CLINT.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v5: No change.
v4: No change.
v3: No change.
v2: Add Conor's Acked-by.
---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index 0d3b8dc362ba..3bab40500df9 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -33,6 +33,7 @@ properties:
               - eswin,eic7700-clint     # ESWIN EIC7700
               - sifive,fu540-c000-clint # SiFive FU540
               - spacemit,k1-clint       # SpacemiT K1
+              - spacemit,k3-clint       # SpacemiT K3
               - starfive,jh7100-clint   # StarFive JH7100
               - starfive,jh7110-clint   # StarFive JH7110
               - starfive,jh8100-clint   # StarFive JH8100

-- 
2.43.0

[PATCH v5 3/7] dt-bindings: interrupt-controller: add SpacemiT K3 APLIC

[Guodong Xu]

Add compatible string for SpacemiT K3 APLIC.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v5: No change.
v4: No change.
v3: No change.
v2: Add Conor's Acked-by.
---
 Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
index bef00521d5da..0718071444d2 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
@@ -28,6 +28,7 @@ properties:
     items:
       - enum:
           - qemu,aplic
+          - spacemit,k3-aplic
       - const: riscv,aplic
 
   reg:

-- 
2.43.0

[PATCH v5 4/7] dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC

[Guodong Xu]

Add compatible string for SpacemiT K3 IMSIC.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v5: No change.
v4: No change.
v3: Add Acked-by from Krzysztof.
v2: Fix the order to keep things alphabetically.
---
 Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
index c23b5c09fdb9..feec122bddde 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
@@ -48,6 +48,7 @@ properties:
     items:
       - enum:
           - qemu,imsics
+          - spacemit,k3-imsics
       - const: riscv,imsics
 
   reg:

-- 
2.43.0

[PATCH v5 5/7] dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings

[Guodong Xu]

Add DT binding documentation for the SpacemiT K3 SoC and the board Pico-ITX
which is a 2.5-inch single-board computer.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v5: Add Reviewed-by from Yixun.
    Add Acked-by from Conor.
v4: Adjust maintainers list in alphabetic order.
    Declare spacemit,k3-pico-itx as an enum, which can save future
     code change when adding new boards.
v3: No change.
v2: Use one-blank-space between name and email address.
---
 Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml
index 9c49482002f7..b958b94a924d 100644
--- a/Documentation/devicetree/bindings/riscv/spacemit.yaml
+++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml
@@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: SpacemiT SoC-based boards
 
 maintainers:
+  - Guodong Xu <guodong@riscstar.com>
   - Yangyu Chen <cyy@cyyself.name>
   - Yixun Lan <dlan@gentoo.org>
 
@@ -26,6 +27,10 @@ properties:
               - xunlong,orangepi-r2s
               - xunlong,orangepi-rv2
           - const: spacemit,k1
+      - items:
+          - enum:
+              - spacemit,k3-pico-itx
+          - const: spacemit,k3
 
 additionalProperties: true
 

-- 
2.43.0

[PATCH v5 6/7] riscv: dts: spacemit: add initial support for K3 SoC

[Guodong Xu]

SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant.
Add nodes of uarts, timer and interrupt-controllers. Also add M-mode
APLIC (maplic) and IMSIC (mimsic) nodes to represent the hardware
topology and ready for potential firmware usage.

Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v5: Update the copyright year to 2026.
    Set M-mode maplic and mimsic status to "reserved".
    Update the commit message per Yixun's suggestion.
    In maplic node, use riscv,delegation to match kernel binding. OpenSBI
     accepts both delegate and delegation, but the binding documents only
     riscv,delegation.
v4: Fix missing blank space after commas in compatible string.
    Add m-mode imsic and aplic node.
    Reorder properties in simsic, saplic, mimsic, and maplic nodes
     to match DTS coding style.
v3: Remove "supm" from the riscv,isa-extensions list.
v2: Remove aliases from k3.dtsi, they should be in board DTS.
    Updated riscv,isa-extensions with new extensions from the extensions.yaml.
---
 arch/riscv/boot/dts/spacemit/k3.dtsi | 590 +++++++++++++++++++++++++++++++++++
 1 file changed, 590 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
new file mode 100644
index 000000000000..53425badfea9
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -0,0 +1,590 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd
+ * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/dts-v1/;
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "SpacemiT K3";
+	compatible = "spacemit,k3";
+
+	cpus: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <24000000>;
+
+		cpu_0: cpu@0 {
+			compatible = "spacemit,x100", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+					       "sha", "shcounterenw", "shgatpa", "shtvala",
+					       "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+					       "smstateen", "ssaia", "ssccptr", "sscofpmf",
+					       "sscounterenw", "ssnpm", "ssstateen", "sstc",
+					       "sstvala", "sstvecd", "ssu64xl", "svade",
+					       "svinval", "svnapot", "svpbmt", "za64rs",
+					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
+					       "zicond", "zicsr", "zifencei", "zihintntl",
+					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+					       "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+					       "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+					       "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <256>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_cache0>;
+			mmu-type = "riscv,sv39";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu_1: cpu@1 {
+			compatible = "spacemit,x100", "riscv";
+			device_type = "cpu";
+			reg = <1>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+					       "sha", "shcounterenw", "shgatpa", "shtvala",
+					       "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+					       "smstateen", "ssaia", "ssccptr", "sscofpmf",
+					       "sscounterenw", "ssnpm", "ssstateen", "sstc",
+					       "sstvala", "sstvecd", "ssu64xl", "svade",
+					       "svinval", "svnapot", "svpbmt", "za64rs",
+					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
+					       "zicond", "zicsr", "zifencei", "zihintntl",
+					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+					       "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+					       "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+					       "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <256>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_cache0>;
+			mmu-type = "riscv,sv39";
+
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu_2: cpu@2 {
+			compatible = "spacemit,x100", "riscv";
+			device_type = "cpu";
+			reg = <2>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+					       "sha", "shcounterenw", "shgatpa", "shtvala",
+					       "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+					       "smstateen", "ssaia", "ssccptr", "sscofpmf",
+					       "sscounterenw", "ssnpm", "ssstateen", "sstc",
+					       "sstvala", "sstvecd", "ssu64xl", "svade",
+					       "svinval", "svnapot", "svpbmt", "za64rs",
+					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
+					       "zicond", "zicsr", "zifencei", "zihintntl",
+					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+					       "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+					       "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+					       "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <256>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_cache0>;
+			mmu-type = "riscv,sv39";
+
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu_3: cpu@3 {
+			compatible = "spacemit,x100", "riscv";
+			device_type = "cpu";
+			reg = <3>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+					       "sha", "shcounterenw", "shgatpa", "shtvala",
+					       "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+					       "smstateen", "ssaia", "ssccptr", "sscofpmf",
+					       "sscounterenw", "ssnpm", "ssstateen", "sstc",
+					       "sstvala", "sstvecd", "ssu64xl", "svade",
+					       "svinval", "svnapot", "svpbmt", "za64rs",
+					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
+					       "zicond", "zicsr", "zifencei", "zihintntl",
+					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+					       "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+					       "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+					       "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <256>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_cache0>;
+			mmu-type = "riscv,sv39";
+
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu_4: cpu@4 {
+			compatible = "spacemit,x100", "riscv";
+			device_type = "cpu";
+			reg = <4>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+					       "sha", "shcounterenw", "shgatpa", "shtvala",
+					       "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+					       "smstateen", "ssaia", "ssccptr", "sscofpmf",
+					       "sscounterenw", "ssnpm", "ssstateen", "sstc",
+					       "sstvala", "sstvecd", "ssu64xl", "svade",
+					       "svinval", "svnapot", "svpbmt", "za64rs",
+					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
+					       "zicond", "zicsr", "zifencei", "zihintntl",
+					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+					       "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+					       "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+					       "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <256>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_cache1>;
+			mmu-type = "riscv,sv39";
+
+			cpu4_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu_5: cpu@5 {
+			compatible = "spacemit,x100", "riscv";
+			device_type = "cpu";
+			reg = <5>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+					       "sha", "shcounterenw", "shgatpa", "shtvala",
+					       "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+					       "smstateen", "ssaia", "ssccptr", "sscofpmf",
+					       "sscounterenw", "ssnpm", "ssstateen", "sstc",
+					       "sstvala", "sstvecd", "ssu64xl", "svade",
+					       "svinval", "svnapot", "svpbmt", "za64rs",
+					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
+					       "zicond", "zicsr", "zifencei", "zihintntl",
+					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+					       "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+					       "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+					       "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <256>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_cache1>;
+			mmu-type = "riscv,sv39";
+
+			cpu5_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu_6: cpu@6 {
+			compatible = "spacemit,x100", "riscv";
+			device_type = "cpu";
+			reg = <6>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+					       "sha", "shcounterenw", "shgatpa", "shtvala",
+					       "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+					       "smstateen", "ssaia", "ssccptr", "sscofpmf",
+					       "sscounterenw", "ssnpm", "ssstateen", "sstc",
+					       "sstvala", "sstvecd", "ssu64xl", "svade",
+					       "svinval", "svnapot", "svpbmt", "za64rs",
+					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
+					       "zicond", "zicsr", "zifencei", "zihintntl",
+					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+					       "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+					       "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+					       "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <256>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_cache1>;
+			mmu-type = "riscv,sv39";
+
+			cpu6_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu_7: cpu@7 {
+			compatible = "spacemit,x100", "riscv";
+			device_type = "cpu";
+			reg = <7>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+					       "sha", "shcounterenw", "shgatpa", "shtvala",
+					       "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+					       "smstateen", "ssaia", "ssccptr", "sscofpmf",
+					       "sscounterenw", "ssnpm", "ssstateen", "sstc",
+					       "sstvala", "sstvecd", "ssu64xl", "svade",
+					       "svinval", "svnapot", "svpbmt", "za64rs",
+					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
+					       "zicond", "zicsr", "zifencei", "zihintntl",
+					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+					       "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+					       "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+					       "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <256>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_cache1>;
+			mmu-type = "riscv,sv39";
+
+			cpu7_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		l2_cache0: cache-controller-0 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <4194304>;
+			cache-sets = <4096>;
+			cache-unified;
+		};
+
+		l2_cache1: cache-controller-1 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <4194304>;
+			cache-sets = <4096>;
+			cache-unified;
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu_0>;
+				};
+				core1 {
+					cpu = <&cpu_1>;
+				};
+				core2 {
+					cpu = <&cpu_2>;
+				};
+				core3 {
+					cpu = <&cpu_3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu_4>;
+				};
+				core1 {
+					cpu = <&cpu_5>;
+				};
+				core2 {
+					cpu = <&cpu_6>;
+				};
+				core3 {
+					cpu = <&cpu_7>;
+				};
+			};
+		};
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&saplic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		dma-noncoherent;
+		ranges;
+
+		uart0: serial@d4017000 {
+			compatible = "spacemit,k3-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017000 0x0 0x100>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clock-frequency = <14700000>;
+			interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+		};
+
+		uart2: serial@d4017100 {
+			compatible = "spacemit,k3-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017100 0x0 0x100>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clock-frequency = <14700000>;
+			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+		};
+
+		uart3: serial@d4017200 {
+			compatible = "spacemit,k3-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017200 0x0 0x100>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clock-frequency = <14700000>;
+			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+		};
+
+		uart4: serial@d4017300 {
+			compatible = "spacemit,k3-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017300 0x0 0x100>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clock-frequency = <14700000>;
+			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+		};
+
+		uart5: serial@d4017400 {
+			compatible = "spacemit,k3-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017400 0x0 0x100>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clock-frequency = <14700000>;
+			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+		};
+
+		uart6: serial@d4017500 {
+			compatible = "spacemit,k3-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017500 0x0 0x100>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clock-frequency = <14700000>;
+			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+		};
+
+		uart7: serial@d4017600 {
+			compatible = "spacemit,k3-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017600 0x0 0x100>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clock-frequency = <14700000>;
+			interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+		};
+
+		uart8: serial@d4017700 {
+			compatible = "spacemit,k3-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017700 0x0 0x100>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clock-frequency = <14700000>;
+			interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+		};
+
+		uart9: serial@d4017800 {
+			compatible = "spacemit,k3-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017800 0x0 0x100>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clock-frequency = <14700000>;
+			interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+		};
+
+		uart10: serial@d401f000 {
+			compatible = "spacemit,k3-uart", "intel,xscale-uart";
+			reg = <0x0 0xd401f000 0x0 0x100>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clock-frequency = <14700000>;
+			interrupts = <281 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+		};
+
+		simsic: interrupt-controller@e0400000 {
+			compatible = "spacemit,k3-imsics", "riscv,imsics";
+			reg = <0x0 0xe0400000 0x0 0x200000>;
+			#interrupt-cells = <0>;
+			#msi-cells = <0>;
+			interrupt-controller;
+			interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>,
+					      <&cpu2_intc 9>, <&cpu3_intc 9>,
+					      <&cpu4_intc 9>, <&cpu5_intc 9>,
+					      <&cpu6_intc 9>, <&cpu7_intc 9>;
+			msi-controller;
+			riscv,guest-index-bits = <6>;
+			riscv,hart-index-bits = <4>;
+			riscv,num-guest-ids = <511>;
+			riscv,num-ids = <511>;
+		};
+
+		saplic: interrupt-controller@e0804000 {
+			compatible = "spacemit,k3-aplic", "riscv,aplic";
+			reg = <0x0 0xe0804000 0x0 0x4000>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			msi-parent = <&simsic>;
+			riscv,num-sources = <512>;
+		};
+
+		clint: timer@e081c000 {
+			compatible = "spacemit,k3-clint", "sifive,clint0";
+			reg = <0x0 0xe081c000 0x0 0x4000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>,
+					      <&cpu2_intc 3>, <&cpu2_intc 7>,
+					      <&cpu3_intc 3>, <&cpu3_intc 7>,
+					      <&cpu4_intc 3>, <&cpu4_intc 7>,
+					      <&cpu5_intc 3>, <&cpu5_intc 7>,
+					      <&cpu6_intc 3>, <&cpu6_intc 7>,
+					      <&cpu7_intc 3>, <&cpu7_intc 7>;
+		};
+
+		mimsic: interrupt-controller@f1000000 {
+			compatible = "spacemit,k3-imsics", "riscv,imsics";
+			reg = <0x0 0xf1000000 0x0 0x10000>;
+			#interrupt-cells = <0>;
+			#msi-cells = <0>;
+			interrupt-controller;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>,
+					      <&cpu2_intc 11>, <&cpu3_intc 11>,
+					      <&cpu4_intc 11>, <&cpu5_intc 11>,
+					      <&cpu6_intc 11>, <&cpu7_intc 11>;
+			msi-controller;
+			riscv,guest-index-bits = <6>;
+			riscv,hart-index-bits = <4>;
+			riscv,num-guest-ids = <511>;
+			riscv,num-ids = <511>;
+
+			status = "reserved";
+		};
+
+		maplic: interrupt-controller@f1800000 {
+			compatible = "spacemit,k3-aplic", "riscv,aplic";
+			reg = <0x0 0xf1800000 0x0 0x4000>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			msi-parent = <&mimsic>;
+			riscv,children = <&saplic>;
+			riscv,delegation = <&saplic 1 512>;
+			riscv,num-sources = <512>;
+
+			status = "reserved";
+		};
+	};
+};

-- 
2.43.0

[PATCH v5 7/7] riscv: dts: spacemit: add K3 Pico-ITX board support

[Guodong Xu]

K3 Pico-ITX is a 2.5-inch single-board computer equipted with a SpacemiT
K3 SoC.

This minimal device tree enables booting into a serial console with UART
output.

Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v5: Update the commit message subject per Yixun's suggestion.
    Remove the unused aliases.
    Update the copyright year to 2026.
v4: No change.
v3: No change.
v2: Add aliases node in this board DT.
    Update the memory node to reflect the hardware truth. Address
     starts at 0x100000000 (4G) boundary.
---
 arch/riscv/boot/dts/spacemit/Makefile        |  1 +
 arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 29 ++++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile
index 95889e7269d1..7e2b87702571 100644
--- a/arch/riscv/boot/dts/spacemit/Makefile
+++ b/arch/riscv/boot/dts/spacemit/Makefile
@@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb
 dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb
 dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb
 dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb
+dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb
diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
new file mode 100644
index 000000000000..b691304d4b74
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd
+ * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
+ */
+
+#include "k3.dtsi"
+
+/ {
+	model = "SpacemiT K3 Pico-ITX";
+	compatible = "spacemit,k3-pico-itx", "spacemit,k3";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+
+	memory@100000000 {
+		device_type = "memory";
+		reg = <0x1 0x00000000 0x4 0x00000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};

-- 
2.43.0

Re: [PATCH v5 0/7] riscv: spacemit: Add SpacemiT K3 SoC and K3 Pico-ITX board

[Yixun Lan]

On Thu, 15 Jan 2026 14:51:39 +0800, Guodong Xu wrote:
> This series introduces basic support for the SpacemiT K3 SoC and the
> K3 Pico-ITX evaluation board.
> 
> In v5, patches 6-9 (dt-bindings) have been dropped as they were accepted
> by Conor and applied to riscv-dt-for-next.
> 
> The series has been rebased on linux-next tag: next-20260114.
> 
> [...]

Applied, thanks!

[1/7] dt-bindings: riscv: add SpacemiT X100 CPU compatible
      https://github.com/spacemit-com/linux/commit/14f77777687e182aa782db86220409f4c149e0b8
[2/7] dt-bindings: timer: add SpacemiT K3 CLINT
      https://github.com/spacemit-com/linux/commit/b647b5e6a7e6533c2974f9aa3255aa7879a7b5f4
[3/7] dt-bindings: interrupt-controller: add SpacemiT K3 APLIC
      https://github.com/spacemit-com/linux/commit/23b3bd93e1e14c1cf7146166c39bdb24e7d713c7
[4/7] dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC
      https://github.com/spacemit-com/linux/commit/5c414d0c0987b95cc985b23e532f1341371eef86
[5/7] dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings
      https://github.com/spacemit-com/linux/commit/66041d5fd564d94249d41bb6aa004ff1e3f25787
[6/7] riscv: dts: spacemit: add initial support for K3 SoC
      https://github.com/spacemit-com/linux/commit/0ef9a718421fbc464edb6e5f6d483e0915e18599
[7/7] riscv: dts: spacemit: add K3 Pico-ITX board support
      https://github.com/spacemit-com/linux/commit/8e149fcd4854204bbb82ee037cdfb62a9978587f

Best regards,
-- 
Yixun Lan <dlan@kernel.org>

Re: [PATCH v5 6/7] riscv: dts: spacemit: add initial support for K3 SoC

[Heinrich Schuchardt]

On 1/15/26 07:51, Guodong Xu wrote:
> SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant.
> Add nodes of uarts, timer and interrupt-controllers. Also add M-mode
> APLIC (maplic) and IMSIC (mimsic) nodes to represent the hardware
> topology and ready for potential firmware usage.
> 
> Signed-off-by: Guodong Xu <guodong@riscstar.com>
> ---
> v5: Update the copyright year to 2026.
>      Set M-mode maplic and mimsic status to "reserved".
>      Update the commit message per Yixun's suggestion.
>      In maplic node, use riscv,delegation to match kernel binding. OpenSBI
>       accepts both delegate and delegation, but the binding documents only
>       riscv,delegation.
> v4: Fix missing blank space after commas in compatible string.
>      Add m-mode imsic and aplic node.
>      Reorder properties in simsic, saplic, mimsic, and maplic nodes
>       to match DTS coding style.
> v3: Remove "supm" from the riscv,isa-extensions list.
> v2: Remove aliases from k3.dtsi, they should be in board DTS.
>      Updated riscv,isa-extensions with new extensions from the extensions.yaml.
> ---
>   arch/riscv/boot/dts/spacemit/k3.dtsi | 590 +++++++++++++++++++++++++++++++++++
>   1 file changed, 590 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> new file mode 100644
> index 000000000000..53425badfea9
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> @@ -0,0 +1,590 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd
> + * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/dts-v1/;
> +
> +/ {
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +	model = "SpacemiT K3";
> +	compatible = "spacemit,k3";
> +
> +	cpus: cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		timebase-frequency = <24000000>;
> +
> +		cpu_0: cpu@0 {
> +			compatible = "spacemit,x100", "riscv";
> +			device_type = "cpu";
> +			reg = <0>;
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> +					       "sha", "shcounterenw", "shgatpa", "shtvala",
> +					       "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> +					       "smstateen", "ssaia", "ssccptr", "sscofpmf",
> +					       "sscounterenw", "ssnpm", "ssstateen", "sstc",
> +					       "sstvala", "sstvecd", "ssu64xl", "svade",
> +					       "svinval", "svnapot", "svpbmt", "za64rs",
> +					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> +					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> +					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> +					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
> +					       "zicond", "zicsr", "zifencei", "zihintntl",
> +					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> +					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> +					       "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> +					       "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> +					       "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <256>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <256>;
> +			next-level-cache = <&l2_cache0>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu0_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				#interrupt-cells = <1>;
> +				interrupt-controller;
> +			};
> +		};
> +
> +		cpu_1: cpu@1 {
> +			compatible = "spacemit,x100", "riscv";
> +			device_type = "cpu";
> +			reg = <1>;
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> +					       "sha", "shcounterenw", "shgatpa", "shtvala",
> +					       "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> +					       "smstateen", "ssaia", "ssccptr", "sscofpmf",
> +					       "sscounterenw", "ssnpm", "ssstateen", "sstc",
> +					       "sstvala", "sstvecd", "ssu64xl", "svade",
> +					       "svinval", "svnapot", "svpbmt", "za64rs",
> +					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> +					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> +					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> +					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
> +					       "zicond", "zicsr", "zifencei", "zihintntl",
> +					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> +					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> +					       "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> +					       "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> +					       "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <256>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <256>;
> +			next-level-cache = <&l2_cache0>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu1_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				#interrupt-cells = <1>;
> +				interrupt-controller;
> +			};
> +		};
> +
> +		cpu_2: cpu@2 {
> +			compatible = "spacemit,x100", "riscv";
> +			device_type = "cpu";
> +			reg = <2>;
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> +					       "sha", "shcounterenw", "shgatpa", "shtvala",
> +					       "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> +					       "smstateen", "ssaia", "ssccptr", "sscofpmf",
> +					       "sscounterenw", "ssnpm", "ssstateen", "sstc",
> +					       "sstvala", "sstvecd", "ssu64xl", "svade",
> +					       "svinval", "svnapot", "svpbmt", "za64rs",
> +					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> +					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> +					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> +					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
> +					       "zicond", "zicsr", "zifencei", "zihintntl",
> +					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> +					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> +					       "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> +					       "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> +					       "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <256>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <256>;
> +			next-level-cache = <&l2_cache0>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu2_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				#interrupt-cells = <1>;
> +				interrupt-controller;
> +			};
> +		};
> +
> +		cpu_3: cpu@3 {
> +			compatible = "spacemit,x100", "riscv";
> +			device_type = "cpu";
> +			reg = <3>;
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> +					       "sha", "shcounterenw", "shgatpa", "shtvala",
> +					       "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> +					       "smstateen", "ssaia", "ssccptr", "sscofpmf",
> +					       "sscounterenw", "ssnpm", "ssstateen", "sstc",
> +					       "sstvala", "sstvecd", "ssu64xl", "svade",
> +					       "svinval", "svnapot", "svpbmt", "za64rs",
> +					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> +					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> +					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> +					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
> +					       "zicond", "zicsr", "zifencei", "zihintntl",
> +					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> +					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> +					       "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> +					       "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> +					       "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <256>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <256>;
> +			next-level-cache = <&l2_cache0>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu3_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				#interrupt-cells = <1>;
> +				interrupt-controller;
> +			};
> +		};
> +
> +		cpu_4: cpu@4 {
> +			compatible = "spacemit,x100", "riscv";
> +			device_type = "cpu";
> +			reg = <4>;
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> +					       "sha", "shcounterenw", "shgatpa", "shtvala",
> +					       "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> +					       "smstateen", "ssaia", "ssccptr", "sscofpmf",
> +					       "sscounterenw", "ssnpm", "ssstateen", "sstc",
> +					       "sstvala", "sstvecd", "ssu64xl", "svade",
> +					       "svinval", "svnapot", "svpbmt", "za64rs",
> +					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> +					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> +					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> +					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
> +					       "zicond", "zicsr", "zifencei", "zihintntl",
> +					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> +					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> +					       "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> +					       "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> +					       "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <256>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <256>;
> +			next-level-cache = <&l2_cache1>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu4_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				#interrupt-cells = <1>;
> +				interrupt-controller;
> +			};
> +		};
> +
> +		cpu_5: cpu@5 {
> +			compatible = "spacemit,x100", "riscv";
> +			device_type = "cpu";
> +			reg = <5>;
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> +					       "sha", "shcounterenw", "shgatpa", "shtvala",
> +					       "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> +					       "smstateen", "ssaia", "ssccptr", "sscofpmf",
> +					       "sscounterenw", "ssnpm", "ssstateen", "sstc",
> +					       "sstvala", "sstvecd", "ssu64xl", "svade",
> +					       "svinval", "svnapot", "svpbmt", "za64rs",
> +					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> +					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> +					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> +					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
> +					       "zicond", "zicsr", "zifencei", "zihintntl",
> +					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> +					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> +					       "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> +					       "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> +					       "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";

Should zvl256b be added to the X100 description to indicate the vector 
length?

Best regards

Heinrich


> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <256>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <256>;
> +			next-level-cache = <&l2_cache1>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu5_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				#interrupt-cells = <1>;
> +				interrupt-controller;
> +			};
> +		};
> +
> +		cpu_6: cpu@6 {
> +			compatible = "spacemit,x100", "riscv";
> +			device_type = "cpu";
> +			reg = <6>;
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> +					       "sha", "shcounterenw", "shgatpa", "shtvala",
> +					       "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> +					       "smstateen", "ssaia", "ssccptr", "sscofpmf",
> +					       "sscounterenw", "ssnpm", "ssstateen", "sstc",
> +					       "sstvala", "sstvecd", "ssu64xl", "svade",
> +					       "svinval", "svnapot", "svpbmt", "za64rs",
> +					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> +					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> +					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> +					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
> +					       "zicond", "zicsr", "zifencei", "zihintntl",
> +					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> +					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> +					       "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> +					       "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> +					       "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <256>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <256>;
> +			next-level-cache = <&l2_cache1>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu6_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				#interrupt-cells = <1>;
> +				interrupt-controller;
> +			};
> +		};
> +
> +		cpu_7: cpu@7 {
> +			compatible = "spacemit,x100", "riscv";
> +			device_type = "cpu";
> +			reg = <7>;
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> +					       "sha", "shcounterenw", "shgatpa", "shtvala",
> +					       "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> +					       "smstateen", "ssaia", "ssccptr", "sscofpmf",
> +					       "sscounterenw", "ssnpm", "ssstateen", "sstc",
> +					       "sstvala", "sstvecd", "ssu64xl", "svade",
> +					       "svinval", "svnapot", "svpbmt", "za64rs",
> +					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> +					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> +					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> +					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
> +					       "zicond", "zicsr", "zifencei", "zihintntl",
> +					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> +					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> +					       "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> +					       "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> +					       "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <256>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <256>;
> +			next-level-cache = <&l2_cache1>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu7_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				#interrupt-cells = <1>;
> +				interrupt-controller;
> +			};
> +		};
> +
> +		l2_cache0: cache-controller-0 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <4194304>;
> +			cache-sets = <4096>;
> +			cache-unified;
> +		};
> +
> +		l2_cache1: cache-controller-1 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <4194304>;
> +			cache-sets = <4096>;
> +			cache-unified;
> +		};
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu_0>;
> +				};
> +				core1 {
> +					cpu = <&cpu_1>;
> +				};
> +				core2 {
> +					cpu = <&cpu_2>;
> +				};
> +				core3 {
> +					cpu = <&cpu_3>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&cpu_4>;
> +				};
> +				core1 {
> +					cpu = <&cpu_5>;
> +				};
> +				core2 {
> +					cpu = <&cpu_6>;
> +				};
> +				core3 {
> +					cpu = <&cpu_7>;
> +				};
> +			};
> +		};
> +	};
> +
> +	soc: soc {
> +		compatible = "simple-bus";
> +		interrupt-parent = <&saplic>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		dma-noncoherent;
> +		ranges;
> +
> +		uart0: serial@d4017000 {
> +			compatible = "spacemit,k3-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017000 0x0 0x100>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clock-frequency = <14700000>;
> +			interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@d4017100 {
> +			compatible = "spacemit,k3-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017100 0x0 0x100>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clock-frequency = <14700000>;
> +			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@d4017200 {
> +			compatible = "spacemit,k3-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017200 0x0 0x100>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clock-frequency = <14700000>;
> +			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			status = "disabled";
> +		};
> +
> +		uart4: serial@d4017300 {
> +			compatible = "spacemit,k3-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017300 0x0 0x100>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clock-frequency = <14700000>;
> +			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			status = "disabled";
> +		};
> +
> +		uart5: serial@d4017400 {
> +			compatible = "spacemit,k3-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017400 0x0 0x100>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clock-frequency = <14700000>;
> +			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			status = "disabled";
> +		};
> +
> +		uart6: serial@d4017500 {
> +			compatible = "spacemit,k3-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017500 0x0 0x100>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clock-frequency = <14700000>;
> +			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			status = "disabled";
> +		};
> +
> +		uart7: serial@d4017600 {
> +			compatible = "spacemit,k3-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017600 0x0 0x100>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clock-frequency = <14700000>;
> +			interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			status = "disabled";
> +		};
> +
> +		uart8: serial@d4017700 {
> +			compatible = "spacemit,k3-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017700 0x0 0x100>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clock-frequency = <14700000>;
> +			interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			status = "disabled";
> +		};
> +
> +		uart9: serial@d4017800 {
> +			compatible = "spacemit,k3-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017800 0x0 0x100>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clock-frequency = <14700000>;
> +			interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			status = "disabled";
> +		};
> +
> +		uart10: serial@d401f000 {
> +			compatible = "spacemit,k3-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd401f000 0x0 0x100>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clock-frequency = <14700000>;
> +			interrupts = <281 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			status = "disabled";
> +		};
> +
> +		simsic: interrupt-controller@e0400000 {
> +			compatible = "spacemit,k3-imsics", "riscv,imsics";
> +			reg = <0x0 0xe0400000 0x0 0x200000>;
> +			#interrupt-cells = <0>;
> +			#msi-cells = <0>;
> +			interrupt-controller;
> +			interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>,
> +					      <&cpu2_intc 9>, <&cpu3_intc 9>,
> +					      <&cpu4_intc 9>, <&cpu5_intc 9>,
> +					      <&cpu6_intc 9>, <&cpu7_intc 9>;
> +			msi-controller;
> +			riscv,guest-index-bits = <6>;
> +			riscv,hart-index-bits = <4>;
> +			riscv,num-guest-ids = <511>;
> +			riscv,num-ids = <511>;
> +		};
> +
> +		saplic: interrupt-controller@e0804000 {
> +			compatible = "spacemit,k3-aplic", "riscv,aplic";
> +			reg = <0x0 0xe0804000 0x0 0x4000>;
> +			#interrupt-cells = <2>;
> +			interrupt-controller;
> +			msi-parent = <&simsic>;
> +			riscv,num-sources = <512>;
> +		};
> +
> +		clint: timer@e081c000 {
> +			compatible = "spacemit,k3-clint", "sifive,clint0";
> +			reg = <0x0 0xe081c000 0x0 0x4000>;
> +			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> +					      <&cpu1_intc 3>, <&cpu1_intc 7>,
> +					      <&cpu2_intc 3>, <&cpu2_intc 7>,
> +					      <&cpu3_intc 3>, <&cpu3_intc 7>,
> +					      <&cpu4_intc 3>, <&cpu4_intc 7>,
> +					      <&cpu5_intc 3>, <&cpu5_intc 7>,
> +					      <&cpu6_intc 3>, <&cpu6_intc 7>,
> +					      <&cpu7_intc 3>, <&cpu7_intc 7>;
> +		};
> +
> +		mimsic: interrupt-controller@f1000000 {
> +			compatible = "spacemit,k3-imsics", "riscv,imsics";
> +			reg = <0x0 0xf1000000 0x0 0x10000>;
> +			#interrupt-cells = <0>;
> +			#msi-cells = <0>;
> +			interrupt-controller;
> +			interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>,
> +					      <&cpu2_intc 11>, <&cpu3_intc 11>,
> +					      <&cpu4_intc 11>, <&cpu5_intc 11>,
> +					      <&cpu6_intc 11>, <&cpu7_intc 11>;
> +			msi-controller;
> +			riscv,guest-index-bits = <6>;
> +			riscv,hart-index-bits = <4>;
> +			riscv,num-guest-ids = <511>;
> +			riscv,num-ids = <511>;
> +
> +			status = "reserved";
> +		};
> +
> +		maplic: interrupt-controller@f1800000 {
> +			compatible = "spacemit,k3-aplic", "riscv,aplic";
> +			reg = <0x0 0xf1800000 0x0 0x4000>;
> +			#interrupt-cells = <2>;
> +			interrupt-controller;
> +			msi-parent = <&mimsic>;
> +			riscv,children = <&saplic>;
> +			riscv,delegation = <&saplic 1 512>;
> +			riscv,num-sources = <512>;
> +
> +			status = "reserved";
> +		};
> +	};
> +};
> 

Re: [PATCH v5 6/7] riscv: dts: spacemit: add initial support for K3 SoC

[Guodong Xu]

Hi, Heinrich

On Sun, Jan 18, 2026 at 7:41 AM Heinrich Schuchardt <xypron.glpk@gmx.de> wrote:
>
> On 1/15/26 07:51, Guodong Xu wrote:
> > SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant.
> > Add nodes of uarts, timer and interrupt-controllers. Also add M-mode
> > APLIC (maplic) and IMSIC (mimsic) nodes to represent the hardware
> > topology and ready for potential firmware usage.
> >
> > Signed-off-by: Guodong Xu <guodong@riscstar.com>
> > ---
> > v5: Update the copyright year to 2026.
> >      Set M-mode maplic and mimsic status to "reserved".
> >      Update the commit message per Yixun's suggestion.
> >      In maplic node, use riscv,delegation to match kernel binding. OpenSBI
> >       accepts both delegate and delegation, but the binding documents only
> >       riscv,delegation.
> > v4: Fix missing blank space after commas in compatible string.
> >      Add m-mode imsic and aplic node.
> >      Reorder properties in simsic, saplic, mimsic, and maplic nodes
> >       to match DTS coding style.
> > v3: Remove "supm" from the riscv,isa-extensions list.
> > v2: Remove aliases from k3.dtsi, they should be in board DTS.
> >      Updated riscv,isa-extensions with new extensions from the extensions.yaml.
> > ---
> >   arch/riscv/boot/dts/spacemit/k3.dtsi | 590 +++++++++++++++++++++++++++++++++++
> >   1 file changed, 590 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > new file mode 100644
> > index 000000000000..53425badfea9
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > @@ -0,0 +1,590 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd
> > + * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/dts-v1/;
> > +
> > +/ {
> > +     #address-cells = <2>;
> > +     #size-cells = <2>;
> > +     model = "SpacemiT K3";
> > +     compatible = "spacemit,k3";
> > +
> > +     cpus: cpus {
> > +             #address-cells = <1>;
> > +             #size-cells = <0>;
> > +             timebase-frequency = <24000000>;
> > +
> > +             cpu_0: cpu@0 {
> > +                     compatible = "spacemit,x100", "riscv";
> > +                     device_type = "cpu";
> > +                     reg = <0>;
> > +                     riscv,isa-base = "rv64i";
> > +                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> > +                                            "sha", "shcounterenw", "shgatpa", "shtvala",
> > +                                            "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> > +                                            "smstateen", "ssaia", "ssccptr", "sscofpmf",
> > +                                            "sscounterenw", "ssnpm", "ssstateen", "sstc",
> > +                                            "sstvala", "sstvecd", "ssu64xl", "svade",
> > +                                            "svinval", "svnapot", "svpbmt", "za64rs",
> > +                                            "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> > +                                            "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> > +                                            "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> > +                                            "ziccamoa", "ziccif", "zicclsm", "zicntr",
> > +                                            "zicond", "zicsr", "zifencei", "zihintntl",
> > +                                            "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> > +                                            "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> > +                                            "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> > +                                            "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> > +                                            "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> > +                     riscv,cbom-block-size = <64>;
> > +                     riscv,cbop-block-size = <64>;
> > +                     riscv,cboz-block-size = <64>;
> > +                     i-cache-block-size = <64>;
> > +                     i-cache-size = <65536>;
> > +                     i-cache-sets = <256>;
> > +                     d-cache-block-size = <64>;
> > +                     d-cache-size = <65536>;
> > +                     d-cache-sets = <256>;
> > +                     next-level-cache = <&l2_cache0>;
> > +                     mmu-type = "riscv,sv39";
> > +
> > +                     cpu0_intc: interrupt-controller {
> > +                             compatible = "riscv,cpu-intc";
> > +                             #interrupt-cells = <1>;
> > +                             interrupt-controller;
> > +                     };
> > +             };
> > +
> > +             cpu_1: cpu@1 {
> > +                     compatible = "spacemit,x100", "riscv";
> > +                     device_type = "cpu";
> > +                     reg = <1>;
> > +                     riscv,isa-base = "rv64i";
> > +                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> > +                                            "sha", "shcounterenw", "shgatpa", "shtvala",
> > +                                            "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> > +                                            "smstateen", "ssaia", "ssccptr", "sscofpmf",
> > +                                            "sscounterenw", "ssnpm", "ssstateen", "sstc",
> > +                                            "sstvala", "sstvecd", "ssu64xl", "svade",
> > +                                            "svinval", "svnapot", "svpbmt", "za64rs",
> > +                                            "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> > +                                            "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> > +                                            "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> > +                                            "ziccamoa", "ziccif", "zicclsm", "zicntr",
> > +                                            "zicond", "zicsr", "zifencei", "zihintntl",
> > +                                            "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> > +                                            "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> > +                                            "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> > +                                            "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> > +                                            "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> > +                     riscv,cbom-block-size = <64>;
> > +                     riscv,cbop-block-size = <64>;
> > +                     riscv,cboz-block-size = <64>;
> > +                     i-cache-block-size = <64>;
> > +                     i-cache-size = <65536>;
> > +                     i-cache-sets = <256>;
> > +                     d-cache-block-size = <64>;
> > +                     d-cache-size = <65536>;
> > +                     d-cache-sets = <256>;
> > +                     next-level-cache = <&l2_cache0>;
> > +                     mmu-type = "riscv,sv39";
> > +
> > +                     cpu1_intc: interrupt-controller {
> > +                             compatible = "riscv,cpu-intc";
> > +                             #interrupt-cells = <1>;
> > +                             interrupt-controller;
> > +                     };
> > +             };
> > +
> > +             cpu_2: cpu@2 {
> > +                     compatible = "spacemit,x100", "riscv";
> > +                     device_type = "cpu";
> > +                     reg = <2>;
> > +                     riscv,isa-base = "rv64i";
> > +                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> > +                                            "sha", "shcounterenw", "shgatpa", "shtvala",
> > +                                            "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> > +                                            "smstateen", "ssaia", "ssccptr", "sscofpmf",
> > +                                            "sscounterenw", "ssnpm", "ssstateen", "sstc",
> > +                                            "sstvala", "sstvecd", "ssu64xl", "svade",
> > +                                            "svinval", "svnapot", "svpbmt", "za64rs",
> > +                                            "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> > +                                            "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> > +                                            "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> > +                                            "ziccamoa", "ziccif", "zicclsm", "zicntr",
> > +                                            "zicond", "zicsr", "zifencei", "zihintntl",
> > +                                            "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> > +                                            "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> > +                                            "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> > +                                            "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> > +                                            "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> > +                     riscv,cbom-block-size = <64>;
> > +                     riscv,cbop-block-size = <64>;
> > +                     riscv,cboz-block-size = <64>;
> > +                     i-cache-block-size = <64>;
> > +                     i-cache-size = <65536>;
> > +                     i-cache-sets = <256>;
> > +                     d-cache-block-size = <64>;
> > +                     d-cache-size = <65536>;
> > +                     d-cache-sets = <256>;
> > +                     next-level-cache = <&l2_cache0>;
> > +                     mmu-type = "riscv,sv39";
> > +
> > +                     cpu2_intc: interrupt-controller {
> > +                             compatible = "riscv,cpu-intc";
> > +                             #interrupt-cells = <1>;
> > +                             interrupt-controller;
> > +                     };
> > +             };
> > +
> > +             cpu_3: cpu@3 {
> > +                     compatible = "spacemit,x100", "riscv";
> > +                     device_type = "cpu";
> > +                     reg = <3>;
> > +                     riscv,isa-base = "rv64i";
> > +                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> > +                                            "sha", "shcounterenw", "shgatpa", "shtvala",
> > +                                            "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> > +                                            "smstateen", "ssaia", "ssccptr", "sscofpmf",
> > +                                            "sscounterenw", "ssnpm", "ssstateen", "sstc",
> > +                                            "sstvala", "sstvecd", "ssu64xl", "svade",
> > +                                            "svinval", "svnapot", "svpbmt", "za64rs",
> > +                                            "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> > +                                            "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> > +                                            "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> > +                                            "ziccamoa", "ziccif", "zicclsm", "zicntr",
> > +                                            "zicond", "zicsr", "zifencei", "zihintntl",
> > +                                            "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> > +                                            "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> > +                                            "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> > +                                            "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> > +                                            "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> > +                     riscv,cbom-block-size = <64>;
> > +                     riscv,cbop-block-size = <64>;
> > +                     riscv,cboz-block-size = <64>;
> > +                     i-cache-block-size = <64>;
> > +                     i-cache-size = <65536>;
> > +                     i-cache-sets = <256>;
> > +                     d-cache-block-size = <64>;
> > +                     d-cache-size = <65536>;
> > +                     d-cache-sets = <256>;
> > +                     next-level-cache = <&l2_cache0>;
> > +                     mmu-type = "riscv,sv39";
> > +
> > +                     cpu3_intc: interrupt-controller {
> > +                             compatible = "riscv,cpu-intc";
> > +                             #interrupt-cells = <1>;
> > +                             interrupt-controller;
> > +                     };
> > +             };
> > +
> > +             cpu_4: cpu@4 {
> > +                     compatible = "spacemit,x100", "riscv";
> > +                     device_type = "cpu";
> > +                     reg = <4>;
> > +                     riscv,isa-base = "rv64i";
> > +                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> > +                                            "sha", "shcounterenw", "shgatpa", "shtvala",
> > +                                            "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> > +                                            "smstateen", "ssaia", "ssccptr", "sscofpmf",
> > +                                            "sscounterenw", "ssnpm", "ssstateen", "sstc",
> > +                                            "sstvala", "sstvecd", "ssu64xl", "svade",
> > +                                            "svinval", "svnapot", "svpbmt", "za64rs",
> > +                                            "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> > +                                            "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> > +                                            "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> > +                                            "ziccamoa", "ziccif", "zicclsm", "zicntr",
> > +                                            "zicond", "zicsr", "zifencei", "zihintntl",
> > +                                            "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> > +                                            "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> > +                                            "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> > +                                            "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> > +                                            "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> > +                     riscv,cbom-block-size = <64>;
> > +                     riscv,cbop-block-size = <64>;
> > +                     riscv,cboz-block-size = <64>;
> > +                     i-cache-block-size = <64>;
> > +                     i-cache-size = <65536>;
> > +                     i-cache-sets = <256>;
> > +                     d-cache-block-size = <64>;
> > +                     d-cache-size = <65536>;
> > +                     d-cache-sets = <256>;
> > +                     next-level-cache = <&l2_cache1>;
> > +                     mmu-type = "riscv,sv39";
> > +
> > +                     cpu4_intc: interrupt-controller {
> > +                             compatible = "riscv,cpu-intc";
> > +                             #interrupt-cells = <1>;
> > +                             interrupt-controller;
> > +                     };
> > +             };
> > +
> > +             cpu_5: cpu@5 {
> > +                     compatible = "spacemit,x100", "riscv";
> > +                     device_type = "cpu";
> > +                     reg = <5>;
> > +                     riscv,isa-base = "rv64i";
> > +                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> > +                                            "sha", "shcounterenw", "shgatpa", "shtvala",
> > +                                            "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> > +                                            "smstateen", "ssaia", "ssccptr", "sscofpmf",
> > +                                            "sscounterenw", "ssnpm", "ssstateen", "sstc",
> > +                                            "sstvala", "sstvecd", "ssu64xl", "svade",
> > +                                            "svinval", "svnapot", "svpbmt", "za64rs",
> > +                                            "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> > +                                            "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> > +                                            "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> > +                                            "ziccamoa", "ziccif", "zicclsm", "zicntr",
> > +                                            "zicond", "zicsr", "zifencei", "zihintntl",
> > +                                            "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> > +                                            "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> > +                                            "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> > +                                            "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> > +                                            "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
>
> Should zvl256b be added to the X100 description to indicate the vector
> length?

This is a general topic relevant to all "v" capable RISC-V cores.

To my knowledge, there are currently no upstream Device Tree bindings defined
for zvl*b or vlen. Instead of defining this statically in the DTS, the kernel
history suggests a preference for dynamic discovery. With the existence of
CSR_VLENB, reading it during kernel boot (or say 'hart boot') makes more sense.

This is what actually happening in the kernel right now.

This approach has been part of the design since the earliest
implementations [1].

Link: https://lore.kernel.org/linux-riscv/e896db91e3303f64ac401021f848e536e9d42aaa.1590474856.git.greentime.hu@sifive.com/
[1]

BR,
Guodong Xu

>
> Best regards
>
> Heinrich
>
>
> > +                     riscv,cbom-block-size = <64>;
> > +                     riscv,cbop-block-size = <64>;
> > +                     riscv,cboz-block-size = <64>;
> > +                     i-cache-block-size = <64>;
> > +                     i-cache-size = <65536>;
> > +                     i-cache-sets = <256>;
> > +                     d-cache-block-size = <64>;
> > +                     d-cache-size = <65536>;
> > +                     d-cache-sets = <256>;
> > +                     next-level-cache = <&l2_cache1>;
> > +                     mmu-type = "riscv,sv39";
> > +
> > +                     cpu5_intc: interrupt-controller {
> > +                             compatible = "riscv,cpu-intc";
> > +                             #interrupt-cells = <1>;
> > +                             interrupt-controller;
> > +                     };
> > +             };
> > +
> > +             cpu_6: cpu@6 {
> > +                     compatible = "spacemit,x100", "riscv";
> > +                     device_type = "cpu";
> > +                     reg = <6>;
> > +                     riscv,isa-base = "rv64i";
> > +                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> > +                                            "sha", "shcounterenw", "shgatpa", "shtvala",
> > +                                            "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> > +                                            "smstateen", "ssaia", "ssccptr", "sscofpmf",
> > +                                            "sscounterenw", "ssnpm", "ssstateen", "sstc",
> > +                                            "sstvala", "sstvecd", "ssu64xl", "svade",
> > +                                            "svinval", "svnapot", "svpbmt", "za64rs",
> > +                                            "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> > +                                            "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> > +                                            "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> > +                                            "ziccamoa", "ziccif", "zicclsm", "zicntr",
> > +                                            "zicond", "zicsr", "zifencei", "zihintntl",
> > +                                            "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> > +                                            "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> > +                                            "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> > +                                            "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> > +                                            "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> > +                     riscv,cbom-block-size = <64>;
> > +                     riscv,cbop-block-size = <64>;
> > +                     riscv,cboz-block-size = <64>;
> > +                     i-cache-block-size = <64>;
> > +                     i-cache-size = <65536>;
> > +                     i-cache-sets = <256>;
> > +                     d-cache-block-size = <64>;
> > +                     d-cache-size = <65536>;
> > +                     d-cache-sets = <256>;
> > +                     next-level-cache = <&l2_cache1>;
> > +                     mmu-type = "riscv,sv39";
> > +
> > +                     cpu6_intc: interrupt-controller {
> > +                             compatible = "riscv,cpu-intc";
> > +                             #interrupt-cells = <1>;
> > +                             interrupt-controller;
> > +                     };
> > +             };
> > +
> > +             cpu_7: cpu@7 {
> > +                     compatible = "spacemit,x100", "riscv";
> > +                     device_type = "cpu";
> > +                     reg = <7>;
> > +                     riscv,isa-base = "rv64i";
> > +                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> > +                                            "sha", "shcounterenw", "shgatpa", "shtvala",
> > +                                            "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> > +                                            "smstateen", "ssaia", "ssccptr", "sscofpmf",
> > +                                            "sscounterenw", "ssnpm", "ssstateen", "sstc",
> > +                                            "sstvala", "sstvecd", "ssu64xl", "svade",
> > +                                            "svinval", "svnapot", "svpbmt", "za64rs",
> > +                                            "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> > +                                            "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> > +                                            "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> > +                                            "ziccamoa", "ziccif", "zicclsm", "zicntr",
> > +                                            "zicond", "zicsr", "zifencei", "zihintntl",
> > +                                            "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> > +                                            "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> > +                                            "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> > +                                            "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> > +                                            "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> > +                     riscv,cbom-block-size = <64>;
> > +                     riscv,cbop-block-size = <64>;
> > +                     riscv,cboz-block-size = <64>;
> > +                     i-cache-block-size = <64>;
> > +                     i-cache-size = <65536>;
> > +                     i-cache-sets = <256>;
> > +                     d-cache-block-size = <64>;
> > +                     d-cache-size = <65536>;
> > +                     d-cache-sets = <256>;
> > +                     next-level-cache = <&l2_cache1>;
> > +                     mmu-type = "riscv,sv39";
> > +
> > +                     cpu7_intc: interrupt-controller {
> > +                             compatible = "riscv,cpu-intc";
> > +                             #interrupt-cells = <1>;
> > +                             interrupt-controller;
> > +                     };
> > +             };
> > +
> > +             l2_cache0: cache-controller-0 {
> > +                     compatible = "cache";
> > +                     cache-block-size = <64>;
> > +                     cache-level = <2>;
> > +                     cache-size = <4194304>;
> > +                     cache-sets = <4096>;
> > +                     cache-unified;
> > +             };
> > +
> > +             l2_cache1: cache-controller-1 {
> > +                     compatible = "cache";
> > +                     cache-block-size = <64>;
> > +                     cache-level = <2>;
> > +                     cache-size = <4194304>;
> > +                     cache-sets = <4096>;
> > +                     cache-unified;
> > +             };
> > +
> > +             cpu-map {
> > +                     cluster0 {
> > +                             core0 {
> > +                                     cpu = <&cpu_0>;
> > +                             };
> > +                             core1 {
> > +                                     cpu = <&cpu_1>;
> > +                             };
> > +                             core2 {
> > +                                     cpu = <&cpu_2>;
> > +                             };
> > +                             core3 {
> > +                                     cpu = <&cpu_3>;
> > +                             };
> > +                     };
> > +
> > +                     cluster1 {
> > +                             core0 {
> > +                                     cpu = <&cpu_4>;
> > +                             };
> > +                             core1 {
> > +                                     cpu = <&cpu_5>;
> > +                             };
> > +                             core2 {
> > +                                     cpu = <&cpu_6>;
> > +                             };
> > +                             core3 {
> > +                                     cpu = <&cpu_7>;
> > +                             };
> > +                     };
> > +             };
> > +     };
> > +
> > +     soc: soc {
> > +             compatible = "simple-bus";
> > +             interrupt-parent = <&saplic>;
> > +             #address-cells = <2>;
> > +             #size-cells = <2>;
> > +             dma-noncoherent;
> > +             ranges;
> > +
> > +             uart0: serial@d4017000 {
> > +                     compatible = "spacemit,k3-uart", "intel,xscale-uart";
> > +                     reg = <0x0 0xd4017000 0x0 0x100>;
> > +                     reg-shift = <2>;
> > +                     reg-io-width = <4>;
> > +                     clock-frequency = <14700000>;
> > +                     interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +                     status = "disabled";
> > +             };
> > +
> > +             uart2: serial@d4017100 {
> > +                     compatible = "spacemit,k3-uart", "intel,xscale-uart";
> > +                     reg = <0x0 0xd4017100 0x0 0x100>;
> > +                     reg-shift = <2>;
> > +                     reg-io-width = <4>;
> > +                     clock-frequency = <14700000>;
> > +                     interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +                     status = "disabled";
> > +             };
> > +
> > +             uart3: serial@d4017200 {
> > +                     compatible = "spacemit,k3-uart", "intel,xscale-uart";
> > +                     reg = <0x0 0xd4017200 0x0 0x100>;
> > +                     reg-shift = <2>;
> > +                     reg-io-width = <4>;
> > +                     clock-frequency = <14700000>;
> > +                     interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +                     status = "disabled";
> > +             };
> > +
> > +             uart4: serial@d4017300 {
> > +                     compatible = "spacemit,k3-uart", "intel,xscale-uart";
> > +                     reg = <0x0 0xd4017300 0x0 0x100>;
> > +                     reg-shift = <2>;
> > +                     reg-io-width = <4>;
> > +                     clock-frequency = <14700000>;
> > +                     interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +                     status = "disabled";
> > +             };
> > +
> > +             uart5: serial@d4017400 {
> > +                     compatible = "spacemit,k3-uart", "intel,xscale-uart";
> > +                     reg = <0x0 0xd4017400 0x0 0x100>;
> > +                     reg-shift = <2>;
> > +                     reg-io-width = <4>;
> > +                     clock-frequency = <14700000>;
> > +                     interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +                     status = "disabled";
> > +             };
> > +
> > +             uart6: serial@d4017500 {
> > +                     compatible = "spacemit,k3-uart", "intel,xscale-uart";
> > +                     reg = <0x0 0xd4017500 0x0 0x100>;
> > +                     reg-shift = <2>;
> > +                     reg-io-width = <4>;
> > +                     clock-frequency = <14700000>;
> > +                     interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +                     status = "disabled";
> > +             };
> > +
> > +             uart7: serial@d4017600 {
> > +                     compatible = "spacemit,k3-uart", "intel,xscale-uart";
> > +                     reg = <0x0 0xd4017600 0x0 0x100>;
> > +                     reg-shift = <2>;
> > +                     reg-io-width = <4>;
> > +                     clock-frequency = <14700000>;
> > +                     interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +                     status = "disabled";
> > +             };
> > +
> > +             uart8: serial@d4017700 {
> > +                     compatible = "spacemit,k3-uart", "intel,xscale-uart";
> > +                     reg = <0x0 0xd4017700 0x0 0x100>;
> > +                     reg-shift = <2>;
> > +                     reg-io-width = <4>;
> > +                     clock-frequency = <14700000>;
> > +                     interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +                     status = "disabled";
> > +             };
> > +
> > +             uart9: serial@d4017800 {
> > +                     compatible = "spacemit,k3-uart", "intel,xscale-uart";
> > +                     reg = <0x0 0xd4017800 0x0 0x100>;
> > +                     reg-shift = <2>;
> > +                     reg-io-width = <4>;
> > +                     clock-frequency = <14700000>;
> > +                     interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +                     status = "disabled";
> > +             };
> > +
> > +             uart10: serial@d401f000 {
> > +                     compatible = "spacemit,k3-uart", "intel,xscale-uart";
> > +                     reg = <0x0 0xd401f000 0x0 0x100>;
> > +                     reg-shift = <2>;
> > +                     reg-io-width = <4>;
> > +                     clock-frequency = <14700000>;
> > +                     interrupts = <281 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +                     status = "disabled";
> > +             };
> > +
> > +             simsic: interrupt-controller@e0400000 {
> > +                     compatible = "spacemit,k3-imsics", "riscv,imsics";
> > +                     reg = <0x0 0xe0400000 0x0 0x200000>;
> > +                     #interrupt-cells = <0>;
> > +                     #msi-cells = <0>;
> > +                     interrupt-controller;
> > +                     interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>,
> > +                                           <&cpu2_intc 9>, <&cpu3_intc 9>,
> > +                                           <&cpu4_intc 9>, <&cpu5_intc 9>,
> > +                                           <&cpu6_intc 9>, <&cpu7_intc 9>;
> > +                     msi-controller;
> > +                     riscv,guest-index-bits = <6>;
> > +                     riscv,hart-index-bits = <4>;
> > +                     riscv,num-guest-ids = <511>;
> > +                     riscv,num-ids = <511>;
> > +             };
> > +
> > +             saplic: interrupt-controller@e0804000 {
> > +                     compatible = "spacemit,k3-aplic", "riscv,aplic";
> > +                     reg = <0x0 0xe0804000 0x0 0x4000>;
> > +                     #interrupt-cells = <2>;
> > +                     interrupt-controller;
> > +                     msi-parent = <&simsic>;
> > +                     riscv,num-sources = <512>;
> > +             };
> > +
> > +             clint: timer@e081c000 {
> > +                     compatible = "spacemit,k3-clint", "sifive,clint0";
> > +                     reg = <0x0 0xe081c000 0x0 0x4000>;
> > +                     interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> > +                                           <&cpu1_intc 3>, <&cpu1_intc 7>,
> > +                                           <&cpu2_intc 3>, <&cpu2_intc 7>,
> > +                                           <&cpu3_intc 3>, <&cpu3_intc 7>,
> > +                                           <&cpu4_intc 3>, <&cpu4_intc 7>,
> > +                                           <&cpu5_intc 3>, <&cpu5_intc 7>,
> > +                                           <&cpu6_intc 3>, <&cpu6_intc 7>,
> > +                                           <&cpu7_intc 3>, <&cpu7_intc 7>;
> > +             };
> > +
> > +             mimsic: interrupt-controller@f1000000 {
> > +                     compatible = "spacemit,k3-imsics", "riscv,imsics";
> > +                     reg = <0x0 0xf1000000 0x0 0x10000>;
> > +                     #interrupt-cells = <0>;
> > +                     #msi-cells = <0>;
> > +                     interrupt-controller;
> > +                     interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>,
> > +                                           <&cpu2_intc 11>, <&cpu3_intc 11>,
> > +                                           <&cpu4_intc 11>, <&cpu5_intc 11>,
> > +                                           <&cpu6_intc 11>, <&cpu7_intc 11>;
> > +                     msi-controller;
> > +                     riscv,guest-index-bits = <6>;
> > +                     riscv,hart-index-bits = <4>;
> > +                     riscv,num-guest-ids = <511>;
> > +                     riscv,num-ids = <511>;
> > +
> > +                     status = "reserved";
> > +             };
> > +
> > +             maplic: interrupt-controller@f1800000 {
> > +                     compatible = "spacemit,k3-aplic", "riscv,aplic";
> > +                     reg = <0x0 0xf1800000 0x0 0x4000>;
> > +                     #interrupt-cells = <2>;
> > +                     interrupt-controller;
> > +                     msi-parent = <&mimsic>;
> > +                     riscv,children = <&saplic>;
> > +                     riscv,delegation = <&saplic 1 512>;
> > +                     riscv,num-sources = <512>;
> > +
> > +                     status = "reserved";
> > +             };
> > +     };
> > +};
> >
>