[PATCH 0/4] Add AST2700 INTC0/INTC1 support

[Ryan Chen <ryan_chen@aspeedtech.com>]

This series replaces the existing AST2700 interrupt controller binding
and driver. The original implementation was focused on a narrow,
PSP-centric view and could not fully describe the complexity of the
AST2700 interrupt fabric:

* It was focused primarily on the perspective of the Primary Service
  Processor (PSP).
* It could not handle interrupt route configuration.
* It could not handle interrupt register protection.

By contrast, the new bindings and drivers describe the interrupt
controllers at the block-function level and provide a unified binding
design that can be used from the perspective of any of the four
integrated processors (the Primary, Secondary and Tertiary Service
Processors, and the Boot MCU):

* Can handle interrupt register protection.
* Can handle interrupt route configuration.
* Has a unified binding design that applies to the system perspective
  of any integrated processors ({P,S,T}SP, BootMCU).
* Provides enough information for any of the {P,S,T}SP or BootMCU to
  route interrupts intended for any of the other processors' interrupt
  controllers.

There are no known upstream users of the existing binding. This series
removes it along with the associated driver after introducing the new
binding and driver at the start of this series.

The AST2700 interrupt architecture is built around two controller
designs. INTC0 routes interrupt outputs to upstream interrupt
controllers (e.g. the ARM GIC used by the PSP, as well as interrupt
controllers associated with other cores such as the SSP and TSP).
INTC1 is a banked secondary controller whose interrupt outputs feed
into INTC0 via INTM lines. Connections between the two interrupt
controllers are described in the devicetree using the
aspeed,interrupt-ranges property.

The INTC0 driver creates a hierarchical irqdomain under the selected
upstream interrupt controller. The INTC1 driver implements the INTM-fed
banked controller and exposes a linear interrupt namespace to its
parent.

The design intent of the binding is that, by default, the interrupt for
a given peripheral is routed to the processor consuming that
peripheral. To support this, the devicetree provided to the operating
environment for each processor should set its own processor-local
interrupt controller (e.g. the GIC for the Cortex-A35 PSP) as the
interrupt-parent of INTC0.

Information derived from interrupt-parent at each interrupt controller
is incorporated into the route resolution algorithm implemented in the
INTC0 driver.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
Ryan Chen (4):
      dt-bindings: interrupt-controller: aspeed: Add ASPEED AST2700 INTC0/INTC1
      irqchip/ast2700-intcx: Add AST2700 INTC0/INTC1 support
      irqchip/aspeed: Remove legacy AST2700 interrupt controller driver
      dt-bindings: interrupt-controller: aspeed: Remove legacy AST2700 interrupt binding

 .../interrupt-controller/aspeed,ast2700-intc.yaml  |  90 ---
 .../aspeed,ast2700-interrupt.yaml                  | 207 ++++++
 drivers/irqchip/Kconfig                            |  11 +
 drivers/irqchip/Makefile                           |   2 +-
 drivers/irqchip/irq-aspeed-intc.c                  | 139 ----
 drivers/irqchip/irq-ast2700-intc0-test.c           | 474 +++++++++++++
 drivers/irqchip/irq-ast2700-intc0.c                | 770 +++++++++++++++++++++
 drivers/irqchip/irq-ast2700-intc1.c                | 345 +++++++++
 drivers/irqchip/irq-ast2700.c                      | 105 +++
 drivers/irqchip/irq-ast2700.h                      |  37 +
 10 files changed, 1950 insertions(+), 230 deletions(-)
---
base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8
change-id: 20260205-irqchip-7eaef3674de9

Best regards,
-- 
Ryan Chen <ryan_chen@aspeedtech.com>