[PATCH] soc: qcom: ubwc: disable bank swizzling for Glymur platform

[PATCH] soc: qcom: ubwc: disable bank swizzling for Glymur platform

[Dmitry Baryshkov]

Due to the way the DDR controller is organized on Glymur, hardware
engineers strongly recommended disabling UBWC bank swizzling on Glymur.
Follow that recommendation.

Fixes: 9b21c3bd2480 ("soc: qcom: ubwc: Add configuration Glymur platform")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/soc/qcom/ubwc_config.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
index 1c25aaf55e52..31e0d55c6d9e 100644
--- a/drivers/soc/qcom/ubwc_config.c
+++ b/drivers/soc/qcom/ubwc_config.c
@@ -231,8 +231,7 @@ static const struct qcom_ubwc_cfg_data x1e80100_data = {
 static const struct qcom_ubwc_cfg_data glymur_data = {
 	.ubwc_enc_version = UBWC_5_0,
 	.ubwc_dec_version = UBWC_5_0,
-	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
-			UBWC_SWIZZLE_ENABLE_LVL3,
+	.ubwc_swizzle = 0;
 	.ubwc_bank_spread = true,
 	/* TODO: highest_bank_bit = 15 for LP_DDR4 */
 	.highest_bank_bit = 16,

---
base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
change-id: 20260228-fix-glymur-ubwc-f673d5ca0581

Best regards,
-- 
With best wishes
Dmitry

Re: [PATCH] soc: qcom: ubwc: disable bank swizzling for Glymur platform

[kernel test robot]

Hi Dmitry,

kernel test robot noticed the following build errors:

[auto build test ERROR on 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f]

url:    https://github.com/intel-lab-lkp/linux/commits/Dmitry-Baryshkov/soc-qcom-ubwc-disable-bank-swizzling-for-Glymur-platform/20260301-040744
base:   6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
patch link:    https://lore.kernel.org/r/20260228-fix-glymur-ubwc-v1-1-d80e3fe0dcc7%40oss.qualcomm.com
patch subject: [PATCH] soc: qcom: ubwc: disable bank swizzling for Glymur platform
config: um-allyesconfig (https://download.01.org/0day-ci/archive/20260301/202603010855.ObqylIRA-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260301/202603010855.ObqylIRA-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603010855.ObqylIRA-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/soc/qcom/ubwc_config.c:234:26: error: expected '}' before ';' token
     234 |         .ubwc_swizzle = 0;
         |                          ^
   drivers/soc/qcom/ubwc_config.c:231:54: note: to match this '{'
     231 | static const struct qcom_ubwc_cfg_data glymur_data = {
         |                                                      ^


vim +234 drivers/soc/qcom/ubwc_config.c

   230	
   231	static const struct qcom_ubwc_cfg_data glymur_data = {
   232		.ubwc_enc_version = UBWC_5_0,
   233		.ubwc_dec_version = UBWC_5_0,
 > 234		.ubwc_swizzle = 0;
   235		.ubwc_bank_spread = true,
   236		/* TODO: highest_bank_bit = 15 for LP_DDR4 */
   237		.highest_bank_bit = 16,
   238		.macrotile_mode = true,
   239	};
   240	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH] soc: qcom: ubwc: disable bank swizzling for Glymur platform

[kernel test robot]

Hi Dmitry,

kernel test robot noticed the following build errors:

[auto build test ERROR on 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f]

url:    https://github.com/intel-lab-lkp/linux/commits/Dmitry-Baryshkov/soc-qcom-ubwc-disable-bank-swizzling-for-Glymur-platform/20260301-040744
base:   6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
patch link:    https://lore.kernel.org/r/20260228-fix-glymur-ubwc-v1-1-d80e3fe0dcc7%40oss.qualcomm.com
patch subject: [PATCH] soc: qcom: ubwc: disable bank swizzling for Glymur platform
config: riscv-allyesconfig (https://download.01.org/0day-ci/archive/20260301/202603012105.z3eOjLcb-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260301/202603012105.z3eOjLcb-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603012105.z3eOjLcb-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/soc/qcom/ubwc_config.c:234:19: error: expected '}'
           .ubwc_swizzle = 0;
                            ^
   drivers/soc/qcom/ubwc_config.c:231:54: note: to match this '{'
   static const struct qcom_ubwc_cfg_data glymur_data = {
                                                        ^
>> drivers/soc/qcom/ubwc_config.c:235:2: error: expected identifier or '('
           .ubwc_bank_spread = true,
           ^
>> drivers/soc/qcom/ubwc_config.c:239:1: error: extraneous closing brace ('}')
   };
   ^
   3 errors generated.


vim +234 drivers/soc/qcom/ubwc_config.c

   230	
   231	static const struct qcom_ubwc_cfg_data glymur_data = {
   232		.ubwc_enc_version = UBWC_5_0,
   233		.ubwc_dec_version = UBWC_5_0,
 > 234		.ubwc_swizzle = 0;
 > 235		.ubwc_bank_spread = true,
   236		/* TODO: highest_bank_bit = 15 for LP_DDR4 */
   237		.highest_bank_bit = 16,
   238		.macrotile_mode = true,
 > 239	};
   240	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH] soc: qcom: ubwc: disable bank swizzling for Glymur platform

[Akhil P Oommen]

On 3/1/2026 12:03 AM, Dmitry Baryshkov wrote:
> Due to the way the DDR controller is organized on Glymur, hardware
> engineers strongly recommended disabling UBWC bank swizzling on Glymur.
> Follow that recommendation.
> 
> Fixes: 9b21c3bd2480 ("soc: qcom: ubwc: Add configuration Glymur platform")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
>  drivers/soc/qcom/ubwc_config.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
> index 1c25aaf55e52..31e0d55c6d9e 100644
> --- a/drivers/soc/qcom/ubwc_config.c
> +++ b/drivers/soc/qcom/ubwc_config.c
> @@ -231,8 +231,7 @@ static const struct qcom_ubwc_cfg_data x1e80100_data = {
>  static const struct qcom_ubwc_cfg_data glymur_data = {
>  	.ubwc_enc_version = UBWC_5_0,
>  	.ubwc_dec_version = UBWC_5_0,
> -	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
> -			UBWC_SWIZZLE_ENABLE_LVL3,
> +	.ubwc_swizzle = 0;
>  	.ubwc_bank_spread = true,
>  	/* TODO: highest_bank_bit = 15 for LP_DDR4 */
>  	.highest_bank_bit = 16,

Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>

We need a fix on the gpu side to properly handle this case. I will post
a patch.

-Akhil.

> 
> ---
> base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
> change-id: 20260228-fix-glymur-ubwc-f673d5ca0581
> 
> Best regards,

Re: [PATCH] soc: qcom: ubwc: disable bank swizzling for Glymur platform

[Dmitry Baryshkov]

On Mon, Mar 02, 2026 at 11:42:32PM +0530, Akhil P Oommen wrote:
> On 3/1/2026 12:03 AM, Dmitry Baryshkov wrote:
> > Due to the way the DDR controller is organized on Glymur, hardware
> > engineers strongly recommended disabling UBWC bank swizzling on Glymur.
> > Follow that recommendation.
> > 
> > Fixes: 9b21c3bd2480 ("soc: qcom: ubwc: Add configuration Glymur platform")
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > ---
> >  drivers/soc/qcom/ubwc_config.c | 3 +--
> >  1 file changed, 1 insertion(+), 2 deletions(-)
> > 
> > diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
> > index 1c25aaf55e52..31e0d55c6d9e 100644
> > --- a/drivers/soc/qcom/ubwc_config.c
> > +++ b/drivers/soc/qcom/ubwc_config.c
> > @@ -231,8 +231,7 @@ static const struct qcom_ubwc_cfg_data x1e80100_data = {
> >  static const struct qcom_ubwc_cfg_data glymur_data = {
> >  	.ubwc_enc_version = UBWC_5_0,
> >  	.ubwc_dec_version = UBWC_5_0,
> > -	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
> > -			UBWC_SWIZZLE_ENABLE_LVL3,
> > +	.ubwc_swizzle = 0;
> >  	.ubwc_bank_spread = true,
> >  	/* TODO: highest_bank_bit = 15 for LP_DDR4 */
> >  	.highest_bank_bit = 16,
> 
> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> 
> We need a fix on the gpu side to properly handle this case. I will post
> a patch.

Ack.


-- 
With best wishes
Dmitry