* [PATCH 0/2] cpufreq: spacemit: Add cpufreq support for K1 SoC
@ 2026-03-08 5:17 Shuwei Wu
2026-03-08 5:17 ` [PATCH 1/2] cpufreq: dt-platdev: Add SpacemiT K1 SoC to the allowlist Shuwei Wu
2026-03-08 5:17 ` [PATCH 2/2] riscv: dts: spacemit: Add cpu scaling for K1 SoC Shuwei Wu
0 siblings, 2 replies; 5+ messages in thread
From: Shuwei Wu @ 2026-03-08 5:17 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Yixun Lan, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti
Cc: linux-pm, linux-kernel, linux-riscv, spacemit, devicetree, Shuwei Wu
This series enables dynamic voltage and frequency scaling (DVFS) for
the SpacemiT K1 SoC using the generic cpufreq-dt driver.
Tested on OrangePi-RV2, the execution time scales as expected
across different CPU frequencies:
~ # echo userspace > /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
~ # echo 1600000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed
~ # time awk 'BEGIN{for(i=0;i<1000000;i++){}}'
real 0m 1.07s
user 0m 1.07s
sys 0m 0.00s
~ # echo 1228800 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed
~ # time awk 'BEGIN{for(i=0;i<1000000;i++){}}'
real 0m 1.40s
user 0m 1.40s
sys 0m 0.00s
~ # echo 1000000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed
~ # time awk 'BEGIN{for(i=0;i<1000000;i++){}}'
real 0m 1.72s
user 0m 1.72s
sys 0m 0.00s
~ # echo 819000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed
~ # time awk 'BEGIN{for(i=0;i<1000000;i++){}}'
real 0m 2.10s
user 0m 2.10s
sys 0m 0.00s
~ # echo 614400 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed
~ # time awk 'BEGIN{for(i=0;i<1000000;i++){}}'
real 0m 2.80s
user 0m 2.80s
sys 0m 0.00s
Signed-off-by: Shuwei Wu <shuwei.wu@mailbox.org>
---
Shuwei Wu (2):
cpufreq: dt-platdev: Add SpacemiT K1 SoC to the allowlist
riscv: dts: spacemit: Add cpu scaling for K1 SoC
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 34 +++++++++-
arch/riscv/boot/dts/spacemit/k1.dtsi | 86 +++++++++++++++++++++++++
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
3 files changed, 120 insertions(+), 1 deletion(-)
---
base-commit: 5164e95565d3fd508ca8a95351323f5716dfb695
change-id: 20260307-shadow-deps-3582a78aa756
prerequisite-patch-id: 154bd4f720ce5065d58b988de8f273207b44572e
prerequisite-message-id: <20260206-spacemit-p1-v4-0-8f695d93811e@riscstar.com>
prerequisite-patch-id: 5da3e75b18291a5540d4f66d7a0600fb8975ef62
prerequisite-patch-id: bcf41917414ecef8cf743095d130f6004c32f6a5
prerequisite-patch-id: cfe3800f8c791ec4c63e070af9628e88e0fc31b9
prerequisite-message-id: <20260305-k1-clk-fix-v1-1-abca85d6e266@mailbox.org>
prerequisite-patch-id: 7c7fb9f87dba019ece4c97c45750349a7cd28f3a
Best regards,
--
Shuwei Wu <shuwei.wu@mailbox.org>
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 1/2] cpufreq: dt-platdev: Add SpacemiT K1 SoC to the allowlist 2026-03-08 5:17 [PATCH 0/2] cpufreq: spacemit: Add cpufreq support for K1 SoC Shuwei Wu @ 2026-03-08 5:17 ` Shuwei Wu 2026-03-08 5:17 ` [PATCH 2/2] riscv: dts: spacemit: Add cpu scaling for K1 SoC Shuwei Wu 1 sibling, 0 replies; 5+ messages in thread From: Shuwei Wu @ 2026-03-08 5:17 UTC (permalink / raw) To: Rafael J. Wysocki, Viresh Kumar, Yixun Lan, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti Cc: linux-pm, linux-kernel, linux-riscv, spacemit, devicetree, Shuwei Wu The SpacemiT K1 SoC uses standard device tree based CPU frequency scaling. Add it to the allowlist to instantiate the cpufreq-dt driver. Signed-off-by: Shuwei Wu <shuwei.wu@mailbox.org> --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index a1d11ecd1ac8..d22198d33b7d 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -81,6 +81,7 @@ static const struct of_device_id allowlist[] __initconst = { { .have_governor_per_policy = true, }, }, + { .compatible = "spacemit,k1", }, { .compatible = "st-ericsson,u8500", }, { .compatible = "st-ericsson,u8540", }, { .compatible = "st-ericsson,u9500", }, -- 2.52.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] riscv: dts: spacemit: Add cpu scaling for K1 SoC 2026-03-08 5:17 [PATCH 0/2] cpufreq: spacemit: Add cpufreq support for K1 SoC Shuwei Wu 2026-03-08 5:17 ` [PATCH 1/2] cpufreq: dt-platdev: Add SpacemiT K1 SoC to the allowlist Shuwei Wu @ 2026-03-08 5:17 ` Shuwei Wu 2026-03-08 17:59 ` Samuel Holland 1 sibling, 1 reply; 5+ messages in thread From: Shuwei Wu @ 2026-03-08 5:17 UTC (permalink / raw) To: Rafael J. Wysocki, Viresh Kumar, Yixun Lan, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti Cc: linux-pm, linux-kernel, linux-riscv, spacemit, devicetree, Shuwei Wu Add Operating Performance Points (OPP) tables and CPU clock properties for the two clusters in the SpacemiT K1 SoC. Also assign the CPU power supply (cpu-supply) for the Banana Pi BPI-F3 board to fully enable CPU DVFS. Signed-off-by: Shuwei Wu <shuwei.wu@mailbox.org> --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 34 +++++++++- arch/riscv/boot/dts/spacemit/k1.dtsi | 86 +++++++++++++++++++++++++ 2 files changed, 119 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 444c3b1e6f44..b87bf9d51cb1 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -86,6 +86,38 @@ &combo_phy { status = "okay"; }; +&cpu_0 { + cpu-supply = <&buck1_3v45>; +}; + +&cpu_1 { + cpu-supply = <&buck1_3v45>; +}; + +&cpu_2 { + cpu-supply = <&buck1_3v45>; +}; + +&cpu_3 { + cpu-supply = <&buck1_3v45>; +}; + +&cpu_4 { + cpu-supply = <&buck1_3v45>; +}; + +&cpu_5 { + cpu-supply = <&buck1_3v45>; +}; + +&cpu_6 { + cpu-supply = <&buck1_3v45>; +}; + +&cpu_7 { + cpu-supply = <&buck1_3v45>; +}; + &emmc { bus-width = <8>; mmc-hs400-1_8v; @@ -201,7 +233,7 @@ pmic@41 { dldoin2-supply = <&buck5>; regulators { - buck1 { + buck1_3v45: buck1 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3450000>; regulator-ramp-delay = <5000>; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 529ec68e9c23..5c7bb5d85fc0 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -54,6 +54,8 @@ cpu_0: cpu@0 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <0>; + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; + operating-points-v2 = <&cluster0_opp_table>; riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", @@ -84,6 +86,8 @@ cpu_1: cpu@1 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <1>; + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; + operating-points-v2 = <&cluster0_opp_table>; riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", @@ -114,6 +118,8 @@ cpu_2: cpu@2 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <2>; + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; + operating-points-v2 = <&cluster0_opp_table>; riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", @@ -144,6 +150,8 @@ cpu_3: cpu@3 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <3>; + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; + operating-points-v2 = <&cluster0_opp_table>; riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", @@ -174,6 +182,8 @@ cpu_4: cpu@4 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <4>; + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; + operating-points-v2 = <&cluster1_opp_table>; riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", @@ -204,6 +214,8 @@ cpu_5: cpu@5 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <5>; + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; + operating-points-v2 = <&cluster1_opp_table>; riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", @@ -234,6 +246,8 @@ cpu_6: cpu@6 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <6>; + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; + operating-points-v2 = <&cluster1_opp_table>; riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", @@ -264,6 +278,8 @@ cpu_7: cpu@7 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <7>; + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; + operating-points-v2 = <&cluster1_opp_table>; riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", @@ -339,6 +355,76 @@ osc_32k: clock-32k { }; }; + cluster0_opp_table: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + + opp-819000000 { + opp-hz = /bits/ 64 <819000000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + + opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <1050000>; + clock-latency-ns = <200000>; + }; + }; + + cluster1_opp_table: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + + opp-819000000 { + opp-hz = /bits/ 64 <819000000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + + opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <1050000>; + clock-latency-ns = <200000>; + }; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; -- 2.52.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] riscv: dts: spacemit: Add cpu scaling for K1 SoC 2026-03-08 5:17 ` [PATCH 2/2] riscv: dts: spacemit: Add cpu scaling for K1 SoC Shuwei Wu @ 2026-03-08 17:59 ` Samuel Holland 2026-03-09 2:45 ` Shuwei Wu 0 siblings, 1 reply; 5+ messages in thread From: Samuel Holland @ 2026-03-08 17:59 UTC (permalink / raw) To: Shuwei Wu Cc: linux-pm, linux-kernel, linux-riscv, spacemit, devicetree, Rafael J. Wysocki, Viresh Kumar, Yixun Lan, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti Hi Shuwei, On 2026-03-07 11:17 PM, Shuwei Wu wrote: > Add Operating Performance Points (OPP) tables and CPU clock properties > for the two clusters in the SpacemiT K1 SoC. > > Also assign the CPU power supply (cpu-supply) for the Banana Pi BPI-F3 > board to fully enable CPU DVFS. > > Signed-off-by: Shuwei Wu <shuwei.wu@mailbox.org> > --- > arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 34 +++++++++- > arch/riscv/boot/dts/spacemit/k1.dtsi | 86 +++++++++++++++++++++++++ > 2 files changed, 119 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts > index 444c3b1e6f44..b87bf9d51cb1 100644 > --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts > +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts > @@ -86,6 +86,38 @@ &combo_phy { > status = "okay"; > }; > > +&cpu_0 { > + cpu-supply = <&buck1_3v45>; > +}; > + > +&cpu_1 { > + cpu-supply = <&buck1_3v45>; > +}; > + > +&cpu_2 { > + cpu-supply = <&buck1_3v45>; > +}; > + > +&cpu_3 { > + cpu-supply = <&buck1_3v45>; > +}; > + > +&cpu_4 { > + cpu-supply = <&buck1_3v45>; > +}; > + > +&cpu_5 { > + cpu-supply = <&buck1_3v45>; > +}; > + > +&cpu_6 { > + cpu-supply = <&buck1_3v45>; > +}; > + > +&cpu_7 { > + cpu-supply = <&buck1_3v45>; > +}; > + > &emmc { > bus-width = <8>; > mmc-hs400-1_8v; > @@ -201,7 +233,7 @@ pmic@41 { > dldoin2-supply = <&buck5>; > > regulators { > - buck1 { > + buck1_3v45: buck1 { > regulator-min-microvolt = <500000>; > regulator-max-microvolt = <3450000>; > regulator-ramp-delay = <5000>; > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi > index 529ec68e9c23..5c7bb5d85fc0 100644 > --- a/arch/riscv/boot/dts/spacemit/k1.dtsi > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi > @@ -54,6 +54,8 @@ cpu_0: cpu@0 { > compatible = "spacemit,x60", "riscv"; > device_type = "cpu"; > reg = <0>; > + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; > + operating-points-v2 = <&cluster0_opp_table>; > riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", > @@ -84,6 +86,8 @@ cpu_1: cpu@1 { > compatible = "spacemit,x60", "riscv"; > device_type = "cpu"; > reg = <1>; > + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; > + operating-points-v2 = <&cluster0_opp_table>; > riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", > @@ -114,6 +118,8 @@ cpu_2: cpu@2 { > compatible = "spacemit,x60", "riscv"; > device_type = "cpu"; > reg = <2>; > + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; > + operating-points-v2 = <&cluster0_opp_table>; > riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", > @@ -144,6 +150,8 @@ cpu_3: cpu@3 { > compatible = "spacemit,x60", "riscv"; > device_type = "cpu"; > reg = <3>; > + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; > + operating-points-v2 = <&cluster0_opp_table>; > riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", > @@ -174,6 +182,8 @@ cpu_4: cpu@4 { > compatible = "spacemit,x60", "riscv"; > device_type = "cpu"; > reg = <4>; > + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; > + operating-points-v2 = <&cluster1_opp_table>; > riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", > @@ -204,6 +214,8 @@ cpu_5: cpu@5 { > compatible = "spacemit,x60", "riscv"; > device_type = "cpu"; > reg = <5>; > + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; > + operating-points-v2 = <&cluster1_opp_table>; > riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", > @@ -234,6 +246,8 @@ cpu_6: cpu@6 { > compatible = "spacemit,x60", "riscv"; > device_type = "cpu"; > reg = <6>; > + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; > + operating-points-v2 = <&cluster1_opp_table>; > riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", > @@ -264,6 +278,8 @@ cpu_7: cpu@7 { > compatible = "spacemit,x60", "riscv"; > device_type = "cpu"; > reg = <7>; > + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; > + operating-points-v2 = <&cluster1_opp_table>; > riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", > @@ -339,6 +355,76 @@ osc_32k: clock-32k { > }; > }; > > + cluster0_opp_table: opp-table-cluster0 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-614400000 { > + opp-hz = /bits/ 64 <614400000>; > + opp-microvolt = <950000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-819000000 { > + opp-hz = /bits/ 64 <819000000>; > + opp-microvolt = <950000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1000000000 { > + opp-hz = /bits/ 64 <1000000000>; > + opp-microvolt = <950000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1228800000 { > + opp-hz = /bits/ 64 <1228800000>; > + opp-microvolt = <950000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1600000000 { > + opp-hz = /bits/ 64 <1600000000>; > + opp-microvolt = <1050000>; > + clock-latency-ns = <200000>; > + }; > + }; > + > + cluster1_opp_table: opp-table-cluster1 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-614400000 { > + opp-hz = /bits/ 64 <614400000>; > + opp-microvolt = <950000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-819000000 { > + opp-hz = /bits/ 64 <819000000>; > + opp-microvolt = <950000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1000000000 { > + opp-hz = /bits/ 64 <1000000000>; > + opp-microvolt = <950000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1228800000 { > + opp-hz = /bits/ 64 <1228800000>; > + opp-microvolt = <950000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1600000000 { > + opp-hz = /bits/ 64 <1600000000>; > + opp-microvolt = <1050000>; > + clock-latency-ns = <200000>; What is the initial voltage set by firmware before Linux boots? If it is 1.05V, this is fine, but if the default is 950mV, then you cannot enable the OPP table in the SoC .dtsi file. Boards other than the BananaPi F3 are missing the cpu-supply property, so they won't raise the CPU voltage before switching to the higher frequency. The usual solution is to put the OPP table (or at least the OPPs that require a higher voltage) in a separate .dtsi file, and only include that file from boards that provide the cpu-supply. Regards, Samuel ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] riscv: dts: spacemit: Add cpu scaling for K1 SoC 2026-03-08 17:59 ` Samuel Holland @ 2026-03-09 2:45 ` Shuwei Wu 0 siblings, 0 replies; 5+ messages in thread From: Shuwei Wu @ 2026-03-09 2:45 UTC (permalink / raw) To: Samuel Holland Cc: linux-pm, linux-kernel, linux-riscv, spacemit, devicetree, Rafael J. Wysocki, Viresh Kumar, Yixun Lan, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti Hi Samuel, On Mon Mar 9, 2026 at 1:59 AM CST, Samuel Holland wrote: > Hi Shuwei, > > On 2026-03-07 11:17 PM, Shuwei Wu wrote: >> Add Operating Performance Points (OPP) tables and CPU clock properties >> for the two clusters in the SpacemiT K1 SoC. >> >> Also assign the CPU power supply (cpu-supply) for the Banana Pi BPI-F3 >> board to fully enable CPU DVFS. >> >> Signed-off-by: Shuwei Wu <shuwei.wu@mailbox.org> >> --- >> arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 34 +++++++++- >> arch/riscv/boot/dts/spacemit/k1.dtsi | 86 +++++++++++++++++++++++++ >> 2 files changed, 119 insertions(+), 1 deletion(-) >> >> diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts >> index 444c3b1e6f44..b87bf9d51cb1 100644 >> --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts >> +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts >> @@ -86,6 +86,38 @@ &combo_phy { >> status = "okay"; >> }; >> >> +&cpu_0 { >> + cpu-supply = <&buck1_3v45>; >> +}; >> + >> +&cpu_1 { >> + cpu-supply = <&buck1_3v45>; >> +}; >> + >> +&cpu_2 { >> + cpu-supply = <&buck1_3v45>; >> +}; >> + >> +&cpu_3 { >> + cpu-supply = <&buck1_3v45>; >> +}; >> + >> +&cpu_4 { >> + cpu-supply = <&buck1_3v45>; >> +}; >> + >> +&cpu_5 { >> + cpu-supply = <&buck1_3v45>; >> +}; >> + >> +&cpu_6 { >> + cpu-supply = <&buck1_3v45>; >> +}; >> + >> +&cpu_7 { >> + cpu-supply = <&buck1_3v45>; >> +}; >> + >> &emmc { >> bus-width = <8>; >> mmc-hs400-1_8v; >> @@ -201,7 +233,7 @@ pmic@41 { >> dldoin2-supply = <&buck5>; >> >> regulators { >> - buck1 { >> + buck1_3v45: buck1 { >> regulator-min-microvolt = <500000>; >> regulator-max-microvolt = <3450000>; >> regulator-ramp-delay = <5000>; >> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi >> index 529ec68e9c23..5c7bb5d85fc0 100644 >> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi >> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi >> @@ -54,6 +54,8 @@ cpu_0: cpu@0 { >> compatible = "spacemit,x60", "riscv"; >> device_type = "cpu"; >> reg = <0>; >> + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; >> + operating-points-v2 = <&cluster0_opp_table>; >> riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; >> riscv,isa-base = "rv64i"; >> riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", >> @@ -84,6 +86,8 @@ cpu_1: cpu@1 { >> compatible = "spacemit,x60", "riscv"; >> device_type = "cpu"; >> reg = <1>; >> + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; >> + operating-points-v2 = <&cluster0_opp_table>; >> riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; >> riscv,isa-base = "rv64i"; >> riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", >> @@ -114,6 +118,8 @@ cpu_2: cpu@2 { >> compatible = "spacemit,x60", "riscv"; >> device_type = "cpu"; >> reg = <2>; >> + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; >> + operating-points-v2 = <&cluster0_opp_table>; >> riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; >> riscv,isa-base = "rv64i"; >> riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", >> @@ -144,6 +150,8 @@ cpu_3: cpu@3 { >> compatible = "spacemit,x60", "riscv"; >> device_type = "cpu"; >> reg = <3>; >> + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; >> + operating-points-v2 = <&cluster0_opp_table>; >> riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; >> riscv,isa-base = "rv64i"; >> riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", >> @@ -174,6 +182,8 @@ cpu_4: cpu@4 { >> compatible = "spacemit,x60", "riscv"; >> device_type = "cpu"; >> reg = <4>; >> + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; >> + operating-points-v2 = <&cluster1_opp_table>; >> riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; >> riscv,isa-base = "rv64i"; >> riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", >> @@ -204,6 +214,8 @@ cpu_5: cpu@5 { >> compatible = "spacemit,x60", "riscv"; >> device_type = "cpu"; >> reg = <5>; >> + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; >> + operating-points-v2 = <&cluster1_opp_table>; >> riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; >> riscv,isa-base = "rv64i"; >> riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", >> @@ -234,6 +246,8 @@ cpu_6: cpu@6 { >> compatible = "spacemit,x60", "riscv"; >> device_type = "cpu"; >> reg = <6>; >> + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; >> + operating-points-v2 = <&cluster1_opp_table>; >> riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; >> riscv,isa-base = "rv64i"; >> riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", >> @@ -264,6 +278,8 @@ cpu_7: cpu@7 { >> compatible = "spacemit,x60", "riscv"; >> device_type = "cpu"; >> reg = <7>; >> + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; >> + operating-points-v2 = <&cluster1_opp_table>; >> riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; >> riscv,isa-base = "rv64i"; >> riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", >> @@ -339,6 +355,76 @@ osc_32k: clock-32k { >> }; >> }; >> >> + cluster0_opp_table: opp-table-cluster0 { >> + compatible = "operating-points-v2"; >> + opp-shared; >> + >> + opp-614400000 { >> + opp-hz = /bits/ 64 <614400000>; >> + opp-microvolt = <950000>; >> + clock-latency-ns = <200000>; >> + }; >> + >> + opp-819000000 { >> + opp-hz = /bits/ 64 <819000000>; >> + opp-microvolt = <950000>; >> + clock-latency-ns = <200000>; >> + }; >> + >> + opp-1000000000 { >> + opp-hz = /bits/ 64 <1000000000>; >> + opp-microvolt = <950000>; >> + clock-latency-ns = <200000>; >> + }; >> + >> + opp-1228800000 { >> + opp-hz = /bits/ 64 <1228800000>; >> + opp-microvolt = <950000>; >> + clock-latency-ns = <200000>; >> + }; >> + >> + opp-1600000000 { >> + opp-hz = /bits/ 64 <1600000000>; >> + opp-microvolt = <1050000>; >> + clock-latency-ns = <200000>; >> + }; >> + }; >> + >> + cluster1_opp_table: opp-table-cluster1 { >> + compatible = "operating-points-v2"; >> + opp-shared; >> + >> + opp-614400000 { >> + opp-hz = /bits/ 64 <614400000>; >> + opp-microvolt = <950000>; >> + clock-latency-ns = <200000>; >> + }; >> + >> + opp-819000000 { >> + opp-hz = /bits/ 64 <819000000>; >> + opp-microvolt = <950000>; >> + clock-latency-ns = <200000>; >> + }; >> + >> + opp-1000000000 { >> + opp-hz = /bits/ 64 <1000000000>; >> + opp-microvolt = <950000>; >> + clock-latency-ns = <200000>; >> + }; >> + >> + opp-1228800000 { >> + opp-hz = /bits/ 64 <1228800000>; >> + opp-microvolt = <950000>; >> + clock-latency-ns = <200000>; >> + }; >> + >> + opp-1600000000 { >> + opp-hz = /bits/ 64 <1600000000>; >> + opp-microvolt = <1050000>; >> + clock-latency-ns = <200000>; > > What is the initial voltage set by firmware before Linux boots? If it is 1.05V, > this is fine, but if the default is 950mV, then you cannot enable the OPP table > in the SoC .dtsi file. Boards other than the BananaPi F3 are missing the > cpu-supply property, so they won't raise the CPU voltage before switching to the > higher frequency. The usual solution is to put the OPP table (or at least the > OPPs that require a higher voltage) in a separate .dtsi file, and only include > that file from boards that provide the cpu-supply. > > Regards, > Samuel Thanks for the suggestion! I confirmed the firmware sets the initial voltage to 1.05V at the default boot frequency before any scaling occurs: ~ # cat /sys/class/regulator/regulator.4/name buck1 ~ # cat /sys/class/regulator/regulator.4/microvolts 1050000 But I agree that moving the OPP tables to a separate .dtsi is a much safer and more robust approach for boards without cpu-supply. I will implement this in v2. Best regards, -- Shuwei Wu ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2026-03-09 2:46 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2026-03-08 5:17 [PATCH 0/2] cpufreq: spacemit: Add cpufreq support for K1 SoC Shuwei Wu 2026-03-08 5:17 ` [PATCH 1/2] cpufreq: dt-platdev: Add SpacemiT K1 SoC to the allowlist Shuwei Wu 2026-03-08 5:17 ` [PATCH 2/2] riscv: dts: spacemit: Add cpu scaling for K1 SoC Shuwei Wu 2026-03-08 17:59 ` Samuel Holland 2026-03-09 2:45 ` Shuwei Wu
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