[PATCH 0/2] iommu/amd: Preserve x2APIC and MSI support when amd_iommu=off

[PATCH 0/2] iommu/amd: Preserve x2APIC and MSI support when amd_iommu=off

[Adrian Huang (Lenovo)]

[Overview]
This patch series modifies the behavior of the amd_iommu=off kernel
parameter to ensure that x2APIC and MSI domain allocation remain
functional, even when DMA translation is disabled.

Currently, on AMD systems, specifying amd_iommu=off completely shuts
down the IOMMU subsystem. This causes the system to disable x2APIC and
fall back to physical flat mode, which limits the system to 255 APIC
IDs. On high-core-count systems (e.g., 448 cores), this results in a
significant number of CPUs failing to bring up. Furthermore, dynamically
added PCI devices (such as SR-IOV VFs) fail to associate with the
correct MSI domain, leading to IOMMU fault events and kernel warnings.

[Motivation]
On Intel platforms, intel_iommu=off only disables DMA translation while
keeping the necessary interrupt remapping infrastructure active to
support x2APIC and high CPU counts. This series brings the AMD IOMMU
driver in line with this behavior, ensuring stability on modern,
large-scale hardware.

[Patch Summary]
Patch 1: Adjusts the amd_iommu=off semantics to keep x2APIC enabled. It
ensures that the kernel can bring up all available CPUs on large systems
by maintaining x2APIC ops instead of falling back to physical flat mode.

Patch 2: With applying "Patch 1", patch 2 ensures the PCI bus notifier
is registered even when amd_iommu=off is used. This allows hotplugged
devices or SR-IOV VFs to be correctly assigned to the IOMMU interrupt
remapping domain, preventing INVALID_DEVICE_REQUEST faults and MSI
activation failures.

[Verification]
Testing was performed on a 448-core Lenovo ThinkSystem server. All 448
CPUs are successfully initialized; SR-IOV VFs are created and assigned
interrupts without faults.

Adrian Huang (Lenovo) (2):
  iommu/amd: Keep x2apic enabled when appending amd_iommu=off
  iommu/amd: Register PCI bus notifier when appending amd_iommu=off

 drivers/iommu/amd/amd_iommu.h |  1 +
 drivers/iommu/amd/init.c      | 81 ++++++++++++++++++++++++++++++-----
 drivers/iommu/amd/iommu.c     | 14 ++++++
 3 files changed, 86 insertions(+), 10 deletions(-)

-- 
2.47.3

[PATCH 1/2] iommu/amd: Keep x2apic enabled when appending amd_iommu=off

[Adrian Huang (Lenovo)]

When booting with amd_iommu=off, the AMD IOMMU driver currently
disables the entire IOMMU subsystem, which also results in x2APIC
being turned off. Consequently, the APIC mode falls back from
x2APIC to physical flat mode.

The dmesg log shows the transition:
  x2apic: enabled by BIOS, switching to x2apic ops
  ...
  APIC: Switched APIC routing to: cluster x2apic
  ...
  APIC: Switch to symmetric I/O mode setup
  x2apic: IRQ remapping doesn't support X2APIC mode
  x2apic disabled
  APIC: Switched APIC routing to: physical flat

Since physical flat mode supports only up to 255 APIC IDs,
systems with large CPU counts cannot fully initialize. For example,
on a 448-core system, the kernel reports repeated errors such as:
  smpboot: CPU 112 has invalid APIC ID 100. Aborting bringup
  smpboot: CPU 113 has invalid APIC ID 102. Aborting bringup
  ...
  smp: Brought up 2 nodes, 224 CPUs

Eventually, only 224 CPUs are brought up because of valid APIC IDs
and the APIC ID limitation of the physical flat mode.

In contrast, on an Intel platform with 960 cores, booting with
intel_iommu=off does not disable x2APIC:
    x2apic: enabled by BIOS, switching to x2apic ops
    ...
    APIC: Switched APIC routing to: cluster x2apic
    ...
    APIC: Switch to symmetric I/O mode setup
    DMAR: Host address width 46
    ...
    smpboot: CPU0: Intel(R) Xeon(R) Platinum 8490H (family: 0x6,
    model: 0x8f, stepping: 0x6)
    ...
    smp: Brought up 8 nodes, 960 CPUs

This confirms that x2APIC remains enabled when intel_iommu=off
is specified.

Adjust the semantics of "amd_iommu=off" so that:

  * DMA translation is disabled
  * x2apic remains enabled

This preserves x2APIC functionality and allows large CPU count
systems to operate correctly, while still disabling DMA remapping.

With this patch, the system correctly brings up all 448 cores when
booting with amd_iommu=off, as verified by the logs below:
  x2apic: enabled by BIOS, switching to x2apic ops
  ...
  APIC: Switched APIC routing to: cluster x2apic
  ...
  APIC: Switch to symmetric I/O mode setup
  ...
  smp: Brought up 2 nodes, 448 CPUs
  ...
  AMD-Vi: Interrupt remapping enabled
  AMD-Vi: X2APIC enabled
  ...

Signed-off-by: Adrian Huang (Lenovo) <adrianhuang0701@gmail.com>
---
 drivers/iommu/amd/amd_iommu.h |  1 +
 drivers/iommu/amd/init.c      | 56 ++++++++++++++++++++++++++++-------
 drivers/iommu/amd/iommu.c     | 14 +++++++++
 3 files changed, 61 insertions(+), 10 deletions(-)

diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
index 1342e764a548..82c10f55f0ea 100644
--- a/drivers/iommu/amd/amd_iommu.h
+++ b/drivers/iommu/amd/amd_iommu.h
@@ -22,6 +22,7 @@ void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
 void amd_iommu_restart_ga_log(struct amd_iommu *iommu);
 void amd_iommu_restart_ppr_log(struct amd_iommu *iommu);
 void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid);
+void amd_iommu_dev_set_pci_msi_domain(struct device *dev);
 void iommu_feature_enable(struct amd_iommu *iommu, u8 bit);
 void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu,
 				  gfp_t gfp, size_t size);
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index f3fd7f39efb4..0f577534702d 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -3396,6 +3396,41 @@ static __init void iommu_snp_enable(void)
 #endif
 }
 
+static int __init amd_iommu_devices_set_pci_msi_domain(void)
+{
+	struct pci_dev *dev = NULL;
+	struct amd_iommu *iommu;
+	int ret = 0;
+
+	/* Register IRQ handler for each iommu device. */
+	for_each_iommu(iommu) {
+		iommu->dev = pci_get_domain_bus_and_slot(iommu->pci_seg->id,
+						 PCI_BUS_NUM(iommu->devid),
+						 iommu->devid & 0xff);
+		if (!iommu->dev)
+			return -ENODEV;
+
+		ret = iommu_init_irq(iommu);
+		if (ret)
+			return ret;
+
+		iommu->dev->irq_managed = 1;
+	}
+
+	/*
+	 * In configurations where the IOMMU is disabled but x2APIC is
+	 * required for high CPU counts (> 256), the kernel must explicitly
+	 * map PCI Message Signaled Interrupt (MSI) domains to the IOMMU
+	 * hardware's interrupt domain to ensure valid interrupt routing.
+	 */
+	for_each_pci_dev(dev)
+		amd_iommu_dev_set_pci_msi_domain(&dev->dev);
+
+	print_iommu_info();
+
+	return ret;
+}
+
 /****************************************************************************
  *
  * AMD IOMMU Initialization State Machine
@@ -3416,13 +3451,8 @@ static int __init state_next(void)
 		}
 		break;
 	case IOMMU_IVRS_DETECTED:
-		if (amd_iommu_disabled) {
-			init_state = IOMMU_CMDLINE_DISABLED;
-			ret = -EINVAL;
-		} else {
-			ret = early_amd_iommu_init();
-			init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
-		}
+		ret = early_amd_iommu_init();
+		init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
 		break;
 	case IOMMU_ACPI_FINISHED:
 		early_enable_iommus();
@@ -3430,9 +3460,15 @@ static int __init state_next(void)
 		init_state = IOMMU_ENABLED;
 		break;
 	case IOMMU_ENABLED:
-		register_syscore(&amd_iommu_syscore);
-		iommu_snp_enable();
-		ret = amd_iommu_init_pci();
+		if (amd_iommu_disabled) {
+			amd_iommu_devices_set_pci_msi_domain();
+			init_state = IOMMU_CMDLINE_DISABLED;
+			ret = -EINVAL;
+		} else {
+			register_syscore(&amd_iommu_syscore);
+			iommu_snp_enable();
+			ret = amd_iommu_init_pci();
+		}
 		init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
 		break;
 	case IOMMU_PCI_INIT:
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 81c4d7733872..75b10eca9ecf 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -2439,6 +2439,20 @@ static void detach_device(struct device *dev)
 	mutex_unlock(&dev_data->mutex);
 }
 
+void amd_iommu_dev_set_pci_msi_domain(struct device *dev)
+{
+	struct amd_iommu *iommu;
+
+	if (!check_device(dev))
+		return;
+
+	iommu = rlookup_amd_iommu(dev);
+	if (!iommu)
+		return;
+
+	amd_iommu_set_pci_msi_domain(dev, iommu);
+}
+
 static struct iommu_device *amd_iommu_probe_device(struct device *dev)
 {
 	struct iommu_device *iommu_dev;
-- 
2.47.3

Re: [PATCH 1/2] iommu/amd: Keep x2apic enabled when appending amd_iommu=off

[Ankit Soni]

On Thu, Mar 19, 2026 at 02:15:06PM +0800, Adrian Huang (Lenovo) wrote:
> When booting with amd_iommu=off, the AMD IOMMU driver currently
> disables the entire IOMMU subsystem, which also results in x2APIC
> being turned off. Consequently, the APIC mode falls back from
> x2APIC to physical flat mode.
> 
> The dmesg log shows the transition:
>   x2apic: enabled by BIOS, switching to x2apic ops
>   ...
>   APIC: Switched APIC routing to: cluster x2apic
>   ...
>   APIC: Switch to symmetric I/O mode setup
>   x2apic: IRQ remapping doesn't support X2APIC mode
>   x2apic disabled
>   APIC: Switched APIC routing to: physical flat
> 
> Since physical flat mode supports only up to 255 APIC IDs,
> systems with large CPU counts cannot fully initialize. For example,
> on a 448-core system, the kernel reports repeated errors such as:
>   smpboot: CPU 112 has invalid APIC ID 100. Aborting bringup
>   smpboot: CPU 113 has invalid APIC ID 102. Aborting bringup
>   ...
>   smp: Brought up 2 nodes, 224 CPUs
> 
> Eventually, only 224 CPUs are brought up because of valid APIC IDs
> and the APIC ID limitation of the physical flat mode.
> 
> In contrast, on an Intel platform with 960 cores, booting with
> intel_iommu=off does not disable x2APIC:
>     x2apic: enabled by BIOS, switching to x2apic ops
>     ...
>     APIC: Switched APIC routing to: cluster x2apic
>     ...
>     APIC: Switch to symmetric I/O mode setup
>     DMAR: Host address width 46
>     ...
>     smpboot: CPU0: Intel(R) Xeon(R) Platinum 8490H (family: 0x6,
>     model: 0x8f, stepping: 0x6)
>     ...
>     smp: Brought up 8 nodes, 960 CPUs
> 
> This confirms that x2APIC remains enabled when intel_iommu=off
> is specified.
> 
> Adjust the semantics of "amd_iommu=off" so that:
> 
>   * DMA translation is disabled
>   * x2apic remains enabled
> 
> This preserves x2APIC functionality and allows large CPU count
> systems to operate correctly, while still disabling DMA remapping.
> 
> With this patch, the system correctly brings up all 448 cores when
> booting with amd_iommu=off, as verified by the logs below:
>   x2apic: enabled by BIOS, switching to x2apic ops
>   ...
>   APIC: Switched APIC routing to: cluster x2apic
>   ...
>   APIC: Switch to symmetric I/O mode setup
>   ...
>   smp: Brought up 2 nodes, 448 CPUs
>   ...
>   AMD-Vi: Interrupt remapping enabled
>   AMD-Vi: X2APIC enabled
>   ...
> 
> Signed-off-by: Adrian Huang (Lenovo) <adrianhuang0701@gmail.com>
> ---
>  drivers/iommu/amd/amd_iommu.h |  1 +
>  drivers/iommu/amd/init.c      | 56 ++++++++++++++++++++++++++++-------
>  drivers/iommu/amd/iommu.c     | 14 +++++++++
>  3 files changed, 61 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
> index 1342e764a548..82c10f55f0ea 100644
> --- a/drivers/iommu/amd/amd_iommu.h
> +++ b/drivers/iommu/amd/amd_iommu.h
> @@ -22,6 +22,7 @@ void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
>  void amd_iommu_restart_ga_log(struct amd_iommu *iommu);
>  void amd_iommu_restart_ppr_log(struct amd_iommu *iommu);
>  void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid);
> +void amd_iommu_dev_set_pci_msi_domain(struct device *dev);
>  void iommu_feature_enable(struct amd_iommu *iommu, u8 bit);
>  void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu,
>  				  gfp_t gfp, size_t size);
> diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
> index f3fd7f39efb4..0f577534702d 100644
> --- a/drivers/iommu/amd/init.c
> +++ b/drivers/iommu/amd/init.c
> @@ -3396,6 +3396,41 @@ static __init void iommu_snp_enable(void)
>  #endif
>  }
>  
> +static int __init amd_iommu_devices_set_pci_msi_domain(void)
> +{
> +	struct pci_dev *dev = NULL;
> +	struct amd_iommu *iommu;
> +	int ret = 0;
> +
> +	/* Register IRQ handler for each iommu device. */
> +	for_each_iommu(iommu) {
> +		iommu->dev = pci_get_domain_bus_and_slot(iommu->pci_seg->id,
> +						 PCI_BUS_NUM(iommu->devid),
> +						 iommu->devid & 0xff);
> +		if (!iommu->dev)
> +			return -ENODEV;
> +
> +		ret = iommu_init_irq(iommu);
> +		if (ret)
> +			return ret;
> +
> +		iommu->dev->irq_managed = 1;
> +	}
> +
> +	/*
> +	 * In configurations where the IOMMU is disabled but x2APIC is
> +	 * required for high CPU counts (> 256), the kernel must explicitly
> +	 * map PCI Message Signaled Interrupt (MSI) domains to the IOMMU
> +	 * hardware's interrupt domain to ensure valid interrupt routing.
> +	 */
> +	for_each_pci_dev(dev)
> +		amd_iommu_dev_set_pci_msi_domain(&dev->dev);
> +
> +	print_iommu_info();
> +
> +	return ret;
> +}
> +
>  /****************************************************************************
>   *
>   * AMD IOMMU Initialization State Machine
> @@ -3416,13 +3451,8 @@ static int __init state_next(void)
>  		}
>  		break;
>  	case IOMMU_IVRS_DETECTED:
> -		if (amd_iommu_disabled) {
> -			init_state = IOMMU_CMDLINE_DISABLED;
> -			ret = -EINVAL;
> -		} else {
> -			ret = early_amd_iommu_init();
> -			init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
> -		}
> +		ret = early_amd_iommu_init();
> +		init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
>  		break;
>  	case IOMMU_ACPI_FINISHED:
>  		early_enable_iommus();
> @@ -3430,9 +3460,15 @@ static int __init state_next(void)
>  		init_state = IOMMU_ENABLED;
>  		break;
>  	case IOMMU_ENABLED:
> -		register_syscore(&amd_iommu_syscore);
> -		iommu_snp_enable();
> -		ret = amd_iommu_init_pci();
> +		if (amd_iommu_disabled) {
> +			amd_iommu_devices_set_pci_msi_domain();
> +			init_state = IOMMU_CMDLINE_DISABLED;

There is no point in assigning IOMMU_CMDLINE_DISABLED as it will
overwrite at below.
and IMO syscore must be registered when interrupt remapping is on, in
order to support suspend/resume operations.

> +			ret = -EINVAL;

and we are relying on this error for teardown(below in this function), which
may be fragile, an explicit handling should be there for 'amd_iommu=off'.
@vasant, your openion?

> +		} else {
> +			register_syscore(&amd_iommu_syscore);
> +			iommu_snp_enable();
> +			ret = amd_iommu_init_pci();
> +		}
>  		init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
>  		break;
>  	case IOMMU_PCI_INIT:
> diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
> index 81c4d7733872..75b10eca9ecf 100644
> --- a/drivers/iommu/amd/iommu.c
> +++ b/drivers/iommu/amd/iommu.c
> @@ -2439,6 +2439,20 @@ static void detach_device(struct device *dev)
>  	mutex_unlock(&dev_data->mutex);
>  }
>  
> +void amd_iommu_dev_set_pci_msi_domain(struct device *dev)
> +{
> +	struct amd_iommu *iommu;
> +
> +	if (!check_device(dev))
> +		return;
> +
> +	iommu = rlookup_amd_iommu(dev);
> +	if (!iommu)
> +		return;
> +
> +	amd_iommu_set_pci_msi_domain(dev, iommu);
> +}
> +
>  static struct iommu_device *amd_iommu_probe_device(struct device *dev)
>  {
>  	struct iommu_device *iommu_dev;
> -- 
> 2.47.3
> 

[PATCH 2/2] iommu/amd: Register PCI bus notifier when appending amd_iommu=off

[Adrian Huang (Lenovo)]

When the amd_iommu=off kernel parameter is used, dynamically adding
PCI devices (e.g., creating SR-IOV VFs) triggers a call trace and
IOMMU fault events. For example, enabling VFs via sysfs:

  # echo 4 > /sys/class/net/eth1/device/sriov_numvfs

It results in an INVALID_DEVICE_REQUEST and a warning in
__irq_msi_compose_msg+0xa3/0xb0:

  pci 0000:41:03.0: [14e4:16c1] type 00 class 0x020000 PCIe Endpoint
  bnxt_en 0000:41:03.0: enabling device (0000 -> 0002)
  bnxt_en 0000:41:03.0 eth4: Broadcom NetXtreme-E Ethernet Virtual Function found at mem 381c7ff40000, node addr 92:42:39:64:ad:24
  ...
  WARNING: arch/x86/kernel/apic/apic.c:2313 at __irq_msi_compose_msg+0xa3/0xb0, CPU#2: NetworkManager/4268
  bnxt_en 0000:41:03.1: enabling device (0000 -> 0002)
  CPU: 2 UID: 0 PID: 4268 Comm: NetworkManager Kdump: loaded Not tainted 7.0.0-rc4+ #23 PREEMPT(lazy)
  ...
  RIP: 0010:__irq_msi_compose_msg+0xa3/0xb0
  ...
  Call Trace:
   <TASK>
   irq_chip_compose_msi_msg+0x2e/0x50
   msi_domain_activate+0x41/0x90
   __irq_domain_activate_irq+0x53/0x90
   ? mtree_load+0x26e/0x2b0
   irq_domain_activate_irq+0x29/0x40
   __setup_irq+0x322/0x790
   ? __pfx_bnxt_msix+0x10/0x10 [bnxt_en]
   request_threaded_irq+0x109/0x1c0
   bnxt_request_irq+0xee/0x270 [bnxt_en]
   ...
   AMD-Vi: Event logged [INVALID_DEVICE_REQUEST device=0000:41:03.0 pasid=0x00000 address=0xfffffffdf8220100 flags=0x0a00]

The root cause is that when IOMMU is disabled via the command line, the
PCI bus notifier is not registered. Consequently, the MSI domain for
dynamically added devices is not properly associated with the IOMMU
interrupt remapping domain. Even when the IOMMU is "off," certain
interrupt remapping configurations must still be handled for newly
enumerated devices to prevent activation failures.

Fix this by ensuring the PCI bus notifier is registered even when
amd_iommu=off is set, allowing the IOMMU interrupt remapping domain to
be correctly assigned to new PCI devices.

Signed-off-by: Adrian Huang (Lenovo) <adrianhuang0701@gmail.com>
---
 drivers/iommu/amd/init.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index 0f577534702d..5509ade0cf0d 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -3431,6 +3431,30 @@ static int __init amd_iommu_devices_set_pci_msi_domain(void)
 	return ret;
 }
 
+static int amd_iommu_pci_bus_notifier(struct notifier_block *nb,
+					unsigned long action, void *data)
+{
+	struct pci_dev *pdev = to_pci_dev(data);
+
+	/* We only care about the add event. */
+	if (action != BUS_NOTIFY_ADD_DEVICE)
+		return NOTIFY_DONE;
+
+	amd_iommu_dev_set_pci_msi_domain(&pdev->dev);
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block amd_iommu_pci_bus_nb = {
+	.notifier_call = amd_iommu_pci_bus_notifier,
+	.priority = 1,
+};
+
+static void __init amd_iommu_register_bus_notifier(void)
+{
+	bus_register_notifier(&pci_bus_type, &amd_iommu_pci_bus_nb);
+}
+
 /****************************************************************************
  *
  * AMD IOMMU Initialization State Machine
@@ -3462,6 +3486,7 @@ static int __init state_next(void)
 	case IOMMU_ENABLED:
 		if (amd_iommu_disabled) {
 			amd_iommu_devices_set_pci_msi_domain();
+			amd_iommu_register_bus_notifier();
 			init_state = IOMMU_CMDLINE_DISABLED;
 			ret = -EINVAL;
 		} else {
-- 
2.47.3