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From: Akhil P Oommen <akhilpo@oss.qualcomm.com>
To: Rob Clark <robin.clark@oss.qualcomm.com>,
	Sean Paul <sean@poorly.run>,
	Konrad Dybcio <konradybcio@kernel.org>,
	Dmitry Baryshkov <lumag@kernel.org>,
	Abhinav Kumar <abhinav.kumar@linux.dev>,
	Jessica Zhang <jesszhan0024@gmail.com>,
	Marijn Suijten <marijn.suijten@somainline.org>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Antonino Maniscalco <antomani103@gmail.com>,
	Connor Abbott <cwabbott0@gmail.com>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Maxime Ripard <mripard@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
	freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	Akhil P Oommen <akhilpo@oss.qualcomm.com>
Subject: [PATCH v2 07/17] drm/msm/a6xx: Add support for Debug HFI Q
Date: Fri, 27 Mar 2026 05:43:56 +0530	[thread overview]
Message-ID: <20260327-a8xx-gpu-batch2-v2-7-2b53c38d2101@oss.qualcomm.com> (raw)
In-Reply-To: <20260327-a8xx-gpu-batch2-v2-0-2b53c38d2101@oss.qualcomm.com>

Add the Debug HFI Queue which contains the F2H messages posted from the
GMU firmware. Having this data in coredump is useful to debug firmware
issues.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.h       |  2 +-
 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c |  2 +-
 drivers/gpu/drm/msm/adreno/a6xx_hfi.c       | 16 +++++++++++++---
 drivers/gpu/drm/msm/adreno/a6xx_hfi.h       |  2 ++
 4 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
index 0cd8ae1b4f5c..3f96b10b5f61 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
@@ -111,7 +111,7 @@ struct a6xx_gmu {
 
 	unsigned long freq;
 
-	struct a6xx_hfi_queue queues[2];
+	struct a6xx_hfi_queue queues[HFI_MAX_QUEUES];
 
 	bool initialized;
 	bool hung;
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
index 7bec4e509d2c..c0b9661131e8 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
@@ -57,7 +57,7 @@ struct a6xx_gpu_state {
 	struct msm_gpu_state_bo *gmu_hfi;
 	struct msm_gpu_state_bo *gmu_debug;
 
-	s32 hfi_queue_history[2][HFI_HISTORY_SZ];
+	s32 hfi_queue_history[HFI_MAX_QUEUES][HFI_HISTORY_SZ];
 
 	struct list_head objs;
 
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
index 4f5dbf46132b..09b6bc464b47 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
@@ -1062,8 +1062,8 @@ void a6xx_hfi_init(struct a6xx_gmu *gmu)
 	struct a6xx_gmu_bo *hfi = &gmu->hfi;
 	struct a6xx_hfi_queue_table_header *table = hfi->virt;
 	struct a6xx_hfi_queue_header *headers = hfi->virt + sizeof(*table);
+	int table_size, idx;
 	u64 offset;
-	int table_size;
 
 	/*
 	 * The table size is the size of the table header plus all of the queue
@@ -1082,12 +1082,22 @@ void a6xx_hfi_init(struct a6xx_gmu *gmu)
 	table->active_queues = ARRAY_SIZE(gmu->queues);
 
 	/* Command queue */
+	idx = 0;
 	offset = SZ_4K;
-	a6xx_hfi_queue_init(&gmu->queues[0], &headers[0], hfi->virt + offset,
+	a6xx_hfi_queue_init(&gmu->queues[idx], &headers[idx], hfi->virt + offset,
 		hfi->iova + offset, 0);
 
 	/* GMU response queue */
+	idx++;
 	offset += SZ_4K;
-	a6xx_hfi_queue_init(&gmu->queues[1], &headers[1], hfi->virt + offset,
+	a6xx_hfi_queue_init(&gmu->queues[idx], &headers[idx], hfi->virt + offset,
 		hfi->iova + offset, gmu->legacy ? 4 : 1);
+
+	/* GMU Debug queue */
+	idx++;
+	offset += SZ_4K;
+	a6xx_hfi_queue_init(&gmu->queues[idx], &headers[idx], hfi->virt + offset,
+		hfi->iova + offset, gmu->legacy ? 5 : 2);
+
+	WARN_ON(idx >= HFI_MAX_QUEUES);
 }
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h
index 6f9f74a0bc85..19f6eca2c8c9 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h
@@ -4,6 +4,8 @@
 #ifndef _A6XX_HFI_H_
 #define _A6XX_HFI_H_
 
+#define HFI_MAX_QUEUES 3
+
 struct a6xx_hfi_queue_table_header {
 	u32 version;
 	u32 size;		/* Size of the queue table in dwords */

-- 
2.51.0


  parent reply	other threads:[~2026-03-27  0:15 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-27  0:13 [PATCH v2 00/17] drm/msm: A8xx Support - Batch 2 Akhil P Oommen
2026-03-27  0:13 ` [PATCH v2 01/17] drm/msm/a6xx: Use barriers while updating HFI Q headers Akhil P Oommen
2026-03-27  0:13 ` [PATCH v2 02/17] drm/msm/a8xx: Fix the ticks used in submit traces Akhil P Oommen
2026-03-27 11:37   ` Konrad Dybcio
2026-03-30 20:58     ` Akhil P Oommen
2026-03-31  8:23       ` Konrad Dybcio
2026-03-27  0:13 ` [PATCH v2 03/17] drm/msm/a6xx: Switch to preemption safe AO counter Akhil P Oommen
2026-03-27 11:32   ` Konrad Dybcio
2026-03-30 20:51     ` Akhil P Oommen
2026-03-30 21:34       ` Rob Clark
2026-03-27  0:13 ` [PATCH v2 04/17] drm/msm/a6xx: Correct OOB usage Akhil P Oommen
2026-03-27  0:13 ` [PATCH v2 05/17] drm/msm/adreno: Implement gx_is_on() for A8x Akhil P Oommen
2026-03-27  0:13 ` [PATCH v2 06/17] drm/msm/a6xx: Fix gpu init from secure world Akhil P Oommen
2026-03-27  0:13 ` Akhil P Oommen [this message]
2026-03-27 10:34   ` [PATCH v2 07/17] drm/msm/a6xx: Add support for Debug HFI Q Konrad Dybcio
2026-03-27  0:13 ` [PATCH v2 08/17] drm/msm/adreno: Coredump on GPU/GMU init failures Akhil P Oommen
2026-03-27 11:35   ` Konrad Dybcio
2026-03-30 20:53     ` Akhil P Oommen
2026-03-30 19:51   ` Rob Clark
2026-03-31 18:05     ` Akhil P Oommen
2026-03-31 18:28       ` Rob Clark
2026-03-27  0:13 ` [PATCH v2 09/17] drm/msm/a6xx: Use packed structs for HFI Akhil P Oommen
2026-03-27  0:13 ` [PATCH v2 10/17] drm/msm/a6xx: Update HFI definitions Akhil P Oommen
2026-03-30 11:15   ` Konrad Dybcio
2026-03-30 20:27     ` Akhil P Oommen
2026-03-31  8:22       ` Konrad Dybcio
2026-03-31 17:44         ` Akhil P Oommen
2026-03-27  0:14 ` [PATCH v2 11/17] drm/msm/a8xx: Add SKU table for A840 Akhil P Oommen
2026-03-27 11:14   ` Konrad Dybcio
2026-03-30 20:35     ` Akhil P Oommen
2026-03-27  0:14 ` [PATCH v2 12/17] drm/msm/a6xx: Add soft fuse detection support Akhil P Oommen
2026-03-27 11:16   ` Konrad Dybcio
2026-03-30 20:36     ` Akhil P Oommen
2026-04-11  2:19   ` Jie Gan
2026-03-27  0:14 ` [PATCH v2 13/17] drm/msm/a6xx: Add SKU detection support for X2-85 Akhil P Oommen
2026-03-27  0:14 ` [PATCH v2 14/17] drm/msm/a8xx: Implement IFPC support for A840 Akhil P Oommen
2026-03-27 11:07   ` Konrad Dybcio
2026-03-30 20:34     ` Akhil P Oommen
2026-03-27  0:14 ` [PATCH v2 15/17] drm/msm/a8xx: Preemption " Akhil P Oommen
2026-04-11  2:22   ` Jie Gan
2026-04-11 13:56     ` Rob Clark
2026-04-11 14:45       ` David Laight
2026-03-27  0:14 ` [PATCH v2 16/17] drm/msm/a6xx: Enable Preemption on X2-85 Akhil P Oommen
2026-03-27  0:14 ` [PATCH v2 17/17] drm/msm/adreno: Expose a PARAM to check AQE support Akhil P Oommen
2026-03-27 11:19   ` Konrad Dybcio

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