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From: Akhil P Oommen <akhilpo@oss.qualcomm.com>
To: Rob Clark <robin.clark@oss.qualcomm.com>,
	Sean Paul <sean@poorly.run>,
	Konrad Dybcio <konradybcio@kernel.org>,
	Dmitry Baryshkov <lumag@kernel.org>,
	Abhinav Kumar <abhinav.kumar@linux.dev>,
	Jessica Zhang <jesszhan0024@gmail.com>,
	Marijn Suijten <marijn.suijten@somainline.org>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Antonino Maniscalco <antomani103@gmail.com>,
	Connor Abbott <cwabbott0@gmail.com>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Maxime Ripard <mripard@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
	freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	Akhil P Oommen <akhilpo@oss.qualcomm.com>,
	Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Subject: [PATCH v2 09/17] drm/msm/a6xx: Use packed structs for HFI
Date: Fri, 27 Mar 2026 05:43:58 +0530	[thread overview]
Message-ID: <20260327-a8xx-gpu-batch2-v2-9-2b53c38d2101@oss.qualcomm.com> (raw)
In-Reply-To: <20260327-a8xx-gpu-batch2-v2-0-2b53c38d2101@oss.qualcomm.com>

HFI related structs define the ABI between the KMD and the GMU firmware.
So, use packed structures to avoid unintended compiler inserted padding.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 40 +++++++++++++++++------------------
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h
index 19f6eca2c8c9..217708b03f6f 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h
@@ -13,7 +13,7 @@ struct a6xx_hfi_queue_table_header {
 	u32 qhdr_size;		/* Size of the queue headers */
 	u32 num_queues;		/* Number of total queues */
 	u32 active_queues;	/* Number of active queues */
-};
+} __packed;
 
 struct a6xx_hfi_queue_header {
 	u32 status;
@@ -28,7 +28,7 @@ struct a6xx_hfi_queue_header {
 	u32 tx_request;
 	u32 read_index;
 	u32 write_index;
-};
+} __packed;
 
 struct a6xx_hfi_queue {
 	struct a6xx_hfi_queue_header *header;
@@ -74,7 +74,7 @@ struct a6xx_hfi_msg_response {
 	u32 ret_header;
 	u32 error;
 	u32 payload[HFI_RESPONSE_PAYLOAD_SIZE];
-};
+} __packed;
 
 #define HFI_F2H_MSG_ERROR 100
 
@@ -82,7 +82,7 @@ struct a6xx_hfi_msg_error {
 	u32 header;
 	u32 code;
 	u32 payload[2];
-};
+} __packed;
 
 #define HFI_H2F_MSG_INIT 0
 
@@ -92,27 +92,27 @@ struct a6xx_hfi_msg_gmu_init_cmd {
 	u32 dbg_buffer_addr;
 	u32 dbg_buffer_size;
 	u32 boot_state;
-};
+} __packed;
 
 #define HFI_H2F_MSG_FW_VERSION 1
 
 struct a6xx_hfi_msg_fw_version {
 	u32 header;
 	u32 supported_version;
-};
+} __packed;
 
 #define HFI_H2F_MSG_PERF_TABLE 4
 
 struct perf_level {
 	u32 vote;
 	u32 freq;
-};
+} __packed;
 
 struct perf_gx_level {
 	u32 vote;
 	u32 acd;
 	u32 freq;
-};
+} __packed;
 
 struct a6xx_hfi_msg_perf_table_v1 {
 	u32 header;
@@ -121,7 +121,7 @@ struct a6xx_hfi_msg_perf_table_v1 {
 
 	struct perf_level gx_votes[16];
 	struct perf_level cx_votes[4];
-};
+} __packed;
 
 struct a6xx_hfi_msg_perf_table {
 	u32 header;
@@ -130,7 +130,7 @@ struct a6xx_hfi_msg_perf_table {
 
 	struct perf_gx_level gx_votes[16];
 	struct perf_level cx_votes[4];
-};
+} __packed;
 
 #define HFI_H2F_MSG_BW_TABLE 3
 
@@ -145,13 +145,13 @@ struct a6xx_hfi_msg_bw_table {
 	u32 cnoc_cmds_data[2][6];
 	u32 ddr_cmds_addrs[8];
 	u32 ddr_cmds_data[16][8];
-};
+} __packed;
 
 #define HFI_H2F_MSG_TEST 5
 
 struct a6xx_hfi_msg_test {
 	u32 header;
-};
+} __packed;
 
 #define HFI_H2F_MSG_ACD 7
 #define MAX_ACD_STRIDE 2
@@ -163,13 +163,13 @@ struct a6xx_hfi_acd_table {
 	u32 stride;
 	u32 num_levels;
 	u32 data[16 * MAX_ACD_STRIDE];
-};
+} __packed;
 
 #define HFI_H2F_MSG_START 10
 
 struct a6xx_hfi_msg_start {
 	u32 header;
-};
+} __packed;
 
 #define HFI_H2F_FEATURE_CTRL 11
 
@@ -178,14 +178,14 @@ struct a6xx_hfi_msg_feature_ctrl {
 	u32 feature;
 	u32 enable;
 	u32 data;
-};
+} __packed;
 
 #define HFI_H2F_MSG_CORE_FW_START 14
 
 struct a6xx_hfi_msg_core_fw_start {
 	u32 header;
 	u32 handle;
-};
+} __packed;
 
 #define HFI_H2F_MSG_TABLE 15
 
@@ -193,7 +193,7 @@ struct a6xx_hfi_table_entry {
 	u32 count;
 	u32 stride;
 	u32 data[];
-};
+} __packed;
 
 struct a6xx_hfi_table {
 	u32 header;
@@ -202,7 +202,7 @@ struct a6xx_hfi_table {
 #define HFI_TABLE_BW_VOTE 0
 #define HFI_TABLE_GPU_PERF 1
 	struct a6xx_hfi_table_entry entry[];
-};
+} __packed;
 
 #define HFI_H2F_MSG_GX_BW_PERF_VOTE 30
 
@@ -211,7 +211,7 @@ struct a6xx_hfi_gx_bw_perf_vote_cmd {
 	u32 ack_type;
 	u32 freq;
 	u32 bw;
-};
+} __packed;
 
 #define AB_VOTE_MASK		GENMASK(31, 16)
 #define MAX_AB_VOTE		(FIELD_MAX(AB_VOTE_MASK) - 1)
@@ -224,6 +224,6 @@ struct a6xx_hfi_prep_slumber_cmd {
 	u32 header;
 	u32 bw;
 	u32 freq;
-};
+} __packed;
 
 #endif

-- 
2.51.0


  parent reply	other threads:[~2026-03-27  0:15 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-27  0:13 [PATCH v2 00/17] drm/msm: A8xx Support - Batch 2 Akhil P Oommen
2026-03-27  0:13 ` [PATCH v2 01/17] drm/msm/a6xx: Use barriers while updating HFI Q headers Akhil P Oommen
2026-03-27  0:13 ` [PATCH v2 02/17] drm/msm/a8xx: Fix the ticks used in submit traces Akhil P Oommen
2026-03-27 11:37   ` Konrad Dybcio
2026-03-30 20:58     ` Akhil P Oommen
2026-03-31  8:23       ` Konrad Dybcio
2026-03-27  0:13 ` [PATCH v2 03/17] drm/msm/a6xx: Switch to preemption safe AO counter Akhil P Oommen
2026-03-27 11:32   ` Konrad Dybcio
2026-03-30 20:51     ` Akhil P Oommen
2026-03-30 21:34       ` Rob Clark
2026-03-27  0:13 ` [PATCH v2 04/17] drm/msm/a6xx: Correct OOB usage Akhil P Oommen
2026-03-27  0:13 ` [PATCH v2 05/17] drm/msm/adreno: Implement gx_is_on() for A8x Akhil P Oommen
2026-03-27  0:13 ` [PATCH v2 06/17] drm/msm/a6xx: Fix gpu init from secure world Akhil P Oommen
2026-03-27  0:13 ` [PATCH v2 07/17] drm/msm/a6xx: Add support for Debug HFI Q Akhil P Oommen
2026-03-27 10:34   ` Konrad Dybcio
2026-03-27  0:13 ` [PATCH v2 08/17] drm/msm/adreno: Coredump on GPU/GMU init failures Akhil P Oommen
2026-03-27 11:35   ` Konrad Dybcio
2026-03-30 20:53     ` Akhil P Oommen
2026-03-30 19:51   ` Rob Clark
2026-03-31 18:05     ` Akhil P Oommen
2026-03-31 18:28       ` Rob Clark
2026-03-27  0:13 ` Akhil P Oommen [this message]
2026-03-27  0:13 ` [PATCH v2 10/17] drm/msm/a6xx: Update HFI definitions Akhil P Oommen
2026-03-30 11:15   ` Konrad Dybcio
2026-03-30 20:27     ` Akhil P Oommen
2026-03-31  8:22       ` Konrad Dybcio
2026-03-31 17:44         ` Akhil P Oommen
2026-03-27  0:14 ` [PATCH v2 11/17] drm/msm/a8xx: Add SKU table for A840 Akhil P Oommen
2026-03-27 11:14   ` Konrad Dybcio
2026-03-30 20:35     ` Akhil P Oommen
2026-03-27  0:14 ` [PATCH v2 12/17] drm/msm/a6xx: Add soft fuse detection support Akhil P Oommen
2026-03-27 11:16   ` Konrad Dybcio
2026-03-30 20:36     ` Akhil P Oommen
2026-04-11  2:19   ` Jie Gan
2026-03-27  0:14 ` [PATCH v2 13/17] drm/msm/a6xx: Add SKU detection support for X2-85 Akhil P Oommen
2026-03-27  0:14 ` [PATCH v2 14/17] drm/msm/a8xx: Implement IFPC support for A840 Akhil P Oommen
2026-03-27 11:07   ` Konrad Dybcio
2026-03-30 20:34     ` Akhil P Oommen
2026-03-27  0:14 ` [PATCH v2 15/17] drm/msm/a8xx: Preemption " Akhil P Oommen
2026-04-11  2:22   ` Jie Gan
2026-04-11 13:56     ` Rob Clark
2026-04-11 14:45       ` David Laight
2026-03-27  0:14 ` [PATCH v2 16/17] drm/msm/a6xx: Enable Preemption on X2-85 Akhil P Oommen
2026-03-27  0:14 ` [PATCH v2 17/17] drm/msm/adreno: Expose a PARAM to check AQE support Akhil P Oommen
2026-03-27 11:19   ` Konrad Dybcio

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