From: Akhil P Oommen <akhilpo@oss.qualcomm.com>
To: rob.clark@oss.qualcomm.com
Cc: Sean Paul <sean@poorly.run>,
Konrad Dybcio <konradybcio@kernel.org>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jesszhan0024@gmail.com>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Antonino Maniscalco <antomani103@gmail.com>,
Connor Abbott <cwabbott0@gmail.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 08/17] drm/msm/adreno: Coredump on GPU/GMU init failures
Date: Tue, 31 Mar 2026 23:35:29 +0530 [thread overview]
Message-ID: <720bf565-342c-45b1-b797-3e27a7e9bb56@oss.qualcomm.com> (raw)
In-Reply-To: <CACSVV01RxTce4qEkt=vPb8AmPSuTLVTh5DR5gCAP2n3U3vkDqw@mail.gmail.com>
On 3/31/2026 1:21 AM, Rob Clark wrote:
> On Thu, Mar 26, 2026 at 5:15 PM Akhil P Oommen <akhilpo@oss.qualcomm.com> wrote:
>>
>> Capture coredump on GPU or GMU errors during initialization to help in
>> debugging the issues. To be consistent with the locks while calling
>> msm_gpu_crashstate_capture(), call pm_runtime_get(gpu) always with
>> msm_gpu->lock.
>>
>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>> ---
>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 1 +
>> drivers/gpu/drm/msm/adreno/adreno_device.c | 5 +++--
>> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 ++++-
>> drivers/gpu/drm/msm/msm_gpu.c | 5 +++--
>> drivers/gpu/drm/msm/msm_gpu.h | 2 ++
>> 5 files changed, 13 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>> index 1b44b9e21ad8..916c5d99c4d1 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>> @@ -1335,6 +1335,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
>>
>> disable_irq:
>> disable_irq(gmu->gmu_irq);
>> + msm_gpu_crashstate_capture(gpu, NULL, NULL, NULL, NULL);
>> a6xx_rpmh_stop(gmu);
>> disable_clk:
>> clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
>> index 4edfe80c5be7..ca5f96e16870 100644
>> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
>> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
>> @@ -105,6 +105,8 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
>> */
>> pm_runtime_enable(&pdev->dev);
>>
>> + guard(mutex)(&gpu->lock);
>
> so, I am a fan of guard(), but I realized this means we are holding
> gpu->lock across the debugfs_init() (only a5xx).. which I suspect will
> anger lockdep, although I don't have a good way to test that atm.
Shall we drop this patch for now? I will send a respin later.
-Akhil.
>
> BR,
> -R
>
>> +
>> ret = pm_runtime_get_sync(&pdev->dev);
>> if (ret < 0) {
>> pm_runtime_put_noidle(&pdev->dev);
>> @@ -112,10 +114,9 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
>> goto err_disable_rpm;
>> }
>>
>> - mutex_lock(&gpu->lock);
>> ret = msm_gpu_hw_init(gpu);
>> - mutex_unlock(&gpu->lock);
>> if (ret) {
>> + msm_gpu_crashstate_capture(gpu, NULL, NULL, NULL, NULL);
>> DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
>> goto err_put_rpm;
>> }
>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> index 785e99fb5bd5..8475802fdde2 100644
>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> @@ -391,10 +391,13 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx,
>> return 0;
>> case MSM_PARAM_TIMESTAMP:
>> if (adreno_gpu->funcs->get_timestamp) {
>> + mutex_lock(&gpu->lock);
>> pm_runtime_get_sync(&gpu->pdev->dev);
>> +
>> *value = adreno_gpu->funcs->get_timestamp(gpu);
>> - pm_runtime_put_autosuspend(&gpu->pdev->dev);
>>
>> + pm_runtime_put_autosuspend(&gpu->pdev->dev);
>> + mutex_unlock(&gpu->lock);
>> return 0;
>> }
>> return -EINVAL;
>> diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
>> index 995549d0bbbc..472db2c916f9 100644
>> --- a/drivers/gpu/drm/msm/msm_gpu.c
>> +++ b/drivers/gpu/drm/msm/msm_gpu.c
>> @@ -361,7 +361,7 @@ static void crashstate_get_vm_logs(struct msm_gpu_state *state, struct msm_gem_v
>> mutex_unlock(&vm->mmu_lock);
>> }
>>
>> -static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
>> +void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
>> struct msm_gem_submit *submit, struct msm_gpu_fault_info *fault_info,
>> char *comm, char *cmd)
>> {
>> @@ -886,7 +886,8 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
>>
>> pm_runtime_get_sync(&gpu->pdev->dev);
>>
>> - msm_gpu_hw_init(gpu);
>> + if (msm_gpu_hw_init(gpu))
>> + msm_gpu_crashstate_capture(gpu, NULL, NULL, NULL, NULL);
>>
>> submit->seqno = submit->hw_fence->seqno;
>>
>> diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
>> index 666cf499b7ec..eb5b3a7b81f9 100644
>> --- a/drivers/gpu/drm/msm/msm_gpu.h
>> +++ b/drivers/gpu/drm/msm/msm_gpu.h
>> @@ -747,6 +747,8 @@ static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)
>> }
>>
>> void msm_gpu_fault_crashstate_capture(struct msm_gpu *gpu, struct msm_gpu_fault_info *fault_info);
>> +void msm_gpu_crashstate_capture(struct msm_gpu *gpu, struct msm_gem_submit *submit,
>> + struct msm_gpu_fault_info *fault_info, char *comm, char *cmd);
>>
>> /*
>> * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can
>>
>> --
>> 2.51.0
>>
next prev parent reply other threads:[~2026-03-31 18:05 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-27 0:13 [PATCH v2 00/17] drm/msm: A8xx Support - Batch 2 Akhil P Oommen
2026-03-27 0:13 ` [PATCH v2 01/17] drm/msm/a6xx: Use barriers while updating HFI Q headers Akhil P Oommen
2026-03-27 0:13 ` [PATCH v2 02/17] drm/msm/a8xx: Fix the ticks used in submit traces Akhil P Oommen
2026-03-27 11:37 ` Konrad Dybcio
2026-03-30 20:58 ` Akhil P Oommen
2026-03-31 8:23 ` Konrad Dybcio
2026-03-27 0:13 ` [PATCH v2 03/17] drm/msm/a6xx: Switch to preemption safe AO counter Akhil P Oommen
2026-03-27 11:32 ` Konrad Dybcio
2026-03-30 20:51 ` Akhil P Oommen
2026-03-30 21:34 ` Rob Clark
2026-03-27 0:13 ` [PATCH v2 04/17] drm/msm/a6xx: Correct OOB usage Akhil P Oommen
2026-03-27 0:13 ` [PATCH v2 05/17] drm/msm/adreno: Implement gx_is_on() for A8x Akhil P Oommen
2026-03-27 0:13 ` [PATCH v2 06/17] drm/msm/a6xx: Fix gpu init from secure world Akhil P Oommen
2026-03-27 0:13 ` [PATCH v2 07/17] drm/msm/a6xx: Add support for Debug HFI Q Akhil P Oommen
2026-03-27 10:34 ` Konrad Dybcio
2026-03-27 0:13 ` [PATCH v2 08/17] drm/msm/adreno: Coredump on GPU/GMU init failures Akhil P Oommen
2026-03-27 11:35 ` Konrad Dybcio
2026-03-30 20:53 ` Akhil P Oommen
2026-03-30 19:51 ` Rob Clark
2026-03-31 18:05 ` Akhil P Oommen [this message]
2026-03-31 18:28 ` Rob Clark
2026-03-27 0:13 ` [PATCH v2 09/17] drm/msm/a6xx: Use packed structs for HFI Akhil P Oommen
2026-03-27 0:13 ` [PATCH v2 10/17] drm/msm/a6xx: Update HFI definitions Akhil P Oommen
2026-03-30 11:15 ` Konrad Dybcio
2026-03-30 20:27 ` Akhil P Oommen
2026-03-31 8:22 ` Konrad Dybcio
2026-03-31 17:44 ` Akhil P Oommen
2026-03-27 0:14 ` [PATCH v2 11/17] drm/msm/a8xx: Add SKU table for A840 Akhil P Oommen
2026-03-27 11:14 ` Konrad Dybcio
2026-03-30 20:35 ` Akhil P Oommen
2026-03-27 0:14 ` [PATCH v2 12/17] drm/msm/a6xx: Add soft fuse detection support Akhil P Oommen
2026-03-27 11:16 ` Konrad Dybcio
2026-03-30 20:36 ` Akhil P Oommen
2026-04-11 2:19 ` Jie Gan
2026-03-27 0:14 ` [PATCH v2 13/17] drm/msm/a6xx: Add SKU detection support for X2-85 Akhil P Oommen
2026-03-27 0:14 ` [PATCH v2 14/17] drm/msm/a8xx: Implement IFPC support for A840 Akhil P Oommen
2026-03-27 11:07 ` Konrad Dybcio
2026-03-30 20:34 ` Akhil P Oommen
2026-03-27 0:14 ` [PATCH v2 15/17] drm/msm/a8xx: Preemption " Akhil P Oommen
2026-04-11 2:22 ` Jie Gan
2026-04-11 13:56 ` Rob Clark
2026-04-11 14:45 ` David Laight
2026-03-27 0:14 ` [PATCH v2 16/17] drm/msm/a6xx: Enable Preemption on X2-85 Akhil P Oommen
2026-03-27 0:14 ` [PATCH v2 17/17] drm/msm/adreno: Expose a PARAM to check AQE support Akhil P Oommen
2026-03-27 11:19 ` Konrad Dybcio
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