From: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
To: Rob Clark <robin.clark@oss.qualcomm.com>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Jessica Zhang <jesszhan0024@gmail.com>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Abhinav Kumar <quic_abhinavk@quicinc.com>
Subject: [PATCH RESEND v5 04/25] drm/msm/dp: use stream_id to change offsets in dp_catalog
Date: Mon, 29 Jun 2026 22:14:25 +0800 [thread overview]
Message-ID: <20260629-msm-dp-mst-v5-4-2ed6aee1867a@oss.qualcomm.com> (raw)
In-Reply-To: <20260629-msm-dp-mst-v5-0-2ed6aee1867a@oss.qualcomm.com>
From: Abhinav Kumar <quic_abhinavk@quicinc.com>
In the DP MST architecture, stream 1 shares the same link clock as
stream 0 but uses different register offsets within the same link
register space. Use the dp_panel's stream_id to select the correct
register offsets for stream 1 in dp_catalog. Also add stream 1
register defines.
Streams 2 and 3 are not covered here, as they use separate link clocks
and require separate handling.
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
---
drivers/gpu/drm/msm/dp/dp_ctrl.c | 78 ++++++++++++++++++++++++------
drivers/gpu/drm/msm/dp/dp_ctrl.h | 4 +-
drivers/gpu/drm/msm/dp/dp_display.c | 24 +++++++++-
drivers/gpu/drm/msm/dp/dp_panel.c | 94 ++++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/msm/dp/dp_panel.h | 4 ++
drivers/gpu/drm/msm/dp/dp_reg.h | 44 +++++++++++++++++
6 files changed, 229 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 68fb4facb056..5c491a925b4b 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -117,6 +117,8 @@ struct msm_dp_ctrl_private {
struct msm_dp_link *link;
void __iomem *ahb_base;
void __iomem *link_base;
+ void __iomem *mst2link_base;
+ void __iomem *mst3link_base;
struct phy *phy;
@@ -172,6 +174,49 @@ static inline void msm_dp_write_link(struct msm_dp_ctrl_private *ctrl,
writel(data, ctrl->link_base + offset);
}
+static inline u32 msm_dp_read_stream_link(struct msm_dp_ctrl_private *ctrl,
+ enum msm_dp_stream_id stream_id, u32 offset)
+{
+ offset = msm_dp_stream_reg(stream_id, offset);
+ switch (stream_id) {
+ case DP_STREAM_0:
+ case DP_STREAM_1:
+ return readl_relaxed(ctrl->link_base + offset);
+ case DP_STREAM_2:
+ return readl_relaxed(ctrl->mst2link_base + offset);
+ case DP_STREAM_3:
+ return readl_relaxed(ctrl->mst3link_base + offset);
+ default:
+ DRM_ERROR("error stream_id\n");
+ return 0;
+ }
+}
+
+static inline void msm_dp_write_stream_link(struct msm_dp_ctrl_private *ctrl,
+ enum msm_dp_stream_id stream_id, u32 offset, u32 data)
+{
+ /*
+ * To make sure link reg writes happens before any other operation,
+ * this function uses writel() instread of writel_relaxed()
+ */
+ offset = msm_dp_stream_reg(stream_id, offset);
+ switch (stream_id) {
+ case DP_STREAM_0:
+ case DP_STREAM_1:
+ writel(data, ctrl->link_base + offset);
+ break;
+ case DP_STREAM_2:
+ writel(data, ctrl->mst2link_base + offset);
+ break;
+ case DP_STREAM_3:
+ writel(data, ctrl->mst3link_base + offset);
+ break;
+ default:
+ DRM_ERROR("error stream_id\n");
+ break;
+ }
+}
+
static int msm_dp_aux_link_configure(struct drm_dp_aux *aux,
struct msm_dp_link_info *link)
{
@@ -397,7 +442,8 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl,
/*
* RMW: Called from atomic_enable(). Serialized by the DRM atomic framework.
*/
- config = msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL);
+ if (msm_dp_panel->stream_id == DP_STREAM_0)
+ config = msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL);
if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420)
config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */
@@ -412,7 +458,7 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl,
drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=0x%x\n", config);
- msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config);
+ msm_dp_write_stream_link(ctrl, msm_dp_panel->stream_id, REG_DP_CONFIGURATION_CTRL, config);
}
static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl,
@@ -469,7 +515,7 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl,
msm_dp_panel->msm_dp_mode.bpp);
colorimetry_cfg = msm_dp_link_get_colorimetry_config(ctrl->link);
- misc_val = msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0);
+ misc_val = msm_dp_read_stream_link(ctrl, msm_dp_panel->stream_id, REG_DP_MISC1_MISC0);
/* clear bpp bits */
misc_val &= ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT);
@@ -479,7 +525,7 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl,
misc_val |= DP_MISC0_SYNCHRONOUS_CLK;
drm_dbg_dp(ctrl->drm_dev, "misc settings = 0x%x\n", misc_val);
- msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val);
+ msm_dp_write_stream_link(ctrl, msm_dp_panel->stream_id, REG_DP_MISC1_MISC0, misc_val);
}
static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl,
@@ -2461,8 +2507,8 @@ static int msm_dp_ctrl_link_retrain(struct msm_dp_ctrl_private *ctrl,
}
static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl,
- u32 rate, u32 stream_rate_khz,
- bool is_ycbcr_420)
+ struct msm_dp_panel *panel,
+ u32 rate, u32 stream_rate_khz)
{
u32 pixel_m, pixel_n;
u32 mvid, nvid, pixel_div, dispcc_input_rate;
@@ -2514,7 +2560,7 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl,
nvid = temp;
}
- if (is_ycbcr_420)
+ if (panel->msm_dp_mode.out_fmt_is_yuv_420)
mvid /= 2;
if (link_rate_hbr2 == rate)
@@ -2524,8 +2570,8 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl,
nvid *= 3;
drm_dbg_dp(ctrl->drm_dev, "mvid=0x%x, nvid=0x%x\n", mvid, nvid);
- msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID, mvid);
- msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid);
+ msm_dp_write_stream_link(ctrl, panel->stream_id, REG_DP_SOFTWARE_MVID, mvid);
+ msm_dp_write_stream_link(ctrl, panel->stream_id, REG_DP_SOFTWARE_NVID, nvid);
}
int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl,
@@ -2597,14 +2643,14 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *
msm_dp_ctrl_lane_mapping(ctrl);
msm_dp_setup_peripheral_flush(ctrl);
- msm_dp_ctrl_config_ctrl_link(ctrl, panel);
+ if (panel->stream_id == DP_STREAM_0)
+ msm_dp_ctrl_config_ctrl_link(ctrl, panel);
msm_dp_ctrl_configure_source_params(ctrl, panel);
msm_dp_ctrl_config_msa(ctrl,
- ctrl->link->link_params.rate,
- pixel_rate_orig,
- panel->msm_dp_mode.out_fmt_is_yuv_420);
+ panel, ctrl->link->link_params.rate,
+ pixel_rate_orig);
msm_dp_panel_clear_dsc_dto(panel);
@@ -2788,7 +2834,9 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link
struct drm_dp_aux *aux,
struct phy *phy,
void __iomem *ahb_base,
- void __iomem *link_base)
+ void __iomem *link_base,
+ void __iomem *mst2link_base,
+ void __iomem *mst3link_base)
{
struct msm_dp_ctrl_private *ctrl;
int ret;
@@ -2827,6 +2875,8 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link
ctrl->phy = phy;
ctrl->ahb_base = ahb_base;
ctrl->link_base = link_base;
+ ctrl->mst2link_base = mst2link_base;
+ ctrl->mst3link_base = mst3link_base;
ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl);
if (ret) {
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h
index 305add3dcd93..49d16911ae8b 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.h
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h
@@ -35,7 +35,9 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev,
struct drm_dp_aux *aux,
struct phy *phy,
void __iomem *ahb_base,
- void __iomem *link_base);
+ void __iomem *link_base,
+ void __iomem *mst2link_base,
+ void __iomem *mst3link_base);
void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl,
struct msm_dp_panel *panel);
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index 74f481a18164..c58896b351b3 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -85,6 +85,12 @@ struct msm_dp_display_private {
void __iomem *link_base;
size_t link_len;
+ void __iomem *mst2link_base;
+ size_t mst2link_len;
+
+ void __iomem *mst3link_base;
+ size_t mst3link_len;
+
void __iomem *pixel_base[DP_STREAM_MAX];
size_t pixel_len;
@@ -564,7 +570,8 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp)
goto error_link;
}
- dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp->pixel_base[0]);
+ dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base,
+ dp->mst2link_base, dp->mst3link_base, dp->pixel_base[0]);
if (IS_ERR(dp->panel)) {
rc = PTR_ERR(dp->panel);
DRM_ERROR("failed to initialize panel, rc = %d\n", rc);
@@ -573,7 +580,8 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp)
}
dp->ctrl = msm_dp_ctrl_get(dev, dp->link, dp->aux,
- phy, dp->ahb_base, dp->link_base);
+ phy, dp->ahb_base, dp->link_base,
+ dp->mst2link_base, dp->mst3link_base);
if (IS_ERR(dp->ctrl)) {
rc = PTR_ERR(dp->ctrl);
DRM_ERROR("failed to initialize ctrl, rc = %d\n", rc);
@@ -850,6 +858,10 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp)
msm_dp_display->aux_base, "dp_aux");
msm_disp_snapshot_add_block(disp_state, msm_dp_display->link_len,
msm_dp_display->link_base, "dp_link");
+ msm_disp_snapshot_add_block(disp_state, msm_dp_display->mst2link_len,
+ msm_dp_display->mst2link_base, "dp_mst2link");
+ msm_disp_snapshot_add_block(disp_state, msm_dp_display->mst3link_len,
+ msm_dp_display->mst3link_base, "dp_mst3link");
msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len,
msm_dp_display->pixel_base[0], "dp_p0");
msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len,
@@ -1196,6 +1208,14 @@ static int msm_dp_display_get_io(struct msm_dp_display_private *display)
}
}
+ display->mst2link_base = msm_dp_ioremap(pdev, 7, &display->mst2link_len);
+ if (IS_ERR(display->mst2link_base))
+ DRM_DEBUG_DP("unable to remap link region: %pe\n", display->mst2link_base);
+
+ display->mst3link_base = msm_dp_ioremap(pdev, 8, &display->mst3link_len);
+ if (IS_ERR(display->mst3link_base))
+ DRM_DEBUG_DP("unable to remap link region: %pe\n", display->mst3link_base);
+
return 0;
}
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c
index 238920c45261..e0c0e8c9178c 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.c
+++ b/drivers/gpu/drm/msm/dp/dp_panel.c
@@ -25,13 +25,84 @@ struct msm_dp_panel_private {
struct drm_dp_aux *aux;
struct msm_dp_link *link;
void __iomem *link_base;
+ void __iomem *mst2link_base;
+ void __iomem *mst3link_base;
void __iomem *pixel_base;
bool panel_on;
};
+u32 msm_dp_stream_reg(enum msm_dp_stream_id id, u32 reg)
+{
+ bool is_s1 = (id == DP_STREAM_1);
+
+ if (id == DP_STREAM_0)
+ return reg;
+
+ switch (reg) {
+ case REG_DP_CONFIGURATION_CTRL:
+ return is_s1 ? REG_DP1_CONFIGURATION_CTRL : REG_DP_MSTLINK_CONFIGURATION_CTRL;
+ case REG_DP_SOFTWARE_MVID:
+ return is_s1 ? REG_DP1_SOFTWARE_MVID : REG_MSTLINK_SOFTWARE_MVID;
+ case REG_DP_SOFTWARE_NVID:
+ return is_s1 ? REG_DP1_SOFTWARE_NVID : REG_MSTLINK_SOFTWARE_NVID;
+ case REG_DP_TOTAL_HOR_VER:
+ return is_s1 ? REG_DP1_TOTAL_HOR_VER : REG_DP_MSTLINK_TOTAL_HOR_VER;
+ case REG_DP_START_HOR_VER_FROM_SYNC:
+ return is_s1 ? REG_DP1_START_HOR_VER_FROM_SYNC
+ : REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC;
+ case REG_DP_HSYNC_VSYNC_WIDTH_POLARITY:
+ return is_s1 ? REG_DP1_HSYNC_VSYNC_WIDTH_POLARITY
+ : REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY;
+ case REG_DP_ACTIVE_HOR_VER:
+ return is_s1 ? REG_DP1_ACTIVE_HOR_VER : REG_DP_MSTLINK_ACTIVE_HOR_VER;
+ case REG_DP_MISC1_MISC0:
+ return is_s1 ? REG_DP1_MISC1_MISC0 : REG_DP_MSTLINK_MISC1_MISC0;
+ case MMSS_DP_SDP_CFG:
+ return is_s1 ? MMSS_DP1_SDP_CFG : MMSS_DP_MSTLINK_SDP_CFG;
+ case MMSS_DP_SDP_CFG2:
+ return is_s1 ? MMSS_DP1_SDP_CFG2 : MMSS_DP_MSTLINK_SDP_CFG2;
+ case MMSS_DP_SDP_CFG3:
+ return is_s1 ? MMSS_DP1_SDP_CFG3 : MMSS_DP_MSTLINK_SDP_CFG3;
+ case MMSS_DP_GENERIC0_0:
+ return is_s1 ? MMSS_DP1_GENERIC0_0 : MMSS_DP_MSTLINK_GENERIC0_0;
+ case MMSS_DP_GENERIC0_1:
+ return is_s1 ? MMSS_DP1_GENERIC0_1 : MMSS_DP_MSTLINK_GENERIC0_1;
+ case MMSS_DP_GENERIC0_2:
+ return is_s1 ? MMSS_DP1_GENERIC0_2 : MMSS_DP_MSTLINK_GENERIC0_2;
+ case MMSS_DP_GENERIC0_3:
+ return is_s1 ? MMSS_DP1_GENERIC0_3 : MMSS_DP_MSTLINK_GENERIC0_3;
+ case MMSS_DP_GENERIC0_4:
+ return is_s1 ? MMSS_DP1_GENERIC0_4 : MMSS_DP_MSTLINK_GENERIC0_4;
+ case MMSS_DP_GENERIC0_5:
+ return is_s1 ? MMSS_DP1_GENERIC0_5 : MMSS_DP_MSTLINK_GENERIC0_5;
+ case MMSS_DP_GENERIC0_6:
+ return is_s1 ? MMSS_DP1_GENERIC0_6 : MMSS_DP_MSTLINK_GENERIC0_6;
+ case MMSS_DP_GENERIC0_7:
+ return is_s1 ? MMSS_DP1_GENERIC0_7 : MMSS_DP_MSTLINK_GENERIC0_7;
+ case MMSS_DP_GENERIC0_8:
+ return is_s1 ? MMSS_DP1_GENERIC0_8 : MMSS_DP_MSTLINK_GENERIC0_8;
+ case MMSS_DP_GENERIC0_9:
+ return is_s1 ? MMSS_DP1_GENERIC0_9 : MMSS_DP_MSTLINK_GENERIC0_9;
+ default:
+ return reg;
+ }
+}
+
static inline u32 msm_dp_read_link(struct msm_dp_panel_private *panel, u32 offset)
{
- return readl_relaxed(panel->link_base + offset);
+ offset = msm_dp_stream_reg(panel->msm_dp_panel.stream_id, offset);
+ switch (panel->msm_dp_panel.stream_id) {
+ case DP_STREAM_0:
+ case DP_STREAM_1:
+ return readl_relaxed(panel->link_base + offset);
+ case DP_STREAM_2:
+ return readl_relaxed(panel->mst2link_base + offset);
+ case DP_STREAM_3:
+ return readl_relaxed(panel->mst3link_base + offset);
+ default:
+ DRM_ERROR("error stream_id\n");
+ return 0;
+ }
}
static inline void msm_dp_write_link(struct msm_dp_panel_private *panel,
@@ -41,7 +112,22 @@ static inline void msm_dp_write_link(struct msm_dp_panel_private *panel,
* To make sure link reg writes happens before any other operation,
* this function uses writel() instread of writel_relaxed()
*/
- writel(data, panel->link_base + offset);
+ offset = msm_dp_stream_reg(panel->msm_dp_panel.stream_id, offset);
+ switch (panel->msm_dp_panel.stream_id) {
+ case DP_STREAM_0:
+ case DP_STREAM_1:
+ writel(data, panel->link_base + offset);
+ break;
+ case DP_STREAM_2:
+ writel(data, panel->mst2link_base + offset);
+ break;
+ case DP_STREAM_3:
+ writel(data, panel->mst3link_base + offset);
+ break;
+ default:
+ DRM_ERROR("error stream_id\n");
+ break;
+ }
}
static inline void msm_dp_write_pn(struct msm_dp_panel_private *panel,
@@ -701,6 +787,8 @@ int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel,
struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux,
struct msm_dp_link *link,
void __iomem *link_base,
+ void __iomem *mst2link_base,
+ void __iomem *mst3link_base,
void __iomem *pixel_base)
{
struct msm_dp_panel_private *panel;
@@ -720,6 +808,8 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux
panel->link = link;
panel->link_base = link_base;
panel->pixel_base = pixel_base;
+ panel->mst2link_base = mst2link_base;
+ panel->mst3link_base = mst3link_base;
msm_dp_panel = &panel->msm_dp_panel;
msm_dp_panel->max_bw_code = DP_LINK_BW_8_1;
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h
index 218a09a2fa65..dc046fec24fc 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.h
+++ b/drivers/gpu/drm/msm/dp/dp_panel.h
@@ -99,8 +99,12 @@ static inline bool is_lane_count_valid(u32 lane_count)
lane_count == 4);
}
+u32 msm_dp_stream_reg(enum msm_dp_stream_id id, u32 reg);
+
struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux,
struct msm_dp_link *link,
void __iomem *link_base,
+ void __iomem *mst2link_base,
+ void __iomem *mst3link_base,
void __iomem *pixel_base);
#endif /* _DP_PANEL_H_ */
diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h
index 3689642b7fc0..310e5a1cc934 100644
--- a/drivers/gpu/drm/msm/dp/dp_reg.h
+++ b/drivers/gpu/drm/msm/dp/dp_reg.h
@@ -332,6 +332,50 @@
#define DP_TPG_VIDEO_CONFIG_BPP_8BIT (0x00000001)
#define DP_TPG_VIDEO_CONFIG_RGB (0x00000004)
+#define REG_DP1_CONFIGURATION_CTRL (0x00000400)
+#define REG_DP1_SOFTWARE_MVID (0x00000414)
+#define REG_DP1_SOFTWARE_NVID (0x00000418)
+#define REG_DP1_TOTAL_HOR_VER (0x0000041C)
+#define REG_DP1_START_HOR_VER_FROM_SYNC (0x00000420)
+#define REG_DP1_HSYNC_VSYNC_WIDTH_POLARITY (0x00000424)
+#define REG_DP1_ACTIVE_HOR_VER (0x00000428)
+#define REG_DP1_MISC1_MISC0 (0x0000042C)
+#define MMSS_DP1_GENERIC0_0 (0x00000490)
+#define MMSS_DP1_GENERIC0_1 (0x00000494)
+#define MMSS_DP1_GENERIC0_2 (0x00000498)
+#define MMSS_DP1_GENERIC0_3 (0x0000049C)
+#define MMSS_DP1_GENERIC0_4 (0x000004A0)
+#define MMSS_DP1_GENERIC0_5 (0x000004A4)
+#define MMSS_DP1_GENERIC0_6 (0x000004A8)
+#define MMSS_DP1_GENERIC0_7 (0x000004AC)
+#define MMSS_DP1_GENERIC0_8 (0x000004B0)
+#define MMSS_DP1_GENERIC0_9 (0x000004B4)
+#define MMSS_DP1_SDP_CFG (0x000004E0)
+#define MMSS_DP1_SDP_CFG2 (0x000004E4)
+#define MMSS_DP1_SDP_CFG3 (0x000004E8)
+
+#define REG_DP_MSTLINK_CONFIGURATION_CTRL (0x00000034)
+#define REG_MSTLINK_SOFTWARE_MVID (0x00000040)
+#define REG_MSTLINK_SOFTWARE_NVID (0x00000044)
+#define REG_DP_MSTLINK_TOTAL_HOR_VER (0x00000048)
+#define REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC (0x0000004C)
+#define REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY (0x00000050)
+#define REG_DP_MSTLINK_ACTIVE_HOR_VER (0x00000054)
+#define REG_DP_MSTLINK_MISC1_MISC0 (0x00000058)
+#define MMSS_DP_MSTLINK_GENERIC0_0 (0x000000BC)
+#define MMSS_DP_MSTLINK_GENERIC0_1 (0x000000C0)
+#define MMSS_DP_MSTLINK_GENERIC0_2 (0x000000C4)
+#define MMSS_DP_MSTLINK_GENERIC0_3 (0x000000C8)
+#define MMSS_DP_MSTLINK_GENERIC0_4 (0x000000CC)
+#define MMSS_DP_MSTLINK_GENERIC0_5 (0x000000D0)
+#define MMSS_DP_MSTLINK_GENERIC0_6 (0x000000D4)
+#define MMSS_DP_MSTLINK_GENERIC0_7 (0x000000D8)
+#define MMSS_DP_MSTLINK_GENERIC0_8 (0x000000DC)
+#define MMSS_DP_MSTLINK_GENERIC0_9 (0x000000E0)
+#define MMSS_DP_MSTLINK_SDP_CFG (0x0000010c)
+#define MMSS_DP_MSTLINK_SDP_CFG2 (0x0000011c)
+#define MMSS_DP_MSTLINK_SDP_CFG3 (0x00000114)
+
#define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088)
#define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C)
--
2.43.0
next prev parent reply other threads:[~2026-06-29 14:15 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-29 14:14 [PATCH RESEND v5 00/25] drm/msm/dp: Add MST support for MSM chipsets Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 01/25] drm/msm/dp: introduce stream_id for each DP panel Yongxing Mou
2026-07-12 11:11 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 02/25] drm/msm/dp: introduce max_streams for DP controller MST support Yongxing Mou
2026-07-12 11:17 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 03/25] drm/msm/dp: Add support for programming p1/p2/p3 register blocks Yongxing Mou
2026-07-12 11:23 ` Dmitry Baryshkov
2026-06-29 14:14 ` Yongxing Mou [this message]
2026-07-12 11:29 ` [PATCH RESEND v5 04/25] drm/msm/dp: use stream_id to change offsets in dp_catalog Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 05/25] drm/msm/dp: add support to send ACT packets for MST Yongxing Mou
2026-07-12 13:56 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 06/25] drm/msm/dp: Add support to enable MST in mainlink control Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 07/25] drm/msm/dp: no need to update tu calculation for mst Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 08/25] drm/msm/dp: Add support for MST channel slot allocation Yongxing Mou
2026-07-12 18:57 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 09/25] drm/msm/dp: Add support for sending VCPF packets in DP controller Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 10/25] drm/msm/dp: Always program MST_FIFO_CONSTANT_FILL for MST use cases Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 11/25] drm/msm/dp: move link-level teardown from display_disable to display_unprepare Yongxing Mou
2026-07-12 18:20 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 12/25] drm/msm/dp: factor out _helper variants of bridge ops accepting a panel Yongxing Mou
2026-07-12 18:43 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 13/25] drm/msm/dp: replace power_on with active_stream_cnt for dp_display Yongxing Mou
2026-07-12 18:51 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 14/25] drm/msm/dp: Mark the SST bridge disconnected when mst is active Yongxing Mou
2026-07-12 21:00 ` Dmitry Baryshkov
2026-07-12 21:03 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 15/25] drm/msm/dp: add an API to initialize MST on sink side Yongxing Mou
2026-07-12 21:35 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 16/25] drm/msm/dp: add msm_dp_display_get_panel() to initialize DP panel Yongxing Mou
2026-07-12 21:56 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 17/25] drm/msm/dp: add link_ready to manage link-level operations Yongxing Mou
2026-07-12 23:46 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 18/25] drm/msm/dpu: initialize encoders per stream for DP MST Yongxing Mou
2026-07-12 23:55 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 19/25] drm/msm/dp: initialize dp_mst module for each DP MST controller Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 20/25] drm/msm/dpu: expose dpu_encoder ops for DP MST reuse Yongxing Mou
2026-07-13 0:01 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 21/25] drm/msm/dpu: use msm_dp_get_mst_intf_id() to get the intf id Yongxing Mou
2026-07-13 0:09 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 22/25] drm/msm/dp: wire MST helpers into atomic check and commit paths Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 23/25] drm/msm/dp: add dp_mst_drm to manage DP MST encoder operations Yongxing Mou
2026-07-13 0:40 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 24/25] drm/msm/dp: add connector abstraction for DP MST Yongxing Mou
2026-07-13 0:52 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 25/25] drm/msm/dp: add HPD callback for dp MST Yongxing Mou
2026-07-13 0:54 ` Dmitry Baryshkov
2026-07-12 11:04 ` [PATCH RESEND v5 00/25] drm/msm/dp: Add MST support for MSM chipsets Dmitry Baryshkov
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