[PATCH v4 0/3] selftests/resctrl: Fix resctrl selftests issues on aarch64

[PATCH v4 0/3] selftests/resctrl: Fix resctrl selftests issues on aarch64

[Richard Cheng]

This series fixes numerous issues in the resctrl selftests on aarch64,
where they currently misreport failures.

Patch 1 skips L3_CAT at feature-check time when MPAM legitimately
reports every CBM bit as shareable, instead of failing the test.

Patch 2 adds aarch64 implementations of cl_flush() and sb() in
fill_buf.c so cache flushes are no longer silent no-ops.

Patch 3 teaches detect_vendor() about aarch64 (which exposes no
vendor_id in /proc/cpuinfo) and lets arch_supports_noncont_cat()
return true for ARM, fixing spurious L3_NONCONT_CAT failures.

Changes since v3:
    - Patch 2: replace "dc civac" in cl_flush() with a dirty store, per
      Ben Horgan's feedback that dc civac only cleans to the Point of
      Coherency and does not reach the SLC where MPAM cache portions
      are enforced.
    - Patch 1, Patch 3: no code changes.

Richard Cheng (3):
  selftests/resctrl: Skip L3_CAT when no exclusive cache portion exists
  selftests/resctrl: Implement cl_flush() and sb() for aarch64
  selftests/resctrl: Recognise aarch64 as a vendor for L3_NONCONT_CAT

 tools/testing/selftests/resctrl/cat_test.c    | 32 +++++++++++++++++--
 tools/testing/selftests/resctrl/fill_buf.c    | 11 +++++++
 tools/testing/selftests/resctrl/resctrl.h     |  1 +
 .../testing/selftests/resctrl/resctrl_tests.c | 21 ++++++++++++
 4 files changed, 62 insertions(+), 3 deletions(-)

-- 
2.43.0

[PATCH v4 1/3] selftests/resctrl: Skip L3_CAT when no exclusive cache portion exists

[Richard Cheng]

L3_CAT measures cache isolation, which requires at least one cache bit
that is not shared with non-CPU agents, i.e. cbm_mask & ~shareable_bits
must be non-zero. On MPAM, shareable_bits == cbm_mask is a legitimate
state, so there are situations in which no bit can be reported as
exclusive.

Previously get_mask_no_shareable() was invoked inside cat_run_test()
and silently returned -1, which surfaced as a test failure on arm64
MPAM systems.

Implement cat_feature_check() to perform the same check at feature-check
time. It prints a diagnostic and returns false so the test case is
skipped instead of failing.

Tested-by: Chen Yu <yu.c.chen@intel.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Richard Cheng <icheng@nvidia.com>
---
 tools/testing/selftests/resctrl/cat_test.c | 23 +++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c
index 371a2f26dc47..692860c7ce59 100644
--- a/tools/testing/selftests/resctrl/cat_test.c
+++ b/tools/testing/selftests/resctrl/cat_test.c
@@ -357,11 +357,32 @@ static bool noncont_cat_feature_check(const struct resctrl_test *test)
 	return resource_info_file_exists(test->resource, "sparse_masks");
 }
 
+static bool cat_feature_check(const struct resctrl_test *test)
+{
+	unsigned long mask;
+
+	if (!test_resource_feature_check(test))
+		return false;
+
+	/*
+	 * The CAT isolation measurement needs a cache portion that no
+	 * other agent shares. On MPAM the kernel may legitimately report
+	 * all bits as shareable; skip the test if that is the case.
+	 */
+	if (get_mask_no_shareable(test->resource, &mask)) {
+		ksft_print_msg("All %s bits are shareable; cannot measure CAT isolation\n",
+			       test->resource);
+		return false;
+	}
+
+	return true;
+}
+
 struct resctrl_test l3_cat_test = {
 	.name = "L3_CAT",
 	.group = "CAT",
 	.resource = "L3",
-	.feature_check = test_resource_feature_check,
+	.feature_check = cat_feature_check,
 	.run_test = cat_run_test,
 	.cleanup = cat_test_cleanup,
 };
-- 
2.43.0

Re: [PATCH v4 1/3] selftests/resctrl: Skip L3_CAT when no exclusive cache portion exists

[Reinette Chatre]

Hi Richard,

On 7/21/26 8:59 PM, Richard Cheng wrote:
> L3_CAT measures cache isolation, which requires at least one cache bit
> that is not shared with non-CPU agents, i.e. cbm_mask & ~shareable_bits
> must be non-zero. On MPAM, shareable_bits == cbm_mask is a legitimate
> state, so there are situations in which no bit can be reported as
> exclusive.
> 
> Previously get_mask_no_shareable() was invoked inside cat_run_test()
> and silently returned -1, which surfaced as a test failure on arm64
> MPAM systems.
> 
> Implement cat_feature_check() to perform the same check at feature-check
> time. It prints a diagnostic and returns false so the test case is
> skipped instead of failing.
> 
> Tested-by: Chen Yu <yu.c.chen@intel.com>
> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> Signed-off-by: Richard Cheng <icheng@nvidia.com>
> ---

This patch is unchanged from v3. My comments against v3 still apply:
https://lore.kernel.org/lkml/5d76e776-82d3-4f02-8384-a890349ae96c@intel.com/

As noted there, this issue does not just impact aarch64. Could you please
split this patch from this series? When it is ready I would like to make a
request for its inclusion in the next cycle.

Thank you.

Reinette

Re: [PATCH v4 1/3] selftests/resctrl: Skip L3_CAT when no exclusive cache portion exists

[Richard Cheng]

On Wed, Aug 12, 2026 at 10:22:03AM +0800, Reinette Chatre wrote:
> Hi Richard,
> 
> On 7/21/26 8:59 PM, Richard Cheng wrote:
> > L3_CAT measures cache isolation, which requires at least one cache bit
> > that is not shared with non-CPU agents, i.e. cbm_mask & ~shareable_bits
> > must be non-zero. On MPAM, shareable_bits == cbm_mask is a legitimate
> > state, so there are situations in which no bit can be reported as
> > exclusive.
> > 
> > Previously get_mask_no_shareable() was invoked inside cat_run_test()
> > and silently returned -1, which surfaced as a test failure on arm64
> > MPAM systems.
> > 
> > Implement cat_feature_check() to perform the same check at feature-check
> > time. It prints a diagnostic and returns false so the test case is
> > skipped instead of failing.
> > 
> > Tested-by: Chen Yu <yu.c.chen@intel.com>
> > Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> > Signed-off-by: Richard Cheng <icheng@nvidia.com>
> > ---
> 
> This patch is unchanged from v3. My comments against v3 still apply:
> https://lore.kernel.org/lkml/5d76e776-82d3-4f02-8384-a890349ae96c@intel.com/
> 
> As noted there, this issue does not just impact aarch64. Could you please
> split this patch from this series? When it is ready I would like to make a
> request for its inclusion in the next cycle.
> 
> Thank you.
> 
> Reinette

Hi Reinette,

Thanks for your patient and review.

Just to confirm that I understand correctly before I send v5.

I plan to
1. Split this patch out of the arm64 series and send it as a standalone v5 patch
2. Keep the code change the same, and udpate the commit message to make it clear that having no exclusive cache portion causes
   L3_CAT to fail, and simplify the desciprtion as you suggested
3. Change the in-code comment to platform-neutral wording

About the editted commit message, I plan to write it like the following

"""
selftests/resctrl: Skip L3_CAT when no exclusive cache portion exists

L3_CAT measures cache isolation, which requires at least one cache bit
that is not shared with non-CPU agents, i.e. cbm_mask & ~shareable_bits
must be non-zero. Some platforms legitimately report every cache bit as
shareable, leaving no exclusive cache portion and causing L3_CAT to fail.

Skip, rather than fail, the L3_CAT test when the platform has no
exclusive cache portion that the test can use.
"""

Does this match what you imagined ?

Best regards,
Richard Cheng.

Re: [PATCH v4 1/3] selftests/resctrl: Skip L3_CAT when no exclusive cache portion exists

[Reinette Chatre]

Hi Richard,

On 8/18/26 3:54 AM, Richard Cheng wrote:
> On Wed, Aug 12, 2026 at 10:22:03AM +0800, Reinette Chatre wrote:
>> Hi Richard,
>>
>> On 7/21/26 8:59 PM, Richard Cheng wrote:
>>> L3_CAT measures cache isolation, which requires at least one cache bit
>>> that is not shared with non-CPU agents, i.e. cbm_mask & ~shareable_bits
>>> must be non-zero. On MPAM, shareable_bits == cbm_mask is a legitimate
>>> state, so there are situations in which no bit can be reported as
>>> exclusive.
>>>
>>> Previously get_mask_no_shareable() was invoked inside cat_run_test()
>>> and silently returned -1, which surfaced as a test failure on arm64
>>> MPAM systems.
>>>
>>> Implement cat_feature_check() to perform the same check at feature-check
>>> time. It prints a diagnostic and returns false so the test case is
>>> skipped instead of failing.
>>>
>>> Tested-by: Chen Yu <yu.c.chen@intel.com>
>>> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
>>> Signed-off-by: Richard Cheng <icheng@nvidia.com>
>>> ---
>>
>> This patch is unchanged from v3. My comments against v3 still apply:
>> https://lore.kernel.org/lkml/5d76e776-82d3-4f02-8384-a890349ae96c@intel.com/
>>
>> As noted there, this issue does not just impact aarch64. Could you please
>> split this patch from this series? When it is ready I would like to make a
>> request for its inclusion in the next cycle.
>>
>> Thank you.
>>
>> Reinette
> 
> Hi Reinette,
> 
> Thanks for your patient and review.
> 
> Just to confirm that I understand correctly before I send v5.
> 
> I plan to
> 1. Split this patch out of the arm64 series and send it as a standalone v5 patch
> 2. Keep the code change the same, and udpate the commit message to make it clear that having no exclusive cache portion causes
>    L3_CAT to fail, and simplify the desciprtion as you suggested
> 3. Change the in-code comment to platform-neutral wording

Sounds good, thank you.

> 
> About the editted commit message, I plan to write it like the following
> 
> """
> selftests/resctrl: Skip L3_CAT when no exclusive cache portion exists
> 
> L3_CAT measures cache isolation, which requires at least one cache bit

nit:
I do not see L3_CAT as measuring cache isolation. Instead, it requires
cache isolation to test whether cache allocation works.

How about something like (please feel free to adjust):
	L3_CAT requires an exclusive cache portion to test cache allocation.
	This means that there cannot be any overlap between the cache portion
	used by the test and the portions of cache other agents may allocate into.

	Some platforms legitimately report every cache portion as shareable,
	leaving no exclusive cache portion and causing L3_CAT to fail.

	Skip, rather than fail, ...

> that is not shared with non-CPU agents, i.e. cbm_mask & ~shareable_bits
> must be non-zero. Some platforms legitimately report every cache bit as
> shareable, leaving no exclusive cache portion and causing L3_CAT to fail.
> 
> Skip, rather than fail, the L3_CAT test when the platform has no
> exclusive cache portion that the test can use.
> """
> 
> Does this match what you imagined ?
This looks good to me. Thank you very much.

Please also consider the above feedback when adjusting the in-code comment.

Specifically, the original comment:
	/*
	 * The CAT isolation measurement needs a cache portion that no
	 * other agent shares. On MPAM the kernel may legitimately report
	 * all bits as shareable; skip the test if that is the case.
	 */
Could be something like:
	/*
	 * Test requires an exclusive cache portion. Some platforms may
	 * legitimately report all bits as shareable; skip the test if that
	 * is the case.
	 */

And the original message:
		ksft_print_msg("All %s bits are shareable; cannot measure CAT isolation\n",
			       test->resource);
Could be something like:
		ksft_print_msg("All %s bits are shareable; test requires an exclusive cache portion\n",
			       test->resource);

Reinette

[PATCH v4 2/3] selftests/resctrl: Implement cl_flush() and sb() for aarch64

[Richard Cheng]

cl_flush() and sb() compile to empty functions on aarch64, making
mem_flush() a silent no-op and leaving CMT/CAT tests operating on
unflushed state.

Add "dsb sy" for sb(), ARM requires a DSB whose access type covers both
loads and stores.

For cl_flush(), "dc civac" only reaches the Point of Coherency, on
ARM MPAM systems the SLC lies past the PoC and may be a NOP on coherent
platforms. Instead, dirty each cacheline with a store so that
mem_flush's full-buffer sweep evicts lines from the SLC via LRU
pressure.

Signed-off-by: Richard Cheng <icheng@nvidia.com>
---
Changes since v3:
  - cl_flush(): replace "dc civac" with a dirty store. dc civac only
    cleans to the Point of Coherency, so it does not reach the SLC
    where MPAM cache portions are enforced. Rely on LRU eviction from
    mem_flush()'s full-buffer sweep instead.

 tools/testing/selftests/resctrl/fill_buf.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/tools/testing/selftests/resctrl/fill_buf.c b/tools/testing/selftests/resctrl/fill_buf.c
index b9fa7968cd6e..eae0262fe265 100644
--- a/tools/testing/selftests/resctrl/fill_buf.c
+++ b/tools/testing/selftests/resctrl/fill_buf.c
@@ -27,6 +27,9 @@ static void sb(void)
 #if defined(__i386) || defined(__x86_64)
 	asm volatile("sfence\n\t"
 		     : : : "memory");
+#elif defined(__aarch64__)
+	asm volatile("dsb sy\n\t"
+		     : : : "memory");
 #endif
 }
 
@@ -35,6 +38,14 @@ static void cl_flush(void *p)
 #if defined(__i386) || defined(__x86_64)
 	asm volatile("clflush (%0)\n\t"
 		     : : "r"(p) : "memory");
+#elif defined(__aarch64__)
+	/*
+	 * Dirty the cache line with a store. As mem_flush() sweeps
+	 * the full test buffer (sized larger than the SLC), cache pressure
+	 * evicts lines from the SLC via LRU replacement.
+	 */
+	asm volatile("strb wzr, [%0]\n\t"
+		     : : "r"(p) : "memory");
 #endif
 }
 
-- 
2.43.0

Re: [PATCH v4 2/3] selftests/resctrl: Implement cl_flush() and sb() for aarch64

[Reinette Chatre]

Hi Everybody,

Could the resctrl Arm folks please consider this patch?

Thank you very much.

Reinette

On 7/21/26 8:59 PM, Richard Cheng wrote:
> cl_flush() and sb() compile to empty functions on aarch64, making
> mem_flush() a silent no-op and leaving CMT/CAT tests operating on
> unflushed state.
> 
> Add "dsb sy" for sb(), ARM requires a DSB whose access type covers both
> loads and stores.
> 
> For cl_flush(), "dc civac" only reaches the Point of Coherency, on
> ARM MPAM systems the SLC lies past the PoC and may be a NOP on coherent
> platforms. Instead, dirty each cacheline with a store so that
> mem_flush's full-buffer sweep evicts lines from the SLC via LRU
> pressure.
> 
> Signed-off-by: Richard Cheng <icheng@nvidia.com>
> ---
> Changes since v3:
>   - cl_flush(): replace "dc civac" with a dirty store. dc civac only
>     cleans to the Point of Coherency, so it does not reach the SLC
>     where MPAM cache portions are enforced. Rely on LRU eviction from
>     mem_flush()'s full-buffer sweep instead.
> 
>  tools/testing/selftests/resctrl/fill_buf.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/tools/testing/selftests/resctrl/fill_buf.c b/tools/testing/selftests/resctrl/fill_buf.c
> index b9fa7968cd6e..eae0262fe265 100644
> --- a/tools/testing/selftests/resctrl/fill_buf.c
> +++ b/tools/testing/selftests/resctrl/fill_buf.c
> @@ -27,6 +27,9 @@ static void sb(void)
>  #if defined(__i386) || defined(__x86_64)
>  	asm volatile("sfence\n\t"
>  		     : : : "memory");
> +#elif defined(__aarch64__)
> +	asm volatile("dsb sy\n\t"
> +		     : : : "memory");
>  #endif
>  }
>  
> @@ -35,6 +38,14 @@ static void cl_flush(void *p)
>  #if defined(__i386) || defined(__x86_64)
>  	asm volatile("clflush (%0)\n\t"
>  		     : : "r"(p) : "memory");
> +#elif defined(__aarch64__)
> +	/*
> +	 * Dirty the cache line with a store. As mem_flush() sweeps
> +	 * the full test buffer (sized larger than the SLC), cache pressure
> +	 * evicts lines from the SLC via LRU replacement.
> +	 */
> +	asm volatile("strb wzr, [%0]\n\t"
> +		     : : "r"(p) : "memory");
>  #endif
>  }
>  

[PATCH v4 3/3] selftests/resctrl: Recognise aarch64 as a vendor for L3_NONCONT_CAT

[Richard Cheng]

aarch64 has no vendor_id in /proc/cpuinfo, so detect_vendor() returns 0
and arch_supports_noncont_cat() falls through to "return false".
L3_NONCONT_CAT therefore spuriously fails on every ARM MPAM platform.

Define ARCH_ARM, short-circuit detect_vendor() to it on aarch64, and
add it to the AMD/Hygon always-supports early-out in
arch_supports_noncont_cat().

aarch64 has many implementers (ARM 0x41, NVIDIA 0x43, etc.), but MPAM
mandates non-contiguous CPBM uniformly, so per-implementer handling is
not needed here.

Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: Richard Cheng <icheng@nvidia.com>
---
 tools/testing/selftests/resctrl/cat_test.c    |  9 ++++++--
 tools/testing/selftests/resctrl/resctrl.h     |  1 +
 .../testing/selftests/resctrl/resctrl_tests.c | 21 +++++++++++++++++++
 3 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c
index 692860c7ce59..55aca0af02c4 100644
--- a/tools/testing/selftests/resctrl/cat_test.c
+++ b/tools/testing/selftests/resctrl/cat_test.c
@@ -271,8 +271,13 @@ static bool arch_supports_noncont_cat(const struct resctrl_test *test)
 {
 	unsigned int vendor_id = get_vendor();
 
-	/* AMD and Hygon always support non-contiguous CBM. */
-	if (vendor_id == ARCH_AMD || vendor_id == ARCH_HYGON)
+	/*
+	 * AMD and Hygon always support non-contiguous CBM. ARM/MPAM defines
+	 * MPAMCFG_CPBM as a bitmap with no contiguity constraint per ARM
+	 * DDI 0598.
+	 */
+	if (vendor_id == ARCH_AMD || vendor_id == ARCH_HYGON ||
+	    vendor_id == ARCH_ARM)
 		return true;
 
 #if defined(__i386__) || defined(__x86_64__) /* arch */
diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/selftests/resctrl/resctrl.h
index ad1c17c0b0bf..5c752fc5d470 100644
--- a/tools/testing/selftests/resctrl/resctrl.h
+++ b/tools/testing/selftests/resctrl/resctrl.h
@@ -40,6 +40,7 @@
 #define ARCH_INTEL	BIT(0)
 #define ARCH_AMD	BIT(1)
 #define ARCH_HYGON	BIT(2)
+#define ARCH_ARM	BIT(3)
 
 #define END_OF_TESTS	1
 
diff --git a/tools/testing/selftests/resctrl/resctrl_tests.c b/tools/testing/selftests/resctrl/resctrl_tests.c
index 593f0ca5251b..57f9f9c0992b 100644
--- a/tools/testing/selftests/resctrl/resctrl_tests.c
+++ b/tools/testing/selftests/resctrl/resctrl_tests.c
@@ -24,6 +24,15 @@ static struct resctrl_test *resctrl_tests[] = {
 	&l2_noncont_cat_test,
 };
 
+static bool detect_aarch64(void)
+{
+#if defined(__aarch64__)
+	return true;
+#else
+	return false;
+#endif
+}
+
 static unsigned int detect_vendor(void)
 {
 	static unsigned int vendor_id;
@@ -35,6 +44,18 @@ static unsigned int detect_vendor(void)
 	if (initialized)
 		return vendor_id;
 
+	if (detect_aarch64()) {
+		/*
+		 * aarch64 has no userspace vendor_id in /proc/cpuinfo.
+		 * MPAM-capable ARM implementations follow ARM DDI 0598;
+		 * treat all aarch64 builds as a single vendor for the
+		 * purposes of resctrl selftests.
+		 */
+		vendor_id = ARCH_ARM;
+		initialized = true;
+		return vendor_id;
+	}
+
 	inf = fopen("/proc/cpuinfo", "r");
 	if (!inf) {
 		vendor_id = 0;
-- 
2.43.0