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* [PATCH] arm64: dts: rockchip: fix hym8563 interrupt pin on Orange Pi 5 Plus
@ 2026-09-06 18:16 Igor Paunovic
  2026-09-08  0:02 ` Ondřej Jirman
  0 siblings, 1 reply; 2+ messages in thread
From: Igor Paunovic @ 2026-09-06 18:16 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Cristian Ciocaltea, Ondrej Jirman, devicetree, linux-arm-kernel,
	linux-rockchip, linux-kernel, stable, Igor Paunovic

The interrupt line of the hym8563 RTC on the Orange Pi 5 Plus is routed
to GPIO0_C6, not GPIO0_B0. The vendor device tree uses RK_PC6 with a
pull-up for this pin; the mainline board file uses RK_PB0, which is not
connected to the RTC.

As a result the alarm interrupt never reaches the SoC, so the RTC alarm
cannot wake the board: rtcwake enters s2idle and the board never
returns, which looks like a hang.

This was verified on the board by enabling the alarm interrupt (AIE with
AF already set, so INT# is asserted) and sampling the EXT_PORT register
of all five GPIO banks: GPIO0_C6 is the only pad that follows AIE
(high with AIE=0, low with AIE=1, across repeated cycles), while GPIO0_B0
stays high and its interrupt counter stays at zero.

Switch the interrupt and its pinctrl entry to GPIO0_C6 and use a pull-up,
as the vendor tree does for this open-drain line.

With this change the alarm interrupt fires while the system is running
and the RTC wakes the board from s2idle ('PM: Triggering wakeup from
IRQ 52'); before it, rtcwake never returned.

Fixes: 236d225e1ee7 ("arm64: dts: rockchip: Add board device tree for rk3588-orangepi-5-plus")
Cc: stable@vger.kernel.org
Assisted-by: LLM checkpatch dtbs_check
Signed-off-by: Igor Paunovic <royalnet026@gmail.com>
---
Notes for reviewers (not part of the commit message):

Measured on an Orange Pi 5 Plus with the vendor-style method described above
(GPIO0 EXT_PORT sampled while toggling the alarm interrupt enable); the vendor
device tree for this board uses RK_PC6 with a pull-up. With the fix the alarm
IRQ fires at runtime and the RTC wakes the SoC from s2idle. Note that on this
board the resume itself can still stall later in the USB 2.0 host controllers
(a separate, unrelated issue being looked at); it does not affect this fix.

 arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
index 145986695720..572b892e4066 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
@@ -189,7 +189,7 @@ &hdptxphy1 {
 
 &hym8563 {
 	interrupt-parent = <&gpio0>;
-	interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+	interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&hym8563_int>;
 };
@@ -298,7 +298,7 @@ hdmi1_tx_on_h: hdmi1-tx-on-h {
 
 	hym8563 {
 		hym8563_int: hym8563-int {
-			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
 	};
 

base-commit: 1fc5a74b108fc90951890ec513ac81869f5eaff1
-- 
2.43.0


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH] arm64: dts: rockchip: fix hym8563 interrupt pin on Orange Pi 5 Plus
  2026-09-06 18:16 [PATCH] arm64: dts: rockchip: fix hym8563 interrupt pin on Orange Pi 5 Plus Igor Paunovic
@ 2026-09-08  0:02 ` Ondřej Jirman
  0 siblings, 0 replies; 2+ messages in thread
From: Ondřej Jirman @ 2026-09-08  0:02 UTC (permalink / raw)
  To: Igor Paunovic
  Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Cristian Ciocaltea, devicetree, linux-arm-kernel, linux-rockchip,
	linux-kernel, stable

Hello,

On Sun, Sep 06, 2026 at 08:16:22PM +0200, Igor Paunovic wrote:
> The interrupt line of the hym8563 RTC on the Orange Pi 5 Plus is routed
> to GPIO0_C6, not GPIO0_B0. The vendor device tree uses RK_PC6 with a
> pull-up for this pin; the mainline board file uses RK_PB0, which is not
> connected to the RTC.
> 
> As a result the alarm interrupt never reaches the SoC, so the RTC alarm
> cannot wake the board: rtcwake enters s2idle and the board never
> returns, which looks like a hang.
> 
> This was verified on the board by enabling the alarm interrupt (AIE with
> AF already set, so INT# is asserted) and sampling the EXT_PORT register
> of all five GPIO banks: GPIO0_C6 is the only pad that follows AIE
> (high with AIE=0, low with AIE=1, across repeated cycles), while GPIO0_B0
> stays high and its interrupt counter stays at zero.
> 
> Switch the interrupt and its pinctrl entry to GPIO0_C6 and use a pull-up,
> as the vendor tree does for this open-drain line.
> 
> With this change the alarm interrupt fires while the system is running
> and the RTC wakes the board from s2idle ('PM: Triggering wakeup from
> IRQ 52'); before it, rtcwake never returned.
> 
> Fixes: 236d225e1ee7 ("arm64: dts: rockchip: Add board device tree for rk3588-orangepi-5-plus")
> Cc: stable@vger.kernel.org
> Assisted-by: LLM checkpatch dtbs_check
> Signed-off-by: Igor Paunovic <royalnet026@gmail.com>
> ---
> Notes for reviewers (not part of the commit message):
> 
> Measured on an Orange Pi 5 Plus with the vendor-style method described above
> (GPIO0 EXT_PORT sampled while toggling the alarm interrupt enable); the vendor
> device tree for this board uses RK_PC6 with a pull-up. With the fix the alarm
> IRQ fires at runtime and the RTC wakes the SoC from s2idle. Note that on this
> board the resume itself can still stall later in the USB 2.0 host controllers
> (a separate, unrelated issue being looked at); it does not affect this fix.
> 
>  arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
> index 145986695720..572b892e4066 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
> @@ -189,7 +189,7 @@ &hdptxphy1 {
>  
>  &hym8563 {
>  	interrupt-parent = <&gpio0>;
> -	interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
> +	interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>;
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&hym8563_int>;
>  };
> @@ -298,7 +298,7 @@ hdmi1_tx_on_h: hdmi1-tx-on-h {
>  
>  	hym8563 {
>  		hym8563_int: hym8563-int {
> -			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
> +			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;

Schematic already shows a pullup, so this should not be needed:

  https://xff.cz/dl/tmp/2995ddec50ce4597.png

Other than that,

Reviewed-by: Ondrej Jirman <megi@xff.cz>

Thank you,
	o.

>  		};
>  	};
>  
> 
> base-commit: 1fc5a74b108fc90951890ec513ac81869f5eaff1
> -- 
> 2.43.0
> 

^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2026-09-08  0:11 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
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2026-09-06 18:16 [PATCH] arm64: dts: rockchip: fix hym8563 interrupt pin on Orange Pi 5 Plus Igor Paunovic
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