From: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Suresh Vankadara <svankada@qti.qualcomm.com>,
Vikram Sharma <vikram.sharma@oss.qualcomm.com>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
Subject: [PATCH 2/6] arm64: dts: qcom: glymur: Add CCI definitions for Glymur
Date: Mon, 07 Sep 2026 15:37:45 +0530 [thread overview]
Message-ID: <20260907-glymur_camss_dts-v1-2-6c2ced5ea5f9@oss.qualcomm.com> (raw)
In-Reply-To: <20260907-glymur_camss_dts-v1-0-6c2ced5ea5f9@oss.qualcomm.com>
Qualcomm Glymur SoC has two Camera Control Interface (CCI)
controllers. Each controller contains two I2C hosts.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 202 +++++++++++++++++++++++++++++++++++
1 file changed, 202 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index c463cde46cc41acd7b8091616657bf49b38b7f9f..4c48df593d1834a6ee7d97c9981965f557cad16c 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -1886,6 +1886,80 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
};
};
+ cci0: cci@ac15000 {
+ compatible = "qcom,glymur-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0ac15000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 456 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>;
+ clock-names = "ahb",
+ "cci";
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ pinctrl-0 = <&cci0_0_default>, <&cci0_1_default>;
+ pinctrl-1 = <&cci0_0_sleep>, <&cci0_1_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac16000 {
+ compatible = "qcom,glymur-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0ac16000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 859 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>;
+ clock-names = "ahb",
+ "cci";
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ pinctrl-0 = <&cci1_0_default>, <&cci1_1_default>;
+ pinctrl-1 = <&cci1_0_sleep>, <&cci1_1_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
camss: isp@acb6000 {
compatible = "qcom,glymur-camss";
@@ -7015,6 +7089,134 @@ rx-pins {
bias-disable;
};
};
+
+ cci0_0_default: cci0-0-default-state {
+ sda-pins {
+ pins = "gpio101";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ pins = "gpio102";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ cci0_0_sleep: cci0-0-sleep-state {
+ sda-pins {
+ pins = "gpio101";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio102";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci0_1_default: cci0-1-default-state {
+ sda-pins {
+ pins = "gpio103";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ pins = "gpio104";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ cci0_1_sleep: cci0-1-sleep-state {
+ sda-pins {
+ pins = "gpio103";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio104";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_0_default: cci1-0-default-state {
+ sda-pins {
+ pins = "gpio105";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ pins = "gpio106";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ cci1_0_sleep: cci1-0-sleep-state {
+ sda-pins {
+ pins = "gpio105";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio106";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_1_default: cci1-1-default-state {
+ sda-pins {
+ pins = "gpio235";
+ function = "asc_cci";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ pins = "gpio236";
+ function = "asc_cci";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ cci1_1_sleep: cci1-1-sleep-state {
+ sda-pins {
+ pins = "gpio235";
+ function = "asc_cci";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio236";
+ function = "asc_cci";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
};
ctcu@10001000 {
--
2.34.1
next prev parent reply other threads:[~2026-09-07 10:08 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-07 10:07 [PATCH 0/6] Add CCI and CAMSS support " Nihal Kumar Gupta
2026-09-07 10:07 ` [PATCH 1/6] arm64: dts: qcom: glymur: Add CAMSS and CSIPHY nodes " Nihal Kumar Gupta
2026-09-14 14:10 ` Konrad Dybcio
2026-09-07 10:07 ` Nihal Kumar Gupta [this message]
2026-09-07 10:47 ` [PATCH 2/6] arm64: dts: qcom: glymur: Add CCI definitions " Abel Vesa
2026-09-07 10:07 ` [PATCH 3/6] arm64: dts: qcom: glymur: Add camera MCLK pinctrl Nihal Kumar Gupta
2026-09-07 10:47 ` Abel Vesa
2026-09-07 10:07 ` [PATCH 4/6] arm64: dts: qcom: glymur-crd: Add PM8010 camera PMIC Nihal Kumar Gupta
2026-09-07 10:07 ` [PATCH 5/6] arm64: dts: qcom: glymur-crd: Add ov08x40 RGB sensor on CSIPHY4 Nihal Kumar Gupta
2026-09-07 10:47 ` Abel Vesa
2026-09-07 10:07 ` [PATCH 6/6] arm64: defconfig: Enable OV08X40 camera sensor driver Nihal Kumar Gupta
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260907-glymur_camss_dts-v1-2-6c2ced5ea5f9@oss.qualcomm.com \
--to=nihal.gupta@oss.qualcomm.com \
--cc=andersson@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=konrad.dybcio@oss.qualcomm.com \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robh@kernel.org \
--cc=svankada@qti.qualcomm.com \
--cc=vikram.sharma@oss.qualcomm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®