[PATCH net] net: dsa: realtek: rtl8365mb: let the SerDes PLL settle after the data-path reset

[PATCH net] net: dsa: realtek: rtl8365mb: let the SerDes PLL settle after the data-path reset

[Stanislaw Pal]

The vendor DW8051 firmware waits ~98 ms after the BMCR data-path reset
(constant SGMII_TIMEOUT_98MS in Sgmii_Init[]) before any further SerDes
register access, giving the SerDes PLL and analog front-end time to
settle. Without the wait the SGMII link on the RTL8367S can come up
half-alive on cold boot: carrier up and RX passing traffic, TX
permanently dead (measured on a TP-Link Archer AX55 v1, IPQ5018).

Fixes: 0b577e2fe06c ("net: dsa: realtek: rtl8365mb: add SGMII support for RTL8367S")
Suggested-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Signed-off-by: Stanislaw Pal <kuncy7@gmail.com>
---
--- a/drivers/net/dsa/realtek/rtl8365mb_main.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_main.c
@@ -1408,6 +1408,14 @@ static int rtl8365mb_pcs_config(struct p
 	if (ret)
 		return ret;
 
+	/* The vendor DW8051 firmware waits ~98 ms after the data-path reset
+	 * (SGMII_TIMEOUT_98MS in Sgmii_Init[]) for the SerDes PLL and analog
+	 * front-end to settle before any further SerDes register access.
+	 * Without the wait the link can come up half-alive on cold boot:
+	 * carrier and RX fine, TX permanently dead.
+	 */
+	msleep(98);
+
 	/* Keep SGMII in-band autonegotiation disabled: the link parameters are
 	 * forced from rtl8365mb_pcs_link_up() instead.
 	 */

Re: [PATCH net] net: dsa: realtek: rtl8365mb: let the SerDes PLL settle after the data-path reset

[Stanislaw Pal]

Withdrawing this one.

The evidence behind it came entirely from a single Archer AX55 v1, and
it was never separated from the chip-reset patch it was sent alongside:
the cold-boot counts I quoted were measured with both applied, as Johan
pointed out on the OpenWrt side. Since then the case for trusting that
board has got weaker rather than stronger. It is four years old, it has
one confirmed power supply fault behind it, its cold-boot behaviour
differs from its warm-boot behaviour in a way Alvin rightly reads as
out-of-spec supplies, and Johan cannot reproduce anything like it on an
MR80X v2.20 with the same IPQ5018 and RTL8367S.

The 98 ms wait may still be right - the vendor firmware does take it,
and the constant is in the vendor SerDes init table - but "the vendor
does it" is not on its own a reason to put a delay in a driver, and I
have nothing else left to offer for it.

If someone reproduces a half-alive SGMII link on hardware that is not
suspect, this is easy to bring back.

The chip-reset patch is respun separately as v3, retargeted at net-next
and without the Fixes tag, for reasons set out there:
https://lore.kernel.org/all/20260908174403.420507-1-kuncy7@gmail.com/

Sorry for the noise, and thanks to all of you for the time on it.

Best regards,
Stanislaw