* [PATCH 01/13] ARM: remove sa1100 platform
2026-09-08 15:27 [PATCH 00/13] ARM: deprecated platform removal Arnd Bergmann
@ 2026-09-08 15:27 ` Arnd Bergmann
2026-09-08 16:26 ` Guenter Roeck
` (3 more replies)
2026-09-08 15:27 ` [PATCH 02/13] ARM: remove footbridge Arnd Bergmann
` (12 subsequent siblings)
13 siblings, 4 replies; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 15:27 UTC (permalink / raw)
To: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Guenter Roeck
From: Arnd Bergmann <arnd@arndb.de>
Most sa1100 platforms were removed a few years, with the remaining
ones left as a starting point for a conversion to devicetree.
Nothing ever happened on that front, so remove the rest now,
including the sa1111 and locomo drivers that were once shared
with pxa but are already sa1100-exclusive now.
Cc: Russell King <linux@armlinux.org.uk>
Cc: Linus Walleij <linusw@kernel.org>
Cc: Kristoffer Ericson <kristoffer.ericson@gmail.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Ethan Nelson-Moore <enelsonmoore@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
Documentation/arch/arm/index.rst | 3 -
Documentation/arch/arm/sa1100/assabet.rst | 301 ---
Documentation/arch/arm/sa1100/cerf.rst | 35 -
Documentation/arch/arm/sa1100/index.rst | 13 -
Documentation/arch/arm/sa1100/lart.rst | 15 -
Documentation/arch/arm/sa1100/serial_uart.rst | 51 -
MAINTAINERS | 8 -
arch/arm/Kconfig | 16 +-
arch/arm/Kconfig.debug | 13 +-
arch/arm/Makefile | 6 -
arch/arm/boot/bootp/Makefile | 1 -
arch/arm/boot/compressed/Makefile | 4 -
arch/arm/boot/compressed/head-sa1100.S | 45 -
arch/arm/boot/compressed/head.S | 7 -
arch/arm/common/Kconfig | 7 -
arch/arm/common/Makefile | 2 -
arch/arm/common/locomo.c | 886 --------
arch/arm/common/sa1111.c | 1413 -------------
arch/arm/configs/assabet_defconfig | 57 -
arch/arm/configs/collie_defconfig | 87 -
arch/arm/configs/h3600_defconfig | 63 -
arch/arm/configs/jornada720_defconfig | 95 -
arch/arm/configs/neponset_defconfig | 88 -
arch/arm/include/asm/cputype.h | 4 -
arch/arm/include/asm/hardware/locomo.h | 217 --
arch/arm/include/asm/hardware/sa1111.h | 442 ----
arch/arm/include/asm/hardware/ssp.h | 25 -
arch/arm/include/debug/sa1100.S | 67 -
arch/arm/mach-sa1100/Kconfig | 92 -
arch/arm/mach-sa1100/Makefile | 20 -
arch/arm/mach-sa1100/assabet.c | 770 -------
arch/arm/mach-sa1100/clock.c | 145 --
arch/arm/mach-sa1100/collie.c | 447 ----
arch/arm/mach-sa1100/generic.c | 470 -----
arch/arm/mach-sa1100/generic.h | 58 -
arch/arm/mach-sa1100/h3600.c | 134 --
arch/arm/mach-sa1100/h3xxx.c | 305 ---
arch/arm/mach-sa1100/include/mach/SA-1100.h | 1798 -----------------
arch/arm/mach-sa1100/include/mach/assabet.h | 99 -
arch/arm/mach-sa1100/include/mach/bitfield.h | 113 --
arch/arm/mach-sa1100/include/mach/collie.h | 94 -
arch/arm/mach-sa1100/include/mach/generic.h | 1 -
arch/arm/mach-sa1100/include/mach/h3xxx.h | 81 -
arch/arm/mach-sa1100/include/mach/hardware.h | 56 -
arch/arm/mach-sa1100/include/mach/irqs.h | 101 -
.../arm/mach-sa1100/include/mach/jornada720.h | 28 -
arch/arm/mach-sa1100/include/mach/memory.h | 37 -
arch/arm/mach-sa1100/include/mach/mtd-xip.h | 23 -
arch/arm/mach-sa1100/include/mach/neponset.h | 31 -
arch/arm/mach-sa1100/include/mach/reset.h | 18 -
.../arm/mach-sa1100/include/mach/uncompress.h | 52 -
arch/arm/mach-sa1100/jornada720.c | 380 ----
arch/arm/mach-sa1100/jornada720_ssp.c | 202 --
arch/arm/mach-sa1100/neponset.c | 438 ----
arch/arm/mach-sa1100/pm.c | 128 --
arch/arm/mach-sa1100/sleep.S | 143 --
arch/arm/mach-sa1100/ssp.c | 240 ---
arch/arm/mm/init.c | 5 -
arch/arm/mm/mmu.c | 8 -
drivers/rtc/Kconfig | 4 +-
drivers/rtc/rtc-sa1100.c | 16 +-
drivers/watchdog/Kconfig | 12 +-
62 files changed, 19 insertions(+), 10501 deletions(-)
delete mode 100644 Documentation/arch/arm/sa1100/assabet.rst
delete mode 100644 Documentation/arch/arm/sa1100/cerf.rst
delete mode 100644 Documentation/arch/arm/sa1100/index.rst
delete mode 100644 Documentation/arch/arm/sa1100/lart.rst
delete mode 100644 Documentation/arch/arm/sa1100/serial_uart.rst
delete mode 100644 arch/arm/boot/compressed/head-sa1100.S
delete mode 100644 arch/arm/common/locomo.c
delete mode 100644 arch/arm/common/sa1111.c
delete mode 100644 arch/arm/configs/assabet_defconfig
delete mode 100644 arch/arm/configs/collie_defconfig
delete mode 100644 arch/arm/configs/h3600_defconfig
delete mode 100644 arch/arm/configs/jornada720_defconfig
delete mode 100644 arch/arm/configs/neponset_defconfig
delete mode 100644 arch/arm/include/asm/hardware/locomo.h
delete mode 100644 arch/arm/include/asm/hardware/sa1111.h
delete mode 100644 arch/arm/include/asm/hardware/ssp.h
delete mode 100644 arch/arm/include/debug/sa1100.S
delete mode 100644 arch/arm/mach-sa1100/Kconfig
delete mode 100644 arch/arm/mach-sa1100/Makefile
delete mode 100644 arch/arm/mach-sa1100/assabet.c
delete mode 100644 arch/arm/mach-sa1100/clock.c
delete mode 100644 arch/arm/mach-sa1100/collie.c
delete mode 100644 arch/arm/mach-sa1100/generic.c
delete mode 100644 arch/arm/mach-sa1100/generic.h
delete mode 100644 arch/arm/mach-sa1100/h3600.c
delete mode 100644 arch/arm/mach-sa1100/h3xxx.c
delete mode 100644 arch/arm/mach-sa1100/include/mach/SA-1100.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/assabet.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/bitfield.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/collie.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/generic.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/h3xxx.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/hardware.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/irqs.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/jornada720.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/memory.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/mtd-xip.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/neponset.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/reset.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/uncompress.h
delete mode 100644 arch/arm/mach-sa1100/jornada720.c
delete mode 100644 arch/arm/mach-sa1100/jornada720_ssp.c
delete mode 100644 arch/arm/mach-sa1100/neponset.c
delete mode 100644 arch/arm/mach-sa1100/pm.c
delete mode 100644 arch/arm/mach-sa1100/sleep.S
delete mode 100644 arch/arm/mach-sa1100/ssp.c
diff --git a/Documentation/arch/arm/index.rst b/Documentation/arch/arm/index.rst
index b15621093f7a..a292b8ac41ce 100644
--- a/Documentation/arch/arm/index.rst
+++ b/Documentation/arch/arm/index.rst
@@ -48,9 +48,6 @@ SoC-specific documents
pxa/mfp
-
- sa1100/index
-
stm32/stm32f746-overview
stm32/overview
stm32/stm32h743-overview
diff --git a/Documentation/arch/arm/sa1100/assabet.rst b/Documentation/arch/arm/sa1100/assabet.rst
deleted file mode 100644
index a761e128fb08..000000000000
--- a/Documentation/arch/arm/sa1100/assabet.rst
+++ /dev/null
@@ -1,301 +0,0 @@
-============================================
-The Intel Assabet (SA-1110 evaluation) board
-============================================
-
-Please see:
-http://developer.intel.com
-
-Also some notes from John G Dorsey <jd5q@andrew.cmu.edu>:
-http://www.cs.cmu.edu/~wearable/software/assabet.html
-
-
-Building the kernel
--------------------
-
-To build the kernel with current defaults::
-
- make assabet_defconfig
- make oldconfig
- make zImage
-
-The resulting kernel image should be available in linux/arch/arm/boot/zImage.
-
-
-Installing a bootloader
------------------------
-
-A couple of bootloaders able to boot Linux on Assabet are available:
-
-BLOB (http://www.lartmaker.nl/lartware/blob/)
-
- BLOB is a bootloader used within the LART project. Some contributed
- patches were merged into BLOB to add support for Assabet.
-
-Compaq's Bootldr + John Dorsey's patch for Assabet support
-(http://www.handhelds.org/Compaq/bootldr.html)
-(http://www.wearablegroup.org/software/bootldr/)
-
- Bootldr is the bootloader developed by Compaq for the iPAQ Pocket PC.
- John Dorsey has produced add-on patches to add support for Assabet and
- the JFFS filesystem.
-
-RedBoot (http://sources.redhat.com/redboot/)
-
- RedBoot is a bootloader developed by Red Hat based on the eCos RTOS
- hardware abstraction layer. It supports Assabet amongst many other
- hardware platforms.
-
-RedBoot is currently the recommended choice since it's the only one to have
-networking support, and is the most actively maintained.
-
-Brief examples on how to boot Linux with RedBoot are shown below. But first
-you need to have RedBoot installed in your flash memory. A known to work
-precompiled RedBoot binary is available from the following location:
-
-- ftp://ftp.netwinder.org/users/n/nico/
-- ftp://ftp.arm.linux.org.uk/pub/linux/arm/people/nico/
-- ftp://ftp.handhelds.org/pub/linux/arm/sa-1100-patches/
-
-Look for redboot-assabet*.tgz. Some installation infos are provided in
-redboot-assabet*.txt.
-
-
-Initial RedBoot configuration
------------------------------
-
-The commands used here are explained in The RedBoot User's Guide available
-on-line at http://sources.redhat.com/ecos/docs.html.
-Please refer to it for explanations.
-
-If you have a CF network card (my Assabet kit contained a CF+ LP-E from
-Socket Communications Inc.), you should strongly consider using it for TFTP
-file transfers. You must insert it before RedBoot runs since it can't detect
-it dynamically.
-
-To initialize the flash directory::
-
- fis init -f
-
-To initialize the non-volatile settings, like whether you want to use BOOTP or
-a static IP address, etc, use this command::
-
- fconfig -i
-
-
-Writing a kernel image into flash
----------------------------------
-
-First, the kernel image must be loaded into RAM. If you have the zImage file
-available on a TFTP server::
-
- load zImage -r -b 0x100000
-
-If you rather want to use Y-Modem upload over the serial port::
-
- load -m ymodem -r -b 0x100000
-
-To write it to flash::
-
- fis create "Linux kernel" -b 0x100000 -l 0xc0000
-
-
-Booting the kernel
-------------------
-
-The kernel still requires a filesystem to boot. A ramdisk image can be loaded
-as follows::
-
- load ramdisk_image.gz -r -b 0x800000
-
-Again, Y-Modem upload can be used instead of TFTP by replacing the file name
-by '-y ymodem'.
-
-Now the kernel can be retrieved from flash like this::
-
- fis load "Linux kernel"
-
-or loaded as described previously. To boot the kernel::
-
- exec -b 0x100000 -l 0xc0000
-
-The ramdisk image could be stored into flash as well, but there are better
-solutions for on-flash filesystems as mentioned below.
-
-
-Using JFFS2
------------
-
-Using JFFS2 (the Second Journalling Flash File System) is probably the most
-convenient way to store a writable filesystem into flash. JFFS2 is used in
-conjunction with the MTD layer which is responsible for low-level flash
-management. More information on the Linux MTD can be found on-line at:
-http://www.linux-mtd.infradead.org/. A JFFS howto with some infos about
-creating JFFS/JFFS2 images is available from the same site.
-
-For instance, a sample JFFS2 image can be retrieved from the same FTP sites
-mentioned below for the precompiled RedBoot image.
-
-To load this file::
-
- load sample_img.jffs2 -r -b 0x100000
-
-The result should look like::
-
- RedBoot> load sample_img.jffs2 -r -b 0x100000
- Raw file loaded 0x00100000-0x00377424
-
-Now we must know the size of the unallocated flash::
-
- fis free
-
-Result::
-
- RedBoot> fis free
- 0x500E0000 .. 0x503C0000
-
-The values above may be different depending on the size of the filesystem and
-the type of flash. See their usage below as an example and take care of
-substituting yours appropriately.
-
-We must determine some values::
-
- size of unallocated flash: 0x503c0000 - 0x500e0000 = 0x2e0000
- size of the filesystem image: 0x00377424 - 0x00100000 = 0x277424
-
-We want to fit the filesystem image of course, but we also want to give it all
-the remaining flash space as well. To write it::
-
- fis unlock -f 0x500E0000 -l 0x2e0000
- fis erase -f 0x500E0000 -l 0x2e0000
- fis write -b 0x100000 -l 0x277424 -f 0x500E0000
- fis create "JFFS2" -n -f 0x500E0000 -l 0x2e0000
-
-Now the filesystem is associated to a MTD "partition" once Linux has discovered
-what they are in the boot process. From Redboot, the 'fis list' command
-displays them::
-
- RedBoot> fis list
- Name FLASH addr Mem addr Length Entry point
- RedBoot 0x50000000 0x50000000 0x00020000 0x00000000
- RedBoot config 0x503C0000 0x503C0000 0x00020000 0x00000000
- FIS directory 0x503E0000 0x503E0000 0x00020000 0x00000000
- Linux kernel 0x50020000 0x00100000 0x000C0000 0x00000000
- JFFS2 0x500E0000 0x500E0000 0x002E0000 0x00000000
-
-However Linux should display something like::
-
- SA1100 flash: probing 32-bit flash bus
- SA1100 flash: Found 2 x16 devices at 0x0 in 32-bit mode
- Using RedBoot partition definition
- Creating 5 MTD partitions on "SA1100 flash":
- 0x00000000-0x00020000 : "RedBoot"
- 0x00020000-0x000e0000 : "Linux kernel"
- 0x000e0000-0x003c0000 : "JFFS2"
- 0x003c0000-0x003e0000 : "RedBoot config"
- 0x003e0000-0x00400000 : "FIS directory"
-
-What's important here is the position of the partition we are interested in,
-which is the third one. Within Linux, this correspond to /dev/mtdblock2.
-Therefore to boot Linux with the kernel and its root filesystem in flash, we
-need this RedBoot command::
-
- fis load "Linux kernel"
- exec -b 0x100000 -l 0xc0000 -c "root=/dev/mtdblock2"
-
-Of course other filesystems than JFFS might be used, like cramfs for example.
-You might want to boot with a root filesystem over NFS, etc. It is also
-possible, and sometimes more convenient, to flash a filesystem directly from
-within Linux while booted from a ramdisk or NFS. The Linux MTD repository has
-many tools to deal with flash memory as well, to erase it for example. JFFS2
-can then be mounted directly on a freshly erased partition and files can be
-copied over directly. Etc...
-
-
-RedBoot scripting
------------------
-
-All the commands above aren't so useful if they have to be typed in every
-time the Assabet is rebooted. Therefore it's possible to automate the boot
-process using RedBoot's scripting capability.
-
-For example, I use this to boot Linux with both the kernel and the ramdisk
-images retrieved from a TFTP server on the network::
-
- RedBoot> fconfig
- Run script at boot: false true
- Boot script:
- Enter script, terminate with empty line
- >> load zImage -r -b 0x100000
- >> load ramdisk_ks.gz -r -b 0x800000
- >> exec -b 0x100000 -l 0xc0000
- >>
- Boot script timeout (1000ms resolution): 3
- Use BOOTP for network configuration: true
- GDB connection port: 9000
- Network debug at boot time: false
- Update RedBoot non-volatile configuration - are you sure (y/n)? y
-
-Then, rebooting the Assabet is just a matter of waiting for the login prompt.
-
-
-
-Nicolas Pitre
-nico@fluxnic.net
-
-June 12, 2001
-
-
-Status of peripherals in -rmk tree (updated 14/10/2001)
--------------------------------------------------------
-
-Assabet:
- Serial ports:
- Radio: TX, RX, CTS, DSR, DCD, RI
- - PM: Not tested.
- - COM: TX, RX, CTS, DSR, DCD, RTS, DTR, PM
- - PM: Not tested.
- - I2C: Implemented, not fully tested.
- - L3: Fully tested, pass.
- - PM: Not tested.
-
- Video:
- - LCD: Fully tested. PM
-
- (LCD doesn't like being blanked with neponset connected)
-
- - Video out: Not fully
-
- Audio:
- UDA1341:
- - Playback: Fully tested, pass.
- - Record: Implemented, not tested.
- - PM: Not tested.
-
- UCB1200:
- - Audio play: Implemented, not heavily tested.
- - Audio rec: Implemented, not heavily tested.
- - Telco audio play: Implemented, not heavily tested.
- - Telco audio rec: Implemented, not heavily tested.
- - POTS control: No
- - Touchscreen: Yes
- - PM: Not tested.
-
- Other:
- - PCMCIA:
- - LPE: Fully tested, pass.
- - USB: No
- - IRDA:
- - SIR: Fully tested, pass.
- - FIR: Fully tested, pass.
- - PM: Not tested.
-
-Neponset:
- Serial ports:
- - COM1,2: TX, RX, CTS, DSR, DCD, RTS, DTR
- - PM: Not tested.
- - USB: Implemented, not heavily tested.
- - PCMCIA: Implemented, not heavily tested.
- - CF: Implemented, not heavily tested.
- - PM: Not tested.
-
-More stuff can be found in the -np (Nicolas Pitre's) tree.
diff --git a/Documentation/arch/arm/sa1100/cerf.rst b/Documentation/arch/arm/sa1100/cerf.rst
deleted file mode 100644
index 7fa71b609bf9..000000000000
--- a/Documentation/arch/arm/sa1100/cerf.rst
+++ /dev/null
@@ -1,35 +0,0 @@
-==============
-CerfBoard/Cube
-==============
-
-*** The StrongARM version of the CerfBoard/Cube has been discontinued ***
-
-The Intrinsyc CerfBoard is a StrongARM 1110-based computer on a board
-that measures approximately 2" square. It includes an Ethernet
-controller, an RS232-compatible serial port, a USB function port, and
-one CompactFlash+ slot on the back. Pictures can be found at the
-Intrinsyc website, http://www.intrinsyc.com.
-
-This document describes the support in the Linux kernel for the
-Intrinsyc CerfBoard.
-
-Supported in this version
-=========================
-
- - CompactFlash+ slot (select PCMCIA in General Setup and any options
- that may be required)
- - Onboard Crystal CS8900 Ethernet controller (Cerf CS8900A support in
- Network Devices)
- - Serial ports with a serial console (hardcoded to 38400 8N1)
-
-In order to get this kernel onto your Cerf, you need a server that runs
-both BOOTP and TFTP. Detailed instructions should have come with your
-evaluation kit on how to use the bootloader. This series of commands
-will suffice::
-
- make ARCH=arm CROSS_COMPILE=arm-linux- cerfcube_defconfig
- make ARCH=arm CROSS_COMPILE=arm-linux- zImage
- make ARCH=arm CROSS_COMPILE=arm-linux- modules
- cp arch/arm/boot/zImage <TFTP directory>
-
-support@intrinsyc.com
diff --git a/Documentation/arch/arm/sa1100/index.rst b/Documentation/arch/arm/sa1100/index.rst
deleted file mode 100644
index c9aed43280ff..000000000000
--- a/Documentation/arch/arm/sa1100/index.rst
+++ /dev/null
@@ -1,13 +0,0 @@
-.. SPDX-License-Identifier: GPL-2.0
-
-====================
-Intel StrongARM 1100
-====================
-
-.. toctree::
- :maxdepth: 1
-
- assabet
- cerf
- lart
- serial_uart
diff --git a/Documentation/arch/arm/sa1100/lart.rst b/Documentation/arch/arm/sa1100/lart.rst
deleted file mode 100644
index 94c0568d1095..000000000000
--- a/Documentation/arch/arm/sa1100/lart.rst
+++ /dev/null
@@ -1,15 +0,0 @@
-====================================
-Linux Advanced Radio Terminal (LART)
-====================================
-
-The LART is a small (7.5 x 10cm) SA-1100 board, designed for embedded
-applications. It has 32 MB DRAM, 4MB Flash ROM, double RS232 and all
-other StrongARM-gadgets. Almost all SA signals are directly accessible
-through a number of connectors. The powersupply accepts voltages
-between 3.5V and 16V and is overdimensioned to support a range of
-daughterboards. A quad Ethernet / IDE / PS2 / sound daughterboard
-is under development, with plenty of others in different stages of
-planning.
-
-The hardware designs for this board have been released under an open license;
-see the LART page at http://www.lartmaker.nl/ for more information.
diff --git a/Documentation/arch/arm/sa1100/serial_uart.rst b/Documentation/arch/arm/sa1100/serial_uart.rst
deleted file mode 100644
index ea983642b9be..000000000000
--- a/Documentation/arch/arm/sa1100/serial_uart.rst
+++ /dev/null
@@ -1,51 +0,0 @@
-==================
-SA1100 serial port
-==================
-
-The SA1100 serial port had its major/minor numbers officially assigned::
-
- > Date: Sun, 24 Sep 2000 21:40:27 -0700
- > From: H. Peter Anvin <hpa@transmeta.com>
- > To: Nicolas Pitre <nico@CAM.ORG>
- > Cc: Device List Maintainer <device@lanana.org>
- > Subject: Re: device
- >
- > Okay. Note that device numbers 204 and 205 are used for "low density
- > serial devices", so you will have a range of minors on those majors (the
- > tty device layer handles this just fine, so you don't have to worry about
- > doing anything special.)
- >
- > So your assignments are:
- >
- > 204 char Low-density serial ports
- > 5 = /dev/ttySA0 SA1100 builtin serial port 0
- > 6 = /dev/ttySA1 SA1100 builtin serial port 1
- > 7 = /dev/ttySA2 SA1100 builtin serial port 2
- >
- > 205 char Low-density serial ports (alternate device)
- > 5 = /dev/cusa0 Callout device for ttySA0
- > 6 = /dev/cusa1 Callout device for ttySA1
- > 7 = /dev/cusa2 Callout device for ttySA2
- >
-
-You must create those inodes in /dev on the root filesystem used
-by your SA1100-based device::
-
- mknod ttySA0 c 204 5
- mknod ttySA1 c 204 6
- mknod ttySA2 c 204 7
- mknod cusa0 c 205 5
- mknod cusa1 c 205 6
- mknod cusa2 c 205 7
-
-In addition to the creation of the appropriate device nodes above, you
-must ensure your user space applications make use of the correct device
-name. The classic example is the content of the /etc/inittab file where
-you might have a getty process started on ttyS0.
-
-In this case:
-
-- replace occurrences of ttyS0 with ttySA0, ttyS1 with ttySA1, etc.
-
-- don't forget to add 'ttySA0', 'console', or the appropriate tty name
- in /etc/securetty for root to be allowed to login as well.
diff --git a/MAINTAINERS b/MAINTAINERS
index 6215fcb07770..fd213c4bc257 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2977,14 +2977,6 @@ F: arch/arm/boot/dts/hisilicon/
F: arch/arm/mach-hisi/
F: arch/arm64/boot/dts/hisilicon/
-ARM/HP JORNADA 7XX MACHINE SUPPORT
-M: Kristoffer Ericson <kristoffer.ericson@gmail.com>
-S: Maintained
-W: www.jlime.com
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/kristoffer/linux-hpc.git
-F: arch/arm/mach-sa1100/include/mach/jornada720.h
-F: arch/arm/mach-sa1100/jornada720.c
-
ARM/HPE GXP ARCHITECTURE
M: Jean-Marie Verdun <verdun@hpe.com>
M: Nick Hawkins <nick.hawkins@hpe.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ffbc7f386131..7f4c2973d630 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -161,7 +161,7 @@ config ARM
select TIMER_OF if OF
select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
- select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
+ select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC)
# Above selects are sorted alphabetically; please add new ones
# according to that. Thanks.
help
@@ -261,9 +261,6 @@ config GENERIC_ISA_DMA
config FIQ
bool
-config ARCH_MTD_XIP
- bool
-
config ARM_PATCH_PHYS_VIRT
bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM
default y
@@ -301,7 +298,7 @@ config PHYS_OFFSET
default 0x00000000 if ARCH_FOOTBRIDGE
default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
default 0xa0000000 if ARCH_PXA
- default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
+ default 0xc0000000 if ARCH_EP93XX
default 0
help
Please provide the physical address corresponding to the
@@ -341,7 +338,7 @@ config ARCH_MMAP_RND_BITS_MAX
config ARCH_MULTIPLATFORM
bool "Require kernel to be portable to multiple machines" if EXPERT
- depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
+ depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC)
default y
help
In general, all Arm machines can be supported in a single
@@ -445,8 +442,6 @@ source "arch/arm/mach-s3c/Kconfig"
source "arch/arm/mach-s5pv210/Kconfig"
-source "arch/arm/mach-sa1100/Kconfig"
-
source "arch/arm/mach-shmobile/Kconfig"
source "arch/arm/mach-socfpga/Kconfig"
@@ -1201,7 +1196,7 @@ config ARCH_SELECT_MEMORY_MODEL
def_bool y
config ARCH_FLATMEM_ENABLE
- def_bool !(ARCH_RPC || ARCH_SA1100)
+ def_bool !ARCH_RPC
config ARCH_SPARSEMEM_ENABLE
def_bool !ARCH_FOOTBRIDGE
@@ -1293,7 +1288,6 @@ config ARM_MODULE_PLTS
config ARCH_FORCE_MAX_ORDER
int "Order of maximal physically contiguous allocations"
default "11" if SOC_AM33XX
- default "8" if SA1111
default "10"
help
The kernel page allocator limits the size of maximal physically
@@ -1605,7 +1599,7 @@ config ARCH_DEFAULT_CRASH_DUMP
config AUTO_ZRELADDR
bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM
- default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
+ default !(ARCH_FOOTBRIDGE || ARCH_RPC)
help
ZRELADDR is the physical address where the decompressed kernel
image will be placed. If AUTO_ZRELADDR is selected, the address
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 366f162e147d..ad0feced4369 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1048,14 +1048,6 @@ choice
their output to UART 3. The port must have been initialised
by the boot-loader before use.
- config DEBUG_SA1100
- depends on ARCH_SA1100
- bool "Use SA1100 UARTs for low-level debug"
- help
- Say Y here if you want kernel low-level debugging support
- on SA-11x0 UART ports. The kernel will check for the first
- enabled UART in a sequence 3-1-2.
-
config DEBUG_SD5203_UART
bool "Hisilicon SD5203 Debug UART"
depends on ARCH_SD5203
@@ -1479,7 +1471,6 @@ config DEBUG_UART_FLOW_CONTROL
config DEBUG_LL_INCLUDE
string
- default "debug/sa1100.S" if DEBUG_SA1100
default "debug/palmchip.S" if DEBUG_UART_8250_PALMCHIP
default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250
default "debug/at91.S" if DEBUG_AT91_UART
@@ -1807,7 +1798,7 @@ config DEBUG_UART_8250_PALMCHIP
config DEBUG_UNCOMPRESS
bool "Enable decompressor debugging via DEBUG_LL output"
depends on !ARCH_MULTIPLATFORM
- depends on !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
+ depends on !(ARCH_FOOTBRIDGE || ARCH_RPC)
depends on DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
(!DEBUG_TEGRA_UART || !ZBOOT_ROM) && \
!DEBUG_BRCMSTB_UART && !DEBUG_SEMIHOSTING
@@ -1817,7 +1808,7 @@ config DEBUG_UNCOMPRESS
config UNCOMPRESS_INCLUDE
string
- default "mach/uncompress.h" if ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100
+ default "mach/uncompress.h" if ARCH_FOOTBRIDGE || ARCH_RPC
default "debug/uncompress.h"
config EARLY_PRINTK
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 573813ef5e77..ea3da21202c8 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -162,10 +162,6 @@ CHECKFLAGS += -D__arm__
textofs-y := 0x00008000
# RTD1195 has Boot ROM at start of address space
textofs-$(CONFIG_ARCH_REALTEK) := 0x00108000
-# SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory
-ifeq ($(CONFIG_ARCH_SA1100),y)
-textofs-$(CONFIG_SA1111) := 0x00208000
-endif
textofs-$(CONFIG_ARCH_QCOM_RESERVE_SMEM) := 0x00208000
textofs-$(CONFIG_ARCH_MESON) := 0x00208000
textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
@@ -214,7 +210,6 @@ machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_ARCH_RPC) += rpc
machine-$(CONFIG_PLAT_SAMSUNG) += s3c
machine-$(CONFIG_ARCH_S5PV210) += s5pv210
-machine-$(CONFIG_ARCH_SA1100) += sa1100
machine-$(CONFIG_ARCH_RENESAS) += shmobile
machine-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_STI) += sti
@@ -232,7 +227,6 @@ machine-$(CONFIG_PLAT_SPEAR) += spear
# these three are mutually exclusive
machdirs-$(CONFIG_ARCH_FOOTBRIDGE) += arch/arm/mach-footbridge
machdirs-$(CONFIG_ARCH_RPC) += arch/arm/mach-rpc
-machdirs-$(CONFIG_ARCH_SA1100) += arch/arm/mach-sa1100
KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%/include,$(machdirs-y))
# The byte offset of the kernel image in RAM from the start of RAM.
diff --git a/arch/arm/boot/bootp/Makefile b/arch/arm/boot/bootp/Makefile
index f3443f7d7b02..a1a1f4bec783 100644
--- a/arch/arm/boot/bootp/Makefile
+++ b/arch/arm/boot/bootp/Makefile
@@ -20,7 +20,6 @@ PARAMS_PHYS := $(call add_hex, $(PHYS_OFFSET), 0x100)
# guess an initrd location if possible
initrd_offset-$(CONFIG_ARCH_FOOTBRIDGE) += 0x00800000
-initrd_offset-$(CONFIG_ARCH_SA1100) += 0x00800000
initrd_offset-$(CONFIG_ARCH_RPC) += 0x08000000
INITRD_OFFSET := $(initrd_offset-y)
ifdef INITRD_OFFSET
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index e3f550d62857..d8d81ba741a2 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -29,10 +29,6 @@ ifeq ($(CONFIG_ARCH_ACORN),y)
OBJS += ll_char_wr.o font.o
endif
-ifeq ($(CONFIG_ARCH_SA1100),y)
-OBJS += head-sa1100.o
-endif
-
ifeq ($(CONFIG_CPU_XSCALE),y)
OBJS += head-xscale.o
endif
diff --git a/arch/arm/boot/compressed/head-sa1100.S b/arch/arm/boot/compressed/head-sa1100.S
deleted file mode 100644
index 23eae1a65064..000000000000
--- a/arch/arm/boot/compressed/head-sa1100.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/arm/boot/compressed/head-sa1100.S
- *
- * Copyright (C) 1999 Nicolas Pitre <nico@fluxnic.net>
- *
- * SA1100 specific tweaks. This is merged into head.S by the linker.
- *
- */
-
-#include <linux/linkage.h>
-#include <asm/mach-types.h>
-
- .section ".start", "ax"
- .arch armv4
-
-__SA1100_start:
-
- @ Preserve r8/r7 i.e. kernel entry values
-#ifdef CONFIG_SA1100_COLLIE
- mov r7, #MACH_TYPE_COLLIE
-#endif
- mrc p15, 0, r0, c1, c0, 0 @ read control reg
- ands r0, r0, #0x0d
- beq 99f
-
- @ Data cache might be active.
- @ Be sure to flush kernel binary out of the cache,
- @ whatever state it is, before it is turned off.
- @ This is done by fetching through currently executed
- @ memory to be sure we hit the same cache.
- bic r2, pc, #0x1f
- add r3, r2, #0x4000 @ 16 kb is quite enough...
-1: ldr r0, [r2], #32
- teq r2, r3
- bne 1b
- mcr p15, 0, r0, c7, c10, 4 @ drain WB
- mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
-
- @ disabling MMU and caches
- mrc p15, 0, r0, c1, c0, 0 @ read control reg
- bic r0, r0, #0x0d @ clear WB, DC, MMU
- bic r0, r0, #0x1000 @ clear Icache
- mcr p15, 0, r0, c1, c0, 0
-99:
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 9f406e9c0ea6..845abffbc2d6 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -64,17 +64,10 @@
busyuart \tmp, \rb
.endm
-#if defined(CONFIG_ARCH_SA1100)
- .macro loadsp, rb, tmp1, tmp2
- mov \rb, #0x80000000 @ physical base address
- add \rb, \rb, #0x00010000 @ Ser1
- .endm
-#else
.macro loadsp, rb, tmp1, tmp2
addruart \rb, \tmp1, \tmp2
.endm
#endif
-#endif
#endif
.macro kputc,val
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index d2fdb1796f48..d72dccf6f3c2 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -1,14 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
-config SA1111
- bool
- select ZONE_DMA if ARCH_SA1100
-
config KRAIT_L2_ACCESSORS
bool
-config SHARP_LOCOMO
- bool
-
config SHARP_PARAM
bool
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 9733381074e0..e1bcc250874f 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -5,9 +5,7 @@
obj-y += firmware.o
-obj-$(CONFIG_SA1111) += sa1111.o
obj-$(CONFIG_KRAIT_L2_ACCESSORS) += krait-l2-accessors.o
-obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
obj-$(CONFIG_SHARP_SCOOP) += scoop.o
obj-$(CONFIG_CPU_V7) += secure_cntvoff.o
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
deleted file mode 100644
index 55e360452828..000000000000
--- a/arch/arm/common/locomo.c
+++ /dev/null
@@ -1,886 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/common/locomo.c
- *
- * Sharp LoCoMo support
- *
- * This file contains all generic LoCoMo support.
- *
- * All initialization functions provided here are intended to be called
- * from machine specific code with proper arguments when required.
- *
- * Based on sa1111.c
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/ioport.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
-
-#include <asm/hardware/locomo.h>
-
-/* LoCoMo Interrupts */
-#define IRQ_LOCOMO_KEY (0)
-#define IRQ_LOCOMO_GPIO (1)
-#define IRQ_LOCOMO_LT (2)
-#define IRQ_LOCOMO_SPI (3)
-
-/* M62332 output channel selection */
-#define M62332_EVR_CH 1 /* M62332 volume channel number */
- /* 0 : CH.1 , 1 : CH. 2 */
-/* DAC send data */
-#define M62332_SLAVE_ADDR 0x4e /* Slave address */
-#define M62332_W_BIT 0x00 /* W bit (0 only) */
-#define M62332_SUB_ADDR 0x00 /* Sub address */
-#define M62332_A_BIT 0x00 /* A bit (0 only) */
-
-/* DAC setup and hold times (expressed in us) */
-#define DAC_BUS_FREE_TIME 5 /* 4.7 us */
-#define DAC_START_SETUP_TIME 5 /* 4.7 us */
-#define DAC_STOP_SETUP_TIME 4 /* 4.0 us */
-#define DAC_START_HOLD_TIME 5 /* 4.7 us */
-#define DAC_SCL_LOW_HOLD_TIME 5 /* 4.7 us */
-#define DAC_SCL_HIGH_HOLD_TIME 4 /* 4.0 us */
-#define DAC_DATA_SETUP_TIME 1 /* 250 ns */
-#define DAC_DATA_HOLD_TIME 1 /* 300 ns */
-#define DAC_LOW_SETUP_TIME 1 /* 300 ns */
-#define DAC_HIGH_SETUP_TIME 1 /* 1000 ns */
-
-/* the following is the overall data for the locomo chip */
-struct locomo {
- struct device *dev;
- unsigned long phys;
- unsigned int irq;
- int irq_base;
- spinlock_t lock;
- void __iomem *base;
-#ifdef CONFIG_PM
- void *saved_state;
-#endif
-};
-
-static const struct bus_type locomo_bus_type;
-
-struct locomo_dev_info {
- unsigned long offset;
- unsigned long length;
- unsigned int devid;
- unsigned int irq[1];
- const char * name;
-};
-
-/* All the locomo devices. If offset is non-zero, the mapbase for the
- * locomo_dev will be set to the chip base plus offset. If offset is
- * zero, then the mapbase for the locomo_dev will be set to zero. An
- * offset of zero means the device only uses GPIOs or other helper
- * functions inside this file */
-static struct locomo_dev_info locomo_devices[] = {
- {
- .devid = LOCOMO_DEVID_KEYBOARD,
- .irq = { IRQ_LOCOMO_KEY },
- .name = "locomo-keyboard",
- .offset = LOCOMO_KEYBOARD,
- .length = 16,
- },
- {
- .devid = LOCOMO_DEVID_FRONTLIGHT,
- .irq = {},
- .name = "locomo-frontlight",
- .offset = LOCOMO_FRONTLIGHT,
- .length = 8,
-
- },
- {
- .devid = LOCOMO_DEVID_BACKLIGHT,
- .irq = {},
- .name = "locomo-backlight",
- .offset = LOCOMO_BACKLIGHT,
- .length = 8,
- },
- {
- .devid = LOCOMO_DEVID_AUDIO,
- .irq = {},
- .name = "locomo-audio",
- .offset = LOCOMO_AUDIO,
- .length = 4,
- },
- {
- .devid = LOCOMO_DEVID_LED,
- .irq = {},
- .name = "locomo-led",
- .offset = LOCOMO_LED,
- .length = 8,
- },
- {
- .devid = LOCOMO_DEVID_UART,
- .irq = {},
- .name = "locomo-uart",
- .offset = 0,
- .length = 0,
- },
- {
- .devid = LOCOMO_DEVID_SPI,
- .irq = {},
- .name = "locomo-spi",
- .offset = LOCOMO_SPI,
- .length = 0x30,
- },
-};
-
-static void locomo_handler(struct irq_desc *desc)
-{
- struct locomo *lchip = irq_desc_get_handler_data(desc);
- int req, i;
-
- /* Acknowledge the parent IRQ */
- desc->irq_data.chip->irq_ack(&desc->irq_data);
-
- /* check why this interrupt was generated */
- req = locomo_readl(lchip->base + LOCOMO_ICR) & 0x0f00;
-
- if (req) {
- unsigned int irq;
-
- /* generate the next interrupt(s) */
- irq = lchip->irq_base;
- for (i = 0; i <= 3; i++, irq++) {
- if (req & (0x0100 << i)) {
- generic_handle_irq(irq);
- }
-
- }
- }
-}
-
-static void locomo_ack_irq(struct irq_data *d)
-{
-}
-
-static void locomo_mask_irq(struct irq_data *d)
-{
- struct locomo *lchip = irq_data_get_irq_chip_data(d);
- unsigned int r;
- r = locomo_readl(lchip->base + LOCOMO_ICR);
- r &= ~(0x0010 << (d->irq - lchip->irq_base));
- locomo_writel(r, lchip->base + LOCOMO_ICR);
-}
-
-static void locomo_unmask_irq(struct irq_data *d)
-{
- struct locomo *lchip = irq_data_get_irq_chip_data(d);
- unsigned int r;
- r = locomo_readl(lchip->base + LOCOMO_ICR);
- r |= (0x0010 << (d->irq - lchip->irq_base));
- locomo_writel(r, lchip->base + LOCOMO_ICR);
-}
-
-static struct irq_chip locomo_chip = {
- .name = "LOCOMO",
- .irq_ack = locomo_ack_irq,
- .irq_mask = locomo_mask_irq,
- .irq_unmask = locomo_unmask_irq,
-};
-
-static void locomo_setup_irq(struct locomo *lchip)
-{
- int irq = lchip->irq_base;
-
- /*
- * Install handler for IRQ_LOCOMO_HW.
- */
- irq_set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING);
- irq_set_chained_handler_and_data(lchip->irq, locomo_handler, lchip);
-
- /* Install handlers for IRQ_LOCOMO_* */
- for ( ; irq <= lchip->irq_base + 3; irq++) {
- irq_set_chip_and_handler(irq, &locomo_chip, handle_level_irq);
- irq_set_chip_data(irq, lchip);
- irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
- }
-}
-
-
-static void locomo_dev_release(struct device *_dev)
-{
- struct locomo_dev *dev = LOCOMO_DEV(_dev);
-
- kfree(dev);
-}
-
-static int
-locomo_init_one_child(struct locomo *lchip, struct locomo_dev_info *info)
-{
- struct locomo_dev *dev;
- int ret;
-
- dev = kzalloc_obj(struct locomo_dev);
- if (!dev) {
- ret = -ENOMEM;
- goto out;
- }
-
- /*
- * If the parent device has a DMA mask associated with it,
- * propagate it down to the children.
- */
- if (lchip->dev->dma_mask) {
- dev->dma_mask = *lchip->dev->dma_mask;
- dev->dev.dma_mask = &dev->dma_mask;
- }
-
- dev_set_name(&dev->dev, "%s", info->name);
- dev->devid = info->devid;
- dev->dev.parent = lchip->dev;
- dev->dev.bus = &locomo_bus_type;
- dev->dev.release = locomo_dev_release;
- dev->dev.coherent_dma_mask = lchip->dev->coherent_dma_mask;
-
- if (info->offset)
- dev->mapbase = lchip->base + info->offset;
- else
- dev->mapbase = 0;
- dev->length = info->length;
-
- dev->irq[0] = (lchip->irq_base == NO_IRQ) ?
- NO_IRQ : lchip->irq_base + info->irq[0];
-
- ret = device_register(&dev->dev);
- if (ret) {
- out:
- kfree(dev);
- }
- return ret;
-}
-
-#ifdef CONFIG_PM
-
-struct locomo_save_data {
- u16 LCM_GPO;
- u16 LCM_SPICT;
- u16 LCM_GPE;
- u16 LCM_ASD;
- u16 LCM_SPIMD;
-};
-
-static int locomo_suspend(struct platform_device *dev, pm_message_t state)
-{
- struct locomo *lchip = platform_get_drvdata(dev);
- struct locomo_save_data *save;
- unsigned long flags;
-
- save = kmalloc_obj(struct locomo_save_data);
- if (!save)
- return -ENOMEM;
-
- lchip->saved_state = save;
-
- spin_lock_irqsave(&lchip->lock, flags);
-
- save->LCM_GPO = locomo_readl(lchip->base + LOCOMO_GPO); /* GPIO */
- locomo_writel(0x00, lchip->base + LOCOMO_GPO);
- save->LCM_SPICT = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPICT); /* SPI */
- locomo_writel(0x40, lchip->base + LOCOMO_SPI + LOCOMO_SPICT);
- save->LCM_GPE = locomo_readl(lchip->base + LOCOMO_GPE); /* GPIO */
- locomo_writel(0x00, lchip->base + LOCOMO_GPE);
- save->LCM_ASD = locomo_readl(lchip->base + LOCOMO_ASD); /* ADSTART */
- locomo_writel(0x00, lchip->base + LOCOMO_ASD);
- save->LCM_SPIMD = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPIMD); /* SPI */
- locomo_writel(0x3C14, lchip->base + LOCOMO_SPI + LOCOMO_SPIMD);
-
- locomo_writel(0x00, lchip->base + LOCOMO_PAIF);
- locomo_writel(0x00, lchip->base + LOCOMO_DAC);
- locomo_writel(0x00, lchip->base + LOCOMO_BACKLIGHT + LOCOMO_TC);
-
- if ((locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT0) & 0x88) && (locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT1) & 0x88))
- locomo_writel(0x00, lchip->base + LOCOMO_C32K); /* CLK32 off */
- else
- /* 18MHz already enabled, so no wait */
- locomo_writel(0xc1, lchip->base + LOCOMO_C32K); /* CLK32 on */
-
- locomo_writel(0x00, lchip->base + LOCOMO_TADC); /* 18MHz clock off*/
- locomo_writel(0x00, lchip->base + LOCOMO_AUDIO + LOCOMO_ACC); /* 22MHz/24MHz clock off */
- locomo_writel(0x00, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS); /* FL */
-
- spin_unlock_irqrestore(&lchip->lock, flags);
-
- return 0;
-}
-
-static int locomo_resume(struct platform_device *dev)
-{
- struct locomo *lchip = platform_get_drvdata(dev);
- struct locomo_save_data *save;
- unsigned long r;
- unsigned long flags;
-
- save = lchip->saved_state;
- if (!save)
- return 0;
-
- spin_lock_irqsave(&lchip->lock, flags);
-
- locomo_writel(save->LCM_GPO, lchip->base + LOCOMO_GPO);
- locomo_writel(save->LCM_SPICT, lchip->base + LOCOMO_SPI + LOCOMO_SPICT);
- locomo_writel(save->LCM_GPE, lchip->base + LOCOMO_GPE);
- locomo_writel(save->LCM_ASD, lchip->base + LOCOMO_ASD);
- locomo_writel(save->LCM_SPIMD, lchip->base + LOCOMO_SPI + LOCOMO_SPIMD);
-
- locomo_writel(0x00, lchip->base + LOCOMO_C32K);
- locomo_writel(0x90, lchip->base + LOCOMO_TADC);
-
- locomo_writel(0, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KSC);
- r = locomo_readl(lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC);
- r &= 0xFEFF;
- locomo_writel(r, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC);
- locomo_writel(0x1, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KCMD);
-
- spin_unlock_irqrestore(&lchip->lock, flags);
-
- lchip->saved_state = NULL;
- kfree(save);
-
- return 0;
-}
-#endif
-
-static int
-__locomo_probe(struct device *me, struct resource *mem, int irq)
-{
- struct locomo_platform_data *pdata = me->platform_data;
- struct locomo *lchip;
- unsigned long r;
- int i, ret = -ENODEV;
-
- lchip = kzalloc_obj(struct locomo);
- if (!lchip)
- return -ENOMEM;
-
- spin_lock_init(&lchip->lock);
-
- lchip->dev = me;
- dev_set_drvdata(lchip->dev, lchip);
-
- lchip->phys = mem->start;
- lchip->irq = irq;
- lchip->irq_base = (pdata) ? pdata->irq_base : NO_IRQ;
-
- /*
- * Map the whole region. This also maps the
- * registers for our children.
- */
- lchip->base = ioremap(mem->start, PAGE_SIZE);
- if (!lchip->base) {
- ret = -ENOMEM;
- goto out;
- }
-
- /* locomo initialize */
- locomo_writel(0, lchip->base + LOCOMO_ICR);
- /* KEYBOARD */
- locomo_writel(0, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC);
-
- /* GPIO */
- locomo_writel(0, lchip->base + LOCOMO_GPO);
- locomo_writel((LOCOMO_GPIO(1) | LOCOMO_GPIO(2) | LOCOMO_GPIO(13) | LOCOMO_GPIO(14))
- , lchip->base + LOCOMO_GPE);
- locomo_writel((LOCOMO_GPIO(1) | LOCOMO_GPIO(2) | LOCOMO_GPIO(13) | LOCOMO_GPIO(14))
- , lchip->base + LOCOMO_GPD);
- locomo_writel(0, lchip->base + LOCOMO_GIE);
-
- /* Frontlight */
- locomo_writel(0, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS);
- locomo_writel(0, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALD);
-
- /* Longtime timer */
- locomo_writel(0, lchip->base + LOCOMO_LTINT);
- /* SPI */
- locomo_writel(0, lchip->base + LOCOMO_SPI + LOCOMO_SPIIE);
-
- locomo_writel(6 + 8 + 320 + 30 - 10, lchip->base + LOCOMO_ASD);
- r = locomo_readl(lchip->base + LOCOMO_ASD);
- r |= 0x8000;
- locomo_writel(r, lchip->base + LOCOMO_ASD);
-
- locomo_writel(6 + 8 + 320 + 30 - 10 - 128 + 4, lchip->base + LOCOMO_HSD);
- r = locomo_readl(lchip->base + LOCOMO_HSD);
- r |= 0x8000;
- locomo_writel(r, lchip->base + LOCOMO_HSD);
-
- locomo_writel(128 / 8, lchip->base + LOCOMO_HSC);
-
- /* XON */
- locomo_writel(0x80, lchip->base + LOCOMO_TADC);
- udelay(1000);
- /* CLK9MEN */
- r = locomo_readl(lchip->base + LOCOMO_TADC);
- r |= 0x10;
- locomo_writel(r, lchip->base + LOCOMO_TADC);
- udelay(100);
-
- /* init DAC */
- r = locomo_readl(lchip->base + LOCOMO_DAC);
- r |= LOCOMO_DAC_SCLOEB | LOCOMO_DAC_SDAOEB;
- locomo_writel(r, lchip->base + LOCOMO_DAC);
-
- r = locomo_readl(lchip->base + LOCOMO_VER);
- printk(KERN_INFO "LoCoMo Chip: %lu%lu\n", (r >> 8), (r & 0xff));
-
- /*
- * The interrupt controller must be initialised before any
- * other device to ensure that the interrupts are available.
- */
- if (lchip->irq != NO_IRQ && lchip->irq_base != NO_IRQ)
- locomo_setup_irq(lchip);
-
- for (i = 0; i < ARRAY_SIZE(locomo_devices); i++)
- locomo_init_one_child(lchip, &locomo_devices[i]);
- return 0;
-
- out:
- kfree(lchip);
- return ret;
-}
-
-static int locomo_remove_child(struct device *dev, void *data)
-{
- device_unregister(dev);
- return 0;
-}
-
-static void __locomo_remove(struct locomo *lchip)
-{
- device_for_each_child(lchip->dev, NULL, locomo_remove_child);
-
- if (lchip->irq != NO_IRQ) {
- irq_set_chained_handler_and_data(lchip->irq, NULL, NULL);
- }
-
- iounmap(lchip->base);
- kfree(lchip);
-}
-
-/**
- * locomo_probe - probe for a single LoCoMo chip.
- * @dev: platform device
- *
- * Probe for a LoCoMo chip. This must be called
- * before any other locomo-specific code.
- *
- * Returns:
- * * %-EINVAL - device's IORESOURCE_MEM not found
- * * %-ENXIO - could not allocate an IRQ for the device
- * * %-ENODEV - device not found.
- * * %-EBUSY - physical address already marked in-use.
- * * %-ENOMEM - could not allocate or iomap memory.
- * * %0 - successful.
- */
-static int locomo_probe(struct platform_device *dev)
-{
- struct resource *mem;
- int irq;
-
- mem = platform_get_resource(dev, IORESOURCE_MEM, 0);
- if (!mem)
- return -EINVAL;
- irq = platform_get_irq(dev, 0);
- if (irq < 0)
- return -ENXIO;
-
- return __locomo_probe(&dev->dev, mem, irq);
-}
-
-static void locomo_remove(struct platform_device *dev)
-{
- struct locomo *lchip = platform_get_drvdata(dev);
-
- if (lchip) {
- __locomo_remove(lchip);
- platform_set_drvdata(dev, NULL);
- }
-}
-
-/*
- * Not sure if this should be on the system bus or not yet.
- * We really want some way to register a system device at
- * the per-machine level, and then have this driver pick
- * up the registered devices.
- */
-static struct platform_driver locomo_device_driver = {
- .probe = locomo_probe,
- .remove = locomo_remove,
-#ifdef CONFIG_PM
- .suspend = locomo_suspend,
- .resume = locomo_resume,
-#endif
- .driver = {
- .name = "locomo",
- },
-};
-
-/*
- * Get the parent device driver (us) structure
- * from a child function device
- */
-static inline struct locomo *locomo_chip_driver(struct locomo_dev *ldev)
-{
- return (struct locomo *)dev_get_drvdata(ldev->dev.parent);
-}
-
-void locomo_gpio_set_dir(struct device *dev, unsigned int bits, unsigned int dir)
-{
- struct locomo *lchip = dev_get_drvdata(dev);
- unsigned long flags;
- unsigned int r;
-
- if (!lchip)
- return;
-
- spin_lock_irqsave(&lchip->lock, flags);
-
- r = locomo_readl(lchip->base + LOCOMO_GPD);
- if (dir)
- r |= bits;
- else
- r &= ~bits;
- locomo_writel(r, lchip->base + LOCOMO_GPD);
-
- r = locomo_readl(lchip->base + LOCOMO_GPE);
- if (dir)
- r |= bits;
- else
- r &= ~bits;
- locomo_writel(r, lchip->base + LOCOMO_GPE);
-
- spin_unlock_irqrestore(&lchip->lock, flags);
-}
-EXPORT_SYMBOL(locomo_gpio_set_dir);
-
-int locomo_gpio_read_level(struct device *dev, unsigned int bits)
-{
- struct locomo *lchip = dev_get_drvdata(dev);
- unsigned long flags;
- unsigned int ret;
-
- if (!lchip)
- return -ENODEV;
-
- spin_lock_irqsave(&lchip->lock, flags);
- ret = locomo_readl(lchip->base + LOCOMO_GPL);
- spin_unlock_irqrestore(&lchip->lock, flags);
-
- ret &= bits;
- return ret;
-}
-EXPORT_SYMBOL(locomo_gpio_read_level);
-
-int locomo_gpio_read_output(struct device *dev, unsigned int bits)
-{
- struct locomo *lchip = dev_get_drvdata(dev);
- unsigned long flags;
- unsigned int ret;
-
- if (!lchip)
- return -ENODEV;
-
- spin_lock_irqsave(&lchip->lock, flags);
- ret = locomo_readl(lchip->base + LOCOMO_GPO);
- spin_unlock_irqrestore(&lchip->lock, flags);
-
- ret &= bits;
- return ret;
-}
-EXPORT_SYMBOL(locomo_gpio_read_output);
-
-void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set)
-{
- struct locomo *lchip = dev_get_drvdata(dev);
- unsigned long flags;
- unsigned int r;
-
- if (!lchip)
- return;
-
- spin_lock_irqsave(&lchip->lock, flags);
-
- r = locomo_readl(lchip->base + LOCOMO_GPO);
- if (set)
- r |= bits;
- else
- r &= ~bits;
- locomo_writel(r, lchip->base + LOCOMO_GPO);
-
- spin_unlock_irqrestore(&lchip->lock, flags);
-}
-EXPORT_SYMBOL(locomo_gpio_write);
-
-static void locomo_m62332_sendbit(void *mapbase, int bit)
-{
- unsigned int r;
-
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r &= ~(LOCOMO_DAC_SCLOEB);
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
- udelay(DAC_DATA_HOLD_TIME); /* 300 nsec */
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r &= ~(LOCOMO_DAC_SCLOEB);
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
- udelay(DAC_SCL_LOW_HOLD_TIME); /* 4.7 usec */
-
- if (bit & 1) {
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r |= LOCOMO_DAC_SDAOEB;
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_HIGH_SETUP_TIME); /* 1000 nsec */
- } else {
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r &= ~(LOCOMO_DAC_SDAOEB);
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
- }
-
- udelay(DAC_DATA_SETUP_TIME); /* 250 nsec */
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r |= LOCOMO_DAC_SCLOEB;
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_HIGH_SETUP_TIME); /* 1000 nsec */
- udelay(DAC_SCL_HIGH_HOLD_TIME); /* 4.0 usec */
-}
-
-void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel)
-{
- struct locomo *lchip = locomo_chip_driver(ldev);
- int i;
- unsigned char data;
- unsigned int r;
- void *mapbase = lchip->base;
- unsigned long flags;
-
- spin_lock_irqsave(&lchip->lock, flags);
-
- /* Start */
- udelay(DAC_BUS_FREE_TIME); /* 5.0 usec */
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r |= LOCOMO_DAC_SCLOEB | LOCOMO_DAC_SDAOEB;
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_HIGH_SETUP_TIME); /* 1000 nsec */
- udelay(DAC_SCL_HIGH_HOLD_TIME); /* 4.0 usec */
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r &= ~(LOCOMO_DAC_SDAOEB);
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_START_HOLD_TIME); /* 5.0 usec */
- udelay(DAC_DATA_HOLD_TIME); /* 300 nsec */
-
- /* Send slave address and W bit (LSB is W bit) */
- data = (M62332_SLAVE_ADDR << 1) | M62332_W_BIT;
- for (i = 1; i <= 8; i++) {
- locomo_m62332_sendbit(mapbase, data >> (8 - i));
- }
-
- /* Check A bit */
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r &= ~(LOCOMO_DAC_SCLOEB);
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
- udelay(DAC_SCL_LOW_HOLD_TIME); /* 4.7 usec */
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r &= ~(LOCOMO_DAC_SDAOEB);
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r |= LOCOMO_DAC_SCLOEB;
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_HIGH_SETUP_TIME); /* 1000 nsec */
- udelay(DAC_SCL_HIGH_HOLD_TIME); /* 4.7 usec */
- if (locomo_readl(mapbase + LOCOMO_DAC) & LOCOMO_DAC_SDAOEB) { /* High is error */
- printk(KERN_WARNING "locomo: m62332_senddata Error 1\n");
- goto out;
- }
-
- /* Send Sub address (LSB is channel select) */
- /* channel = 0 : ch1 select */
- /* = 1 : ch2 select */
- data = M62332_SUB_ADDR + channel;
- for (i = 1; i <= 8; i++) {
- locomo_m62332_sendbit(mapbase, data >> (8 - i));
- }
-
- /* Check A bit */
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r &= ~(LOCOMO_DAC_SCLOEB);
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
- udelay(DAC_SCL_LOW_HOLD_TIME); /* 4.7 usec */
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r &= ~(LOCOMO_DAC_SDAOEB);
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r |= LOCOMO_DAC_SCLOEB;
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_HIGH_SETUP_TIME); /* 1000 nsec */
- udelay(DAC_SCL_HIGH_HOLD_TIME); /* 4.7 usec */
- if (locomo_readl(mapbase + LOCOMO_DAC) & LOCOMO_DAC_SDAOEB) { /* High is error */
- printk(KERN_WARNING "locomo: m62332_senddata Error 2\n");
- goto out;
- }
-
- /* Send DAC data */
- for (i = 1; i <= 8; i++) {
- locomo_m62332_sendbit(mapbase, dac_data >> (8 - i));
- }
-
- /* Check A bit */
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r &= ~(LOCOMO_DAC_SCLOEB);
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
- udelay(DAC_SCL_LOW_HOLD_TIME); /* 4.7 usec */
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r &= ~(LOCOMO_DAC_SDAOEB);
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r |= LOCOMO_DAC_SCLOEB;
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_HIGH_SETUP_TIME); /* 1000 nsec */
- udelay(DAC_SCL_HIGH_HOLD_TIME); /* 4.7 usec */
- if (locomo_readl(mapbase + LOCOMO_DAC) & LOCOMO_DAC_SDAOEB) { /* High is error */
- printk(KERN_WARNING "locomo: m62332_senddata Error 3\n");
- }
-
-out:
- /* stop */
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r &= ~(LOCOMO_DAC_SCLOEB);
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
- udelay(DAC_SCL_LOW_HOLD_TIME); /* 4.7 usec */
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r |= LOCOMO_DAC_SCLOEB;
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_HIGH_SETUP_TIME); /* 1000 nsec */
- udelay(DAC_SCL_HIGH_HOLD_TIME); /* 4 usec */
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r |= LOCOMO_DAC_SDAOEB;
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_HIGH_SETUP_TIME); /* 1000 nsec */
- udelay(DAC_SCL_HIGH_HOLD_TIME); /* 4 usec */
-
- r = locomo_readl(mapbase + LOCOMO_DAC);
- r |= LOCOMO_DAC_SCLOEB | LOCOMO_DAC_SDAOEB;
- locomo_writel(r, mapbase + LOCOMO_DAC);
- udelay(DAC_LOW_SETUP_TIME); /* 1000 nsec */
- udelay(DAC_SCL_LOW_HOLD_TIME); /* 4.7 usec */
-
- spin_unlock_irqrestore(&lchip->lock, flags);
-}
-EXPORT_SYMBOL(locomo_m62332_senddata);
-
-/*
- * Frontlight control
- */
-
-void locomo_frontlight_set(struct locomo_dev *dev, int duty, int vr, int bpwf)
-{
- unsigned long flags;
- struct locomo *lchip = locomo_chip_driver(dev);
-
- if (vr)
- locomo_gpio_write(dev->dev.parent, LOCOMO_GPIO_FL_VR, 1);
- else
- locomo_gpio_write(dev->dev.parent, LOCOMO_GPIO_FL_VR, 0);
-
- spin_lock_irqsave(&lchip->lock, flags);
- locomo_writel(bpwf, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS);
- udelay(100);
- locomo_writel(duty, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALD);
- locomo_writel(bpwf | LOCOMO_ALC_EN, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS);
- spin_unlock_irqrestore(&lchip->lock, flags);
-}
-EXPORT_SYMBOL(locomo_frontlight_set);
-
-/*
- * LoCoMo "Register Access Bus."
- *
- * We model this as a regular bus type, and hang devices directly
- * off this.
- */
-static int locomo_match(struct device *_dev, const struct device_driver *_drv)
-{
- struct locomo_dev *dev = LOCOMO_DEV(_dev);
- const struct locomo_driver *drv = LOCOMO_DRV(_drv);
-
- return dev->devid == drv->devid;
-}
-
-static int locomo_bus_probe(struct device *dev)
-{
- struct locomo_dev *ldev = LOCOMO_DEV(dev);
- struct locomo_driver *drv = LOCOMO_DRV(dev->driver);
- int ret = -ENODEV;
-
- if (drv->probe)
- ret = drv->probe(ldev);
- return ret;
-}
-
-static void locomo_bus_remove(struct device *dev)
-{
- struct locomo_dev *ldev = LOCOMO_DEV(dev);
- struct locomo_driver *drv = LOCOMO_DRV(dev->driver);
-
- if (drv->remove)
- drv->remove(ldev);
-}
-
-static const struct bus_type locomo_bus_type = {
- .name = "locomo-bus",
- .match = locomo_match,
- .probe = locomo_bus_probe,
- .remove = locomo_bus_remove,
-};
-
-int locomo_driver_register(struct locomo_driver *driver)
-{
- driver->drv.bus = &locomo_bus_type;
- return driver_register(&driver->drv);
-}
-EXPORT_SYMBOL(locomo_driver_register);
-
-void locomo_driver_unregister(struct locomo_driver *driver)
-{
- driver_unregister(&driver->drv);
-}
-EXPORT_SYMBOL(locomo_driver_unregister);
-
-static int __init locomo_init(void)
-{
- int ret = bus_register(&locomo_bus_type);
- if (ret == 0)
- platform_driver_register(&locomo_device_driver);
- return ret;
-}
-
-static void __exit locomo_exit(void)
-{
- platform_driver_unregister(&locomo_device_driver);
- bus_unregister(&locomo_bus_type);
-}
-
-module_init(locomo_init);
-module_exit(locomo_exit);
-
-MODULE_DESCRIPTION("Sharp LoCoMo core driver");
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("John Lenz <lenz@cs.wisc.edu>");
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
deleted file mode 100644
index a0f854cf4748..000000000000
--- a/arch/arm/common/sa1111.c
+++ /dev/null
@@ -1,1413 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/common/sa1111.c
- *
- * SA1111 support
- *
- * Original code by John Dorsey
- *
- * This file contains all generic SA1111 support.
- *
- * All initialization functions provided here are intended to be called
- * from machine specific code with proper arguments when required.
- */
-#include <linux/module.h>
-#include <linux/gpio/driver.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/ioport.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-#include <linux/dma-map-ops.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include <asm/mach/irq.h>
-#include <asm/mach-types.h>
-#include <linux/sizes.h>
-
-#include <asm/hardware/sa1111.h>
-
-#ifdef CONFIG_ARCH_SA1100
-#include <mach/hardware.h>
-#endif
-
-/* SA1111 IRQs */
-#define IRQ_GPAIN0 (0)
-#define IRQ_GPAIN1 (1)
-#define IRQ_GPAIN2 (2)
-#define IRQ_GPAIN3 (3)
-#define IRQ_GPBIN0 (4)
-#define IRQ_GPBIN1 (5)
-#define IRQ_GPBIN2 (6)
-#define IRQ_GPBIN3 (7)
-#define IRQ_GPBIN4 (8)
-#define IRQ_GPBIN5 (9)
-#define IRQ_GPCIN0 (10)
-#define IRQ_GPCIN1 (11)
-#define IRQ_GPCIN2 (12)
-#define IRQ_GPCIN3 (13)
-#define IRQ_GPCIN4 (14)
-#define IRQ_GPCIN5 (15)
-#define IRQ_GPCIN6 (16)
-#define IRQ_GPCIN7 (17)
-#define IRQ_MSTXINT (18)
-#define IRQ_MSRXINT (19)
-#define IRQ_MSSTOPERRINT (20)
-#define IRQ_TPTXINT (21)
-#define IRQ_TPRXINT (22)
-#define IRQ_TPSTOPERRINT (23)
-#define SSPXMTINT (24)
-#define SSPRCVINT (25)
-#define SSPROR (26)
-#define AUDXMTDMADONEA (32)
-#define AUDRCVDMADONEA (33)
-#define AUDXMTDMADONEB (34)
-#define AUDRCVDMADONEB (35)
-#define AUDTFSR (36)
-#define AUDRFSR (37)
-#define AUDTUR (38)
-#define AUDROR (39)
-#define AUDDTS (40)
-#define AUDRDD (41)
-#define AUDSTO (42)
-#define IRQ_USBPWR (43)
-#define IRQ_HCIM (44)
-#define IRQ_HCIBUFFACC (45)
-#define IRQ_HCIRMTWKP (46)
-#define IRQ_NHCIMFCIR (47)
-#define IRQ_USB_PORT_RESUME (48)
-#define IRQ_S0_READY_NINT (49)
-#define IRQ_S1_READY_NINT (50)
-#define IRQ_S0_CD_VALID (51)
-#define IRQ_S1_CD_VALID (52)
-#define IRQ_S0_BVD1_STSCHG (53)
-#define IRQ_S1_BVD1_STSCHG (54)
-#define SA1111_IRQ_NR (55)
-
-extern void sa1110_mb_enable(void);
-extern void sa1110_mb_disable(void);
-
-/*
- * We keep the following data for the overall SA1111. Note that the
- * struct device and struct resource are "fake"; they should be supplied
- * by the bus above us. However, in the interests of getting all SA1111
- * drivers converted over to the device model, we provide this as an
- * anchor point for all the other drivers.
- */
-struct sa1111 {
- struct device *dev;
- struct clk *clk;
- unsigned long phys;
- int irq;
- int irq_base; /* base for cascaded on-chip IRQs */
- spinlock_t lock;
- void __iomem *base;
- struct sa1111_platform_data *pdata;
- struct irq_domain *irqdomain;
- struct gpio_chip gc;
-#ifdef CONFIG_PM
- void *saved_state;
-#endif
-};
-
-/*
- * We _really_ need to eliminate this. Its only users
- * are the PWM and DMA checking code.
- */
-static struct sa1111 *g_sa1111;
-
-struct sa1111_dev_info {
- unsigned long offset;
- unsigned long skpcr_mask;
- bool dma;
- unsigned int devid;
- unsigned int hwirq[6];
-};
-
-static struct sa1111_dev_info sa1111_devices[] = {
- {
- .offset = SA1111_USB,
- .skpcr_mask = SKPCR_UCLKEN,
- .dma = true,
- .devid = SA1111_DEVID_USB,
- .hwirq = {
- IRQ_USBPWR,
- IRQ_HCIM,
- IRQ_HCIBUFFACC,
- IRQ_HCIRMTWKP,
- IRQ_NHCIMFCIR,
- IRQ_USB_PORT_RESUME
- },
- },
- {
- .offset = 0x0600,
- .skpcr_mask = SKPCR_I2SCLKEN | SKPCR_L3CLKEN,
- .dma = true,
- .devid = SA1111_DEVID_SAC,
- .hwirq = {
- AUDXMTDMADONEA,
- AUDXMTDMADONEB,
- AUDRCVDMADONEA,
- AUDRCVDMADONEB
- },
- },
- {
- .offset = 0x0800,
- .skpcr_mask = SKPCR_SCLKEN,
- .devid = SA1111_DEVID_SSP,
- },
- {
- .offset = SA1111_KBD,
- .skpcr_mask = SKPCR_PTCLKEN,
- .devid = SA1111_DEVID_PS2_KBD,
- .hwirq = {
- IRQ_TPRXINT,
- IRQ_TPTXINT
- },
- },
- {
- .offset = SA1111_MSE,
- .skpcr_mask = SKPCR_PMCLKEN,
- .devid = SA1111_DEVID_PS2_MSE,
- .hwirq = {
- IRQ_MSRXINT,
- IRQ_MSTXINT
- },
- },
- {
- .offset = 0x1800,
- .skpcr_mask = 0,
- .devid = SA1111_DEVID_PCMCIA,
- .hwirq = {
- IRQ_S0_READY_NINT,
- IRQ_S0_CD_VALID,
- IRQ_S0_BVD1_STSCHG,
- IRQ_S1_READY_NINT,
- IRQ_S1_CD_VALID,
- IRQ_S1_BVD1_STSCHG,
- },
- },
-};
-
-static int sa1111_map_irq(struct sa1111 *sachip, irq_hw_number_t hwirq)
-{
- return irq_create_mapping(sachip->irqdomain, hwirq);
-}
-
-/*
- * SA1111 interrupt support. Since clearing an IRQ while there are
- * active IRQs causes the interrupt output to pulse, the upper levels
- * will call us again if there are more interrupts to process.
- */
-static void sa1111_irq_handler(struct irq_desc *desc)
-{
- unsigned int stat0, stat1, i;
- struct sa1111 *sachip = irq_desc_get_handler_data(desc);
- struct irq_domain *irqdomain;
- void __iomem *mapbase = sachip->base + SA1111_INTC;
-
- stat0 = readl_relaxed(mapbase + SA1111_INTSTATCLR0);
- stat1 = readl_relaxed(mapbase + SA1111_INTSTATCLR1);
-
- writel_relaxed(stat0, mapbase + SA1111_INTSTATCLR0);
-
- desc->irq_data.chip->irq_ack(&desc->irq_data);
-
- writel_relaxed(stat1, mapbase + SA1111_INTSTATCLR1);
-
- if (stat0 == 0 && stat1 == 0) {
- handle_bad_irq(desc);
- return;
- }
-
- irqdomain = sachip->irqdomain;
-
- for (i = 0; stat0; i++, stat0 >>= 1)
- if (stat0 & 1)
- generic_handle_domain_irq(irqdomain, i);
-
- for (i = 32; stat1; i++, stat1 >>= 1)
- if (stat1 & 1)
- generic_handle_domain_irq(irqdomain, i);
-
- /* For level-based interrupts */
- desc->irq_data.chip->irq_unmask(&desc->irq_data);
-}
-
-static u32 sa1111_irqmask(struct irq_data *d)
-{
- return BIT(irqd_to_hwirq(d) & 31);
-}
-
-static int sa1111_irqbank(struct irq_data *d)
-{
- return (irqd_to_hwirq(d) / 32) * 4;
-}
-
-static void sa1111_ack_irq(struct irq_data *d)
-{
-}
-
-static void sa1111_mask_irq(struct irq_data *d)
-{
- struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
- void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
- u32 ie;
-
- ie = readl_relaxed(mapbase + SA1111_INTEN0);
- ie &= ~sa1111_irqmask(d);
- writel(ie, mapbase + SA1111_INTEN0);
-}
-
-static void sa1111_unmask_irq(struct irq_data *d)
-{
- struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
- void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
- u32 ie;
-
- ie = readl_relaxed(mapbase + SA1111_INTEN0);
- ie |= sa1111_irqmask(d);
- writel_relaxed(ie, mapbase + SA1111_INTEN0);
-}
-
-/*
- * Attempt to re-trigger the interrupt. The SA1111 contains a register
- * (INTSET) which claims to do this. However, in practice no amount of
- * manipulation of INTEN and INTSET guarantees that the interrupt will
- * be triggered. In fact, its very difficult, if not impossible to get
- * INTSET to re-trigger the interrupt.
- */
-static int sa1111_retrigger_irq(struct irq_data *d)
-{
- struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
- void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
- u32 ip, mask = sa1111_irqmask(d);
- int i;
-
- ip = readl_relaxed(mapbase + SA1111_INTPOL0);
- for (i = 0; i < 8; i++) {
- writel_relaxed(ip ^ mask, mapbase + SA1111_INTPOL0);
- writel_relaxed(ip, mapbase + SA1111_INTPOL0);
- if (readl_relaxed(mapbase + SA1111_INTSTATCLR0) & mask)
- break;
- }
-
- if (i == 8) {
- pr_err("Danger Will Robinson: failed to re-trigger IRQ%d\n",
- d->irq);
- return 0;
- }
-
- return 1;
-}
-
-static int sa1111_type_irq(struct irq_data *d, unsigned int flags)
-{
- struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
- void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
- u32 ip, mask = sa1111_irqmask(d);
-
- if (flags == IRQ_TYPE_PROBE)
- return 0;
-
- if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0)
- return -EINVAL;
-
- ip = readl_relaxed(mapbase + SA1111_INTPOL0);
- if (flags & IRQ_TYPE_EDGE_RISING)
- ip &= ~mask;
- else
- ip |= mask;
- writel_relaxed(ip, mapbase + SA1111_INTPOL0);
- writel_relaxed(ip, mapbase + SA1111_WAKEPOL0);
-
- return 0;
-}
-
-static int sa1111_wake_irq(struct irq_data *d, unsigned int on)
-{
- struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
- void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
- u32 we, mask = sa1111_irqmask(d);
-
- we = readl_relaxed(mapbase + SA1111_WAKEEN0);
- if (on)
- we |= mask;
- else
- we &= ~mask;
- writel_relaxed(we, mapbase + SA1111_WAKEEN0);
-
- return 0;
-}
-
-static struct irq_chip sa1111_irq_chip = {
- .name = "SA1111",
- .irq_ack = sa1111_ack_irq,
- .irq_mask = sa1111_mask_irq,
- .irq_unmask = sa1111_unmask_irq,
- .irq_retrigger = sa1111_retrigger_irq,
- .irq_set_type = sa1111_type_irq,
- .irq_set_wake = sa1111_wake_irq,
-};
-
-static int sa1111_irqdomain_map(struct irq_domain *d, unsigned int irq,
- irq_hw_number_t hwirq)
-{
- struct sa1111 *sachip = d->host_data;
-
- /* Disallow unavailable interrupts */
- if (hwirq > SSPROR && hwirq < AUDXMTDMADONEA)
- return -EINVAL;
-
- irq_set_chip_data(irq, sachip);
- irq_set_chip_and_handler(irq, &sa1111_irq_chip, handle_edge_irq);
- irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
-
- return 0;
-}
-
-static const struct irq_domain_ops sa1111_irqdomain_ops = {
- .map = sa1111_irqdomain_map,
- .xlate = irq_domain_xlate_twocell,
-};
-
-static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base)
-{
- void __iomem *irqbase = sachip->base + SA1111_INTC;
- int ret;
-
- /*
- * We're guaranteed that this region hasn't been taken.
- */
- request_mem_region(sachip->phys + SA1111_INTC, 512, "irq");
-
- ret = irq_alloc_descs(-1, irq_base, SA1111_IRQ_NR, -1);
- if (ret <= 0) {
- dev_err(sachip->dev, "unable to allocate %u irqs: %d\n",
- SA1111_IRQ_NR, ret);
- if (ret == 0)
- ret = -EINVAL;
- return ret;
- }
-
- sachip->irq_base = ret;
-
- /* disable all IRQs */
- writel_relaxed(0, irqbase + SA1111_INTEN0);
- writel_relaxed(0, irqbase + SA1111_INTEN1);
- writel_relaxed(0, irqbase + SA1111_WAKEEN0);
- writel_relaxed(0, irqbase + SA1111_WAKEEN1);
-
- /*
- * detect on rising edge. Note: Feb 2001 Errata for SA1111
- * specifies that S0ReadyInt and S1ReadyInt should be '1'.
- */
- writel_relaxed(0, irqbase + SA1111_INTPOL0);
- writel_relaxed(BIT(IRQ_S0_READY_NINT & 31) |
- BIT(IRQ_S1_READY_NINT & 31),
- irqbase + SA1111_INTPOL1);
-
- /* clear all IRQs */
- writel_relaxed(~0, irqbase + SA1111_INTSTATCLR0);
- writel_relaxed(~0, irqbase + SA1111_INTSTATCLR1);
-
- sachip->irqdomain = irq_domain_create_linear(NULL, SA1111_IRQ_NR,
- &sa1111_irqdomain_ops,
- sachip);
- if (!sachip->irqdomain) {
- irq_free_descs(sachip->irq_base, SA1111_IRQ_NR);
- return -ENOMEM;
- }
-
- irq_domain_associate_many(sachip->irqdomain,
- sachip->irq_base + IRQ_GPAIN0,
- IRQ_GPAIN0, SSPROR + 1 - IRQ_GPAIN0);
- irq_domain_associate_many(sachip->irqdomain,
- sachip->irq_base + AUDXMTDMADONEA,
- AUDXMTDMADONEA,
- IRQ_S1_BVD1_STSCHG + 1 - AUDXMTDMADONEA);
-
- /*
- * Register SA1111 interrupt
- */
- irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
- irq_set_chained_handler_and_data(sachip->irq, sa1111_irq_handler,
- sachip);
-
- dev_info(sachip->dev, "Providing IRQ%u-%u\n",
- sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1);
-
- return 0;
-}
-
-static void sa1111_remove_irq(struct sa1111 *sachip)
-{
- struct irq_domain *domain = sachip->irqdomain;
- void __iomem *irqbase = sachip->base + SA1111_INTC;
- int i;
-
- /* disable all IRQs */
- writel_relaxed(0, irqbase + SA1111_INTEN0);
- writel_relaxed(0, irqbase + SA1111_INTEN1);
- writel_relaxed(0, irqbase + SA1111_WAKEEN0);
- writel_relaxed(0, irqbase + SA1111_WAKEEN1);
-
- irq_set_chained_handler_and_data(sachip->irq, NULL, NULL);
- for (i = 0; i < SA1111_IRQ_NR; i++)
- irq_dispose_mapping(irq_find_mapping(domain, i));
- irq_domain_remove(domain);
-
- release_mem_region(sachip->phys + SA1111_INTC, 512);
-}
-
-enum {
- SA1111_GPIO_PXDDR = (SA1111_GPIO_PADDR - SA1111_GPIO_PADDR),
- SA1111_GPIO_PXDRR = (SA1111_GPIO_PADRR - SA1111_GPIO_PADDR),
- SA1111_GPIO_PXDWR = (SA1111_GPIO_PADWR - SA1111_GPIO_PADDR),
- SA1111_GPIO_PXSDR = (SA1111_GPIO_PASDR - SA1111_GPIO_PADDR),
- SA1111_GPIO_PXSSR = (SA1111_GPIO_PASSR - SA1111_GPIO_PADDR),
-};
-
-static struct sa1111 *gc_to_sa1111(struct gpio_chip *gc)
-{
- return container_of(gc, struct sa1111, gc);
-}
-
-static void __iomem *sa1111_gpio_map_reg(struct sa1111 *sachip, unsigned offset)
-{
- void __iomem *reg = sachip->base + SA1111_GPIO;
-
- if (offset < 4)
- return reg + SA1111_GPIO_PADDR;
- if (offset < 10)
- return reg + SA1111_GPIO_PBDDR;
- if (offset < 18)
- return reg + SA1111_GPIO_PCDDR;
- return NULL;
-}
-
-static u32 sa1111_gpio_map_bit(unsigned offset)
-{
- if (offset < 4)
- return BIT(offset);
- if (offset < 10)
- return BIT(offset - 4);
- if (offset < 18)
- return BIT(offset - 10);
- return 0;
-}
-
-static void sa1111_gpio_modify(void __iomem *reg, u32 mask, u32 set)
-{
- u32 val;
-
- val = readl_relaxed(reg);
- val &= ~mask;
- val |= mask & set;
- writel_relaxed(val, reg);
-}
-
-static int sa1111_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
-{
- struct sa1111 *sachip = gc_to_sa1111(gc);
- void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
- u32 mask = sa1111_gpio_map_bit(offset);
-
- return !!(readl_relaxed(reg + SA1111_GPIO_PXDDR) & mask);
-}
-
-static int sa1111_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
-{
- struct sa1111 *sachip = gc_to_sa1111(gc);
- unsigned long flags;
- void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
- u32 mask = sa1111_gpio_map_bit(offset);
-
- spin_lock_irqsave(&sachip->lock, flags);
- sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, mask);
- sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, mask);
- spin_unlock_irqrestore(&sachip->lock, flags);
-
- return 0;
-}
-
-static int sa1111_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
- int value)
-{
- struct sa1111 *sachip = gc_to_sa1111(gc);
- unsigned long flags;
- void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
- u32 mask = sa1111_gpio_map_bit(offset);
-
- spin_lock_irqsave(&sachip->lock, flags);
- sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0);
- sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0);
- sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, 0);
- sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, 0);
- spin_unlock_irqrestore(&sachip->lock, flags);
-
- return 0;
-}
-
-static int sa1111_gpio_get(struct gpio_chip *gc, unsigned offset)
-{
- struct sa1111 *sachip = gc_to_sa1111(gc);
- void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
- u32 mask = sa1111_gpio_map_bit(offset);
-
- return !!(readl_relaxed(reg + SA1111_GPIO_PXDRR) & mask);
-}
-
-static int sa1111_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
-{
- struct sa1111 *sachip = gc_to_sa1111(gc);
- unsigned long flags;
- void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
- u32 mask = sa1111_gpio_map_bit(offset);
-
- spin_lock_irqsave(&sachip->lock, flags);
- sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0);
- sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0);
- spin_unlock_irqrestore(&sachip->lock, flags);
-
- return 0;
-}
-
-static int sa1111_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
- unsigned long *bits)
-{
- struct sa1111 *sachip = gc_to_sa1111(gc);
- unsigned long flags;
- void __iomem *reg = sachip->base + SA1111_GPIO;
- u32 msk, val;
-
- msk = *mask;
- val = *bits;
-
- spin_lock_irqsave(&sachip->lock, flags);
- sa1111_gpio_modify(reg + SA1111_GPIO_PADWR, msk & 15, val);
- sa1111_gpio_modify(reg + SA1111_GPIO_PASSR, msk & 15, val);
- sa1111_gpio_modify(reg + SA1111_GPIO_PBDWR, (msk >> 4) & 255, val >> 4);
- sa1111_gpio_modify(reg + SA1111_GPIO_PBSSR, (msk >> 4) & 255, val >> 4);
- sa1111_gpio_modify(reg + SA1111_GPIO_PCDWR, (msk >> 12) & 255, val >> 12);
- sa1111_gpio_modify(reg + SA1111_GPIO_PCSSR, (msk >> 12) & 255, val >> 12);
- spin_unlock_irqrestore(&sachip->lock, flags);
-
- return 0;
-}
-
-static int sa1111_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
-{
- struct sa1111 *sachip = gc_to_sa1111(gc);
-
- return sa1111_map_irq(sachip, offset);
-}
-
-static int sa1111_setup_gpios(struct sa1111 *sachip)
-{
- sachip->gc.label = "sa1111";
- sachip->gc.parent = sachip->dev;
- sachip->gc.owner = THIS_MODULE;
- sachip->gc.get_direction = sa1111_gpio_get_direction;
- sachip->gc.direction_input = sa1111_gpio_direction_input;
- sachip->gc.direction_output = sa1111_gpio_direction_output;
- sachip->gc.get = sa1111_gpio_get;
- sachip->gc.set = sa1111_gpio_set;
- sachip->gc.set_multiple = sa1111_gpio_set_multiple;
- sachip->gc.to_irq = sa1111_gpio_to_irq;
- sachip->gc.base = -1;
- sachip->gc.ngpio = 18;
-
- return devm_gpiochip_add_data(sachip->dev, &sachip->gc, sachip);
-}
-
-/*
- * Bring the SA1111 out of reset. This requires a set procedure:
- * 1. nRESET asserted (by hardware)
- * 2. CLK turned on from SA1110
- * 3. nRESET deasserted
- * 4. VCO turned on, PLL_BYPASS turned off
- * 5. Wait lock time, then assert RCLKEn
- * 7. PCR set to allow clocking of individual functions
- *
- * Until we've done this, the only registers we can access are:
- * SBI_SKCR
- * SBI_SMCR
- * SBI_SKID
- */
-static void sa1111_wake(struct sa1111 *sachip)
-{
- unsigned long flags, r;
-
- spin_lock_irqsave(&sachip->lock, flags);
-
- clk_enable(sachip->clk);
-
- /*
- * Turn VCO on, and disable PLL Bypass.
- */
- r = readl_relaxed(sachip->base + SA1111_SKCR);
- r &= ~SKCR_VCO_OFF;
- writel_relaxed(r, sachip->base + SA1111_SKCR);
- r |= SKCR_PLL_BYPASS | SKCR_OE_EN;
- writel_relaxed(r, sachip->base + SA1111_SKCR);
-
- /*
- * Wait lock time. SA1111 manual _doesn't_
- * specify a figure for this! We choose 100us.
- */
- udelay(100);
-
- /*
- * Enable RCLK. We also ensure that RDYEN is set.
- */
- r |= SKCR_RCLKEN | SKCR_RDYEN;
- writel_relaxed(r, sachip->base + SA1111_SKCR);
-
- /*
- * Wait 14 RCLK cycles for the chip to finish coming out
- * of reset. (RCLK=24MHz). This is 590ns.
- */
- udelay(1);
-
- /*
- * Ensure all clocks are initially off.
- */
- writel_relaxed(0, sachip->base + SA1111_SKPCR);
-
- spin_unlock_irqrestore(&sachip->lock, flags);
-}
-
-#ifdef CONFIG_ARCH_SA1100
-
-static u32 sa1111_dma_mask[] = {
- ~0,
- ~(1 << 20),
- ~(1 << 23),
- ~(1 << 24),
- ~(1 << 25),
- ~(1 << 20),
- ~(1 << 20),
- 0,
-};
-
-/*
- * Configure the SA1111 shared memory controller.
- */
-static void
-sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac,
- unsigned int cas_latency)
-{
- unsigned int smcr = SMCR_DTIM | SMCR_MBGE | FInsrt(drac, SMCR_DRAC);
-
- if (cas_latency == 3)
- smcr |= SMCR_CLAT;
-
- writel_relaxed(smcr, sachip->base + SA1111_SMCR);
-
- /*
- * Now clear the bits in the DMA mask to work around the SA1111
- * DMA erratum (Intel StrongARM SA-1111 Microprocessor Companion
- * Chip Specification Update, June 2000, Erratum #7).
- */
- if (sachip->dev->dma_mask)
- *sachip->dev->dma_mask &= sa1111_dma_mask[drac >> 2];
-
- sachip->dev->coherent_dma_mask &= sa1111_dma_mask[drac >> 2];
-}
-#endif
-
-static void sa1111_dev_release(struct device *_dev)
-{
- struct sa1111_dev *dev = to_sa1111_device(_dev);
-
- kfree(dev);
-}
-
-static int
-sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent,
- struct sa1111_dev_info *info)
-{
- struct sa1111_dev *dev;
- unsigned i;
- int ret;
-
- dev = kzalloc_obj(struct sa1111_dev);
- if (!dev) {
- ret = -ENOMEM;
- goto err_alloc;
- }
-
- device_initialize(&dev->dev);
- dev_set_name(&dev->dev, "%4.4lx", info->offset);
- dev->devid = info->devid;
- dev->dev.parent = sachip->dev;
- dev->dev.bus = &sa1111_bus_type;
- dev->dev.release = sa1111_dev_release;
- dev->res.start = sachip->phys + info->offset;
- dev->res.end = dev->res.start + 511;
- dev->res.name = dev_name(&dev->dev);
- dev->res.flags = IORESOURCE_MEM;
- dev->mapbase = sachip->base + info->offset;
- dev->skpcr_mask = info->skpcr_mask;
-
- for (i = 0; i < ARRAY_SIZE(info->hwirq); i++)
- dev->hwirq[i] = info->hwirq[i];
-
- /*
- * If the parent device has a DMA mask associated with it, and
- * this child supports DMA, propagate it down to the children.
- */
- if (info->dma && sachip->dev->dma_mask) {
- dev->dma_mask = *sachip->dev->dma_mask;
- dev->dev.dma_mask = &dev->dma_mask;
- dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask;
- }
-
- ret = request_resource(parent, &dev->res);
- if (ret) {
- dev_err(sachip->dev, "failed to allocate resource for %s\n",
- dev->res.name);
- goto err_resource;
- }
-
- ret = device_add(&dev->dev);
- if (ret)
- goto err_add;
- return 0;
-
- err_add:
- release_resource(&dev->res);
- err_resource:
- put_device(&dev->dev);
- err_alloc:
- return ret;
-}
-
-static int __sa1111_probe(struct device *me, struct resource *mem, int irq)
-{
- struct sa1111_platform_data *pd = me->platform_data;
- struct sa1111 *sachip;
- unsigned long id;
- unsigned int has_devs;
- int i, ret = -ENODEV;
-
- if (!pd)
- return -EINVAL;
-
- sachip = devm_kzalloc(me, sizeof(struct sa1111), GFP_KERNEL);
- if (!sachip)
- return -ENOMEM;
-
- sachip->clk = devm_clk_get(me, "SA1111_CLK");
- if (IS_ERR(sachip->clk))
- return PTR_ERR(sachip->clk);
-
- ret = clk_prepare(sachip->clk);
- if (ret)
- return ret;
-
- spin_lock_init(&sachip->lock);
-
- sachip->dev = me;
- dev_set_drvdata(sachip->dev, sachip);
-
- sachip->pdata = pd;
- sachip->phys = mem->start;
- sachip->irq = irq;
-
- /*
- * Map the whole region. This also maps the
- * registers for our children.
- */
- sachip->base = ioremap(mem->start, PAGE_SIZE * 2);
- if (!sachip->base) {
- ret = -ENOMEM;
- goto err_clk_unprep;
- }
-
- /*
- * Probe for the chip. Only touch the SBI registers.
- */
- id = readl_relaxed(sachip->base + SA1111_SKID);
- if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
- printk(KERN_DEBUG "SA1111 not detected: ID = %08lx\n", id);
- ret = -ENODEV;
- goto err_unmap;
- }
-
- pr_info("SA1111 Microprocessor Companion Chip: silicon revision %lx, metal revision %lx\n",
- (id & SKID_SIREV_MASK) >> 4, id & SKID_MTREV_MASK);
-
- /*
- * We found it. Wake the chip up, and initialise.
- */
- sa1111_wake(sachip);
-
- /*
- * The interrupt controller must be initialised before any
- * other device to ensure that the interrupts are available.
- */
- ret = sa1111_setup_irq(sachip, pd->irq_base);
- if (ret)
- goto err_clk;
-
- /* Setup the GPIOs - should really be done after the IRQ setup */
- ret = sa1111_setup_gpios(sachip);
- if (ret)
- goto err_irq;
-
-#ifdef CONFIG_ARCH_SA1100
- {
- unsigned int val;
-
- /*
- * The SDRAM configuration of the SA1110 and the SA1111 must
- * match. This is very important to ensure that SA1111 accesses
- * don't corrupt the SDRAM. Note that this ungates the SA1111's
- * MBGNT signal, so we must have called sa1110_mb_disable()
- * beforehand.
- */
- sa1111_configure_smc(sachip, 1,
- FExtr(MDCNFG, MDCNFG_SA1110_DRAC0),
- FExtr(MDCNFG, MDCNFG_SA1110_TDL0));
-
- /*
- * We only need to turn on DCLK whenever we want to use the
- * DMA. It can otherwise be held firmly in the off position.
- * (currently, we always enable it.)
- */
- val = readl_relaxed(sachip->base + SA1111_SKPCR);
- writel_relaxed(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR);
-
- /*
- * Enable the SA1110 memory bus request and grant signals.
- */
- sa1110_mb_enable();
- }
-#endif
-
- g_sa1111 = sachip;
-
- has_devs = ~0;
- if (pd)
- has_devs &= ~pd->disable_devs;
-
- for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++)
- if (sa1111_devices[i].devid & has_devs)
- sa1111_init_one_child(sachip, mem, &sa1111_devices[i]);
-
- return 0;
-
- err_irq:
- sa1111_remove_irq(sachip);
- err_clk:
- clk_disable(sachip->clk);
- err_unmap:
- iounmap(sachip->base);
- err_clk_unprep:
- clk_unprepare(sachip->clk);
- return ret;
-}
-
-static int sa1111_remove_one(struct device *dev, void *data)
-{
- struct sa1111_dev *sadev = to_sa1111_device(dev);
- if (dev->bus != &sa1111_bus_type)
- return 0;
- device_del(&sadev->dev);
- release_resource(&sadev->res);
- put_device(&sadev->dev);
- return 0;
-}
-
-static void __sa1111_remove(struct sa1111 *sachip)
-{
- device_for_each_child(sachip->dev, NULL, sa1111_remove_one);
-
- sa1111_remove_irq(sachip);
-
- clk_disable(sachip->clk);
- clk_unprepare(sachip->clk);
-
- iounmap(sachip->base);
-}
-
-struct sa1111_save_data {
- unsigned int skcr;
- unsigned int skpcr;
- unsigned int skcdr;
- unsigned char skaud;
- unsigned char skpwm0;
- unsigned char skpwm1;
-
- /*
- * Interrupt controller
- */
- unsigned int intpol0;
- unsigned int intpol1;
- unsigned int inten0;
- unsigned int inten1;
- unsigned int wakepol0;
- unsigned int wakepol1;
- unsigned int wakeen0;
- unsigned int wakeen1;
-};
-
-#ifdef CONFIG_PM
-
-static int sa1111_suspend_noirq(struct device *dev)
-{
- struct sa1111 *sachip = dev_get_drvdata(dev);
- struct sa1111_save_data *save;
- unsigned long flags;
- unsigned int val;
- void __iomem *base;
-
- save = kmalloc_obj(struct sa1111_save_data);
- if (!save)
- return -ENOMEM;
- sachip->saved_state = save;
-
- spin_lock_irqsave(&sachip->lock, flags);
-
- /*
- * Save state.
- */
- base = sachip->base;
- save->skcr = readl_relaxed(base + SA1111_SKCR);
- save->skpcr = readl_relaxed(base + SA1111_SKPCR);
- save->skcdr = readl_relaxed(base + SA1111_SKCDR);
- save->skaud = readl_relaxed(base + SA1111_SKAUD);
- save->skpwm0 = readl_relaxed(base + SA1111_SKPWM0);
- save->skpwm1 = readl_relaxed(base + SA1111_SKPWM1);
-
- writel_relaxed(0, sachip->base + SA1111_SKPWM0);
- writel_relaxed(0, sachip->base + SA1111_SKPWM1);
-
- base = sachip->base + SA1111_INTC;
- save->intpol0 = readl_relaxed(base + SA1111_INTPOL0);
- save->intpol1 = readl_relaxed(base + SA1111_INTPOL1);
- save->inten0 = readl_relaxed(base + SA1111_INTEN0);
- save->inten1 = readl_relaxed(base + SA1111_INTEN1);
- save->wakepol0 = readl_relaxed(base + SA1111_WAKEPOL0);
- save->wakepol1 = readl_relaxed(base + SA1111_WAKEPOL1);
- save->wakeen0 = readl_relaxed(base + SA1111_WAKEEN0);
- save->wakeen1 = readl_relaxed(base + SA1111_WAKEEN1);
-
- /*
- * Disable.
- */
- val = readl_relaxed(sachip->base + SA1111_SKCR);
- writel_relaxed(val | SKCR_SLEEP, sachip->base + SA1111_SKCR);
-
- clk_disable(sachip->clk);
-
- spin_unlock_irqrestore(&sachip->lock, flags);
-
-#ifdef CONFIG_ARCH_SA1100
- sa1110_mb_disable();
-#endif
-
- return 0;
-}
-
-/*
- * sa1111_resume - Restore the SA1111 device state.
- * @dev: device to restore
- *
- * Restore the general state of the SA1111; clock control and
- * interrupt controller. Other parts of the SA1111 must be
- * restored by their respective drivers, and must be called
- * via LDM after this function.
- */
-static int sa1111_resume_noirq(struct device *dev)
-{
- struct sa1111 *sachip = dev_get_drvdata(dev);
- struct sa1111_save_data *save;
- unsigned long flags, id;
- void __iomem *base;
-
- save = sachip->saved_state;
- if (!save)
- return 0;
-
- /*
- * Ensure that the SA1111 is still here.
- * FIXME: shouldn't do this here.
- */
- id = readl_relaxed(sachip->base + SA1111_SKID);
- if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
- __sa1111_remove(sachip);
- dev_set_drvdata(dev, NULL);
- kfree(save);
- return 0;
- }
-
- /*
- * First of all, wake up the chip.
- */
- sa1111_wake(sachip);
-
-#ifdef CONFIG_ARCH_SA1100
- /* Enable the memory bus request/grant signals */
- sa1110_mb_enable();
-#endif
-
- /*
- * Only lock for write ops. Also, sa1111_wake must be called with
- * released spinlock!
- */
- spin_lock_irqsave(&sachip->lock, flags);
-
- writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN0);
- writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN1);
-
- base = sachip->base;
- writel_relaxed(save->skcr, base + SA1111_SKCR);
- writel_relaxed(save->skpcr, base + SA1111_SKPCR);
- writel_relaxed(save->skcdr, base + SA1111_SKCDR);
- writel_relaxed(save->skaud, base + SA1111_SKAUD);
- writel_relaxed(save->skpwm0, base + SA1111_SKPWM0);
- writel_relaxed(save->skpwm1, base + SA1111_SKPWM1);
-
- base = sachip->base + SA1111_INTC;
- writel_relaxed(save->intpol0, base + SA1111_INTPOL0);
- writel_relaxed(save->intpol1, base + SA1111_INTPOL1);
- writel_relaxed(save->inten0, base + SA1111_INTEN0);
- writel_relaxed(save->inten1, base + SA1111_INTEN1);
- writel_relaxed(save->wakepol0, base + SA1111_WAKEPOL0);
- writel_relaxed(save->wakepol1, base + SA1111_WAKEPOL1);
- writel_relaxed(save->wakeen0, base + SA1111_WAKEEN0);
- writel_relaxed(save->wakeen1, base + SA1111_WAKEEN1);
-
- spin_unlock_irqrestore(&sachip->lock, flags);
-
- sachip->saved_state = NULL;
- kfree(save);
-
- return 0;
-}
-
-#else
-#define sa1111_suspend_noirq NULL
-#define sa1111_resume_noirq NULL
-#endif
-
-/**
- * sa1111_probe - probe for a single SA1111 chip.
- * @pdev: platform device.
- *
- * Probe for a SA1111 chip. This must be called
- * before any other SA1111-specific code.
- *
- * Returns:
- * * %-ENODEV - device not found.
- * * %-ENOMEM - memory allocation failure.
- * * %-EBUSY - physical address already marked in-use.
- * * %-EINVAL - no platform data passed
- * * %0 - successful.
- */
-static int sa1111_probe(struct platform_device *pdev)
-{
- struct resource *mem;
- int irq;
-
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!mem)
- return -EINVAL;
- irq = platform_get_irq(pdev, 0);
- if (irq < 0)
- return irq;
-
- return __sa1111_probe(&pdev->dev, mem, irq);
-}
-
-static void sa1111_remove(struct platform_device *pdev)
-{
- struct sa1111 *sachip = platform_get_drvdata(pdev);
-
- if (sachip) {
-#ifdef CONFIG_PM
- kfree(sachip->saved_state);
- sachip->saved_state = NULL;
-#endif
- __sa1111_remove(sachip);
- platform_set_drvdata(pdev, NULL);
- }
-}
-
-static struct dev_pm_ops sa1111_pm_ops = {
- .suspend_noirq = sa1111_suspend_noirq,
- .resume_noirq = sa1111_resume_noirq,
-};
-
-/*
- * Not sure if this should be on the system bus or not yet.
- * We really want some way to register a system device at
- * the per-machine level, and then have this driver pick
- * up the registered devices.
- *
- * We also need to handle the SDRAM configuration for
- * PXA250/SA1110 machine classes.
- */
-static struct platform_driver sa1111_device_driver = {
- .probe = sa1111_probe,
- .remove = sa1111_remove,
- .driver = {
- .name = "sa1111",
- .pm = &sa1111_pm_ops,
- },
-};
-
-/*
- * Get the parent device driver (us) structure
- * from a child function device
- */
-static inline struct sa1111 *sa1111_chip_driver(struct sa1111_dev *sadev)
-{
- return (struct sa1111 *)dev_get_drvdata(sadev->dev.parent);
-}
-
-/*
- * The bits in the opdiv field are non-linear.
- */
-static unsigned char opdiv_table[] = { 1, 4, 2, 8 };
-
-static unsigned int __sa1111_pll_clock(struct sa1111 *sachip)
-{
- unsigned int skcdr, fbdiv, ipdiv, opdiv;
-
- skcdr = readl_relaxed(sachip->base + SA1111_SKCDR);
-
- fbdiv = (skcdr & 0x007f) + 2;
- ipdiv = ((skcdr & 0x0f80) >> 7) + 2;
- opdiv = opdiv_table[(skcdr & 0x3000) >> 12];
-
- return 3686400 * fbdiv / (ipdiv * opdiv);
-}
-
-/**
- * sa1111_pll_clock - return the current PLL clock frequency.
- * @sadev: SA1111 function block
- *
- * BUG: we should look at SKCR. We also blindly believe that
- * the chip is being fed with the 3.6864MHz clock.
- *
- * Returns the PLL clock in Hz.
- */
-unsigned int sa1111_pll_clock(struct sa1111_dev *sadev)
-{
- struct sa1111 *sachip = sa1111_chip_driver(sadev);
-
- return __sa1111_pll_clock(sachip);
-}
-EXPORT_SYMBOL(sa1111_pll_clock);
-
-/**
- * sa1111_select_audio_mode - select I2S or AC link mode
- * @sadev: SA1111 function block
- * @mode: One of %SA1111_AUDIO_ACLINK or %SA1111_AUDIO_I2S
- *
- * Frob the SKCR to select AC Link mode or I2S mode for
- * the audio block.
- */
-void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode)
-{
- struct sa1111 *sachip = sa1111_chip_driver(sadev);
- unsigned long flags;
- unsigned int val;
-
- spin_lock_irqsave(&sachip->lock, flags);
-
- val = readl_relaxed(sachip->base + SA1111_SKCR);
- if (mode == SA1111_AUDIO_I2S) {
- val &= ~SKCR_SELAC;
- } else {
- val |= SKCR_SELAC;
- }
- writel_relaxed(val, sachip->base + SA1111_SKCR);
-
- spin_unlock_irqrestore(&sachip->lock, flags);
-}
-EXPORT_SYMBOL(sa1111_select_audio_mode);
-
-/**
- * sa1111_set_audio_rate - set the audio sample rate
- * @sadev: SA1111 SAC function block
- * @rate: sample rate to select
- */
-int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate)
-{
- struct sa1111 *sachip = sa1111_chip_driver(sadev);
- unsigned int div;
-
- if (sadev->devid != SA1111_DEVID_SAC)
- return -EINVAL;
-
- div = (__sa1111_pll_clock(sachip) / 256 + rate / 2) / rate;
- if (div == 0)
- div = 1;
- if (div > 128)
- div = 128;
-
- writel_relaxed(div - 1, sachip->base + SA1111_SKAUD);
-
- return 0;
-}
-EXPORT_SYMBOL(sa1111_set_audio_rate);
-
-/**
- * sa1111_get_audio_rate - get the audio sample rate
- * @sadev: SA1111 SAC function block device
- */
-int sa1111_get_audio_rate(struct sa1111_dev *sadev)
-{
- struct sa1111 *sachip = sa1111_chip_driver(sadev);
- unsigned long div;
-
- if (sadev->devid != SA1111_DEVID_SAC)
- return -EINVAL;
-
- div = readl_relaxed(sachip->base + SA1111_SKAUD) + 1;
-
- return __sa1111_pll_clock(sachip) / (256 * div);
-}
-EXPORT_SYMBOL(sa1111_get_audio_rate);
-
-/*
- * Individual device operations.
- */
-
-/**
- * sa1111_enable_device - enable an on-chip SA1111 function block
- * @sadev: SA1111 function block device to enable
- */
-int sa1111_enable_device(struct sa1111_dev *sadev)
-{
- struct sa1111 *sachip = sa1111_chip_driver(sadev);
- unsigned long flags;
- unsigned int val;
- int ret = 0;
-
- if (sachip->pdata && sachip->pdata->enable)
- ret = sachip->pdata->enable(sachip->pdata->data, sadev->devid);
-
- if (ret == 0) {
- spin_lock_irqsave(&sachip->lock, flags);
- val = readl_relaxed(sachip->base + SA1111_SKPCR);
- writel_relaxed(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
- spin_unlock_irqrestore(&sachip->lock, flags);
- }
- return ret;
-}
-EXPORT_SYMBOL(sa1111_enable_device);
-
-/**
- * sa1111_disable_device - disable an on-chip SA1111 function block
- * @sadev: SA1111 function block device to disable
- */
-void sa1111_disable_device(struct sa1111_dev *sadev)
-{
- struct sa1111 *sachip = sa1111_chip_driver(sadev);
- unsigned long flags;
- unsigned int val;
-
- spin_lock_irqsave(&sachip->lock, flags);
- val = readl_relaxed(sachip->base + SA1111_SKPCR);
- writel_relaxed(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
- spin_unlock_irqrestore(&sachip->lock, flags);
-
- if (sachip->pdata && sachip->pdata->disable)
- sachip->pdata->disable(sachip->pdata->data, sadev->devid);
-}
-EXPORT_SYMBOL(sa1111_disable_device);
-
-int sa1111_get_irq(struct sa1111_dev *sadev, unsigned num)
-{
- struct sa1111 *sachip = sa1111_chip_driver(sadev);
- if (num >= ARRAY_SIZE(sadev->hwirq))
- return -EINVAL;
- return sa1111_map_irq(sachip, sadev->hwirq[num]);
-}
-EXPORT_SYMBOL_GPL(sa1111_get_irq);
-
-/*
- * SA1111 "Register Access Bus."
- *
- * We model this as a regular bus type, and hang devices directly
- * off this.
- */
-static int sa1111_match(struct device *_dev, const struct device_driver *_drv)
-{
- struct sa1111_dev *dev = to_sa1111_device(_dev);
- const struct sa1111_driver *drv = SA1111_DRV(_drv);
-
- return !!(dev->devid & drv->devid);
-}
-
-static int sa1111_bus_probe(struct device *dev)
-{
- struct sa1111_dev *sadev = to_sa1111_device(dev);
- struct sa1111_driver *drv = SA1111_DRV(dev->driver);
- int ret = -ENODEV;
-
- if (drv->probe)
- ret = drv->probe(sadev);
- return ret;
-}
-
-static void sa1111_bus_remove(struct device *dev)
-{
- struct sa1111_dev *sadev = to_sa1111_device(dev);
- struct sa1111_driver *drv = SA1111_DRV(dev->driver);
-
- if (drv->remove)
- drv->remove(sadev);
-}
-
-const struct bus_type sa1111_bus_type = {
- .name = "sa1111-rab",
- .match = sa1111_match,
- .probe = sa1111_bus_probe,
- .remove = sa1111_bus_remove,
-};
-EXPORT_SYMBOL(sa1111_bus_type);
-
-int sa1111_driver_register(struct sa1111_driver *driver)
-{
- driver->drv.bus = &sa1111_bus_type;
- return driver_register(&driver->drv);
-}
-EXPORT_SYMBOL(sa1111_driver_register);
-
-void sa1111_driver_unregister(struct sa1111_driver *driver)
-{
- driver_unregister(&driver->drv);
-}
-EXPORT_SYMBOL(sa1111_driver_unregister);
-
-static int __init sa1111_init(void)
-{
- int ret = bus_register(&sa1111_bus_type);
- if (ret == 0)
- platform_driver_register(&sa1111_device_driver);
- return ret;
-}
-
-static void __exit sa1111_exit(void)
-{
- platform_driver_unregister(&sa1111_device_driver);
- bus_unregister(&sa1111_bus_type);
-}
-
-subsys_initcall(sa1111_init);
-module_exit(sa1111_exit);
-
-MODULE_DESCRIPTION("Intel Corporation SA1111 core driver");
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/configs/assabet_defconfig b/arch/arm/configs/assabet_defconfig
deleted file mode 100644
index e4264fdac2e5..000000000000
--- a/arch/arm/configs/assabet_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_ARCH_MULTI_V4=y
-# CONFIG_ARCH_MULTI_V7 is not set
-CONFIG_ARCH_SA1100=y
-CONFIG_SA1100_ASSABET=y
-# CONFIG_AEABI is not set
-CONFIG_ATAGS=y
-CONFIG_CMDLINE="mem=32M console=ttySA0,38400n8 initrd=0xc0800000,3M root=/dev/ram"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_MODULES=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IPV6 is not set
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_SA1100=y
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I1 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_SA1100=y
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_PCMCIA=y
-CONFIG_PCMCIA_PCNET=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=m
-CONFIG_SERIAL_SA1100=y
-CONFIG_SERIAL_SA1100_CONSOLE=y
-CONFIG_FB=y
-CONFIG_FB_SA1100=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig
deleted file mode 100644
index 570a5f8bc57b..000000000000
--- a/arch/arm/configs/collie_defconfig
+++ /dev/null
@@ -1,87 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-CONFIG_BASE_SMALL=y
-# CONFIG_EPOLL is not set
-CONFIG_ARCH_MULTI_V4=y
-# CONFIG_ARCH_MULTI_V7 is not set
-CONFIG_ARCH_SA1100=y
-CONFIG_SA1100_COLLIE=y
-CONFIG_ATAGS=y
-CONFIG_CMDLINE="noinitrd root=/dev/mtdblock2 rootfstype=jffs2 fbcon=rotate:1"
-CONFIG_PM=y
-# CONFIG_SWAP is not set
-CONFIG_SLUB_TINY=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IPV6 is not set
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_SA1100=y
-CONFIG_PCMCIA_DEBUG=y
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set
-# CONFIG_MTD_CFI_I1 is not set
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_CFI_I4=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_SA1100=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=1024
-CONFIG_BLK_DEV_SD=y
-CONFIG_ATA=y
-CONFIG_PATA_PCMCIA=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_LOCOMO=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CS=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_SA1100=y
-CONFIG_SERIAL_SA1100_CONSOLE=y
-# CONFIG_HWMON is not set
-CONFIG_MCP_SA11X0=y
-CONFIG_MCP_UCB1200=y
-CONFIG_MCP_UCB1200_TS=y
-CONFIG_FB=y
-CONFIG_FB_SA1100=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_LOCOMO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_DISK=y
-# CONFIG_DNOTIFY is not set
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_FONTS=y
-CONFIG_FONT_MINI_4x6=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DETECT_SOFTLOCKUP is not set
-CONFIG_DEBUG_MUTEXES=y
diff --git a/arch/arm/configs/h3600_defconfig b/arch/arm/configs/h3600_defconfig
deleted file mode 100644
index 3e8da62d959d..000000000000
--- a/arch/arm/configs/h3600_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_ARCH_MULTI_V4=y
-# CONFIG_ARCH_MULTI_V7 is not set
-CONFIG_ARCH_SA1100=y
-CONFIG_SA1100_H3600=y
-# CONFIG_CPU_FREQ_STAT is not set
-CONFIG_ATAGS=y
-CONFIG_MODULES=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_SA1100=y
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I1 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_SA1100=y
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_SD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ATA=y
-CONFIG_PATA_PCMCIA=y
-CONFIG_NETDEVICES=y
-CONFIG_PCMCIA_PCNET=y
-CONFIG_PPP=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_ASYNC=m
-# CONFIG_WLAN is not set
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_SA1100=y
-CONFIG_SERIAL_SA1100_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_SA1100=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=m
-CONFIG_NFS_FS=y
-CONFIG_NFSD=m
-CONFIG_NLS=y
diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig
deleted file mode 100644
index a96cfb81aba5..000000000000
--- a/arch/arm/configs/jornada720_defconfig
+++ /dev/null
@@ -1,95 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EXPERT=y
-CONFIG_ARCH_MULTI_V4=y
-# CONFIG_ARCH_MULTI_V7 is not set
-CONFIG_ARCH_SA1100=y
-CONFIG_SA1100_JORNADA720=y
-CONFIG_SA1100_JORNADA720_SSP=y
-CONFIG_PM=y
-CONFIG_ATAGS=y
-CONFIG_MODULES=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_SA1100=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ATA=y
-CONFIG_PATA_PCMCIA=y
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=y
-CONFIG_NET_PCMCIA=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_HP7XX=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_HP7XX=y
-CONFIG_LEGACY_PTY_COUNT=32
-CONFIG_SERIAL_SA1100=y
-CONFIG_SERIAL_SA1100_CONSOLE=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_S1D13XXX=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_SA1100=y
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/neponset_defconfig b/arch/arm/configs/neponset_defconfig
deleted file mode 100644
index 164643f1b6c0..000000000000
--- a/arch/arm/configs/neponset_defconfig
+++ /dev/null
@@ -1,88 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_ARCH_MULTI_V4=y
-# CONFIG_ARCH_MULTI_V7 is not set
-CONFIG_ARCH_SA1100=y
-CONFIG_SA1100_ASSABET=y
-CONFIG_ASSABET_NEPONSET=y
-CONFIG_ATAGS=y
-CONFIG_ZBOOT_ROM_TEXT=0x80000
-CONFIG_ZBOOT_ROM_BSS=0xc1000000
-CONFIG_ZBOOT_ROM=y
-CONFIG_CMDLINE="console=ttySA0,38400n8 cpufreq=221200 rw root=/dev/mtdblock2 mtdparts=sa1100:512K(boot),1M(kernel),2560K(initrd),4M(root) mem=32M noinitrd initrd=0xc0800000,3M"
-CONFIG_FPE_NWFPE=y
-# CONFIG_AEABI is not set
-CONFIG_PM=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_MSDOS_PARTITION is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IPV6 is not set
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_SA1100=y
-CONFIG_PCMCIA_SA1111=y
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_SA1100=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_NETDEVICES=y
-CONFIG_NET_VENDOR_SMC=y
-CONFIG_PCMCIA_PCNET=y
-CONFIG_SMC91X=y
-CONFIG_NET_PCMCIA=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_SA1111=y
-CONFIG_LEGACY_PTY_COUNT=64
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CS=y
-CONFIG_SERIAL_SA1100=y
-CONFIG_SERIAL_SA1100_CONSOLE=y
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_WATCHDOG=y
-CONFIG_SA1100_WATCHDOG=m
-CONFIG_FB=y
-CONFIG_FB_SA1100=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_SOUND=y
-CONFIG_SOUND_PRIME=y
-# CONFIG_USB_HID is not set
-CONFIG_USB=m
-CONFIG_USB_MON=m
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_STORAGE=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_DEBUG_KERNEL=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 0163c3e78a67..d58f6b5c4c35 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -262,10 +262,6 @@ static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
return read_cpuid(CPUID_MPIDR);
}
-/* StrongARM-11x0 CPUs */
-#define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100)
-#define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110)
-
/*
* Intel's XScale3 core supports some v6 features (supersections, L2)
* but advertises itself as v5 as it does not support the v6 ISA. For
diff --git a/arch/arm/include/asm/hardware/locomo.h b/arch/arm/include/asm/hardware/locomo.h
deleted file mode 100644
index 3190e1e5067a..000000000000
--- a/arch/arm/include/asm/hardware/locomo.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * arch/arm/include/asm/hardware/locomo.h
- *
- * This file contains the definitions for the LoCoMo G/A Chip
- *
- * (C) Copyright 2004 John Lenz
- *
- * May be copied or modified under the terms of the GNU General Public
- * License. See linux/COPYING for more information.
- *
- * Based on sa1111.h
- */
-#ifndef _ASM_ARCH_LOCOMO
-#define _ASM_ARCH_LOCOMO
-
-#define locomo_writel(val,addr) ({ *(volatile u16 *)(addr) = (val); })
-#define locomo_readl(addr) (*(volatile u16 *)(addr))
-
-/* LOCOMO version */
-#define LOCOMO_VER 0x00
-
-/* Pin status */
-#define LOCOMO_ST 0x04
-
-/* Pin status */
-#define LOCOMO_C32K 0x08
-
-/* Interrupt controller */
-#define LOCOMO_ICR 0x0C
-
-/* MCS decoder for boot selecting */
-#define LOCOMO_MCSX0 0x10
-#define LOCOMO_MCSX1 0x14
-#define LOCOMO_MCSX2 0x18
-#define LOCOMO_MCSX3 0x1c
-
-/* Touch panel controller */
-#define LOCOMO_ASD 0x20 /* AD start delay */
-#define LOCOMO_HSD 0x28 /* HSYS delay */
-#define LOCOMO_HSC 0x2c /* HSYS period */
-#define LOCOMO_TADC 0x30 /* tablet ADC clock */
-
-
-/* Long time timer */
-#define LOCOMO_LTC 0xd8 /* LTC interrupt setting */
-#define LOCOMO_LTINT 0xdc /* LTC interrupt */
-
-/* DAC control signal for LCD (COMADJ ) */
-#define LOCOMO_DAC 0xe0
-/* DAC control */
-#define LOCOMO_DAC_SCLOEB 0x08 /* SCL pin output data */
-#define LOCOMO_DAC_TEST 0x04 /* Test bit */
-#define LOCOMO_DAC_SDA 0x02 /* SDA pin level (read-only) */
-#define LOCOMO_DAC_SDAOEB 0x01 /* SDA pin output data */
-
-/* SPI interface */
-#define LOCOMO_SPI 0x60
-#define LOCOMO_SPIMD 0x00 /* SPI mode setting */
-#define LOCOMO_SPICT 0x04 /* SPI mode control */
-#define LOCOMO_SPIST 0x08 /* SPI status */
-#define LOCOMO_SPI_TEND (1 << 3) /* Transfer end bit */
-#define LOCOMO_SPI_REND (1 << 2) /* Receive end bit */
-#define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */
-#define LOCOMO_SPI_RFR (1) /* read buffer bit */
-
-#define LOCOMO_SPIIS 0x10 /* SPI interrupt status */
-#define LOCOMO_SPIWE 0x14 /* SPI interrupt status write enable */
-#define LOCOMO_SPIIE 0x18 /* SPI interrupt enable */
-#define LOCOMO_SPIIR 0x1c /* SPI interrupt request */
-#define LOCOMO_SPITD 0x20 /* SPI transfer data write */
-#define LOCOMO_SPIRD 0x24 /* SPI receive data read */
-#define LOCOMO_SPITS 0x28 /* SPI transfer data shift */
-#define LOCOMO_SPIRS 0x2C /* SPI receive data shift */
-
-/* GPIO */
-#define LOCOMO_GPD 0x90 /* GPIO direction */
-#define LOCOMO_GPE 0x94 /* GPIO input enable */
-#define LOCOMO_GPL 0x98 /* GPIO level */
-#define LOCOMO_GPO 0x9c /* GPIO out data setting */
-#define LOCOMO_GRIE 0xa0 /* GPIO rise detection */
-#define LOCOMO_GFIE 0xa4 /* GPIO fall detection */
-#define LOCOMO_GIS 0xa8 /* GPIO edge detection status */
-#define LOCOMO_GWE 0xac /* GPIO status write enable */
-#define LOCOMO_GIE 0xb0 /* GPIO interrupt enable */
-#define LOCOMO_GIR 0xb4 /* GPIO interrupt request */
-#define LOCOMO_GPIO(Nb) (0x01 << (Nb))
-#define LOCOMO_GPIO_RTS LOCOMO_GPIO(0)
-#define LOCOMO_GPIO_CTS LOCOMO_GPIO(1)
-#define LOCOMO_GPIO_DSR LOCOMO_GPIO(2)
-#define LOCOMO_GPIO_DTR LOCOMO_GPIO(3)
-#define LOCOMO_GPIO_LCD_VSHA_ON LOCOMO_GPIO(4)
-#define LOCOMO_GPIO_LCD_VSHD_ON LOCOMO_GPIO(5)
-#define LOCOMO_GPIO_LCD_VEE_ON LOCOMO_GPIO(6)
-#define LOCOMO_GPIO_LCD_MOD LOCOMO_GPIO(7)
-#define LOCOMO_GPIO_DAC_ON LOCOMO_GPIO(8)
-#define LOCOMO_GPIO_FL_VR LOCOMO_GPIO(9)
-#define LOCOMO_GPIO_DAC_SDATA LOCOMO_GPIO(10)
-#define LOCOMO_GPIO_DAC_SCK LOCOMO_GPIO(11)
-#define LOCOMO_GPIO_DAC_SLOAD LOCOMO_GPIO(12)
-#define LOCOMO_GPIO_CARD_DETECT LOCOMO_GPIO(13)
-#define LOCOMO_GPIO_WRITE_PROT LOCOMO_GPIO(14)
-#define LOCOMO_GPIO_CARD_POWER LOCOMO_GPIO(15)
-
-/* Start the definitions of the devices. Each device has an initial
- * base address and a series of offsets from that base address. */
-
-/* Keyboard controller */
-#define LOCOMO_KEYBOARD 0x40
-#define LOCOMO_KIB 0x00 /* KIB level */
-#define LOCOMO_KSC 0x04 /* KSTRB control */
-#define LOCOMO_KCMD 0x08 /* KSTRB command */
-#define LOCOMO_KIC 0x0c /* Key interrupt */
-
-/* Front light adjustment controller */
-#define LOCOMO_FRONTLIGHT 0xc8
-#define LOCOMO_ALS 0x00 /* Adjust light cycle */
-#define LOCOMO_ALD 0x04 /* Adjust light duty */
-
-#define LOCOMO_ALC_EN 0x8000
-
-/* Backlight controller: TFT signal */
-#define LOCOMO_BACKLIGHT 0x38
-#define LOCOMO_TC 0x00 /* TFT control signal */
-#define LOCOMO_CPSD 0x04 /* CPS delay */
-
-/* Audio controller */
-#define LOCOMO_AUDIO 0x54
-#define LOCOMO_ACC 0x00 /* Audio clock */
-#define LOCOMO_PAIF 0xD0 /* PCM audio interface */
-/* Audio clock */
-#define LOCOMO_ACC_XON 0x80
-#define LOCOMO_ACC_XEN 0x40
-#define LOCOMO_ACC_XSEL0 0x00
-#define LOCOMO_ACC_XSEL1 0x20
-#define LOCOMO_ACC_MCLKEN 0x10
-#define LOCOMO_ACC_64FSEN 0x08
-#define LOCOMO_ACC_CLKSEL000 0x00 /* mclk 2 */
-#define LOCOMO_ACC_CLKSEL001 0x01 /* mclk 3 */
-#define LOCOMO_ACC_CLKSEL010 0x02 /* mclk 4 */
-#define LOCOMO_ACC_CLKSEL011 0x03 /* mclk 6 */
-#define LOCOMO_ACC_CLKSEL100 0x04 /* mclk 8 */
-#define LOCOMO_ACC_CLKSEL101 0x05 /* mclk 12 */
-/* PCM audio interface */
-#define LOCOMO_PAIF_SCINV 0x20
-#define LOCOMO_PAIF_SCEN 0x10
-#define LOCOMO_PAIF_LRCRST 0x08
-#define LOCOMO_PAIF_LRCEVE 0x04
-#define LOCOMO_PAIF_LRCINV 0x02
-#define LOCOMO_PAIF_LRCEN 0x01
-
-/* LED controller */
-#define LOCOMO_LED 0xe8
-#define LOCOMO_LPT0 0x00
-#define LOCOMO_LPT1 0x04
-/* LED control */
-#define LOCOMO_LPT_TOFH 0x80
-#define LOCOMO_LPT_TOFL 0x08
-#define LOCOMO_LPT_TOH(TOH) ((TOH & 0x7) << 4)
-#define LOCOMO_LPT_TOL(TOL) ((TOL & 0x7))
-
-#define LOCOMO_DEVID_KEYBOARD 0
-#define LOCOMO_DEVID_FRONTLIGHT 1
-#define LOCOMO_DEVID_BACKLIGHT 2
-#define LOCOMO_DEVID_AUDIO 3
-#define LOCOMO_DEVID_LED 4
-#define LOCOMO_DEVID_UART 5
-#define LOCOMO_DEVID_SPI 6
-
-struct locomo_dev {
- struct device dev;
- unsigned int devid;
- unsigned int irq[1];
-
- void *mapbase;
- unsigned long length;
-
- u64 dma_mask;
-};
-
-#define LOCOMO_DEV(_d) container_of((_d), struct locomo_dev, dev)
-
-#define locomo_get_drvdata(d) dev_get_drvdata(&(d)->dev)
-#define locomo_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
-
-struct locomo_driver {
- struct device_driver drv;
- unsigned int devid;
- int (*probe)(struct locomo_dev *);
- void (*remove)(struct locomo_dev *);
-};
-
-#define LOCOMO_DRV(_d) container_of_const((_d), struct locomo_driver, drv)
-
-#define LOCOMO_DRIVER_NAME(_ldev) ((_ldev)->dev.driver->name)
-
-extern void locomolcd_power(int on);
-
-int locomo_driver_register(struct locomo_driver *);
-void locomo_driver_unregister(struct locomo_driver *);
-
-/* GPIO control functions */
-void locomo_gpio_set_dir(struct device *dev, unsigned int bits, unsigned int dir);
-int locomo_gpio_read_level(struct device *dev, unsigned int bits);
-int locomo_gpio_read_output(struct device *dev, unsigned int bits);
-void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set);
-
-/* M62332 control function */
-void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel);
-
-/* Frontlight control */
-void locomo_frontlight_set(struct locomo_dev *dev, int duty, int vr, int bpwf);
-
-struct locomo_platform_data {
- int irq_base; /* IRQ base for cascaded on-chip IRQs */
-};
-
-#endif
diff --git a/arch/arm/include/asm/hardware/sa1111.h b/arch/arm/include/asm/hardware/sa1111.h
deleted file mode 100644
index 90b6a832108d..000000000000
--- a/arch/arm/include/asm/hardware/sa1111.h
+++ /dev/null
@@ -1,442 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/include/asm/hardware/sa1111.h
- *
- * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
- *
- * This file contains definitions for the SA-1111 Companion Chip.
- * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.)
- *
- * Macro that calculates real address for registers in the SA-1111
- */
-
-#ifndef _ASM_ARCH_SA1111
-#define _ASM_ARCH_SA1111
-
-/*
- * Don't ask the (SAC) DMA engines to move less than this amount.
- */
-
-#define SA1111_SAC_DMA_MIN_XFER (0x800)
-
-/*
- * System Bus Interface (SBI)
- *
- * Registers
- * SKCR Control Register
- * SMCR Shared Memory Controller Register
- * SKID ID Register
- */
-#define SA1111_SKCR 0x0000
-#define SA1111_SMCR 0x0004
-#define SA1111_SKID 0x0008
-
-#define SKCR_PLL_BYPASS (1<<0)
-#define SKCR_RCLKEN (1<<1)
-#define SKCR_SLEEP (1<<2)
-#define SKCR_DOZE (1<<3)
-#define SKCR_VCO_OFF (1<<4)
-#define SKCR_SCANTSTEN (1<<5)
-#define SKCR_CLKTSTEN (1<<6)
-#define SKCR_RDYEN (1<<7)
-#define SKCR_SELAC (1<<8)
-#define SKCR_OPPC (1<<9)
-#define SKCR_PLLTSTEN (1<<10)
-#define SKCR_USBIOTSTEN (1<<11)
-/*
- * Don't believe the specs! Take them, throw them outside. Leave them
- * there for a week. Spit on them. Walk on them. Stamp on them.
- * Pour gasoline over them and finally burn them. Now think about coding.
- * - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
- * - The Feb 2001 errata (278260-010) says that the previous errata
- * (278260-009) is wrong, and its bit actually 12, fixed in spec
- * 278242-003.
- * - The SA1111 manual (278242) says bit 12, but 0 to enable.
- * - Reality is bit 13, 1 to enable.
- * -- rmk
- */
-#define SKCR_OE_EN (1<<13)
-
-#define SMCR_DTIM (1<<0)
-#define SMCR_MBGE (1<<1)
-#define SMCR_DRAC_0 (1<<2)
-#define SMCR_DRAC_1 (1<<3)
-#define SMCR_DRAC_2 (1<<4)
-#define SMCR_DRAC Fld(3, 2)
-#define SMCR_CLAT (1<<5)
-
-#define SKID_SIREV_MASK (0x000000f0)
-#define SKID_MTREV_MASK (0x0000000f)
-#define SKID_ID_MASK (0xffffff00)
-#define SKID_SA1111_ID (0x690cc200)
-
-/*
- * System Controller
- *
- * Registers
- * SKPCR Power Control Register
- * SKCDR Clock Divider Register
- * SKAUD Audio Clock Divider Register
- * SKPMC PS/2 Mouse Clock Divider Register
- * SKPTC PS/2 Track Pad Clock Divider Register
- * SKPEN0 PWM0 Enable Register
- * SKPWM0 PWM0 Clock Register
- * SKPEN1 PWM1 Enable Register
- * SKPWM1 PWM1 Clock Register
- */
-#define SA1111_SKPCR 0x0200
-#define SA1111_SKCDR 0x0204
-#define SA1111_SKAUD 0x0208
-#define SA1111_SKPMC 0x020c
-#define SA1111_SKPTC 0x0210
-#define SA1111_SKPEN0 0x0214
-#define SA1111_SKPWM0 0x0218
-#define SA1111_SKPEN1 0x021c
-#define SA1111_SKPWM1 0x0220
-
-#define SKPCR_UCLKEN (1<<0)
-#define SKPCR_ACCLKEN (1<<1)
-#define SKPCR_I2SCLKEN (1<<2)
-#define SKPCR_L3CLKEN (1<<3)
-#define SKPCR_SCLKEN (1<<4)
-#define SKPCR_PMCLKEN (1<<5)
-#define SKPCR_PTCLKEN (1<<6)
-#define SKPCR_DCLKEN (1<<7)
-#define SKPCR_PWMCLKEN (1<<8)
-
-/* USB Host controller */
-#define SA1111_USB 0x0400
-
-/*
- * Serial Audio Controller
- *
- * Registers
- * SACR0 Serial Audio Common Control Register
- * SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register
- * SACR2 Serial Audio AC-link Control Register
- * SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register
- * SASR1 Serial Audio AC-link Interface & FIFO Status Register
- * SASCR Serial Audio Status Clear Register
- * L3_CAR L3 Control Bus Address Register
- * L3_CDR L3 Control Bus Data Register
- * ACCAR AC-link Command Address Register
- * ACCDR AC-link Command Data Register
- * ACSAR AC-link Status Address Register
- * ACSDR AC-link Status Data Register
- * SADTCS Serial Audio DMA Transmit Control/Status Register
- * SADTSA Serial Audio DMA Transmit Buffer Start Address A
- * SADTCA Serial Audio DMA Transmit Buffer Count Register A
- * SADTSB Serial Audio DMA Transmit Buffer Start Address B
- * SADTCB Serial Audio DMA Transmit Buffer Count Register B
- * SADRCS Serial Audio DMA Receive Control/Status Register
- * SADRSA Serial Audio DMA Receive Buffer Start Address A
- * SADRCA Serial Audio DMA Receive Buffer Count Register A
- * SADRSB Serial Audio DMA Receive Buffer Start Address B
- * SADRCB Serial Audio DMA Receive Buffer Count Register B
- * SAITR Serial Audio Interrupt Test Register
- * SADR Serial Audio Data Register (16 x 32-bit)
- */
-
-#define SA1111_SERAUDIO 0x0600
-
-/*
- * These are offsets from the above base.
- */
-#define SA1111_SACR0 0x00
-#define SA1111_SACR1 0x04
-#define SA1111_SACR2 0x08
-#define SA1111_SASR0 0x0c
-#define SA1111_SASR1 0x10
-#define SA1111_SASCR 0x18
-#define SA1111_L3_CAR 0x1c
-#define SA1111_L3_CDR 0x20
-#define SA1111_ACCAR 0x24
-#define SA1111_ACCDR 0x28
-#define SA1111_ACSAR 0x2c
-#define SA1111_ACSDR 0x30
-#define SA1111_SADTCS 0x34
-#define SA1111_SADTSA 0x38
-#define SA1111_SADTCA 0x3c
-#define SA1111_SADTSB 0x40
-#define SA1111_SADTCB 0x44
-#define SA1111_SADRCS 0x48
-#define SA1111_SADRSA 0x4c
-#define SA1111_SADRCA 0x50
-#define SA1111_SADRSB 0x54
-#define SA1111_SADRCB 0x58
-#define SA1111_SAITR 0x5c
-#define SA1111_SADR 0x80
-
-#ifndef CONFIG_ARCH_PXA
-
-#define SACR0_ENB (1<<0)
-#define SACR0_BCKD (1<<2)
-#define SACR0_RST (1<<3)
-
-#define SACR1_AMSL (1<<0)
-#define SACR1_L3EN (1<<1)
-#define SACR1_L3MB (1<<2)
-#define SACR1_DREC (1<<3)
-#define SACR1_DRPL (1<<4)
-#define SACR1_ENLBF (1<<5)
-
-#define SACR2_TS3V (1<<0)
-#define SACR2_TS4V (1<<1)
-#define SACR2_WKUP (1<<2)
-#define SACR2_DREC (1<<3)
-#define SACR2_DRPL (1<<4)
-#define SACR2_ENLBF (1<<5)
-#define SACR2_RESET (1<<6)
-
-#define SASR0_TNF (1<<0)
-#define SASR0_RNE (1<<1)
-#define SASR0_BSY (1<<2)
-#define SASR0_TFS (1<<3)
-#define SASR0_RFS (1<<4)
-#define SASR0_TUR (1<<5)
-#define SASR0_ROR (1<<6)
-#define SASR0_L3WD (1<<16)
-#define SASR0_L3RD (1<<17)
-
-#define SASR1_TNF (1<<0)
-#define SASR1_RNE (1<<1)
-#define SASR1_BSY (1<<2)
-#define SASR1_TFS (1<<3)
-#define SASR1_RFS (1<<4)
-#define SASR1_TUR (1<<5)
-#define SASR1_ROR (1<<6)
-#define SASR1_CADT (1<<16)
-#define SASR1_SADR (1<<17)
-#define SASR1_RSTO (1<<18)
-#define SASR1_CLPM (1<<19)
-#define SASR1_CRDY (1<<20)
-#define SASR1_RS3V (1<<21)
-#define SASR1_RS4V (1<<22)
-
-#define SASCR_TUR (1<<5)
-#define SASCR_ROR (1<<6)
-#define SASCR_DTS (1<<16)
-#define SASCR_RDD (1<<17)
-#define SASCR_STO (1<<18)
-
-#define SADTCS_TDEN (1<<0)
-#define SADTCS_TDIE (1<<1)
-#define SADTCS_TDBDA (1<<3)
-#define SADTCS_TDSTA (1<<4)
-#define SADTCS_TDBDB (1<<5)
-#define SADTCS_TDSTB (1<<6)
-#define SADTCS_TBIU (1<<7)
-
-#define SADRCS_RDEN (1<<0)
-#define SADRCS_RDIE (1<<1)
-#define SADRCS_RDBDA (1<<3)
-#define SADRCS_RDSTA (1<<4)
-#define SADRCS_RDBDB (1<<5)
-#define SADRCS_RDSTB (1<<6)
-#define SADRCS_RBIU (1<<7)
-
-#define SAD_CS_DEN (1<<0)
-#define SAD_CS_DIE (1<<1) /* Not functional on metal 1 */
-#define SAD_CS_DBDA (1<<3) /* Not functional on metal 1 */
-#define SAD_CS_DSTA (1<<4)
-#define SAD_CS_DBDB (1<<5) /* Not functional on metal 1 */
-#define SAD_CS_DSTB (1<<6)
-#define SAD_CS_BIU (1<<7) /* Not functional on metal 1 */
-
-#define SAITR_TFS (1<<0)
-#define SAITR_RFS (1<<1)
-#define SAITR_TUR (1<<2)
-#define SAITR_ROR (1<<3)
-#define SAITR_CADT (1<<4)
-#define SAITR_SADR (1<<5)
-#define SAITR_RSTO (1<<6)
-#define SAITR_TDBDA (1<<8)
-#define SAITR_TDBDB (1<<9)
-#define SAITR_RDBDA (1<<10)
-#define SAITR_RDBDB (1<<11)
-
-#endif /* !CONFIG_ARCH_PXA */
-
-/*
- * General-Purpose I/O Interface
- *
- * Registers
- * PA_DDR GPIO Block A Data Direction
- * PA_DRR/PA_DWR GPIO Block A Data Value Register (read/write)
- * PA_SDR GPIO Block A Sleep Direction
- * PA_SSR GPIO Block A Sleep State
- * PB_DDR GPIO Block B Data Direction
- * PB_DRR/PB_DWR GPIO Block B Data Value Register (read/write)
- * PB_SDR GPIO Block B Sleep Direction
- * PB_SSR GPIO Block B Sleep State
- * PC_DDR GPIO Block C Data Direction
- * PC_DRR/PC_DWR GPIO Block C Data Value Register (read/write)
- * PC_SDR GPIO Block C Sleep Direction
- * PC_SSR GPIO Block C Sleep State
- */
-
-#define SA1111_GPIO 0x1000
-
-#define SA1111_GPIO_PADDR (0x000)
-#define SA1111_GPIO_PADRR (0x004)
-#define SA1111_GPIO_PADWR (0x004)
-#define SA1111_GPIO_PASDR (0x008)
-#define SA1111_GPIO_PASSR (0x00c)
-#define SA1111_GPIO_PBDDR (0x010)
-#define SA1111_GPIO_PBDRR (0x014)
-#define SA1111_GPIO_PBDWR (0x014)
-#define SA1111_GPIO_PBSDR (0x018)
-#define SA1111_GPIO_PBSSR (0x01c)
-#define SA1111_GPIO_PCDDR (0x020)
-#define SA1111_GPIO_PCDRR (0x024)
-#define SA1111_GPIO_PCDWR (0x024)
-#define SA1111_GPIO_PCSDR (0x028)
-#define SA1111_GPIO_PCSSR (0x02c)
-
-#define GPIO_A0 (1 << 0)
-#define GPIO_A1 (1 << 1)
-#define GPIO_A2 (1 << 2)
-#define GPIO_A3 (1 << 3)
-
-#define GPIO_B0 (1 << 8)
-#define GPIO_B1 (1 << 9)
-#define GPIO_B2 (1 << 10)
-#define GPIO_B3 (1 << 11)
-#define GPIO_B4 (1 << 12)
-#define GPIO_B5 (1 << 13)
-#define GPIO_B6 (1 << 14)
-#define GPIO_B7 (1 << 15)
-
-#define GPIO_C0 (1 << 16)
-#define GPIO_C1 (1 << 17)
-#define GPIO_C2 (1 << 18)
-#define GPIO_C3 (1 << 19)
-#define GPIO_C4 (1 << 20)
-#define GPIO_C5 (1 << 21)
-#define GPIO_C6 (1 << 22)
-#define GPIO_C7 (1 << 23)
-
-/*
- * Interrupt Controller
- *
- * Registers
- * INTTEST0 Test register 0
- * INTTEST1 Test register 1
- * INTEN0 Interrupt Enable register 0
- * INTEN1 Interrupt Enable register 1
- * INTPOL0 Interrupt Polarity selection 0
- * INTPOL1 Interrupt Polarity selection 1
- * INTTSTSEL Interrupt source selection
- * INTSTATCLR0 Interrupt Status/Clear 0
- * INTSTATCLR1 Interrupt Status/Clear 1
- * INTSET0 Interrupt source set 0
- * INTSET1 Interrupt source set 1
- * WAKE_EN0 Wake-up source enable 0
- * WAKE_EN1 Wake-up source enable 1
- * WAKE_POL0 Wake-up polarity selection 0
- * WAKE_POL1 Wake-up polarity selection 1
- */
-#define SA1111_INTC 0x1600
-
-/*
- * These are offsets from the above base.
- */
-#define SA1111_INTTEST0 0x0000
-#define SA1111_INTTEST1 0x0004
-#define SA1111_INTEN0 0x0008
-#define SA1111_INTEN1 0x000c
-#define SA1111_INTPOL0 0x0010
-#define SA1111_INTPOL1 0x0014
-#define SA1111_INTTSTSEL 0x0018
-#define SA1111_INTSTATCLR0 0x001c
-#define SA1111_INTSTATCLR1 0x0020
-#define SA1111_INTSET0 0x0024
-#define SA1111_INTSET1 0x0028
-#define SA1111_WAKEEN0 0x002c
-#define SA1111_WAKEEN1 0x0030
-#define SA1111_WAKEPOL0 0x0034
-#define SA1111_WAKEPOL1 0x0038
-
-/* PS/2 Trackpad and Mouse Interfaces */
-#define SA1111_KBD 0x0a00
-#define SA1111_MSE 0x0c00
-
-/* PCMCIA Interface */
-#define SA1111_PCMCIA 0x1600
-
-
-
-
-
-extern const struct bus_type sa1111_bus_type;
-
-#define SA1111_DEVID_SBI (1 << 0)
-#define SA1111_DEVID_SK (1 << 1)
-#define SA1111_DEVID_USB (1 << 2)
-#define SA1111_DEVID_SAC (1 << 3)
-#define SA1111_DEVID_SSP (1 << 4)
-#define SA1111_DEVID_PS2 (3 << 5)
-#define SA1111_DEVID_PS2_KBD (1 << 5)
-#define SA1111_DEVID_PS2_MSE (1 << 6)
-#define SA1111_DEVID_GPIO (1 << 7)
-#define SA1111_DEVID_INT (1 << 8)
-#define SA1111_DEVID_PCMCIA (1 << 9)
-
-struct sa1111_dev {
- struct device dev;
- unsigned int devid;
- struct resource res;
- void __iomem *mapbase;
- unsigned int skpcr_mask;
- unsigned int hwirq[6];
- u64 dma_mask;
-};
-
-#define to_sa1111_device(x) container_of(x, struct sa1111_dev, dev)
-
-#define sa1111_get_drvdata(d) dev_get_drvdata(&(d)->dev)
-#define sa1111_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
-
-struct sa1111_driver {
- struct device_driver drv;
- unsigned int devid;
- int (*probe)(struct sa1111_dev *);
- void (*remove)(struct sa1111_dev *);
-};
-
-#define SA1111_DRV(_d) container_of_const((_d), struct sa1111_driver, drv)
-
-#define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name)
-
-/*
- * These frob the SKPCR register, and call platform specific
- * enable/disable functions.
- */
-int sa1111_enable_device(struct sa1111_dev *);
-void sa1111_disable_device(struct sa1111_dev *);
-
-int sa1111_get_irq(struct sa1111_dev *, unsigned num);
-
-unsigned int sa1111_pll_clock(struct sa1111_dev *);
-
-#define SA1111_AUDIO_ACLINK 0
-#define SA1111_AUDIO_I2S 1
-
-void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode);
-int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate);
-int sa1111_get_audio_rate(struct sa1111_dev *sadev);
-
-int sa1111_check_dma_bug(dma_addr_t addr);
-
-int sa1111_driver_register(struct sa1111_driver *);
-void sa1111_driver_unregister(struct sa1111_driver *);
-
-struct sa1111_platform_data {
- int irq_base; /* base for cascaded on-chip IRQs */
- unsigned disable_devs;
- void *data;
- int (*enable)(void *, unsigned);
- void (*disable)(void *, unsigned);
-};
-
-#endif /* _ASM_ARCH_SA1111 */
diff --git a/arch/arm/include/asm/hardware/ssp.h b/arch/arm/include/asm/hardware/ssp.h
deleted file mode 100644
index 72d176790308..000000000000
--- a/arch/arm/include/asm/hardware/ssp.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * ssp.h
- *
- * Copyright (C) 2003 Russell King, All Rights Reserved.
- */
-#ifndef SSP_H
-#define SSP_H
-
-struct ssp_state {
- unsigned int cr0;
- unsigned int cr1;
-};
-
-int ssp_write_word(u16 data);
-int ssp_read_word(u16 *data);
-int ssp_flush(void);
-void ssp_enable(void);
-void ssp_disable(void);
-void ssp_save_state(struct ssp_state *ssp);
-void ssp_restore_state(struct ssp_state *ssp);
-int ssp_init(void);
-void ssp_exit(void);
-
-#endif
diff --git a/arch/arm/include/debug/sa1100.S b/arch/arm/include/debug/sa1100.S
deleted file mode 100644
index 7968ea52df3d..000000000000
--- a/arch/arm/include/debug/sa1100.S
+++ /dev/null
@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* arch/arm/include/debug/sa1100.S
- *
- * Debugging macro include header
- *
- * Copyright (C) 1994-1999 Russell King
- * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
-*/
-
-#define UTCR3 0x0c
-#define UTDR 0x14
-#define UTSR1 0x20
-#define UTCR3_TXE 0x00000002 /* Transmit Enable */
-#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
-#define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
-
- .macro addruart, rp, rv, tmp
- mrc p15, 0, \rp, c1, c0
- tst \rp, #1 @ MMU enabled?
- moveq \rp, #0x80000000 @ physical base address
- movne \rp, #0xf8000000 @ virtual address
-
- @ We probe for the active serial port here, coherently with
- @ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.
- @ We assume r1 can be clobbered.
-
- @ see if Ser3 is active
- add \rp, \rp, #0x00050000
- ldr \rv, [\rp, #UTCR3]
- tst \rv, #UTCR3_TXE
-
- @ if Ser3 is inactive, then try Ser1
- addeq \rp, \rp, #(0x00010000 - 0x00050000)
- ldreq \rv, [\rp, #UTCR3]
- tsteq \rv, #UTCR3_TXE
-
- @ if Ser1 is inactive, then try Ser2
- addeq \rp, \rp, #(0x00030000 - 0x00010000)
- ldreq \rv, [\rp, #UTCR3]
- tsteq \rv, #UTCR3_TXE
-
- @ clear top bits, and generate both phys and virt addresses
- lsl \rp, \rp, #8
- lsr \rp, \rp, #8
- orr \rv, \rp, #0xf8000000 @ virtual
- orr \rp, \rp, #0x80000000 @ physical
-
- .endm
-
- .macro senduart,rd,rx
- str \rd, [\rx, #UTDR]
- .endm
-
- .macro waituartcts,rd,rx
- .endm
-
- .macro waituarttxrdy,rd,rx
-1001: ldr \rd, [\rx, #UTSR1]
- tst \rd, #UTSR1_TNF
- beq 1001b
- .endm
-
- .macro busyuart,rd,rx
-1001: ldr \rd, [\rx, #UTSR1]
- tst \rd, #UTSR1_TBY
- bne 1001b
- .endm
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
deleted file mode 100644
index d50721e39641..000000000000
--- a/arch/arm/mach-sa1100/Kconfig
+++ /dev/null
@@ -1,92 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-menuconfig ARCH_SA1100
- bool "SA11x0 Implementations (DEPRECATED)"
- depends on ARCH_MULTI_V4 && !(ARCH_MULTI_V4T || ARCH_MULTI_V5)
- depends on !(ARCH_MOXART || ARCH_GEMINI)
- depends on ATAGS
- depends on CPU_LITTLE_ENDIAN
- depends on MMU
- select ARCH_NO_SG_CHAIN
- select ARCH_MTD_XIP
- select CLKSRC_MMIO
- select CLKSRC_PXA
- select CPU_FREQ
- select CPU_SA1100
- select GPIOLIB
- select GPIOLIB_LEGACY
- select IRQ_DOMAIN
- select ISA
- select NEED_MACH_MEMORY_H
- help
- Support for StrongARM 11x0 based boards.
-
- Support for these machines will go away in 2027,
- unless there are any remaining users that speak up.
-
-if ARCH_SA1100
-
-config SA1100_ASSABET
- bool "Assabet"
- select ARM_SA1110_CPUFREQ
- select GPIO_REG
- select LEDS_GPIO_REGISTER
- select REGULATOR
- select REGULATOR_FIXED_VOLTAGE
- help
- Say Y here if you are using the Intel(R) StrongARM(R) SA-1110
- Microprocessor Development Board (also known as the Assabet).
-
-config ASSABET_NEPONSET
- bool "Include support for Neponset"
- depends on SA1100_ASSABET
- select SA1111
- help
- Say Y here if you are using the Intel(R) StrongARM(R) SA-1110
- Microprocessor Development Board (Assabet) with the SA-1111
- Development Board (Nepon).
-
-config SA1100_COLLIE
- bool "Sharp Zaurus SL5500"
- # FIXME: select ARM_SA11x0_CPUFREQ
- select SHARP_LOCOMO
- select SHARP_PARAM
- select SHARP_SCOOP
- help
- Say Y here to support the Sharp Zaurus SL5500 PDAs.
-
-config SA1100_H3600
- bool "Compaq iPAQ H3600/H3700"
- select ARM_SA1110_CPUFREQ
- select HTC_EGPIO
- select MFD_IPAQ_MICRO
- help
- Say Y here if you intend to run this kernel on the Compaq iPAQ
- H3600 and H3700 handheld computers.
-
-config SA1100_JORNADA720
- bool "HP Jornada 720"
- # FIXME: select ARM_SA11x0_CPUFREQ
- select SA1111
- help
- Say Y here if you want to build a kernel for the HP Jornada 720
- handheld computer. See
- <http://h10025.www1.hp.com/ewfrf/wc/product?product=61677&cc=us&lc=en&dlc=en&product=61677#>
-
-config SA1100_JORNADA720_SSP
- bool "HP Jornada 720 Extended SSP driver"
- depends on SA1100_JORNADA720
- select SA1100_SSP
- help
- Say Y here if you have a HP Jornada 7xx handheld computer and you
- want to access devices connected to the MCU. Those include the
- keyboard, touchscreen, backlight and battery. This driver also activates
- the generic SSP which it extends.
-
-config SA1100_SSP
- tristate "Generic PIO SSP"
- help
- Say Y here to enable support for the generic PIO SSP driver.
- This isn't for audio support, but for attached sensors and
- other devices, eg for BadgePAD 4 sensor support.
-
-endif
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
deleted file mode 100644
index b5816d675152..000000000000
--- a/arch/arm/mach-sa1100/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the linux kernel.
-#
-
-# Common support
-obj-y := clock.o generic.o #nmi-oopser.o
-
-# Specific board support
-obj-$(CONFIG_SA1100_ASSABET) += assabet.o
-obj-$(CONFIG_ASSABET_NEPONSET) += neponset.o
-obj-$(CONFIG_SA1100_COLLIE) += collie.o
-obj-$(CONFIG_SA1100_H3600) += h3600.o h3xxx.o
-obj-$(CONFIG_SA1100_JORNADA720) += jornada720.o
-obj-$(CONFIG_SA1100_JORNADA720_SSP) += jornada720_ssp.o
-
-# Miscellaneous functions
-obj-$(CONFIG_PM) += pm.o sleep.o
-obj-$(CONFIG_SA1100_SSP) += ssp.o
-
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
deleted file mode 100644
index b001f0b6a3fa..000000000000
--- a/arch/arm/mach-sa1100/assabet.c
+++ /dev/null
@@ -1,770 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-sa1100/assabet.c
- *
- * Author: Nicolas Pitre
- *
- * This file contains all Assabet-specific tweaks.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/gpio/driver.h>
-#include <linux/gpio/gpio-reg.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio/property.h>
-#include <linux/input.h>
-#include <linux/ioport.h>
-#include <linux/property.h>
-#include <linux/platform_data/sa11x0-serial.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-#include <linux/serial_core.h>
-#include <linux/platform_device.h>
-#include <linux/mfd/ucb1x00.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/delay.h>
-#include <linux/mm.h>
-#include <linux/leds.h>
-#include <linux/slab.h>
-
-#include <video/sa1100fb.h>
-
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/pgtable-hwdef.h>
-#include <asm/tlbflush.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/map.h>
-#include <mach/assabet.h>
-#include <linux/platform_data/mfd-mcp-sa11x0.h>
-#include <mach/irqs.h>
-
-#include "generic.h"
-
-#define ASSABET_BCR_DB1110 \
- (ASSABET_BCR_SPK_OFF | \
- ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \
- ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \
- ASSABET_BCR_IRDA_MD0)
-
-#define ASSABET_BCR_DB1111 \
- (ASSABET_BCR_SPK_OFF | \
- ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \
- ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \
- ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \
- ASSABET_BCR_IRDA_MD0 | ASSABET_BCR_CF_RST)
-
-unsigned long SCR_value = ASSABET_SCR_INIT;
-EXPORT_SYMBOL(SCR_value);
-
-static struct gpio_chip *assabet_bcr_gc;
-
-static const char *assabet_names[] = {
- "cf_pwr", "cf_gfx_reset", "nsoft_reset", "irda_fsel",
- "irda_md0", "irda_md1", "stereo_loopback", "ncf_bus_on",
- "audio_pwr_on", "light_pwr_on", "lcd16data", "lcd_pwr_on",
- "rs232_on", "nred_led", "ngreen_led", "vib_on",
- "com_dtr", "com_rts", "radio_wake_mod", "i2c_enab",
- "tvir_enab", "qmute", "radio_pwr_on", "spkr_off",
- "rs232_valid", "com_dcd", "com_cts", "com_dsr",
- "radio_cts", "radio_dsr", "radio_dcd", "radio_ri",
-};
-
-/* The old deprecated interface */
-void ASSABET_BCR_frob(unsigned int mask, unsigned int val)
-{
- unsigned long m = mask, v = val;
-
- assabet_bcr_gc->set_multiple(assabet_bcr_gc, &m, &v);
-}
-EXPORT_SYMBOL(ASSABET_BCR_frob);
-
-static void __init assabet_init_gpio(void __iomem *reg, u32 def_val)
-{
- struct gpio_chip *gc;
-
- writel_relaxed(def_val, reg);
-
- gc = gpio_reg_init(NULL, reg, -1, 32, "assabet", 0xff000000, def_val,
- assabet_names, NULL, NULL);
-
- if (IS_ERR(gc))
- return;
-
- assabet_bcr_gc = gc;
-}
-
-/*
- * The codec reset goes to three devices, so we need to release
- * the rest when any one of these requests it. However, that
- * causes the ADV7171 to consume around 100mA - more than half
- * the LCD-blanked power.
- *
- * With the ADV7171, LCD and backlight enabled, we go over
- * budget on the MAX846 Li-Ion charger, and if no Li-Ion battery
- * is connected, the Assabet crashes.
- */
-#define RST_UCB1X00 (1 << 0)
-#define RST_UDA1341 (1 << 1)
-#define RST_ADV7171 (1 << 2)
-
-#define SDA GPIO_GPIO(15)
-#define SCK GPIO_GPIO(18)
-#define MOD GPIO_GPIO(17)
-
-static void adv7171_start(void)
-{
- GPSR = SCK;
- udelay(1);
- GPSR = SDA;
- udelay(2);
- GPCR = SDA;
-}
-
-static void adv7171_stop(void)
-{
- GPSR = SCK;
- udelay(2);
- GPSR = SDA;
- udelay(1);
-}
-
-static void adv7171_send(unsigned byte)
-{
- unsigned i;
-
- for (i = 0; i < 8; i++, byte <<= 1) {
- GPCR = SCK;
- udelay(1);
- if (byte & 0x80)
- GPSR = SDA;
- else
- GPCR = SDA;
- udelay(1);
- GPSR = SCK;
- udelay(1);
- }
- GPCR = SCK;
- udelay(1);
- GPSR = SDA;
- udelay(1);
- GPDR &= ~SDA;
- GPSR = SCK;
- udelay(1);
- if (GPLR & SDA)
- printk(KERN_WARNING "No ACK from ADV7171\n");
- udelay(1);
- GPCR = SCK | SDA;
- udelay(1);
- GPDR |= SDA;
- udelay(1);
-}
-
-static void adv7171_write(unsigned reg, unsigned val)
-{
- unsigned gpdr = GPDR;
- unsigned gplr = GPLR;
-
- ASSABET_BCR_frob(ASSABET_BCR_AUDIO_ON, ASSABET_BCR_AUDIO_ON);
- udelay(100);
-
- GPCR = SDA | SCK | MOD; /* clear L3 mode to ensure UDA1341 doesn't respond */
- GPDR = (GPDR | SCK | MOD) & ~SDA;
- udelay(10);
- if (!(GPLR & SDA))
- printk(KERN_WARNING "Something dragging SDA down?\n");
- GPDR |= SDA;
-
- adv7171_start();
- adv7171_send(0x54);
- adv7171_send(reg);
- adv7171_send(val);
- adv7171_stop();
-
- /* Restore GPIO state for L3 bus */
- GPSR = gplr & (SDA | SCK | MOD);
- GPCR = (~gplr) & (SDA | SCK | MOD);
- GPDR = gpdr;
-}
-
-static void adv7171_sleep(void)
-{
- /* Put the ADV7171 into sleep mode */
- adv7171_write(0x04, 0x40);
-}
-
-static unsigned codec_nreset;
-
-static void assabet_codec_reset(unsigned mask, int set)
-{
- unsigned long flags;
- bool old;
-
- local_irq_save(flags);
- old = !codec_nreset;
- if (set)
- codec_nreset &= ~mask;
- else
- codec_nreset |= mask;
-
- if (old != !codec_nreset) {
- if (codec_nreset) {
- ASSABET_BCR_set(ASSABET_BCR_NCODEC_RST);
- adv7171_sleep();
- } else {
- ASSABET_BCR_clear(ASSABET_BCR_NCODEC_RST);
- }
- }
- local_irq_restore(flags);
-}
-
-static void assabet_ucb1x00_reset(enum ucb1x00_reset state)
-{
- int set = state == UCB_RST_REMOVE || state == UCB_RST_SUSPEND ||
- state == UCB_RST_PROBE_FAIL;
- assabet_codec_reset(RST_UCB1X00, set);
-}
-
-void assabet_uda1341_reset(int set)
-{
- assabet_codec_reset(RST_UDA1341, set);
-}
-EXPORT_SYMBOL(assabet_uda1341_reset);
-
-
-/*
- * Assabet flash support code.
- */
-
-#ifdef ASSABET_REV_4
-/*
- * Phase 4 Assabet has two 28F160B3 flash parts in bank 0:
- */
-static struct mtd_partition assabet_partitions[] = {
- {
- .name = "bootloader",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "bootloader params",
- .size = 0x00020000,
- .offset = MTDPART_OFS_APPEND,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "jffs",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-#else
-/*
- * Phase 5 Assabet has two 28F128J3A flash parts in bank 0:
- */
-static struct mtd_partition assabet_partitions[] = {
- {
- .name = "bootloader",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "bootloader params",
- .size = 0x00040000,
- .offset = MTDPART_OFS_APPEND,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "jffs",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-#endif
-
-static struct flash_platform_data assabet_flash_data = {
- .map_name = "cfi_probe",
- .parts = assabet_partitions,
- .nr_parts = ARRAY_SIZE(assabet_partitions),
-};
-
-static struct resource assabet_flash_resources[] = {
- DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
- DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M),
-};
-
-
-static struct ucb1x00_plat_data assabet_ucb1x00_data = {
- .reset = assabet_ucb1x00_reset,
- .gpio_base = -1,
- .can_wakeup = 1,
-};
-
-static struct mcp_plat_data assabet_mcp_data = {
- .mccr0 = MCCR0_ADM,
- .sclk_rate = 11981000,
- .codec_pdata = &assabet_ucb1x00_data,
-};
-
-static void assabet_lcd_set_visual(u32 visual)
-{
- u_int is_true_color = visual == FB_VISUAL_TRUECOLOR;
-
- if (machine_is_assabet()) {
-#if 1 // phase 4 or newer Assabet's
- if (is_true_color)
- ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
- else
- ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
-#else
- // older Assabet's
- if (is_true_color)
- ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
- else
- ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
-#endif
- }
-}
-
-#ifndef ASSABET_PAL_VIDEO
-static void assabet_lcd_backlight_power(int on)
-{
- if (on)
- ASSABET_BCR_set(ASSABET_BCR_LIGHT_ON);
- else
- ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
-}
-
-/*
- * Turn on/off the backlight. When turning the backlight on, we wait
- * 500us after turning it on so we don't cause the supplies to droop
- * when we enable the LCD controller (and cause a hard reset.)
- */
-static void assabet_lcd_power(int on)
-{
- if (on) {
- ASSABET_BCR_set(ASSABET_BCR_LCD_ON);
- udelay(500);
- } else
- ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
-}
-
-/*
- * The assabet uses a sharp LQ039Q2DS54 LCD module. It is actually
- * takes an RGB666 signal, but we provide it with an RGB565 signal
- * instead (def_rgb_16).
- */
-static struct sa1100fb_mach_info lq039q2ds54_info = {
- .pixclock = 171521, .bpp = 16,
- .xres = 320, .yres = 240,
-
- .hsync_len = 5, .vsync_len = 1,
- .left_margin = 61, .upper_margin = 3,
- .right_margin = 9, .lower_margin = 0,
-
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-
- .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
- .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
-
- .backlight_power = assabet_lcd_backlight_power,
- .lcd_power = assabet_lcd_power,
- .set_visual = assabet_lcd_set_visual,
-};
-#else
-static void assabet_pal_backlight_power(int on)
-{
- ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
-}
-
-static void assabet_pal_power(int on)
-{
- ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
-}
-
-static struct sa1100fb_mach_info pal_info = {
- .pixclock = 67797, .bpp = 16,
- .xres = 640, .yres = 512,
-
- .hsync_len = 64, .vsync_len = 6,
- .left_margin = 125, .upper_margin = 70,
- .right_margin = 115, .lower_margin = 36,
-
- .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
- .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
-
- .backlight_power = assabet_pal_backlight_power,
- .lcd_power = assabet_pal_power,
- .set_visual = assabet_lcd_set_visual,
-};
-#endif
-
-#ifdef CONFIG_ASSABET_NEPONSET
-static struct resource neponset_resources[] = {
- DEFINE_RES_MEM(0x10000000, 0x08000000),
- DEFINE_RES_MEM(0x18000000, 0x04000000),
- DEFINE_RES_MEM(0x40000000, SZ_8K),
- DEFINE_RES_IRQ(IRQ_GPIO25),
-};
-#endif
-
-static struct gpiod_lookup_table assabet_cf_gpio_table = {
- .dev_id = "sa11x0-pcmcia.1",
- .table = {
- GPIO_LOOKUP("gpio", 21, "ready", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio", 22, "detect", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio", 24, "bvd2", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio", 25, "bvd1", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("assabet", 1, "reset", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("assabet", 7, "bus-enable", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct regulator_consumer_supply assabet_cf_vcc_consumers[] = {
- REGULATOR_SUPPLY("vcc", "sa11x0-pcmcia.1"),
-};
-
-static struct fixed_voltage_config assabet_cf_vcc_pdata __initdata = {
- .supply_name = "cf-power",
- .microvolts = 3300000,
-};
-
-static struct gpiod_lookup_table assabet_cf_vcc_gpio_table = {
- .dev_id = "reg-fixed-voltage.0",
- .table = {
- GPIO_LOOKUP("assabet", 0, NULL, GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct gpiod_lookup_table assabet_leds_gpio_table = {
- .dev_id = "leds-gpio",
- .table = {
- GPIO_LOOKUP("assabet", 13, NULL, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("assabet", 14, NULL, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct gpio_led assabet_leds[] __initdata = {
- {
- .name = "assabet:red",
- .default_trigger = "cpu0",
- .default_state = LEDS_GPIO_DEFSTATE_KEEP,
- }, {
- .name = "assabet:green",
- .default_trigger = "heartbeat",
- .default_state = LEDS_GPIO_DEFSTATE_KEEP,
- },
-};
-
-static const struct gpio_led_platform_data assabet_leds_pdata __initconst = {
- .num_leds = ARRAY_SIZE(assabet_leds),
- .leds = assabet_leds,
-};
-
-static const struct software_node assabet_gpio_keys_node = {
- .name = "assabet-gpio-keys",
-};
-
-static const struct property_entry assabet_key0_props[] = {
- PROPERTY_ENTRY_U32("linux,code", KEY_RESERVED),
- PROPERTY_ENTRY_GPIO("gpios", &sa1100_gpiochip_node,
- 0, GPIO_ACTIVE_HIGH),
- PROPERTY_ENTRY_STRING("label", "gpio0"),
- PROPERTY_ENTRY_BOOL("wakeup-source"),
- PROPERTY_ENTRY_BOOL("linux,can-disable"),
- PROPERTY_ENTRY_U32("debounce-interval", 5),
- { }
-};
-
-static const struct software_node assabet_key0_node = {
- .parent = &assabet_gpio_keys_node,
- .properties = assabet_key0_props,
-};
-
-static const struct property_entry assabet_key1_props[] = {
- PROPERTY_ENTRY_U32("linux,code", KEY_RESERVED),
- PROPERTY_ENTRY_GPIO("gpios", &sa1100_gpiochip_node,
- 1, GPIO_ACTIVE_HIGH),
- PROPERTY_ENTRY_STRING("label", "gpio1"),
- PROPERTY_ENTRY_BOOL("wakeup-source"),
- PROPERTY_ENTRY_BOOL("linux,can-disable"),
- PROPERTY_ENTRY_U32("debounce-interval", 5),
- { }
-};
-
-static const struct software_node assabet_key1_node = {
- .parent = &assabet_gpio_keys_node,
- .properties = assabet_key1_props,
-};
-
-static const struct software_node * const assabet_gpio_keys_swnodes[] __initconst = {
- &assabet_gpio_keys_node,
- &assabet_key0_node,
- &assabet_key1_node,
- NULL
-};
-
-static const struct platform_device_info assabet_gpio_keys_dev_info __initconst = {
- .name = "gpio-keys",
- .id = PLATFORM_DEVID_NONE,
- .swnode = &assabet_gpio_keys_node,
-};
-
-static struct gpiod_lookup_table assabet_uart1_gpio_table = {
- .dev_id = "sa11x0-uart.1",
- .table = {
- GPIO_LOOKUP("assabet", 16, "dtr", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("assabet", 17, "rts", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("assabet", 25, "dcd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("assabet", 26, "cts", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("assabet", 27, "dsr", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct gpiod_lookup_table assabet_uart3_gpio_table = {
- .dev_id = "sa11x0-uart.3",
- .table = {
- GPIO_LOOKUP("assabet", 28, "cts", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("assabet", 29, "dsr", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("assabet", 30, "dcd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("assabet", 31, "rng", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static void __init assabet_init(void)
-{
- /*
- * Ensure that the power supply is in "high power" mode.
- */
- GPSR = GPIO_GPIO16;
- GPDR |= GPIO_GPIO16;
-
- /*
- * Ensure that these pins are set as outputs and are driving
- * logic 0. This ensures that we won't inadvertently toggle
- * the WS latch in the CPLD, and we don't float causing
- * excessive power drain. --rmk
- */
- GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
- GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
-
- /*
- * Also set GPIO27 as an output; this is used to clock UART3
- * via the FPGA and as otherwise has no pullups or pulldowns,
- * so stop it floating.
- */
- GPCR = GPIO_GPIO27;
- GPDR |= GPIO_GPIO27;
-
- /*
- * Set up registers for sleep mode.
- */
- PWER = PWER_GPIO0;
- PGSR = 0;
- PCFR = 0;
- PSDR = 0;
- PPDR |= PPC_TXD3 | PPC_TXD1;
- PPSR |= PPC_TXD3 | PPC_TXD1;
-
- sa11x0_ppc_configure_mcp();
-
- if (machine_has_neponset()) {
-#ifndef CONFIG_ASSABET_NEPONSET
- printk( "Warning: Neponset detected but full support "
- "hasn't been configured in the kernel\n" );
-#else
- platform_device_register_simple("neponset", 0,
- neponset_resources, ARRAY_SIZE(neponset_resources));
-#endif
- } else {
- gpiod_add_lookup_table(&assabet_uart1_gpio_table);
- gpiod_add_lookup_table(&assabet_uart3_gpio_table);
- gpiod_add_lookup_table(&assabet_cf_vcc_gpio_table);
-
- sa11x0_register_fixed_regulator(0, &assabet_cf_vcc_pdata,
- assabet_cf_vcc_consumers,
- ARRAY_SIZE(assabet_cf_vcc_consumers),
- true);
-
- }
-
- software_node_register_node_group(assabet_gpio_keys_swnodes);
- platform_device_register_full(&assabet_gpio_keys_dev_info);
-
- gpiod_add_lookup_table(&assabet_leds_gpio_table);
- gpio_led_register_device(-1, &assabet_leds_pdata);
-
-#ifndef ASSABET_PAL_VIDEO
- sa11x0_register_lcd(&lq039q2ds54_info);
-#else
- sa11x0_register_lcd(&pal_video);
-#endif
- sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources,
- ARRAY_SIZE(assabet_flash_resources));
- sa11x0_register_mcp(&assabet_mcp_data);
-
- if (!machine_has_neponset())
- sa11x0_register_pcmcia(1, &assabet_cf_gpio_table);
-}
-
-/*
- * On Assabet, we must probe for the Neponset board _before_
- * paging_init() has occurred to actually determine the amount
- * of RAM available. To do so, we map the appropriate IO section
- * in the page table here in order to access GPIO registers.
- */
-static void __init map_sa1100_gpio_regs( void )
-{
- unsigned long phys = __PREG(GPLR) & PMD_MASK;
- unsigned long virt = (unsigned long)io_p2v(phys);
- int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO);
- pmd_t *pmd;
-
- pmd = pmd_off_k(virt);
- *pmd = __pmd(phys | prot);
- flush_pmd_entry(pmd);
-}
-
-/*
- * Read System Configuration "Register"
- * (taken from "Intel StrongARM SA-1110 Microprocessor Development Board
- * User's Guide", section 4.4.1)
- *
- * This same scan is performed in arch/arm/boot/compressed/head-sa1100.S
- * to set up the serial port for decompression status messages. We
- * repeat it here because the kernel may not be loaded as a zImage, and
- * also because it's a hassle to communicate the SCR value to the kernel
- * from the decompressor.
- *
- * Note that IRQs are guaranteed to be disabled.
- */
-static void __init get_assabet_scr(void)
-{
- unsigned long scr, i;
-
- GPDR |= 0x3fc; /* Configure GPIO 9:2 as outputs */
- GPSR = 0x3fc; /* Write 0xFF to GPIO 9:2 */
- GPDR &= ~(0x3fc); /* Configure GPIO 9:2 as inputs */
- for(i = 100; i--; ) /* Read GPIO 9:2 */
- scr = GPLR;
- GPDR |= 0x3fc; /* restore correct pin direction */
- scr &= 0x3fc; /* save as system configuration byte. */
- SCR_value = scr;
-}
-
-static void __init
-fixup_assabet(struct tag *tags, char **cmdline)
-{
- /* This must be done before any call to machine_has_neponset() */
- map_sa1100_gpio_regs();
- get_assabet_scr();
-
- if (machine_has_neponset())
- printk("Neponset expansion board detected\n");
-}
-
-
-static void assabet_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
-{
- if (port->mapbase == _Ser1UTCR0) {
- if (state)
- ASSABET_BCR_clear(ASSABET_BCR_RS232EN);
- else
- ASSABET_BCR_set(ASSABET_BCR_RS232EN);
- }
-}
-
-static struct sa1100_port_fns assabet_port_fns __initdata = {
- .pm = assabet_uart_pm,
-};
-
-static struct map_desc assabet_io_desc[] __initdata = {
- { /* Board Control Register */
- .virtual = 0xf1000000,
- .pfn = __phys_to_pfn(0x12000000),
- .length = 0x00100000,
- .type = MT_DEVICE
- }, { /* MQ200 */
- .virtual = 0xf2800000,
- .pfn = __phys_to_pfn(0x4b800000),
- .length = 0x00800000,
- .type = MT_DEVICE
- }
-};
-
-static void __init assabet_map_io(void)
-{
- sa1100_map_io();
- iotable_init(assabet_io_desc, ARRAY_SIZE(assabet_io_desc));
-
- /*
- * Set SUS bit in SDCR0 so serial port 1 functions.
- * Its called GPCLKR0 in my SA1110 manual.
- */
- Ser1SDCR0 |= SDCR0_SUS;
- MSC1 = (MSC1 & ~0xffff) |
- MSC_NonBrst | MSC_32BitStMem |
- MSC_RdAcc(2) | MSC_WrAcc(2) | MSC_Rec(0);
-
- if (!machine_has_neponset())
- sa1100_register_uart_fns(&assabet_port_fns);
-
- /*
- * When Neponset is attached, the first UART should be
- * UART3. That's what Angel is doing and many documents
- * are stating this.
- *
- * We do the Neponset mapping even if Neponset support
- * isn't compiled in so the user will still get something on
- * the expected physical serial port.
- *
- * We no longer do this; not all boot loaders support it,
- * and UART3 appears to be somewhat unreliable with blob.
- */
- sa1100_register_uart(0, 1);
- sa1100_register_uart(2, 3);
-}
-
-static void __init assabet_init_irq(void)
-{
- u32 def_val;
-
- sa1100_init_irq();
-
- if (machine_has_neponset())
- def_val = ASSABET_BCR_DB1111;
- else
- def_val = ASSABET_BCR_DB1110;
-
- /*
- * Angel sets this, but other bootloaders may not.
- *
- * This must precede any driver calls to BCR_set() or BCR_clear().
- */
- assabet_init_gpio((void *)&ASSABET_BCR, def_val);
-}
-
-MACHINE_START(ASSABET, "Intel-Assabet")
- .atag_offset = 0x100,
- .fixup = fixup_assabet,
- .map_io = assabet_map_io,
- .nr_irqs = SA1100_NR_IRQS,
- .init_irq = assabet_init_irq,
- .init_time = sa1100_timer_init,
- .init_machine = assabet_init,
- .init_late = sa11x0_init_late,
-#ifdef CONFIG_SA1111
- .dma_zone_size = SZ_1M,
-#endif
- .restart = sa11x0_restart,
-MACHINE_END
diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c
deleted file mode 100644
index eafeb38502af..000000000000
--- a/arch/arm/mach-sa1100/clock.c
+++ /dev/null
@@ -1,145 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/arm/mach-sa1100/clock.c
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-
-#include <mach/hardware.h>
-#include <mach/generic.h>
-
-static const char * const clk_tucr_parents[] = {
- "clk32768", "clk3686400",
-};
-
-static DEFINE_SPINLOCK(tucr_lock);
-
-static int clk_gpio27_enable(struct clk_hw *hw)
-{
- unsigned long flags;
-
- /*
- * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
- * (SA-1110 Developer's Manual, section 9.1.2.1)
- */
- local_irq_save(flags);
- GAFR |= GPIO_32_768kHz;
- GPDR |= GPIO_32_768kHz;
- local_irq_restore(flags);
-
- return 0;
-}
-
-static void clk_gpio27_disable(struct clk_hw *hw)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- GPDR &= ~GPIO_32_768kHz;
- GAFR &= ~GPIO_32_768kHz;
- local_irq_restore(flags);
-}
-
-static const struct clk_ops clk_gpio27_ops = {
- .enable = clk_gpio27_enable,
- .disable = clk_gpio27_disable,
-};
-
-static const char * const clk_gpio27_parents[] = {
- "tucr-mux",
-};
-
-static const struct clk_init_data clk_gpio27_init_data __initconst = {
- .name = "gpio27",
- .ops = &clk_gpio27_ops,
- .parent_names = clk_gpio27_parents,
- .num_parents = ARRAY_SIZE(clk_gpio27_parents),
-};
-
-/*
- * Derived from the table 8-1 in the SA1110 manual, the MPLL appears to
- * multiply its input rate by 4 x (4 + PPCR). This calculation gives
- * the exact rate. The figures given in the table are the rates rounded
- * to 100kHz. Stick with sa11x0_getspeed() for the time being.
- */
-static unsigned long clk_mpll_recalc_rate(struct clk_hw *hw,
- unsigned long prate)
-{
- return sa11x0_getspeed(0) * 1000;
-}
-
-static const struct clk_ops clk_mpll_ops = {
- .recalc_rate = clk_mpll_recalc_rate,
-};
-
-static const char * const clk_mpll_parents[] = {
- "clk3686400",
-};
-
-static const struct clk_init_data clk_mpll_init_data __initconst = {
- .name = "mpll",
- .ops = &clk_mpll_ops,
- .parent_names = clk_mpll_parents,
- .num_parents = ARRAY_SIZE(clk_mpll_parents),
- .flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL,
-};
-
-int __init sa11xx_clk_init(void)
-{
- struct clk_hw *hw;
- int ret;
-
- hw = clk_hw_register_fixed_rate(NULL, "clk32768", NULL, 0, 32768);
- if (IS_ERR(hw))
- return PTR_ERR(hw);
-
- clk_hw_register_clkdev(hw, NULL, "sa1100-rtc");
-
- hw = clk_hw_register_fixed_rate(NULL, "clk3686400", NULL, 0, 3686400);
- if (IS_ERR(hw))
- return PTR_ERR(hw);
-
- clk_hw_register_clkdev(hw, "OSTIMER0", NULL);
-
- hw = kzalloc_obj(*hw);
- if (!hw)
- return -ENOMEM;
- hw->init = &clk_mpll_init_data;
- ret = clk_hw_register(NULL, hw);
- if (ret) {
- kfree(hw);
- return ret;
- }
-
- clk_hw_register_clkdev(hw, NULL, "sa11x0-fb");
- clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia");
- clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.0");
- clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.1");
- clk_hw_register_clkdev(hw, NULL, "1800");
-
- hw = clk_hw_register_mux(NULL, "tucr-mux", clk_tucr_parents,
- ARRAY_SIZE(clk_tucr_parents), 0,
- (void __iomem *)&TUCR, FShft(TUCR_TSEL),
- FAlnMsk(TUCR_TSEL), 0, &tucr_lock);
- clk_set_rate(hw->clk, 3686400);
-
- hw = kzalloc_obj(*hw);
- if (!hw)
- return -ENOMEM;
- hw->init = &clk_gpio27_init_data;
- ret = clk_hw_register(NULL, hw);
- if (ret) {
- kfree(hw);
- return ret;
- }
-
- clk_hw_register_clkdev(hw, NULL, "sa1111.0");
-
- return 0;
-}
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
deleted file mode 100644
index d1931f51c900..000000000000
--- a/arch/arm/mach-sa1100/collie.c
+++ /dev/null
@@ -1,447 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/collie.c
- *
- * May be copied or modified under the terms of the GNU General Public
- * License. See linux/COPYING for more information.
- *
- * This file contains all Collie-specific tweaks.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * ChangeLog:
- * 2006 Pavel Machek <pavel@ucw.cz>
- * 03-06-2004 John Lenz <lenz@cs.wisc.edu>
- * 06-04-2002 Chris Larson <kergoth@digitalnemesis.net>
- * 04-16-2001 Lineo Japan,Inc. ...
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/tty.h>
-#include <linux/delay.h>
-#include <linux/platform_data/sa11x0-serial.h>
-#include <linux/platform_device.h>
-#include <linux/mfd/ucb1x00.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/timer.h>
-#include <linux/gpio/property.h>
-#include <linux/input.h>
-#include <linux/gpio/legacy.h>
-#include <linux/gpio/machine.h>
-#include <linux/property.h>
-#include <linux/power/gpio-charger.h>
-
-#include <video/sa1100fb.h>
-
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/page.h>
-#include <asm/setup.h>
-#include <mach/collie.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/map.h>
-
-#include <asm/hardware/scoop.h>
-#include <asm/mach/sharpsl_param.h>
-#include <asm/hardware/locomo.h>
-#include <linux/platform_data/mfd-mcp-sa11x0.h>
-#include <mach/irqs.h>
-
-#include "generic.h"
-
-static struct resource collie_scoop_resources[] = {
- [0] = DEFINE_RES_MEM(0x40800000, SZ_4K),
-};
-
-static struct scoop_config collie_scoop_setup = {
- .io_dir = COLLIE_SCOOP_IO_DIR,
- .io_out = COLLIE_SCOOP_IO_OUT,
- .gpio_base = COLLIE_SCOOP_GPIO_BASE,
-};
-
-struct platform_device colliescoop_device = {
- .name = "sharp-scoop",
- .id = -1,
- .dev = {
- .platform_data = &collie_scoop_setup,
- },
- .num_resources = ARRAY_SIZE(collie_scoop_resources),
- .resource = collie_scoop_resources,
-};
-
-static struct scoop_pcmcia_dev collie_pcmcia_scoop[] = {
- {
- .dev = &colliescoop_device.dev,
- .irq = COLLIE_IRQ_GPIO_CF_IRQ,
- .cd_irq = COLLIE_IRQ_GPIO_CF_CD,
- .cd_irq_str = "PCMCIA0 CD",
- },
-};
-
-static struct scoop_pcmcia_config collie_pcmcia_config = {
- .devs = &collie_pcmcia_scoop[0],
- .num_devs = 1,
-};
-
-static struct ucb1x00_plat_data collie_ucb1x00_data = {
- .gpio_base = COLLIE_TC35143_GPIO_BASE,
-};
-
-static struct mcp_plat_data collie_mcp_data = {
- .mccr0 = MCCR0_ADM | MCCR0_ExtClk,
- .sclk_rate = 9216000,
- .codec_pdata = &collie_ucb1x00_data,
-};
-
-/* Battery management GPIOs */
-static struct gpiod_lookup_table collie_battery_gpiod_table = {
- /* the MCP codec mcp0 has the ucb1x00 as attached device */
- .dev_id = "ucb1x00",
- .table = {
- /* This is found on the main GPIO on the SA1100 */
- GPIO_LOOKUP("gpio", COLLIE_GPIO_CO,
- "main battery full", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio", COLLIE_GPIO_MAIN_BAT_LOW,
- "main battery low", GPIO_ACTIVE_HIGH),
- /*
- * This is GPIO 0 on the Scoop expander, which is registered
- * from common/scoop.c with this gpio chip label.
- */
- GPIO_LOOKUP("sharp-scoop", 0,
- "main charge on", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-/*
- * Collie AC IN
- */
-static struct gpiod_lookup_table collie_power_gpiod_table = {
- .dev_id = "gpio-charger",
- .table = {
- GPIO_LOOKUP("gpio", COLLIE_GPIO_AC_IN,
- NULL, GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static char *collie_ac_supplied_to[] = {
- "main-battery",
- "backup-battery",
-};
-
-static struct gpio_charger_platform_data collie_power_data = {
- .name = "charger",
- .type = POWER_SUPPLY_TYPE_MAINS,
- .supplied_to = collie_ac_supplied_to,
- .num_supplicants = ARRAY_SIZE(collie_ac_supplied_to),
-};
-
-static struct platform_device collie_power_device = {
- .name = "gpio-charger",
- .id = -1,
- .dev.platform_data = &collie_power_data,
-};
-
-#ifdef CONFIG_SHARP_LOCOMO
-/*
- * low-level UART features.
- */
-struct platform_device collie_locomo_device;
-
-static void collie_uart_set_mctrl(struct uart_port *port, u_int mctrl)
-{
- if (mctrl & TIOCM_RTS)
- locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 0);
- else
- locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 1);
-
- if (mctrl & TIOCM_DTR)
- locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 0);
- else
- locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 1);
-}
-
-static u_int collie_uart_get_mctrl(struct uart_port *port)
-{
- int ret = TIOCM_CD;
- unsigned int r;
-
- r = locomo_gpio_read_output(&collie_locomo_device.dev, LOCOMO_GPIO_CTS & LOCOMO_GPIO_DSR);
- if (r == -ENODEV)
- return ret;
- if (r & LOCOMO_GPIO_CTS)
- ret |= TIOCM_CTS;
- if (r & LOCOMO_GPIO_DSR)
- ret |= TIOCM_DSR;
-
- return ret;
-}
-
-static struct sa1100_port_fns collie_port_fns __initdata = {
- .set_mctrl = collie_uart_set_mctrl,
- .get_mctrl = collie_uart_get_mctrl,
-};
-
-static int collie_uart_probe(struct locomo_dev *dev)
-{
- return 0;
-}
-
-static struct locomo_driver collie_uart_driver = {
- .drv = {
- .name = "collie_uart",
- },
- .devid = LOCOMO_DEVID_UART,
- .probe = collie_uart_probe,
-};
-
-static int __init collie_uart_init(void)
-{
- return locomo_driver_register(&collie_uart_driver);
-}
-device_initcall(collie_uart_init);
-
-#endif
-
-
-static struct resource locomo_resources[] = {
- [0] = DEFINE_RES_MEM(0x40000000, SZ_8K),
- [1] = DEFINE_RES_IRQ(IRQ_GPIO25),
-};
-
-static struct locomo_platform_data locomo_info = {
- .irq_base = IRQ_BOARD_START,
-};
-
-struct platform_device collie_locomo_device = {
- .name = "locomo",
- .id = 0,
- .dev = {
- .platform_data = &locomo_info,
- },
- .num_resources = ARRAY_SIZE(locomo_resources),
- .resource = locomo_resources,
-};
-
-static const struct software_node collie_gpio_keys_node = {
- .name = "collie-gpio-keys",
-};
-
-static const struct property_entry collie_on_key_props[] = {
- PROPERTY_ENTRY_U32("linux,code", KEY_RESERVED),
- PROPERTY_ENTRY_GPIO("gpios", &sa1100_gpiochip_node,
- COLLIE_GPIO_ON_KEY, GPIO_ACTIVE_LOW),
- PROPERTY_ENTRY_STRING("label", "On key"),
- PROPERTY_ENTRY_U32("linux,input-type", EV_PWR),
- PROPERTY_ENTRY_BOOL("wakeup-source"),
- { }
-};
-
-static const struct software_node collie_on_key_node = {
- .parent = &collie_gpio_keys_node,
- .properties = collie_on_key_props,
-};
-
-static const struct property_entry collie_wakeup_key_props[] = {
- PROPERTY_ENTRY_U32("linux,code", KEY_WAKEUP),
- PROPERTY_ENTRY_GPIO("gpios", &sa1100_gpiochip_node,
- COLLIE_GPIO_WAKEUP, GPIO_ACTIVE_LOW),
- PROPERTY_ENTRY_STRING("label", "Sync"),
- PROPERTY_ENTRY_U32("linux,input-type", EV_PWR),
- PROPERTY_ENTRY_BOOL("wakeup-source"),
- { }
-};
-
-static const struct software_node collie_wakeup_key_node = {
- .parent = &collie_gpio_keys_node,
- .properties = collie_wakeup_key_props,
-};
-
-static const struct software_node * const collie_gpio_keys_swnodes[] __initconst = {
- &collie_gpio_keys_node,
- &collie_on_key_node,
- &collie_wakeup_key_node,
- NULL
-};
-
-static const struct platform_device_info collie_gpio_keys_dev_info __initconst = {
- .name = "gpio-keys",
- .id = PLATFORM_DEVID_NONE,
- .swnode = &collie_gpio_keys_node,
-};
-
-static struct platform_device *devices[] __initdata = {
- &collie_locomo_device,
- &colliescoop_device,
- &collie_power_device,
-};
-
-static struct mtd_partition collie_partitions[] = {
- {
- .name = "bootloader",
- .offset = 0,
- .size = 0x000C0000,
- .mask_flags = MTD_WRITEABLE
- }, {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = 0x00100000,
- }, {
- .name = "rootfs",
- .offset = MTDPART_OFS_APPEND,
- .size = 0x00e20000,
- }, {
- .name = "bootblock",
- .offset = MTDPART_OFS_APPEND,
- .size = 0x00020000,
- .mask_flags = MTD_WRITEABLE
- }
-};
-
-static int collie_flash_init(void)
-{
- int rc = gpio_request(COLLIE_GPIO_VPEN, "flash Vpp enable");
- if (rc)
- return rc;
-
- rc = gpio_direction_output(COLLIE_GPIO_VPEN, 1);
- if (rc)
- gpio_free(COLLIE_GPIO_VPEN);
-
- return rc;
-}
-
-static void collie_set_vpp(int vpp)
-{
- gpio_set_value(COLLIE_GPIO_VPEN, vpp);
-}
-
-static void collie_flash_exit(void)
-{
- gpio_free(COLLIE_GPIO_VPEN);
-}
-
-static struct flash_platform_data collie_flash_data = {
- .map_name = "cfi_probe",
- .init = collie_flash_init,
- .set_vpp = collie_set_vpp,
- .exit = collie_flash_exit,
- .parts = collie_partitions,
- .nr_parts = ARRAY_SIZE(collie_partitions),
-};
-
-static struct resource collie_flash_resources[] = {
- DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
-};
-
-static struct sa1100fb_mach_info collie_lcd_info = {
- .pixclock = 171521, .bpp = 16,
- .xres = 320, .yres = 240,
-
- .hsync_len = 5, .vsync_len = 1,
- .left_margin = 11, .upper_margin = 2,
- .right_margin = 30, .lower_margin = 0,
-
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-
- .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
- .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
-
-#ifdef CONFIG_BACKLIGHT_LOCOMO
- .lcd_power = locomolcd_power
-#endif
-};
-
-static void __init collie_init(void)
-{
- int ret = 0;
-
- /* cpu initialize */
- GAFR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM | GPIO_SSP_CLK |
- GPIO_MCP_CLK | GPIO_32_768kHz;
-
- GPDR = GPIO_LDD8 | GPIO_LDD9 | GPIO_LDD10 | GPIO_LDD11 | GPIO_LDD12 |
- GPIO_LDD13 | GPIO_LDD14 | GPIO_LDD15 | GPIO_SSP_TXD |
- GPIO_SSP_SCLK | GPIO_SSP_SFRM | GPIO_SDLC_SCLK |
- _COLLIE_GPIO_UCB1x00_RESET | _COLLIE_GPIO_nMIC_ON |
- _COLLIE_GPIO_nREMOCON_ON | GPIO_32_768kHz;
-
- PPDR = PPC_LDD0 | PPC_LDD1 | PPC_LDD2 | PPC_LDD3 | PPC_LDD4 | PPC_LDD5 |
- PPC_LDD6 | PPC_LDD7 | PPC_L_PCLK | PPC_L_LCLK | PPC_L_FCLK | PPC_L_BIAS |
- PPC_TXD1 | PPC_TXD2 | PPC_TXD3 | PPC_TXD4 | PPC_SCLK | PPC_SFRM;
-
- PWER = 0;
-
- PGSR = _COLLIE_GPIO_nREMOCON_ON;
-
- PSDR = PPC_RXD1 | PPC_RXD2 | PPC_RXD3 | PPC_RXD4;
-
- PCFR = PCFR_OPDE;
-
- GPSR |= _COLLIE_GPIO_UCB1x00_RESET;
-
- sa11x0_ppc_configure_mcp();
-
-
- platform_scoop_config = &collie_pcmcia_config;
-
- gpiod_add_lookup_table(&collie_power_gpiod_table);
- gpiod_add_lookup_table(&collie_battery_gpiod_table);
-
- ret = platform_add_devices(devices, ARRAY_SIZE(devices));
- if (ret) {
- printk(KERN_WARNING "collie: Unable to register LoCoMo device\n");
- }
-
- software_node_register_node_group(collie_gpio_keys_swnodes);
- platform_device_register_full(&collie_gpio_keys_dev_info);
-
- sa11x0_register_lcd(&collie_lcd_info);
- sa11x0_register_mtd(&collie_flash_data, collie_flash_resources,
- ARRAY_SIZE(collie_flash_resources));
- sa11x0_register_mcp(&collie_mcp_data);
-
- sharpsl_save_param();
-}
-
-static struct map_desc collie_io_desc[] __initdata = {
- { /* 32M main flash (cs0) */
- .virtual = 0xe8000000,
- .pfn = __phys_to_pfn(0x00000000),
- .length = 0x02000000,
- .type = MT_DEVICE
- }, { /* 32M boot flash (cs1) */
- .virtual = 0xea000000,
- .pfn = __phys_to_pfn(0x08000000),
- .length = 0x02000000,
- .type = MT_DEVICE
- }
-};
-
-static void __init collie_map_io(void)
-{
- sa1100_map_io();
- iotable_init(collie_io_desc, ARRAY_SIZE(collie_io_desc));
-
-#ifdef CONFIG_SHARP_LOCOMO
- sa1100_register_uart_fns(&collie_port_fns);
-#endif
- sa1100_register_uart(0, 3);
- sa1100_register_uart(1, 1);
-}
-
-MACHINE_START(COLLIE, "Sharp-Collie")
- .map_io = collie_map_io,
- .nr_irqs = SA1100_NR_IRQS,
- .init_irq = sa1100_init_irq,
- .init_time = sa1100_timer_init,
- .init_machine = collie_init,
- .init_late = sa11x0_init_late,
- .restart = sa11x0_restart,
-MACHINE_END
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
deleted file mode 100644
index a995625ab1a0..000000000000
--- a/arch/arm/mach-sa1100/generic.c
+++ /dev/null
@@ -1,470 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-sa1100/generic.c
- *
- * Author: Nicolas Pitre
- *
- * Code common to all SA11x0 machines.
- */
-#include <linux/gpio/consumer.h>
-#include <linux/gpio/machine.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/pm.h>
-#include <linux/cpufreq.h>
-#include <linux/ioport.h>
-#include <linux/platform_device.h>
-#include <linux/reboot.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-#include <linux/irqchip/irq-sa11x0.h>
-
-#include <video/sa1100fb.h>
-
-#include <soc/sa1100/pwer.h>
-
-#include <asm/div64.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/irq.h>
-#include <asm/system_misc.h>
-
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <mach/reset.h>
-
-#include "generic.h"
-#include <clocksource/pxa.h>
-
-#define NR_FREQS 16
-
-/*
- * This table is setup for a 3.6864MHz Crystal.
- */
-struct cpufreq_frequency_table sa11x0_freq_table[NR_FREQS+1] = {
- { .frequency = 59000, /* 59.0 MHz */},
- { .frequency = 73700, /* 73.7 MHz */},
- { .frequency = 88500, /* 88.5 MHz */},
- { .frequency = 103200, /* 103.2 MHz */},
- { .frequency = 118000, /* 118.0 MHz */},
- { .frequency = 132700, /* 132.7 MHz */},
- { .frequency = 147500, /* 147.5 MHz */},
- { .frequency = 162200, /* 162.2 MHz */},
- { .frequency = 176900, /* 176.9 MHz */},
- { .frequency = 191700, /* 191.7 MHz */},
- { .frequency = 206400, /* 206.4 MHz */},
- { .frequency = 221200, /* 221.2 MHz */},
- { .frequency = 235900, /* 235.9 MHz */},
- { .frequency = 250700, /* 250.7 MHz */},
- { .frequency = 265400, /* 265.4 MHz */},
- { .frequency = 280200, /* 280.2 MHz */},
- { .frequency = CPUFREQ_TABLE_END, },
-};
-
-unsigned int sa11x0_getspeed(unsigned int cpu)
-{
- if (cpu)
- return 0;
- return sa11x0_freq_table[PPCR & 0xf].frequency;
-}
-
-/*
- * Default power-off for SA1100
- */
-static void sa1100_power_off(void)
-{
- mdelay(100);
- local_irq_disable();
- /* disable internal oscillator, float CS lines */
- PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
- /* enable wake-up on GPIO0 (Assabet...) */
- PWER = GFER = GRER = 1;
- /*
- * set scratchpad to zero, just in case it is used as a
- * restart address by the bootloader.
- */
- PSPR = 0;
- /* enter sleep mode */
- PMCR = PMCR_SF;
-}
-
-void sa11x0_restart(enum reboot_mode mode, const char *cmd)
-{
- clear_reset_status(RESET_STATUS_ALL);
-
- if (mode == REBOOT_SOFT) {
- /* Jump into ROM at address 0 */
- soft_restart(0);
- } else {
- /* Use on-chip reset capability */
- RSRR = RSRR_SWR;
- }
-}
-
-static void sa11x0_register_device(struct platform_device *dev, void *data)
-{
- int err;
- dev->dev.platform_data = data;
- err = platform_device_register(dev);
- if (err)
- printk(KERN_ERR "Unable to register device %s: %d\n",
- dev->name, err);
-}
-
-
-static struct resource sa11x0udc_resources[] = {
- [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
- [1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
-};
-
-static u64 sa11x0udc_dma_mask = 0xffffffffUL;
-
-static struct platform_device sa11x0udc_device = {
- .name = "sa11x0-udc",
- .id = -1,
- .dev = {
- .dma_mask = &sa11x0udc_dma_mask,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(sa11x0udc_resources),
- .resource = sa11x0udc_resources,
-};
-
-static struct resource sa11x0uart1_resources[] = {
- [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
- [1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
-};
-
-static struct platform_device sa11x0uart1_device = {
- .name = "sa11x0-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(sa11x0uart1_resources),
- .resource = sa11x0uart1_resources,
-};
-
-static struct resource sa11x0uart3_resources[] = {
- [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
- [1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
-};
-
-static struct platform_device sa11x0uart3_device = {
- .name = "sa11x0-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(sa11x0uart3_resources),
- .resource = sa11x0uart3_resources,
-};
-
-static struct resource sa11x0mcp_resources[] = {
- [0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
- [1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4),
- [2] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
-};
-
-static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
-
-static struct platform_device sa11x0mcp_device = {
- .name = "sa11x0-mcp",
- .id = -1,
- .dev = {
- .dma_mask = &sa11x0mcp_dma_mask,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(sa11x0mcp_resources),
- .resource = sa11x0mcp_resources,
-};
-
-void __init sa11x0_ppc_configure_mcp(void)
-{
- /* Setup the PPC unit for the MCP */
- PPDR &= ~PPC_RXD4;
- PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
- PSDR |= PPC_RXD4;
- PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
- PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
-}
-
-void sa11x0_register_mcp(struct mcp_plat_data *data)
-{
- sa11x0_register_device(&sa11x0mcp_device, data);
-}
-
-static struct resource sa11x0ssp_resources[] = {
- [0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
- [1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
-};
-
-static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
-
-static struct platform_device sa11x0ssp_device = {
- .name = "sa11x0-ssp",
- .id = -1,
- .dev = {
- .dma_mask = &sa11x0ssp_dma_mask,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(sa11x0ssp_resources),
- .resource = sa11x0ssp_resources,
-};
-
-static struct resource sa11x0fb_resources[] = {
- [0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
- [1] = DEFINE_RES_IRQ(IRQ_LCD),
-};
-
-static struct platform_device sa11x0fb_device = {
- .name = "sa11x0-fb",
- .id = -1,
- .dev = {
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(sa11x0fb_resources),
- .resource = sa11x0fb_resources,
-};
-
-void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
-{
- sa11x0_register_device(&sa11x0fb_device, inf);
-}
-
-void sa11x0_register_pcmcia(int socket, struct gpiod_lookup_table *table)
-{
- if (table)
- gpiod_add_lookup_table(table);
- platform_device_register_simple("sa11x0-pcmcia", socket, NULL, 0);
-}
-
-static struct platform_device sa11x0mtd_device = {
- .name = "sa1100-mtd",
- .id = -1,
-};
-
-void sa11x0_register_mtd(struct flash_platform_data *flash,
- struct resource *res, int nr)
-{
- flash->name = "sa1100";
- sa11x0mtd_device.resource = res;
- sa11x0mtd_device.num_resources = nr;
- sa11x0_register_device(&sa11x0mtd_device, flash);
-}
-
-static struct resource sa1100_rtc_resources[] = {
- DEFINE_RES_MEM(0x90010000, 0x40),
- DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
- DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
-};
-
-static struct platform_device sa11x0rtc_device = {
- .name = "sa1100-rtc",
- .id = -1,
- .num_resources = ARRAY_SIZE(sa1100_rtc_resources),
- .resource = sa1100_rtc_resources,
-};
-
-static struct resource sa11x0dma_resources[] = {
- DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
- DEFINE_RES_IRQ(IRQ_DMA0),
- DEFINE_RES_IRQ(IRQ_DMA1),
- DEFINE_RES_IRQ(IRQ_DMA2),
- DEFINE_RES_IRQ(IRQ_DMA3),
- DEFINE_RES_IRQ(IRQ_DMA4),
- DEFINE_RES_IRQ(IRQ_DMA5),
-};
-
-static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device sa11x0dma_device = {
- .name = "sa11x0-dma",
- .id = -1,
- .dev = {
- .dma_mask = &sa11x0dma_dma_mask,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(sa11x0dma_resources),
- .resource = sa11x0dma_resources,
-};
-
-static struct platform_device *sa11x0_devices[] __initdata = {
- &sa11x0udc_device,
- &sa11x0uart1_device,
- &sa11x0uart3_device,
- &sa11x0ssp_device,
- &sa11x0rtc_device,
- &sa11x0dma_device,
-};
-
-static int __init sa1100_init(void)
-{
- struct resource wdt_res = DEFINE_RES_MEM(0x90000000, 0x20);
- register_platform_power_off(sa1100_power_off);
-
- regulator_has_full_constraints();
-
- platform_device_register_simple("sa1100_wdt", -1, &wdt_res, 1);
-
- return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
-}
-
-arch_initcall(sa1100_init);
-
-void __init sa11x0_init_late(void)
-{
- sa11x0_pm_init();
-}
-
-int __init sa11x0_register_fixed_regulator(int n,
- struct fixed_voltage_config *cfg,
- struct regulator_consumer_supply *supplies, unsigned num_supplies,
- bool uses_gpio)
-{
- struct regulator_init_data *id;
-
- cfg->init_data = id = kzalloc_obj(*cfg->init_data);
- if (!cfg->init_data)
- return -ENOMEM;
-
- if (!uses_gpio)
- id->constraints.always_on = 1;
- id->constraints.name = cfg->supply_name;
- id->constraints.min_uV = cfg->microvolts;
- id->constraints.max_uV = cfg->microvolts;
- id->constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
- id->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
- id->consumer_supplies = supplies;
- id->num_consumer_supplies = num_supplies;
-
- platform_device_register_resndata(NULL, "reg-fixed-voltage", n,
- NULL, 0, cfg, sizeof(*cfg));
- return 0;
-}
-
-/*
- * Common I/O mapping:
- *
- * Typically, static virtual address mappings are as follow:
- *
- * 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.)
- * 0xf4000000-0xf4ffffff: SA-1111
- * 0xf5000000-0xf5ffffff: reserved (used by cache flushing area)
- * 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above)
- * 0xffff0000-0xffff0fff: SA1100 exception vectors
- * 0xffff2000-0xffff2fff: Minicache copy_user_page area
- *
- * Below 0xe8000000 is reserved for vm allocation.
- *
- * The machine specific code must provide the extra mapping beside the
- * default mapping provided here.
- */
-
-static struct map_desc standard_io_desc[] __initdata = {
- { /* PCM */
- .virtual = 0xf8000000,
- .pfn = __phys_to_pfn(0x80000000),
- .length = 0x00100000,
- .type = MT_DEVICE
- }, { /* SCM */
- .virtual = 0xfa000000,
- .pfn = __phys_to_pfn(0x90000000),
- .length = 0x00100000,
- .type = MT_DEVICE
- }, { /* MER */
- .virtual = 0xfc000000,
- .pfn = __phys_to_pfn(0xa0000000),
- .length = 0x00100000,
- .type = MT_DEVICE
- }, { /* LCD + DMA */
- .virtual = 0xfe000000,
- .pfn = __phys_to_pfn(0xb0000000),
- .length = 0x00200000,
- .type = MT_DEVICE
- },
-};
-
-void __init sa1100_map_io(void)
-{
- iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
-}
-
-void __init sa1100_timer_init(void)
-{
- pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000));
-}
-
-static struct resource irq_resource =
- DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
-
-void __init sa1100_init_irq(void)
-{
- request_resource(&iomem_resource, &irq_resource);
-
- sa11x0_init_irq_nodt(IRQ_GPIO0_SC, irq_resource.start);
-
- sa1100_init_gpio();
- sa11xx_clk_init();
-}
-
-/*
- * Disable the memory bus request/grant signals on the SA1110 to
- * ensure that we don't receive spurious memory requests. We set
- * the MBGNT signal false to ensure the SA1111 doesn't own the
- * SDRAM bus.
- */
-void sa1110_mb_disable(void)
-{
- unsigned long flags;
-
- local_irq_save(flags);
-
- PGSR &= ~GPIO_MBGNT;
- GPCR = GPIO_MBGNT;
- GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
-
- GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);
-
- local_irq_restore(flags);
-}
-
-/*
- * If the system is going to use the SA-1111 DMA engines, set up
- * the memory bus request/grant pins.
- */
-void sa1110_mb_enable(void)
-{
- unsigned long flags;
-
- local_irq_save(flags);
-
- PGSR &= ~GPIO_MBGNT;
- GPCR = GPIO_MBGNT;
- GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
-
- GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
- TUCR |= TUCR_MR;
-
- local_irq_restore(flags);
-}
-
-int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on)
-{
- if (on)
- PWER |= BIT(gpio);
- else
- PWER &= ~BIT(gpio);
-
- return 0;
-}
-
-int sa11x0_sc_set_wake(unsigned int irq, unsigned int on)
-{
- if (BIT(irq) != IC_RTCAlrm)
- return -EINVAL;
-
- if (on)
- PWER |= PWER_RTC;
- else
- PWER &= ~PWER_RTC;
-
- return 0;
-}
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
deleted file mode 100644
index 3cfe3b647711..000000000000
--- a/arch/arm/mach-sa1100/generic.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/arm/mach-sa1100/generic.h
- *
- * Author: Nicolas Pitre
- */
-#include <linux/cpufreq.h>
-#include <linux/reboot.h>
-
-extern void sa1100_timer_init(void);
-extern void __init sa1100_map_io(void);
-extern void __init sa1100_init_irq(void);
-extern void __init sa1100_init_gpio(void);
-extern void sa11x0_restart(enum reboot_mode, const char *);
-extern void sa11x0_init_late(void);
-
-#define SET_BANK(__nr,__start,__size) \
- mi->bank[__nr].start = (__start), \
- mi->bank[__nr].size = (__size)
-
-extern void sa1110_mb_enable(void);
-extern void sa1110_mb_disable(void);
-
-extern struct cpufreq_frequency_table sa11x0_freq_table[];
-extern unsigned int sa11x0_getspeed(unsigned int cpu);
-
-struct flash_platform_data;
-struct resource;
-
-void sa11x0_register_mtd(struct flash_platform_data *flash,
- struct resource *res, int nr);
-
-struct mcp_plat_data;
-void sa11x0_ppc_configure_mcp(void);
-void sa11x0_register_mcp(struct mcp_plat_data *data);
-
-struct sa1100fb_mach_info;
-void sa11x0_register_lcd(struct sa1100fb_mach_info *inf);
-
-#ifdef CONFIG_PM
-int sa11x0_pm_init(void);
-#else
-static inline int sa11x0_pm_init(void) { return 0; }
-#endif
-
-int sa11xx_clk_init(void);
-
-struct gpiod_lookup_table;
-void sa11x0_register_pcmcia(int socket, struct gpiod_lookup_table *);
-
-struct software_node;
-extern const struct software_node sa1100_gpiochip_node;
-
-struct fixed_voltage_config;
-struct regulator_consumer_supply;
-int sa11x0_register_fixed_regulator(int n, struct fixed_voltage_config *cfg,
- struct regulator_consumer_supply *supplies, unsigned num_supplies,
- bool uses_gpio);
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
deleted file mode 100644
index 59e9251a138e..000000000000
--- a/arch/arm/mach-sa1100/h3600.c
+++ /dev/null
@@ -1,134 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Support for Compaq iPAQ H3600 handheld computer
- *
- * Copyright (c) 2000,1 Compaq Computer Corporation. (Author: Jamey Hicks)
- * Copyright (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru>
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/gpio/legacy.h>
-
-#include <video/sa1100fb.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <mach/h3xxx.h>
-#include <mach/irqs.h>
-
-#include "generic.h"
-
-static bool h3600_lcd_request(void)
-{
- static bool h3600_lcd_ok;
- int rc;
-
- if (h3600_lcd_ok)
- return true;
-
- rc = gpio_request(H3XXX_EGPIO_LCD_ON, "LCD power");
- if (rc)
- goto out;
- rc = gpio_direction_output(H3XXX_EGPIO_LCD_ON, 0);
- if (rc)
- goto out_free_on;
- rc = gpio_request(H3600_EGPIO_LCD_PCI, "LCD control");
- if (rc)
- goto out_free_on;
- rc = gpio_direction_output(H3600_EGPIO_LCD_PCI, 0);
- if (rc)
- goto out_free_pci;
- rc = gpio_request(H3600_EGPIO_LCD_5V_ON, "LCD 5v");
- if (rc)
- goto out_free_pci;
- rc = gpio_direction_output(H3600_EGPIO_LCD_5V_ON, 0);
- if (rc)
- goto out_free_5v_on;
- rc = gpio_request(H3600_EGPIO_LVDD_ON, "LCD 9v/-6.5v");
- if (rc)
- goto out_free_5v_on;
- rc = gpio_direction_output(H3600_EGPIO_LVDD_ON, 0);
- if (rc)
- goto out_free_lvdd_on;
-
- goto out;
-
-out_free_lvdd_on:
- gpio_free(H3600_EGPIO_LVDD_ON);
-out_free_5v_on:
- gpio_free(H3600_EGPIO_LCD_5V_ON);
-out_free_pci:
- gpio_free(H3600_EGPIO_LCD_PCI);
-out_free_on:
- gpio_free(H3XXX_EGPIO_LCD_ON);
-out:
- if (rc)
- pr_err("%s: can't request GPIOs\n", __func__);
- else
- h3600_lcd_ok = true;
-
- return h3600_lcd_ok;
-}
-
-static void h3600_lcd_power(int enable)
-{
- if (!h3600_lcd_request())
- return;
-
- gpio_direction_output(H3XXX_EGPIO_LCD_ON, enable);
- gpio_direction_output(H3600_EGPIO_LCD_PCI, enable);
- gpio_direction_output(H3600_EGPIO_LCD_5V_ON, enable);
- gpio_direction_output(H3600_EGPIO_LVDD_ON, enable);
-}
-
-static const struct sa1100fb_rgb h3600_rgb_16 = {
- .red = { .offset = 12, .length = 4, },
- .green = { .offset = 7, .length = 4, },
- .blue = { .offset = 1, .length = 4, },
- .transp = { .offset = 0, .length = 0, },
-};
-
-static struct sa1100fb_mach_info h3600_lcd_info = {
- .pixclock = 174757, .bpp = 16,
- .xres = 320, .yres = 240,
-
- .hsync_len = 3, .vsync_len = 3,
- .left_margin = 12, .upper_margin = 10,
- .right_margin = 17, .lower_margin = 1,
-
- .cmap_static = 1,
-
- .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
- .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
-
- .rgb[RGB_16] = &h3600_rgb_16,
-
- .lcd_power = h3600_lcd_power,
-};
-
-
-static void __init h3600_map_io(void)
-{
- h3xxx_map_io();
-}
-
-static void __init h3600_mach_init(void)
-{
- h3xxx_mach_init();
-
- sa11x0_register_lcd(&h3600_lcd_info);
-}
-
-MACHINE_START(H3600, "Compaq iPAQ H3600")
- .atag_offset = 0x100,
- .map_io = h3600_map_io,
- .nr_irqs = SA1100_NR_IRQS,
- .init_irq = sa1100_init_irq,
- .init_time = sa1100_timer_init,
- .init_machine = h3600_mach_init,
- .init_late = sa11x0_init_late,
- .restart = sa11x0_restart,
-MACHINE_END
-
diff --git a/arch/arm/mach-sa1100/h3xxx.c b/arch/arm/mach-sa1100/h3xxx.c
deleted file mode 100644
index 6f4c5d2be569..000000000000
--- a/arch/arm/mach-sa1100/h3xxx.c
+++ /dev/null
@@ -1,305 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Support for Compaq iPAQ H3100 and H3600 handheld computers (common code)
- *
- * Copyright (c) 2000,1 Compaq Computer Corporation. (Author: Jamey Hicks)
- * Copyright (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru>
- */
-
-#include <linux/kernel.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio/legacy.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio/property.h>
-#include <linux/gpio/consumer.h>
-#include <linux/input.h>
-#include <linux/property.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/platform_data/gpio-htc-egpio.h>
-#include <linux/platform_data/sa11x0-serial.h>
-#include <linux/platform_device.h>
-#include <linux/serial_core.h>
-
-#include <asm/mach/flash.h>
-#include <asm/mach/map.h>
-
-#include <mach/h3xxx.h>
-#include <mach/irqs.h>
-
-#include "generic.h"
-
-/*
- * H3xxx flash support
- */
-static struct mtd_partition h3xxx_partitions[] = {
- {
- .name = "H3XXX boot firmware",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- }, {
- .name = "H3XXX rootfs",
- .size = MTDPART_SIZ_FULL,
- .offset = 0x00040000,
- }
-};
-
-static void h3xxx_set_vpp(int vpp)
-{
- gpio_set_value(H3XXX_EGPIO_VPP_ON, vpp);
-}
-
-static int h3xxx_flash_init(void)
-{
- int err = gpio_request(H3XXX_EGPIO_VPP_ON, "Flash Vpp");
- if (err) {
- pr_err("%s: can't request H3XXX_EGPIO_VPP_ON\n", __func__);
- return err;
- }
-
- err = gpio_direction_output(H3XXX_EGPIO_VPP_ON, 0);
- if (err)
- gpio_free(H3XXX_EGPIO_VPP_ON);
-
- return err;
-}
-
-static void h3xxx_flash_exit(void)
-{
- gpio_free(H3XXX_EGPIO_VPP_ON);
-}
-
-static struct flash_platform_data h3xxx_flash_data = {
- .map_name = "cfi_probe",
- .set_vpp = h3xxx_set_vpp,
- .init = h3xxx_flash_init,
- .exit = h3xxx_flash_exit,
- .parts = h3xxx_partitions,
- .nr_parts = ARRAY_SIZE(h3xxx_partitions),
-};
-
-static struct resource h3xxx_flash_resource =
- DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
-
-
-/*
- * H3xxx uart support
- */
-static void h3xxx_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
-{
- if (port->mapbase == _Ser3UTCR0) {
- if (!gpio_request(H3XXX_EGPIO_RS232_ON, "RS232 transceiver")) {
- gpio_direction_output(H3XXX_EGPIO_RS232_ON, !state);
- gpio_free(H3XXX_EGPIO_RS232_ON);
- } else {
- pr_err("%s: can't request H3XXX_EGPIO_RS232_ON\n",
- __func__);
- }
- }
-}
-
-/*
- * Enable/Disable wake up events for this serial port.
- * Obviously, we only support this on the normal COM port.
- */
-static int h3xxx_uart_set_wake(struct uart_port *port, u_int enable)
-{
- int err = -EINVAL;
-
- if (port->mapbase == _Ser3UTCR0) {
- if (enable)
- PWER |= PWER_GPIO23 | PWER_GPIO25; /* DCD and CTS */
- else
- PWER &= ~(PWER_GPIO23 | PWER_GPIO25); /* DCD and CTS */
- err = 0;
- }
- return err;
-}
-
-static struct sa1100_port_fns h3xxx_port_fns __initdata = {
- .pm = h3xxx_uart_pm,
- .set_wake = h3xxx_uart_set_wake,
-};
-
-static struct gpiod_lookup_table h3xxx_uart3_gpio_table = {
- .dev_id = "sa11x0-uart.3",
- .table = {
- GPIO_LOOKUP("gpio", H3XXX_GPIO_COM_DCD, "dcd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio", H3XXX_GPIO_COM_CTS, "cts", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio", H3XXX_GPIO_COM_RTS, "rts", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-/*
- * EGPIO
- */
-
-static struct resource egpio_resources[] = {
- [0] = DEFINE_RES_MEM(H3600_EGPIO_PHYS, 0x4),
-};
-
-static struct htc_egpio_chip egpio_chips[] = {
- [0] = {
- .reg_start = 0,
- .gpio_base = H3XXX_EGPIO_BASE,
- .num_gpios = 16,
- .direction = HTC_EGPIO_OUTPUT,
- .initial_values = 0x0080, /* H3XXX_EGPIO_RS232_ON */
- },
-};
-
-static struct htc_egpio_platform_data egpio_info = {
- .reg_width = 16,
- .bus_width = 16,
- .chip = egpio_chips,
- .num_chips = ARRAY_SIZE(egpio_chips),
-};
-
-static struct platform_device h3xxx_egpio = {
- .name = "htc-egpio",
- .id = -1,
- .resource = egpio_resources,
- .num_resources = ARRAY_SIZE(egpio_resources),
- .dev = {
- .platform_data = &egpio_info,
- },
-};
-
-/*
- * GPIO keys
- */
-
-static const struct software_node h3xxx_gpio_keys_node = {
- .name = "h3xxx-gpio-keys",
-};
-
-static const struct property_entry h3xxx_power_key_props[] = {
- PROPERTY_ENTRY_U32("linux,code", KEY_POWER),
- PROPERTY_ENTRY_GPIO("gpios", &sa1100_gpiochip_node,
- H3XXX_GPIO_PWR_BUTTON, GPIO_ACTIVE_LOW),
- PROPERTY_ENTRY_STRING("label", "Power Button"),
- PROPERTY_ENTRY_BOOL("wakeup-source"),
- { }
-};
-
-static const struct software_node h3xxx_power_key_node = {
- .parent = &h3xxx_gpio_keys_node,
- .properties = h3xxx_power_key_props,
-};
-
-static const struct property_entry h3xxx_action_key_props[] = {
- PROPERTY_ENTRY_U32("linux,code", KEY_ENTER),
- PROPERTY_ENTRY_GPIO("gpios", &sa1100_gpiochip_node,
- H3XXX_GPIO_ACTION_BUTTON, GPIO_ACTIVE_LOW),
- PROPERTY_ENTRY_STRING("label", "Action button"),
- { }
-};
-
-static const struct software_node h3xxx_action_key_node = {
- .parent = &h3xxx_gpio_keys_node,
- .properties = h3xxx_action_key_props,
-};
-
-static const struct software_node * const h3xxx_gpio_keys_swnodes[] __initconst = {
- &h3xxx_gpio_keys_node,
- &h3xxx_power_key_node,
- &h3xxx_action_key_node,
- NULL
-};
-
-static const struct platform_device_info h3xxx_gpio_keys_dev_info __initconst = {
- .name = "gpio-keys",
- .id = PLATFORM_DEVID_NONE,
- .swnode = &h3xxx_gpio_keys_node,
-};
-
-static struct resource h3xxx_micro_resources[] = {
- DEFINE_RES_MEM(0x80010000, SZ_4K),
- DEFINE_RES_MEM(0x80020000, SZ_4K),
- DEFINE_RES_IRQ(IRQ_Ser1UART),
-};
-
-struct platform_device h3xxx_micro_asic = {
- .name = "ipaq-h3xxx-micro",
- .id = -1,
- .resource = h3xxx_micro_resources,
- .num_resources = ARRAY_SIZE(h3xxx_micro_resources),
-};
-
-static struct platform_device *h3xxx_devices[] = {
- &h3xxx_egpio,
- &h3xxx_micro_asic,
-};
-
-static struct gpiod_lookup_table h3xxx_pcmcia_gpio_table = {
- .dev_id = "sa11x0-pcmcia",
- .table = {
- GPIO_LOOKUP("gpio", H3XXX_GPIO_PCMCIA_CD0,
- "pcmcia0-detect", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio", H3XXX_GPIO_PCMCIA_IRQ0,
- "pcmcia0-ready", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio", H3XXX_GPIO_PCMCIA_CD1,
- "pcmcia1-detect", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio", H3XXX_GPIO_PCMCIA_IRQ1,
- "pcmcia1-ready", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-void __init h3xxx_mach_init(void)
-{
- gpiod_add_lookup_table(&h3xxx_pcmcia_gpio_table);
- gpiod_add_lookup_table(&h3xxx_uart3_gpio_table);
- sa1100_register_uart_fns(&h3xxx_port_fns);
- sa11x0_register_mtd(&h3xxx_flash_data, &h3xxx_flash_resource, 1);
- platform_add_devices(h3xxx_devices, ARRAY_SIZE(h3xxx_devices));
- software_node_register_node_group(h3xxx_gpio_keys_swnodes);
- platform_device_register_full(&h3xxx_gpio_keys_dev_info);
-}
-
-static struct map_desc h3600_io_desc[] __initdata = {
- { /* static memory bank 2 CS#2 */
- .virtual = H3600_BANK_2_VIRT,
- .pfn = __phys_to_pfn(SA1100_CS2_PHYS),
- .length = 0x02800000,
- .type = MT_DEVICE
- }, { /* static memory bank 4 CS#4 */
- .virtual = H3600_BANK_4_VIRT,
- .pfn = __phys_to_pfn(SA1100_CS4_PHYS),
- .length = 0x00800000,
- .type = MT_DEVICE
- }, { /* EGPIO 0 CS#5 */
- .virtual = H3600_EGPIO_VIRT,
- .pfn = __phys_to_pfn(H3600_EGPIO_PHYS),
- .length = 0x01000000,
- .type = MT_DEVICE
- }
-};
-
-/*
- * Common map_io initialization
- */
-
-void __init h3xxx_map_io(void)
-{
- sa1100_map_io();
- iotable_init(h3600_io_desc, ARRAY_SIZE(h3600_io_desc));
-
- sa1100_register_uart(0, 3); /* Common serial port */
-// sa1100_register_uart(1, 1); /* Microcontroller on 3100/3600 */
-
- /* Ensure those pins are outputs and driving low */
- PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
- PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
-
- /* Configure suspend conditions */
- PGSR = 0;
- PCFR = PCFR_OPDE;
- PSDR = 0;
-
- GPCR = 0x0fffffff; /* All outputs are set low by default */
- GPDR = 0; /* Configure all GPIOs as input */
-}
-
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
deleted file mode 100644
index 6e6ff3e18f0f..000000000000
--- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
+++ /dev/null
@@ -1,1798 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * FILE SA-1100.h
- *
- * Version 1.2
- * Author Copyright (c) Marc A. Viredaz, 1998
- * DEC Western Research Laboratory, Palo Alto, CA
- * Date January 1998 (April 1997)
- * System StrongARM SA-1100
- * Language C or ARM Assembly
- * Purpose Definition of constants related to the StrongARM
- * SA-1100 microprocessor (Advanced RISC Machine (ARM)
- * architecture version 4). This file is based on the
- * StrongARM SA-1100 data sheet version 2.2.
- *
- */
-
-
-/* Be sure that virtual mapping is defined right */
-#ifndef __ASM_ARCH_HARDWARE_H
-#error You must include hardware.h not SA-1100.h
-#endif
-
-#include "bitfield.h"
-
-/*
- * SA1100 CS line to physical address
- */
-
-#define SA1100_CS0_PHYS 0x00000000
-#define SA1100_CS1_PHYS 0x08000000
-#define SA1100_CS2_PHYS 0x10000000
-#define SA1100_CS3_PHYS 0x18000000
-#define SA1100_CS4_PHYS 0x40000000
-#define SA1100_CS5_PHYS 0x48000000
-
-/*
- * Personal Computer Memory Card International Association (PCMCIA) sockets
- */
-
-#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
-#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
-#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
-#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
-#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
-
-#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
-#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
-#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
-#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
-
-#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
-#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
-#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
-#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
-
-#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
- (0x20000000 + (Nb)*PCMCIASp)
-#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
-#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
- (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
-#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
- (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
-
-#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
-#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
-#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
-#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
-
-#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
-#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
-#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
-#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
-
-
-/*
- * Universal Serial Bus (USB) Device Controller (UDC) control registers
- *
- * Registers
- * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Control Register (read/write).
- * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Address Register (read/write).
- * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Output Maximum Packet size register
- * (read/write).
- * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Input Maximum Packet size register
- * (read/write).
- * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Control/Status register end-point 0
- * (read/write).
- * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Control/Status register end-point 1
- * (output, read/write).
- * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Control/Status register end-point 2
- * (input, read/write).
- * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Data register end-point 0
- * (read/write).
- * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Write Count register end-point 0
- * (read).
- * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Data Register (read/write).
- * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Status Register (read/write).
- */
-
-#define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */
-#define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */
-#define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */
-#define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */
-#define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */
-#define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */
-#define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */
-#define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */
-#define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */
-#define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */
-#define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */
-
-#define UDCCR_UDD 0x00000001 /* UDC Disable */
-#define UDCCR_UDA 0x00000002 /* UDC Active (read) */
-#define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */
-#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */
- /* (disable) */
-#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */
- /* (disable) */
-#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */
- /* (disable) */
-#define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */
- /* (disable) */
-#define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */
-#define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */
-
-#define UDCAR_ADD Fld (7, 0) /* function ADDress */
-
-#define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
- /* [byte] */
-#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \
- /* [1..256 byte] */ \
- (((Size) - 1) << FShft (UDCOMP_OUTMAXP))
-
-#define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
- /* [byte] */
-#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \
- /* [1..256 byte] */ \
- (((Size) - 1) << FShft (UDCIMP_INMAXP))
-
-#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */
-#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */
-#define UDCCS0_SST 0x00000004 /* Sent STall */
-#define UDCCS0_FST 0x00000008 /* Force STall */
-#define UDCCS0_DE 0x00000010 /* Data End */
-#define UDCCS0_SE 0x00000020 /* Setup End (read) */
-#define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */
- /* (write) */
-#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */
-
-#define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */
- /* Service request (read) */
-#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */
-#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */
-#define UDCCS1_SST 0x00000008 /* Sent STall */
-#define UDCCS1_FST 0x00000010 /* Force STall */
-#define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */
-
-#define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */
- /* Service request (read) */
-#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */
-#define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */
-#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */
-#define UDCCS2_SST 0x00000010 /* Sent STall */
-#define UDCCS2_FST 0x00000020 /* Force STall */
-
-#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
-
-#define UDCWC_WC Fld (4, 0) /* Write Count */
-
-#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
-
-#define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */
-#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */
-#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */
-#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */
-#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */
-#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */
-
-
-/*
- * Universal Asynchronous Receiver/Transmitter (UART) control registers
- *
- * Registers
- * Ser1UTCR0 Serial port 1 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 0
- * (read/write).
- * Ser1UTCR1 Serial port 1 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 1
- * (read/write).
- * Ser1UTCR2 Serial port 1 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 2
- * (read/write).
- * Ser1UTCR3 Serial port 1 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 3
- * (read/write).
- * Ser1UTDR Serial port 1 Universal Asynchronous
- * Receiver/Transmitter (UART) Data Register
- * (read/write).
- * Ser1UTSR0 Serial port 1 Universal Asynchronous
- * Receiver/Transmitter (UART) Status Register 0
- * (read/write).
- * Ser1UTSR1 Serial port 1 Universal Asynchronous
- * Receiver/Transmitter (UART) Status Register 1 (read).
- *
- * Ser2UTCR0 Serial port 2 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 0
- * (read/write).
- * Ser2UTCR1 Serial port 2 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 1
- * (read/write).
- * Ser2UTCR2 Serial port 2 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 2
- * (read/write).
- * Ser2UTCR3 Serial port 2 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 3
- * (read/write).
- * Ser2UTCR4 Serial port 2 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 4
- * (read/write).
- * Ser2UTDR Serial port 2 Universal Asynchronous
- * Receiver/Transmitter (UART) Data Register
- * (read/write).
- * Ser2UTSR0 Serial port 2 Universal Asynchronous
- * Receiver/Transmitter (UART) Status Register 0
- * (read/write).
- * Ser2UTSR1 Serial port 2 Universal Asynchronous
- * Receiver/Transmitter (UART) Status Register 1 (read).
- *
- * Ser3UTCR0 Serial port 3 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 0
- * (read/write).
- * Ser3UTCR1 Serial port 3 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 1
- * (read/write).
- * Ser3UTCR2 Serial port 3 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 2
- * (read/write).
- * Ser3UTCR3 Serial port 3 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 3
- * (read/write).
- * Ser3UTDR Serial port 3 Universal Asynchronous
- * Receiver/Transmitter (UART) Data Register
- * (read/write).
- * Ser3UTSR0 Serial port 3 Universal Asynchronous
- * Receiver/Transmitter (UART) Status Register 0
- * (read/write).
- * Ser3UTSR1 Serial port 3 Universal Asynchronous
- * Receiver/Transmitter (UART) Status Register 1 (read).
- *
- * Clocks
- * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
- * or 3.5795 MHz).
- * fua, Tua Frequency, period of the UART communication.
- */
-
-#define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */
-#define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */
-#define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */
-#define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */
-#define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */
-#define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */
-#define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */
-#define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */
-
-#define Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */
-#define Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */
-#define Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */
-#define Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */
-#define Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */
-#define Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */
-#define Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */
-
-#define Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */
-#define Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */
-#define Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */
-#define Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */
-#define Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */
-#define Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */
-#define Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */
-#define Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */
-
-#define Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */
-#define Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */
-#define Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */
-#define Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */
-#define Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */
-#define Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */
-#define Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */
-
-/* Those are still used in some places */
-#define _Ser1UTCR0 __PREG(Ser1UTCR0)
-#define _Ser2UTCR0 __PREG(Ser2UTCR0)
-#define _Ser3UTCR0 __PREG(Ser3UTCR0)
-
-/* Register offsets */
-#define UTCR0 0x00
-#define UTCR1 0x04
-#define UTCR2 0x08
-#define UTCR3 0x0c
-#define UTDR 0x14
-#define UTSR0 0x1c
-#define UTSR1 0x20
-
-#define UTCR0_PE 0x00000001 /* Parity Enable */
-#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */
-#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */
-#define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */
-#define UTCR0_SBS 0x00000004 /* Stop Bit Select */
-#define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */
-#define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */
-#define UTCR0_DSS 0x00000008 /* Data Size Select */
-#define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */
-#define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */
-#define UTCR0_SCE 0x00000010 /* Sample Clock Enable */
- /* (ser. port 1: GPIO [18], */
- /* ser. port 3: GPIO [20]) */
-#define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */
-#define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */
-#define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */
-#define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */
-#define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */
-#define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */
-#define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \
- (UTCR0_1StpBit + UTCR0_8BitData)
-
-#define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
-#define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
- /* fua = fxtl/(16*(BRD[11:0] + 1)) */
- /* Tua = 16*(BRD [11:0] + 1)*Txtl */
-#define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
- (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
- FShft (UTCR1_BRD))
-#define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
- (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
- FShft (UTCR2_BRD))
- /* fua = fxtl/(16*Floor (Div/16)) */
- /* Tua = 16*Floor (Div/16)*Txtl */
-#define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
- (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
- FShft (UTCR1_BRD))
-#define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
- (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
- FShft (UTCR2_BRD))
- /* fua = fxtl/(16*Ceil (Div/16)) */
- /* Tua = 16*Ceil (Div/16)*Txtl */
-
-#define UTCR3_RXE 0x00000001 /* Receive Enable */
-#define UTCR3_TXE 0x00000002 /* Transmit Enable */
-#define UTCR3_BRK 0x00000004 /* BReaK mode */
-#define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
- /* more Interrupt Enable */
-#define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
- /* Interrupt Enable */
-#define UTCR3_LBM 0x00000020 /* Look-Back Mode */
-#define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \
- /* TIE, LBM can be set or cleared) */ \
- (UTCR3_RXE + UTCR3_TXE)
-
-#define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */
- /* (HP-SIR) modulation Enable */
-#define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */
-#define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */
-#define UTCR4_LPM 0x00000002 /* Low-Power Mode */
-#define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */
-#define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */
-
-#define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
-#if 0 /* Hidden receive FIFO bits */
-#define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */
-#define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */
-#define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
-#endif /* 0 */
-
-#define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */
- /* Service request (read) */
-#define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */
- /* more Service request (read) */
-#define UTSR0_RID 0x00000004 /* Receiver IDle */
-#define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */
-#define UTSR0_REB 0x00000010 /* Receive End of Break */
-#define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */
-
-#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
-#define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */
-#define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
-#define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */
-#define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */
-#define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */
-
-
-/*
- * Synchronous Data Link Controller (SDLC) control registers
- *
- * Registers
- * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC)
- * Control Register 0 (read/write).
- * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC)
- * Control Register 1 (read/write).
- * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC)
- * Control Register 2 (read/write).
- * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC)
- * Control Register 3 (read/write).
- * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC)
- * Control Register 4 (read/write).
- * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC)
- * Data Register (read/write).
- * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC)
- * Status Register 0 (read/write).
- * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC)
- * Status Register 1 (read/write).
- *
- * Clocks
- * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
- * or 3.5795 MHz).
- * fsd, Tsd Frequency, period of the SDLC communication.
- */
-
-#define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */
-#define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */
-#define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */
-#define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */
-#define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */
-#define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */
-#define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */
-#define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */
-
-#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */
-#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */
-#define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */
-#define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */
-#define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */
-#define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */
-#define SDCR0_LBM 0x00000004 /* Look-Back Mode */
-#define SDCR0_BMS 0x00000008 /* Bit Modulation Select */
-#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */
-#define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */
-#define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */
-#define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */
- /* (GPIO [16]) */
-#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */
-#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */
-#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */
-#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */
-#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */
-#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */
-#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */
-#define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */
-
-#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */
- /* (GPIO [17]) */
-#define SDCR1_TXE 0x00000002 /* Transmit Enable */
-#define SDCR1_RXE 0x00000004 /* Receive Enable */
-#define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
- /* more Interrupt Enable */
-#define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
- /* Interrupt Enable */
-#define SDCR1_AME 0x00000020 /* Address Match Enable */
-#define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */
-#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */
-#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */
-#define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */
-
-#define SDCR2_AMV Fld (8, 0) /* Address Match Value */
-
-#define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
-#define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
- /* fsd = fxtl/(16*(BRD[11:0] + 1)) */
- /* Tsd = 16*(BRD[11:0] + 1)*Txtl */
-#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
- (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
- FShft (SDCR3_BRD))
-#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
- (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
- FShft (SDCR4_BRD))
- /* fsd = fxtl/(16*Floor (Div/16)) */
- /* Tsd = 16*Floor (Div/16)*Txtl */
-#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
- (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
- FShft (SDCR3_BRD))
-#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
- (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
- FShft (SDCR4_BRD))
- /* fsd = fxtl/(16*Ceil (Div/16)) */
- /* Tsd = 16*Ceil (Div/16)*Txtl */
-
-#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
-#if 0 /* Hidden receive FIFO bits */
-#define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
-#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */
-#define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
-#endif /* 0 */
-
-#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */
-#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
-#define SDSR0_RAB 0x00000004 /* Receive ABort */
-#define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
- /* Service request (read) */
-#define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */
- /* more Service request (read) */
-
-#define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
-#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */
-#define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
-#define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
-#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */
-#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
-#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */
-#define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */
-
-
-/*
- * High-Speed Serial to Parallel controller (HSSP) control registers
- *
- * Registers
- * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel
- * controller (HSSP) Control Register 0 (read/write).
- * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel
- * controller (HSSP) Control Register 1 (read/write).
- * Ser2HSDR Serial port 2 High-Speed Serial to Parallel
- * controller (HSSP) Data Register (read/write).
- * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel
- * controller (HSSP) Status Register 0 (read/write).
- * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel
- * controller (HSSP) Status Register 1 (read).
- * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel
- * controller (HSSP) Control Register 2 (read/write).
- * [The HSCR2 register is only implemented in
- * versions 2.0 (rev. = 8) and higher of the StrongARM
- * SA-1100.]
- */
-
-#define Ser2HSCR0 __REG(0x80040060) /* Ser. port 2 HSSP Control Reg. 0 */
-#define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */
-#define Ser2HSDR __REG(0x8004006C) /* Ser. port 2 HSSP Data Reg. */
-#define Ser2HSSR0 __REG(0x80040074) /* Ser. port 2 HSSP Status Reg. 0 */
-#define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */
-#define Ser2HSCR2 __REG(0x90060028) /* Ser. port 2 HSSP Control Reg. 2 */
-
-#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */
-#define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */
-#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */
-#define HSCR0_LBM 0x00000002 /* Look-Back Mode */
-#define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */
-#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */
-#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */
-#define HSCR0_TXE 0x00000008 /* Transmit Enable */
-#define HSCR0_RXE 0x00000010 /* Receive Enable */
-#define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */
- /* more Interrupt Enable */
-#define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */
- /* Interrupt Enable */
-#define HSCR0_AME 0x00000080 /* Address Match Enable */
-
-#define HSCR1_AMV Fld (8, 0) /* Address Match Value */
-
-#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
-#if 0 /* Hidden receive FIFO bits */
-#define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
-#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */
-#define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
-#endif /* 0 */
-
-#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */
-#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
-#define HSSR0_RAB 0x00000004 /* Receive ABort */
-#define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
- /* Service request (read) */
-#define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */
- /* more Service request (read) */
-#define HSSR0_FRE 0x00000020 /* receive FRaming Error */
-
-#define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
-#define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */
-#define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
-#define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
-#define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */
-#define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */
-#define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */
-
-#define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */
-#define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */
- /* (inverted) */
-#define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */
- /* (non-inverted) */
-#define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */
-#define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */
- /* (inverted) */
-#define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */
- /* (non-inverted) */
-
-
-/*
- * Multi-media Communications Port (MCP) control registers
- *
- * Registers
- * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP)
- * Control Register 0 (read/write).
- * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP)
- * Data Register 0 (audio, read/write).
- * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP)
- * Data Register 1 (telecom, read/write).
- * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP)
- * Data Register 2 (CODEC registers, read/write).
- * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP)
- * Status Register (read/write).
- * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP)
- * Control Register 1 (read/write).
- * [The MCCR1 register is only implemented in
- * versions 2.0 (rev. = 8) and higher of the StrongARM
- * SA-1100.]
- *
- * Clocks
- * fmc, Tmc Frequency, period of the MCP communication (10 MHz,
- * 12 MHz, or GPIO [21]).
- * faud, Taud Frequency, period of the audio sampling.
- * ftcm, Ttcm Frequency, period of the telecom sampling.
- */
-
-#define Ser4MCCR0 __REG(0x80060000) /* Ser. port 4 MCP Control Reg. 0 */
-#define Ser4MCDR0 __REG(0x80060008) /* Ser. port 4 MCP Data Reg. 0 (audio) */
-#define Ser4MCDR1 __REG(0x8006000C) /* Ser. port 4 MCP Data Reg. 1 (telecom) */
-#define Ser4MCDR2 __REG(0x80060010) /* Ser. port 4 MCP Data Reg. 2 (CODEC reg.) */
-#define Ser4MCSR __REG(0x80060018) /* Ser. port 4 MCP Status Reg. */
-#define Ser4MCCR1 __REG(0x90060030) /* Ser. port 4 MCP Control Reg. 1 */
-
-#define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */
- /* [6..127] */
- /* faud = fmc/(32*ASD) */
- /* Taud = 32*ASD*Tmc */
-#define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \
- /* [192..4064] */ \
- ((Div)/32 << FShft (MCCR0_ASD))
- /* faud = fmc/(32*Floor (Div/32)) */
- /* Taud = 32*Floor (Div/32)*Tmc */
-#define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \
- (((Div) + 31)/32 << FShft (MCCR0_ASD))
- /* faud = fmc/(32*Ceil (Div/32)) */
- /* Taud = 32*Ceil (Div/32)*Tmc */
-#define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */
- /* Divisor/32 [16..127] */
- /* ftcm = fmc/(32*TSD) */
- /* Ttcm = 32*TSD*Tmc */
-#define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \
- /* [512..4064] */ \
- ((Div)/32 << FShft (MCCR0_TSD))
- /* ftcm = fmc/(32*Floor (Div/32)) */
- /* Ttcm = 32*Floor (Div/32)*Tmc */
-#define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \
- (((Div) + 31)/32 << FShft (MCCR0_TSD))
- /* ftcm = fmc/(32*Ceil (Div/32)) */
- /* Ttcm = 32*Ceil (Div/32)*Tmc */
-#define MCCR0_MCE 0x00010000 /* MCP Enable */
-#define MCCR0_ECS 0x00020000 /* External Clock Select */
-#define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */
-#define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */
-#define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */
- /* sampling/storing Mode */
-#define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */
-#define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */
-#define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */
- /* or less interrupt Enable */
-#define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */
- /* or more interrupt Enable */
-#define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */
- /* or less interrupt Enable */
-#define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */
- /* more interrupt Enable */
-#define MCCR0_LBM 0x00800000 /* Look-Back Mode */
-#define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */
-#define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \
- (((Div) - 1) << FShft (MCCR0_ECP))
-
-#define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */
- /* FIFOs */
-
-#define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */
- /* FIFOs */
-
- /* receive/transmit CODEC reg. */
- /* FIFOs: */
-#define MCDR2_DATA Fld (16, 0) /* reg. DATA */
-#define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */
-#define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */
-#define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */
-#define MCDR2_ADD Fld (4, 17) /* reg. ADDress */
-
-#define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */
- /* or less Service request (read) */
-#define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */
- /* more Service request (read) */
-#define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */
- /* or less Service request (read) */
-#define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */
- /* or more Service request (read) */
-#define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */
-#define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */
-#define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */
-#define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */
-#define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */
- /* (read) */
-#define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */
- /* (read) */
-#define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */
- /* (read) */
-#define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */
- /* (read) */
-#define MCSR_CWC 0x00001000 /* CODEC register Write Completed */
- /* (read) */
-#define MCSR_CRC 0x00002000 /* CODEC register Read Completed */
- /* (read) */
-#define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */
-#define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */
-
-#define MCCR1_CFS 0x00100000 /* Clock Freq. Select */
-#define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */
- /* (11.981 MHz) */
-#define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */
- /* (9.585 MHz) */
-
-
-/*
- * Synchronous Serial Port (SSP) control registers
- *
- * Registers
- * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control
- * Register 0 (read/write).
- * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control
- * Register 1 (read/write).
- * [Bits SPO and SP are only implemented in versions 2.0
- * (rev. = 8) and higher of the StrongARM SA-1100.]
- * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data
- * Register (read/write).
- * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status
- * Register (read/write).
- *
- * Clocks
- * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
- * or 3.5795 MHz).
- * fss, Tss Frequency, period of the SSP communication.
- */
-
-#define Ser4SSCR0 __REG(0x80070060) /* Ser. port 4 SSP Control Reg. 0 */
-#define Ser4SSCR1 __REG(0x80070064) /* Ser. port 4 SSP Control Reg. 1 */
-#define Ser4SSDR __REG(0x8007006C) /* Ser. port 4 SSP Data Reg. */
-#define Ser4SSSR __REG(0x80070074) /* Ser. port 4 SSP Status Reg. */
-
-#define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */
-#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \
- (((Size) - 1) << FShft (SSCR0_DSS))
-#define SSCR0_FRF Fld (2, 4) /* FRame Format */
-#define SSCR0_Motorola /* Motorola Serial Peripheral */ \
- /* Interface (SPI) format */ \
- (0 << FShft (SSCR0_FRF))
-#define SSCR0_TI /* Texas Instruments Synchronous */ \
- /* Serial format */ \
- (1 << FShft (SSCR0_FRF))
-#define SSCR0_National /* National Microwire format */ \
- (2 << FShft (SSCR0_FRF))
-#define SSCR0_SSE 0x00000080 /* SSP Enable */
-#define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */
- /* fss = fxtl/(2*(SCR + 1)) */
- /* Tss = 2*(SCR + 1)*Txtl */
-#define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \
- (((Div) - 2)/2 << FShft (SSCR0_SCR))
- /* fss = fxtl/(2*Floor (Div/2)) */
- /* Tss = 2*Floor (Div/2)*Txtl */
-#define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \
- (((Div) - 1)/2 << FShft (SSCR0_SCR))
- /* fss = fxtl/(2*Ceil (Div/2)) */
- /* Tss = 2*Ceil (Div/2)*Txtl */
-
-#define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */
- /* Interrupt Enable */
-#define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */
- /* Interrupt Enable */
-#define SSCR1_LBM 0x00000004 /* Look-Back Mode */
-#define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */
-#define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */
-#define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */
-#define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */
-#define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */
- /* after frame (SFRM, 1st edge) */
-#define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */
- /* after frame (SFRM, 1st edge) */
-#define SSCR1_ECS 0x00000020 /* External Clock Select */
-#define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */
-#define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */
-
-#define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */
-
-#define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */
-#define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
-#define SSSR_BSY 0x00000008 /* SSP BuSY (read) */
-#define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */
- /* Service request (read) */
-#define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */
- /* Service request (read) */
-#define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */
-
-
-/*
- * Operating System (OS) timer control registers
- *
- * Registers
- * OSMR0 Operating System (OS) timer Match Register 0
- * (read/write).
- * OSMR1 Operating System (OS) timer Match Register 1
- * (read/write).
- * OSMR2 Operating System (OS) timer Match Register 2
- * (read/write).
- * OSMR3 Operating System (OS) timer Match Register 3
- * (read/write).
- * OSCR Operating System (OS) timer Counter Register
- * (read/write).
- * OSSR Operating System (OS) timer Status Register
- * (read/write).
- * OWER Operating System (OS) timer Watch-dog Enable Register
- * (read/write).
- * OIER Operating System (OS) timer Interrupt Enable Register
- * (read/write).
- */
-
-#define OSMR0 io_p2v(0x90000000) /* OS timer Match Reg. 0 */
-#define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */
-#define OSMR2 io_p2v(0x90000008) /* OS timer Match Reg. 2 */
-#define OSMR3 io_p2v(0x9000000c) /* OS timer Match Reg. 3 */
-#define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */
-#define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */
-#define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */
-#define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */
-
-#define OSSR_M(Nb) /* Match detected [0..3] */ \
- (0x00000001 << (Nb))
-#define OSSR_M0 OSSR_M (0) /* Match detected 0 */
-#define OSSR_M1 OSSR_M (1) /* Match detected 1 */
-#define OSSR_M2 OSSR_M (2) /* Match detected 2 */
-#define OSSR_M3 OSSR_M (3) /* Match detected 3 */
-
-#define OWER_WME 0x00000001 /* Watch-dog Match Enable */
- /* (set only) */
-
-#define OIER_E(Nb) /* match interrupt Enable [0..3] */ \
- (0x00000001 << (Nb))
-#define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */
-#define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */
-#define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */
-#define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */
-
-
-/*
- * Power Manager (PM) control registers
- *
- * Registers
- * PMCR Power Manager (PM) Control Register (read/write).
- * PSSR Power Manager (PM) Sleep Status Register (read/write).
- * PSPR Power Manager (PM) Scratch-Pad Register (read/write).
- * PWER Power Manager (PM) Wake-up Enable Register
- * (read/write).
- * PCFR Power Manager (PM) general ConFiguration Register
- * (read/write).
- * PPCR Power Manager (PM) Phase-Locked Loop (PLL)
- * Configuration Register (read/write).
- * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO)
- * Sleep state Register (read/write, see GPIO pins).
- * POSR Power Manager (PM) Oscillator Status Register (read).
- *
- * Clocks
- * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
- * or 3.5795 MHz).
- * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
- */
-
-#define PMCR __REG(0x90020000) /* PM Control Reg. */
-#define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */
-#define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */
-#define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */
-#define PCFR __REG(0x90020010) /* PM general ConFiguration Reg. */
-#define PPCR __REG(0x90020014) /* PM PLL Configuration Reg. */
-#define PGSR __REG(0x90020018) /* PM GPIO Sleep state Reg. */
-#define POSR __REG(0x9002001C) /* PM Oscillator Status Reg. */
-
-#define PMCR_SF 0x00000001 /* Sleep Force (set only) */
-
-#define PSSR_SS 0x00000001 /* Software Sleep */
-#define PSSR_BFS 0x00000002 /* Battery Fault Status */
- /* (BATT_FAULT) */
-#define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */
-#define PSSR_DH 0x00000008 /* DRAM control Hold */
-#define PSSR_PH 0x00000010 /* Peripheral control Hold */
-
-#define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */
-#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
-#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
-#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
-#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
-#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
-#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
-#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
-#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
-#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
-#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
-#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
-#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
-#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
-#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
-#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
-#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
-#define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */
-#define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */
-#define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */
-#define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */
-#define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */
-#define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */
-#define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */
-#define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */
-#define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */
-#define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */
-#define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */
-#define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */
-#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
-
-#define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */
-#define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */
-#define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */
-#define PCFR_FP 0x00000002 /* Float PCMCIA pins */
-#define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */
-#define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */
-#define PCFR_FS 0x00000004 /* Float Static memory pins */
-#define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */
-#define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */
-#define PCFR_FO 0x00000008 /* Force RTC oscillator */
- /* (32.768 kHz) enable On */
-
-#define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */
-#define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \
- (0x00 << FShft (PPCR_CCF))
-#define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \
- (0x01 << FShft (PPCR_CCF))
-#define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \
- (0x02 << FShft (PPCR_CCF))
-#define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \
- (0x03 << FShft (PPCR_CCF))
-#define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \
- (0x04 << FShft (PPCR_CCF))
-#define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \
- (0x05 << FShft (PPCR_CCF))
-#define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \
- (0x06 << FShft (PPCR_CCF))
-#define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \
- (0x07 << FShft (PPCR_CCF))
-#define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \
- (0x08 << FShft (PPCR_CCF))
-#define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \
- (0x09 << FShft (PPCR_CCF))
-#define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \
- (0x0A << FShft (PPCR_CCF))
-#define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \
- (0x0B << FShft (PPCR_CCF))
-#define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \
- (0x0C << FShft (PPCR_CCF))
-#define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \
- (0x0D << FShft (PPCR_CCF))
-#define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \
- (0x0E << FShft (PPCR_CCF))
-#define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \
- (0x0F << FShft (PPCR_CCF))
- /* 3.6864 MHz crystal (fxtl): */
-#define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */
-#define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */
-#define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */
-#define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */
-#define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */
-#define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */
-#define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */
-#define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */
-#define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */
-#define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */
-#define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */
-#define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */
-#define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */
-#define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */
-#define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */
-#define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */
- /* 3.5795 MHz crystal (fxtl): */
-#define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */
-#define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */
-#define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */
-#define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */
-#define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */
-#define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */
-#define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */
-#define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */
-#define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */
-#define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */
-#define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */
-#define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */
-#define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */
-#define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */
-#define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */
-#define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */
-
-#define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */
-
-
-/*
- * Reset Controller (RC) control registers
- *
- * Registers
- * RSRR Reset Controller (RC) Software Reset Register
- * (read/write).
- * RCSR Reset Controller (RC) Status Register (read/write).
- */
-
-#define RSRR __REG(0x90030000) /* RC Software Reset Reg. */
-#define RCSR __REG(0x90030004) /* RC Status Reg. */
-
-#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */
-
-#define RCSR_HWR 0x00000001 /* HardWare Reset */
-#define RCSR_SWR 0x00000002 /* SoftWare Reset */
-#define RCSR_WDR 0x00000004 /* Watch-Dog Reset */
-#define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */
-
-
-/*
- * Test unit control registers
- *
- * Registers
- * TUCR Test Unit Control Register (read/write).
- */
-
-#define TUCR __REG(0x90030008) /* Test Unit Control Reg. */
-
-#define TUCR_TIC 0x00000040 /* TIC mode */
-#define TUCR_TTST 0x00000080 /* Trim TeST mode */
-#define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */
- /* Check */
-#define TUCR_PMD 0x00000200 /* Power Management Disable */
-#define TUCR_MR 0x00000400 /* Memory Request mode */
-#define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */
-#define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */
- /* grant (MBGNT) on GPIO [22:21] */
-#define TUCR_CTB Fld (3, 20) /* Clock Test Bits */
-#define TUCR_FDC 0x00800000 /* RTC Force Delete Count */
-#define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */
-#define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */
-#define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */
-#define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */
-#define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \
- (0 << FShft (TUCR_TSEL))
-#define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \
- (1 << FShft (TUCR_TSEL))
-#define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \
- (2 << FShft (TUCR_TSEL))
-#define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \
- (3 << FShft (TUCR_TSEL))
-#define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \
- /* Clocks on GPIO [26:27] */ \
- (4 << FShft (TUCR_TSEL))
-#define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \
- /* (Alternative) */ \
- (5 << FShft (TUCR_TSEL))
-#define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \
- (6 << FShft (TUCR_TSEL))
-#define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \
- (7 << FShft (TUCR_TSEL))
-
-
-/*
- * General-Purpose Input/Output (GPIO) control registers
- *
- * Registers
- * GPLR General-Purpose Input/Output (GPIO) Pin Level
- * Register (read).
- * GPDR General-Purpose Input/Output (GPIO) Pin Direction
- * Register (read/write).
- * GPSR General-Purpose Input/Output (GPIO) Pin output Set
- * Register (write).
- * GPCR General-Purpose Input/Output (GPIO) Pin output Clear
- * Register (write).
- * GRER General-Purpose Input/Output (GPIO) Rising-Edge
- * detect Register (read/write).
- * GFER General-Purpose Input/Output (GPIO) Falling-Edge
- * detect Register (read/write).
- * GEDR General-Purpose Input/Output (GPIO) Edge Detect
- * status Register (read/write).
- * GAFR General-Purpose Input/Output (GPIO) Alternate
- * Function Register (read/write).
- *
- * Clock
- * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
- */
-
-#define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */
-#define GPDR __REG(0x90040004) /* GPIO Pin Direction Reg. */
-#define GPSR __REG(0x90040008) /* GPIO Pin output Set Reg. */
-#define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */
-#define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */
-#define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */
-#define GEDR __REG(0x90040018) /* GPIO Edge Detect status Reg. */
-#define GAFR __REG(0x9004001C) /* GPIO Alternate Function Reg. */
-
-#define GPIO_MIN (0)
-#define GPIO_MAX (27)
-
-#define GPIO_GPIO(Nb) /* GPIO [0..27] */ \
- (0x00000001 << (Nb))
-#define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */
-#define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */
-#define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */
-#define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */
-#define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */
-#define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */
-#define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */
-#define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */
-#define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */
-#define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */
-#define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */
-#define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */
-#define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */
-#define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */
-#define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */
-#define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */
-#define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */
-#define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */
-#define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */
-#define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */
-#define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */
-#define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */
-#define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */
-#define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */
-#define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */
-#define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */
-#define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */
-#define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */
-
-#define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \
- GPIO_GPIO ((Nb) - 6)
-#define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */
-#define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */
-#define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */
-#define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */
-#define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */
-#define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */
-#define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */
-#define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */
- /* ser. port 4: */
-#define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */
-#define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */
-#define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */
-#define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */
- /* ser. port 1: */
-#define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */
-#define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */
-#define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */
-#define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */
-#define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */
- /* ser. port 4: */
-#define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */
- /* ser. port 3: */
-#define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */
- /* ser. port 4: */
-#define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */
- /* test controller: */
-#define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */
-#define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */
-#define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */
-#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */
-#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */
-#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */
-#define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */
-#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */
-
-#define GPDR_In 0 /* Input */
-#define GPDR_Out 1 /* Output */
-
-
-/*
- * Interrupt Controller (IC) control registers
- *
- * Registers
- * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ)
- * Pending register (read).
- * ICMR Interrupt Controller (IC) Mask Register (read/write).
- * ICLR Interrupt Controller (IC) Level Register (read/write).
- * ICCR Interrupt Controller (IC) Control Register
- * (read/write).
- * [The ICCR register is only implemented in versions 2.0
- * (rev. = 8) and higher of the StrongARM SA-1100.]
- * ICFP Interrupt Controller (IC) Fast Interrupt reQuest
- * (FIQ) Pending register (read).
- * ICPR Interrupt Controller (IC) Pending Register (read).
- * [The ICPR register is active low (inverted) in
- * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
- * StrongARM SA-1100, it is active high (non-inverted) in
- * versions 2.0 (rev. = 8) and higher.]
- */
-
-#define ICIP __REG(0x90050000) /* IC IRQ Pending reg. */
-#define ICMR __REG(0x90050004) /* IC Mask Reg. */
-#define ICLR __REG(0x90050008) /* IC Level Reg. */
-#define ICCR __REG(0x9005000C) /* IC Control Reg. */
-#define ICFP __REG(0x90050010) /* IC FIQ Pending reg. */
-#define ICPR __REG(0x90050020) /* IC Pending Reg. */
-
-#define IC_GPIO(Nb) /* GPIO [0..10] */ \
- (0x00000001 << (Nb))
-#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */
-#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */
-#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */
-#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */
-#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */
-#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */
-#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */
-#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */
-#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */
-#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */
-#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */
-#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */
-#define IC_LCD 0x00001000 /* LCD controller */
-#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */
-#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */
-#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */
-#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */
-#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */
-#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */
-#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */
-#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \
- (0x00100000 << (Nb))
-#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */
-#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */
-#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */
-#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */
-#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */
-#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */
-#define IC_OST(Nb) /* OS Timer match [0..3] */ \
- (0x04000000 << (Nb))
-#define IC_OST0 IC_OST (0) /* OS Timer match 0 */
-#define IC_OST1 IC_OST (1) /* OS Timer match 1 */
-#define IC_OST2 IC_OST (2) /* OS Timer match 2 */
-#define IC_OST3 IC_OST (3) /* OS Timer match 3 */
-#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */
-#define IC_RTCAlrm 0x80000000 /* RTC Alarm */
-
-#define ICLR_IRQ 0 /* Interrupt ReQuest */
-#define ICLR_FIQ 1 /* Fast Interrupt reQuest */
-
-#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */
- /* Mask */
-#define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */
- /* (ICMR ignored) */
-#define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */
- /* enable (ICMR used) */
-
-
-/*
- * Peripheral Pin Controller (PPC) control registers
- *
- * Registers
- * PPDR Peripheral Pin Controller (PPC) Pin Direction
- * Register (read/write).
- * PPSR Peripheral Pin Controller (PPC) Pin State Register
- * (read/write).
- * PPAR Peripheral Pin Controller (PPC) Pin Assignment
- * Register (read/write).
- * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin
- * Direction Register (read/write).
- * PPFR Peripheral Pin Controller (PPC) Pin Flag Register
- * (read).
- */
-
-#define PPDR __REG(0x90060000) /* PPC Pin Direction Reg. */
-#define PPSR __REG(0x90060004) /* PPC Pin State Reg. */
-#define PPAR __REG(0x90060008) /* PPC Pin Assignment Reg. */
-#define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */
-#define PPFR __REG(0x90060010) /* PPC Pin Flag Reg. */
-
-#define PPC_LDD(Nb) /* LCD Data [0..7] */ \
- (0x00000001 << (Nb))
-#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */
-#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */
-#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */
-#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */
-#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */
-#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */
-#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */
-#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */
-#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */
-#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */
-#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */
-#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */
- /* ser. port 1: */
-#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */
-#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */
- /* ser. port 2: */
-#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */
-#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */
- /* ser. port 3: */
-#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */
-#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */
- /* ser. port 4: */
-#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */
-#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */
-#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */
-#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */
-
-#define PPDR_In 0 /* Input */
-#define PPDR_Out 1 /* Output */
-
- /* ser. port 1: */
-#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */
-#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */
-#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */
- /* ser. port 4: */
-#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */
-#define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */
- /* & SFRM_C */
-#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */
-
-#define PSDR_OutL 0 /* Output Low in sleep mode */
-#define PSDR_Flt 1 /* Floating (input) in sleep mode */
-
-#define PPFR_LCD 0x00000001 /* LCD controller */
-#define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */
-#define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */
-#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */
-#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */
-#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */
-#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */
-#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */
-#define PPFR_PerEn 0 /* Peripheral Enabled */
-#define PPFR_PPCEn 1 /* PPC Enabled */
-
-
-/*
- * Dynamic Random-Access Memory (DRAM) control registers
- *
- * Registers
- * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM)
- * CoNFiGuration register (read/write).
- * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM)
- * Column Address Strobe (CAS) shift register 0
- * (read/write).
- * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM)
- * Column Address Strobe (CAS) shift register 1
- * (read/write).
- * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM)
- * Column Address Strobe (CAS) shift register 2
- * (read/write).
- *
- * Clocks
- * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
- * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
- * fcas, Tcas Frequency, period of the DRAM CAS shift registers.
- */
-
-#define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */
-#define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */
-#define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */
-#define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */
-
-/* SA1100 MDCNFG values */
-#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \
- (0x00000001 << (Nb))
-#define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */
-#define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */
-#define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */
-#define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */
-#define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */
-#define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \
- (((Add) - 9) << FShft (MDCNFG_DRAC))
-#define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */
- /* (fcas = fcpu/2) */
-#define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */
-#define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \
- (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
-#define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \
- (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
-#define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */
-#define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \
- (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
-#define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \
- (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
-#define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */
-#define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \
- ((Tcpu) << FShft (MDCNFG_TDL))
-#define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */
- /* [Tmem] */
-#define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \
- /* [0..262136 Tcpu] */ \
- ((Tcpu)/8 << FShft (MDCNFG_DRI))
-
-/* SA1110 MDCNFG values */
-#define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */
-#define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */
-#define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */
-#define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */
-#define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */
- /* bank 0/1 */
-#define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */
-#define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */
-#define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/
- /* deassertion 0/1 */
-#define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */
-#define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */
-#define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */
-#define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */
-#define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */
-#define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */
- /* bank 0/1 */
-#define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */
-#define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */
-#define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/
- /* deassertion 0/1 */
-#define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */
-
-
-/*
- * Static memory control registers
- *
- * Registers
- * MSC0 Memory system: Static memory Control register 0
- * (read/write).
- * MSC1 Memory system: Static memory Control register 1
- * (read/write).
- *
- * Clocks
- * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
- * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
- */
-
-#define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */
-#define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */
-#define MSC2 __REG(0xa000002c) /* Static memory Control reg. 2, not contiguous */
-
-#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \
- Fld (16, ((Nb) Modulo 2)*16)
-#define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */
-#define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */
-#define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */
-#define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */
-
-#define MSC_RT Fld (2, 0) /* ROM/static memory Type */
-#define MSC_NonBrst /* Non-Burst static memory */ \
- (0 << FShft (MSC_RT))
-#define MSC_SRAM /* 32-bit byte-writable SRAM */ \
- (1 << FShft (MSC_RT))
-#define MSC_Brst4 /* Burst-of-4 static memory */ \
- (2 << FShft (MSC_RT))
-#define MSC_Brst8 /* Burst-of-8 static memory */ \
- (3 << FShft (MSC_RT))
-#define MSC_RBW 0x0004 /* ROM/static memory Bus Width */
-#define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */
-#define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */
-#define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */
- /* First access - 1(.5) [Tmem] */
-#define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \
- /* static memory) [3..65 Tcpu] */ \
- ((((Tcpu) - 3)/2) << FShft (MSC_RDF))
-#define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \
- ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
-#define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \
- /* static memory) [2..64 Tcpu] */ \
- ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
-#define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \
- ((((Tcpu) - 1)/2) << FShft (MSC_RDF))
-#define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */
- /* Next access - 1 [Tmem] */
-#define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \
- /* static memory) [2..64 Tcpu] */ \
- ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
-#define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \
- ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
-#define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \
- /* static memory) [2..64 Tcpu] */ \
- ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
-#define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \
- ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
-#define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */
- /* time/2 [Tmem] */
-#define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \
- (((Tcpu)/4) << FShft (MSC_RRR))
-#define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \
- ((((Tcpu) + 3)/4) << FShft (MSC_RRR))
-
-
-/*
- * Personal Computer Memory Card International Association (PCMCIA) control
- * register
- *
- * Register
- * MECR Memory system: Expansion memory bus (PCMCIA)
- * Configuration Register (read/write).
- *
- * Clocks
- * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
- * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
- * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK).
- */
-
- /* Memory system: */
-#define MECR __REG(0xA0000018) /* Expansion memory bus (PCMCIA) Configuration Reg. */
-
-#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \
- Fld (15, (Nb)*16)
-#define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */
-#define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */
-
-#define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */
-#define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \
- ((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
-#define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \
- ((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
-#define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */
- /* [Tmem] */
-#define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \
- ((((Tcpu) - 2)/2) << FShft (MECR_BSA))
-#define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \
- ((((Tcpu) - 1)/2) << FShft (MECR_BSA))
-#define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */
-#define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \
- ((((Tcpu) - 2)/2) << FShft (MECR_BSM))
-#define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \
- ((((Tcpu) - 1)/2) << FShft (MECR_BSM))
-
-/*
- * On SA1110 only
- */
-
-#define MDREFR __REG(0xA000001C)
-
-#define MDREFR_TRASR Fld (4, 0)
-#define MDREFR_DRI Fld (12, 4)
-#define MDREFR_E0PIN (1 << 16)
-#define MDREFR_K0RUN (1 << 17)
-#define MDREFR_K0DB2 (1 << 18)
-#define MDREFR_E1PIN (1 << 20)
-#define MDREFR_K1RUN (1 << 21)
-#define MDREFR_K1DB2 (1 << 22)
-#define MDREFR_K2RUN (1 << 25)
-#define MDREFR_K2DB2 (1 << 26)
-#define MDREFR_EAPD (1 << 28)
-#define MDREFR_KAPD (1 << 29)
-#define MDREFR_SLFRSH (1 << 31)
-
-
-/*
- * Direct Memory Access (DMA) control registers
- */
-#define DMA_SIZE (6 * 0x20)
-#define DMA_PHYS 0xb0000000
-
-
-/*
- * Liquid Crystal Display (LCD) control registers
- *
- * Registers
- * LCCR0 Liquid Crystal Display (LCD) Control Register 0
- * (read/write).
- * [Bits LDM, BAM, and ERM are only implemented in
- * versions 2.0 (rev. = 8) and higher of the StrongARM
- * SA-1100.]
- * LCSR Liquid Crystal Display (LCD) Status Register
- * (read/write).
- * [Bit LDD can be only read in versions 1.0 (rev. = 1)
- * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
- * read and written (cleared) in versions 2.0 (rev. = 8)
- * and higher.]
- * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access
- * (DMA) Base Address Register channel 1 (read/write).
- * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access
- * (DMA) Current Address Register channel 1 (read).
- * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access
- * (DMA) Base Address Register channel 2 (read/write).
- * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access
- * (DMA) Current Address Register channel 2 (read).
- * LCCR1 Liquid Crystal Display (LCD) Control Register 1
- * (read/write).
- * [The LCCR1 register can be only written in
- * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
- * StrongARM SA-1100, it can be written and read in
- * versions 2.0 (rev. = 8) and higher.]
- * LCCR2 Liquid Crystal Display (LCD) Control Register 2
- * (read/write).
- * [The LCCR1 register can be only written in
- * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
- * StrongARM SA-1100, it can be written and read in
- * versions 2.0 (rev. = 8) and higher.]
- * LCCR3 Liquid Crystal Display (LCD) Control Register 3
- * (read/write).
- * [The LCCR1 register can be only written in
- * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
- * StrongARM SA-1100, it can be written and read in
- * versions 2.0 (rev. = 8) and higher. Bit PCP is only
- * implemented in versions 2.0 (rev. = 8) and higher of
- * the StrongARM SA-1100.]
- *
- * Clocks
- * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
- * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
- * fpix, Tpix Frequency, period of the pixel clock.
- * fln, Tln Frequency, period of the line clock.
- * fac, Tac Frequency, period of the AC bias clock.
- */
-
-#define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */
-#define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \
- /* [byte] */ \
- (16*LCD_PEntrySp)
-#define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \
- /* [byte] */ \
- (256*LCD_PEntrySp)
-#define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \
- /* dummy-Palette Space [byte] */ \
- (16*LCD_PEntrySp)
-
-#define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */
-#define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */
-#define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */
-#define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */
-#define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */
-#define LCD_4Bit /* LCD 4-Bit pixel mode */ \
- (0 << FShft (LCD_PBS))
-#define LCD_8Bit /* LCD 8-Bit pixel mode */ \
- (1 << FShft (LCD_PBS))
-#define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \
- (2 << FShft (LCD_PBS))
-
-#define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */
-#define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */
-#define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */
-#define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */
-#define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */
-#define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */
-#define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */
-#define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */
-#define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */
-#define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */
-#define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */
-#define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */
-#define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */
-#define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */
-#define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */
-#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
- /* (Alternative) */
-
-#define LCCR0_LEN 0x00000001 /* LCD ENable */
-#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */
-#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
-#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
-#define LCCR0_SDS 0x00000004 /* Single/Dual panel display */
- /* Select */
-#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
-#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
-#define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */
- /* interrupt Mask (disable) */
-#define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */
- /* interrupt Mask (disable) */
-#define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */
- /* IUU, OOL, OUL, OOU, and OUU) */
- /* interrupt Mask (disable) */
-#define LCCR0_PAS 0x00000080 /* Passive/Active display Select */
-#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
-#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
-#define LCCR0_BLE 0x00000100 /* Big/Little Endian select */
-#define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */
-#define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */
-#define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */
- /* display mode) */
-#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
- /* display */
-#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
- /* display */
-#define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */
- /* [Tmem] */
-#define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \
- /* [0..510 Tcpu] */ \
- ((Tcpu)/2 << FShft (LCCR0_PDD))
-
-#define LCSR_LDD 0x00000001 /* LCD Disable Done */
-#define LCSR_BAU 0x00000002 /* Base Address Update (read) */
-#define LCSR_BER 0x00000004 /* Bus ERror */
-#define LCSR_ABC 0x00000008 /* AC Bias clock Count */
-#define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */
- /* panel */
-#define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */
- /* panel */
-#define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */
- /* panel */
-#define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */
- /* panel */
-#define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */
- /* panel */
-#define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */
- /* panel */
-#define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */
- /* panel */
-#define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */
- /* panel */
-
-#define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */
-#define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \
- (((Pixel) - 16)/16 << FShft (LCCR1_PPL))
-#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
- /* pulse Width - 1 [Tpix] (L_LCLK) */
-#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
- /* pulse Width [1..64 Tpix] */ \
- (((Tpix) - 1) << FShft (LCCR1_HSW))
-#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
- /* count - 1 [Tpix] */
-#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
- /* [1..256 Tpix] */ \
- (((Tpix) - 1) << FShft (LCCR1_ELW))
-#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
- /* Wait count - 1 [Tpix] */
-#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
- /* [1..256 Tpix] */ \
- (((Tpix) - 1) << FShft (LCCR1_BLW))
-
-#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
-#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
- (((Line) - 1) << FShft (LCCR2_LPP))
-#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
- /* Width - 1 [Tln] (L_FCLK) */
-#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
- /* Width [1..64 Tln] */ \
- (((Tln) - 1) << FShft (LCCR2_VSW))
-#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
- /* count [Tln] */
-#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
- /* [0..255 Tln] */ \
- ((Tln) << FShft (LCCR2_EFW))
-#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
- /* Wait count [Tln] */
-#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
- /* [0..255 Tln] */ \
- ((Tln) << FShft (LCCR2_BFW))
-
-#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
- /* [1..255] (L_PCLK) */
- /* fpix = fcpu/(2*(PCD + 2)) */
- /* Tpix = 2*(PCD + 2)*Tcpu */
-#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \
- (((Div) - 4)/2 << FShft (LCCR3_PCD))
- /* fpix = fcpu/(2*Floor (Div/2)) */
- /* Tpix = 2*Floor (Div/2)*Tcpu */
-#define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \
- (((Div) - 3)/2 << FShft (LCCR3_PCD))
- /* fpix = fcpu/(2*Ceil (Div/2)) */
- /* Tpix = 2*Ceil (Div/2)*Tcpu */
-#define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */
- /* [Tln] (L_BIAS) */
-#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \
- (((Div) - 2)/2 << FShft (LCCR3_ACB))
- /* fac = fln/(2*Floor (Div/2)) */
- /* Tac = 2*Floor (Div/2)*Tln */
-#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \
- (((Div) - 1)/2 << FShft (LCCR3_ACB))
- /* fac = fln/(2*Ceil (Div/2)) */
- /* Tac = 2*Ceil (Div/2)*Tln */
-#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */
- /* Interrupt */
-#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \
- /* Off */ \
- (0 << FShft (LCCR3_API))
-#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \
- /* [1..15] */ \
- ((Trans) << FShft (LCCR3_API))
-#define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */
- /* Polarity (L_FCLK) */
-#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
- /* active High */
-#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
- /* active Low */
-#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */
- /* pulse Polarity (L_LCLK) */
-#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
- /* pulse active High */
-#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
- /* pulse active Low */
-#define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */
-#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
-#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
-#define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */
- /* active display mode) */
-#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
-#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
diff --git a/arch/arm/mach-sa1100/include/mach/assabet.h b/arch/arm/mach-sa1100/include/mach/assabet.h
deleted file mode 100644
index 641a961653af..000000000000
--- a/arch/arm/mach-sa1100/include/mach/assabet.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/mach-sa1100/include/mach/assabet.h
- *
- * Created 2000/06/05 by Nicolas Pitre <nico@fluxnic.net>
- *
- * This file contains the hardware specific definitions for Assabet
- * Only include this file from SA1100-specific files.
- *
- * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
- * Definitions for Neponset added.
- */
-#ifndef __ASM_ARCH_ASSABET_H
-#define __ASM_ARCH_ASSABET_H
-
-
-/* System Configuration Register flags */
-
-#define ASSABET_SCR_SDRAM_LOW (1<<2) /* SDRAM size (low bit) */
-#define ASSABET_SCR_SDRAM_HIGH (1<<3) /* SDRAM size (high bit) */
-#define ASSABET_SCR_FLASH_LOW (1<<4) /* Flash size (low bit) */
-#define ASSABET_SCR_FLASH_HIGH (1<<5) /* Flash size (high bit) */
-#define ASSABET_SCR_GFX (1<<8) /* Graphics Accelerator (0 = present) */
-#define ASSABET_SCR_SA1111 (1<<9) /* Neponset (0 = present) */
-
-#define ASSABET_SCR_INIT -1
-
-extern unsigned long SCR_value;
-
-#ifdef CONFIG_ASSABET_NEPONSET
-#define machine_has_neponset() ((SCR_value & ASSABET_SCR_SA1111) == 0)
-#else
-#define machine_has_neponset() (0)
-#endif
-
-/* Board Control Register */
-
-#define ASSABET_BCR_BASE 0xf1000000
-#define ASSABET_BCR (*(volatile unsigned int *)(ASSABET_BCR_BASE))
-
-#define ASSABET_BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */
-#define ASSABET_BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */
-#define ASSABET_BCR_NGFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */
-#define ASSABET_BCR_NCODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */
-#define ASSABET_BCR_IRDA_FSEL (1<<3) /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */
-#define ASSABET_BCR_IRDA_MD0 (1<<4) /* Range/Power select */
-#define ASSABET_BCR_IRDA_MD1 (1<<5) /* Range/Power select */
-#define ASSABET_BCR_STEREO_LB (1<<6) /* Stereo Loopback */
-#define ASSABET_BCR_CF_BUS_OFF (1<<7) /* Compact Flash bus (0 = on, 1 = off (float)) */
-#define ASSABET_BCR_AUDIO_ON (1<<8) /* Audio power on */
-#define ASSABET_BCR_LIGHT_ON (1<<9) /* Backlight */
-#define ASSABET_BCR_LCD_12RGB (1<<10) /* 0 = 16RGB, 1 = 12RGB */
-#define ASSABET_BCR_LCD_ON (1<<11) /* LCD power on */
-#define ASSABET_BCR_RS232EN (1<<12) /* RS232 transceiver enable */
-#define ASSABET_BCR_LED_RED (1<<13) /* D9 (0 = on, 1 = off) */
-#define ASSABET_BCR_LED_GREEN (1<<14) /* D8 (0 = on, 1 = off) */
-#define ASSABET_BCR_VIB_ON (1<<15) /* Vibration motor (quiet alert) */
-#define ASSABET_BCR_COM_DTR (1<<16) /* COMport Data Terminal Ready */
-#define ASSABET_BCR_COM_RTS (1<<17) /* COMport Request To Send */
-#define ASSABET_BCR_RAD_WU (1<<18) /* Radio wake up interrupt */
-#define ASSABET_BCR_SMB_EN (1<<19) /* System management bus enable */
-#define ASSABET_BCR_TV_IR_DEC (1<<20) /* TV IR Decode Enable (not implemented) */
-#define ASSABET_BCR_QMUTE (1<<21) /* Quick Mute */
-#define ASSABET_BCR_RAD_ON (1<<22) /* Radio Power On */
-#define ASSABET_BCR_SPK_OFF (1<<23) /* 1 = Speaker amplifier power off */
-
-#ifdef CONFIG_SA1100_ASSABET
-extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set);
-#else
-#define ASSABET_BCR_frob(x,y) do { } while (0)
-#endif
-
-extern void assabet_uda1341_reset(int set);
-
-#define ASSABET_BCR_set(x) ASSABET_BCR_frob((x), (x))
-#define ASSABET_BCR_clear(x) ASSABET_BCR_frob((x), 0)
-
-#define ASSABET_BSR_BASE 0xf1000000
-#define ASSABET_BSR (*(volatile unsigned int*)(ASSABET_BSR_BASE))
-
-#define ASSABET_BSR_RS232_VALID (1 << 24)
-#define ASSABET_BSR_COM_DCD (1 << 25)
-#define ASSABET_BSR_COM_CTS (1 << 26)
-#define ASSABET_BSR_COM_DSR (1 << 27)
-#define ASSABET_BSR_RAD_CTS (1 << 28)
-#define ASSABET_BSR_RAD_DSR (1 << 29)
-#define ASSABET_BSR_RAD_DCD (1 << 30)
-#define ASSABET_BSR_RAD_RI (1 << 31)
-
-
-/* GPIOs (bitmasks) for which the generic definition doesn't say much */
-#define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */
-#define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */
-#define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */
-#define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */
-#define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */
-#define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */
-
-#endif
diff --git a/arch/arm/mach-sa1100/include/mach/bitfield.h b/arch/arm/mach-sa1100/include/mach/bitfield.h
deleted file mode 100644
index f1f0e3387d9c..000000000000
--- a/arch/arm/mach-sa1100/include/mach/bitfield.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FILE bitfield.h
- *
- * Version 1.1
- * Author Copyright (c) Marc A. Viredaz, 1998
- * DEC Western Research Laboratory, Palo Alto, CA
- * Date April 1998 (April 1997)
- * System Advanced RISC Machine (ARM)
- * Language C or ARM Assembly
- * Purpose Definition of macros to operate on bit fields.
- */
-
-
-
-#ifndef __BITFIELD_H
-#define __BITFIELD_H
-
-#ifndef __ASSEMBLY__
-#define UData(Data) ((unsigned long) (Data))
-#else
-#define UData(Data) (Data)
-#endif
-
-
-/*
- * MACRO: Fld
- *
- * Purpose
- * The macro "Fld" encodes a bit field, given its size and its shift value
- * with respect to bit 0.
- *
- * Note
- * A more intuitive way to encode bit fields would have been to use their
- * mask. However, extracting size and shift value information from a bit
- * field's mask is cumbersome and might break the assembler (255-character
- * line-size limit).
- *
- * Input
- * Size Size of the bit field, in number of bits.
- * Shft Shift value of the bit field with respect to bit 0.
- *
- * Output
- * Fld Encoded bit field.
- */
-
-#define Fld(Size, Shft) (((Size) << 16) + (Shft))
-
-
-/*
- * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
- *
- * Purpose
- * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
- * the size, shift value, mask, aligned mask, and first bit of a
- * bit field.
- *
- * Input
- * Field Encoded bit field (using the macro "Fld").
- *
- * Output
- * FSize Size of the bit field, in number of bits.
- * FShft Shift value of the bit field with respect to bit 0.
- * FMsk Mask for the bit field.
- * FAlnMsk Mask for the bit field, aligned on bit 0.
- * F1stBit First bit of the bit field.
- */
-
-#define FSize(Field) ((Field) >> 16)
-#define FShft(Field) ((Field) & 0x0000FFFF)
-#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
-#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
-#define F1stBit(Field) (UData (1) << FShft (Field))
-
-
-/*
- * MACRO: FInsrt
- *
- * Purpose
- * The macro "FInsrt" inserts a value into a bit field by shifting the
- * former appropriately.
- *
- * Input
- * Value Bit-field value.
- * Field Encoded bit field (using the macro "Fld").
- *
- * Output
- * FInsrt Bit-field value positioned appropriately.
- */
-
-#define FInsrt(Value, Field) \
- (UData (Value) << FShft (Field))
-
-
-/*
- * MACRO: FExtr
- *
- * Purpose
- * The macro "FExtr" extracts the value of a bit field by masking and
- * shifting it appropriately.
- *
- * Input
- * Data Data containing the bit-field to be extracted.
- * Field Encoded bit field (using the macro "Fld").
- *
- * Output
- * FExtr Bit-field value.
- */
-
-#define FExtr(Data, Field) \
- ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
-
-
-#endif /* __BITFIELD_H */
diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h
deleted file mode 100644
index c95273c9567b..000000000000
--- a/arch/arm/mach-sa1100/include/mach/collie.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/mach-sa1100/include/mach/collie.h
- *
- * This file contains the hardware specific definitions for Collie
- * Only include this file from SA1100-specific files.
- *
- * ChangeLog:
- * 04-06-2001 Lineo Japan, Inc.
- * 04-16-2001 SHARP Corporation
- * 07-07-2002 Chris Larson <clarson@digi.com>
- *
- */
-#ifndef __ASM_ARCH_COLLIE_H
-#define __ASM_ARCH_COLLIE_H
-
-#include "hardware.h" /* Gives GPIO_MAX */
-
-#define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1)
-#define COLLIE_GPIO_CHARGE_ON (COLLIE_SCOOP_GPIO_BASE + 0)
-#define COLLIE_SCP_DIAG_BOOT1 SCOOP_GPCR_PA12
-#define COLLIE_SCP_DIAG_BOOT2 SCOOP_GPCR_PA13
-#define COLLIE_SCP_MUTE_L SCOOP_GPCR_PA14
-#define COLLIE_SCP_MUTE_R SCOOP_GPCR_PA15
-#define COLLIE_SCP_5VON SCOOP_GPCR_PA16
-#define COLLIE_SCP_AMP_ON SCOOP_GPCR_PA17
-#define COLLIE_GPIO_VPEN (COLLIE_SCOOP_GPIO_BASE + 7)
-#define COLLIE_SCP_LB_VOL_CHG SCOOP_GPCR_PA19
-
-#define COLLIE_SCOOP_IO_DIR (COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \
- COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | \
- COLLIE_SCP_LB_VOL_CHG)
-#define COLLIE_SCOOP_IO_OUT (COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R)
-
-/* GPIOs for gpiolib */
-
-#define COLLIE_GPIO_ON_KEY (0)
-#define COLLIE_GPIO_AC_IN (1)
-#define COLLIE_GPIO_SDIO_INT (11)
-#define COLLIE_GPIO_CF_IRQ (14)
-#define COLLIE_GPIO_nREMOCON_INT (15)
-#define COLLIE_GPIO_UCB1x00_RESET (16)
-#define COLLIE_GPIO_nMIC_ON (17)
-#define COLLIE_GPIO_nREMOCON_ON (18)
-#define COLLIE_GPIO_CO (20)
-#define COLLIE_GPIO_MCP_CLK (21)
-#define COLLIE_GPIO_CF_CD (22)
-#define COLLIE_GPIO_UCB1x00_IRQ (23)
-#define COLLIE_GPIO_WAKEUP (24)
-#define COLLIE_GPIO_GA_INT (25)
-#define COLLIE_GPIO_MAIN_BAT_LOW (26)
-
-/* GPIO definitions for direct register access */
-
-#define _COLLIE_GPIO_ON_KEY GPIO_GPIO(0)
-#define _COLLIE_GPIO_AC_IN GPIO_GPIO(1)
-#define _COLLIE_GPIO_nREMOCON_INT GPIO_GPIO(15)
-#define _COLLIE_GPIO_UCB1x00_RESET GPIO_GPIO(16)
-#define _COLLIE_GPIO_nMIC_ON GPIO_GPIO(17)
-#define _COLLIE_GPIO_nREMOCON_ON GPIO_GPIO(18)
-#define _COLLIE_GPIO_CO GPIO_GPIO(20)
-#define _COLLIE_GPIO_WAKEUP GPIO_GPIO(24)
-/* Interrupts */
-
-#define COLLIE_IRQ_GPIO_ON_KEY IRQ_GPIO0
-#define COLLIE_IRQ_GPIO_AC_IN IRQ_GPIO1
-#define COLLIE_IRQ_GPIO_SDIO_IRQ IRQ_GPIO11
-#define COLLIE_IRQ_GPIO_CF_IRQ IRQ_GPIO14
-#define COLLIE_IRQ_GPIO_nREMOCON_INT IRQ_GPIO15
-#define COLLIE_IRQ_GPIO_CO IRQ_GPIO20
-#define COLLIE_IRQ_GPIO_CF_CD IRQ_GPIO22
-#define COLLIE_IRQ_GPIO_UCB1x00_IRQ IRQ_GPIO23
-#define COLLIE_IRQ_GPIO_WAKEUP IRQ_GPIO24
-#define COLLIE_IRQ_GPIO_GA_INT IRQ_GPIO25
-#define COLLIE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO26
-
-/* GPIO's on the TC35143AF (Toshiba Analog Frontend) */
-#define COLLIE_TC35143_GPIO_BASE (GPIO_MAX + 13)
-#define COLLIE_TC35143_GPIO_VERSION0 UCB_IO_0
-#define COLLIE_TC35143_GPIO_TBL_CHK UCB_IO_1
-#define COLLIE_TC35143_GPIO_VPEN_ON UCB_IO_2
-#define COLLIE_GPIO_IR_ON (COLLIE_TC35143_GPIO_BASE + 3)
-#define COLLIE_TC35143_GPIO_AMP_ON UCB_IO_4
-#define COLLIE_TC35143_GPIO_VERSION1 UCB_IO_5
-#define COLLIE_TC35143_GPIO_FS8KLPF UCB_IO_5
-#define COLLIE_TC35143_GPIO_BUZZER_BIAS UCB_IO_6
-#define COLLIE_GPIO_MBAT_ON (COLLIE_TC35143_GPIO_BASE + 7)
-#define COLLIE_GPIO_BBAT_ON (COLLIE_TC35143_GPIO_BASE + 8)
-#define COLLIE_GPIO_TMP_ON (COLLIE_TC35143_GPIO_BASE + 9)
-#define COLLIE_TC35143_GPIO_IN (UCB_IO_0 | UCB_IO_2 | UCB_IO_5)
-#define COLLIE_TC35143_GPIO_OUT (UCB_IO_1 | UCB_IO_3 | UCB_IO_4 \
- | UCB_IO_6)
-
-#endif
diff --git a/arch/arm/mach-sa1100/include/mach/generic.h b/arch/arm/mach-sa1100/include/mach/generic.h
deleted file mode 100644
index 665542e0c9e2..000000000000
--- a/arch/arm/mach-sa1100/include/mach/generic.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../generic.h"
diff --git a/arch/arm/mach-sa1100/include/mach/h3xxx.h b/arch/arm/mach-sa1100/include/mach/h3xxx.h
deleted file mode 100644
index 0ee2578e0006..000000000000
--- a/arch/arm/mach-sa1100/include/mach/h3xxx.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Definitions for Compaq iPAQ H3100 and H3600 handheld computers
- *
- * (c) 2000 Compaq Computer Corporation. (Author: Jamey Hicks)
- * (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru>
- */
-
-#ifndef _INCLUDE_H3XXX_H_
-#define _INCLUDE_H3XXX_H_
-
-#include "hardware.h" /* Gives GPIO_MAX */
-
-/* Physical memory regions corresponding to chip selects */
-#define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000)
-#define H3600_BANK_2_PHYS SA1100_CS2_PHYS
-#define H3600_BANK_4_PHYS SA1100_CS4_PHYS
-
-/* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */
-#define H3600_EGPIO_VIRT 0xf0000000
-#define H3600_BANK_2_VIRT 0xf1000000
-#define H3600_BANK_4_VIRT 0xf3800000
-
-/*
- * gpiolib numbers for all iPAQs
- */
-#define H3XXX_GPIO_PWR_BUTTON 0
-#define H3XXX_GPIO_PCMCIA_CD1 10
-#define H3XXX_GPIO_PCMCIA_IRQ1 11
-#define H3XXX_GPIO_PCMCIA_CD0 17
-#define H3XXX_GPIO_ACTION_BUTTON 18
-#define H3XXX_GPIO_SYS_CLK 19
-#define H3XXX_GPIO_PCMCIA_IRQ0 21
-#define H3XXX_GPIO_COM_DCD 23
-#define H3XXX_GPIO_OPTION 24
-#define H3XXX_GPIO_COM_CTS 25
-#define H3XXX_GPIO_COM_RTS 26
-
-/* machine-specific gpios */
-
-#define H3100_GPIO_BT_ON 2
-#define H3100_GPIO_QMUTE 4
-#define H3100_GPIO_LCD_3V_ON 5
-#define H3100_GPIO_AUD_ON 6
-#define H3100_GPIO_AUD_PWR_ON 7
-#define H3100_GPIO_IR_ON 8
-#define H3100_GPIO_IR_FSEL 9
-
-#define H3600_GPIO_CLK_SET0 12 /* audio sample rate clock generator */
-#define H3600_GPIO_CLK_SET1 13
-#define H3600_GPIO_SOFT_RESET 20 /* also known as BATT_FAULT */
-#define H3600_GPIO_OPT_LOCK 22
-#define H3600_GPIO_OPT_DET 27
-
-
-/* H3100 / 3600 EGPIO pins */
-#define H3XXX_EGPIO_BASE (GPIO_MAX + 1)
-
-#define H3XXX_EGPIO_VPP_ON (H3XXX_EGPIO_BASE + 0)
-#define H3XXX_EGPIO_CARD_RESET (H3XXX_EGPIO_BASE + 1) /* reset the attached pcmcia/compactflash card. active high. */
-#define H3XXX_EGPIO_OPT_RESET (H3XXX_EGPIO_BASE + 2) /* reset the attached option pack. active high. */
-#define H3XXX_EGPIO_CODEC_NRESET (H3XXX_EGPIO_BASE + 3) /* reset the onboard UDA1341. active low. */
-#define H3XXX_EGPIO_OPT_NVRAM_ON (H3XXX_EGPIO_BASE + 4) /* apply power to optionpack nvram, active high. */
-#define H3XXX_EGPIO_OPT_ON (H3XXX_EGPIO_BASE + 5) /* full power to option pack. active high. */
-#define H3XXX_EGPIO_LCD_ON (H3XXX_EGPIO_BASE + 6) /* enable 3.3V to LCD. active high. */
-#define H3XXX_EGPIO_RS232_ON (H3XXX_EGPIO_BASE + 7) /* UART3 transceiver force on. Active high. */
-
-/* H3600 only EGPIO pins */
-#define H3600_EGPIO_LCD_PCI (H3XXX_EGPIO_BASE + 8) /* LCD control IC enable. active high. */
-#define H3600_EGPIO_IR_ON (H3XXX_EGPIO_BASE + 9) /* apply power to IR module. active high. */
-#define H3600_EGPIO_AUD_AMP_ON (H3XXX_EGPIO_BASE + 10) /* apply power to audio power amp. active high. */
-#define H3600_EGPIO_AUD_PWR_ON (H3XXX_EGPIO_BASE + 11) /* apply power to reset of audio circuit. active high. */
-#define H3600_EGPIO_QMUTE (H3XXX_EGPIO_BASE + 12) /* mute control for onboard UDA1341. active high. */
-#define H3600_EGPIO_IR_FSEL (H3XXX_EGPIO_BASE + 13) /* IR speed select: 1->fast, 0->slow */
-#define H3600_EGPIO_LCD_5V_ON (H3XXX_EGPIO_BASE + 14) /* enable 5V to LCD. active high. */
-#define H3600_EGPIO_LVDD_ON (H3XXX_EGPIO_BASE + 15) /* enable 9V and -6.5V to LCD. */
-
-void __init h3xxx_map_io(void);
-void __init h3xxx_mach_init(void);
-
-#endif /* _INCLUDE_H3XXX_H_ */
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
deleted file mode 100644
index 6f2dbdc28663..000000000000
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/mach-sa1100/include/mach/hardware.h
- *
- * Copyright (C) 1998 Nicolas Pitre <nico@fluxnic.net>
- *
- * This file contains the hardware definitions for SA1100 architecture
- *
- * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
- * Definitions for SA1111 added.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-
-#define UNCACHEABLE_ADDR 0xfa050000 /* ICIP */
-
-
-/*
- * SA1100 internal I/O mappings
- *
- * We have the following mapping:
- * phys virt
- * 80000000 f8000000
- * 90000000 fa000000
- * a0000000 fc000000
- * b0000000 fe000000
- */
-
-#define VIO_BASE 0xf8000000 /* virtual start of IO space */
-#define VIO_SHIFT 3 /* x = IO space shrink power */
-#define PIO_START 0x80000000 /* physical start of IO space */
-
-#define io_p2v( x ) \
- IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
-#define io_v2p( x ) \
- ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
-
-#define __MREG(x) IOMEM(io_p2v(x))
-
-#ifndef __ASSEMBLY__
-
-# define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x)))
-# define __PREG(x) (io_v2p((unsigned long)&(x)))
-
-#else
-
-# define __REG(x) io_p2v(x)
-# define __PREG(x) io_v2p(x)
-
-#endif
-
-#include "SA-1100.h"
-
-#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h
deleted file mode 100644
index f4a41e665262..000000000000
--- a/arch/arm/mach-sa1100/include/mach/irqs.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/mach-sa1100/include/mach/irqs.h
- *
- * Copyright (C) 1996 Russell King
- * Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus).
- * Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation)
- *
- * 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs.
- */
-
-#define IRQ_GPIO0_SC 1
-#define IRQ_GPIO1_SC 2
-#define IRQ_GPIO2_SC 3
-#define IRQ_GPIO3_SC 4
-#define IRQ_GPIO4_SC 5
-#define IRQ_GPIO5_SC 6
-#define IRQ_GPIO6_SC 7
-#define IRQ_GPIO7_SC 8
-#define IRQ_GPIO8_SC 9
-#define IRQ_GPIO9_SC 10
-#define IRQ_GPIO10_SC 11
-#define IRQ_GPIO11_27 12
-#define IRQ_LCD 13 /* LCD controller */
-#define IRQ_Ser0UDC 14 /* Ser. port 0 UDC */
-#define IRQ_Ser1SDLC 15 /* Ser. port 1 SDLC */
-#define IRQ_Ser1UART 16 /* Ser. port 1 UART */
-#define IRQ_Ser2ICP 17 /* Ser. port 2 ICP */
-#define IRQ_Ser3UART 18 /* Ser. port 3 UART */
-#define IRQ_Ser4MCP 19 /* Ser. port 4 MCP */
-#define IRQ_Ser4SSP 20 /* Ser. port 4 SSP */
-#define IRQ_DMA0 21 /* DMA controller channel 0 */
-#define IRQ_DMA1 22 /* DMA controller channel 1 */
-#define IRQ_DMA2 23 /* DMA controller channel 2 */
-#define IRQ_DMA3 24 /* DMA controller channel 3 */
-#define IRQ_DMA4 25 /* DMA controller channel 4 */
-#define IRQ_DMA5 26 /* DMA controller channel 5 */
-#define IRQ_OST0 27 /* OS Timer match 0 */
-#define IRQ_OST1 28 /* OS Timer match 1 */
-#define IRQ_OST2 29 /* OS Timer match 2 */
-#define IRQ_OST3 30 /* OS Timer match 3 */
-#define IRQ_RTC1Hz 31 /* RTC 1 Hz clock */
-#define IRQ_RTCAlrm 32 /* RTC Alarm */
-
-#define IRQ_GPIO0 33
-#define IRQ_GPIO1 34
-#define IRQ_GPIO2 35
-#define IRQ_GPIO3 36
-#define IRQ_GPIO4 37
-#define IRQ_GPIO5 38
-#define IRQ_GPIO6 39
-#define IRQ_GPIO7 40
-#define IRQ_GPIO8 41
-#define IRQ_GPIO9 42
-#define IRQ_GPIO10 43
-#define IRQ_GPIO11 44
-#define IRQ_GPIO12 45
-#define IRQ_GPIO13 46
-#define IRQ_GPIO14 47
-#define IRQ_GPIO15 48
-#define IRQ_GPIO16 49
-#define IRQ_GPIO17 50
-#define IRQ_GPIO18 51
-#define IRQ_GPIO19 52
-#define IRQ_GPIO20 53
-#define IRQ_GPIO21 54
-#define IRQ_GPIO22 55
-#define IRQ_GPIO23 56
-#define IRQ_GPIO24 57
-#define IRQ_GPIO25 58
-#define IRQ_GPIO26 59
-#define IRQ_GPIO27 60
-
-/*
- * The next 16 interrupts are for board specific purposes. Since
- * the kernel can only run on one machine at a time, we can re-use
- * these. If you need more, increase IRQ_BOARD_END, but keep it
- * within sensible limits. IRQs 61 to 76 are available.
- */
-#define IRQ_BOARD_START 61
-#define IRQ_BOARD_END 77
-
-/*
- * Figure out the MAX IRQ number.
- *
- * Neponset, SA1111 and UCB1x00 are sparse IRQ aware, so can dynamically
- * allocate their IRQs above NR_IRQS.
- *
- * LoCoMo has 4 additional IRQs, but is not sparse IRQ aware, and so has
- * to be included in the NR_IRQS calculation.
- */
-#ifdef CONFIG_SHARP_LOCOMO
-#define NR_IRQS_LOCOMO 4
-#else
-#define NR_IRQS_LOCOMO 0
-#endif
-
-#ifndef NR_IRQS
-#define NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO)
-#endif
-#define SA1100_NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO)
diff --git a/arch/arm/mach-sa1100/include/mach/jornada720.h b/arch/arm/mach-sa1100/include/mach/jornada720.h
deleted file mode 100644
index bb22fcab8c6c..000000000000
--- a/arch/arm/mach-sa1100/include/mach/jornada720.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-sa1100/include/mach/jornada720.h
- *
- * SSP/MCU communication definitions for HP Jornada 710/720/728
- *
- * Copyright 2007,2008 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
- * Copyright 2000 John Ankcorn <jca@lcs.mit.edu>
- */
-
- /* HP Jornada 7xx microprocessor commands */
-#define GETBATTERYDATA 0xc0
-#define GETSCANKEYCODE 0x90
-#define GETTOUCHSAMPLES 0xa0
-#define GETCONTRAST 0xD0
-#define SETCONTRAST 0xD1
-#define GETBRIGHTNESS 0xD2
-#define SETBRIGHTNESS 0xD3
-#define CONTRASTOFF 0xD8
-#define BRIGHTNESSOFF 0xD9
-#define PWMOFF 0xDF
-#define TXDUMMY 0x11
-#define ERRORCODE 0x00
-
-extern void jornada_ssp_start(void);
-extern void jornada_ssp_end(void);
-extern int jornada_ssp_inout(u8 byte);
-extern int jornada_ssp_byte(u8 byte);
diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h
deleted file mode 100644
index 3b19296f5062..000000000000
--- a/arch/arm/mach-sa1100/include/mach/memory.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/mach-sa1100/include/mach/memory.h
- *
- * Copyright (C) 1999-2000 Nicolas Pitre <nico@fluxnic.net>
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#include <linux/sizes.h>
-
-/*
- * Because of the wide memory address space between physical RAM banks on the
- * SA1100, it's much convenient to use Linux's SparseMEM support to implement
- * our memory map representation. Assuming all memory nodes have equal access
- * characteristics, we then have generic discontiguous memory support.
- *
- * The sparsemem banks are matched with the physical memory bank addresses
- * which are incidentally the same as virtual addresses.
- *
- * node 0: 0xc0000000 - 0xc7ffffff
- * node 1: 0xc8000000 - 0xcfffffff
- * node 2: 0xd0000000 - 0xd7ffffff
- * node 3: 0xd8000000 - 0xdfffffff
- */
-#define MAX_PHYSMEM_BITS 32
-#define SECTION_SIZE_BITS 27
-
-/*
- * Cache flushing area - SA1100 zero bank
- */
-#define FLUSH_BASE_PHYS 0xe0000000
-#define FLUSH_BASE 0xf5000000
-#define FLUSH_BASE_MINICACHE 0xf5100000
-
-#endif
diff --git a/arch/arm/mach-sa1100/include/mach/mtd-xip.h b/arch/arm/mach-sa1100/include/mach/mtd-xip.h
deleted file mode 100644
index 85e6a79112d2..000000000000
--- a/arch/arm/mach-sa1100/include/mach/mtd-xip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * MTD primitives for XIP support. Architecture specific functions
- *
- * Do not include this file directly. It's included from linux/mtd/xip.h
- *
- * Author: Nicolas Pitre
- * Created: Nov 2, 2004
- * Copyright: (C) 2004 MontaVista Software, Inc.
- */
-
-#ifndef __ARCH_SA1100_MTD_XIP_H__
-#define __ARCH_SA1100_MTD_XIP_H__
-
-#include <mach/hardware.h>
-
-#define xip_irqpending() (ICIP & ICMR)
-
-/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
-#define xip_currtime() readl_relaxed(OSCR)
-#define xip_elapsed_since(x) (signed)((readl_relaxed(OSCR) - (x)) / 4)
-
-#endif /* __ARCH_SA1100_MTD_XIP_H__ */
diff --git a/arch/arm/mach-sa1100/include/mach/neponset.h b/arch/arm/mach-sa1100/include/mach/neponset.h
deleted file mode 100644
index 18411cfdfe8e..000000000000
--- a/arch/arm/mach-sa1100/include/mach/neponset.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/mach-sa1100/include/mach/neponset.h
- *
- * Created 2000/06/05 by Nicolas Pitre <nico@fluxnic.net>
- *
- * This file contains the hardware specific definitions for Assabet
- * Only include this file from SA1100-specific files.
- *
- * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
- * Definitions for Neponset added.
- */
-#ifndef __ASM_ARCH_NEPONSET_H
-#define __ASM_ARCH_NEPONSET_H
-
-/*
- * Neponset definitions:
- */
-#define NCR_GP01_OFF (1<<0)
-#define NCR_TP_PWR_EN (1<<1)
-#define NCR_MS_PWR_EN (1<<2)
-#define NCR_ENET_OSC_EN (1<<3)
-#define NCR_SPI_KB_WK_UP (1<<4)
-#define NCR_A0VPP (1<<5)
-#define NCR_A1VPP (1<<6)
-
-void neponset_ncr_frob(unsigned int, unsigned int);
-#define neponset_ncr_set(v) neponset_ncr_frob(0, v)
-#define neponset_ncr_clear(v) neponset_ncr_frob(v, 0)
-
-#endif
diff --git a/arch/arm/mach-sa1100/include/mach/reset.h b/arch/arm/mach-sa1100/include/mach/reset.h
deleted file mode 100644
index a6723d45ae2a..000000000000
--- a/arch/arm/mach-sa1100/include/mach/reset.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_ARCH_RESET_H
-#define __ASM_ARCH_RESET_H
-
-#include "hardware.h"
-
-#define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */
-#define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */
-#define RESET_STATUS_LOWPOWER (1 << 2) /* Exit from Low Power/Sleep */
-#define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */
-#define RESET_STATUS_ALL (0xf)
-
-static inline void clear_reset_status(unsigned int mask)
-{
- RCSR = mask;
-}
-
-#endif /* __ASM_ARCH_RESET_H */
diff --git a/arch/arm/mach-sa1100/include/mach/uncompress.h b/arch/arm/mach-sa1100/include/mach/uncompress.h
deleted file mode 100644
index f5eaa90a4576..000000000000
--- a/arch/arm/mach-sa1100/include/mach/uncompress.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/mach-sa1100/include/mach/uncompress.h
- *
- * (C) 1999 Nicolas Pitre <nico@fluxnic.net>
- *
- * Reorganised to be machine independent.
- */
-
-#include "hardware.h"
-
-#define IOMEM(x) (x)
-
-/*
- * The following code assumes the serial port has already been
- * initialized by the bootloader. We search for the first enabled
- * port in the most probable order. If you didn't setup a port in
- * your bootloader then nothing will appear (which might be desired).
- */
-
-#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
-
-static inline void putc(int c)
-{
- unsigned long serial_port;
-
- do {
- serial_port = _Ser3UTCR0;
- if (UART(UTCR3) & UTCR3_TXE) break;
- serial_port = _Ser1UTCR0;
- if (UART(UTCR3) & UTCR3_TXE) break;
- serial_port = _Ser2UTCR0;
- if (UART(UTCR3) & UTCR3_TXE) break;
- return;
- } while (0);
-
- /* wait for space in the UART's transmitter */
- while (!(UART(UTSR1) & UTSR1_TNF))
- barrier();
-
- /* send the character out. */
- UART(UTDR) = c;
-}
-
-static inline void flush(void)
-{
-}
-
-/*
- * Nothing to do for these
- */
-#define arch_decomp_setup()
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
deleted file mode 100644
index e259298d9465..000000000000
--- a/arch/arm/mach-sa1100/jornada720.c
+++ /dev/null
@@ -1,380 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-sa1100/jornada720.c
- *
- * HP Jornada720 init code
- *
- * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
- * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
- * Copyright (C) 2005 Michael Gernoth <michael@gernoth.net>
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/tty.h>
-#include <linux/delay.h>
-#include <linux/gpio/machine.h>
-#include <linux/platform_data/sa11x0-serial.h>
-#include <linux/platform_device.h>
-#include <linux/ioport.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <video/s1d13xxxfb.h>
-
-#include <asm/hardware/sa1111.h>
-#include <asm/page.h>
-#include <asm/mach-types.h>
-#include <asm/setup.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-
-#include "generic.h"
-
-/*
- * HP Documentation referred in this file:
- * http://www.jlime.com/downloads/development/docs/jornada7xx/jornada720.txt
- */
-
-/* line 110 of HP's doc */
-#define TUCR_VAL 0x20000400
-
-/* memory space (line 52 of HP's doc) */
-#define SA1111REGSTART 0x40000000
-#define SA1111REGLEN 0x00002000
-#define EPSONREGSTART 0x48000000
-#define EPSONREGLEN 0x00100000
-#define EPSONFBSTART 0x48200000
-/* 512kB framebuffer */
-#define EPSONFBLEN 512*1024
-
-static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
- /* line 344 of HP's doc */
- {0x0001,0x00}, // Miscellaneous Register
- {0x01FC,0x00}, // Display Mode Register
- {0x0004,0x00}, // General IO Pins Configuration Register 0
- {0x0005,0x00}, // General IO Pins Configuration Register 1
- {0x0008,0x00}, // General IO Pins Control Register 0
- {0x0009,0x00}, // General IO Pins Control Register 1
- {0x0010,0x01}, // Memory Clock Configuration Register
- {0x0014,0x11}, // LCD Pixel Clock Configuration Register
- {0x0018,0x01}, // CRT/TV Pixel Clock Configuration Register
- {0x001C,0x01}, // MediaPlug Clock Configuration Register
- {0x001E,0x01}, // CPU To Memory Wait State Select Register
- {0x0020,0x00}, // Memory Configuration Register
- {0x0021,0x45}, // DRAM Refresh Rate Register
- {0x002A,0x01}, // DRAM Timings Control Register 0
- {0x002B,0x03}, // DRAM Timings Control Register 1
- {0x0030,0x1c}, // Panel Type Register
- {0x0031,0x00}, // MOD Rate Register
- {0x0032,0x4F}, // LCD Horizontal Display Width Register
- {0x0034,0x07}, // LCD Horizontal Non-Display Period Register
- {0x0035,0x01}, // TFT FPLINE Start Position Register
- {0x0036,0x0B}, // TFT FPLINE Pulse Width Register
- {0x0038,0xEF}, // LCD Vertical Display Height Register 0
- {0x0039,0x00}, // LCD Vertical Display Height Register 1
- {0x003A,0x13}, // LCD Vertical Non-Display Period Register
- {0x003B,0x0B}, // TFT FPFRAME Start Position Register
- {0x003C,0x01}, // TFT FPFRAME Pulse Width Register
- {0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
- {0x0041,0x00}, // LCD Miscellaneous Register
- {0x0042,0x00}, // LCD Display Start Address Register 0
- {0x0043,0x00}, // LCD Display Start Address Register 1
- {0x0044,0x00}, // LCD Display Start Address Register 2
- {0x0046,0x80}, // LCD Memory Address Offset Register 0
- {0x0047,0x02}, // LCD Memory Address Offset Register 1
- {0x0048,0x00}, // LCD Pixel Panning Register
- {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
- {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
- {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
- {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
- {0x0053,0x01}, // CRT/TV HRTC Start Position Register
- {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
- {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
- {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
- {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
- {0x0059,0x09}, // CRT/TV VRTC Start Position Register
- {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
- {0x005B,0x10}, // TV Output Control Register
- {0x0060,0x03}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
- {0x0062,0x00}, // CRT/TV Display Start Address Register 0
- {0x0063,0x00}, // CRT/TV Display Start Address Register 1
- {0x0064,0x00}, // CRT/TV Display Start Address Register 2
- {0x0066,0x40}, // CRT/TV Memory Address Offset Register 0
- {0x0067,0x01}, // CRT/TV Memory Address Offset Register 1
- {0x0068,0x00}, // CRT/TV Pixel Panning Register
- {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
- {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
- {0x0070,0x00}, // LCD Ink/Cursor Control Register
- {0x0071,0x01}, // LCD Ink/Cursor Start Address Register
- {0x0072,0x00}, // LCD Cursor X Position Register 0
- {0x0073,0x00}, // LCD Cursor X Position Register 1
- {0x0074,0x00}, // LCD Cursor Y Position Register 0
- {0x0075,0x00}, // LCD Cursor Y Position Register 1
- {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
- {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
- {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
- {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
- {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
- {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
- {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
- {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
- {0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register
- {0x0082,0x00}, // CRT/TV Cursor X Position Register 0
- {0x0083,0x00}, // CRT/TV Cursor X Position Register 1
- {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
- {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
- {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
- {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
- {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
- {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
- {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
- {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
- {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
- {0x0100,0x00}, // BitBlt Control Register 0
- {0x0101,0x00}, // BitBlt Control Register 1
- {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
- {0x0103,0x00}, // BitBlt Operation Register
- {0x0104,0x00}, // BitBlt Source Start Address Register 0
- {0x0105,0x00}, // BitBlt Source Start Address Register 1
- {0x0106,0x00}, // BitBlt Source Start Address Register 2
- {0x0108,0x00}, // BitBlt Destination Start Address Register 0
- {0x0109,0x00}, // BitBlt Destination Start Address Register 1
- {0x010A,0x00}, // BitBlt Destination Start Address Register 2
- {0x010C,0x00}, // BitBlt Memory Address Offset Register 0
- {0x010D,0x00}, // BitBlt Memory Address Offset Register 1
- {0x0110,0x00}, // BitBlt Width Register 0
- {0x0111,0x00}, // BitBlt Width Register 1
- {0x0112,0x00}, // BitBlt Height Register 0
- {0x0113,0x00}, // BitBlt Height Register 1
- {0x0114,0x00}, // BitBlt Background Color Register 0
- {0x0115,0x00}, // BitBlt Background Color Register 1
- {0x0118,0x00}, // BitBlt Foreground Color Register 0
- {0x0119,0x00}, // BitBlt Foreground Color Register 1
- {0x01E0,0x00}, // Look-Up Table Mode Register
- {0x01E2,0x00}, // Look-Up Table Address Register
- /* not sure, wouldn't like to mess with the driver */
- {0x01E4,0x00}, // Look-Up Table Data Register
- /* jornada doc says 0x00, but I trust the driver */
- {0x01F0,0x10}, // Power Save Configuration Register
- {0x01F1,0x00}, // Power Save Status Register
- {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
- {0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
-};
-
-static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
- .initregs = s1d13xxxfb_initregs,
- .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
- .platform_init_video = NULL
-};
-
-static struct resource s1d13xxxfb_resources[] = {
- [0] = DEFINE_RES_MEM(EPSONFBSTART, EPSONFBLEN),
- [1] = DEFINE_RES_MEM(EPSONREGSTART, EPSONREGLEN),
-};
-
-static struct platform_device s1d13xxxfb_device = {
- .name = S1D_DEVICENAME,
- .id = 0,
- .dev = {
- .platform_data = &s1d13xxxfb_data,
- },
- .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
- .resource = s1d13xxxfb_resources,
-};
-
-static struct gpiod_lookup_table jornada_pcmcia_gpiod_table = {
- .dev_id = "1800",
- .table = {
- GPIO_LOOKUP("sa1111", 0, "s0-power", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("sa1111", 1, "s1-power", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("sa1111", 2, "s0-3v", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("sa1111", 3, "s1-3v", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct resource sa1111_resources[] = {
- [0] = DEFINE_RES_MEM(SA1111REGSTART, SA1111REGLEN),
- [1] = DEFINE_RES_IRQ(IRQ_GPIO1),
-};
-
-static struct sa1111_platform_data sa1111_info = {
- .disable_devs = SA1111_DEVID_PS2_MSE,
-};
-
-static u64 sa1111_dmamask = 0xffffffffUL;
-
-static struct platform_device sa1111_device = {
- .name = "sa1111",
- .id = 0,
- .dev = {
- .dma_mask = &sa1111_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &sa1111_info,
- },
- .num_resources = ARRAY_SIZE(sa1111_resources),
- .resource = sa1111_resources,
-};
-
-static struct platform_device jornada_ssp_device = {
- .name = "jornada_ssp",
- .id = -1,
-};
-
-static struct resource jornada_kbd_resources[] = {
- DEFINE_RES_IRQ(IRQ_GPIO0),
-};
-
-static struct platform_device jornada_kbd_device = {
- .name = "jornada720_kbd",
- .id = -1,
- .num_resources = ARRAY_SIZE(jornada_kbd_resources),
- .resource = jornada_kbd_resources,
-};
-
-static struct gpiod_lookup_table jornada_ts_gpiod_table = {
- .dev_id = "jornada_ts",
- .table = {
- GPIO_LOOKUP("gpio", 9, "penup", GPIO_ACTIVE_HIGH),
- },
-};
-
-static struct platform_device jornada_ts_device = {
- .name = "jornada_ts",
- .id = -1,
-};
-
-static struct platform_device *devices[] __initdata = {
- &sa1111_device,
- &jornada_ssp_device,
- &s1d13xxxfb_device,
- &jornada_kbd_device,
- &jornada_ts_device,
-};
-
-static int __init jornada720_init(void)
-{
- int ret = -ENODEV;
-
- if (machine_is_jornada720()) {
- /* we want to use gpio20 as input to drive the clock of our uart 3 */
- GPDR |= GPIO_GPIO20; /* Clear gpio20 pin as input */
- TUCR = TUCR_VAL;
- GPSR = GPIO_GPIO20; /* start gpio20 pin */
- udelay(1);
- GPCR = GPIO_GPIO20; /* stop gpio20 */
- udelay(1);
- GPSR = GPIO_GPIO20; /* restart gpio20 */
- udelay(20); /* give it some time to restart */
-
- gpiod_add_lookup_table(&jornada_ts_gpiod_table);
- gpiod_add_lookup_table(&jornada_pcmcia_gpiod_table);
-
- ret = platform_add_devices(devices, ARRAY_SIZE(devices));
- }
-
- return ret;
-}
-
-arch_initcall(jornada720_init);
-
-static struct map_desc jornada720_io_desc[] __initdata = {
- { /* Epson registers */
- .virtual = 0xf0000000,
- .pfn = __phys_to_pfn(EPSONREGSTART),
- .length = EPSONREGLEN,
- .type = MT_DEVICE
- }, { /* Epson frame buffer */
- .virtual = 0xf1000000,
- .pfn = __phys_to_pfn(EPSONFBSTART),
- .length = EPSONFBLEN,
- .type = MT_DEVICE
- }
-};
-
-static void __init jornada720_map_io(void)
-{
- sa1100_map_io();
- iotable_init(jornada720_io_desc, ARRAY_SIZE(jornada720_io_desc));
-
- sa1100_register_uart(0, 3);
- sa1100_register_uart(1, 1);
-}
-
-static struct mtd_partition jornada720_partitions[] = {
- {
- .name = "JORNADA720 boot firmware",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- }, {
- .name = "JORNADA720 kernel",
- .size = 0x000c0000,
- .offset = 0x00040000,
- }, {
- .name = "JORNADA720 params",
- .size = 0x00040000,
- .offset = 0x00100000,
- }, {
- .name = "JORNADA720 initrd",
- .size = 0x00100000,
- .offset = 0x00140000,
- }, {
- .name = "JORNADA720 root cramfs",
- .size = 0x00300000,
- .offset = 0x00240000,
- }, {
- .name = "JORNADA720 usr cramfs",
- .size = 0x00800000,
- .offset = 0x00540000,
- }, {
- .name = "JORNADA720 usr local",
- .size = 0, /* will expand to the end of the flash */
- .offset = 0x00d00000,
- }
-};
-
-static void jornada720_set_vpp(int vpp)
-{
- if (vpp)
- /* enabling flash write (line 470 of HP's doc) */
- PPSR |= PPC_LDD7;
- else
- /* disabling flash write (line 470 of HP's doc) */
- PPSR &= ~PPC_LDD7;
- PPDR |= PPC_LDD7;
-}
-
-static struct flash_platform_data jornada720_flash_data = {
- .map_name = "cfi_probe",
- .set_vpp = jornada720_set_vpp,
- .parts = jornada720_partitions,
- .nr_parts = ARRAY_SIZE(jornada720_partitions),
-};
-
-static struct resource jornada720_flash_resource =
- DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
-
-static void __init jornada720_mach_init(void)
-{
- sa11x0_register_mtd(&jornada720_flash_data, &jornada720_flash_resource, 1);
-}
-
-MACHINE_START(JORNADA720, "HP Jornada 720")
- /* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */
- .atag_offset = 0x100,
- .map_io = jornada720_map_io,
- .nr_irqs = SA1100_NR_IRQS,
- .init_irq = sa1100_init_irq,
- .init_time = sa1100_timer_init,
- .init_machine = jornada720_mach_init,
- .init_late = sa11x0_init_late,
-#ifdef CONFIG_SA1111
- .dma_zone_size = SZ_1M,
-#endif
- .restart = sa11x0_restart,
-MACHINE_END
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
deleted file mode 100644
index d94810217095..000000000000
--- a/arch/arm/mach-sa1100/jornada720_ssp.c
+++ /dev/null
@@ -1,202 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mac-sa1100/jornada720_ssp.c
- *
- * Copyright (C) 2006/2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
- * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
- *
- * SSP driver for the HP Jornada 710/720/728
- */
-
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/sched.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/jornada720.h>
-#include <asm/hardware/ssp.h>
-
-static DEFINE_SPINLOCK(jornada_ssp_lock);
-static unsigned long jornada_ssp_flags;
-
-/**
- * jornada_ssp_reverse - reverses input byte
- * @byte: input byte to reverse
- *
- * we need to reverse all data we receive from the mcu due to its physical location
- * returns : 01110111 -> 11101110
- */
-inline u8 jornada_ssp_reverse(u8 byte)
-{
- return
- ((0x80 & byte) >> 7) |
- ((0x40 & byte) >> 5) |
- ((0x20 & byte) >> 3) |
- ((0x10 & byte) >> 1) |
- ((0x08 & byte) << 1) |
- ((0x04 & byte) << 3) |
- ((0x02 & byte) << 5) |
- ((0x01 & byte) << 7);
-};
-EXPORT_SYMBOL(jornada_ssp_reverse);
-
-/**
- * jornada_ssp_byte - waits for ready ssp bus and sends byte
- * @byte: input byte to transmit
- *
- * waits for fifo buffer to clear and then transmits, if it doesn't then we will
- * timeout after <timeout> rounds. Needs mcu running before its called.
- *
- * returns : %mcu output on success
- * : %-ETIMEDOUT on timeout
- */
-int jornada_ssp_byte(u8 byte)
-{
- int timeout = 400000;
- u16 ret;
-
- while ((GPLR & GPIO_GPIO10)) {
- if (!--timeout) {
- printk(KERN_WARNING "SSP: timeout while waiting for transmit\n");
- return -ETIMEDOUT;
- }
- cpu_relax();
- }
-
- ret = jornada_ssp_reverse(byte) << 8;
-
- ssp_write_word(ret);
- ssp_read_word(&ret);
-
- return jornada_ssp_reverse(ret);
-};
-EXPORT_SYMBOL(jornada_ssp_byte);
-
-/**
- * jornada_ssp_inout - decide if input is command or trading byte
- * @byte: input byte to send (may be %TXDUMMY)
- *
- * returns : (jornada_ssp_byte(byte)) on success
- * : %-ETIMEDOUT on timeout failure
- */
-int jornada_ssp_inout(u8 byte)
-{
- int ret, i;
-
- /* true means command byte */
- if (byte != TXDUMMY) {
- ret = jornada_ssp_byte(byte);
- /* Proper return to commands is TxDummy */
- if (ret != TXDUMMY) {
- for (i = 0; i < 256; i++)/* flushing bus */
- if (jornada_ssp_byte(TXDUMMY) == -1)
- break;
- return -ETIMEDOUT;
- }
- } else /* Exchange TxDummy for data */
- ret = jornada_ssp_byte(TXDUMMY);
-
- return ret;
-};
-EXPORT_SYMBOL(jornada_ssp_inout);
-
-/**
- * jornada_ssp_start - enable mcu
- *
- */
-void jornada_ssp_start(void)
-{
- spin_lock_irqsave(&jornada_ssp_lock, jornada_ssp_flags);
- GPCR = GPIO_GPIO25;
- udelay(50);
- return;
-};
-EXPORT_SYMBOL(jornada_ssp_start);
-
-/**
- * jornada_ssp_end - disable mcu and turn off lock
- *
- */
-void jornada_ssp_end(void)
-{
- GPSR = GPIO_GPIO25;
- spin_unlock_irqrestore(&jornada_ssp_lock, jornada_ssp_flags);
- return;
-};
-EXPORT_SYMBOL(jornada_ssp_end);
-
-static int jornada_ssp_probe(struct platform_device *dev)
-{
- int ret;
-
- GPSR = GPIO_GPIO25;
-
- ret = ssp_init();
-
- /* worked fine, lets not bother with anything else */
- if (!ret) {
- printk(KERN_INFO "SSP: device initialized with irq\n");
- return ret;
- }
-
- printk(KERN_WARNING "SSP: initialization failed, trying non-irq solution \n");
-
- /* init of Serial 4 port */
- Ser4MCCR0 = 0;
- Ser4SSCR0 = 0x0387;
- Ser4SSCR1 = 0x18;
-
- /* clear out any left over data */
- ssp_flush();
-
- /* enable MCU */
- jornada_ssp_start();
-
- /* see if return value makes sense */
- ret = jornada_ssp_inout(GETBRIGHTNESS);
-
- /* seems like it worked, just feed it with TxDummy to get rid of data */
- if (ret == TXDUMMY)
- jornada_ssp_inout(TXDUMMY);
-
- jornada_ssp_end();
-
- /* failed, lets just kill everything */
- if (ret == -ETIMEDOUT) {
- printk(KERN_WARNING "SSP: attempts failed, bailing\n");
- ssp_exit();
- return -ENODEV;
- }
-
- /* all fine */
- printk(KERN_INFO "SSP: device initialized\n");
- return 0;
-};
-
-static void jornada_ssp_remove(struct platform_device *dev)
-{
- /* Note that this doesn't actually remove the driver, since theres nothing to remove
- * It just makes sure everything is turned off */
- GPSR = GPIO_GPIO25;
- ssp_exit();
-};
-
-struct platform_driver jornadassp_driver = {
- .probe = jornada_ssp_probe,
- .remove = jornada_ssp_remove,
- .driver = {
- .name = "jornada_ssp",
- },
-};
-
-static int __init jornada_ssp_init(void)
-{
- return platform_driver_register(&jornadassp_driver);
-}
-
-module_init(jornada_ssp_init);
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
deleted file mode 100644
index 9e8a3284a6cf..000000000000
--- a/arch/arm/mach-sa1100/neponset.c
+++ /dev/null
@@ -1,438 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/arm/mach-sa1100/neponset.c
- */
-#include <linux/err.h>
-#include <linux/gpio/driver.h>
-#include <linux/gpio/gpio-reg.h>
-#include <linux/gpio/machine.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/pm.h>
-#include <linux/serial_core.h>
-#include <linux/slab.h>
-#include <linux/smc91x.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/map.h>
-#include <asm/hardware/sa1111.h>
-#include <linux/sizes.h>
-
-#include <mach/hardware.h>
-#include <mach/assabet.h>
-#include <mach/neponset.h>
-#include <mach/irqs.h>
-
-#define NEP_IRQ_SMC91X 0
-#define NEP_IRQ_USAR 1
-#define NEP_IRQ_SA1111 2
-#define NEP_IRQ_NR 3
-
-#define WHOAMI 0x00
-#define LEDS 0x10
-#define SWPK 0x20
-#define IRR 0x24
-#define KP_Y_IN 0x80
-#define KP_X_OUT 0x90
-#define NCR_0 0xa0
-#define MDM_CTL_0 0xb0
-#define MDM_CTL_1 0xb4
-#define AUD_CTL 0xc0
-
-#define IRR_ETHERNET (1 << 0)
-#define IRR_USAR (1 << 1)
-#define IRR_SA1111 (1 << 2)
-
-#define NCR_NGPIO 7
-#define MDM_CTL0_NGPIO 4
-#define MDM_CTL1_NGPIO 6
-#define AUD_NGPIO 2
-
-extern void sa1110_mb_disable(void);
-
-#define to_neponset_gpio_chip(x) container_of(x, struct neponset_gpio_chip, gc)
-
-static const char *neponset_ncr_names[] = {
- "gp01_off", "tp_power", "ms_power", "enet_osc",
- "spi_kb_wk_up", "a0vpp", "a1vpp"
-};
-
-static const char *neponset_mdmctl0_names[] = {
- "rts3", "dtr3", "rts1", "dtr1",
-};
-
-static const char *neponset_mdmctl1_names[] = {
- "cts3", "dsr3", "dcd3", "cts1", "dsr1", "dcd1"
-};
-
-static const char *neponset_aud_names[] = {
- "sel_1341", "mute_1341",
-};
-
-struct neponset_drvdata {
- void __iomem *base;
- struct platform_device *sa1111;
- struct platform_device *smc91x;
- unsigned irq_base;
- struct gpio_chip *gpio[4];
-};
-
-static struct gpiod_lookup_table neponset_uart1_gpio_table = {
- .dev_id = "sa11x0-uart.1",
- .table = {
- GPIO_LOOKUP("neponset-mdm-ctl0", 2, "rts", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("neponset-mdm-ctl0", 3, "dtr", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("neponset-mdm-ctl1", 3, "cts", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("neponset-mdm-ctl1", 4, "dsr", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("neponset-mdm-ctl1", 5, "dcd", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct gpiod_lookup_table neponset_uart3_gpio_table = {
- .dev_id = "sa11x0-uart.3",
- .table = {
- GPIO_LOOKUP("neponset-mdm-ctl0", 0, "rts", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("neponset-mdm-ctl0", 1, "dtr", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("neponset-mdm-ctl1", 0, "cts", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("neponset-mdm-ctl1", 1, "dsr", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("neponset-mdm-ctl1", 2, "dcd", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct gpiod_lookup_table neponset_pcmcia_table = {
- .dev_id = "1800",
- .table = {
- GPIO_LOOKUP("sa1111", 1, "a0vcc", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("sa1111", 0, "a1vcc", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("neponset-ncr", 5, "a0vpp", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("neponset-ncr", 6, "a1vpp", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("sa1111", 2, "b0vcc", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("sa1111", 3, "b1vcc", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct neponset_drvdata *nep;
-
-void neponset_ncr_frob(unsigned int mask, unsigned int val)
-{
- struct neponset_drvdata *n = nep;
- unsigned long m = mask, v = val;
-
- if (nep)
- n->gpio[0]->set_multiple(n->gpio[0], &m, &v);
- else
- WARN(1, "nep unset\n");
-}
-EXPORT_SYMBOL(neponset_ncr_frob);
-
-/*
- * Install handler for Neponset IRQ. Note that we have to loop here
- * since the ETHERNET and USAR IRQs are level based, and we need to
- * ensure that the IRQ signal is deasserted before returning. This
- * is rather unfortunate.
- */
-static void neponset_irq_handler(struct irq_desc *desc)
-{
- struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
- unsigned int irr;
-
- while (1) {
- /*
- * Acknowledge the parent IRQ.
- */
- desc->irq_data.chip->irq_ack(&desc->irq_data);
-
- /*
- * Read the interrupt reason register. Let's have all
- * active IRQ bits high. Note: there is a typo in the
- * Neponset user's guide for the SA1111 IRR level.
- */
- irr = readb_relaxed(d->base + IRR);
- irr ^= IRR_ETHERNET | IRR_USAR;
-
- if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
- break;
-
- /*
- * Since there is no individual mask, we have to
- * mask the parent IRQ. This is safe, since we'll
- * recheck the register for any pending IRQs.
- */
- if (irr & (IRR_ETHERNET | IRR_USAR)) {
- desc->irq_data.chip->irq_mask(&desc->irq_data);
-
- /*
- * Ack the interrupt now to prevent re-entering
- * this neponset handler. Again, this is safe
- * since we'll check the IRR register prior to
- * leaving.
- */
- desc->irq_data.chip->irq_ack(&desc->irq_data);
-
- if (irr & IRR_ETHERNET)
- generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X);
-
- if (irr & IRR_USAR)
- generic_handle_irq(d->irq_base + NEP_IRQ_USAR);
-
- desc->irq_data.chip->irq_unmask(&desc->irq_data);
- }
-
- if (irr & IRR_SA1111)
- generic_handle_irq(d->irq_base + NEP_IRQ_SA1111);
- }
-}
-
-/* Yes, we really do not have any kind of masking or unmasking */
-static void nochip_noop(struct irq_data *irq)
-{
-}
-
-static struct irq_chip nochip = {
- .name = "neponset",
- .irq_ack = nochip_noop,
- .irq_mask = nochip_noop,
- .irq_unmask = nochip_noop,
-};
-
-static int neponset_init_gpio(struct gpio_chip **gcp,
- struct device *dev, const char *label, void __iomem *reg,
- unsigned num, bool in, const char *const * names)
-{
- struct gpio_chip *gc;
-
- gc = gpio_reg_init(dev, reg, -1, num, label, in ? 0xffffffff : 0,
- readl_relaxed(reg), names, NULL, NULL);
- if (IS_ERR(gc))
- return PTR_ERR(gc);
-
- *gcp = gc;
-
- return 0;
-}
-
-static struct sa1111_platform_data sa1111_info = {
- .disable_devs = SA1111_DEVID_PS2_MSE,
-};
-
-static int neponset_probe(struct platform_device *dev)
-{
- struct neponset_drvdata *d;
- struct resource *nep_res, *sa1111_res, *smc91x_res;
- struct resource sa1111_resources[] = {
- DEFINE_RES_MEM(0x40000000, SZ_8K),
- { .flags = IORESOURCE_IRQ },
- };
- struct platform_device_info sa1111_devinfo = {
- .parent = &dev->dev,
- .name = "sa1111",
- .id = 0,
- .res = sa1111_resources,
- .num_res = ARRAY_SIZE(sa1111_resources),
- .data = &sa1111_info,
- .size_data = sizeof(sa1111_info),
- .dma_mask = 0xffffffffUL,
- };
- struct resource smc91x_resources[] = {
- DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
- 0x02000000, "smc91x-regs"),
- DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
- 0x02000000, "smc91x-attrib"),
- { .flags = IORESOURCE_IRQ },
- };
- struct smc91x_platdata smc91x_platdata = {
- .flags = SMC91X_USE_8BIT | SMC91X_IO_SHIFT_2 | SMC91X_NOWAIT,
- };
- struct platform_device_info smc91x_devinfo = {
- .parent = &dev->dev,
- .name = "smc91x",
- .id = 0,
- .res = smc91x_resources,
- .num_res = ARRAY_SIZE(smc91x_resources),
- .data = &smc91x_platdata,
- .size_data = sizeof(smc91x_platdata),
- };
- int ret, irq;
-
- if (nep)
- return -EBUSY;
-
- irq = ret = platform_get_irq(dev, 0);
- if (ret < 0)
- goto err_alloc;
-
- nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
- smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
- sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
- if (!nep_res || !smc91x_res || !sa1111_res) {
- ret = -ENXIO;
- goto err_alloc;
- }
-
- d = kzalloc_obj(*d);
- if (!d) {
- ret = -ENOMEM;
- goto err_alloc;
- }
-
- d->base = ioremap(nep_res->start, SZ_4K);
- if (!d->base) {
- ret = -ENOMEM;
- goto err_ioremap;
- }
-
- if (readb_relaxed(d->base + WHOAMI) != 0x11) {
- dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
- readb_relaxed(d->base + WHOAMI));
- ret = -ENODEV;
- goto err_id;
- }
-
- ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
- if (ret <= 0) {
- dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
- NEP_IRQ_NR, ret);
- if (ret == 0)
- ret = -ENOMEM;
- goto err_irq_alloc;
- }
-
- d->irq_base = ret;
-
- irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
- handle_simple_irq);
- irq_clear_status_flags(d->irq_base + NEP_IRQ_SMC91X, IRQ_NOREQUEST | IRQ_NOPROBE);
- irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
- handle_simple_irq);
- irq_clear_status_flags(d->irq_base + NEP_IRQ_USAR, IRQ_NOREQUEST | IRQ_NOPROBE);
- irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);
-
- irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
- irq_set_chained_handler_and_data(irq, neponset_irq_handler, d);
-
- /* Disable GPIO 0/1 drivers so the buttons work on the Assabet */
- writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0);
-
- neponset_init_gpio(&d->gpio[0], &dev->dev, "neponset-ncr",
- d->base + NCR_0, NCR_NGPIO, false,
- neponset_ncr_names);
- neponset_init_gpio(&d->gpio[1], &dev->dev, "neponset-mdm-ctl0",
- d->base + MDM_CTL_0, MDM_CTL0_NGPIO, false,
- neponset_mdmctl0_names);
- neponset_init_gpio(&d->gpio[2], &dev->dev, "neponset-mdm-ctl1",
- d->base + MDM_CTL_1, MDM_CTL1_NGPIO, true,
- neponset_mdmctl1_names);
- neponset_init_gpio(&d->gpio[3], &dev->dev, "neponset-aud-ctl",
- d->base + AUD_CTL, AUD_NGPIO, false,
- neponset_aud_names);
-
- gpiod_add_lookup_table(&neponset_uart1_gpio_table);
- gpiod_add_lookup_table(&neponset_uart3_gpio_table);
- gpiod_add_lookup_table(&neponset_pcmcia_table);
-
- /*
- * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately
- * something on the Neponset activates this IRQ on sleep (eth?)
- */
-#if 0
- enable_irq_wake(irq);
-#endif
-
- dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n",
- d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
- nep = d;
-
- /* Ensure that the memory bus request/grant signals are setup */
- sa1110_mb_disable();
-
- sa1111_resources[0].parent = sa1111_res;
- sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111;
- sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111;
- d->sa1111 = platform_device_register_full(&sa1111_devinfo);
-
- smc91x_resources[0].parent = smc91x_res;
- smc91x_resources[1].parent = smc91x_res;
- smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
- smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
- d->smc91x = platform_device_register_full(&smc91x_devinfo);
-
- platform_set_drvdata(dev, d);
-
- return 0;
-
- err_irq_alloc:
- err_id:
- iounmap(d->base);
- err_ioremap:
- kfree(d);
- err_alloc:
- return ret;
-}
-
-static void neponset_remove(struct platform_device *dev)
-{
- struct neponset_drvdata *d = platform_get_drvdata(dev);
- int irq = platform_get_irq(dev, 0);
-
- if (!IS_ERR(d->sa1111))
- platform_device_unregister(d->sa1111);
- if (!IS_ERR(d->smc91x))
- platform_device_unregister(d->smc91x);
-
- gpiod_remove_lookup_table(&neponset_pcmcia_table);
- gpiod_remove_lookup_table(&neponset_uart3_gpio_table);
- gpiod_remove_lookup_table(&neponset_uart1_gpio_table);
-
- irq_set_chained_handler(irq, NULL);
- irq_free_descs(d->irq_base, NEP_IRQ_NR);
- nep = NULL;
- iounmap(d->base);
- kfree(d);
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int neponset_resume(struct device *dev)
-{
- struct neponset_drvdata *d = dev_get_drvdata(dev);
- int i, ret = 0;
-
- for (i = 0; i < ARRAY_SIZE(d->gpio); i++) {
- ret = gpio_reg_resume(d->gpio[i]);
- if (ret)
- break;
- }
-
- return ret;
-}
-
-static const struct dev_pm_ops neponset_pm_ops = {
- .resume_noirq = neponset_resume,
- .restore_noirq = neponset_resume,
-};
-#define PM_OPS &neponset_pm_ops
-#else
-#define PM_OPS NULL
-#endif
-
-static struct platform_driver neponset_device_driver = {
- .probe = neponset_probe,
- .remove = neponset_remove,
- .driver = {
- .name = "neponset",
- .pm = PM_OPS,
- },
-};
-
-static int __init neponset_init(void)
-{
- return platform_driver_register(&neponset_device_driver);
-}
-
-subsys_initcall(neponset_init);
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
deleted file mode 100644
index 9495fc109baa..000000000000
--- a/arch/arm/mach-sa1100/pm.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * SA1100 Power Management Routines
- *
- * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License.
- *
- * History:
- *
- * 2001-02-06: Cliff Brake Initial code
- *
- * 2001-02-25: Sukjae Cho <sjcho@east.isi.edu> &
- * Chester Kuo <chester@linux.org.tw>
- * Save more value for the resume function! Support
- * Bitsy/Assabet/Freebird board
- *
- * 2001-08-29: Nicolas Pitre <nico@fluxnic.net>
- * Cleaned up, pushed platform dependent stuff
- * in the platform specific files.
- *
- * 2002-05-27: Nicolas Pitre Killed sleep.h and the kmalloced save array.
- * Storage is local on the stack now.
- */
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/suspend.h>
-#include <linux/errno.h>
-#include <linux/time.h>
-
-#include <mach/hardware.h>
-#include <asm/page.h>
-#include <asm/suspend.h>
-#include <asm/mach/time.h>
-
-#include "generic.h"
-
-extern int sa1100_finish_suspend(unsigned long);
-
-#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
-#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
-
-/*
- * List of global SA11x0 peripheral registers to preserve.
- * More ones like CP and general purpose register values are preserved
- * on the stack and then the stack pointer is stored last in sleep.S.
- */
-enum { SLEEP_SAVE_GPDR, SLEEP_SAVE_GAFR,
- SLEEP_SAVE_PPDR, SLEEP_SAVE_PPSR, SLEEP_SAVE_PPAR, SLEEP_SAVE_PSDR,
-
- SLEEP_SAVE_Ser1SDCR0,
-
- SLEEP_SAVE_COUNT
-};
-
-
-static int sa11x0_pm_enter(suspend_state_t state)
-{
- unsigned long gpio, sleep_save[SLEEP_SAVE_COUNT];
-
- gpio = GPLR;
-
- /* save vital registers */
- SAVE(GPDR);
- SAVE(GAFR);
-
- SAVE(PPDR);
- SAVE(PPSR);
- SAVE(PPAR);
- SAVE(PSDR);
-
- SAVE(Ser1SDCR0);
-
- /* Clear previous reset status */
- RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR;
-
- /* set resume return address */
- PSPR = __pa_symbol(cpu_resume);
-
- /* go zzz */
- cpu_suspend(0, sa1100_finish_suspend);
-
- /*
- * Ensure not to come back here if it wasn't intended
- */
- RCSR = RCSR_SMR;
- PSPR = 0;
-
- /*
- * Ensure interrupt sources are disabled; we will re-init
- * the interrupt subsystem via the device manager.
- */
- ICLR = 0;
- ICCR = 1;
- ICMR = 0;
-
- /* restore registers */
- RESTORE(GPDR);
- RESTORE(GAFR);
-
- RESTORE(PPDR);
- RESTORE(PPSR);
- RESTORE(PPAR);
- RESTORE(PSDR);
-
- RESTORE(Ser1SDCR0);
-
- GPSR = gpio;
- GPCR = ~gpio;
-
- /*
- * Clear the peripheral sleep-hold bit.
- */
- PSSR = PSSR_PH;
-
- return 0;
-}
-
-static const struct platform_suspend_ops sa11x0_pm_ops = {
- .enter = sa11x0_pm_enter,
- .valid = suspend_valid_only_mem,
-};
-
-int __init sa11x0_pm_init(void)
-{
- suspend_set_ops(&sa11x0_pm_ops);
- return 0;
-}
diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
deleted file mode 100644
index 85863741ef8b..000000000000
--- a/arch/arm/mach-sa1100/sleep.S
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * SA11x0 Assembler Sleep/WakeUp Management Routines
- *
- * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License.
- *
- * History:
- *
- * 2001-02-06: Cliff Brake Initial code
- *
- * 2001-08-29: Nicolas Pitre Simplified.
- *
- * 2002-05-27: Nicolas Pitre Revisited, more cleanup and simplification.
- * Storage is on the stack now.
- */
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <mach/hardware.h>
-
- .text
-/*
- * sa1100_finish_suspend()
- *
- * Causes sa11x0 to enter sleep state
- *
- * Must be aligned to a cacheline.
- */
- .balign 32
-ENTRY(sa1100_finish_suspend)
- @ disable clock switching
- mcr p15, 0, r1, c15, c2, 2
-
- ldr r6, =MDREFR
- ldr r4, [r6]
- orr r4, r4, #MDREFR_K1DB2
- ldr r5, =PPCR
-
- @ Pre-load __loop_udelay into the I-cache
- mov r0, #1
- bl __loop_udelay
- mov r0, r0
-
- @ The following must all exist in a single cache line to
- @ avoid accessing memory until this sequence is complete,
- @ otherwise we occasionally hang.
-
- @ Adjust memory timing before lowering CPU clock
- str r4, [r6]
-
- @ delay 90us and set CPU PLL to lowest speed
- @ fixes resume problem on high speed SA1110
- mov r0, #90
- bl __loop_udelay
- mov r1, #0
- str r1, [r5]
- mov r0, #90
- bl __loop_udelay
-
- /*
- * SA1110 SDRAM controller workaround. register values:
- *
- * r0 = &MSC0
- * r1 = &MSC1
- * r2 = &MSC2
- * r3 = MSC0 value
- * r4 = MSC1 value
- * r5 = MSC2 value
- * r6 = &MDREFR
- * r7 = first MDREFR value
- * r8 = second MDREFR value
- * r9 = &MDCNFG
- * r10 = MDCNFG value
- * r11 = third MDREFR value
- * r12 = &PMCR
- * r13 = PMCR value (1)
- */
-
- ldr r0, =MSC0
- ldr r1, =MSC1
- ldr r2, =MSC2
-
- ldr r3, [r0]
- bic r3, r3, #FMsk(MSC_RT)
- bic r3, r3, #FMsk(MSC_RT)<<16
-
- ldr r4, [r1]
- bic r4, r4, #FMsk(MSC_RT)
- bic r4, r4, #FMsk(MSC_RT)<<16
-
- ldr r5, [r2]
- bic r5, r5, #FMsk(MSC_RT)
- bic r5, r5, #FMsk(MSC_RT)<<16
-
- ldr r7, [r6]
- bic r7, r7, #0x0000FF00
- bic r7, r7, #0x000000F0
- orr r8, r7, #MDREFR_SLFRSH
-
- ldr r9, =MDCNFG
- ldr r10, [r9]
- bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1)
- bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3)
-
- bic r11, r8, #MDREFR_SLFRSH
- bic r11, r11, #MDREFR_E1PIN
-
- ldr r12, =PMCR
-
- mov r13, #PMCR_SF
-
- b sa1110_sdram_controller_fix
-
- .align 5
-sa1110_sdram_controller_fix:
-
- @ Step 1 clear RT field of all MSCx registers
- str r3, [r0]
- str r4, [r1]
- str r5, [r2]
-
- @ Step 2 clear DRI field in MDREFR
- str r7, [r6]
-
- @ Step 3 set SLFRSH bit in MDREFR
- str r8, [r6]
-
- @ Step 4 clear DE bis in MDCNFG
- str r10, [r9]
-
- @ Step 5 clear DRAM refresh control register
- str r11, [r6]
-
- @ Wow, now the hardware suspend request pins can be used, that makes them functional for
- @ about 7 ns out of the entire time that the CPU is running!
-
- @ Step 6 set force sleep bit in PMCR
-
- str r13, [r12]
-
-20: b 20b @ loop waiting for sleep
diff --git a/arch/arm/mach-sa1100/ssp.c b/arch/arm/mach-sa1100/ssp.c
deleted file mode 100644
index 613fd767afcf..000000000000
--- a/arch/arm/mach-sa1100/ssp.c
+++ /dev/null
@@ -1,240 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-sa1100/ssp.c
- *
- * Copyright (C) 2003 Russell King.
- *
- * Generic SSP driver. This provides the generic core for simple
- * IO-based SSP applications.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <asm/hardware/ssp.h>
-
-#define TIMEOUT 100000
-
-static irqreturn_t ssp_interrupt(int irq, void *dev_id)
-{
- unsigned int status = Ser4SSSR;
-
- if (status & SSSR_ROR)
- printk(KERN_WARNING "SSP: receiver overrun\n");
-
- Ser4SSSR = SSSR_ROR;
-
- return status ? IRQ_HANDLED : IRQ_NONE;
-}
-
-/**
- * ssp_write_word - write a word to the SSP port
- * @data: 16-bit, MSB justified data to write.
- *
- * Wait for a free entry in the SSP transmit FIFO, and write a data
- * word to the SSP port. Wait for the SSP port to start sending
- * the data.
- *
- * The caller is expected to perform the necessary locking.
- *
- * Returns:
- * %-ETIMEDOUT timeout occurred
- * 0 success
- */
-int ssp_write_word(u16 data)
-{
- int timeout = TIMEOUT;
-
- while (!(Ser4SSSR & SSSR_TNF)) {
- if (!--timeout)
- return -ETIMEDOUT;
- cpu_relax();
- }
-
- Ser4SSDR = data;
-
- timeout = TIMEOUT;
- while (!(Ser4SSSR & SSSR_BSY)) {
- if (!--timeout)
- return -ETIMEDOUT;
- cpu_relax();
- }
-
- return 0;
-}
-
-/**
- * ssp_read_word - read a word from the SSP port
- *
- * Wait for a data word in the SSP receive FIFO, and return the
- * received data. Data is LSB justified.
- *
- * Note: Currently, if data is not expected to be received, this
- * function will wait for ever.
- *
- * The caller is expected to perform the necessary locking.
- *
- * Returns:
- * %-ETIMEDOUT timeout occurred
- * 16-bit data success
- */
-int ssp_read_word(u16 *data)
-{
- int timeout = TIMEOUT;
-
- while (!(Ser4SSSR & SSSR_RNE)) {
- if (!--timeout)
- return -ETIMEDOUT;
- cpu_relax();
- }
-
- *data = (u16)Ser4SSDR;
-
- return 0;
-}
-
-/**
- * ssp_flush - flush the transmit and receive FIFOs
- *
- * Wait for the SSP to idle, and ensure that the receive FIFO
- * is empty.
- *
- * The caller is expected to perform the necessary locking.
- *
- * Returns:
- * %-ETIMEDOUT timeout occurred
- * 0 success
- */
-int ssp_flush(void)
-{
- int timeout = TIMEOUT * 2;
-
- do {
- while (Ser4SSSR & SSSR_RNE) {
- if (!--timeout)
- return -ETIMEDOUT;
- (void) Ser4SSDR;
- }
- if (!--timeout)
- return -ETIMEDOUT;
- } while (Ser4SSSR & SSSR_BSY);
-
- return 0;
-}
-
-/**
- * ssp_enable - enable the SSP port
- *
- * Turn on the SSP port.
- */
-void ssp_enable(void)
-{
- Ser4SSCR0 |= SSCR0_SSE;
-}
-
-/**
- * ssp_disable - shut down the SSP port
- *
- * Turn off the SSP port, optionally powering it down.
- */
-void ssp_disable(void)
-{
- Ser4SSCR0 &= ~SSCR0_SSE;
-}
-
-/**
- * ssp_save_state - save the SSP configuration
- * @ssp: pointer to structure to save SSP configuration
- *
- * Save the configured SSP state for suspend.
- */
-void ssp_save_state(struct ssp_state *ssp)
-{
- ssp->cr0 = Ser4SSCR0;
- ssp->cr1 = Ser4SSCR1;
-
- Ser4SSCR0 &= ~SSCR0_SSE;
-}
-
-/**
- * ssp_restore_state - restore a previously saved SSP configuration
- * @ssp: pointer to configuration saved by ssp_save_state
- *
- * Restore the SSP configuration saved previously by ssp_save_state.
- */
-void ssp_restore_state(struct ssp_state *ssp)
-{
- Ser4SSSR = SSSR_ROR;
-
- Ser4SSCR0 = ssp->cr0 & ~SSCR0_SSE;
- Ser4SSCR1 = ssp->cr1;
- Ser4SSCR0 = ssp->cr0;
-}
-
-/**
- * ssp_init - setup the SSP port
- *
- * initialise and claim resources for the SSP port.
- *
- * Returns:
- * %-ENODEV if the SSP port is unavailable
- * %-EBUSY if the resources are already in use
- * %0 on success
- */
-int ssp_init(void)
-{
- int ret;
-
- if (!(PPAR & PPAR_SPR) && (Ser4MCCR0 & MCCR0_MCE))
- return -ENODEV;
-
- if (!request_mem_region(__PREG(Ser4SSCR0), 0x18, "SSP")) {
- return -EBUSY;
- }
-
- Ser4SSSR = SSSR_ROR;
-
- ret = request_irq(IRQ_Ser4SSP, ssp_interrupt, 0, "SSP", NULL);
- if (ret)
- goto out_region;
-
- return 0;
-
- out_region:
- release_mem_region(__PREG(Ser4SSCR0), 0x18);
- return ret;
-}
-
-/**
- * ssp_exit - undo the effects of ssp_init
- *
- * release and free resources for the SSP port.
- */
-void ssp_exit(void)
-{
- Ser4SSCR0 &= ~SSCR0_SSE;
-
- free_irq(IRQ_Ser4SSP, NULL);
- release_mem_region(__PREG(Ser4SSCR0), 0x18);
-}
-
-MODULE_AUTHOR("Russell King");
-MODULE_DESCRIPTION("SA11x0 SSP PIO driver");
-MODULE_LICENSE("GPL");
-
-EXPORT_SYMBOL(ssp_write_word);
-EXPORT_SYMBOL(ssp_read_word);
-EXPORT_SYMBOL(ssp_flush);
-EXPORT_SYMBOL(ssp_enable);
-EXPORT_SYMBOL(ssp_disable);
-EXPORT_SYMBOL(ssp_save_state);
-EXPORT_SYMBOL(ssp_restore_state);
-EXPORT_SYMBOL(ssp_init);
-EXPORT_SYMBOL(ssp_exit);
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 0cc1bf04686d..bf94f2718293 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -226,11 +226,6 @@ void __init arch_mm_preinit(void)
swiotlb_init(max_pfn > arm_dma_pfn_limit, SWIOTLB_VERBOSE);
#endif
-#ifdef CONFIG_SA1111
- /* now that our DMA memory is actually so designated, we can free it */
- memblock_phys_free(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
-#endif
-
/*
* Check boundaries twice: Some fundamental inconsistencies can
* be detected at build time already.
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 23b87b5ef7f1..350f6dcc24cc 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -1339,14 +1339,6 @@ void __init arm_mm_memblock_reserve(void)
* and can only be in node 0.
*/
memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
-
-#ifdef CONFIG_SA1111
- /*
- * Because of the SA1111 DMA bug, we want to preserve our
- * precious DMA-able memory...
- */
- memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
-#endif
}
/*
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 05b9233b9418..55ffee3d75ce 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1541,8 +1541,8 @@ config RTC_DRV_EP93XX
will be called rtc-ep93xx.
config RTC_DRV_SA1100
- tristate "SA11x0/PXA2xx/PXA910"
- depends on ARCH_SA1100 || ARCH_PXA || ARCH_MMP
+ tristate "PXA2xx/PXA910"
+ depends on ARCH_PXA || ARCH_MMP
help
If you say Y here you will get access to the real time clock
built into your SA11x0 or PXA2xx CPU.
diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c
index 26b2f4184ecc..dc98484dbe27 100644
--- a/drivers/rtc/rtc-sa1100.c
+++ b/drivers/rtc/rtc-sa1100.c
@@ -275,18 +275,10 @@ static int sa1100_rtc_probe(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
- if (IS_ENABLED(CONFIG_ARCH_SA1100) ||
- of_device_is_compatible(pdev->dev.of_node, "mrvl,sa1100-rtc")) {
- info->rcnr = base + 0x04;
- info->rtsr = base + 0x10;
- info->rtar = base + 0x00;
- info->rttr = base + 0x08;
- } else {
- info->rcnr = base + 0x0;
- info->rtsr = base + 0x8;
- info->rtar = base + 0x4;
- info->rttr = base + 0xc;
- }
+ info->rcnr = base + 0x0;
+ info->rtsr = base + 0x8;
+ info->rtar = base + 0x4;
+ info->rttr = base + 0xc;
platform_set_drvdata(pdev, info);
device_init_wakeup(&pdev->dev, true);
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index f7d0a0c2c0ef..0ab0dcc6d27d 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -614,16 +614,16 @@ config S3C2410_WATCHDOG
be called s3c2410_wdt.
config SA1100_WATCHDOG
- tristate "SA1100/PXA2xx watchdog"
- depends on ARCH_SA1100 || ARCH_PXA || COMPILE_TEST
+ tristate "PXA2xx watchdog"
+ depends on ARCH_PXA || COMPILE_TEST
help
- Watchdog timer embedded into SA11x0 and PXA2xx chips. This will
- reboot your system when timeout is reached.
+ Watchdog timer embedded PXA2xx chips. This will reboot your
+ system when timeout is reached.
NOTE: once enabled, this timer cannot be disabled.
- To compile this driver as a module, choose M here: the
- module will be called sa1100_wdt.
+ To compile this driver as a module, choose M here: the module
+ will be called sa1100_wdt.
config DW_WATCHDOG
tristate "Synopsys DesignWare watchdog"
--
2.53.0
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 01/13] ARM: remove sa1100 platform
2026-09-08 15:27 ` [PATCH 01/13] ARM: remove sa1100 platform Arnd Bergmann
@ 2026-09-08 16:26 ` Guenter Roeck
2026-09-08 17:23 ` Linus Walleij
` (2 subsequent siblings)
3 siblings, 0 replies; 70+ messages in thread
From: Guenter Roeck @ 2026-09-08 16:26 UTC (permalink / raw)
To: Arnd Bergmann, Krzysztof Kozlowski, Alexandre Belloni,
Linus Walleij, Russell King
Cc: Arnd Bergmann, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap
On 9/8/26 08:27, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> Most sa1100 platforms were removed a few years, with the remaining
> ones left as a starting point for a conversion to devicetree.
>
> Nothing ever happened on that front, so remove the rest now,
> including the sa1111 and locomo drivers that were once shared
> with pxa but are already sa1100-exclusive now.
>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Linus Walleij <linusw@kernel.org>
> Cc: Kristoffer Ericson <kristoffer.ericson@gmail.com>
> Cc: Guenter Roeck <linux@roeck-us.net>
> Cc: Ethan Nelson-Moore <enelsonmoore@gmail.com>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
Acked-by: Guenter Roeck <linux@roeck-us.net>
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 01/13] ARM: remove sa1100 platform
2026-09-08 15:27 ` [PATCH 01/13] ARM: remove sa1100 platform Arnd Bergmann
2026-09-08 16:26 ` Guenter Roeck
@ 2026-09-08 17:23 ` Linus Walleij
2026-09-08 19:39 ` Karl Mehltretter
2026-09-08 20:36 ` Nicolas Pitre
3 siblings, 0 replies; 70+ messages in thread
From: Linus Walleij @ 2026-09-08 17:23 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Russell King,
Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Guenter Roeck
On Tue, Sep 8, 2026 at 5:28 PM Arnd Bergmann <arnd@kernel.org> wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> Most sa1100 platforms were removed a few years, with the remaining
> ones left as a starting point for a conversion to devicetree.
>
> Nothing ever happened on that front, so remove the rest now,
> including the sa1111 and locomo drivers that were once shared
> with pxa but are already sa1100-exclusive now.
>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Linus Walleij <linusw@kernel.org>
> Cc: Kristoffer Ericson <kristoffer.ericson@gmail.com>
> Cc: Guenter Roeck <linux@roeck-us.net>
> Cc: Ethan Nelson-Moore <enelsonmoore@gmail.com>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linusw@kernel.org>
If some user really want to keep this platform around and it
willing to invest time in testing, I do not think it is hard to
convert it to device tree using an LLM.
But if there are no users, away it goes.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 01/13] ARM: remove sa1100 platform
2026-09-08 15:27 ` [PATCH 01/13] ARM: remove sa1100 platform Arnd Bergmann
2026-09-08 16:26 ` Guenter Roeck
2026-09-08 17:23 ` Linus Walleij
@ 2026-09-08 19:39 ` Karl Mehltretter
2026-09-08 20:09 ` Arnd Bergmann
2026-09-08 20:36 ` Nicolas Pitre
3 siblings, 1 reply; 70+ messages in thread
From: Karl Mehltretter @ 2026-09-08 19:39 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Arnd Bergmann, Rob Herring,
Conor Dooley, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Guenter Roeck
On Tue, Sep 08, 2026 at 05:27:51PM +0100, Arnd Bergmann wrote:
> 62 files changed, 19 insertions(+), 10501 deletions(-)
Note that Sashiko skipped reviewing this patch, because it exceeded
its current 10000 line limit.
> diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c
> @@ -275,18 +275,10 @@ static int sa1100_rtc_probe(struct platform_device *pdev)
> - if (IS_ENABLED(CONFIG_ARCH_SA1100) ||
> - of_device_is_compatible(pdev->dev.of_node, "mrvl,sa1100-rtc")) {
> - info->rcnr = base + 0x04;
> - info->rtsr = base + 0x10;
> - info->rtar = base + 0x00;
> - info->rttr = base + 0x08;
> - } else {
> - info->rcnr = base + 0x0;
> - info->rtsr = base + 0x8;
> - info->rtar = base + 0x4;
> - info->rttr = base + 0xc;
> - }
> + info->rcnr = base + 0x0;
> + info->rtsr = base + 0x8;
> + info->rtar = base + 0x4;
> + info->rttr = base + 0xc;
This drops the layout switch but keeps "mrvl,sa1100-rtc" in
sa1100_rtc_dt_ids[] and in bindings/rtc/sa1100-rtc.yaml, so a DT with
that compatible would now silently get the MMP register offsets instead
of the SA1100 ones.
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> @@ -614,16 +614,16 @@ config S3C2410_WATCHDOG
> be called s3c2410_wdt.
>
> config SA1100_WATCHDOG
> - tristate "SA1100/PXA2xx watchdog"
> - depends on ARCH_SA1100 || ARCH_PXA || COMPILE_TEST
> + tristate "PXA2xx watchdog"
> + depends on ARCH_PXA || COMPILE_TEST
> help
> - Watchdog timer embedded into SA11x0 and PXA2xx chips. This will
> - reboot your system when timeout is reached.
> + Watchdog timer embedded PXA2xx chips. This will reboot your
> + system when timeout is reached.
>
"embedded into PXA2xx chips" is better.
The RTC_DRV_SA1100 help text a bit earlier in the patch also still says
"built into your SA11x0 or PXA2xx CPU".
Thanks,
Karl
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 01/13] ARM: remove sa1100 platform
2026-09-08 19:39 ` Karl Mehltretter
@ 2026-09-08 20:09 ` Arnd Bergmann
0 siblings, 0 replies; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 20:09 UTC (permalink / raw)
To: Karl Mehltretter, Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, A. Sverdlin, Shawn Guo,
David Hildenbrand (Red Hat),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, Linux-OMAP, Guenter Roeck
On Tue, Sep 8, 2026, at 21:39, Karl Mehltretter wrote:
> On Tue, Sep 08, 2026 at 05:27:51PM +0100, Arnd Bergmann wrote:
>> 62 files changed, 19 insertions(+), 10501 deletions(-)
>
> Note that Sashiko skipped reviewing this patch, because it exceeded
> its current 10000 line limit.
>
>> diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c
>> @@ -275,18 +275,10 @@ static int sa1100_rtc_probe(struct platform_device *pdev)
>> - if (IS_ENABLED(CONFIG_ARCH_SA1100) ||
>> - of_device_is_compatible(pdev->dev.of_node, "mrvl,sa1100-rtc")) {
>> - info->rcnr = base + 0x04;
>> - info->rtsr = base + 0x10;
>> - info->rtar = base + 0x00;
>> - info->rttr = base + 0x08;
>> - } else {
>> - info->rcnr = base + 0x0;
>> - info->rtsr = base + 0x8;
>> - info->rtar = base + 0x4;
>> - info->rttr = base + 0xc;
>> - }
>> + info->rcnr = base + 0x0;
>> + info->rtsr = base + 0x8;
>> + info->rtar = base + 0x4;
>> + info->rttr = base + 0xc;
>
> This drops the layout switch but keeps "mrvl,sa1100-rtc" in
> sa1100_rtc_dt_ids[] and in bindings/rtc/sa1100-rtc.yaml, so a DT with
> that compatible would now silently get the MMP register offsets instead
> of the SA1100 ones.
This one is interesting: this was already the behavior before
my patch, as CONFIG_ARCH_SA1100 is mutually exclusive with all
other targets. That obviously wasn't the intention of the code.
I've removed the sa1100_rtc_dt_ids[] entry now.
>> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
>> @@ -614,16 +614,16 @@ config S3C2410_WATCHDOG
>> be called s3c2410_wdt.
>>
>> config SA1100_WATCHDOG
>> - tristate "SA1100/PXA2xx watchdog"
>> - depends on ARCH_SA1100 || ARCH_PXA || COMPILE_TEST
>> + tristate "PXA2xx watchdog"
>> + depends on ARCH_PXA || COMPILE_TEST
>> help
>> - Watchdog timer embedded into SA11x0 and PXA2xx chips. This will
>> - reboot your system when timeout is reached.
>> + Watchdog timer embedded PXA2xx chips. This will reboot your
>> + system when timeout is reached.
>>
>
> "embedded into PXA2xx chips" is better.
>
> The RTC_DRV_SA1100 help text a bit earlier in the patch also still says
> "built into your SA11x0 or PXA2xx CPU".
Fixed all these now, thanks for the review!
Arnd
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 01/13] ARM: remove sa1100 platform
2026-09-08 15:27 ` [PATCH 01/13] ARM: remove sa1100 platform Arnd Bergmann
` (2 preceding siblings ...)
2026-09-08 19:39 ` Karl Mehltretter
@ 2026-09-08 20:36 ` Nicolas Pitre
2026-09-08 21:26 ` David Laight
2026-09-08 21:32 ` Arnd Bergmann
3 siblings, 2 replies; 70+ messages in thread
From: Nicolas Pitre @ 2026-09-08 20:36 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Arnd Bergmann, Rob Herring,
Conor Dooley, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
linux-doc, linux-kernel, linux-arm-kernel, devicetree, imx,
linux-stm32, linux-omap, Guenter Roeck
On Tue, 8 Sep 2026, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> Most sa1100 platforms were removed a few years, with the remaining
> ones left as a starting point for a conversion to devicetree.
>
> Nothing ever happened on that front, so remove the rest now,
> including the sa1111 and locomo drivers that were once shared
> with pxa but are already sa1100-exclusive now.
The SA1100 was the starting point of my career. Feels strange how much
time has passed.
I parted with such hardware a long time ago in any case.
Acked-by: Nicolas Pitre <nico@fluxnic.net>
>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Linus Walleij <linusw@kernel.org>
> Cc: Kristoffer Ericson <kristoffer.ericson@gmail.com>
> Cc: Guenter Roeck <linux@roeck-us.net>
> Cc: Ethan Nelson-Moore <enelsonmoore@gmail.com>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> Documentation/arch/arm/index.rst | 3 -
> Documentation/arch/arm/sa1100/assabet.rst | 301 ---
> Documentation/arch/arm/sa1100/cerf.rst | 35 -
> Documentation/arch/arm/sa1100/index.rst | 13 -
> Documentation/arch/arm/sa1100/lart.rst | 15 -
> Documentation/arch/arm/sa1100/serial_uart.rst | 51 -
> MAINTAINERS | 8 -
> arch/arm/Kconfig | 16 +-
> arch/arm/Kconfig.debug | 13 +-
> arch/arm/Makefile | 6 -
> arch/arm/boot/bootp/Makefile | 1 -
> arch/arm/boot/compressed/Makefile | 4 -
> arch/arm/boot/compressed/head-sa1100.S | 45 -
> arch/arm/boot/compressed/head.S | 7 -
> arch/arm/common/Kconfig | 7 -
> arch/arm/common/Makefile | 2 -
> arch/arm/common/locomo.c | 886 --------
> arch/arm/common/sa1111.c | 1413 -------------
> arch/arm/configs/assabet_defconfig | 57 -
> arch/arm/configs/collie_defconfig | 87 -
> arch/arm/configs/h3600_defconfig | 63 -
> arch/arm/configs/jornada720_defconfig | 95 -
> arch/arm/configs/neponset_defconfig | 88 -
> arch/arm/include/asm/cputype.h | 4 -
> arch/arm/include/asm/hardware/locomo.h | 217 --
> arch/arm/include/asm/hardware/sa1111.h | 442 ----
> arch/arm/include/asm/hardware/ssp.h | 25 -
> arch/arm/include/debug/sa1100.S | 67 -
> arch/arm/mach-sa1100/Kconfig | 92 -
> arch/arm/mach-sa1100/Makefile | 20 -
> arch/arm/mach-sa1100/assabet.c | 770 -------
> arch/arm/mach-sa1100/clock.c | 145 --
> arch/arm/mach-sa1100/collie.c | 447 ----
> arch/arm/mach-sa1100/generic.c | 470 -----
> arch/arm/mach-sa1100/generic.h | 58 -
> arch/arm/mach-sa1100/h3600.c | 134 --
> arch/arm/mach-sa1100/h3xxx.c | 305 ---
> arch/arm/mach-sa1100/include/mach/SA-1100.h | 1798 -----------------
> arch/arm/mach-sa1100/include/mach/assabet.h | 99 -
> arch/arm/mach-sa1100/include/mach/bitfield.h | 113 --
> arch/arm/mach-sa1100/include/mach/collie.h | 94 -
> arch/arm/mach-sa1100/include/mach/generic.h | 1 -
> arch/arm/mach-sa1100/include/mach/h3xxx.h | 81 -
> arch/arm/mach-sa1100/include/mach/hardware.h | 56 -
> arch/arm/mach-sa1100/include/mach/irqs.h | 101 -
> .../arm/mach-sa1100/include/mach/jornada720.h | 28 -
> arch/arm/mach-sa1100/include/mach/memory.h | 37 -
> arch/arm/mach-sa1100/include/mach/mtd-xip.h | 23 -
> arch/arm/mach-sa1100/include/mach/neponset.h | 31 -
> arch/arm/mach-sa1100/include/mach/reset.h | 18 -
> .../arm/mach-sa1100/include/mach/uncompress.h | 52 -
> arch/arm/mach-sa1100/jornada720.c | 380 ----
> arch/arm/mach-sa1100/jornada720_ssp.c | 202 --
> arch/arm/mach-sa1100/neponset.c | 438 ----
> arch/arm/mach-sa1100/pm.c | 128 --
> arch/arm/mach-sa1100/sleep.S | 143 --
> arch/arm/mach-sa1100/ssp.c | 240 ---
> arch/arm/mm/init.c | 5 -
> arch/arm/mm/mmu.c | 8 -
> drivers/rtc/Kconfig | 4 +-
> drivers/rtc/rtc-sa1100.c | 16 +-
> drivers/watchdog/Kconfig | 12 +-
> 62 files changed, 19 insertions(+), 10501 deletions(-)
> delete mode 100644 Documentation/arch/arm/sa1100/assabet.rst
> delete mode 100644 Documentation/arch/arm/sa1100/cerf.rst
> delete mode 100644 Documentation/arch/arm/sa1100/index.rst
> delete mode 100644 Documentation/arch/arm/sa1100/lart.rst
> delete mode 100644 Documentation/arch/arm/sa1100/serial_uart.rst
> delete mode 100644 arch/arm/boot/compressed/head-sa1100.S
> delete mode 100644 arch/arm/common/locomo.c
> delete mode 100644 arch/arm/common/sa1111.c
> delete mode 100644 arch/arm/configs/assabet_defconfig
> delete mode 100644 arch/arm/configs/collie_defconfig
> delete mode 100644 arch/arm/configs/h3600_defconfig
> delete mode 100644 arch/arm/configs/jornada720_defconfig
> delete mode 100644 arch/arm/configs/neponset_defconfig
> delete mode 100644 arch/arm/include/asm/hardware/locomo.h
> delete mode 100644 arch/arm/include/asm/hardware/sa1111.h
> delete mode 100644 arch/arm/include/asm/hardware/ssp.h
> delete mode 100644 arch/arm/include/debug/sa1100.S
> delete mode 100644 arch/arm/mach-sa1100/Kconfig
> delete mode 100644 arch/arm/mach-sa1100/Makefile
> delete mode 100644 arch/arm/mach-sa1100/assabet.c
> delete mode 100644 arch/arm/mach-sa1100/clock.c
> delete mode 100644 arch/arm/mach-sa1100/collie.c
> delete mode 100644 arch/arm/mach-sa1100/generic.c
> delete mode 100644 arch/arm/mach-sa1100/generic.h
> delete mode 100644 arch/arm/mach-sa1100/h3600.c
> delete mode 100644 arch/arm/mach-sa1100/h3xxx.c
> delete mode 100644 arch/arm/mach-sa1100/include/mach/SA-1100.h
> delete mode 100644 arch/arm/mach-sa1100/include/mach/assabet.h
> delete mode 100644 arch/arm/mach-sa1100/include/mach/bitfield.h
> delete mode 100644 arch/arm/mach-sa1100/include/mach/collie.h
> delete mode 100644 arch/arm/mach-sa1100/include/mach/generic.h
> delete mode 100644 arch/arm/mach-sa1100/include/mach/h3xxx.h
> delete mode 100644 arch/arm/mach-sa1100/include/mach/hardware.h
> delete mode 100644 arch/arm/mach-sa1100/include/mach/irqs.h
> delete mode 100644 arch/arm/mach-sa1100/include/mach/jornada720.h
> delete mode 100644 arch/arm/mach-sa1100/include/mach/memory.h
> delete mode 100644 arch/arm/mach-sa1100/include/mach/mtd-xip.h
> delete mode 100644 arch/arm/mach-sa1100/include/mach/neponset.h
> delete mode 100644 arch/arm/mach-sa1100/include/mach/reset.h
> delete mode 100644 arch/arm/mach-sa1100/include/mach/uncompress.h
> delete mode 100644 arch/arm/mach-sa1100/jornada720.c
> delete mode 100644 arch/arm/mach-sa1100/jornada720_ssp.c
> delete mode 100644 arch/arm/mach-sa1100/neponset.c
> delete mode 100644 arch/arm/mach-sa1100/pm.c
> delete mode 100644 arch/arm/mach-sa1100/sleep.S
> delete mode 100644 arch/arm/mach-sa1100/ssp.c
>
> diff --git a/Documentation/arch/arm/index.rst b/Documentation/arch/arm/index.rst
> index b15621093f7a..a292b8ac41ce 100644
> --- a/Documentation/arch/arm/index.rst
> +++ b/Documentation/arch/arm/index.rst
> @@ -48,9 +48,6 @@ SoC-specific documents
>
> pxa/mfp
>
> -
> - sa1100/index
> -
> stm32/stm32f746-overview
> stm32/overview
> stm32/stm32h743-overview
> diff --git a/Documentation/arch/arm/sa1100/assabet.rst b/Documentation/arch/arm/sa1100/assabet.rst
> deleted file mode 100644
> index a761e128fb08..000000000000
> --- a/Documentation/arch/arm/sa1100/assabet.rst
> +++ /dev/null
> @@ -1,301 +0,0 @@
> -============================================
> -The Intel Assabet (SA-1110 evaluation) board
> -============================================
> -
> -Please see:
> -http://developer.intel.com
> -
> -Also some notes from John G Dorsey <jd5q@andrew.cmu.edu>:
> -http://www.cs.cmu.edu/~wearable/software/assabet.html
> -
> -
> -Building the kernel
> --------------------
> -
> -To build the kernel with current defaults::
> -
> - make assabet_defconfig
> - make oldconfig
> - make zImage
> -
> -The resulting kernel image should be available in linux/arch/arm/boot/zImage.
> -
> -
> -Installing a bootloader
> ------------------------
> -
> -A couple of bootloaders able to boot Linux on Assabet are available:
> -
> -BLOB (http://www.lartmaker.nl/lartware/blob/)
> -
> - BLOB is a bootloader used within the LART project. Some contributed
> - patches were merged into BLOB to add support for Assabet.
> -
> -Compaq's Bootldr + John Dorsey's patch for Assabet support
> -(http://www.handhelds.org/Compaq/bootldr.html)
> -(http://www.wearablegroup.org/software/bootldr/)
> -
> - Bootldr is the bootloader developed by Compaq for the iPAQ Pocket PC.
> - John Dorsey has produced add-on patches to add support for Assabet and
> - the JFFS filesystem.
> -
> -RedBoot (http://sources.redhat.com/redboot/)
> -
> - RedBoot is a bootloader developed by Red Hat based on the eCos RTOS
> - hardware abstraction layer. It supports Assabet amongst many other
> - hardware platforms.
> -
> -RedBoot is currently the recommended choice since it's the only one to have
> -networking support, and is the most actively maintained.
> -
> -Brief examples on how to boot Linux with RedBoot are shown below. But first
> -you need to have RedBoot installed in your flash memory. A known to work
> -precompiled RedBoot binary is available from the following location:
> -
> -- ftp://ftp.netwinder.org/users/n/nico/
> -- ftp://ftp.arm.linux.org.uk/pub/linux/arm/people/nico/
> -- ftp://ftp.handhelds.org/pub/linux/arm/sa-1100-patches/
> -
> -Look for redboot-assabet*.tgz. Some installation infos are provided in
> -redboot-assabet*.txt.
> -
> -
> -Initial RedBoot configuration
> ------------------------------
> -
> -The commands used here are explained in The RedBoot User's Guide available
> -on-line at http://sources.redhat.com/ecos/docs.html.
> -Please refer to it for explanations.
> -
> -If you have a CF network card (my Assabet kit contained a CF+ LP-E from
> -Socket Communications Inc.), you should strongly consider using it for TFTP
> -file transfers. You must insert it before RedBoot runs since it can't detect
> -it dynamically.
> -
> -To initialize the flash directory::
> -
> - fis init -f
> -
> -To initialize the non-volatile settings, like whether you want to use BOOTP or
> -a static IP address, etc, use this command::
> -
> - fconfig -i
> -
> -
> -Writing a kernel image into flash
> ----------------------------------
> -
> -First, the kernel image must be loaded into RAM. If you have the zImage file
> -available on a TFTP server::
> -
> - load zImage -r -b 0x100000
> -
> -If you rather want to use Y-Modem upload over the serial port::
> -
> - load -m ymodem -r -b 0x100000
> -
> -To write it to flash::
> -
> - fis create "Linux kernel" -b 0x100000 -l 0xc0000
> -
> -
> -Booting the kernel
> -------------------
> -
> -The kernel still requires a filesystem to boot. A ramdisk image can be loaded
> -as follows::
> -
> - load ramdisk_image.gz -r -b 0x800000
> -
> -Again, Y-Modem upload can be used instead of TFTP by replacing the file name
> -by '-y ymodem'.
> -
> -Now the kernel can be retrieved from flash like this::
> -
> - fis load "Linux kernel"
> -
> -or loaded as described previously. To boot the kernel::
> -
> - exec -b 0x100000 -l 0xc0000
> -
> -The ramdisk image could be stored into flash as well, but there are better
> -solutions for on-flash filesystems as mentioned below.
> -
> -
> -Using JFFS2
> ------------
> -
> -Using JFFS2 (the Second Journalling Flash File System) is probably the most
> -convenient way to store a writable filesystem into flash. JFFS2 is used in
> -conjunction with the MTD layer which is responsible for low-level flash
> -management. More information on the Linux MTD can be found on-line at:
> -http://www.linux-mtd.infradead.org/. A JFFS howto with some infos about
> -creating JFFS/JFFS2 images is available from the same site.
> -
> -For instance, a sample JFFS2 image can be retrieved from the same FTP sites
> -mentioned below for the precompiled RedBoot image.
> -
> -To load this file::
> -
> - load sample_img.jffs2 -r -b 0x100000
> -
> -The result should look like::
> -
> - RedBoot> load sample_img.jffs2 -r -b 0x100000
> - Raw file loaded 0x00100000-0x00377424
> -
> -Now we must know the size of the unallocated flash::
> -
> - fis free
> -
> -Result::
> -
> - RedBoot> fis free
> - 0x500E0000 .. 0x503C0000
> -
> -The values above may be different depending on the size of the filesystem and
> -the type of flash. See their usage below as an example and take care of
> -substituting yours appropriately.
> -
> -We must determine some values::
> -
> - size of unallocated flash: 0x503c0000 - 0x500e0000 = 0x2e0000
> - size of the filesystem image: 0x00377424 - 0x00100000 = 0x277424
> -
> -We want to fit the filesystem image of course, but we also want to give it all
> -the remaining flash space as well. To write it::
> -
> - fis unlock -f 0x500E0000 -l 0x2e0000
> - fis erase -f 0x500E0000 -l 0x2e0000
> - fis write -b 0x100000 -l 0x277424 -f 0x500E0000
> - fis create "JFFS2" -n -f 0x500E0000 -l 0x2e0000
> -
> -Now the filesystem is associated to a MTD "partition" once Linux has discovered
> -what they are in the boot process. From Redboot, the 'fis list' command
> -displays them::
> -
> - RedBoot> fis list
> - Name FLASH addr Mem addr Length Entry point
> - RedBoot 0x50000000 0x50000000 0x00020000 0x00000000
> - RedBoot config 0x503C0000 0x503C0000 0x00020000 0x00000000
> - FIS directory 0x503E0000 0x503E0000 0x00020000 0x00000000
> - Linux kernel 0x50020000 0x00100000 0x000C0000 0x00000000
> - JFFS2 0x500E0000 0x500E0000 0x002E0000 0x00000000
> -
> -However Linux should display something like::
> -
> - SA1100 flash: probing 32-bit flash bus
> - SA1100 flash: Found 2 x16 devices at 0x0 in 32-bit mode
> - Using RedBoot partition definition
> - Creating 5 MTD partitions on "SA1100 flash":
> - 0x00000000-0x00020000 : "RedBoot"
> - 0x00020000-0x000e0000 : "Linux kernel"
> - 0x000e0000-0x003c0000 : "JFFS2"
> - 0x003c0000-0x003e0000 : "RedBoot config"
> - 0x003e0000-0x00400000 : "FIS directory"
> -
> -What's important here is the position of the partition we are interested in,
> -which is the third one. Within Linux, this correspond to /dev/mtdblock2.
> -Therefore to boot Linux with the kernel and its root filesystem in flash, we
> -need this RedBoot command::
> -
> - fis load "Linux kernel"
> - exec -b 0x100000 -l 0xc0000 -c "root=/dev/mtdblock2"
> -
> -Of course other filesystems than JFFS might be used, like cramfs for example.
> -You might want to boot with a root filesystem over NFS, etc. It is also
> -possible, and sometimes more convenient, to flash a filesystem directly from
> -within Linux while booted from a ramdisk or NFS. The Linux MTD repository has
> -many tools to deal with flash memory as well, to erase it for example. JFFS2
> -can then be mounted directly on a freshly erased partition and files can be
> -copied over directly. Etc...
> -
> -
> -RedBoot scripting
> ------------------
> -
> -All the commands above aren't so useful if they have to be typed in every
> -time the Assabet is rebooted. Therefore it's possible to automate the boot
> -process using RedBoot's scripting capability.
> -
> -For example, I use this to boot Linux with both the kernel and the ramdisk
> -images retrieved from a TFTP server on the network::
> -
> - RedBoot> fconfig
> - Run script at boot: false true
> - Boot script:
> - Enter script, terminate with empty line
> - >> load zImage -r -b 0x100000
> - >> load ramdisk_ks.gz -r -b 0x800000
> - >> exec -b 0x100000 -l 0xc0000
> - >>
> - Boot script timeout (1000ms resolution): 3
> - Use BOOTP for network configuration: true
> - GDB connection port: 9000
> - Network debug at boot time: false
> - Update RedBoot non-volatile configuration - are you sure (y/n)? y
> -
> -Then, rebooting the Assabet is just a matter of waiting for the login prompt.
> -
> -
> -
> -Nicolas Pitre
> -nico@fluxnic.net
> -
> -June 12, 2001
> -
> -
> -Status of peripherals in -rmk tree (updated 14/10/2001)
> --------------------------------------------------------
> -
> -Assabet:
> - Serial ports:
> - Radio: TX, RX, CTS, DSR, DCD, RI
> - - PM: Not tested.
> - - COM: TX, RX, CTS, DSR, DCD, RTS, DTR, PM
> - - PM: Not tested.
> - - I2C: Implemented, not fully tested.
> - - L3: Fully tested, pass.
> - - PM: Not tested.
> -
> - Video:
> - - LCD: Fully tested. PM
> -
> - (LCD doesn't like being blanked with neponset connected)
> -
> - - Video out: Not fully
> -
> - Audio:
> - UDA1341:
> - - Playback: Fully tested, pass.
> - - Record: Implemented, not tested.
> - - PM: Not tested.
> -
> - UCB1200:
> - - Audio play: Implemented, not heavily tested.
> - - Audio rec: Implemented, not heavily tested.
> - - Telco audio play: Implemented, not heavily tested.
> - - Telco audio rec: Implemented, not heavily tested.
> - - POTS control: No
> - - Touchscreen: Yes
> - - PM: Not tested.
> -
> - Other:
> - - PCMCIA:
> - - LPE: Fully tested, pass.
> - - USB: No
> - - IRDA:
> - - SIR: Fully tested, pass.
> - - FIR: Fully tested, pass.
> - - PM: Not tested.
> -
> -Neponset:
> - Serial ports:
> - - COM1,2: TX, RX, CTS, DSR, DCD, RTS, DTR
> - - PM: Not tested.
> - - USB: Implemented, not heavily tested.
> - - PCMCIA: Implemented, not heavily tested.
> - - CF: Implemented, not heavily tested.
> - - PM: Not tested.
> -
> -More stuff can be found in the -np (Nicolas Pitre's) tree.
> diff --git a/Documentation/arch/arm/sa1100/cerf.rst b/Documentation/arch/arm/sa1100/cerf.rst
> deleted file mode 100644
> index 7fa71b609bf9..000000000000
> --- a/Documentation/arch/arm/sa1100/cerf.rst
> +++ /dev/null
> @@ -1,35 +0,0 @@
> -==============
> -CerfBoard/Cube
> -==============
> -
> -*** The StrongARM version of the CerfBoard/Cube has been discontinued ***
> -
> -The Intrinsyc CerfBoard is a StrongARM 1110-based computer on a board
> -that measures approximately 2" square. It includes an Ethernet
> -controller, an RS232-compatible serial port, a USB function port, and
> -one CompactFlash+ slot on the back. Pictures can be found at the
> -Intrinsyc website, http://www.intrinsyc.com.
> -
> -This document describes the support in the Linux kernel for the
> -Intrinsyc CerfBoard.
> -
> -Supported in this version
> -=========================
> -
> - - CompactFlash+ slot (select PCMCIA in General Setup and any options
> - that may be required)
> - - Onboard Crystal CS8900 Ethernet controller (Cerf CS8900A support in
> - Network Devices)
> - - Serial ports with a serial console (hardcoded to 38400 8N1)
> -
> -In order to get this kernel onto your Cerf, you need a server that runs
> -both BOOTP and TFTP. Detailed instructions should have come with your
> -evaluation kit on how to use the bootloader. This series of commands
> -will suffice::
> -
> - make ARCH=arm CROSS_COMPILE=arm-linux- cerfcube_defconfig
> - make ARCH=arm CROSS_COMPILE=arm-linux- zImage
> - make ARCH=arm CROSS_COMPILE=arm-linux- modules
> - cp arch/arm/boot/zImage <TFTP directory>
> -
> -support@intrinsyc.com
> diff --git a/Documentation/arch/arm/sa1100/index.rst b/Documentation/arch/arm/sa1100/index.rst
> deleted file mode 100644
> index c9aed43280ff..000000000000
> --- a/Documentation/arch/arm/sa1100/index.rst
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -.. SPDX-License-Identifier: GPL-2.0
> -
> -====================
> -Intel StrongARM 1100
> -====================
> -
> -.. toctree::
> - :maxdepth: 1
> -
> - assabet
> - cerf
> - lart
> - serial_uart
> diff --git a/Documentation/arch/arm/sa1100/lart.rst b/Documentation/arch/arm/sa1100/lart.rst
> deleted file mode 100644
> index 94c0568d1095..000000000000
> --- a/Documentation/arch/arm/sa1100/lart.rst
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -====================================
> -Linux Advanced Radio Terminal (LART)
> -====================================
> -
> -The LART is a small (7.5 x 10cm) SA-1100 board, designed for embedded
> -applications. It has 32 MB DRAM, 4MB Flash ROM, double RS232 and all
> -other StrongARM-gadgets. Almost all SA signals are directly accessible
> -through a number of connectors. The powersupply accepts voltages
> -between 3.5V and 16V and is overdimensioned to support a range of
> -daughterboards. A quad Ethernet / IDE / PS2 / sound daughterboard
> -is under development, with plenty of others in different stages of
> -planning.
> -
> -The hardware designs for this board have been released under an open license;
> -see the LART page at http://www.lartmaker.nl/ for more information.
> diff --git a/Documentation/arch/arm/sa1100/serial_uart.rst b/Documentation/arch/arm/sa1100/serial_uart.rst
> deleted file mode 100644
> index ea983642b9be..000000000000
> --- a/Documentation/arch/arm/sa1100/serial_uart.rst
> +++ /dev/null
> @@ -1,51 +0,0 @@
> -==================
> -SA1100 serial port
> -==================
> -
> -The SA1100 serial port had its major/minor numbers officially assigned::
> -
> - > Date: Sun, 24 Sep 2000 21:40:27 -0700
> - > From: H. Peter Anvin <hpa@transmeta.com>
> - > To: Nicolas Pitre <nico@CAM.ORG>
> - > Cc: Device List Maintainer <device@lanana.org>
> - > Subject: Re: device
> - >
> - > Okay. Note that device numbers 204 and 205 are used for "low density
> - > serial devices", so you will have a range of minors on those majors (the
> - > tty device layer handles this just fine, so you don't have to worry about
> - > doing anything special.)
> - >
> - > So your assignments are:
> - >
> - > 204 char Low-density serial ports
> - > 5 = /dev/ttySA0 SA1100 builtin serial port 0
> - > 6 = /dev/ttySA1 SA1100 builtin serial port 1
> - > 7 = /dev/ttySA2 SA1100 builtin serial port 2
> - >
> - > 205 char Low-density serial ports (alternate device)
> - > 5 = /dev/cusa0 Callout device for ttySA0
> - > 6 = /dev/cusa1 Callout device for ttySA1
> - > 7 = /dev/cusa2 Callout device for ttySA2
> - >
> -
> -You must create those inodes in /dev on the root filesystem used
> -by your SA1100-based device::
> -
> - mknod ttySA0 c 204 5
> - mknod ttySA1 c 204 6
> - mknod ttySA2 c 204 7
> - mknod cusa0 c 205 5
> - mknod cusa1 c 205 6
> - mknod cusa2 c 205 7
> -
> -In addition to the creation of the appropriate device nodes above, you
> -must ensure your user space applications make use of the correct device
> -name. The classic example is the content of the /etc/inittab file where
> -you might have a getty process started on ttyS0.
> -
> -In this case:
> -
> -- replace occurrences of ttyS0 with ttySA0, ttyS1 with ttySA1, etc.
> -
> -- don't forget to add 'ttySA0', 'console', or the appropriate tty name
> - in /etc/securetty for root to be allowed to login as well.
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 6215fcb07770..fd213c4bc257 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2977,14 +2977,6 @@ F: arch/arm/boot/dts/hisilicon/
> F: arch/arm/mach-hisi/
> F: arch/arm64/boot/dts/hisilicon/
>
> -ARM/HP JORNADA 7XX MACHINE SUPPORT
> -M: Kristoffer Ericson <kristoffer.ericson@gmail.com>
> -S: Maintained
> -W: www.jlime.com
> -T: git git://git.kernel.org/pub/scm/linux/kernel/git/kristoffer/linux-hpc.git
> -F: arch/arm/mach-sa1100/include/mach/jornada720.h
> -F: arch/arm/mach-sa1100/jornada720.c
> -
> ARM/HPE GXP ARCHITECTURE
> M: Jean-Marie Verdun <verdun@hpe.com>
> M: Nick Hawkins <nick.hawkins@hpe.com>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index ffbc7f386131..7f4c2973d630 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -161,7 +161,7 @@ config ARM
> select TIMER_OF if OF
> select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
> select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
> - select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
> + select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC)
> # Above selects are sorted alphabetically; please add new ones
> # according to that. Thanks.
> help
> @@ -261,9 +261,6 @@ config GENERIC_ISA_DMA
> config FIQ
> bool
>
> -config ARCH_MTD_XIP
> - bool
> -
> config ARM_PATCH_PHYS_VIRT
> bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM
> default y
> @@ -301,7 +298,7 @@ config PHYS_OFFSET
> default 0x00000000 if ARCH_FOOTBRIDGE
> default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
> default 0xa0000000 if ARCH_PXA
> - default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
> + default 0xc0000000 if ARCH_EP93XX
> default 0
> help
> Please provide the physical address corresponding to the
> @@ -341,7 +338,7 @@ config ARCH_MMAP_RND_BITS_MAX
>
> config ARCH_MULTIPLATFORM
> bool "Require kernel to be portable to multiple machines" if EXPERT
> - depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
> + depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC)
> default y
> help
> In general, all Arm machines can be supported in a single
> @@ -445,8 +442,6 @@ source "arch/arm/mach-s3c/Kconfig"
>
> source "arch/arm/mach-s5pv210/Kconfig"
>
> -source "arch/arm/mach-sa1100/Kconfig"
> -
> source "arch/arm/mach-shmobile/Kconfig"
>
> source "arch/arm/mach-socfpga/Kconfig"
> @@ -1201,7 +1196,7 @@ config ARCH_SELECT_MEMORY_MODEL
> def_bool y
>
> config ARCH_FLATMEM_ENABLE
> - def_bool !(ARCH_RPC || ARCH_SA1100)
> + def_bool !ARCH_RPC
>
> config ARCH_SPARSEMEM_ENABLE
> def_bool !ARCH_FOOTBRIDGE
> @@ -1293,7 +1288,6 @@ config ARM_MODULE_PLTS
> config ARCH_FORCE_MAX_ORDER
> int "Order of maximal physically contiguous allocations"
> default "11" if SOC_AM33XX
> - default "8" if SA1111
> default "10"
> help
> The kernel page allocator limits the size of maximal physically
> @@ -1605,7 +1599,7 @@ config ARCH_DEFAULT_CRASH_DUMP
>
> config AUTO_ZRELADDR
> bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM
> - default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
> + default !(ARCH_FOOTBRIDGE || ARCH_RPC)
> help
> ZRELADDR is the physical address where the decompressed kernel
> image will be placed. If AUTO_ZRELADDR is selected, the address
> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index 366f162e147d..ad0feced4369 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -1048,14 +1048,6 @@ choice
> their output to UART 3. The port must have been initialised
> by the boot-loader before use.
>
> - config DEBUG_SA1100
> - depends on ARCH_SA1100
> - bool "Use SA1100 UARTs for low-level debug"
> - help
> - Say Y here if you want kernel low-level debugging support
> - on SA-11x0 UART ports. The kernel will check for the first
> - enabled UART in a sequence 3-1-2.
> -
> config DEBUG_SD5203_UART
> bool "Hisilicon SD5203 Debug UART"
> depends on ARCH_SD5203
> @@ -1479,7 +1471,6 @@ config DEBUG_UART_FLOW_CONTROL
>
> config DEBUG_LL_INCLUDE
> string
> - default "debug/sa1100.S" if DEBUG_SA1100
> default "debug/palmchip.S" if DEBUG_UART_8250_PALMCHIP
> default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250
> default "debug/at91.S" if DEBUG_AT91_UART
> @@ -1807,7 +1798,7 @@ config DEBUG_UART_8250_PALMCHIP
> config DEBUG_UNCOMPRESS
> bool "Enable decompressor debugging via DEBUG_LL output"
> depends on !ARCH_MULTIPLATFORM
> - depends on !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
> + depends on !(ARCH_FOOTBRIDGE || ARCH_RPC)
> depends on DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
> (!DEBUG_TEGRA_UART || !ZBOOT_ROM) && \
> !DEBUG_BRCMSTB_UART && !DEBUG_SEMIHOSTING
> @@ -1817,7 +1808,7 @@ config DEBUG_UNCOMPRESS
>
> config UNCOMPRESS_INCLUDE
> string
> - default "mach/uncompress.h" if ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100
> + default "mach/uncompress.h" if ARCH_FOOTBRIDGE || ARCH_RPC
> default "debug/uncompress.h"
>
> config EARLY_PRINTK
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 573813ef5e77..ea3da21202c8 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -162,10 +162,6 @@ CHECKFLAGS += -D__arm__
> textofs-y := 0x00008000
> # RTD1195 has Boot ROM at start of address space
> textofs-$(CONFIG_ARCH_REALTEK) := 0x00108000
> -# SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory
> -ifeq ($(CONFIG_ARCH_SA1100),y)
> -textofs-$(CONFIG_SA1111) := 0x00208000
> -endif
> textofs-$(CONFIG_ARCH_QCOM_RESERVE_SMEM) := 0x00208000
> textofs-$(CONFIG_ARCH_MESON) := 0x00208000
> textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
> @@ -214,7 +210,6 @@ machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
> machine-$(CONFIG_ARCH_RPC) += rpc
> machine-$(CONFIG_PLAT_SAMSUNG) += s3c
> machine-$(CONFIG_ARCH_S5PV210) += s5pv210
> -machine-$(CONFIG_ARCH_SA1100) += sa1100
> machine-$(CONFIG_ARCH_RENESAS) += shmobile
> machine-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga
> machine-$(CONFIG_ARCH_STI) += sti
> @@ -232,7 +227,6 @@ machine-$(CONFIG_PLAT_SPEAR) += spear
> # these three are mutually exclusive
> machdirs-$(CONFIG_ARCH_FOOTBRIDGE) += arch/arm/mach-footbridge
> machdirs-$(CONFIG_ARCH_RPC) += arch/arm/mach-rpc
> -machdirs-$(CONFIG_ARCH_SA1100) += arch/arm/mach-sa1100
> KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%/include,$(machdirs-y))
>
> # The byte offset of the kernel image in RAM from the start of RAM.
> diff --git a/arch/arm/boot/bootp/Makefile b/arch/arm/boot/bootp/Makefile
> index f3443f7d7b02..a1a1f4bec783 100644
> --- a/arch/arm/boot/bootp/Makefile
> +++ b/arch/arm/boot/bootp/Makefile
> @@ -20,7 +20,6 @@ PARAMS_PHYS := $(call add_hex, $(PHYS_OFFSET), 0x100)
>
> # guess an initrd location if possible
> initrd_offset-$(CONFIG_ARCH_FOOTBRIDGE) += 0x00800000
> -initrd_offset-$(CONFIG_ARCH_SA1100) += 0x00800000
> initrd_offset-$(CONFIG_ARCH_RPC) += 0x08000000
> INITRD_OFFSET := $(initrd_offset-y)
> ifdef INITRD_OFFSET
> diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
> index e3f550d62857..d8d81ba741a2 100644
> --- a/arch/arm/boot/compressed/Makefile
> +++ b/arch/arm/boot/compressed/Makefile
> @@ -29,10 +29,6 @@ ifeq ($(CONFIG_ARCH_ACORN),y)
> OBJS += ll_char_wr.o font.o
> endif
>
> -ifeq ($(CONFIG_ARCH_SA1100),y)
> -OBJS += head-sa1100.o
> -endif
> -
> ifeq ($(CONFIG_CPU_XSCALE),y)
> OBJS += head-xscale.o
> endif
> diff --git a/arch/arm/boot/compressed/head-sa1100.S b/arch/arm/boot/compressed/head-sa1100.S
> deleted file mode 100644
> index 23eae1a65064..000000000000
> --- a/arch/arm/boot/compressed/head-sa1100.S
> +++ /dev/null
> @@ -1,45 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * linux/arch/arm/boot/compressed/head-sa1100.S
> - *
> - * Copyright (C) 1999 Nicolas Pitre <nico@fluxnic.net>
> - *
> - * SA1100 specific tweaks. This is merged into head.S by the linker.
> - *
> - */
> -
> -#include <linux/linkage.h>
> -#include <asm/mach-types.h>
> -
> - .section ".start", "ax"
> - .arch armv4
> -
> -__SA1100_start:
> -
> - @ Preserve r8/r7 i.e. kernel entry values
> -#ifdef CONFIG_SA1100_COLLIE
> - mov r7, #MACH_TYPE_COLLIE
> -#endif
> - mrc p15, 0, r0, c1, c0, 0 @ read control reg
> - ands r0, r0, #0x0d
> - beq 99f
> -
> - @ Data cache might be active.
> - @ Be sure to flush kernel binary out of the cache,
> - @ whatever state it is, before it is turned off.
> - @ This is done by fetching through currently executed
> - @ memory to be sure we hit the same cache.
> - bic r2, pc, #0x1f
> - add r3, r2, #0x4000 @ 16 kb is quite enough...
> -1: ldr r0, [r2], #32
> - teq r2, r3
> - bne 1b
> - mcr p15, 0, r0, c7, c10, 4 @ drain WB
> - mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
> -
> - @ disabling MMU and caches
> - mrc p15, 0, r0, c1, c0, 0 @ read control reg
> - bic r0, r0, #0x0d @ clear WB, DC, MMU
> - bic r0, r0, #0x1000 @ clear Icache
> - mcr p15, 0, r0, c1, c0, 0
> -99:
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index 9f406e9c0ea6..845abffbc2d6 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -64,17 +64,10 @@
> busyuart \tmp, \rb
> .endm
>
> -#if defined(CONFIG_ARCH_SA1100)
> - .macro loadsp, rb, tmp1, tmp2
> - mov \rb, #0x80000000 @ physical base address
> - add \rb, \rb, #0x00010000 @ Ser1
> - .endm
> -#else
> .macro loadsp, rb, tmp1, tmp2
> addruart \rb, \tmp1, \tmp2
> .endm
> #endif
> -#endif
> #endif
>
> .macro kputc,val
> diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
> index d2fdb1796f48..d72dccf6f3c2 100644
> --- a/arch/arm/common/Kconfig
> +++ b/arch/arm/common/Kconfig
> @@ -1,14 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
> -config SA1111
> - bool
> - select ZONE_DMA if ARCH_SA1100
> -
> config KRAIT_L2_ACCESSORS
> bool
>
> -config SHARP_LOCOMO
> - bool
> -
> config SHARP_PARAM
> bool
>
> diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
> index 9733381074e0..e1bcc250874f 100644
> --- a/arch/arm/common/Makefile
> +++ b/arch/arm/common/Makefile
> @@ -5,9 +5,7 @@
>
> obj-y += firmware.o
>
> -obj-$(CONFIG_SA1111) += sa1111.o
> obj-$(CONFIG_KRAIT_L2_ACCESSORS) += krait-l2-accessors.o
> -obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
> obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
> obj-$(CONFIG_SHARP_SCOOP) += scoop.o
> obj-$(CONFIG_CPU_V7) += secure_cntvoff.o
> diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
> deleted file mode 100644
> index 55e360452828..000000000000
> --- a/arch/arm/common/locomo.c
> +++ /dev/null
> @@ -1,886 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * linux/arch/arm/common/locomo.c
> - *
> - * Sharp LoCoMo support
> - *
> - * This file contains all generic LoCoMo support.
> - *
> - * All initialization functions provided here are intended to be called
> - * from machine specific code with proper arguments when required.
> - *
> - * Based on sa1111.c
> - */
> -
> -#include <linux/module.h>
> -#include <linux/init.h>
> -#include <linux/kernel.h>
> -#include <linux/delay.h>
> -#include <linux/errno.h>
> -#include <linux/ioport.h>
> -#include <linux/platform_device.h>
> -#include <linux/slab.h>
> -#include <linux/spinlock.h>
> -#include <linux/io.h>
> -
> -#include <asm/irq.h>
> -#include <asm/mach/irq.h>
> -
> -#include <asm/hardware/locomo.h>
> -
> -/* LoCoMo Interrupts */
> -#define IRQ_LOCOMO_KEY (0)
> -#define IRQ_LOCOMO_GPIO (1)
> -#define IRQ_LOCOMO_LT (2)
> -#define IRQ_LOCOMO_SPI (3)
> -
> -/* M62332 output channel selection */
> -#define M62332_EVR_CH 1 /* M62332 volume channel number */
> - /* 0 : CH.1 , 1 : CH. 2 */
> -/* DAC send data */
> -#define M62332_SLAVE_ADDR 0x4e /* Slave address */
> -#define M62332_W_BIT 0x00 /* W bit (0 only) */
> -#define M62332_SUB_ADDR 0x00 /* Sub address */
> -#define M62332_A_BIT 0x00 /* A bit (0 only) */
> -
> -/* DAC setup and hold times (expressed in us) */
> -#define DAC_BUS_FREE_TIME 5 /* 4.7 us */
> -#define DAC_START_SETUP_TIME 5 /* 4.7 us */
> -#define DAC_STOP_SETUP_TIME 4 /* 4.0 us */
> -#define DAC_START_HOLD_TIME 5 /* 4.7 us */
> -#define DAC_SCL_LOW_HOLD_TIME 5 /* 4.7 us */
> -#define DAC_SCL_HIGH_HOLD_TIME 4 /* 4.0 us */
> -#define DAC_DATA_SETUP_TIME 1 /* 250 ns */
> -#define DAC_DATA_HOLD_TIME 1 /* 300 ns */
> -#define DAC_LOW_SETUP_TIME 1 /* 300 ns */
> -#define DAC_HIGH_SETUP_TIME 1 /* 1000 ns */
> -
> -/* the following is the overall data for the locomo chip */
> -struct locomo {
> - struct device *dev;
> - unsigned long phys;
> - unsigned int irq;
> - int irq_base;
> - spinlock_t lock;
> - void __iomem *base;
> -#ifdef CONFIG_PM
> - void *saved_state;
> -#endif
> -};
> -
> -static const struct bus_type locomo_bus_type;
> -
> -struct locomo_dev_info {
> - unsigned long offset;
> - unsigned long length;
> - unsigned int devid;
> - unsigned int irq[1];
> - const char * name;
> -};
> -
> -/* All the locomo devices. If offset is non-zero, the mapbase for the
> - * locomo_dev will be set to the chip base plus offset. If offset is
> - * zero, then the mapbase for the locomo_dev will be set to zero. An
> - * offset of zero means the device only uses GPIOs or other helper
> - * functions inside this file */
> -static struct locomo_dev_info locomo_devices[] = {
> - {
> - .devid = LOCOMO_DEVID_KEYBOARD,
> - .irq = { IRQ_LOCOMO_KEY },
> - .name = "locomo-keyboard",
> - .offset = LOCOMO_KEYBOARD,
> - .length = 16,
> - },
> - {
> - .devid = LOCOMO_DEVID_FRONTLIGHT,
> - .irq = {},
> - .name = "locomo-frontlight",
> - .offset = LOCOMO_FRONTLIGHT,
> - .length = 8,
> -
> - },
> - {
> - .devid = LOCOMO_DEVID_BACKLIGHT,
> - .irq = {},
> - .name = "locomo-backlight",
> - .offset = LOCOMO_BACKLIGHT,
> - .length = 8,
> - },
> - {
> - .devid = LOCOMO_DEVID_AUDIO,
> - .irq = {},
> - .name = "locomo-audio",
> - .offset = LOCOMO_AUDIO,
> - .length = 4,
> - },
> - {
> - .devid = LOCOMO_DEVID_LED,
> - .irq = {},
> - .name = "locomo-led",
> - .offset = LOCOMO_LED,
> - .length = 8,
> - },
> - {
> - .devid = LOCOMO_DEVID_UART,
> - .irq = {},
> - .name = "locomo-uart",
> - .offset = 0,
> - .length = 0,
> - },
> - {
> - .devid = LOCOMO_DEVID_SPI,
> - .irq = {},
> - .name = "locomo-spi",
> - .offset = LOCOMO_SPI,
> - .length = 0x30,
> - },
> -};
> -
> -static void locomo_handler(struct irq_desc *desc)
> -{
> - struct locomo *lchip = irq_desc_get_handler_data(desc);
> - int req, i;
> -
> - /* Acknowledge the parent IRQ */
> - desc->irq_data.chip->irq_ack(&desc->irq_data);
> -
> - /* check why this interrupt was generated */
> - req = locomo_readl(lchip->base + LOCOMO_ICR) & 0x0f00;
> -
> - if (req) {
> - unsigned int irq;
> -
> - /* generate the next interrupt(s) */
> - irq = lchip->irq_base;
> - for (i = 0; i <= 3; i++, irq++) {
> - if (req & (0x0100 << i)) {
> - generic_handle_irq(irq);
> - }
> -
> - }
> - }
> -}
> -
> -static void locomo_ack_irq(struct irq_data *d)
> -{
> -}
> -
> -static void locomo_mask_irq(struct irq_data *d)
> -{
> - struct locomo *lchip = irq_data_get_irq_chip_data(d);
> - unsigned int r;
> - r = locomo_readl(lchip->base + LOCOMO_ICR);
> - r &= ~(0x0010 << (d->irq - lchip->irq_base));
> - locomo_writel(r, lchip->base + LOCOMO_ICR);
> -}
> -
> -static void locomo_unmask_irq(struct irq_data *d)
> -{
> - struct locomo *lchip = irq_data_get_irq_chip_data(d);
> - unsigned int r;
> - r = locomo_readl(lchip->base + LOCOMO_ICR);
> - r |= (0x0010 << (d->irq - lchip->irq_base));
> - locomo_writel(r, lchip->base + LOCOMO_ICR);
> -}
> -
> -static struct irq_chip locomo_chip = {
> - .name = "LOCOMO",
> - .irq_ack = locomo_ack_irq,
> - .irq_mask = locomo_mask_irq,
> - .irq_unmask = locomo_unmask_irq,
> -};
> -
> -static void locomo_setup_irq(struct locomo *lchip)
> -{
> - int irq = lchip->irq_base;
> -
> - /*
> - * Install handler for IRQ_LOCOMO_HW.
> - */
> - irq_set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING);
> - irq_set_chained_handler_and_data(lchip->irq, locomo_handler, lchip);
> -
> - /* Install handlers for IRQ_LOCOMO_* */
> - for ( ; irq <= lchip->irq_base + 3; irq++) {
> - irq_set_chip_and_handler(irq, &locomo_chip, handle_level_irq);
> - irq_set_chip_data(irq, lchip);
> - irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
> - }
> -}
> -
> -
> -static void locomo_dev_release(struct device *_dev)
> -{
> - struct locomo_dev *dev = LOCOMO_DEV(_dev);
> -
> - kfree(dev);
> -}
> -
> -static int
> -locomo_init_one_child(struct locomo *lchip, struct locomo_dev_info *info)
> -{
> - struct locomo_dev *dev;
> - int ret;
> -
> - dev = kzalloc_obj(struct locomo_dev);
> - if (!dev) {
> - ret = -ENOMEM;
> - goto out;
> - }
> -
> - /*
> - * If the parent device has a DMA mask associated with it,
> - * propagate it down to the children.
> - */
> - if (lchip->dev->dma_mask) {
> - dev->dma_mask = *lchip->dev->dma_mask;
> - dev->dev.dma_mask = &dev->dma_mask;
> - }
> -
> - dev_set_name(&dev->dev, "%s", info->name);
> - dev->devid = info->devid;
> - dev->dev.parent = lchip->dev;
> - dev->dev.bus = &locomo_bus_type;
> - dev->dev.release = locomo_dev_release;
> - dev->dev.coherent_dma_mask = lchip->dev->coherent_dma_mask;
> -
> - if (info->offset)
> - dev->mapbase = lchip->base + info->offset;
> - else
> - dev->mapbase = 0;
> - dev->length = info->length;
> -
> - dev->irq[0] = (lchip->irq_base == NO_IRQ) ?
> - NO_IRQ : lchip->irq_base + info->irq[0];
> -
> - ret = device_register(&dev->dev);
> - if (ret) {
> - out:
> - kfree(dev);
> - }
> - return ret;
> -}
> -
> -#ifdef CONFIG_PM
> -
> -struct locomo_save_data {
> - u16 LCM_GPO;
> - u16 LCM_SPICT;
> - u16 LCM_GPE;
> - u16 LCM_ASD;
> - u16 LCM_SPIMD;
> -};
> -
> -static int locomo_suspend(struct platform_device *dev, pm_message_t state)
> -{
> - struct locomo *lchip = platform_get_drvdata(dev);
> - struct locomo_save_data *save;
> - unsigned long flags;
> -
> - save = kmalloc_obj(struct locomo_save_data);
> - if (!save)
> - return -ENOMEM;
> -
> - lchip->saved_state = save;
> -
> - spin_lock_irqsave(&lchip->lock, flags);
> -
> - save->LCM_GPO = locomo_readl(lchip->base + LOCOMO_GPO); /* GPIO */
> - locomo_writel(0x00, lchip->base + LOCOMO_GPO);
> - save->LCM_SPICT = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPICT); /* SPI */
> - locomo_writel(0x40, lchip->base + LOCOMO_SPI + LOCOMO_SPICT);
> - save->LCM_GPE = locomo_readl(lchip->base + LOCOMO_GPE); /* GPIO */
> - locomo_writel(0x00, lchip->base + LOCOMO_GPE);
> - save->LCM_ASD = locomo_readl(lchip->base + LOCOMO_ASD); /* ADSTART */
> - locomo_writel(0x00, lchip->base + LOCOMO_ASD);
> - save->LCM_SPIMD = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPIMD); /* SPI */
> - locomo_writel(0x3C14, lchip->base + LOCOMO_SPI + LOCOMO_SPIMD);
> -
> - locomo_writel(0x00, lchip->base + LOCOMO_PAIF);
> - locomo_writel(0x00, lchip->base + LOCOMO_DAC);
> - locomo_writel(0x00, lchip->base + LOCOMO_BACKLIGHT + LOCOMO_TC);
> -
> - if ((locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT0) & 0x88) && (locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT1) & 0x88))
> - locomo_writel(0x00, lchip->base + LOCOMO_C32K); /* CLK32 off */
> - else
> - /* 18MHz already enabled, so no wait */
> - locomo_writel(0xc1, lchip->base + LOCOMO_C32K); /* CLK32 on */
> -
> - locomo_writel(0x00, lchip->base + LOCOMO_TADC); /* 18MHz clock off*/
> - locomo_writel(0x00, lchip->base + LOCOMO_AUDIO + LOCOMO_ACC); /* 22MHz/24MHz clock off */
> - locomo_writel(0x00, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS); /* FL */
> -
> - spin_unlock_irqrestore(&lchip->lock, flags);
> -
> - return 0;
> -}
> -
> -static int locomo_resume(struct platform_device *dev)
> -{
> - struct locomo *lchip = platform_get_drvdata(dev);
> - struct locomo_save_data *save;
> - unsigned long r;
> - unsigned long flags;
> -
> - save = lchip->saved_state;
> - if (!save)
> - return 0;
> -
> - spin_lock_irqsave(&lchip->lock, flags);
> -
> - locomo_writel(save->LCM_GPO, lchip->base + LOCOMO_GPO);
> - locomo_writel(save->LCM_SPICT, lchip->base + LOCOMO_SPI + LOCOMO_SPICT);
> - locomo_writel(save->LCM_GPE, lchip->base + LOCOMO_GPE);
> - locomo_writel(save->LCM_ASD, lchip->base + LOCOMO_ASD);
> - locomo_writel(save->LCM_SPIMD, lchip->base + LOCOMO_SPI + LOCOMO_SPIMD);
> -
> - locomo_writel(0x00, lchip->base + LOCOMO_C32K);
> - locomo_writel(0x90, lchip->base + LOCOMO_TADC);
> -
> - locomo_writel(0, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KSC);
> - r = locomo_readl(lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC);
> - r &= 0xFEFF;
> - locomo_writel(r, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC);
> - locomo_writel(0x1, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KCMD);
> -
> - spin_unlock_irqrestore(&lchip->lock, flags);
> -
> - lchip->saved_state = NULL;
> - kfree(save);
> -
> - return 0;
> -}
> -#endif
> -
> -static int
> -__locomo_probe(struct device *me, struct resource *mem, int irq)
> -{
> - struct locomo_platform_data *pdata = me->platform_data;
> - struct locomo *lchip;
> - unsigned long r;
> - int i, ret = -ENODEV;
> -
> - lchip = kzalloc_obj(struct locomo);
> - if (!lchip)
> - return -ENOMEM;
> -
> - spin_lock_init(&lchip->lock);
> -
> - lchip->dev = me;
> - dev_set_drvdata(lchip->dev, lchip);
> -
> - lchip->phys = mem->start;
> - lchip->irq = irq;
> - lchip->irq_base = (pdata) ? pdata->irq_base : NO_IRQ;
> -
> - /*
> - * Map the whole region. This also maps the
> - * registers for our children.
> - */
> - lchip->base = ioremap(mem->start, PAGE_SIZE);
> - if (!lchip->base) {
> - ret = -ENOMEM;
> - goto out;
> - }
> -
> - /* locomo initialize */
> - locomo_writel(0, lchip->base + LOCOMO_ICR);
> - /* KEYBOARD */
> - locomo_writel(0, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC);
> -
> - /* GPIO */
> - locomo_writel(0, lchip->base + LOCOMO_GPO);
> - locomo_writel((LOCOMO_GPIO(1) | LOCOMO_GPIO(2) | LOCOMO_GPIO(13) | LOCOMO_GPIO(14))
> - , lchip->base + LOCOMO_GPE);
> - locomo_writel((LOCOMO_GPIO(1) | LOCOMO_GPIO(2) | LOCOMO_GPIO(13) | LOCOMO_GPIO(14))
> - , lchip->base + LOCOMO_GPD);
> - locomo_writel(0, lchip->base + LOCOMO_GIE);
> -
> - /* Frontlight */
> - locomo_writel(0, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS);
> - locomo_writel(0, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALD);
> -
> - /* Longtime timer */
> - locomo_writel(0, lchip->base + LOCOMO_LTINT);
> - /* SPI */
> - locomo_writel(0, lchip->base + LOCOMO_SPI + LOCOMO_SPIIE);
> -
> - locomo_writel(6 + 8 + 320 + 30 - 10, lchip->base + LOCOMO_ASD);
> - r = locomo_readl(lchip->base + LOCOMO_ASD);
> - r |= 0x8000;
> - locomo_writel(r, lchip->base + LOCOMO_ASD);
> -
> - locomo_writel(6 + 8 + 320 + 30 - 10 - 128 + 4, lchip->base + LOCOMO_HSD);
> - r = locomo_readl(lchip->base + LOCOMO_HSD);
> - r |= 0x8000;
> - locomo_writel(r, lchip->base + LOCOMO_HSD);
> -
> - locomo_writel(128 / 8, lchip->base + LOCOMO_HSC);
> -
> - /* XON */
> - locomo_writel(0x80, lchip->base + LOCOMO_TADC);
> - udelay(1000);
> - /* CLK9MEN */
> - r = locomo_readl(lchip->base + LOCOMO_TADC);
> - r |= 0x10;
> - locomo_writel(r, lchip->base + LOCOMO_TADC);
> - udelay(100);
> -
> - /* init DAC */
> - r = locomo_readl(lchip->base + LOCOMO_DAC);
> - r |= LOCOMO_DAC_SCLOEB | LOCOMO_DAC_SDAOEB;
> - locomo_writel(r, lchip->base + LOCOMO_DAC);
> -
> - r = locomo_readl(lchip->base + LOCOMO_VER);
> - printk(KERN_INFO "LoCoMo Chip: %lu%lu\n", (r >> 8), (r & 0xff));
> -
> - /*
> - * The interrupt controller must be initialised before any
> - * other device to ensure that the interrupts are available.
> - */
> - if (lchip->irq != NO_IRQ && lchip->irq_base != NO_IRQ)
> - locomo_setup_irq(lchip);
> -
> - for (i = 0; i < ARRAY_SIZE(locomo_devices); i++)
> - locomo_init_one_child(lchip, &locomo_devices[i]);
> - return 0;
> -
> - out:
> - kfree(lchip);
> - return ret;
> -}
> -
> -static int locomo_remove_child(struct device *dev, void *data)
> -{
> - device_unregister(dev);
> - return 0;
> -}
> -
> -static void __locomo_remove(struct locomo *lchip)
> -{
> - device_for_each_child(lchip->dev, NULL, locomo_remove_child);
> -
> - if (lchip->irq != NO_IRQ) {
> - irq_set_chained_handler_and_data(lchip->irq, NULL, NULL);
> - }
> -
> - iounmap(lchip->base);
> - kfree(lchip);
> -}
> -
> -/**
> - * locomo_probe - probe for a single LoCoMo chip.
> - * @dev: platform device
> - *
> - * Probe for a LoCoMo chip. This must be called
> - * before any other locomo-specific code.
> - *
> - * Returns:
> - * * %-EINVAL - device's IORESOURCE_MEM not found
> - * * %-ENXIO - could not allocate an IRQ for the device
> - * * %-ENODEV - device not found.
> - * * %-EBUSY - physical address already marked in-use.
> - * * %-ENOMEM - could not allocate or iomap memory.
> - * * %0 - successful.
> - */
> -static int locomo_probe(struct platform_device *dev)
> -{
> - struct resource *mem;
> - int irq;
> -
> - mem = platform_get_resource(dev, IORESOURCE_MEM, 0);
> - if (!mem)
> - return -EINVAL;
> - irq = platform_get_irq(dev, 0);
> - if (irq < 0)
> - return -ENXIO;
> -
> - return __locomo_probe(&dev->dev, mem, irq);
> -}
> -
> -static void locomo_remove(struct platform_device *dev)
> -{
> - struct locomo *lchip = platform_get_drvdata(dev);
> -
> - if (lchip) {
> - __locomo_remove(lchip);
> - platform_set_drvdata(dev, NULL);
> - }
> -}
> -
> -/*
> - * Not sure if this should be on the system bus or not yet.
> - * We really want some way to register a system device at
> - * the per-machine level, and then have this driver pick
> - * up the registered devices.
> - */
> -static struct platform_driver locomo_device_driver = {
> - .probe = locomo_probe,
> - .remove = locomo_remove,
> -#ifdef CONFIG_PM
> - .suspend = locomo_suspend,
> - .resume = locomo_resume,
> -#endif
> - .driver = {
> - .name = "locomo",
> - },
> -};
> -
> -/*
> - * Get the parent device driver (us) structure
> - * from a child function device
> - */
> -static inline struct locomo *locomo_chip_driver(struct locomo_dev *ldev)
> -{
> - return (struct locomo *)dev_get_drvdata(ldev->dev.parent);
> -}
> -
> -void locomo_gpio_set_dir(struct device *dev, unsigned int bits, unsigned int dir)
> -{
> - struct locomo *lchip = dev_get_drvdata(dev);
> - unsigned long flags;
> - unsigned int r;
> -
> - if (!lchip)
> - return;
> -
> - spin_lock_irqsave(&lchip->lock, flags);
> -
> - r = locomo_readl(lchip->base + LOCOMO_GPD);
> - if (dir)
> - r |= bits;
> - else
> - r &= ~bits;
> - locomo_writel(r, lchip->base + LOCOMO_GPD);
> -
> - r = locomo_readl(lchip->base + LOCOMO_GPE);
> - if (dir)
> - r |= bits;
> - else
> - r &= ~bits;
> - locomo_writel(r, lchip->base + LOCOMO_GPE);
> -
> - spin_unlock_irqrestore(&lchip->lock, flags);
> -}
> -EXPORT_SYMBOL(locomo_gpio_set_dir);
> -
> -int locomo_gpio_read_level(struct device *dev, unsigned int bits)
> -{
> - struct locomo *lchip = dev_get_drvdata(dev);
> - unsigned long flags;
> - unsigned int ret;
> -
> - if (!lchip)
> - return -ENODEV;
> -
> - spin_lock_irqsave(&lchip->lock, flags);
> - ret = locomo_readl(lchip->base + LOCOMO_GPL);
> - spin_unlock_irqrestore(&lchip->lock, flags);
> -
> - ret &= bits;
> - return ret;
> -}
> -EXPORT_SYMBOL(locomo_gpio_read_level);
> -
> -int locomo_gpio_read_output(struct device *dev, unsigned int bits)
> -{
> - struct locomo *lchip = dev_get_drvdata(dev);
> - unsigned long flags;
> - unsigned int ret;
> -
> - if (!lchip)
> - return -ENODEV;
> -
> - spin_lock_irqsave(&lchip->lock, flags);
> - ret = locomo_readl(lchip->base + LOCOMO_GPO);
> - spin_unlock_irqrestore(&lchip->lock, flags);
> -
> - ret &= bits;
> - return ret;
> -}
> -EXPORT_SYMBOL(locomo_gpio_read_output);
> -
> -void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set)
> -{
> - struct locomo *lchip = dev_get_drvdata(dev);
> - unsigned long flags;
> - unsigned int r;
> -
> - if (!lchip)
> - return;
> -
> - spin_lock_irqsave(&lchip->lock, flags);
> -
> - r = locomo_readl(lchip->base + LOCOMO_GPO);
> - if (set)
> - r |= bits;
> - else
> - r &= ~bits;
> - locomo_writel(r, lchip->base + LOCOMO_GPO);
> -
> - spin_unlock_irqrestore(&lchip->lock, flags);
> -}
> -EXPORT_SYMBOL(locomo_gpio_write);
> -
> -static void locomo_m62332_sendbit(void *mapbase, int bit)
> -{
> - unsigned int r;
> -
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r &= ~(LOCOMO_DAC_SCLOEB);
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
> - udelay(DAC_DATA_HOLD_TIME); /* 300 nsec */
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r &= ~(LOCOMO_DAC_SCLOEB);
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
> - udelay(DAC_SCL_LOW_HOLD_TIME); /* 4.7 usec */
> -
> - if (bit & 1) {
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r |= LOCOMO_DAC_SDAOEB;
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_HIGH_SETUP_TIME); /* 1000 nsec */
> - } else {
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r &= ~(LOCOMO_DAC_SDAOEB);
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
> - }
> -
> - udelay(DAC_DATA_SETUP_TIME); /* 250 nsec */
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r |= LOCOMO_DAC_SCLOEB;
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_HIGH_SETUP_TIME); /* 1000 nsec */
> - udelay(DAC_SCL_HIGH_HOLD_TIME); /* 4.0 usec */
> -}
> -
> -void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel)
> -{
> - struct locomo *lchip = locomo_chip_driver(ldev);
> - int i;
> - unsigned char data;
> - unsigned int r;
> - void *mapbase = lchip->base;
> - unsigned long flags;
> -
> - spin_lock_irqsave(&lchip->lock, flags);
> -
> - /* Start */
> - udelay(DAC_BUS_FREE_TIME); /* 5.0 usec */
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r |= LOCOMO_DAC_SCLOEB | LOCOMO_DAC_SDAOEB;
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_HIGH_SETUP_TIME); /* 1000 nsec */
> - udelay(DAC_SCL_HIGH_HOLD_TIME); /* 4.0 usec */
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r &= ~(LOCOMO_DAC_SDAOEB);
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_START_HOLD_TIME); /* 5.0 usec */
> - udelay(DAC_DATA_HOLD_TIME); /* 300 nsec */
> -
> - /* Send slave address and W bit (LSB is W bit) */
> - data = (M62332_SLAVE_ADDR << 1) | M62332_W_BIT;
> - for (i = 1; i <= 8; i++) {
> - locomo_m62332_sendbit(mapbase, data >> (8 - i));
> - }
> -
> - /* Check A bit */
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r &= ~(LOCOMO_DAC_SCLOEB);
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
> - udelay(DAC_SCL_LOW_HOLD_TIME); /* 4.7 usec */
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r &= ~(LOCOMO_DAC_SDAOEB);
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r |= LOCOMO_DAC_SCLOEB;
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_HIGH_SETUP_TIME); /* 1000 nsec */
> - udelay(DAC_SCL_HIGH_HOLD_TIME); /* 4.7 usec */
> - if (locomo_readl(mapbase + LOCOMO_DAC) & LOCOMO_DAC_SDAOEB) { /* High is error */
> - printk(KERN_WARNING "locomo: m62332_senddata Error 1\n");
> - goto out;
> - }
> -
> - /* Send Sub address (LSB is channel select) */
> - /* channel = 0 : ch1 select */
> - /* = 1 : ch2 select */
> - data = M62332_SUB_ADDR + channel;
> - for (i = 1; i <= 8; i++) {
> - locomo_m62332_sendbit(mapbase, data >> (8 - i));
> - }
> -
> - /* Check A bit */
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r &= ~(LOCOMO_DAC_SCLOEB);
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
> - udelay(DAC_SCL_LOW_HOLD_TIME); /* 4.7 usec */
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r &= ~(LOCOMO_DAC_SDAOEB);
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r |= LOCOMO_DAC_SCLOEB;
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_HIGH_SETUP_TIME); /* 1000 nsec */
> - udelay(DAC_SCL_HIGH_HOLD_TIME); /* 4.7 usec */
> - if (locomo_readl(mapbase + LOCOMO_DAC) & LOCOMO_DAC_SDAOEB) { /* High is error */
> - printk(KERN_WARNING "locomo: m62332_senddata Error 2\n");
> - goto out;
> - }
> -
> - /* Send DAC data */
> - for (i = 1; i <= 8; i++) {
> - locomo_m62332_sendbit(mapbase, dac_data >> (8 - i));
> - }
> -
> - /* Check A bit */
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r &= ~(LOCOMO_DAC_SCLOEB);
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
> - udelay(DAC_SCL_LOW_HOLD_TIME); /* 4.7 usec */
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r &= ~(LOCOMO_DAC_SDAOEB);
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r |= LOCOMO_DAC_SCLOEB;
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_HIGH_SETUP_TIME); /* 1000 nsec */
> - udelay(DAC_SCL_HIGH_HOLD_TIME); /* 4.7 usec */
> - if (locomo_readl(mapbase + LOCOMO_DAC) & LOCOMO_DAC_SDAOEB) { /* High is error */
> - printk(KERN_WARNING "locomo: m62332_senddata Error 3\n");
> - }
> -
> -out:
> - /* stop */
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r &= ~(LOCOMO_DAC_SCLOEB);
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_LOW_SETUP_TIME); /* 300 nsec */
> - udelay(DAC_SCL_LOW_HOLD_TIME); /* 4.7 usec */
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r |= LOCOMO_DAC_SCLOEB;
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_HIGH_SETUP_TIME); /* 1000 nsec */
> - udelay(DAC_SCL_HIGH_HOLD_TIME); /* 4 usec */
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r |= LOCOMO_DAC_SDAOEB;
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_HIGH_SETUP_TIME); /* 1000 nsec */
> - udelay(DAC_SCL_HIGH_HOLD_TIME); /* 4 usec */
> -
> - r = locomo_readl(mapbase + LOCOMO_DAC);
> - r |= LOCOMO_DAC_SCLOEB | LOCOMO_DAC_SDAOEB;
> - locomo_writel(r, mapbase + LOCOMO_DAC);
> - udelay(DAC_LOW_SETUP_TIME); /* 1000 nsec */
> - udelay(DAC_SCL_LOW_HOLD_TIME); /* 4.7 usec */
> -
> - spin_unlock_irqrestore(&lchip->lock, flags);
> -}
> -EXPORT_SYMBOL(locomo_m62332_senddata);
> -
> -/*
> - * Frontlight control
> - */
> -
> -void locomo_frontlight_set(struct locomo_dev *dev, int duty, int vr, int bpwf)
> -{
> - unsigned long flags;
> - struct locomo *lchip = locomo_chip_driver(dev);
> -
> - if (vr)
> - locomo_gpio_write(dev->dev.parent, LOCOMO_GPIO_FL_VR, 1);
> - else
> - locomo_gpio_write(dev->dev.parent, LOCOMO_GPIO_FL_VR, 0);
> -
> - spin_lock_irqsave(&lchip->lock, flags);
> - locomo_writel(bpwf, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS);
> - udelay(100);
> - locomo_writel(duty, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALD);
> - locomo_writel(bpwf | LOCOMO_ALC_EN, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS);
> - spin_unlock_irqrestore(&lchip->lock, flags);
> -}
> -EXPORT_SYMBOL(locomo_frontlight_set);
> -
> -/*
> - * LoCoMo "Register Access Bus."
> - *
> - * We model this as a regular bus type, and hang devices directly
> - * off this.
> - */
> -static int locomo_match(struct device *_dev, const struct device_driver *_drv)
> -{
> - struct locomo_dev *dev = LOCOMO_DEV(_dev);
> - const struct locomo_driver *drv = LOCOMO_DRV(_drv);
> -
> - return dev->devid == drv->devid;
> -}
> -
> -static int locomo_bus_probe(struct device *dev)
> -{
> - struct locomo_dev *ldev = LOCOMO_DEV(dev);
> - struct locomo_driver *drv = LOCOMO_DRV(dev->driver);
> - int ret = -ENODEV;
> -
> - if (drv->probe)
> - ret = drv->probe(ldev);
> - return ret;
> -}
> -
> -static void locomo_bus_remove(struct device *dev)
> -{
> - struct locomo_dev *ldev = LOCOMO_DEV(dev);
> - struct locomo_driver *drv = LOCOMO_DRV(dev->driver);
> -
> - if (drv->remove)
> - drv->remove(ldev);
> -}
> -
> -static const struct bus_type locomo_bus_type = {
> - .name = "locomo-bus",
> - .match = locomo_match,
> - .probe = locomo_bus_probe,
> - .remove = locomo_bus_remove,
> -};
> -
> -int locomo_driver_register(struct locomo_driver *driver)
> -{
> - driver->drv.bus = &locomo_bus_type;
> - return driver_register(&driver->drv);
> -}
> -EXPORT_SYMBOL(locomo_driver_register);
> -
> -void locomo_driver_unregister(struct locomo_driver *driver)
> -{
> - driver_unregister(&driver->drv);
> -}
> -EXPORT_SYMBOL(locomo_driver_unregister);
> -
> -static int __init locomo_init(void)
> -{
> - int ret = bus_register(&locomo_bus_type);
> - if (ret == 0)
> - platform_driver_register(&locomo_device_driver);
> - return ret;
> -}
> -
> -static void __exit locomo_exit(void)
> -{
> - platform_driver_unregister(&locomo_device_driver);
> - bus_unregister(&locomo_bus_type);
> -}
> -
> -module_init(locomo_init);
> -module_exit(locomo_exit);
> -
> -MODULE_DESCRIPTION("Sharp LoCoMo core driver");
> -MODULE_LICENSE("GPL");
> -MODULE_AUTHOR("John Lenz <lenz@cs.wisc.edu>");
> diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
> deleted file mode 100644
> index a0f854cf4748..000000000000
> --- a/arch/arm/common/sa1111.c
> +++ /dev/null
> @@ -1,1413 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * linux/arch/arm/common/sa1111.c
> - *
> - * SA1111 support
> - *
> - * Original code by John Dorsey
> - *
> - * This file contains all generic SA1111 support.
> - *
> - * All initialization functions provided here are intended to be called
> - * from machine specific code with proper arguments when required.
> - */
> -#include <linux/module.h>
> -#include <linux/gpio/driver.h>
> -#include <linux/init.h>
> -#include <linux/irq.h>
> -#include <linux/kernel.h>
> -#include <linux/delay.h>
> -#include <linux/errno.h>
> -#include <linux/ioport.h>
> -#include <linux/platform_device.h>
> -#include <linux/slab.h>
> -#include <linux/spinlock.h>
> -#include <linux/dma-map-ops.h>
> -#include <linux/clk.h>
> -#include <linux/io.h>
> -
> -#include <asm/mach/irq.h>
> -#include <asm/mach-types.h>
> -#include <linux/sizes.h>
> -
> -#include <asm/hardware/sa1111.h>
> -
> -#ifdef CONFIG_ARCH_SA1100
> -#include <mach/hardware.h>
> -#endif
> -
> -/* SA1111 IRQs */
> -#define IRQ_GPAIN0 (0)
> -#define IRQ_GPAIN1 (1)
> -#define IRQ_GPAIN2 (2)
> -#define IRQ_GPAIN3 (3)
> -#define IRQ_GPBIN0 (4)
> -#define IRQ_GPBIN1 (5)
> -#define IRQ_GPBIN2 (6)
> -#define IRQ_GPBIN3 (7)
> -#define IRQ_GPBIN4 (8)
> -#define IRQ_GPBIN5 (9)
> -#define IRQ_GPCIN0 (10)
> -#define IRQ_GPCIN1 (11)
> -#define IRQ_GPCIN2 (12)
> -#define IRQ_GPCIN3 (13)
> -#define IRQ_GPCIN4 (14)
> -#define IRQ_GPCIN5 (15)
> -#define IRQ_GPCIN6 (16)
> -#define IRQ_GPCIN7 (17)
> -#define IRQ_MSTXINT (18)
> -#define IRQ_MSRXINT (19)
> -#define IRQ_MSSTOPERRINT (20)
> -#define IRQ_TPTXINT (21)
> -#define IRQ_TPRXINT (22)
> -#define IRQ_TPSTOPERRINT (23)
> -#define SSPXMTINT (24)
> -#define SSPRCVINT (25)
> -#define SSPROR (26)
> -#define AUDXMTDMADONEA (32)
> -#define AUDRCVDMADONEA (33)
> -#define AUDXMTDMADONEB (34)
> -#define AUDRCVDMADONEB (35)
> -#define AUDTFSR (36)
> -#define AUDRFSR (37)
> -#define AUDTUR (38)
> -#define AUDROR (39)
> -#define AUDDTS (40)
> -#define AUDRDD (41)
> -#define AUDSTO (42)
> -#define IRQ_USBPWR (43)
> -#define IRQ_HCIM (44)
> -#define IRQ_HCIBUFFACC (45)
> -#define IRQ_HCIRMTWKP (46)
> -#define IRQ_NHCIMFCIR (47)
> -#define IRQ_USB_PORT_RESUME (48)
> -#define IRQ_S0_READY_NINT (49)
> -#define IRQ_S1_READY_NINT (50)
> -#define IRQ_S0_CD_VALID (51)
> -#define IRQ_S1_CD_VALID (52)
> -#define IRQ_S0_BVD1_STSCHG (53)
> -#define IRQ_S1_BVD1_STSCHG (54)
> -#define SA1111_IRQ_NR (55)
> -
> -extern void sa1110_mb_enable(void);
> -extern void sa1110_mb_disable(void);
> -
> -/*
> - * We keep the following data for the overall SA1111. Note that the
> - * struct device and struct resource are "fake"; they should be supplied
> - * by the bus above us. However, in the interests of getting all SA1111
> - * drivers converted over to the device model, we provide this as an
> - * anchor point for all the other drivers.
> - */
> -struct sa1111 {
> - struct device *dev;
> - struct clk *clk;
> - unsigned long phys;
> - int irq;
> - int irq_base; /* base for cascaded on-chip IRQs */
> - spinlock_t lock;
> - void __iomem *base;
> - struct sa1111_platform_data *pdata;
> - struct irq_domain *irqdomain;
> - struct gpio_chip gc;
> -#ifdef CONFIG_PM
> - void *saved_state;
> -#endif
> -};
> -
> -/*
> - * We _really_ need to eliminate this. Its only users
> - * are the PWM and DMA checking code.
> - */
> -static struct sa1111 *g_sa1111;
> -
> -struct sa1111_dev_info {
> - unsigned long offset;
> - unsigned long skpcr_mask;
> - bool dma;
> - unsigned int devid;
> - unsigned int hwirq[6];
> -};
> -
> -static struct sa1111_dev_info sa1111_devices[] = {
> - {
> - .offset = SA1111_USB,
> - .skpcr_mask = SKPCR_UCLKEN,
> - .dma = true,
> - .devid = SA1111_DEVID_USB,
> - .hwirq = {
> - IRQ_USBPWR,
> - IRQ_HCIM,
> - IRQ_HCIBUFFACC,
> - IRQ_HCIRMTWKP,
> - IRQ_NHCIMFCIR,
> - IRQ_USB_PORT_RESUME
> - },
> - },
> - {
> - .offset = 0x0600,
> - .skpcr_mask = SKPCR_I2SCLKEN | SKPCR_L3CLKEN,
> - .dma = true,
> - .devid = SA1111_DEVID_SAC,
> - .hwirq = {
> - AUDXMTDMADONEA,
> - AUDXMTDMADONEB,
> - AUDRCVDMADONEA,
> - AUDRCVDMADONEB
> - },
> - },
> - {
> - .offset = 0x0800,
> - .skpcr_mask = SKPCR_SCLKEN,
> - .devid = SA1111_DEVID_SSP,
> - },
> - {
> - .offset = SA1111_KBD,
> - .skpcr_mask = SKPCR_PTCLKEN,
> - .devid = SA1111_DEVID_PS2_KBD,
> - .hwirq = {
> - IRQ_TPRXINT,
> - IRQ_TPTXINT
> - },
> - },
> - {
> - .offset = SA1111_MSE,
> - .skpcr_mask = SKPCR_PMCLKEN,
> - .devid = SA1111_DEVID_PS2_MSE,
> - .hwirq = {
> - IRQ_MSRXINT,
> - IRQ_MSTXINT
> - },
> - },
> - {
> - .offset = 0x1800,
> - .skpcr_mask = 0,
> - .devid = SA1111_DEVID_PCMCIA,
> - .hwirq = {
> - IRQ_S0_READY_NINT,
> - IRQ_S0_CD_VALID,
> - IRQ_S0_BVD1_STSCHG,
> - IRQ_S1_READY_NINT,
> - IRQ_S1_CD_VALID,
> - IRQ_S1_BVD1_STSCHG,
> - },
> - },
> -};
> -
> -static int sa1111_map_irq(struct sa1111 *sachip, irq_hw_number_t hwirq)
> -{
> - return irq_create_mapping(sachip->irqdomain, hwirq);
> -}
> -
> -/*
> - * SA1111 interrupt support. Since clearing an IRQ while there are
> - * active IRQs causes the interrupt output to pulse, the upper levels
> - * will call us again if there are more interrupts to process.
> - */
> -static void sa1111_irq_handler(struct irq_desc *desc)
> -{
> - unsigned int stat0, stat1, i;
> - struct sa1111 *sachip = irq_desc_get_handler_data(desc);
> - struct irq_domain *irqdomain;
> - void __iomem *mapbase = sachip->base + SA1111_INTC;
> -
> - stat0 = readl_relaxed(mapbase + SA1111_INTSTATCLR0);
> - stat1 = readl_relaxed(mapbase + SA1111_INTSTATCLR1);
> -
> - writel_relaxed(stat0, mapbase + SA1111_INTSTATCLR0);
> -
> - desc->irq_data.chip->irq_ack(&desc->irq_data);
> -
> - writel_relaxed(stat1, mapbase + SA1111_INTSTATCLR1);
> -
> - if (stat0 == 0 && stat1 == 0) {
> - handle_bad_irq(desc);
> - return;
> - }
> -
> - irqdomain = sachip->irqdomain;
> -
> - for (i = 0; stat0; i++, stat0 >>= 1)
> - if (stat0 & 1)
> - generic_handle_domain_irq(irqdomain, i);
> -
> - for (i = 32; stat1; i++, stat1 >>= 1)
> - if (stat1 & 1)
> - generic_handle_domain_irq(irqdomain, i);
> -
> - /* For level-based interrupts */
> - desc->irq_data.chip->irq_unmask(&desc->irq_data);
> -}
> -
> -static u32 sa1111_irqmask(struct irq_data *d)
> -{
> - return BIT(irqd_to_hwirq(d) & 31);
> -}
> -
> -static int sa1111_irqbank(struct irq_data *d)
> -{
> - return (irqd_to_hwirq(d) / 32) * 4;
> -}
> -
> -static void sa1111_ack_irq(struct irq_data *d)
> -{
> -}
> -
> -static void sa1111_mask_irq(struct irq_data *d)
> -{
> - struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
> - void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
> - u32 ie;
> -
> - ie = readl_relaxed(mapbase + SA1111_INTEN0);
> - ie &= ~sa1111_irqmask(d);
> - writel(ie, mapbase + SA1111_INTEN0);
> -}
> -
> -static void sa1111_unmask_irq(struct irq_data *d)
> -{
> - struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
> - void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
> - u32 ie;
> -
> - ie = readl_relaxed(mapbase + SA1111_INTEN0);
> - ie |= sa1111_irqmask(d);
> - writel_relaxed(ie, mapbase + SA1111_INTEN0);
> -}
> -
> -/*
> - * Attempt to re-trigger the interrupt. The SA1111 contains a register
> - * (INTSET) which claims to do this. However, in practice no amount of
> - * manipulation of INTEN and INTSET guarantees that the interrupt will
> - * be triggered. In fact, its very difficult, if not impossible to get
> - * INTSET to re-trigger the interrupt.
> - */
> -static int sa1111_retrigger_irq(struct irq_data *d)
> -{
> - struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
> - void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
> - u32 ip, mask = sa1111_irqmask(d);
> - int i;
> -
> - ip = readl_relaxed(mapbase + SA1111_INTPOL0);
> - for (i = 0; i < 8; i++) {
> - writel_relaxed(ip ^ mask, mapbase + SA1111_INTPOL0);
> - writel_relaxed(ip, mapbase + SA1111_INTPOL0);
> - if (readl_relaxed(mapbase + SA1111_INTSTATCLR0) & mask)
> - break;
> - }
> -
> - if (i == 8) {
> - pr_err("Danger Will Robinson: failed to re-trigger IRQ%d\n",
> - d->irq);
> - return 0;
> - }
> -
> - return 1;
> -}
> -
> -static int sa1111_type_irq(struct irq_data *d, unsigned int flags)
> -{
> - struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
> - void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
> - u32 ip, mask = sa1111_irqmask(d);
> -
> - if (flags == IRQ_TYPE_PROBE)
> - return 0;
> -
> - if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0)
> - return -EINVAL;
> -
> - ip = readl_relaxed(mapbase + SA1111_INTPOL0);
> - if (flags & IRQ_TYPE_EDGE_RISING)
> - ip &= ~mask;
> - else
> - ip |= mask;
> - writel_relaxed(ip, mapbase + SA1111_INTPOL0);
> - writel_relaxed(ip, mapbase + SA1111_WAKEPOL0);
> -
> - return 0;
> -}
> -
> -static int sa1111_wake_irq(struct irq_data *d, unsigned int on)
> -{
> - struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
> - void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
> - u32 we, mask = sa1111_irqmask(d);
> -
> - we = readl_relaxed(mapbase + SA1111_WAKEEN0);
> - if (on)
> - we |= mask;
> - else
> - we &= ~mask;
> - writel_relaxed(we, mapbase + SA1111_WAKEEN0);
> -
> - return 0;
> -}
> -
> -static struct irq_chip sa1111_irq_chip = {
> - .name = "SA1111",
> - .irq_ack = sa1111_ack_irq,
> - .irq_mask = sa1111_mask_irq,
> - .irq_unmask = sa1111_unmask_irq,
> - .irq_retrigger = sa1111_retrigger_irq,
> - .irq_set_type = sa1111_type_irq,
> - .irq_set_wake = sa1111_wake_irq,
> -};
> -
> -static int sa1111_irqdomain_map(struct irq_domain *d, unsigned int irq,
> - irq_hw_number_t hwirq)
> -{
> - struct sa1111 *sachip = d->host_data;
> -
> - /* Disallow unavailable interrupts */
> - if (hwirq > SSPROR && hwirq < AUDXMTDMADONEA)
> - return -EINVAL;
> -
> - irq_set_chip_data(irq, sachip);
> - irq_set_chip_and_handler(irq, &sa1111_irq_chip, handle_edge_irq);
> - irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
> -
> - return 0;
> -}
> -
> -static const struct irq_domain_ops sa1111_irqdomain_ops = {
> - .map = sa1111_irqdomain_map,
> - .xlate = irq_domain_xlate_twocell,
> -};
> -
> -static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base)
> -{
> - void __iomem *irqbase = sachip->base + SA1111_INTC;
> - int ret;
> -
> - /*
> - * We're guaranteed that this region hasn't been taken.
> - */
> - request_mem_region(sachip->phys + SA1111_INTC, 512, "irq");
> -
> - ret = irq_alloc_descs(-1, irq_base, SA1111_IRQ_NR, -1);
> - if (ret <= 0) {
> - dev_err(sachip->dev, "unable to allocate %u irqs: %d\n",
> - SA1111_IRQ_NR, ret);
> - if (ret == 0)
> - ret = -EINVAL;
> - return ret;
> - }
> -
> - sachip->irq_base = ret;
> -
> - /* disable all IRQs */
> - writel_relaxed(0, irqbase + SA1111_INTEN0);
> - writel_relaxed(0, irqbase + SA1111_INTEN1);
> - writel_relaxed(0, irqbase + SA1111_WAKEEN0);
> - writel_relaxed(0, irqbase + SA1111_WAKEEN1);
> -
> - /*
> - * detect on rising edge. Note: Feb 2001 Errata for SA1111
> - * specifies that S0ReadyInt and S1ReadyInt should be '1'.
> - */
> - writel_relaxed(0, irqbase + SA1111_INTPOL0);
> - writel_relaxed(BIT(IRQ_S0_READY_NINT & 31) |
> - BIT(IRQ_S1_READY_NINT & 31),
> - irqbase + SA1111_INTPOL1);
> -
> - /* clear all IRQs */
> - writel_relaxed(~0, irqbase + SA1111_INTSTATCLR0);
> - writel_relaxed(~0, irqbase + SA1111_INTSTATCLR1);
> -
> - sachip->irqdomain = irq_domain_create_linear(NULL, SA1111_IRQ_NR,
> - &sa1111_irqdomain_ops,
> - sachip);
> - if (!sachip->irqdomain) {
> - irq_free_descs(sachip->irq_base, SA1111_IRQ_NR);
> - return -ENOMEM;
> - }
> -
> - irq_domain_associate_many(sachip->irqdomain,
> - sachip->irq_base + IRQ_GPAIN0,
> - IRQ_GPAIN0, SSPROR + 1 - IRQ_GPAIN0);
> - irq_domain_associate_many(sachip->irqdomain,
> - sachip->irq_base + AUDXMTDMADONEA,
> - AUDXMTDMADONEA,
> - IRQ_S1_BVD1_STSCHG + 1 - AUDXMTDMADONEA);
> -
> - /*
> - * Register SA1111 interrupt
> - */
> - irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
> - irq_set_chained_handler_and_data(sachip->irq, sa1111_irq_handler,
> - sachip);
> -
> - dev_info(sachip->dev, "Providing IRQ%u-%u\n",
> - sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1);
> -
> - return 0;
> -}
> -
> -static void sa1111_remove_irq(struct sa1111 *sachip)
> -{
> - struct irq_domain *domain = sachip->irqdomain;
> - void __iomem *irqbase = sachip->base + SA1111_INTC;
> - int i;
> -
> - /* disable all IRQs */
> - writel_relaxed(0, irqbase + SA1111_INTEN0);
> - writel_relaxed(0, irqbase + SA1111_INTEN1);
> - writel_relaxed(0, irqbase + SA1111_WAKEEN0);
> - writel_relaxed(0, irqbase + SA1111_WAKEEN1);
> -
> - irq_set_chained_handler_and_data(sachip->irq, NULL, NULL);
> - for (i = 0; i < SA1111_IRQ_NR; i++)
> - irq_dispose_mapping(irq_find_mapping(domain, i));
> - irq_domain_remove(domain);
> -
> - release_mem_region(sachip->phys + SA1111_INTC, 512);
> -}
> -
> -enum {
> - SA1111_GPIO_PXDDR = (SA1111_GPIO_PADDR - SA1111_GPIO_PADDR),
> - SA1111_GPIO_PXDRR = (SA1111_GPIO_PADRR - SA1111_GPIO_PADDR),
> - SA1111_GPIO_PXDWR = (SA1111_GPIO_PADWR - SA1111_GPIO_PADDR),
> - SA1111_GPIO_PXSDR = (SA1111_GPIO_PASDR - SA1111_GPIO_PADDR),
> - SA1111_GPIO_PXSSR = (SA1111_GPIO_PASSR - SA1111_GPIO_PADDR),
> -};
> -
> -static struct sa1111 *gc_to_sa1111(struct gpio_chip *gc)
> -{
> - return container_of(gc, struct sa1111, gc);
> -}
> -
> -static void __iomem *sa1111_gpio_map_reg(struct sa1111 *sachip, unsigned offset)
> -{
> - void __iomem *reg = sachip->base + SA1111_GPIO;
> -
> - if (offset < 4)
> - return reg + SA1111_GPIO_PADDR;
> - if (offset < 10)
> - return reg + SA1111_GPIO_PBDDR;
> - if (offset < 18)
> - return reg + SA1111_GPIO_PCDDR;
> - return NULL;
> -}
> -
> -static u32 sa1111_gpio_map_bit(unsigned offset)
> -{
> - if (offset < 4)
> - return BIT(offset);
> - if (offset < 10)
> - return BIT(offset - 4);
> - if (offset < 18)
> - return BIT(offset - 10);
> - return 0;
> -}
> -
> -static void sa1111_gpio_modify(void __iomem *reg, u32 mask, u32 set)
> -{
> - u32 val;
> -
> - val = readl_relaxed(reg);
> - val &= ~mask;
> - val |= mask & set;
> - writel_relaxed(val, reg);
> -}
> -
> -static int sa1111_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
> -{
> - struct sa1111 *sachip = gc_to_sa1111(gc);
> - void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
> - u32 mask = sa1111_gpio_map_bit(offset);
> -
> - return !!(readl_relaxed(reg + SA1111_GPIO_PXDDR) & mask);
> -}
> -
> -static int sa1111_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
> -{
> - struct sa1111 *sachip = gc_to_sa1111(gc);
> - unsigned long flags;
> - void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
> - u32 mask = sa1111_gpio_map_bit(offset);
> -
> - spin_lock_irqsave(&sachip->lock, flags);
> - sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, mask);
> - sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, mask);
> - spin_unlock_irqrestore(&sachip->lock, flags);
> -
> - return 0;
> -}
> -
> -static int sa1111_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
> - int value)
> -{
> - struct sa1111 *sachip = gc_to_sa1111(gc);
> - unsigned long flags;
> - void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
> - u32 mask = sa1111_gpio_map_bit(offset);
> -
> - spin_lock_irqsave(&sachip->lock, flags);
> - sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0);
> - sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0);
> - sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, 0);
> - sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, 0);
> - spin_unlock_irqrestore(&sachip->lock, flags);
> -
> - return 0;
> -}
> -
> -static int sa1111_gpio_get(struct gpio_chip *gc, unsigned offset)
> -{
> - struct sa1111 *sachip = gc_to_sa1111(gc);
> - void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
> - u32 mask = sa1111_gpio_map_bit(offset);
> -
> - return !!(readl_relaxed(reg + SA1111_GPIO_PXDRR) & mask);
> -}
> -
> -static int sa1111_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
> -{
> - struct sa1111 *sachip = gc_to_sa1111(gc);
> - unsigned long flags;
> - void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
> - u32 mask = sa1111_gpio_map_bit(offset);
> -
> - spin_lock_irqsave(&sachip->lock, flags);
> - sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0);
> - sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0);
> - spin_unlock_irqrestore(&sachip->lock, flags);
> -
> - return 0;
> -}
> -
> -static int sa1111_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
> - unsigned long *bits)
> -{
> - struct sa1111 *sachip = gc_to_sa1111(gc);
> - unsigned long flags;
> - void __iomem *reg = sachip->base + SA1111_GPIO;
> - u32 msk, val;
> -
> - msk = *mask;
> - val = *bits;
> -
> - spin_lock_irqsave(&sachip->lock, flags);
> - sa1111_gpio_modify(reg + SA1111_GPIO_PADWR, msk & 15, val);
> - sa1111_gpio_modify(reg + SA1111_GPIO_PASSR, msk & 15, val);
> - sa1111_gpio_modify(reg + SA1111_GPIO_PBDWR, (msk >> 4) & 255, val >> 4);
> - sa1111_gpio_modify(reg + SA1111_GPIO_PBSSR, (msk >> 4) & 255, val >> 4);
> - sa1111_gpio_modify(reg + SA1111_GPIO_PCDWR, (msk >> 12) & 255, val >> 12);
> - sa1111_gpio_modify(reg + SA1111_GPIO_PCSSR, (msk >> 12) & 255, val >> 12);
> - spin_unlock_irqrestore(&sachip->lock, flags);
> -
> - return 0;
> -}
> -
> -static int sa1111_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
> -{
> - struct sa1111 *sachip = gc_to_sa1111(gc);
> -
> - return sa1111_map_irq(sachip, offset);
> -}
> -
> -static int sa1111_setup_gpios(struct sa1111 *sachip)
> -{
> - sachip->gc.label = "sa1111";
> - sachip->gc.parent = sachip->dev;
> - sachip->gc.owner = THIS_MODULE;
> - sachip->gc.get_direction = sa1111_gpio_get_direction;
> - sachip->gc.direction_input = sa1111_gpio_direction_input;
> - sachip->gc.direction_output = sa1111_gpio_direction_output;
> - sachip->gc.get = sa1111_gpio_get;
> - sachip->gc.set = sa1111_gpio_set;
> - sachip->gc.set_multiple = sa1111_gpio_set_multiple;
> - sachip->gc.to_irq = sa1111_gpio_to_irq;
> - sachip->gc.base = -1;
> - sachip->gc.ngpio = 18;
> -
> - return devm_gpiochip_add_data(sachip->dev, &sachip->gc, sachip);
> -}
> -
> -/*
> - * Bring the SA1111 out of reset. This requires a set procedure:
> - * 1. nRESET asserted (by hardware)
> - * 2. CLK turned on from SA1110
> - * 3. nRESET deasserted
> - * 4. VCO turned on, PLL_BYPASS turned off
> - * 5. Wait lock time, then assert RCLKEn
> - * 7. PCR set to allow clocking of individual functions
> - *
> - * Until we've done this, the only registers we can access are:
> - * SBI_SKCR
> - * SBI_SMCR
> - * SBI_SKID
> - */
> -static void sa1111_wake(struct sa1111 *sachip)
> -{
> - unsigned long flags, r;
> -
> - spin_lock_irqsave(&sachip->lock, flags);
> -
> - clk_enable(sachip->clk);
> -
> - /*
> - * Turn VCO on, and disable PLL Bypass.
> - */
> - r = readl_relaxed(sachip->base + SA1111_SKCR);
> - r &= ~SKCR_VCO_OFF;
> - writel_relaxed(r, sachip->base + SA1111_SKCR);
> - r |= SKCR_PLL_BYPASS | SKCR_OE_EN;
> - writel_relaxed(r, sachip->base + SA1111_SKCR);
> -
> - /*
> - * Wait lock time. SA1111 manual _doesn't_
> - * specify a figure for this! We choose 100us.
> - */
> - udelay(100);
> -
> - /*
> - * Enable RCLK. We also ensure that RDYEN is set.
> - */
> - r |= SKCR_RCLKEN | SKCR_RDYEN;
> - writel_relaxed(r, sachip->base + SA1111_SKCR);
> -
> - /*
> - * Wait 14 RCLK cycles for the chip to finish coming out
> - * of reset. (RCLK=24MHz). This is 590ns.
> - */
> - udelay(1);
> -
> - /*
> - * Ensure all clocks are initially off.
> - */
> - writel_relaxed(0, sachip->base + SA1111_SKPCR);
> -
> - spin_unlock_irqrestore(&sachip->lock, flags);
> -}
> -
> -#ifdef CONFIG_ARCH_SA1100
> -
> -static u32 sa1111_dma_mask[] = {
> - ~0,
> - ~(1 << 20),
> - ~(1 << 23),
> - ~(1 << 24),
> - ~(1 << 25),
> - ~(1 << 20),
> - ~(1 << 20),
> - 0,
> -};
> -
> -/*
> - * Configure the SA1111 shared memory controller.
> - */
> -static void
> -sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac,
> - unsigned int cas_latency)
> -{
> - unsigned int smcr = SMCR_DTIM | SMCR_MBGE | FInsrt(drac, SMCR_DRAC);
> -
> - if (cas_latency == 3)
> - smcr |= SMCR_CLAT;
> -
> - writel_relaxed(smcr, sachip->base + SA1111_SMCR);
> -
> - /*
> - * Now clear the bits in the DMA mask to work around the SA1111
> - * DMA erratum (Intel StrongARM SA-1111 Microprocessor Companion
> - * Chip Specification Update, June 2000, Erratum #7).
> - */
> - if (sachip->dev->dma_mask)
> - *sachip->dev->dma_mask &= sa1111_dma_mask[drac >> 2];
> -
> - sachip->dev->coherent_dma_mask &= sa1111_dma_mask[drac >> 2];
> -}
> -#endif
> -
> -static void sa1111_dev_release(struct device *_dev)
> -{
> - struct sa1111_dev *dev = to_sa1111_device(_dev);
> -
> - kfree(dev);
> -}
> -
> -static int
> -sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent,
> - struct sa1111_dev_info *info)
> -{
> - struct sa1111_dev *dev;
> - unsigned i;
> - int ret;
> -
> - dev = kzalloc_obj(struct sa1111_dev);
> - if (!dev) {
> - ret = -ENOMEM;
> - goto err_alloc;
> - }
> -
> - device_initialize(&dev->dev);
> - dev_set_name(&dev->dev, "%4.4lx", info->offset);
> - dev->devid = info->devid;
> - dev->dev.parent = sachip->dev;
> - dev->dev.bus = &sa1111_bus_type;
> - dev->dev.release = sa1111_dev_release;
> - dev->res.start = sachip->phys + info->offset;
> - dev->res.end = dev->res.start + 511;
> - dev->res.name = dev_name(&dev->dev);
> - dev->res.flags = IORESOURCE_MEM;
> - dev->mapbase = sachip->base + info->offset;
> - dev->skpcr_mask = info->skpcr_mask;
> -
> - for (i = 0; i < ARRAY_SIZE(info->hwirq); i++)
> - dev->hwirq[i] = info->hwirq[i];
> -
> - /*
> - * If the parent device has a DMA mask associated with it, and
> - * this child supports DMA, propagate it down to the children.
> - */
> - if (info->dma && sachip->dev->dma_mask) {
> - dev->dma_mask = *sachip->dev->dma_mask;
> - dev->dev.dma_mask = &dev->dma_mask;
> - dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask;
> - }
> -
> - ret = request_resource(parent, &dev->res);
> - if (ret) {
> - dev_err(sachip->dev, "failed to allocate resource for %s\n",
> - dev->res.name);
> - goto err_resource;
> - }
> -
> - ret = device_add(&dev->dev);
> - if (ret)
> - goto err_add;
> - return 0;
> -
> - err_add:
> - release_resource(&dev->res);
> - err_resource:
> - put_device(&dev->dev);
> - err_alloc:
> - return ret;
> -}
> -
> -static int __sa1111_probe(struct device *me, struct resource *mem, int irq)
> -{
> - struct sa1111_platform_data *pd = me->platform_data;
> - struct sa1111 *sachip;
> - unsigned long id;
> - unsigned int has_devs;
> - int i, ret = -ENODEV;
> -
> - if (!pd)
> - return -EINVAL;
> -
> - sachip = devm_kzalloc(me, sizeof(struct sa1111), GFP_KERNEL);
> - if (!sachip)
> - return -ENOMEM;
> -
> - sachip->clk = devm_clk_get(me, "SA1111_CLK");
> - if (IS_ERR(sachip->clk))
> - return PTR_ERR(sachip->clk);
> -
> - ret = clk_prepare(sachip->clk);
> - if (ret)
> - return ret;
> -
> - spin_lock_init(&sachip->lock);
> -
> - sachip->dev = me;
> - dev_set_drvdata(sachip->dev, sachip);
> -
> - sachip->pdata = pd;
> - sachip->phys = mem->start;
> - sachip->irq = irq;
> -
> - /*
> - * Map the whole region. This also maps the
> - * registers for our children.
> - */
> - sachip->base = ioremap(mem->start, PAGE_SIZE * 2);
> - if (!sachip->base) {
> - ret = -ENOMEM;
> - goto err_clk_unprep;
> - }
> -
> - /*
> - * Probe for the chip. Only touch the SBI registers.
> - */
> - id = readl_relaxed(sachip->base + SA1111_SKID);
> - if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
> - printk(KERN_DEBUG "SA1111 not detected: ID = %08lx\n", id);
> - ret = -ENODEV;
> - goto err_unmap;
> - }
> -
> - pr_info("SA1111 Microprocessor Companion Chip: silicon revision %lx, metal revision %lx\n",
> - (id & SKID_SIREV_MASK) >> 4, id & SKID_MTREV_MASK);
> -
> - /*
> - * We found it. Wake the chip up, and initialise.
> - */
> - sa1111_wake(sachip);
> -
> - /*
> - * The interrupt controller must be initialised before any
> - * other device to ensure that the interrupts are available.
> - */
> - ret = sa1111_setup_irq(sachip, pd->irq_base);
> - if (ret)
> - goto err_clk;
> -
> - /* Setup the GPIOs - should really be done after the IRQ setup */
> - ret = sa1111_setup_gpios(sachip);
> - if (ret)
> - goto err_irq;
> -
> -#ifdef CONFIG_ARCH_SA1100
> - {
> - unsigned int val;
> -
> - /*
> - * The SDRAM configuration of the SA1110 and the SA1111 must
> - * match. This is very important to ensure that SA1111 accesses
> - * don't corrupt the SDRAM. Note that this ungates the SA1111's
> - * MBGNT signal, so we must have called sa1110_mb_disable()
> - * beforehand.
> - */
> - sa1111_configure_smc(sachip, 1,
> - FExtr(MDCNFG, MDCNFG_SA1110_DRAC0),
> - FExtr(MDCNFG, MDCNFG_SA1110_TDL0));
> -
> - /*
> - * We only need to turn on DCLK whenever we want to use the
> - * DMA. It can otherwise be held firmly in the off position.
> - * (currently, we always enable it.)
> - */
> - val = readl_relaxed(sachip->base + SA1111_SKPCR);
> - writel_relaxed(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR);
> -
> - /*
> - * Enable the SA1110 memory bus request and grant signals.
> - */
> - sa1110_mb_enable();
> - }
> -#endif
> -
> - g_sa1111 = sachip;
> -
> - has_devs = ~0;
> - if (pd)
> - has_devs &= ~pd->disable_devs;
> -
> - for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++)
> - if (sa1111_devices[i].devid & has_devs)
> - sa1111_init_one_child(sachip, mem, &sa1111_devices[i]);
> -
> - return 0;
> -
> - err_irq:
> - sa1111_remove_irq(sachip);
> - err_clk:
> - clk_disable(sachip->clk);
> - err_unmap:
> - iounmap(sachip->base);
> - err_clk_unprep:
> - clk_unprepare(sachip->clk);
> - return ret;
> -}
> -
> -static int sa1111_remove_one(struct device *dev, void *data)
> -{
> - struct sa1111_dev *sadev = to_sa1111_device(dev);
> - if (dev->bus != &sa1111_bus_type)
> - return 0;
> - device_del(&sadev->dev);
> - release_resource(&sadev->res);
> - put_device(&sadev->dev);
> - return 0;
> -}
> -
> -static void __sa1111_remove(struct sa1111 *sachip)
> -{
> - device_for_each_child(sachip->dev, NULL, sa1111_remove_one);
> -
> - sa1111_remove_irq(sachip);
> -
> - clk_disable(sachip->clk);
> - clk_unprepare(sachip->clk);
> -
> - iounmap(sachip->base);
> -}
> -
> -struct sa1111_save_data {
> - unsigned int skcr;
> - unsigned int skpcr;
> - unsigned int skcdr;
> - unsigned char skaud;
> - unsigned char skpwm0;
> - unsigned char skpwm1;
> -
> - /*
> - * Interrupt controller
> - */
> - unsigned int intpol0;
> - unsigned int intpol1;
> - unsigned int inten0;
> - unsigned int inten1;
> - unsigned int wakepol0;
> - unsigned int wakepol1;
> - unsigned int wakeen0;
> - unsigned int wakeen1;
> -};
> -
> -#ifdef CONFIG_PM
> -
> -static int sa1111_suspend_noirq(struct device *dev)
> -{
> - struct sa1111 *sachip = dev_get_drvdata(dev);
> - struct sa1111_save_data *save;
> - unsigned long flags;
> - unsigned int val;
> - void __iomem *base;
> -
> - save = kmalloc_obj(struct sa1111_save_data);
> - if (!save)
> - return -ENOMEM;
> - sachip->saved_state = save;
> -
> - spin_lock_irqsave(&sachip->lock, flags);
> -
> - /*
> - * Save state.
> - */
> - base = sachip->base;
> - save->skcr = readl_relaxed(base + SA1111_SKCR);
> - save->skpcr = readl_relaxed(base + SA1111_SKPCR);
> - save->skcdr = readl_relaxed(base + SA1111_SKCDR);
> - save->skaud = readl_relaxed(base + SA1111_SKAUD);
> - save->skpwm0 = readl_relaxed(base + SA1111_SKPWM0);
> - save->skpwm1 = readl_relaxed(base + SA1111_SKPWM1);
> -
> - writel_relaxed(0, sachip->base + SA1111_SKPWM0);
> - writel_relaxed(0, sachip->base + SA1111_SKPWM1);
> -
> - base = sachip->base + SA1111_INTC;
> - save->intpol0 = readl_relaxed(base + SA1111_INTPOL0);
> - save->intpol1 = readl_relaxed(base + SA1111_INTPOL1);
> - save->inten0 = readl_relaxed(base + SA1111_INTEN0);
> - save->inten1 = readl_relaxed(base + SA1111_INTEN1);
> - save->wakepol0 = readl_relaxed(base + SA1111_WAKEPOL0);
> - save->wakepol1 = readl_relaxed(base + SA1111_WAKEPOL1);
> - save->wakeen0 = readl_relaxed(base + SA1111_WAKEEN0);
> - save->wakeen1 = readl_relaxed(base + SA1111_WAKEEN1);
> -
> - /*
> - * Disable.
> - */
> - val = readl_relaxed(sachip->base + SA1111_SKCR);
> - writel_relaxed(val | SKCR_SLEEP, sachip->base + SA1111_SKCR);
> -
> - clk_disable(sachip->clk);
> -
> - spin_unlock_irqrestore(&sachip->lock, flags);
> -
> -#ifdef CONFIG_ARCH_SA1100
> - sa1110_mb_disable();
> -#endif
> -
> - return 0;
> -}
> -
> -/*
> - * sa1111_resume - Restore the SA1111 device state.
> - * @dev: device to restore
> - *
> - * Restore the general state of the SA1111; clock control and
> - * interrupt controller. Other parts of the SA1111 must be
> - * restored by their respective drivers, and must be called
> - * via LDM after this function.
> - */
> -static int sa1111_resume_noirq(struct device *dev)
> -{
> - struct sa1111 *sachip = dev_get_drvdata(dev);
> - struct sa1111_save_data *save;
> - unsigned long flags, id;
> - void __iomem *base;
> -
> - save = sachip->saved_state;
> - if (!save)
> - return 0;
> -
> - /*
> - * Ensure that the SA1111 is still here.
> - * FIXME: shouldn't do this here.
> - */
> - id = readl_relaxed(sachip->base + SA1111_SKID);
> - if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
> - __sa1111_remove(sachip);
> - dev_set_drvdata(dev, NULL);
> - kfree(save);
> - return 0;
> - }
> -
> - /*
> - * First of all, wake up the chip.
> - */
> - sa1111_wake(sachip);
> -
> -#ifdef CONFIG_ARCH_SA1100
> - /* Enable the memory bus request/grant signals */
> - sa1110_mb_enable();
> -#endif
> -
> - /*
> - * Only lock for write ops. Also, sa1111_wake must be called with
> - * released spinlock!
> - */
> - spin_lock_irqsave(&sachip->lock, flags);
> -
> - writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN0);
> - writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN1);
> -
> - base = sachip->base;
> - writel_relaxed(save->skcr, base + SA1111_SKCR);
> - writel_relaxed(save->skpcr, base + SA1111_SKPCR);
> - writel_relaxed(save->skcdr, base + SA1111_SKCDR);
> - writel_relaxed(save->skaud, base + SA1111_SKAUD);
> - writel_relaxed(save->skpwm0, base + SA1111_SKPWM0);
> - writel_relaxed(save->skpwm1, base + SA1111_SKPWM1);
> -
> - base = sachip->base + SA1111_INTC;
> - writel_relaxed(save->intpol0, base + SA1111_INTPOL0);
> - writel_relaxed(save->intpol1, base + SA1111_INTPOL1);
> - writel_relaxed(save->inten0, base + SA1111_INTEN0);
> - writel_relaxed(save->inten1, base + SA1111_INTEN1);
> - writel_relaxed(save->wakepol0, base + SA1111_WAKEPOL0);
> - writel_relaxed(save->wakepol1, base + SA1111_WAKEPOL1);
> - writel_relaxed(save->wakeen0, base + SA1111_WAKEEN0);
> - writel_relaxed(save->wakeen1, base + SA1111_WAKEEN1);
> -
> - spin_unlock_irqrestore(&sachip->lock, flags);
> -
> - sachip->saved_state = NULL;
> - kfree(save);
> -
> - return 0;
> -}
> -
> -#else
> -#define sa1111_suspend_noirq NULL
> -#define sa1111_resume_noirq NULL
> -#endif
> -
> -/**
> - * sa1111_probe - probe for a single SA1111 chip.
> - * @pdev: platform device.
> - *
> - * Probe for a SA1111 chip. This must be called
> - * before any other SA1111-specific code.
> - *
> - * Returns:
> - * * %-ENODEV - device not found.
> - * * %-ENOMEM - memory allocation failure.
> - * * %-EBUSY - physical address already marked in-use.
> - * * %-EINVAL - no platform data passed
> - * * %0 - successful.
> - */
> -static int sa1111_probe(struct platform_device *pdev)
> -{
> - struct resource *mem;
> - int irq;
> -
> - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> - if (!mem)
> - return -EINVAL;
> - irq = platform_get_irq(pdev, 0);
> - if (irq < 0)
> - return irq;
> -
> - return __sa1111_probe(&pdev->dev, mem, irq);
> -}
> -
> -static void sa1111_remove(struct platform_device *pdev)
> -{
> - struct sa1111 *sachip = platform_get_drvdata(pdev);
> -
> - if (sachip) {
> -#ifdef CONFIG_PM
> - kfree(sachip->saved_state);
> - sachip->saved_state = NULL;
> -#endif
> - __sa1111_remove(sachip);
> - platform_set_drvdata(pdev, NULL);
> - }
> -}
> -
> -static struct dev_pm_ops sa1111_pm_ops = {
> - .suspend_noirq = sa1111_suspend_noirq,
> - .resume_noirq = sa1111_resume_noirq,
> -};
> -
> -/*
> - * Not sure if this should be on the system bus or not yet.
> - * We really want some way to register a system device at
> - * the per-machine level, and then have this driver pick
> - * up the registered devices.
> - *
> - * We also need to handle the SDRAM configuration for
> - * PXA250/SA1110 machine classes.
> - */
> -static struct platform_driver sa1111_device_driver = {
> - .probe = sa1111_probe,
> - .remove = sa1111_remove,
> - .driver = {
> - .name = "sa1111",
> - .pm = &sa1111_pm_ops,
> - },
> -};
> -
> -/*
> - * Get the parent device driver (us) structure
> - * from a child function device
> - */
> -static inline struct sa1111 *sa1111_chip_driver(struct sa1111_dev *sadev)
> -{
> - return (struct sa1111 *)dev_get_drvdata(sadev->dev.parent);
> -}
> -
> -/*
> - * The bits in the opdiv field are non-linear.
> - */
> -static unsigned char opdiv_table[] = { 1, 4, 2, 8 };
> -
> -static unsigned int __sa1111_pll_clock(struct sa1111 *sachip)
> -{
> - unsigned int skcdr, fbdiv, ipdiv, opdiv;
> -
> - skcdr = readl_relaxed(sachip->base + SA1111_SKCDR);
> -
> - fbdiv = (skcdr & 0x007f) + 2;
> - ipdiv = ((skcdr & 0x0f80) >> 7) + 2;
> - opdiv = opdiv_table[(skcdr & 0x3000) >> 12];
> -
> - return 3686400 * fbdiv / (ipdiv * opdiv);
> -}
> -
> -/**
> - * sa1111_pll_clock - return the current PLL clock frequency.
> - * @sadev: SA1111 function block
> - *
> - * BUG: we should look at SKCR. We also blindly believe that
> - * the chip is being fed with the 3.6864MHz clock.
> - *
> - * Returns the PLL clock in Hz.
> - */
> -unsigned int sa1111_pll_clock(struct sa1111_dev *sadev)
> -{
> - struct sa1111 *sachip = sa1111_chip_driver(sadev);
> -
> - return __sa1111_pll_clock(sachip);
> -}
> -EXPORT_SYMBOL(sa1111_pll_clock);
> -
> -/**
> - * sa1111_select_audio_mode - select I2S or AC link mode
> - * @sadev: SA1111 function block
> - * @mode: One of %SA1111_AUDIO_ACLINK or %SA1111_AUDIO_I2S
> - *
> - * Frob the SKCR to select AC Link mode or I2S mode for
> - * the audio block.
> - */
> -void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode)
> -{
> - struct sa1111 *sachip = sa1111_chip_driver(sadev);
> - unsigned long flags;
> - unsigned int val;
> -
> - spin_lock_irqsave(&sachip->lock, flags);
> -
> - val = readl_relaxed(sachip->base + SA1111_SKCR);
> - if (mode == SA1111_AUDIO_I2S) {
> - val &= ~SKCR_SELAC;
> - } else {
> - val |= SKCR_SELAC;
> - }
> - writel_relaxed(val, sachip->base + SA1111_SKCR);
> -
> - spin_unlock_irqrestore(&sachip->lock, flags);
> -}
> -EXPORT_SYMBOL(sa1111_select_audio_mode);
> -
> -/**
> - * sa1111_set_audio_rate - set the audio sample rate
> - * @sadev: SA1111 SAC function block
> - * @rate: sample rate to select
> - */
> -int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate)
> -{
> - struct sa1111 *sachip = sa1111_chip_driver(sadev);
> - unsigned int div;
> -
> - if (sadev->devid != SA1111_DEVID_SAC)
> - return -EINVAL;
> -
> - div = (__sa1111_pll_clock(sachip) / 256 + rate / 2) / rate;
> - if (div == 0)
> - div = 1;
> - if (div > 128)
> - div = 128;
> -
> - writel_relaxed(div - 1, sachip->base + SA1111_SKAUD);
> -
> - return 0;
> -}
> -EXPORT_SYMBOL(sa1111_set_audio_rate);
> -
> -/**
> - * sa1111_get_audio_rate - get the audio sample rate
> - * @sadev: SA1111 SAC function block device
> - */
> -int sa1111_get_audio_rate(struct sa1111_dev *sadev)
> -{
> - struct sa1111 *sachip = sa1111_chip_driver(sadev);
> - unsigned long div;
> -
> - if (sadev->devid != SA1111_DEVID_SAC)
> - return -EINVAL;
> -
> - div = readl_relaxed(sachip->base + SA1111_SKAUD) + 1;
> -
> - return __sa1111_pll_clock(sachip) / (256 * div);
> -}
> -EXPORT_SYMBOL(sa1111_get_audio_rate);
> -
> -/*
> - * Individual device operations.
> - */
> -
> -/**
> - * sa1111_enable_device - enable an on-chip SA1111 function block
> - * @sadev: SA1111 function block device to enable
> - */
> -int sa1111_enable_device(struct sa1111_dev *sadev)
> -{
> - struct sa1111 *sachip = sa1111_chip_driver(sadev);
> - unsigned long flags;
> - unsigned int val;
> - int ret = 0;
> -
> - if (sachip->pdata && sachip->pdata->enable)
> - ret = sachip->pdata->enable(sachip->pdata->data, sadev->devid);
> -
> - if (ret == 0) {
> - spin_lock_irqsave(&sachip->lock, flags);
> - val = readl_relaxed(sachip->base + SA1111_SKPCR);
> - writel_relaxed(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
> - spin_unlock_irqrestore(&sachip->lock, flags);
> - }
> - return ret;
> -}
> -EXPORT_SYMBOL(sa1111_enable_device);
> -
> -/**
> - * sa1111_disable_device - disable an on-chip SA1111 function block
> - * @sadev: SA1111 function block device to disable
> - */
> -void sa1111_disable_device(struct sa1111_dev *sadev)
> -{
> - struct sa1111 *sachip = sa1111_chip_driver(sadev);
> - unsigned long flags;
> - unsigned int val;
> -
> - spin_lock_irqsave(&sachip->lock, flags);
> - val = readl_relaxed(sachip->base + SA1111_SKPCR);
> - writel_relaxed(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
> - spin_unlock_irqrestore(&sachip->lock, flags);
> -
> - if (sachip->pdata && sachip->pdata->disable)
> - sachip->pdata->disable(sachip->pdata->data, sadev->devid);
> -}
> -EXPORT_SYMBOL(sa1111_disable_device);
> -
> -int sa1111_get_irq(struct sa1111_dev *sadev, unsigned num)
> -{
> - struct sa1111 *sachip = sa1111_chip_driver(sadev);
> - if (num >= ARRAY_SIZE(sadev->hwirq))
> - return -EINVAL;
> - return sa1111_map_irq(sachip, sadev->hwirq[num]);
> -}
> -EXPORT_SYMBOL_GPL(sa1111_get_irq);
> -
> -/*
> - * SA1111 "Register Access Bus."
> - *
> - * We model this as a regular bus type, and hang devices directly
> - * off this.
> - */
> -static int sa1111_match(struct device *_dev, const struct device_driver *_drv)
> -{
> - struct sa1111_dev *dev = to_sa1111_device(_dev);
> - const struct sa1111_driver *drv = SA1111_DRV(_drv);
> -
> - return !!(dev->devid & drv->devid);
> -}
> -
> -static int sa1111_bus_probe(struct device *dev)
> -{
> - struct sa1111_dev *sadev = to_sa1111_device(dev);
> - struct sa1111_driver *drv = SA1111_DRV(dev->driver);
> - int ret = -ENODEV;
> -
> - if (drv->probe)
> - ret = drv->probe(sadev);
> - return ret;
> -}
> -
> -static void sa1111_bus_remove(struct device *dev)
> -{
> - struct sa1111_dev *sadev = to_sa1111_device(dev);
> - struct sa1111_driver *drv = SA1111_DRV(dev->driver);
> -
> - if (drv->remove)
> - drv->remove(sadev);
> -}
> -
> -const struct bus_type sa1111_bus_type = {
> - .name = "sa1111-rab",
> - .match = sa1111_match,
> - .probe = sa1111_bus_probe,
> - .remove = sa1111_bus_remove,
> -};
> -EXPORT_SYMBOL(sa1111_bus_type);
> -
> -int sa1111_driver_register(struct sa1111_driver *driver)
> -{
> - driver->drv.bus = &sa1111_bus_type;
> - return driver_register(&driver->drv);
> -}
> -EXPORT_SYMBOL(sa1111_driver_register);
> -
> -void sa1111_driver_unregister(struct sa1111_driver *driver)
> -{
> - driver_unregister(&driver->drv);
> -}
> -EXPORT_SYMBOL(sa1111_driver_unregister);
> -
> -static int __init sa1111_init(void)
> -{
> - int ret = bus_register(&sa1111_bus_type);
> - if (ret == 0)
> - platform_driver_register(&sa1111_device_driver);
> - return ret;
> -}
> -
> -static void __exit sa1111_exit(void)
> -{
> - platform_driver_unregister(&sa1111_device_driver);
> - bus_unregister(&sa1111_bus_type);
> -}
> -
> -subsys_initcall(sa1111_init);
> -module_exit(sa1111_exit);
> -
> -MODULE_DESCRIPTION("Intel Corporation SA1111 core driver");
> -MODULE_LICENSE("GPL");
> diff --git a/arch/arm/configs/assabet_defconfig b/arch/arm/configs/assabet_defconfig
> deleted file mode 100644
> index e4264fdac2e5..000000000000
> --- a/arch/arm/configs/assabet_defconfig
> +++ /dev/null
> @@ -1,57 +0,0 @@
> -CONFIG_SYSVIPC=y
> -CONFIG_LOG_BUF_SHIFT=14
> -CONFIG_BLK_DEV_INITRD=y
> -CONFIG_EXPERT=y
> -CONFIG_ARCH_MULTI_V4=y
> -# CONFIG_ARCH_MULTI_V7 is not set
> -CONFIG_ARCH_SA1100=y
> -CONFIG_SA1100_ASSABET=y
> -# CONFIG_AEABI is not set
> -CONFIG_ATAGS=y
> -CONFIG_CMDLINE="mem=32M console=ttySA0,38400n8 initrd=0xc0800000,3M root=/dev/ram"
> -CONFIG_FPE_NWFPE=y
> -CONFIG_PM=y
> -CONFIG_MODULES=y
> -CONFIG_PARTITION_ADVANCED=y
> -CONFIG_NET=y
> -CONFIG_UNIX=y
> -CONFIG_INET=y
> -# CONFIG_IPV6 is not set
> -CONFIG_PCCARD=y
> -CONFIG_PCMCIA_SA1100=y
> -CONFIG_MTD=y
> -CONFIG_MTD_REDBOOT_PARTS=y
> -CONFIG_MTD_BLOCK=y
> -CONFIG_MTD_CFI=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_GEOMETRY=y
> -# CONFIG_MTD_CFI_I1 is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -CONFIG_MTD_SA1100=y
> -CONFIG_BLK_DEV_LOOP=m
> -CONFIG_BLK_DEV_RAM=y
> -CONFIG_NETDEVICES=y
> -CONFIG_NET_PCMCIA=y
> -CONFIG_PCMCIA_PCNET=y
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_INPUT_KEYBOARD is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_SERIO is not set
> -CONFIG_SERIAL_8250=m
> -CONFIG_SERIAL_SA1100=y
> -CONFIG_SERIAL_SA1100_CONSOLE=y
> -CONFIG_FB=y
> -CONFIG_FB_SA1100=y
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_SOUND=y
> -CONFIG_NEW_LEDS=y
> -CONFIG_LEDS_CLASS=y
> -CONFIG_LEDS_TRIGGERS=y
> -CONFIG_LEDS_TRIGGER_CPU=y
> -CONFIG_EXT2_FS=y
> -CONFIG_MSDOS_FS=y
> -CONFIG_TMPFS=y
> -CONFIG_JFFS2_FS=y
> -CONFIG_NFS_FS=y
> -CONFIG_NLS_CODEPAGE_437=y
> -CONFIG_DEBUG_USER=y
> diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig
> deleted file mode 100644
> index 570a5f8bc57b..000000000000
> --- a/arch/arm/configs/collie_defconfig
> +++ /dev/null
> @@ -1,87 +0,0 @@
> -CONFIG_SYSVIPC=y
> -CONFIG_LOG_BUF_SHIFT=14
> -CONFIG_BLK_DEV_INITRD=y
> -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
> -CONFIG_EXPERT=y
> -CONFIG_BASE_SMALL=y
> -# CONFIG_EPOLL is not set
> -CONFIG_ARCH_MULTI_V4=y
> -# CONFIG_ARCH_MULTI_V7 is not set
> -CONFIG_ARCH_SA1100=y
> -CONFIG_SA1100_COLLIE=y
> -CONFIG_ATAGS=y
> -CONFIG_CMDLINE="noinitrd root=/dev/mtdblock2 rootfstype=jffs2 fbcon=rotate:1"
> -CONFIG_PM=y
> -# CONFIG_SWAP is not set
> -CONFIG_SLUB_TINY=y
> -CONFIG_NET=y
> -CONFIG_PACKET=y
> -CONFIG_UNIX=y
> -CONFIG_INET=y
> -# CONFIG_IPV6 is not set
> -CONFIG_PCCARD=y
> -CONFIG_PCMCIA_SA1100=y
> -CONFIG_PCMCIA_DEBUG=y
> -CONFIG_MTD=y
> -CONFIG_MTD_BLOCK=y
> -CONFIG_MTD_CFI=y
> -CONFIG_MTD_JEDECPROBE=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_GEOMETRY=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set
> -# CONFIG_MTD_CFI_I1 is not set
> -# CONFIG_MTD_CFI_I2 is not set
> -CONFIG_MTD_CFI_I4=y
> -CONFIG_MTD_CFI_INTELEXT=y
> -CONFIG_MTD_SA1100=y
> -CONFIG_BLK_DEV_LOOP=y
> -CONFIG_BLK_DEV_RAM=y
> -CONFIG_BLK_DEV_RAM_SIZE=1024
> -CONFIG_BLK_DEV_SD=y
> -CONFIG_ATA=y
> -CONFIG_PATA_PCMCIA=y
> -# CONFIG_INPUT_MOUSEDEV is not set
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_KEYBOARD_ATKBD is not set
> -CONFIG_KEYBOARD_LOCOMO=y
> -# CONFIG_INPUT_MOUSE is not set
> -CONFIG_INPUT_TOUCHSCREEN=y
> -# CONFIG_SERIO_SERPORT is not set
> -# CONFIG_LEGACY_PTYS is not set
> -CONFIG_SERIAL_8250=y
> -CONFIG_SERIAL_8250_CS=y
> -CONFIG_SERIAL_8250_EXTENDED=y
> -CONFIG_SERIAL_SA1100=y
> -CONFIG_SERIAL_SA1100_CONSOLE=y
> -# CONFIG_HWMON is not set
> -CONFIG_MCP_SA11X0=y
> -CONFIG_MCP_UCB1200=y
> -CONFIG_MCP_UCB1200_TS=y
> -CONFIG_FB=y
> -CONFIG_FB_SA1100=y
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_FB_MODE_HELPERS=y
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
> -CONFIG_NEW_LEDS=y
> -CONFIG_LEDS_CLASS=y
> -CONFIG_LEDS_LOCOMO=y
> -CONFIG_LEDS_TRIGGERS=y
> -CONFIG_LEDS_TRIGGER_TIMER=y
> -CONFIG_LEDS_TRIGGER_DISK=y
> -# CONFIG_DNOTIFY is not set
> -CONFIG_VFAT_FS=y
> -CONFIG_TMPFS=y
> -CONFIG_JFFS2_FS=y
> -CONFIG_ROMFS_FS=y
> -CONFIG_NLS_DEFAULT="cp437"
> -CONFIG_NLS_CODEPAGE_437=y
> -CONFIG_NLS_ISO8859_1=y
> -CONFIG_FONTS=y
> -CONFIG_FONT_MINI_4x6=y
> -# CONFIG_DEBUG_BUGVERBOSE is not set
> -CONFIG_MAGIC_SYSRQ=y
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_DETECT_SOFTLOCKUP is not set
> -CONFIG_DEBUG_MUTEXES=y
> diff --git a/arch/arm/configs/h3600_defconfig b/arch/arm/configs/h3600_defconfig
> deleted file mode 100644
> index 3e8da62d959d..000000000000
> --- a/arch/arm/configs/h3600_defconfig
> +++ /dev/null
> @@ -1,63 +0,0 @@
> -CONFIG_SYSVIPC=y
> -CONFIG_NO_HZ_IDLE=y
> -CONFIG_HIGH_RES_TIMERS=y
> -CONFIG_PREEMPT=y
> -CONFIG_LOG_BUF_SHIFT=14
> -CONFIG_BLK_DEV_INITRD=y
> -CONFIG_EXPERT=y
> -CONFIG_ARCH_MULTI_V4=y
> -# CONFIG_ARCH_MULTI_V7 is not set
> -CONFIG_ARCH_SA1100=y
> -CONFIG_SA1100_H3600=y
> -# CONFIG_CPU_FREQ_STAT is not set
> -CONFIG_ATAGS=y
> -CONFIG_MODULES=y
> -CONFIG_NET=y
> -CONFIG_UNIX=y
> -CONFIG_INET=y
> -# CONFIG_IPV6 is not set
> -# CONFIG_WIRELESS is not set
> -CONFIG_PCCARD=y
> -CONFIG_PCMCIA_SA1100=y
> -CONFIG_MTD=y
> -CONFIG_MTD_REDBOOT_PARTS=y
> -CONFIG_MTD_BLOCK=y
> -CONFIG_MTD_CFI=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_GEOMETRY=y
> -# CONFIG_MTD_CFI_I1 is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -CONFIG_MTD_SA1100=y
> -CONFIG_BLK_DEV_LOOP=m
> -CONFIG_BLK_DEV_RAM=y
> -CONFIG_BLK_DEV_RAM_SIZE=8192
> -CONFIG_BLK_DEV_SD=y
> -# CONFIG_BLK_DEV_BSG is not set
> -CONFIG_ATA=y
> -CONFIG_PATA_PCMCIA=y
> -CONFIG_NETDEVICES=y
> -CONFIG_PCMCIA_PCNET=y
> -CONFIG_PPP=m
> -CONFIG_PPP_BSDCOMP=m
> -CONFIG_PPP_DEFLATE=m
> -CONFIG_PPP_ASYNC=m
> -# CONFIG_WLAN is not set
> -# CONFIG_KEYBOARD_ATKBD is not set
> -CONFIG_KEYBOARD_GPIO=y
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_SERIO is not set
> -CONFIG_SERIAL_SA1100=y
> -CONFIG_SERIAL_SA1100_CONSOLE=y
> -# CONFIG_HW_RANDOM is not set
> -# CONFIG_HWMON is not set
> -CONFIG_FB=y
> -CONFIG_FB_SA1100=y
> -# CONFIG_USB_SUPPORT is not set
> -CONFIG_EXT2_FS=y
> -CONFIG_MSDOS_FS=m
> -CONFIG_VFAT_FS=m
> -CONFIG_JFFS2_FS=y
> -CONFIG_CRAMFS=m
> -CONFIG_NFS_FS=y
> -CONFIG_NFSD=m
> -CONFIG_NLS=y
> diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig
> deleted file mode 100644
> index a96cfb81aba5..000000000000
> --- a/arch/arm/configs/jornada720_defconfig
> +++ /dev/null
> @@ -1,95 +0,0 @@
> -CONFIG_SYSVIPC=y
> -CONFIG_LOG_BUF_SHIFT=14
> -CONFIG_EXPERT=y
> -CONFIG_ARCH_MULTI_V4=y
> -# CONFIG_ARCH_MULTI_V7 is not set
> -CONFIG_ARCH_SA1100=y
> -CONFIG_SA1100_JORNADA720=y
> -CONFIG_SA1100_JORNADA720_SSP=y
> -CONFIG_PM=y
> -CONFIG_ATAGS=y
> -CONFIG_MODULES=y
> -CONFIG_NET=y
> -CONFIG_PACKET=y
> -CONFIG_UNIX=y
> -CONFIG_INET=y
> -CONFIG_IP_MULTICAST=y
> -# CONFIG_IPV6 is not set
> -CONFIG_NETFILTER=y
> -CONFIG_PCCARD=y
> -CONFIG_PCMCIA_SA1100=y
> -CONFIG_BLK_DEV_LOOP=y
> -CONFIG_BLK_DEV_NBD=y
> -CONFIG_BLK_DEV_SD=y
> -# CONFIG_BLK_DEV_BSG is not set
> -CONFIG_ATA=y
> -CONFIG_PATA_PCMCIA=y
> -CONFIG_NETDEVICES=y
> -CONFIG_DUMMY=y
> -CONFIG_NET_PCMCIA=y
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
> -# CONFIG_KEYBOARD_ATKBD is not set
> -CONFIG_KEYBOARD_HP7XX=y
> -# CONFIG_INPUT_MOUSE is not set
> -CONFIG_INPUT_TOUCHSCREEN=y
> -CONFIG_TOUCHSCREEN_HP7XX=y
> -CONFIG_LEGACY_PTY_COUNT=32
> -CONFIG_SERIAL_SA1100=y
> -CONFIG_SERIAL_SA1100_CONSOLE=y
> -# CONFIG_HWMON is not set
> -CONFIG_FB=y
> -CONFIG_FB_S1D13XXX=y
> -CONFIG_LCD_CLASS_DEVICE=y
> -CONFIG_BACKLIGHT_CLASS_DEVICE=y
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
> -# CONFIG_USB_SUPPORT is not set
> -CONFIG_RTC_CLASS=y
> -CONFIG_RTC_DRV_SA1100=y
> -CONFIG_EXT2_FS=y
> -CONFIG_MSDOS_FS=y
> -CONFIG_VFAT_FS=y
> -# CONFIG_NETWORK_FILESYSTEMS is not set
> -CONFIG_NLS_CODEPAGE_437=m
> -CONFIG_NLS_CODEPAGE_737=m
> -CONFIG_NLS_CODEPAGE_775=m
> -CONFIG_NLS_CODEPAGE_850=m
> -CONFIG_NLS_CODEPAGE_852=m
> -CONFIG_NLS_CODEPAGE_855=m
> -CONFIG_NLS_CODEPAGE_857=m
> -CONFIG_NLS_CODEPAGE_860=m
> -CONFIG_NLS_CODEPAGE_861=m
> -CONFIG_NLS_CODEPAGE_862=m
> -CONFIG_NLS_CODEPAGE_863=m
> -CONFIG_NLS_CODEPAGE_864=m
> -CONFIG_NLS_CODEPAGE_865=m
> -CONFIG_NLS_CODEPAGE_866=m
> -CONFIG_NLS_CODEPAGE_869=m
> -CONFIG_NLS_CODEPAGE_936=m
> -CONFIG_NLS_CODEPAGE_950=m
> -CONFIG_NLS_CODEPAGE_932=m
> -CONFIG_NLS_CODEPAGE_949=m
> -CONFIG_NLS_CODEPAGE_874=m
> -CONFIG_NLS_ISO8859_8=m
> -CONFIG_NLS_CODEPAGE_1250=m
> -CONFIG_NLS_CODEPAGE_1251=m
> -CONFIG_NLS_ASCII=m
> -CONFIG_NLS_ISO8859_1=m
> -CONFIG_NLS_ISO8859_2=m
> -CONFIG_NLS_ISO8859_3=m
> -CONFIG_NLS_ISO8859_4=m
> -CONFIG_NLS_ISO8859_5=m
> -CONFIG_NLS_ISO8859_6=m
> -CONFIG_NLS_ISO8859_7=m
> -CONFIG_NLS_ISO8859_9=m
> -CONFIG_NLS_ISO8859_13=m
> -CONFIG_NLS_ISO8859_14=m
> -CONFIG_NLS_ISO8859_15=m
> -CONFIG_NLS_KOI8_R=m
> -CONFIG_NLS_KOI8_U=m
> -CONFIG_NLS_UTF8=m
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_FTRACE is not set
> -CONFIG_DEBUG_LL=y
> diff --git a/arch/arm/configs/neponset_defconfig b/arch/arm/configs/neponset_defconfig
> deleted file mode 100644
> index 164643f1b6c0..000000000000
> --- a/arch/arm/configs/neponset_defconfig
> +++ /dev/null
> @@ -1,88 +0,0 @@
> -CONFIG_SYSVIPC=y
> -CONFIG_LOG_BUF_SHIFT=14
> -CONFIG_BLK_DEV_INITRD=y
> -CONFIG_EXPERT=y
> -CONFIG_ARCH_MULTI_V4=y
> -# CONFIG_ARCH_MULTI_V7 is not set
> -CONFIG_ARCH_SA1100=y
> -CONFIG_SA1100_ASSABET=y
> -CONFIG_ASSABET_NEPONSET=y
> -CONFIG_ATAGS=y
> -CONFIG_ZBOOT_ROM_TEXT=0x80000
> -CONFIG_ZBOOT_ROM_BSS=0xc1000000
> -CONFIG_ZBOOT_ROM=y
> -CONFIG_CMDLINE="console=ttySA0,38400n8 cpufreq=221200 rw root=/dev/mtdblock2 mtdparts=sa1100:512K(boot),1M(kernel),2560K(initrd),4M(root) mem=32M noinitrd initrd=0xc0800000,3M"
> -CONFIG_FPE_NWFPE=y
> -# CONFIG_AEABI is not set
> -CONFIG_PM=y
> -CONFIG_MODULES=y
> -CONFIG_MODULE_UNLOAD=y
> -CONFIG_PARTITION_ADVANCED=y
> -# CONFIG_MSDOS_PARTITION is not set
> -CONFIG_NET=y
> -CONFIG_PACKET=y
> -CONFIG_UNIX=y
> -CONFIG_INET=y
> -# CONFIG_IPV6 is not set
> -CONFIG_PCCARD=y
> -CONFIG_PCMCIA_SA1100=y
> -CONFIG_PCMCIA_SA1111=y
> -CONFIG_MTD=y
> -CONFIG_MTD_CMDLINE_PARTS=y
> -CONFIG_MTD_REDBOOT_PARTS=y
> -CONFIG_MTD_BLOCK=y
> -CONFIG_MTD_CFI=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_INTELEXT=y
> -CONFIG_MTD_RAM=y
> -CONFIG_MTD_SA1100=y
> -CONFIG_BLK_DEV_RAM=y
> -CONFIG_BLK_DEV_RAM_SIZE=8192
> -CONFIG_SCSI=m
> -CONFIG_BLK_DEV_SD=m
> -CONFIG_NETDEVICES=y
> -CONFIG_NET_VENDOR_SMC=y
> -CONFIG_PCMCIA_PCNET=y
> -CONFIG_SMC91X=y
> -CONFIG_NET_PCMCIA=y
> -# CONFIG_INPUT_MOUSE is not set
> -CONFIG_INPUT_TOUCHSCREEN=y
> -CONFIG_SERIO_SERPORT=m
> -CONFIG_SERIO_SA1111=y
> -CONFIG_LEGACY_PTY_COUNT=64
> -CONFIG_SERIAL_8250=y
> -CONFIG_SERIAL_8250_CS=y
> -CONFIG_SERIAL_SA1100=y
> -CONFIG_SERIAL_SA1100_CONSOLE=y
> -CONFIG_SERIAL_NONSTANDARD=y
> -CONFIG_I2C=y
> -CONFIG_I2C_CHARDEV=y
> -CONFIG_WATCHDOG=y
> -CONFIG_SA1100_WATCHDOG=m
> -CONFIG_FB=y
> -CONFIG_FB_SA1100=y
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -CONFIG_SOUND=y
> -CONFIG_SOUND_PRIME=y
> -# CONFIG_USB_HID is not set
> -CONFIG_USB=m
> -CONFIG_USB_MON=m
> -CONFIG_USB_OHCI_HCD=m
> -CONFIG_USB_STORAGE=m
> -CONFIG_NEW_LEDS=y
> -CONFIG_LEDS_CLASS=y
> -CONFIG_LEDS_TRIGGERS=y
> -CONFIG_LEDS_TRIGGER_CPU=y
> -CONFIG_EXT2_FS=y
> -CONFIG_MSDOS_FS=m
> -CONFIG_VFAT_FS=m
> -CONFIG_JFFS2_FS=y
> -CONFIG_NFS_FS=y
> -CONFIG_NLS=y
> -CONFIG_NLS_CODEPAGE_437=m
> -CONFIG_NLS_ISO8859_1=m
> -CONFIG_DEBUG_KERNEL=y
> -CONFIG_MAGIC_SYSRQ=y
> -CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_LL=y
> diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
> index 0163c3e78a67..d58f6b5c4c35 100644
> --- a/arch/arm/include/asm/cputype.h
> +++ b/arch/arm/include/asm/cputype.h
> @@ -262,10 +262,6 @@ static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
> return read_cpuid(CPUID_MPIDR);
> }
>
> -/* StrongARM-11x0 CPUs */
> -#define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100)
> -#define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110)
> -
> /*
> * Intel's XScale3 core supports some v6 features (supersections, L2)
> * but advertises itself as v5 as it does not support the v6 ISA. For
> diff --git a/arch/arm/include/asm/hardware/locomo.h b/arch/arm/include/asm/hardware/locomo.h
> deleted file mode 100644
> index 3190e1e5067a..000000000000
> --- a/arch/arm/include/asm/hardware/locomo.h
> +++ /dev/null
> @@ -1,217 +0,0 @@
> -/*
> - * arch/arm/include/asm/hardware/locomo.h
> - *
> - * This file contains the definitions for the LoCoMo G/A Chip
> - *
> - * (C) Copyright 2004 John Lenz
> - *
> - * May be copied or modified under the terms of the GNU General Public
> - * License. See linux/COPYING for more information.
> - *
> - * Based on sa1111.h
> - */
> -#ifndef _ASM_ARCH_LOCOMO
> -#define _ASM_ARCH_LOCOMO
> -
> -#define locomo_writel(val,addr) ({ *(volatile u16 *)(addr) = (val); })
> -#define locomo_readl(addr) (*(volatile u16 *)(addr))
> -
> -/* LOCOMO version */
> -#define LOCOMO_VER 0x00
> -
> -/* Pin status */
> -#define LOCOMO_ST 0x04
> -
> -/* Pin status */
> -#define LOCOMO_C32K 0x08
> -
> -/* Interrupt controller */
> -#define LOCOMO_ICR 0x0C
> -
> -/* MCS decoder for boot selecting */
> -#define LOCOMO_MCSX0 0x10
> -#define LOCOMO_MCSX1 0x14
> -#define LOCOMO_MCSX2 0x18
> -#define LOCOMO_MCSX3 0x1c
> -
> -/* Touch panel controller */
> -#define LOCOMO_ASD 0x20 /* AD start delay */
> -#define LOCOMO_HSD 0x28 /* HSYS delay */
> -#define LOCOMO_HSC 0x2c /* HSYS period */
> -#define LOCOMO_TADC 0x30 /* tablet ADC clock */
> -
> -
> -/* Long time timer */
> -#define LOCOMO_LTC 0xd8 /* LTC interrupt setting */
> -#define LOCOMO_LTINT 0xdc /* LTC interrupt */
> -
> -/* DAC control signal for LCD (COMADJ ) */
> -#define LOCOMO_DAC 0xe0
> -/* DAC control */
> -#define LOCOMO_DAC_SCLOEB 0x08 /* SCL pin output data */
> -#define LOCOMO_DAC_TEST 0x04 /* Test bit */
> -#define LOCOMO_DAC_SDA 0x02 /* SDA pin level (read-only) */
> -#define LOCOMO_DAC_SDAOEB 0x01 /* SDA pin output data */
> -
> -/* SPI interface */
> -#define LOCOMO_SPI 0x60
> -#define LOCOMO_SPIMD 0x00 /* SPI mode setting */
> -#define LOCOMO_SPICT 0x04 /* SPI mode control */
> -#define LOCOMO_SPIST 0x08 /* SPI status */
> -#define LOCOMO_SPI_TEND (1 << 3) /* Transfer end bit */
> -#define LOCOMO_SPI_REND (1 << 2) /* Receive end bit */
> -#define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */
> -#define LOCOMO_SPI_RFR (1) /* read buffer bit */
> -
> -#define LOCOMO_SPIIS 0x10 /* SPI interrupt status */
> -#define LOCOMO_SPIWE 0x14 /* SPI interrupt status write enable */
> -#define LOCOMO_SPIIE 0x18 /* SPI interrupt enable */
> -#define LOCOMO_SPIIR 0x1c /* SPI interrupt request */
> -#define LOCOMO_SPITD 0x20 /* SPI transfer data write */
> -#define LOCOMO_SPIRD 0x24 /* SPI receive data read */
> -#define LOCOMO_SPITS 0x28 /* SPI transfer data shift */
> -#define LOCOMO_SPIRS 0x2C /* SPI receive data shift */
> -
> -/* GPIO */
> -#define LOCOMO_GPD 0x90 /* GPIO direction */
> -#define LOCOMO_GPE 0x94 /* GPIO input enable */
> -#define LOCOMO_GPL 0x98 /* GPIO level */
> -#define LOCOMO_GPO 0x9c /* GPIO out data setting */
> -#define LOCOMO_GRIE 0xa0 /* GPIO rise detection */
> -#define LOCOMO_GFIE 0xa4 /* GPIO fall detection */
> -#define LOCOMO_GIS 0xa8 /* GPIO edge detection status */
> -#define LOCOMO_GWE 0xac /* GPIO status write enable */
> -#define LOCOMO_GIE 0xb0 /* GPIO interrupt enable */
> -#define LOCOMO_GIR 0xb4 /* GPIO interrupt request */
> -#define LOCOMO_GPIO(Nb) (0x01 << (Nb))
> -#define LOCOMO_GPIO_RTS LOCOMO_GPIO(0)
> -#define LOCOMO_GPIO_CTS LOCOMO_GPIO(1)
> -#define LOCOMO_GPIO_DSR LOCOMO_GPIO(2)
> -#define LOCOMO_GPIO_DTR LOCOMO_GPIO(3)
> -#define LOCOMO_GPIO_LCD_VSHA_ON LOCOMO_GPIO(4)
> -#define LOCOMO_GPIO_LCD_VSHD_ON LOCOMO_GPIO(5)
> -#define LOCOMO_GPIO_LCD_VEE_ON LOCOMO_GPIO(6)
> -#define LOCOMO_GPIO_LCD_MOD LOCOMO_GPIO(7)
> -#define LOCOMO_GPIO_DAC_ON LOCOMO_GPIO(8)
> -#define LOCOMO_GPIO_FL_VR LOCOMO_GPIO(9)
> -#define LOCOMO_GPIO_DAC_SDATA LOCOMO_GPIO(10)
> -#define LOCOMO_GPIO_DAC_SCK LOCOMO_GPIO(11)
> -#define LOCOMO_GPIO_DAC_SLOAD LOCOMO_GPIO(12)
> -#define LOCOMO_GPIO_CARD_DETECT LOCOMO_GPIO(13)
> -#define LOCOMO_GPIO_WRITE_PROT LOCOMO_GPIO(14)
> -#define LOCOMO_GPIO_CARD_POWER LOCOMO_GPIO(15)
> -
> -/* Start the definitions of the devices. Each device has an initial
> - * base address and a series of offsets from that base address. */
> -
> -/* Keyboard controller */
> -#define LOCOMO_KEYBOARD 0x40
> -#define LOCOMO_KIB 0x00 /* KIB level */
> -#define LOCOMO_KSC 0x04 /* KSTRB control */
> -#define LOCOMO_KCMD 0x08 /* KSTRB command */
> -#define LOCOMO_KIC 0x0c /* Key interrupt */
> -
> -/* Front light adjustment controller */
> -#define LOCOMO_FRONTLIGHT 0xc8
> -#define LOCOMO_ALS 0x00 /* Adjust light cycle */
> -#define LOCOMO_ALD 0x04 /* Adjust light duty */
> -
> -#define LOCOMO_ALC_EN 0x8000
> -
> -/* Backlight controller: TFT signal */
> -#define LOCOMO_BACKLIGHT 0x38
> -#define LOCOMO_TC 0x00 /* TFT control signal */
> -#define LOCOMO_CPSD 0x04 /* CPS delay */
> -
> -/* Audio controller */
> -#define LOCOMO_AUDIO 0x54
> -#define LOCOMO_ACC 0x00 /* Audio clock */
> -#define LOCOMO_PAIF 0xD0 /* PCM audio interface */
> -/* Audio clock */
> -#define LOCOMO_ACC_XON 0x80
> -#define LOCOMO_ACC_XEN 0x40
> -#define LOCOMO_ACC_XSEL0 0x00
> -#define LOCOMO_ACC_XSEL1 0x20
> -#define LOCOMO_ACC_MCLKEN 0x10
> -#define LOCOMO_ACC_64FSEN 0x08
> -#define LOCOMO_ACC_CLKSEL000 0x00 /* mclk 2 */
> -#define LOCOMO_ACC_CLKSEL001 0x01 /* mclk 3 */
> -#define LOCOMO_ACC_CLKSEL010 0x02 /* mclk 4 */
> -#define LOCOMO_ACC_CLKSEL011 0x03 /* mclk 6 */
> -#define LOCOMO_ACC_CLKSEL100 0x04 /* mclk 8 */
> -#define LOCOMO_ACC_CLKSEL101 0x05 /* mclk 12 */
> -/* PCM audio interface */
> -#define LOCOMO_PAIF_SCINV 0x20
> -#define LOCOMO_PAIF_SCEN 0x10
> -#define LOCOMO_PAIF_LRCRST 0x08
> -#define LOCOMO_PAIF_LRCEVE 0x04
> -#define LOCOMO_PAIF_LRCINV 0x02
> -#define LOCOMO_PAIF_LRCEN 0x01
> -
> -/* LED controller */
> -#define LOCOMO_LED 0xe8
> -#define LOCOMO_LPT0 0x00
> -#define LOCOMO_LPT1 0x04
> -/* LED control */
> -#define LOCOMO_LPT_TOFH 0x80
> -#define LOCOMO_LPT_TOFL 0x08
> -#define LOCOMO_LPT_TOH(TOH) ((TOH & 0x7) << 4)
> -#define LOCOMO_LPT_TOL(TOL) ((TOL & 0x7))
> -
> -#define LOCOMO_DEVID_KEYBOARD 0
> -#define LOCOMO_DEVID_FRONTLIGHT 1
> -#define LOCOMO_DEVID_BACKLIGHT 2
> -#define LOCOMO_DEVID_AUDIO 3
> -#define LOCOMO_DEVID_LED 4
> -#define LOCOMO_DEVID_UART 5
> -#define LOCOMO_DEVID_SPI 6
> -
> -struct locomo_dev {
> - struct device dev;
> - unsigned int devid;
> - unsigned int irq[1];
> -
> - void *mapbase;
> - unsigned long length;
> -
> - u64 dma_mask;
> -};
> -
> -#define LOCOMO_DEV(_d) container_of((_d), struct locomo_dev, dev)
> -
> -#define locomo_get_drvdata(d) dev_get_drvdata(&(d)->dev)
> -#define locomo_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
> -
> -struct locomo_driver {
> - struct device_driver drv;
> - unsigned int devid;
> - int (*probe)(struct locomo_dev *);
> - void (*remove)(struct locomo_dev *);
> -};
> -
> -#define LOCOMO_DRV(_d) container_of_const((_d), struct locomo_driver, drv)
> -
> -#define LOCOMO_DRIVER_NAME(_ldev) ((_ldev)->dev.driver->name)
> -
> -extern void locomolcd_power(int on);
> -
> -int locomo_driver_register(struct locomo_driver *);
> -void locomo_driver_unregister(struct locomo_driver *);
> -
> -/* GPIO control functions */
> -void locomo_gpio_set_dir(struct device *dev, unsigned int bits, unsigned int dir);
> -int locomo_gpio_read_level(struct device *dev, unsigned int bits);
> -int locomo_gpio_read_output(struct device *dev, unsigned int bits);
> -void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set);
> -
> -/* M62332 control function */
> -void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel);
> -
> -/* Frontlight control */
> -void locomo_frontlight_set(struct locomo_dev *dev, int duty, int vr, int bpwf);
> -
> -struct locomo_platform_data {
> - int irq_base; /* IRQ base for cascaded on-chip IRQs */
> -};
> -
> -#endif
> diff --git a/arch/arm/include/asm/hardware/sa1111.h b/arch/arm/include/asm/hardware/sa1111.h
> deleted file mode 100644
> index 90b6a832108d..000000000000
> --- a/arch/arm/include/asm/hardware/sa1111.h
> +++ /dev/null
> @@ -1,442 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * arch/arm/include/asm/hardware/sa1111.h
> - *
> - * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
> - *
> - * This file contains definitions for the SA-1111 Companion Chip.
> - * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.)
> - *
> - * Macro that calculates real address for registers in the SA-1111
> - */
> -
> -#ifndef _ASM_ARCH_SA1111
> -#define _ASM_ARCH_SA1111
> -
> -/*
> - * Don't ask the (SAC) DMA engines to move less than this amount.
> - */
> -
> -#define SA1111_SAC_DMA_MIN_XFER (0x800)
> -
> -/*
> - * System Bus Interface (SBI)
> - *
> - * Registers
> - * SKCR Control Register
> - * SMCR Shared Memory Controller Register
> - * SKID ID Register
> - */
> -#define SA1111_SKCR 0x0000
> -#define SA1111_SMCR 0x0004
> -#define SA1111_SKID 0x0008
> -
> -#define SKCR_PLL_BYPASS (1<<0)
> -#define SKCR_RCLKEN (1<<1)
> -#define SKCR_SLEEP (1<<2)
> -#define SKCR_DOZE (1<<3)
> -#define SKCR_VCO_OFF (1<<4)
> -#define SKCR_SCANTSTEN (1<<5)
> -#define SKCR_CLKTSTEN (1<<6)
> -#define SKCR_RDYEN (1<<7)
> -#define SKCR_SELAC (1<<8)
> -#define SKCR_OPPC (1<<9)
> -#define SKCR_PLLTSTEN (1<<10)
> -#define SKCR_USBIOTSTEN (1<<11)
> -/*
> - * Don't believe the specs! Take them, throw them outside. Leave them
> - * there for a week. Spit on them. Walk on them. Stamp on them.
> - * Pour gasoline over them and finally burn them. Now think about coding.
> - * - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
> - * - The Feb 2001 errata (278260-010) says that the previous errata
> - * (278260-009) is wrong, and its bit actually 12, fixed in spec
> - * 278242-003.
> - * - The SA1111 manual (278242) says bit 12, but 0 to enable.
> - * - Reality is bit 13, 1 to enable.
> - * -- rmk
> - */
> -#define SKCR_OE_EN (1<<13)
> -
> -#define SMCR_DTIM (1<<0)
> -#define SMCR_MBGE (1<<1)
> -#define SMCR_DRAC_0 (1<<2)
> -#define SMCR_DRAC_1 (1<<3)
> -#define SMCR_DRAC_2 (1<<4)
> -#define SMCR_DRAC Fld(3, 2)
> -#define SMCR_CLAT (1<<5)
> -
> -#define SKID_SIREV_MASK (0x000000f0)
> -#define SKID_MTREV_MASK (0x0000000f)
> -#define SKID_ID_MASK (0xffffff00)
> -#define SKID_SA1111_ID (0x690cc200)
> -
> -/*
> - * System Controller
> - *
> - * Registers
> - * SKPCR Power Control Register
> - * SKCDR Clock Divider Register
> - * SKAUD Audio Clock Divider Register
> - * SKPMC PS/2 Mouse Clock Divider Register
> - * SKPTC PS/2 Track Pad Clock Divider Register
> - * SKPEN0 PWM0 Enable Register
> - * SKPWM0 PWM0 Clock Register
> - * SKPEN1 PWM1 Enable Register
> - * SKPWM1 PWM1 Clock Register
> - */
> -#define SA1111_SKPCR 0x0200
> -#define SA1111_SKCDR 0x0204
> -#define SA1111_SKAUD 0x0208
> -#define SA1111_SKPMC 0x020c
> -#define SA1111_SKPTC 0x0210
> -#define SA1111_SKPEN0 0x0214
> -#define SA1111_SKPWM0 0x0218
> -#define SA1111_SKPEN1 0x021c
> -#define SA1111_SKPWM1 0x0220
> -
> -#define SKPCR_UCLKEN (1<<0)
> -#define SKPCR_ACCLKEN (1<<1)
> -#define SKPCR_I2SCLKEN (1<<2)
> -#define SKPCR_L3CLKEN (1<<3)
> -#define SKPCR_SCLKEN (1<<4)
> -#define SKPCR_PMCLKEN (1<<5)
> -#define SKPCR_PTCLKEN (1<<6)
> -#define SKPCR_DCLKEN (1<<7)
> -#define SKPCR_PWMCLKEN (1<<8)
> -
> -/* USB Host controller */
> -#define SA1111_USB 0x0400
> -
> -/*
> - * Serial Audio Controller
> - *
> - * Registers
> - * SACR0 Serial Audio Common Control Register
> - * SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register
> - * SACR2 Serial Audio AC-link Control Register
> - * SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register
> - * SASR1 Serial Audio AC-link Interface & FIFO Status Register
> - * SASCR Serial Audio Status Clear Register
> - * L3_CAR L3 Control Bus Address Register
> - * L3_CDR L3 Control Bus Data Register
> - * ACCAR AC-link Command Address Register
> - * ACCDR AC-link Command Data Register
> - * ACSAR AC-link Status Address Register
> - * ACSDR AC-link Status Data Register
> - * SADTCS Serial Audio DMA Transmit Control/Status Register
> - * SADTSA Serial Audio DMA Transmit Buffer Start Address A
> - * SADTCA Serial Audio DMA Transmit Buffer Count Register A
> - * SADTSB Serial Audio DMA Transmit Buffer Start Address B
> - * SADTCB Serial Audio DMA Transmit Buffer Count Register B
> - * SADRCS Serial Audio DMA Receive Control/Status Register
> - * SADRSA Serial Audio DMA Receive Buffer Start Address A
> - * SADRCA Serial Audio DMA Receive Buffer Count Register A
> - * SADRSB Serial Audio DMA Receive Buffer Start Address B
> - * SADRCB Serial Audio DMA Receive Buffer Count Register B
> - * SAITR Serial Audio Interrupt Test Register
> - * SADR Serial Audio Data Register (16 x 32-bit)
> - */
> -
> -#define SA1111_SERAUDIO 0x0600
> -
> -/*
> - * These are offsets from the above base.
> - */
> -#define SA1111_SACR0 0x00
> -#define SA1111_SACR1 0x04
> -#define SA1111_SACR2 0x08
> -#define SA1111_SASR0 0x0c
> -#define SA1111_SASR1 0x10
> -#define SA1111_SASCR 0x18
> -#define SA1111_L3_CAR 0x1c
> -#define SA1111_L3_CDR 0x20
> -#define SA1111_ACCAR 0x24
> -#define SA1111_ACCDR 0x28
> -#define SA1111_ACSAR 0x2c
> -#define SA1111_ACSDR 0x30
> -#define SA1111_SADTCS 0x34
> -#define SA1111_SADTSA 0x38
> -#define SA1111_SADTCA 0x3c
> -#define SA1111_SADTSB 0x40
> -#define SA1111_SADTCB 0x44
> -#define SA1111_SADRCS 0x48
> -#define SA1111_SADRSA 0x4c
> -#define SA1111_SADRCA 0x50
> -#define SA1111_SADRSB 0x54
> -#define SA1111_SADRCB 0x58
> -#define SA1111_SAITR 0x5c
> -#define SA1111_SADR 0x80
> -
> -#ifndef CONFIG_ARCH_PXA
> -
> -#define SACR0_ENB (1<<0)
> -#define SACR0_BCKD (1<<2)
> -#define SACR0_RST (1<<3)
> -
> -#define SACR1_AMSL (1<<0)
> -#define SACR1_L3EN (1<<1)
> -#define SACR1_L3MB (1<<2)
> -#define SACR1_DREC (1<<3)
> -#define SACR1_DRPL (1<<4)
> -#define SACR1_ENLBF (1<<5)
> -
> -#define SACR2_TS3V (1<<0)
> -#define SACR2_TS4V (1<<1)
> -#define SACR2_WKUP (1<<2)
> -#define SACR2_DREC (1<<3)
> -#define SACR2_DRPL (1<<4)
> -#define SACR2_ENLBF (1<<5)
> -#define SACR2_RESET (1<<6)
> -
> -#define SASR0_TNF (1<<0)
> -#define SASR0_RNE (1<<1)
> -#define SASR0_BSY (1<<2)
> -#define SASR0_TFS (1<<3)
> -#define SASR0_RFS (1<<4)
> -#define SASR0_TUR (1<<5)
> -#define SASR0_ROR (1<<6)
> -#define SASR0_L3WD (1<<16)
> -#define SASR0_L3RD (1<<17)
> -
> -#define SASR1_TNF (1<<0)
> -#define SASR1_RNE (1<<1)
> -#define SASR1_BSY (1<<2)
> -#define SASR1_TFS (1<<3)
> -#define SASR1_RFS (1<<4)
> -#define SASR1_TUR (1<<5)
> -#define SASR1_ROR (1<<6)
> -#define SASR1_CADT (1<<16)
> -#define SASR1_SADR (1<<17)
> -#define SASR1_RSTO (1<<18)
> -#define SASR1_CLPM (1<<19)
> -#define SASR1_CRDY (1<<20)
> -#define SASR1_RS3V (1<<21)
> -#define SASR1_RS4V (1<<22)
> -
> -#define SASCR_TUR (1<<5)
> -#define SASCR_ROR (1<<6)
> -#define SASCR_DTS (1<<16)
> -#define SASCR_RDD (1<<17)
> -#define SASCR_STO (1<<18)
> -
> -#define SADTCS_TDEN (1<<0)
> -#define SADTCS_TDIE (1<<1)
> -#define SADTCS_TDBDA (1<<3)
> -#define SADTCS_TDSTA (1<<4)
> -#define SADTCS_TDBDB (1<<5)
> -#define SADTCS_TDSTB (1<<6)
> -#define SADTCS_TBIU (1<<7)
> -
> -#define SADRCS_RDEN (1<<0)
> -#define SADRCS_RDIE (1<<1)
> -#define SADRCS_RDBDA (1<<3)
> -#define SADRCS_RDSTA (1<<4)
> -#define SADRCS_RDBDB (1<<5)
> -#define SADRCS_RDSTB (1<<6)
> -#define SADRCS_RBIU (1<<7)
> -
> -#define SAD_CS_DEN (1<<0)
> -#define SAD_CS_DIE (1<<1) /* Not functional on metal 1 */
> -#define SAD_CS_DBDA (1<<3) /* Not functional on metal 1 */
> -#define SAD_CS_DSTA (1<<4)
> -#define SAD_CS_DBDB (1<<5) /* Not functional on metal 1 */
> -#define SAD_CS_DSTB (1<<6)
> -#define SAD_CS_BIU (1<<7) /* Not functional on metal 1 */
> -
> -#define SAITR_TFS (1<<0)
> -#define SAITR_RFS (1<<1)
> -#define SAITR_TUR (1<<2)
> -#define SAITR_ROR (1<<3)
> -#define SAITR_CADT (1<<4)
> -#define SAITR_SADR (1<<5)
> -#define SAITR_RSTO (1<<6)
> -#define SAITR_TDBDA (1<<8)
> -#define SAITR_TDBDB (1<<9)
> -#define SAITR_RDBDA (1<<10)
> -#define SAITR_RDBDB (1<<11)
> -
> -#endif /* !CONFIG_ARCH_PXA */
> -
> -/*
> - * General-Purpose I/O Interface
> - *
> - * Registers
> - * PA_DDR GPIO Block A Data Direction
> - * PA_DRR/PA_DWR GPIO Block A Data Value Register (read/write)
> - * PA_SDR GPIO Block A Sleep Direction
> - * PA_SSR GPIO Block A Sleep State
> - * PB_DDR GPIO Block B Data Direction
> - * PB_DRR/PB_DWR GPIO Block B Data Value Register (read/write)
> - * PB_SDR GPIO Block B Sleep Direction
> - * PB_SSR GPIO Block B Sleep State
> - * PC_DDR GPIO Block C Data Direction
> - * PC_DRR/PC_DWR GPIO Block C Data Value Register (read/write)
> - * PC_SDR GPIO Block C Sleep Direction
> - * PC_SSR GPIO Block C Sleep State
> - */
> -
> -#define SA1111_GPIO 0x1000
> -
> -#define SA1111_GPIO_PADDR (0x000)
> -#define SA1111_GPIO_PADRR (0x004)
> -#define SA1111_GPIO_PADWR (0x004)
> -#define SA1111_GPIO_PASDR (0x008)
> -#define SA1111_GPIO_PASSR (0x00c)
> -#define SA1111_GPIO_PBDDR (0x010)
> -#define SA1111_GPIO_PBDRR (0x014)
> -#define SA1111_GPIO_PBDWR (0x014)
> -#define SA1111_GPIO_PBSDR (0x018)
> -#define SA1111_GPIO_PBSSR (0x01c)
> -#define SA1111_GPIO_PCDDR (0x020)
> -#define SA1111_GPIO_PCDRR (0x024)
> -#define SA1111_GPIO_PCDWR (0x024)
> -#define SA1111_GPIO_PCSDR (0x028)
> -#define SA1111_GPIO_PCSSR (0x02c)
> -
> -#define GPIO_A0 (1 << 0)
> -#define GPIO_A1 (1 << 1)
> -#define GPIO_A2 (1 << 2)
> -#define GPIO_A3 (1 << 3)
> -
> -#define GPIO_B0 (1 << 8)
> -#define GPIO_B1 (1 << 9)
> -#define GPIO_B2 (1 << 10)
> -#define GPIO_B3 (1 << 11)
> -#define GPIO_B4 (1 << 12)
> -#define GPIO_B5 (1 << 13)
> -#define GPIO_B6 (1 << 14)
> -#define GPIO_B7 (1 << 15)
> -
> -#define GPIO_C0 (1 << 16)
> -#define GPIO_C1 (1 << 17)
> -#define GPIO_C2 (1 << 18)
> -#define GPIO_C3 (1 << 19)
> -#define GPIO_C4 (1 << 20)
> -#define GPIO_C5 (1 << 21)
> -#define GPIO_C6 (1 << 22)
> -#define GPIO_C7 (1 << 23)
> -
> -/*
> - * Interrupt Controller
> - *
> - * Registers
> - * INTTEST0 Test register 0
> - * INTTEST1 Test register 1
> - * INTEN0 Interrupt Enable register 0
> - * INTEN1 Interrupt Enable register 1
> - * INTPOL0 Interrupt Polarity selection 0
> - * INTPOL1 Interrupt Polarity selection 1
> - * INTTSTSEL Interrupt source selection
> - * INTSTATCLR0 Interrupt Status/Clear 0
> - * INTSTATCLR1 Interrupt Status/Clear 1
> - * INTSET0 Interrupt source set 0
> - * INTSET1 Interrupt source set 1
> - * WAKE_EN0 Wake-up source enable 0
> - * WAKE_EN1 Wake-up source enable 1
> - * WAKE_POL0 Wake-up polarity selection 0
> - * WAKE_POL1 Wake-up polarity selection 1
> - */
> -#define SA1111_INTC 0x1600
> -
> -/*
> - * These are offsets from the above base.
> - */
> -#define SA1111_INTTEST0 0x0000
> -#define SA1111_INTTEST1 0x0004
> -#define SA1111_INTEN0 0x0008
> -#define SA1111_INTEN1 0x000c
> -#define SA1111_INTPOL0 0x0010
> -#define SA1111_INTPOL1 0x0014
> -#define SA1111_INTTSTSEL 0x0018
> -#define SA1111_INTSTATCLR0 0x001c
> -#define SA1111_INTSTATCLR1 0x0020
> -#define SA1111_INTSET0 0x0024
> -#define SA1111_INTSET1 0x0028
> -#define SA1111_WAKEEN0 0x002c
> -#define SA1111_WAKEEN1 0x0030
> -#define SA1111_WAKEPOL0 0x0034
> -#define SA1111_WAKEPOL1 0x0038
> -
> -/* PS/2 Trackpad and Mouse Interfaces */
> -#define SA1111_KBD 0x0a00
> -#define SA1111_MSE 0x0c00
> -
> -/* PCMCIA Interface */
> -#define SA1111_PCMCIA 0x1600
> -
> -
> -
> -
> -
> -extern const struct bus_type sa1111_bus_type;
> -
> -#define SA1111_DEVID_SBI (1 << 0)
> -#define SA1111_DEVID_SK (1 << 1)
> -#define SA1111_DEVID_USB (1 << 2)
> -#define SA1111_DEVID_SAC (1 << 3)
> -#define SA1111_DEVID_SSP (1 << 4)
> -#define SA1111_DEVID_PS2 (3 << 5)
> -#define SA1111_DEVID_PS2_KBD (1 << 5)
> -#define SA1111_DEVID_PS2_MSE (1 << 6)
> -#define SA1111_DEVID_GPIO (1 << 7)
> -#define SA1111_DEVID_INT (1 << 8)
> -#define SA1111_DEVID_PCMCIA (1 << 9)
> -
> -struct sa1111_dev {
> - struct device dev;
> - unsigned int devid;
> - struct resource res;
> - void __iomem *mapbase;
> - unsigned int skpcr_mask;
> - unsigned int hwirq[6];
> - u64 dma_mask;
> -};
> -
> -#define to_sa1111_device(x) container_of(x, struct sa1111_dev, dev)
> -
> -#define sa1111_get_drvdata(d) dev_get_drvdata(&(d)->dev)
> -#define sa1111_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
> -
> -struct sa1111_driver {
> - struct device_driver drv;
> - unsigned int devid;
> - int (*probe)(struct sa1111_dev *);
> - void (*remove)(struct sa1111_dev *);
> -};
> -
> -#define SA1111_DRV(_d) container_of_const((_d), struct sa1111_driver, drv)
> -
> -#define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name)
> -
> -/*
> - * These frob the SKPCR register, and call platform specific
> - * enable/disable functions.
> - */
> -int sa1111_enable_device(struct sa1111_dev *);
> -void sa1111_disable_device(struct sa1111_dev *);
> -
> -int sa1111_get_irq(struct sa1111_dev *, unsigned num);
> -
> -unsigned int sa1111_pll_clock(struct sa1111_dev *);
> -
> -#define SA1111_AUDIO_ACLINK 0
> -#define SA1111_AUDIO_I2S 1
> -
> -void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode);
> -int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate);
> -int sa1111_get_audio_rate(struct sa1111_dev *sadev);
> -
> -int sa1111_check_dma_bug(dma_addr_t addr);
> -
> -int sa1111_driver_register(struct sa1111_driver *);
> -void sa1111_driver_unregister(struct sa1111_driver *);
> -
> -struct sa1111_platform_data {
> - int irq_base; /* base for cascaded on-chip IRQs */
> - unsigned disable_devs;
> - void *data;
> - int (*enable)(void *, unsigned);
> - void (*disable)(void *, unsigned);
> -};
> -
> -#endif /* _ASM_ARCH_SA1111 */
> diff --git a/arch/arm/include/asm/hardware/ssp.h b/arch/arm/include/asm/hardware/ssp.h
> deleted file mode 100644
> index 72d176790308..000000000000
> --- a/arch/arm/include/asm/hardware/ssp.h
> +++ /dev/null
> @@ -1,25 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * ssp.h
> - *
> - * Copyright (C) 2003 Russell King, All Rights Reserved.
> - */
> -#ifndef SSP_H
> -#define SSP_H
> -
> -struct ssp_state {
> - unsigned int cr0;
> - unsigned int cr1;
> -};
> -
> -int ssp_write_word(u16 data);
> -int ssp_read_word(u16 *data);
> -int ssp_flush(void);
> -void ssp_enable(void);
> -void ssp_disable(void);
> -void ssp_save_state(struct ssp_state *ssp);
> -void ssp_restore_state(struct ssp_state *ssp);
> -int ssp_init(void);
> -void ssp_exit(void);
> -
> -#endif
> diff --git a/arch/arm/include/debug/sa1100.S b/arch/arm/include/debug/sa1100.S
> deleted file mode 100644
> index 7968ea52df3d..000000000000
> --- a/arch/arm/include/debug/sa1100.S
> +++ /dev/null
> @@ -1,67 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/* arch/arm/include/debug/sa1100.S
> - *
> - * Debugging macro include header
> - *
> - * Copyright (C) 1994-1999 Russell King
> - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
> -*/
> -
> -#define UTCR3 0x0c
> -#define UTDR 0x14
> -#define UTSR1 0x20
> -#define UTCR3_TXE 0x00000002 /* Transmit Enable */
> -#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
> -#define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
> -
> - .macro addruart, rp, rv, tmp
> - mrc p15, 0, \rp, c1, c0
> - tst \rp, #1 @ MMU enabled?
> - moveq \rp, #0x80000000 @ physical base address
> - movne \rp, #0xf8000000 @ virtual address
> -
> - @ We probe for the active serial port here, coherently with
> - @ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.
> - @ We assume r1 can be clobbered.
> -
> - @ see if Ser3 is active
> - add \rp, \rp, #0x00050000
> - ldr \rv, [\rp, #UTCR3]
> - tst \rv, #UTCR3_TXE
> -
> - @ if Ser3 is inactive, then try Ser1
> - addeq \rp, \rp, #(0x00010000 - 0x00050000)
> - ldreq \rv, [\rp, #UTCR3]
> - tsteq \rv, #UTCR3_TXE
> -
> - @ if Ser1 is inactive, then try Ser2
> - addeq \rp, \rp, #(0x00030000 - 0x00010000)
> - ldreq \rv, [\rp, #UTCR3]
> - tsteq \rv, #UTCR3_TXE
> -
> - @ clear top bits, and generate both phys and virt addresses
> - lsl \rp, \rp, #8
> - lsr \rp, \rp, #8
> - orr \rv, \rp, #0xf8000000 @ virtual
> - orr \rp, \rp, #0x80000000 @ physical
> -
> - .endm
> -
> - .macro senduart,rd,rx
> - str \rd, [\rx, #UTDR]
> - .endm
> -
> - .macro waituartcts,rd,rx
> - .endm
> -
> - .macro waituarttxrdy,rd,rx
> -1001: ldr \rd, [\rx, #UTSR1]
> - tst \rd, #UTSR1_TNF
> - beq 1001b
> - .endm
> -
> - .macro busyuart,rd,rx
> -1001: ldr \rd, [\rx, #UTSR1]
> - tst \rd, #UTSR1_TBY
> - bne 1001b
> - .endm
> diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
> deleted file mode 100644
> index d50721e39641..000000000000
> --- a/arch/arm/mach-sa1100/Kconfig
> +++ /dev/null
> @@ -1,92 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0-only
> -menuconfig ARCH_SA1100
> - bool "SA11x0 Implementations (DEPRECATED)"
> - depends on ARCH_MULTI_V4 && !(ARCH_MULTI_V4T || ARCH_MULTI_V5)
> - depends on !(ARCH_MOXART || ARCH_GEMINI)
> - depends on ATAGS
> - depends on CPU_LITTLE_ENDIAN
> - depends on MMU
> - select ARCH_NO_SG_CHAIN
> - select ARCH_MTD_XIP
> - select CLKSRC_MMIO
> - select CLKSRC_PXA
> - select CPU_FREQ
> - select CPU_SA1100
> - select GPIOLIB
> - select GPIOLIB_LEGACY
> - select IRQ_DOMAIN
> - select ISA
> - select NEED_MACH_MEMORY_H
> - help
> - Support for StrongARM 11x0 based boards.
> -
> - Support for these machines will go away in 2027,
> - unless there are any remaining users that speak up.
> -
> -if ARCH_SA1100
> -
> -config SA1100_ASSABET
> - bool "Assabet"
> - select ARM_SA1110_CPUFREQ
> - select GPIO_REG
> - select LEDS_GPIO_REGISTER
> - select REGULATOR
> - select REGULATOR_FIXED_VOLTAGE
> - help
> - Say Y here if you are using the Intel(R) StrongARM(R) SA-1110
> - Microprocessor Development Board (also known as the Assabet).
> -
> -config ASSABET_NEPONSET
> - bool "Include support for Neponset"
> - depends on SA1100_ASSABET
> - select SA1111
> - help
> - Say Y here if you are using the Intel(R) StrongARM(R) SA-1110
> - Microprocessor Development Board (Assabet) with the SA-1111
> - Development Board (Nepon).
> -
> -config SA1100_COLLIE
> - bool "Sharp Zaurus SL5500"
> - # FIXME: select ARM_SA11x0_CPUFREQ
> - select SHARP_LOCOMO
> - select SHARP_PARAM
> - select SHARP_SCOOP
> - help
> - Say Y here to support the Sharp Zaurus SL5500 PDAs.
> -
> -config SA1100_H3600
> - bool "Compaq iPAQ H3600/H3700"
> - select ARM_SA1110_CPUFREQ
> - select HTC_EGPIO
> - select MFD_IPAQ_MICRO
> - help
> - Say Y here if you intend to run this kernel on the Compaq iPAQ
> - H3600 and H3700 handheld computers.
> -
> -config SA1100_JORNADA720
> - bool "HP Jornada 720"
> - # FIXME: select ARM_SA11x0_CPUFREQ
> - select SA1111
> - help
> - Say Y here if you want to build a kernel for the HP Jornada 720
> - handheld computer. See
> - <http://h10025.www1.hp.com/ewfrf/wc/product?product=61677&cc=us&lc=en&dlc=en&product=61677#>
> -
> -config SA1100_JORNADA720_SSP
> - bool "HP Jornada 720 Extended SSP driver"
> - depends on SA1100_JORNADA720
> - select SA1100_SSP
> - help
> - Say Y here if you have a HP Jornada 7xx handheld computer and you
> - want to access devices connected to the MCU. Those include the
> - keyboard, touchscreen, backlight and battery. This driver also activates
> - the generic SSP which it extends.
> -
> -config SA1100_SSP
> - tristate "Generic PIO SSP"
> - help
> - Say Y here to enable support for the generic PIO SSP driver.
> - This isn't for audio support, but for attached sensors and
> - other devices, eg for BadgePAD 4 sensor support.
> -
> -endif
> diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
> deleted file mode 100644
> index b5816d675152..000000000000
> --- a/arch/arm/mach-sa1100/Makefile
> +++ /dev/null
> @@ -1,20 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0
> -#
> -# Makefile for the linux kernel.
> -#
> -
> -# Common support
> -obj-y := clock.o generic.o #nmi-oopser.o
> -
> -# Specific board support
> -obj-$(CONFIG_SA1100_ASSABET) += assabet.o
> -obj-$(CONFIG_ASSABET_NEPONSET) += neponset.o
> -obj-$(CONFIG_SA1100_COLLIE) += collie.o
> -obj-$(CONFIG_SA1100_H3600) += h3600.o h3xxx.o
> -obj-$(CONFIG_SA1100_JORNADA720) += jornada720.o
> -obj-$(CONFIG_SA1100_JORNADA720_SSP) += jornada720_ssp.o
> -
> -# Miscellaneous functions
> -obj-$(CONFIG_PM) += pm.o sleep.o
> -obj-$(CONFIG_SA1100_SSP) += ssp.o
> -
> diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
> deleted file mode 100644
> index b001f0b6a3fa..000000000000
> --- a/arch/arm/mach-sa1100/assabet.c
> +++ /dev/null
> @@ -1,770 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * linux/arch/arm/mach-sa1100/assabet.c
> - *
> - * Author: Nicolas Pitre
> - *
> - * This file contains all Assabet-specific tweaks.
> - */
> -#include <linux/init.h>
> -#include <linux/kernel.h>
> -#include <linux/module.h>
> -#include <linux/errno.h>
> -#include <linux/gpio/driver.h>
> -#include <linux/gpio/gpio-reg.h>
> -#include <linux/gpio/machine.h>
> -#include <linux/gpio/property.h>
> -#include <linux/input.h>
> -#include <linux/ioport.h>
> -#include <linux/property.h>
> -#include <linux/platform_data/sa11x0-serial.h>
> -#include <linux/regulator/fixed.h>
> -#include <linux/regulator/machine.h>
> -#include <linux/serial_core.h>
> -#include <linux/platform_device.h>
> -#include <linux/mfd/ucb1x00.h>
> -#include <linux/mtd/mtd.h>
> -#include <linux/mtd/partitions.h>
> -#include <linux/delay.h>
> -#include <linux/mm.h>
> -#include <linux/leds.h>
> -#include <linux/slab.h>
> -
> -#include <video/sa1100fb.h>
> -
> -#include <mach/hardware.h>
> -#include <asm/mach-types.h>
> -#include <asm/setup.h>
> -#include <asm/page.h>
> -#include <asm/pgtable-hwdef.h>
> -#include <asm/tlbflush.h>
> -
> -#include <asm/mach/arch.h>
> -#include <asm/mach/flash.h>
> -#include <asm/mach/map.h>
> -#include <mach/assabet.h>
> -#include <linux/platform_data/mfd-mcp-sa11x0.h>
> -#include <mach/irqs.h>
> -
> -#include "generic.h"
> -
> -#define ASSABET_BCR_DB1110 \
> - (ASSABET_BCR_SPK_OFF | \
> - ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \
> - ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \
> - ASSABET_BCR_IRDA_MD0)
> -
> -#define ASSABET_BCR_DB1111 \
> - (ASSABET_BCR_SPK_OFF | \
> - ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \
> - ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \
> - ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \
> - ASSABET_BCR_IRDA_MD0 | ASSABET_BCR_CF_RST)
> -
> -unsigned long SCR_value = ASSABET_SCR_INIT;
> -EXPORT_SYMBOL(SCR_value);
> -
> -static struct gpio_chip *assabet_bcr_gc;
> -
> -static const char *assabet_names[] = {
> - "cf_pwr", "cf_gfx_reset", "nsoft_reset", "irda_fsel",
> - "irda_md0", "irda_md1", "stereo_loopback", "ncf_bus_on",
> - "audio_pwr_on", "light_pwr_on", "lcd16data", "lcd_pwr_on",
> - "rs232_on", "nred_led", "ngreen_led", "vib_on",
> - "com_dtr", "com_rts", "radio_wake_mod", "i2c_enab",
> - "tvir_enab", "qmute", "radio_pwr_on", "spkr_off",
> - "rs232_valid", "com_dcd", "com_cts", "com_dsr",
> - "radio_cts", "radio_dsr", "radio_dcd", "radio_ri",
> -};
> -
> -/* The old deprecated interface */
> -void ASSABET_BCR_frob(unsigned int mask, unsigned int val)
> -{
> - unsigned long m = mask, v = val;
> -
> - assabet_bcr_gc->set_multiple(assabet_bcr_gc, &m, &v);
> -}
> -EXPORT_SYMBOL(ASSABET_BCR_frob);
> -
> -static void __init assabet_init_gpio(void __iomem *reg, u32 def_val)
> -{
> - struct gpio_chip *gc;
> -
> - writel_relaxed(def_val, reg);
> -
> - gc = gpio_reg_init(NULL, reg, -1, 32, "assabet", 0xff000000, def_val,
> - assabet_names, NULL, NULL);
> -
> - if (IS_ERR(gc))
> - return;
> -
> - assabet_bcr_gc = gc;
> -}
> -
> -/*
> - * The codec reset goes to three devices, so we need to release
> - * the rest when any one of these requests it. However, that
> - * causes the ADV7171 to consume around 100mA - more than half
> - * the LCD-blanked power.
> - *
> - * With the ADV7171, LCD and backlight enabled, we go over
> - * budget on the MAX846 Li-Ion charger, and if no Li-Ion battery
> - * is connected, the Assabet crashes.
> - */
> -#define RST_UCB1X00 (1 << 0)
> -#define RST_UDA1341 (1 << 1)
> -#define RST_ADV7171 (1 << 2)
> -
> -#define SDA GPIO_GPIO(15)
> -#define SCK GPIO_GPIO(18)
> -#define MOD GPIO_GPIO(17)
> -
> -static void adv7171_start(void)
> -{
> - GPSR = SCK;
> - udelay(1);
> - GPSR = SDA;
> - udelay(2);
> - GPCR = SDA;
> -}
> -
> -static void adv7171_stop(void)
> -{
> - GPSR = SCK;
> - udelay(2);
> - GPSR = SDA;
> - udelay(1);
> -}
> -
> -static void adv7171_send(unsigned byte)
> -{
> - unsigned i;
> -
> - for (i = 0; i < 8; i++, byte <<= 1) {
> - GPCR = SCK;
> - udelay(1);
> - if (byte & 0x80)
> - GPSR = SDA;
> - else
> - GPCR = SDA;
> - udelay(1);
> - GPSR = SCK;
> - udelay(1);
> - }
> - GPCR = SCK;
> - udelay(1);
> - GPSR = SDA;
> - udelay(1);
> - GPDR &= ~SDA;
> - GPSR = SCK;
> - udelay(1);
> - if (GPLR & SDA)
> - printk(KERN_WARNING "No ACK from ADV7171\n");
> - udelay(1);
> - GPCR = SCK | SDA;
> - udelay(1);
> - GPDR |= SDA;
> - udelay(1);
> -}
> -
> -static void adv7171_write(unsigned reg, unsigned val)
> -{
> - unsigned gpdr = GPDR;
> - unsigned gplr = GPLR;
> -
> - ASSABET_BCR_frob(ASSABET_BCR_AUDIO_ON, ASSABET_BCR_AUDIO_ON);
> - udelay(100);
> -
> - GPCR = SDA | SCK | MOD; /* clear L3 mode to ensure UDA1341 doesn't respond */
> - GPDR = (GPDR | SCK | MOD) & ~SDA;
> - udelay(10);
> - if (!(GPLR & SDA))
> - printk(KERN_WARNING "Something dragging SDA down?\n");
> - GPDR |= SDA;
> -
> - adv7171_start();
> - adv7171_send(0x54);
> - adv7171_send(reg);
> - adv7171_send(val);
> - adv7171_stop();
> -
> - /* Restore GPIO state for L3 bus */
> - GPSR = gplr & (SDA | SCK | MOD);
> - GPCR = (~gplr) & (SDA | SCK | MOD);
> - GPDR = gpdr;
> -}
> -
> -static void adv7171_sleep(void)
> -{
> - /* Put the ADV7171 into sleep mode */
> - adv7171_write(0x04, 0x40);
> -}
> -
> -static unsigned codec_nreset;
> -
> -static void assabet_codec_reset(unsigned mask, int set)
> -{
> - unsigned long flags;
> - bool old;
> -
> - local_irq_save(flags);
> - old = !codec_nreset;
> - if (set)
> - codec_nreset &= ~mask;
> - else
> - codec_nreset |= mask;
> -
> - if (old != !codec_nreset) {
> - if (codec_nreset) {
> - ASSABET_BCR_set(ASSABET_BCR_NCODEC_RST);
> - adv7171_sleep();
> - } else {
> - ASSABET_BCR_clear(ASSABET_BCR_NCODEC_RST);
> - }
> - }
> - local_irq_restore(flags);
> -}
> -
> -static void assabet_ucb1x00_reset(enum ucb1x00_reset state)
> -{
> - int set = state == UCB_RST_REMOVE || state == UCB_RST_SUSPEND ||
> - state == UCB_RST_PROBE_FAIL;
> - assabet_codec_reset(RST_UCB1X00, set);
> -}
> -
> -void assabet_uda1341_reset(int set)
> -{
> - assabet_codec_reset(RST_UDA1341, set);
> -}
> -EXPORT_SYMBOL(assabet_uda1341_reset);
> -
> -
> -/*
> - * Assabet flash support code.
> - */
> -
> -#ifdef ASSABET_REV_4
> -/*
> - * Phase 4 Assabet has two 28F160B3 flash parts in bank 0:
> - */
> -static struct mtd_partition assabet_partitions[] = {
> - {
> - .name = "bootloader",
> - .size = 0x00020000,
> - .offset = 0,
> - .mask_flags = MTD_WRITEABLE,
> - }, {
> - .name = "bootloader params",
> - .size = 0x00020000,
> - .offset = MTDPART_OFS_APPEND,
> - .mask_flags = MTD_WRITEABLE,
> - }, {
> - .name = "jffs",
> - .size = MTDPART_SIZ_FULL,
> - .offset = MTDPART_OFS_APPEND,
> - }
> -};
> -#else
> -/*
> - * Phase 5 Assabet has two 28F128J3A flash parts in bank 0:
> - */
> -static struct mtd_partition assabet_partitions[] = {
> - {
> - .name = "bootloader",
> - .size = 0x00040000,
> - .offset = 0,
> - .mask_flags = MTD_WRITEABLE,
> - }, {
> - .name = "bootloader params",
> - .size = 0x00040000,
> - .offset = MTDPART_OFS_APPEND,
> - .mask_flags = MTD_WRITEABLE,
> - }, {
> - .name = "jffs",
> - .size = MTDPART_SIZ_FULL,
> - .offset = MTDPART_OFS_APPEND,
> - }
> -};
> -#endif
> -
> -static struct flash_platform_data assabet_flash_data = {
> - .map_name = "cfi_probe",
> - .parts = assabet_partitions,
> - .nr_parts = ARRAY_SIZE(assabet_partitions),
> -};
> -
> -static struct resource assabet_flash_resources[] = {
> - DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
> - DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M),
> -};
> -
> -
> -static struct ucb1x00_plat_data assabet_ucb1x00_data = {
> - .reset = assabet_ucb1x00_reset,
> - .gpio_base = -1,
> - .can_wakeup = 1,
> -};
> -
> -static struct mcp_plat_data assabet_mcp_data = {
> - .mccr0 = MCCR0_ADM,
> - .sclk_rate = 11981000,
> - .codec_pdata = &assabet_ucb1x00_data,
> -};
> -
> -static void assabet_lcd_set_visual(u32 visual)
> -{
> - u_int is_true_color = visual == FB_VISUAL_TRUECOLOR;
> -
> - if (machine_is_assabet()) {
> -#if 1 // phase 4 or newer Assabet's
> - if (is_true_color)
> - ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
> - else
> - ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
> -#else
> - // older Assabet's
> - if (is_true_color)
> - ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
> - else
> - ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
> -#endif
> - }
> -}
> -
> -#ifndef ASSABET_PAL_VIDEO
> -static void assabet_lcd_backlight_power(int on)
> -{
> - if (on)
> - ASSABET_BCR_set(ASSABET_BCR_LIGHT_ON);
> - else
> - ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
> -}
> -
> -/*
> - * Turn on/off the backlight. When turning the backlight on, we wait
> - * 500us after turning it on so we don't cause the supplies to droop
> - * when we enable the LCD controller (and cause a hard reset.)
> - */
> -static void assabet_lcd_power(int on)
> -{
> - if (on) {
> - ASSABET_BCR_set(ASSABET_BCR_LCD_ON);
> - udelay(500);
> - } else
> - ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
> -}
> -
> -/*
> - * The assabet uses a sharp LQ039Q2DS54 LCD module. It is actually
> - * takes an RGB666 signal, but we provide it with an RGB565 signal
> - * instead (def_rgb_16).
> - */
> -static struct sa1100fb_mach_info lq039q2ds54_info = {
> - .pixclock = 171521, .bpp = 16,
> - .xres = 320, .yres = 240,
> -
> - .hsync_len = 5, .vsync_len = 1,
> - .left_margin = 61, .upper_margin = 3,
> - .right_margin = 9, .lower_margin = 0,
> -
> - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
> -
> - .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
> - .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
> -
> - .backlight_power = assabet_lcd_backlight_power,
> - .lcd_power = assabet_lcd_power,
> - .set_visual = assabet_lcd_set_visual,
> -};
> -#else
> -static void assabet_pal_backlight_power(int on)
> -{
> - ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
> -}
> -
> -static void assabet_pal_power(int on)
> -{
> - ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
> -}
> -
> -static struct sa1100fb_mach_info pal_info = {
> - .pixclock = 67797, .bpp = 16,
> - .xres = 640, .yres = 512,
> -
> - .hsync_len = 64, .vsync_len = 6,
> - .left_margin = 125, .upper_margin = 70,
> - .right_margin = 115, .lower_margin = 36,
> -
> - .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
> - .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
> -
> - .backlight_power = assabet_pal_backlight_power,
> - .lcd_power = assabet_pal_power,
> - .set_visual = assabet_lcd_set_visual,
> -};
> -#endif
> -
> -#ifdef CONFIG_ASSABET_NEPONSET
> -static struct resource neponset_resources[] = {
> - DEFINE_RES_MEM(0x10000000, 0x08000000),
> - DEFINE_RES_MEM(0x18000000, 0x04000000),
> - DEFINE_RES_MEM(0x40000000, SZ_8K),
> - DEFINE_RES_IRQ(IRQ_GPIO25),
> -};
> -#endif
> -
> -static struct gpiod_lookup_table assabet_cf_gpio_table = {
> - .dev_id = "sa11x0-pcmcia.1",
> - .table = {
> - GPIO_LOOKUP("gpio", 21, "ready", GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP("gpio", 22, "detect", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("gpio", 24, "bvd2", GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP("gpio", 25, "bvd1", GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP("assabet", 1, "reset", GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP("assabet", 7, "bus-enable", GPIO_ACTIVE_LOW),
> - { },
> - },
> -};
> -
> -static struct regulator_consumer_supply assabet_cf_vcc_consumers[] = {
> - REGULATOR_SUPPLY("vcc", "sa11x0-pcmcia.1"),
> -};
> -
> -static struct fixed_voltage_config assabet_cf_vcc_pdata __initdata = {
> - .supply_name = "cf-power",
> - .microvolts = 3300000,
> -};
> -
> -static struct gpiod_lookup_table assabet_cf_vcc_gpio_table = {
> - .dev_id = "reg-fixed-voltage.0",
> - .table = {
> - GPIO_LOOKUP("assabet", 0, NULL, GPIO_ACTIVE_HIGH),
> - { },
> - },
> -};
> -
> -static struct gpiod_lookup_table assabet_leds_gpio_table = {
> - .dev_id = "leds-gpio",
> - .table = {
> - GPIO_LOOKUP("assabet", 13, NULL, GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("assabet", 14, NULL, GPIO_ACTIVE_LOW),
> - { },
> - },
> -};
> -
> -static struct gpio_led assabet_leds[] __initdata = {
> - {
> - .name = "assabet:red",
> - .default_trigger = "cpu0",
> - .default_state = LEDS_GPIO_DEFSTATE_KEEP,
> - }, {
> - .name = "assabet:green",
> - .default_trigger = "heartbeat",
> - .default_state = LEDS_GPIO_DEFSTATE_KEEP,
> - },
> -};
> -
> -static const struct gpio_led_platform_data assabet_leds_pdata __initconst = {
> - .num_leds = ARRAY_SIZE(assabet_leds),
> - .leds = assabet_leds,
> -};
> -
> -static const struct software_node assabet_gpio_keys_node = {
> - .name = "assabet-gpio-keys",
> -};
> -
> -static const struct property_entry assabet_key0_props[] = {
> - PROPERTY_ENTRY_U32("linux,code", KEY_RESERVED),
> - PROPERTY_ENTRY_GPIO("gpios", &sa1100_gpiochip_node,
> - 0, GPIO_ACTIVE_HIGH),
> - PROPERTY_ENTRY_STRING("label", "gpio0"),
> - PROPERTY_ENTRY_BOOL("wakeup-source"),
> - PROPERTY_ENTRY_BOOL("linux,can-disable"),
> - PROPERTY_ENTRY_U32("debounce-interval", 5),
> - { }
> -};
> -
> -static const struct software_node assabet_key0_node = {
> - .parent = &assabet_gpio_keys_node,
> - .properties = assabet_key0_props,
> -};
> -
> -static const struct property_entry assabet_key1_props[] = {
> - PROPERTY_ENTRY_U32("linux,code", KEY_RESERVED),
> - PROPERTY_ENTRY_GPIO("gpios", &sa1100_gpiochip_node,
> - 1, GPIO_ACTIVE_HIGH),
> - PROPERTY_ENTRY_STRING("label", "gpio1"),
> - PROPERTY_ENTRY_BOOL("wakeup-source"),
> - PROPERTY_ENTRY_BOOL("linux,can-disable"),
> - PROPERTY_ENTRY_U32("debounce-interval", 5),
> - { }
> -};
> -
> -static const struct software_node assabet_key1_node = {
> - .parent = &assabet_gpio_keys_node,
> - .properties = assabet_key1_props,
> -};
> -
> -static const struct software_node * const assabet_gpio_keys_swnodes[] __initconst = {
> - &assabet_gpio_keys_node,
> - &assabet_key0_node,
> - &assabet_key1_node,
> - NULL
> -};
> -
> -static const struct platform_device_info assabet_gpio_keys_dev_info __initconst = {
> - .name = "gpio-keys",
> - .id = PLATFORM_DEVID_NONE,
> - .swnode = &assabet_gpio_keys_node,
> -};
> -
> -static struct gpiod_lookup_table assabet_uart1_gpio_table = {
> - .dev_id = "sa11x0-uart.1",
> - .table = {
> - GPIO_LOOKUP("assabet", 16, "dtr", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("assabet", 17, "rts", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("assabet", 25, "dcd", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("assabet", 26, "cts", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("assabet", 27, "dsr", GPIO_ACTIVE_LOW),
> - { },
> - },
> -};
> -
> -static struct gpiod_lookup_table assabet_uart3_gpio_table = {
> - .dev_id = "sa11x0-uart.3",
> - .table = {
> - GPIO_LOOKUP("assabet", 28, "cts", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("assabet", 29, "dsr", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("assabet", 30, "dcd", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("assabet", 31, "rng", GPIO_ACTIVE_LOW),
> - { },
> - },
> -};
> -
> -static void __init assabet_init(void)
> -{
> - /*
> - * Ensure that the power supply is in "high power" mode.
> - */
> - GPSR = GPIO_GPIO16;
> - GPDR |= GPIO_GPIO16;
> -
> - /*
> - * Ensure that these pins are set as outputs and are driving
> - * logic 0. This ensures that we won't inadvertently toggle
> - * the WS latch in the CPLD, and we don't float causing
> - * excessive power drain. --rmk
> - */
> - GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
> - GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
> -
> - /*
> - * Also set GPIO27 as an output; this is used to clock UART3
> - * via the FPGA and as otherwise has no pullups or pulldowns,
> - * so stop it floating.
> - */
> - GPCR = GPIO_GPIO27;
> - GPDR |= GPIO_GPIO27;
> -
> - /*
> - * Set up registers for sleep mode.
> - */
> - PWER = PWER_GPIO0;
> - PGSR = 0;
> - PCFR = 0;
> - PSDR = 0;
> - PPDR |= PPC_TXD3 | PPC_TXD1;
> - PPSR |= PPC_TXD3 | PPC_TXD1;
> -
> - sa11x0_ppc_configure_mcp();
> -
> - if (machine_has_neponset()) {
> -#ifndef CONFIG_ASSABET_NEPONSET
> - printk( "Warning: Neponset detected but full support "
> - "hasn't been configured in the kernel\n" );
> -#else
> - platform_device_register_simple("neponset", 0,
> - neponset_resources, ARRAY_SIZE(neponset_resources));
> -#endif
> - } else {
> - gpiod_add_lookup_table(&assabet_uart1_gpio_table);
> - gpiod_add_lookup_table(&assabet_uart3_gpio_table);
> - gpiod_add_lookup_table(&assabet_cf_vcc_gpio_table);
> -
> - sa11x0_register_fixed_regulator(0, &assabet_cf_vcc_pdata,
> - assabet_cf_vcc_consumers,
> - ARRAY_SIZE(assabet_cf_vcc_consumers),
> - true);
> -
> - }
> -
> - software_node_register_node_group(assabet_gpio_keys_swnodes);
> - platform_device_register_full(&assabet_gpio_keys_dev_info);
> -
> - gpiod_add_lookup_table(&assabet_leds_gpio_table);
> - gpio_led_register_device(-1, &assabet_leds_pdata);
> -
> -#ifndef ASSABET_PAL_VIDEO
> - sa11x0_register_lcd(&lq039q2ds54_info);
> -#else
> - sa11x0_register_lcd(&pal_video);
> -#endif
> - sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources,
> - ARRAY_SIZE(assabet_flash_resources));
> - sa11x0_register_mcp(&assabet_mcp_data);
> -
> - if (!machine_has_neponset())
> - sa11x0_register_pcmcia(1, &assabet_cf_gpio_table);
> -}
> -
> -/*
> - * On Assabet, we must probe for the Neponset board _before_
> - * paging_init() has occurred to actually determine the amount
> - * of RAM available. To do so, we map the appropriate IO section
> - * in the page table here in order to access GPIO registers.
> - */
> -static void __init map_sa1100_gpio_regs( void )
> -{
> - unsigned long phys = __PREG(GPLR) & PMD_MASK;
> - unsigned long virt = (unsigned long)io_p2v(phys);
> - int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO);
> - pmd_t *pmd;
> -
> - pmd = pmd_off_k(virt);
> - *pmd = __pmd(phys | prot);
> - flush_pmd_entry(pmd);
> -}
> -
> -/*
> - * Read System Configuration "Register"
> - * (taken from "Intel StrongARM SA-1110 Microprocessor Development Board
> - * User's Guide", section 4.4.1)
> - *
> - * This same scan is performed in arch/arm/boot/compressed/head-sa1100.S
> - * to set up the serial port for decompression status messages. We
> - * repeat it here because the kernel may not be loaded as a zImage, and
> - * also because it's a hassle to communicate the SCR value to the kernel
> - * from the decompressor.
> - *
> - * Note that IRQs are guaranteed to be disabled.
> - */
> -static void __init get_assabet_scr(void)
> -{
> - unsigned long scr, i;
> -
> - GPDR |= 0x3fc; /* Configure GPIO 9:2 as outputs */
> - GPSR = 0x3fc; /* Write 0xFF to GPIO 9:2 */
> - GPDR &= ~(0x3fc); /* Configure GPIO 9:2 as inputs */
> - for(i = 100; i--; ) /* Read GPIO 9:2 */
> - scr = GPLR;
> - GPDR |= 0x3fc; /* restore correct pin direction */
> - scr &= 0x3fc; /* save as system configuration byte. */
> - SCR_value = scr;
> -}
> -
> -static void __init
> -fixup_assabet(struct tag *tags, char **cmdline)
> -{
> - /* This must be done before any call to machine_has_neponset() */
> - map_sa1100_gpio_regs();
> - get_assabet_scr();
> -
> - if (machine_has_neponset())
> - printk("Neponset expansion board detected\n");
> -}
> -
> -
> -static void assabet_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
> -{
> - if (port->mapbase == _Ser1UTCR0) {
> - if (state)
> - ASSABET_BCR_clear(ASSABET_BCR_RS232EN);
> - else
> - ASSABET_BCR_set(ASSABET_BCR_RS232EN);
> - }
> -}
> -
> -static struct sa1100_port_fns assabet_port_fns __initdata = {
> - .pm = assabet_uart_pm,
> -};
> -
> -static struct map_desc assabet_io_desc[] __initdata = {
> - { /* Board Control Register */
> - .virtual = 0xf1000000,
> - .pfn = __phys_to_pfn(0x12000000),
> - .length = 0x00100000,
> - .type = MT_DEVICE
> - }, { /* MQ200 */
> - .virtual = 0xf2800000,
> - .pfn = __phys_to_pfn(0x4b800000),
> - .length = 0x00800000,
> - .type = MT_DEVICE
> - }
> -};
> -
> -static void __init assabet_map_io(void)
> -{
> - sa1100_map_io();
> - iotable_init(assabet_io_desc, ARRAY_SIZE(assabet_io_desc));
> -
> - /*
> - * Set SUS bit in SDCR0 so serial port 1 functions.
> - * Its called GPCLKR0 in my SA1110 manual.
> - */
> - Ser1SDCR0 |= SDCR0_SUS;
> - MSC1 = (MSC1 & ~0xffff) |
> - MSC_NonBrst | MSC_32BitStMem |
> - MSC_RdAcc(2) | MSC_WrAcc(2) | MSC_Rec(0);
> -
> - if (!machine_has_neponset())
> - sa1100_register_uart_fns(&assabet_port_fns);
> -
> - /*
> - * When Neponset is attached, the first UART should be
> - * UART3. That's what Angel is doing and many documents
> - * are stating this.
> - *
> - * We do the Neponset mapping even if Neponset support
> - * isn't compiled in so the user will still get something on
> - * the expected physical serial port.
> - *
> - * We no longer do this; not all boot loaders support it,
> - * and UART3 appears to be somewhat unreliable with blob.
> - */
> - sa1100_register_uart(0, 1);
> - sa1100_register_uart(2, 3);
> -}
> -
> -static void __init assabet_init_irq(void)
> -{
> - u32 def_val;
> -
> - sa1100_init_irq();
> -
> - if (machine_has_neponset())
> - def_val = ASSABET_BCR_DB1111;
> - else
> - def_val = ASSABET_BCR_DB1110;
> -
> - /*
> - * Angel sets this, but other bootloaders may not.
> - *
> - * This must precede any driver calls to BCR_set() or BCR_clear().
> - */
> - assabet_init_gpio((void *)&ASSABET_BCR, def_val);
> -}
> -
> -MACHINE_START(ASSABET, "Intel-Assabet")
> - .atag_offset = 0x100,
> - .fixup = fixup_assabet,
> - .map_io = assabet_map_io,
> - .nr_irqs = SA1100_NR_IRQS,
> - .init_irq = assabet_init_irq,
> - .init_time = sa1100_timer_init,
> - .init_machine = assabet_init,
> - .init_late = sa11x0_init_late,
> -#ifdef CONFIG_SA1111
> - .dma_zone_size = SZ_1M,
> -#endif
> - .restart = sa11x0_restart,
> -MACHINE_END
> diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c
> deleted file mode 100644
> index eafeb38502af..000000000000
> --- a/arch/arm/mach-sa1100/clock.c
> +++ /dev/null
> @@ -1,145 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * linux/arch/arm/mach-sa1100/clock.c
> - */
> -#include <linux/kernel.h>
> -#include <linux/errno.h>
> -#include <linux/err.h>
> -#include <linux/clk.h>
> -#include <linux/clkdev.h>
> -#include <linux/clk-provider.h>
> -#include <linux/io.h>
> -#include <linux/spinlock.h>
> -
> -#include <mach/hardware.h>
> -#include <mach/generic.h>
> -
> -static const char * const clk_tucr_parents[] = {
> - "clk32768", "clk3686400",
> -};
> -
> -static DEFINE_SPINLOCK(tucr_lock);
> -
> -static int clk_gpio27_enable(struct clk_hw *hw)
> -{
> - unsigned long flags;
> -
> - /*
> - * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
> - * (SA-1110 Developer's Manual, section 9.1.2.1)
> - */
> - local_irq_save(flags);
> - GAFR |= GPIO_32_768kHz;
> - GPDR |= GPIO_32_768kHz;
> - local_irq_restore(flags);
> -
> - return 0;
> -}
> -
> -static void clk_gpio27_disable(struct clk_hw *hw)
> -{
> - unsigned long flags;
> -
> - local_irq_save(flags);
> - GPDR &= ~GPIO_32_768kHz;
> - GAFR &= ~GPIO_32_768kHz;
> - local_irq_restore(flags);
> -}
> -
> -static const struct clk_ops clk_gpio27_ops = {
> - .enable = clk_gpio27_enable,
> - .disable = clk_gpio27_disable,
> -};
> -
> -static const char * const clk_gpio27_parents[] = {
> - "tucr-mux",
> -};
> -
> -static const struct clk_init_data clk_gpio27_init_data __initconst = {
> - .name = "gpio27",
> - .ops = &clk_gpio27_ops,
> - .parent_names = clk_gpio27_parents,
> - .num_parents = ARRAY_SIZE(clk_gpio27_parents),
> -};
> -
> -/*
> - * Derived from the table 8-1 in the SA1110 manual, the MPLL appears to
> - * multiply its input rate by 4 x (4 + PPCR). This calculation gives
> - * the exact rate. The figures given in the table are the rates rounded
> - * to 100kHz. Stick with sa11x0_getspeed() for the time being.
> - */
> -static unsigned long clk_mpll_recalc_rate(struct clk_hw *hw,
> - unsigned long prate)
> -{
> - return sa11x0_getspeed(0) * 1000;
> -}
> -
> -static const struct clk_ops clk_mpll_ops = {
> - .recalc_rate = clk_mpll_recalc_rate,
> -};
> -
> -static const char * const clk_mpll_parents[] = {
> - "clk3686400",
> -};
> -
> -static const struct clk_init_data clk_mpll_init_data __initconst = {
> - .name = "mpll",
> - .ops = &clk_mpll_ops,
> - .parent_names = clk_mpll_parents,
> - .num_parents = ARRAY_SIZE(clk_mpll_parents),
> - .flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL,
> -};
> -
> -int __init sa11xx_clk_init(void)
> -{
> - struct clk_hw *hw;
> - int ret;
> -
> - hw = clk_hw_register_fixed_rate(NULL, "clk32768", NULL, 0, 32768);
> - if (IS_ERR(hw))
> - return PTR_ERR(hw);
> -
> - clk_hw_register_clkdev(hw, NULL, "sa1100-rtc");
> -
> - hw = clk_hw_register_fixed_rate(NULL, "clk3686400", NULL, 0, 3686400);
> - if (IS_ERR(hw))
> - return PTR_ERR(hw);
> -
> - clk_hw_register_clkdev(hw, "OSTIMER0", NULL);
> -
> - hw = kzalloc_obj(*hw);
> - if (!hw)
> - return -ENOMEM;
> - hw->init = &clk_mpll_init_data;
> - ret = clk_hw_register(NULL, hw);
> - if (ret) {
> - kfree(hw);
> - return ret;
> - }
> -
> - clk_hw_register_clkdev(hw, NULL, "sa11x0-fb");
> - clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia");
> - clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.0");
> - clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.1");
> - clk_hw_register_clkdev(hw, NULL, "1800");
> -
> - hw = clk_hw_register_mux(NULL, "tucr-mux", clk_tucr_parents,
> - ARRAY_SIZE(clk_tucr_parents), 0,
> - (void __iomem *)&TUCR, FShft(TUCR_TSEL),
> - FAlnMsk(TUCR_TSEL), 0, &tucr_lock);
> - clk_set_rate(hw->clk, 3686400);
> -
> - hw = kzalloc_obj(*hw);
> - if (!hw)
> - return -ENOMEM;
> - hw->init = &clk_gpio27_init_data;
> - ret = clk_hw_register(NULL, hw);
> - if (ret) {
> - kfree(hw);
> - return ret;
> - }
> -
> - clk_hw_register_clkdev(hw, NULL, "sa1111.0");
> -
> - return 0;
> -}
> diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
> deleted file mode 100644
> index d1931f51c900..000000000000
> --- a/arch/arm/mach-sa1100/collie.c
> +++ /dev/null
> @@ -1,447 +0,0 @@
> -/*
> - * linux/arch/arm/mach-sa1100/collie.c
> - *
> - * May be copied or modified under the terms of the GNU General Public
> - * License. See linux/COPYING for more information.
> - *
> - * This file contains all Collie-specific tweaks.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - *
> - * ChangeLog:
> - * 2006 Pavel Machek <pavel@ucw.cz>
> - * 03-06-2004 John Lenz <lenz@cs.wisc.edu>
> - * 06-04-2002 Chris Larson <kergoth@digitalnemesis.net>
> - * 04-16-2001 Lineo Japan,Inc. ...
> - */
> -
> -#include <linux/init.h>
> -#include <linux/kernel.h>
> -#include <linux/tty.h>
> -#include <linux/delay.h>
> -#include <linux/platform_data/sa11x0-serial.h>
> -#include <linux/platform_device.h>
> -#include <linux/mfd/ucb1x00.h>
> -#include <linux/mtd/mtd.h>
> -#include <linux/mtd/partitions.h>
> -#include <linux/timer.h>
> -#include <linux/gpio/property.h>
> -#include <linux/input.h>
> -#include <linux/gpio/legacy.h>
> -#include <linux/gpio/machine.h>
> -#include <linux/property.h>
> -#include <linux/power/gpio-charger.h>
> -
> -#include <video/sa1100fb.h>
> -
> -#include <mach/hardware.h>
> -#include <asm/mach-types.h>
> -#include <asm/page.h>
> -#include <asm/setup.h>
> -#include <mach/collie.h>
> -
> -#include <asm/mach/arch.h>
> -#include <asm/mach/flash.h>
> -#include <asm/mach/map.h>
> -
> -#include <asm/hardware/scoop.h>
> -#include <asm/mach/sharpsl_param.h>
> -#include <asm/hardware/locomo.h>
> -#include <linux/platform_data/mfd-mcp-sa11x0.h>
> -#include <mach/irqs.h>
> -
> -#include "generic.h"
> -
> -static struct resource collie_scoop_resources[] = {
> - [0] = DEFINE_RES_MEM(0x40800000, SZ_4K),
> -};
> -
> -static struct scoop_config collie_scoop_setup = {
> - .io_dir = COLLIE_SCOOP_IO_DIR,
> - .io_out = COLLIE_SCOOP_IO_OUT,
> - .gpio_base = COLLIE_SCOOP_GPIO_BASE,
> -};
> -
> -struct platform_device colliescoop_device = {
> - .name = "sharp-scoop",
> - .id = -1,
> - .dev = {
> - .platform_data = &collie_scoop_setup,
> - },
> - .num_resources = ARRAY_SIZE(collie_scoop_resources),
> - .resource = collie_scoop_resources,
> -};
> -
> -static struct scoop_pcmcia_dev collie_pcmcia_scoop[] = {
> - {
> - .dev = &colliescoop_device.dev,
> - .irq = COLLIE_IRQ_GPIO_CF_IRQ,
> - .cd_irq = COLLIE_IRQ_GPIO_CF_CD,
> - .cd_irq_str = "PCMCIA0 CD",
> - },
> -};
> -
> -static struct scoop_pcmcia_config collie_pcmcia_config = {
> - .devs = &collie_pcmcia_scoop[0],
> - .num_devs = 1,
> -};
> -
> -static struct ucb1x00_plat_data collie_ucb1x00_data = {
> - .gpio_base = COLLIE_TC35143_GPIO_BASE,
> -};
> -
> -static struct mcp_plat_data collie_mcp_data = {
> - .mccr0 = MCCR0_ADM | MCCR0_ExtClk,
> - .sclk_rate = 9216000,
> - .codec_pdata = &collie_ucb1x00_data,
> -};
> -
> -/* Battery management GPIOs */
> -static struct gpiod_lookup_table collie_battery_gpiod_table = {
> - /* the MCP codec mcp0 has the ucb1x00 as attached device */
> - .dev_id = "ucb1x00",
> - .table = {
> - /* This is found on the main GPIO on the SA1100 */
> - GPIO_LOOKUP("gpio", COLLIE_GPIO_CO,
> - "main battery full", GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP("gpio", COLLIE_GPIO_MAIN_BAT_LOW,
> - "main battery low", GPIO_ACTIVE_HIGH),
> - /*
> - * This is GPIO 0 on the Scoop expander, which is registered
> - * from common/scoop.c with this gpio chip label.
> - */
> - GPIO_LOOKUP("sharp-scoop", 0,
> - "main charge on", GPIO_ACTIVE_HIGH),
> - { },
> - },
> -};
> -
> -/*
> - * Collie AC IN
> - */
> -static struct gpiod_lookup_table collie_power_gpiod_table = {
> - .dev_id = "gpio-charger",
> - .table = {
> - GPIO_LOOKUP("gpio", COLLIE_GPIO_AC_IN,
> - NULL, GPIO_ACTIVE_HIGH),
> - { },
> - },
> -};
> -
> -static char *collie_ac_supplied_to[] = {
> - "main-battery",
> - "backup-battery",
> -};
> -
> -static struct gpio_charger_platform_data collie_power_data = {
> - .name = "charger",
> - .type = POWER_SUPPLY_TYPE_MAINS,
> - .supplied_to = collie_ac_supplied_to,
> - .num_supplicants = ARRAY_SIZE(collie_ac_supplied_to),
> -};
> -
> -static struct platform_device collie_power_device = {
> - .name = "gpio-charger",
> - .id = -1,
> - .dev.platform_data = &collie_power_data,
> -};
> -
> -#ifdef CONFIG_SHARP_LOCOMO
> -/*
> - * low-level UART features.
> - */
> -struct platform_device collie_locomo_device;
> -
> -static void collie_uart_set_mctrl(struct uart_port *port, u_int mctrl)
> -{
> - if (mctrl & TIOCM_RTS)
> - locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 0);
> - else
> - locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 1);
> -
> - if (mctrl & TIOCM_DTR)
> - locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 0);
> - else
> - locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 1);
> -}
> -
> -static u_int collie_uart_get_mctrl(struct uart_port *port)
> -{
> - int ret = TIOCM_CD;
> - unsigned int r;
> -
> - r = locomo_gpio_read_output(&collie_locomo_device.dev, LOCOMO_GPIO_CTS & LOCOMO_GPIO_DSR);
> - if (r == -ENODEV)
> - return ret;
> - if (r & LOCOMO_GPIO_CTS)
> - ret |= TIOCM_CTS;
> - if (r & LOCOMO_GPIO_DSR)
> - ret |= TIOCM_DSR;
> -
> - return ret;
> -}
> -
> -static struct sa1100_port_fns collie_port_fns __initdata = {
> - .set_mctrl = collie_uart_set_mctrl,
> - .get_mctrl = collie_uart_get_mctrl,
> -};
> -
> -static int collie_uart_probe(struct locomo_dev *dev)
> -{
> - return 0;
> -}
> -
> -static struct locomo_driver collie_uart_driver = {
> - .drv = {
> - .name = "collie_uart",
> - },
> - .devid = LOCOMO_DEVID_UART,
> - .probe = collie_uart_probe,
> -};
> -
> -static int __init collie_uart_init(void)
> -{
> - return locomo_driver_register(&collie_uart_driver);
> -}
> -device_initcall(collie_uart_init);
> -
> -#endif
> -
> -
> -static struct resource locomo_resources[] = {
> - [0] = DEFINE_RES_MEM(0x40000000, SZ_8K),
> - [1] = DEFINE_RES_IRQ(IRQ_GPIO25),
> -};
> -
> -static struct locomo_platform_data locomo_info = {
> - .irq_base = IRQ_BOARD_START,
> -};
> -
> -struct platform_device collie_locomo_device = {
> - .name = "locomo",
> - .id = 0,
> - .dev = {
> - .platform_data = &locomo_info,
> - },
> - .num_resources = ARRAY_SIZE(locomo_resources),
> - .resource = locomo_resources,
> -};
> -
> -static const struct software_node collie_gpio_keys_node = {
> - .name = "collie-gpio-keys",
> -};
> -
> -static const struct property_entry collie_on_key_props[] = {
> - PROPERTY_ENTRY_U32("linux,code", KEY_RESERVED),
> - PROPERTY_ENTRY_GPIO("gpios", &sa1100_gpiochip_node,
> - COLLIE_GPIO_ON_KEY, GPIO_ACTIVE_LOW),
> - PROPERTY_ENTRY_STRING("label", "On key"),
> - PROPERTY_ENTRY_U32("linux,input-type", EV_PWR),
> - PROPERTY_ENTRY_BOOL("wakeup-source"),
> - { }
> -};
> -
> -static const struct software_node collie_on_key_node = {
> - .parent = &collie_gpio_keys_node,
> - .properties = collie_on_key_props,
> -};
> -
> -static const struct property_entry collie_wakeup_key_props[] = {
> - PROPERTY_ENTRY_U32("linux,code", KEY_WAKEUP),
> - PROPERTY_ENTRY_GPIO("gpios", &sa1100_gpiochip_node,
> - COLLIE_GPIO_WAKEUP, GPIO_ACTIVE_LOW),
> - PROPERTY_ENTRY_STRING("label", "Sync"),
> - PROPERTY_ENTRY_U32("linux,input-type", EV_PWR),
> - PROPERTY_ENTRY_BOOL("wakeup-source"),
> - { }
> -};
> -
> -static const struct software_node collie_wakeup_key_node = {
> - .parent = &collie_gpio_keys_node,
> - .properties = collie_wakeup_key_props,
> -};
> -
> -static const struct software_node * const collie_gpio_keys_swnodes[] __initconst = {
> - &collie_gpio_keys_node,
> - &collie_on_key_node,
> - &collie_wakeup_key_node,
> - NULL
> -};
> -
> -static const struct platform_device_info collie_gpio_keys_dev_info __initconst = {
> - .name = "gpio-keys",
> - .id = PLATFORM_DEVID_NONE,
> - .swnode = &collie_gpio_keys_node,
> -};
> -
> -static struct platform_device *devices[] __initdata = {
> - &collie_locomo_device,
> - &colliescoop_device,
> - &collie_power_device,
> -};
> -
> -static struct mtd_partition collie_partitions[] = {
> - {
> - .name = "bootloader",
> - .offset = 0,
> - .size = 0x000C0000,
> - .mask_flags = MTD_WRITEABLE
> - }, {
> - .name = "kernel",
> - .offset = MTDPART_OFS_APPEND,
> - .size = 0x00100000,
> - }, {
> - .name = "rootfs",
> - .offset = MTDPART_OFS_APPEND,
> - .size = 0x00e20000,
> - }, {
> - .name = "bootblock",
> - .offset = MTDPART_OFS_APPEND,
> - .size = 0x00020000,
> - .mask_flags = MTD_WRITEABLE
> - }
> -};
> -
> -static int collie_flash_init(void)
> -{
> - int rc = gpio_request(COLLIE_GPIO_VPEN, "flash Vpp enable");
> - if (rc)
> - return rc;
> -
> - rc = gpio_direction_output(COLLIE_GPIO_VPEN, 1);
> - if (rc)
> - gpio_free(COLLIE_GPIO_VPEN);
> -
> - return rc;
> -}
> -
> -static void collie_set_vpp(int vpp)
> -{
> - gpio_set_value(COLLIE_GPIO_VPEN, vpp);
> -}
> -
> -static void collie_flash_exit(void)
> -{
> - gpio_free(COLLIE_GPIO_VPEN);
> -}
> -
> -static struct flash_platform_data collie_flash_data = {
> - .map_name = "cfi_probe",
> - .init = collie_flash_init,
> - .set_vpp = collie_set_vpp,
> - .exit = collie_flash_exit,
> - .parts = collie_partitions,
> - .nr_parts = ARRAY_SIZE(collie_partitions),
> -};
> -
> -static struct resource collie_flash_resources[] = {
> - DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
> -};
> -
> -static struct sa1100fb_mach_info collie_lcd_info = {
> - .pixclock = 171521, .bpp = 16,
> - .xres = 320, .yres = 240,
> -
> - .hsync_len = 5, .vsync_len = 1,
> - .left_margin = 11, .upper_margin = 2,
> - .right_margin = 30, .lower_margin = 0,
> -
> - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
> -
> - .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
> - .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
> -
> -#ifdef CONFIG_BACKLIGHT_LOCOMO
> - .lcd_power = locomolcd_power
> -#endif
> -};
> -
> -static void __init collie_init(void)
> -{
> - int ret = 0;
> -
> - /* cpu initialize */
> - GAFR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM | GPIO_SSP_CLK |
> - GPIO_MCP_CLK | GPIO_32_768kHz;
> -
> - GPDR = GPIO_LDD8 | GPIO_LDD9 | GPIO_LDD10 | GPIO_LDD11 | GPIO_LDD12 |
> - GPIO_LDD13 | GPIO_LDD14 | GPIO_LDD15 | GPIO_SSP_TXD |
> - GPIO_SSP_SCLK | GPIO_SSP_SFRM | GPIO_SDLC_SCLK |
> - _COLLIE_GPIO_UCB1x00_RESET | _COLLIE_GPIO_nMIC_ON |
> - _COLLIE_GPIO_nREMOCON_ON | GPIO_32_768kHz;
> -
> - PPDR = PPC_LDD0 | PPC_LDD1 | PPC_LDD2 | PPC_LDD3 | PPC_LDD4 | PPC_LDD5 |
> - PPC_LDD6 | PPC_LDD7 | PPC_L_PCLK | PPC_L_LCLK | PPC_L_FCLK | PPC_L_BIAS |
> - PPC_TXD1 | PPC_TXD2 | PPC_TXD3 | PPC_TXD4 | PPC_SCLK | PPC_SFRM;
> -
> - PWER = 0;
> -
> - PGSR = _COLLIE_GPIO_nREMOCON_ON;
> -
> - PSDR = PPC_RXD1 | PPC_RXD2 | PPC_RXD3 | PPC_RXD4;
> -
> - PCFR = PCFR_OPDE;
> -
> - GPSR |= _COLLIE_GPIO_UCB1x00_RESET;
> -
> - sa11x0_ppc_configure_mcp();
> -
> -
> - platform_scoop_config = &collie_pcmcia_config;
> -
> - gpiod_add_lookup_table(&collie_power_gpiod_table);
> - gpiod_add_lookup_table(&collie_battery_gpiod_table);
> -
> - ret = platform_add_devices(devices, ARRAY_SIZE(devices));
> - if (ret) {
> - printk(KERN_WARNING "collie: Unable to register LoCoMo device\n");
> - }
> -
> - software_node_register_node_group(collie_gpio_keys_swnodes);
> - platform_device_register_full(&collie_gpio_keys_dev_info);
> -
> - sa11x0_register_lcd(&collie_lcd_info);
> - sa11x0_register_mtd(&collie_flash_data, collie_flash_resources,
> - ARRAY_SIZE(collie_flash_resources));
> - sa11x0_register_mcp(&collie_mcp_data);
> -
> - sharpsl_save_param();
> -}
> -
> -static struct map_desc collie_io_desc[] __initdata = {
> - { /* 32M main flash (cs0) */
> - .virtual = 0xe8000000,
> - .pfn = __phys_to_pfn(0x00000000),
> - .length = 0x02000000,
> - .type = MT_DEVICE
> - }, { /* 32M boot flash (cs1) */
> - .virtual = 0xea000000,
> - .pfn = __phys_to_pfn(0x08000000),
> - .length = 0x02000000,
> - .type = MT_DEVICE
> - }
> -};
> -
> -static void __init collie_map_io(void)
> -{
> - sa1100_map_io();
> - iotable_init(collie_io_desc, ARRAY_SIZE(collie_io_desc));
> -
> -#ifdef CONFIG_SHARP_LOCOMO
> - sa1100_register_uart_fns(&collie_port_fns);
> -#endif
> - sa1100_register_uart(0, 3);
> - sa1100_register_uart(1, 1);
> -}
> -
> -MACHINE_START(COLLIE, "Sharp-Collie")
> - .map_io = collie_map_io,
> - .nr_irqs = SA1100_NR_IRQS,
> - .init_irq = sa1100_init_irq,
> - .init_time = sa1100_timer_init,
> - .init_machine = collie_init,
> - .init_late = sa11x0_init_late,
> - .restart = sa11x0_restart,
> -MACHINE_END
> diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
> deleted file mode 100644
> index a995625ab1a0..000000000000
> --- a/arch/arm/mach-sa1100/generic.c
> +++ /dev/null
> @@ -1,470 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * linux/arch/arm/mach-sa1100/generic.c
> - *
> - * Author: Nicolas Pitre
> - *
> - * Code common to all SA11x0 machines.
> - */
> -#include <linux/gpio/consumer.h>
> -#include <linux/gpio/machine.h>
> -#include <linux/module.h>
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/delay.h>
> -#include <linux/dma-mapping.h>
> -#include <linux/pm.h>
> -#include <linux/cpufreq.h>
> -#include <linux/ioport.h>
> -#include <linux/platform_device.h>
> -#include <linux/reboot.h>
> -#include <linux/regulator/fixed.h>
> -#include <linux/regulator/machine.h>
> -#include <linux/irqchip/irq-sa11x0.h>
> -
> -#include <video/sa1100fb.h>
> -
> -#include <soc/sa1100/pwer.h>
> -
> -#include <asm/div64.h>
> -#include <asm/mach/map.h>
> -#include <asm/mach/flash.h>
> -#include <asm/irq.h>
> -#include <asm/system_misc.h>
> -
> -#include <mach/hardware.h>
> -#include <mach/irqs.h>
> -#include <mach/reset.h>
> -
> -#include "generic.h"
> -#include <clocksource/pxa.h>
> -
> -#define NR_FREQS 16
> -
> -/*
> - * This table is setup for a 3.6864MHz Crystal.
> - */
> -struct cpufreq_frequency_table sa11x0_freq_table[NR_FREQS+1] = {
> - { .frequency = 59000, /* 59.0 MHz */},
> - { .frequency = 73700, /* 73.7 MHz */},
> - { .frequency = 88500, /* 88.5 MHz */},
> - { .frequency = 103200, /* 103.2 MHz */},
> - { .frequency = 118000, /* 118.0 MHz */},
> - { .frequency = 132700, /* 132.7 MHz */},
> - { .frequency = 147500, /* 147.5 MHz */},
> - { .frequency = 162200, /* 162.2 MHz */},
> - { .frequency = 176900, /* 176.9 MHz */},
> - { .frequency = 191700, /* 191.7 MHz */},
> - { .frequency = 206400, /* 206.4 MHz */},
> - { .frequency = 221200, /* 221.2 MHz */},
> - { .frequency = 235900, /* 235.9 MHz */},
> - { .frequency = 250700, /* 250.7 MHz */},
> - { .frequency = 265400, /* 265.4 MHz */},
> - { .frequency = 280200, /* 280.2 MHz */},
> - { .frequency = CPUFREQ_TABLE_END, },
> -};
> -
> -unsigned int sa11x0_getspeed(unsigned int cpu)
> -{
> - if (cpu)
> - return 0;
> - return sa11x0_freq_table[PPCR & 0xf].frequency;
> -}
> -
> -/*
> - * Default power-off for SA1100
> - */
> -static void sa1100_power_off(void)
> -{
> - mdelay(100);
> - local_irq_disable();
> - /* disable internal oscillator, float CS lines */
> - PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
> - /* enable wake-up on GPIO0 (Assabet...) */
> - PWER = GFER = GRER = 1;
> - /*
> - * set scratchpad to zero, just in case it is used as a
> - * restart address by the bootloader.
> - */
> - PSPR = 0;
> - /* enter sleep mode */
> - PMCR = PMCR_SF;
> -}
> -
> -void sa11x0_restart(enum reboot_mode mode, const char *cmd)
> -{
> - clear_reset_status(RESET_STATUS_ALL);
> -
> - if (mode == REBOOT_SOFT) {
> - /* Jump into ROM at address 0 */
> - soft_restart(0);
> - } else {
> - /* Use on-chip reset capability */
> - RSRR = RSRR_SWR;
> - }
> -}
> -
> -static void sa11x0_register_device(struct platform_device *dev, void *data)
> -{
> - int err;
> - dev->dev.platform_data = data;
> - err = platform_device_register(dev);
> - if (err)
> - printk(KERN_ERR "Unable to register device %s: %d\n",
> - dev->name, err);
> -}
> -
> -
> -static struct resource sa11x0udc_resources[] = {
> - [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
> - [1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
> -};
> -
> -static u64 sa11x0udc_dma_mask = 0xffffffffUL;
> -
> -static struct platform_device sa11x0udc_device = {
> - .name = "sa11x0-udc",
> - .id = -1,
> - .dev = {
> - .dma_mask = &sa11x0udc_dma_mask,
> - .coherent_dma_mask = 0xffffffff,
> - },
> - .num_resources = ARRAY_SIZE(sa11x0udc_resources),
> - .resource = sa11x0udc_resources,
> -};
> -
> -static struct resource sa11x0uart1_resources[] = {
> - [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
> - [1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
> -};
> -
> -static struct platform_device sa11x0uart1_device = {
> - .name = "sa11x0-uart",
> - .id = 1,
> - .num_resources = ARRAY_SIZE(sa11x0uart1_resources),
> - .resource = sa11x0uart1_resources,
> -};
> -
> -static struct resource sa11x0uart3_resources[] = {
> - [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
> - [1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
> -};
> -
> -static struct platform_device sa11x0uart3_device = {
> - .name = "sa11x0-uart",
> - .id = 3,
> - .num_resources = ARRAY_SIZE(sa11x0uart3_resources),
> - .resource = sa11x0uart3_resources,
> -};
> -
> -static struct resource sa11x0mcp_resources[] = {
> - [0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
> - [1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4),
> - [2] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
> -};
> -
> -static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
> -
> -static struct platform_device sa11x0mcp_device = {
> - .name = "sa11x0-mcp",
> - .id = -1,
> - .dev = {
> - .dma_mask = &sa11x0mcp_dma_mask,
> - .coherent_dma_mask = 0xffffffff,
> - },
> - .num_resources = ARRAY_SIZE(sa11x0mcp_resources),
> - .resource = sa11x0mcp_resources,
> -};
> -
> -void __init sa11x0_ppc_configure_mcp(void)
> -{
> - /* Setup the PPC unit for the MCP */
> - PPDR &= ~PPC_RXD4;
> - PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
> - PSDR |= PPC_RXD4;
> - PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
> - PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
> -}
> -
> -void sa11x0_register_mcp(struct mcp_plat_data *data)
> -{
> - sa11x0_register_device(&sa11x0mcp_device, data);
> -}
> -
> -static struct resource sa11x0ssp_resources[] = {
> - [0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
> - [1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
> -};
> -
> -static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
> -
> -static struct platform_device sa11x0ssp_device = {
> - .name = "sa11x0-ssp",
> - .id = -1,
> - .dev = {
> - .dma_mask = &sa11x0ssp_dma_mask,
> - .coherent_dma_mask = 0xffffffff,
> - },
> - .num_resources = ARRAY_SIZE(sa11x0ssp_resources),
> - .resource = sa11x0ssp_resources,
> -};
> -
> -static struct resource sa11x0fb_resources[] = {
> - [0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
> - [1] = DEFINE_RES_IRQ(IRQ_LCD),
> -};
> -
> -static struct platform_device sa11x0fb_device = {
> - .name = "sa11x0-fb",
> - .id = -1,
> - .dev = {
> - .coherent_dma_mask = 0xffffffff,
> - },
> - .num_resources = ARRAY_SIZE(sa11x0fb_resources),
> - .resource = sa11x0fb_resources,
> -};
> -
> -void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
> -{
> - sa11x0_register_device(&sa11x0fb_device, inf);
> -}
> -
> -void sa11x0_register_pcmcia(int socket, struct gpiod_lookup_table *table)
> -{
> - if (table)
> - gpiod_add_lookup_table(table);
> - platform_device_register_simple("sa11x0-pcmcia", socket, NULL, 0);
> -}
> -
> -static struct platform_device sa11x0mtd_device = {
> - .name = "sa1100-mtd",
> - .id = -1,
> -};
> -
> -void sa11x0_register_mtd(struct flash_platform_data *flash,
> - struct resource *res, int nr)
> -{
> - flash->name = "sa1100";
> - sa11x0mtd_device.resource = res;
> - sa11x0mtd_device.num_resources = nr;
> - sa11x0_register_device(&sa11x0mtd_device, flash);
> -}
> -
> -static struct resource sa1100_rtc_resources[] = {
> - DEFINE_RES_MEM(0x90010000, 0x40),
> - DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
> - DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
> -};
> -
> -static struct platform_device sa11x0rtc_device = {
> - .name = "sa1100-rtc",
> - .id = -1,
> - .num_resources = ARRAY_SIZE(sa1100_rtc_resources),
> - .resource = sa1100_rtc_resources,
> -};
> -
> -static struct resource sa11x0dma_resources[] = {
> - DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
> - DEFINE_RES_IRQ(IRQ_DMA0),
> - DEFINE_RES_IRQ(IRQ_DMA1),
> - DEFINE_RES_IRQ(IRQ_DMA2),
> - DEFINE_RES_IRQ(IRQ_DMA3),
> - DEFINE_RES_IRQ(IRQ_DMA4),
> - DEFINE_RES_IRQ(IRQ_DMA5),
> -};
> -
> -static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);
> -
> -static struct platform_device sa11x0dma_device = {
> - .name = "sa11x0-dma",
> - .id = -1,
> - .dev = {
> - .dma_mask = &sa11x0dma_dma_mask,
> - .coherent_dma_mask = 0xffffffff,
> - },
> - .num_resources = ARRAY_SIZE(sa11x0dma_resources),
> - .resource = sa11x0dma_resources,
> -};
> -
> -static struct platform_device *sa11x0_devices[] __initdata = {
> - &sa11x0udc_device,
> - &sa11x0uart1_device,
> - &sa11x0uart3_device,
> - &sa11x0ssp_device,
> - &sa11x0rtc_device,
> - &sa11x0dma_device,
> -};
> -
> -static int __init sa1100_init(void)
> -{
> - struct resource wdt_res = DEFINE_RES_MEM(0x90000000, 0x20);
> - register_platform_power_off(sa1100_power_off);
> -
> - regulator_has_full_constraints();
> -
> - platform_device_register_simple("sa1100_wdt", -1, &wdt_res, 1);
> -
> - return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
> -}
> -
> -arch_initcall(sa1100_init);
> -
> -void __init sa11x0_init_late(void)
> -{
> - sa11x0_pm_init();
> -}
> -
> -int __init sa11x0_register_fixed_regulator(int n,
> - struct fixed_voltage_config *cfg,
> - struct regulator_consumer_supply *supplies, unsigned num_supplies,
> - bool uses_gpio)
> -{
> - struct regulator_init_data *id;
> -
> - cfg->init_data = id = kzalloc_obj(*cfg->init_data);
> - if (!cfg->init_data)
> - return -ENOMEM;
> -
> - if (!uses_gpio)
> - id->constraints.always_on = 1;
> - id->constraints.name = cfg->supply_name;
> - id->constraints.min_uV = cfg->microvolts;
> - id->constraints.max_uV = cfg->microvolts;
> - id->constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
> - id->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
> - id->consumer_supplies = supplies;
> - id->num_consumer_supplies = num_supplies;
> -
> - platform_device_register_resndata(NULL, "reg-fixed-voltage", n,
> - NULL, 0, cfg, sizeof(*cfg));
> - return 0;
> -}
> -
> -/*
> - * Common I/O mapping:
> - *
> - * Typically, static virtual address mappings are as follow:
> - *
> - * 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.)
> - * 0xf4000000-0xf4ffffff: SA-1111
> - * 0xf5000000-0xf5ffffff: reserved (used by cache flushing area)
> - * 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above)
> - * 0xffff0000-0xffff0fff: SA1100 exception vectors
> - * 0xffff2000-0xffff2fff: Minicache copy_user_page area
> - *
> - * Below 0xe8000000 is reserved for vm allocation.
> - *
> - * The machine specific code must provide the extra mapping beside the
> - * default mapping provided here.
> - */
> -
> -static struct map_desc standard_io_desc[] __initdata = {
> - { /* PCM */
> - .virtual = 0xf8000000,
> - .pfn = __phys_to_pfn(0x80000000),
> - .length = 0x00100000,
> - .type = MT_DEVICE
> - }, { /* SCM */
> - .virtual = 0xfa000000,
> - .pfn = __phys_to_pfn(0x90000000),
> - .length = 0x00100000,
> - .type = MT_DEVICE
> - }, { /* MER */
> - .virtual = 0xfc000000,
> - .pfn = __phys_to_pfn(0xa0000000),
> - .length = 0x00100000,
> - .type = MT_DEVICE
> - }, { /* LCD + DMA */
> - .virtual = 0xfe000000,
> - .pfn = __phys_to_pfn(0xb0000000),
> - .length = 0x00200000,
> - .type = MT_DEVICE
> - },
> -};
> -
> -void __init sa1100_map_io(void)
> -{
> - iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
> -}
> -
> -void __init sa1100_timer_init(void)
> -{
> - pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000));
> -}
> -
> -static struct resource irq_resource =
> - DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
> -
> -void __init sa1100_init_irq(void)
> -{
> - request_resource(&iomem_resource, &irq_resource);
> -
> - sa11x0_init_irq_nodt(IRQ_GPIO0_SC, irq_resource.start);
> -
> - sa1100_init_gpio();
> - sa11xx_clk_init();
> -}
> -
> -/*
> - * Disable the memory bus request/grant signals on the SA1110 to
> - * ensure that we don't receive spurious memory requests. We set
> - * the MBGNT signal false to ensure the SA1111 doesn't own the
> - * SDRAM bus.
> - */
> -void sa1110_mb_disable(void)
> -{
> - unsigned long flags;
> -
> - local_irq_save(flags);
> -
> - PGSR &= ~GPIO_MBGNT;
> - GPCR = GPIO_MBGNT;
> - GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
> -
> - GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);
> -
> - local_irq_restore(flags);
> -}
> -
> -/*
> - * If the system is going to use the SA-1111 DMA engines, set up
> - * the memory bus request/grant pins.
> - */
> -void sa1110_mb_enable(void)
> -{
> - unsigned long flags;
> -
> - local_irq_save(flags);
> -
> - PGSR &= ~GPIO_MBGNT;
> - GPCR = GPIO_MBGNT;
> - GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
> -
> - GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
> - TUCR |= TUCR_MR;
> -
> - local_irq_restore(flags);
> -}
> -
> -int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on)
> -{
> - if (on)
> - PWER |= BIT(gpio);
> - else
> - PWER &= ~BIT(gpio);
> -
> - return 0;
> -}
> -
> -int sa11x0_sc_set_wake(unsigned int irq, unsigned int on)
> -{
> - if (BIT(irq) != IC_RTCAlrm)
> - return -EINVAL;
> -
> - if (on)
> - PWER |= PWER_RTC;
> - else
> - PWER &= ~PWER_RTC;
> -
> - return 0;
> -}
> diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
> deleted file mode 100644
> index 3cfe3b647711..000000000000
> --- a/arch/arm/mach-sa1100/generic.h
> +++ /dev/null
> @@ -1,58 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * linux/arch/arm/mach-sa1100/generic.h
> - *
> - * Author: Nicolas Pitre
> - */
> -#include <linux/cpufreq.h>
> -#include <linux/reboot.h>
> -
> -extern void sa1100_timer_init(void);
> -extern void __init sa1100_map_io(void);
> -extern void __init sa1100_init_irq(void);
> -extern void __init sa1100_init_gpio(void);
> -extern void sa11x0_restart(enum reboot_mode, const char *);
> -extern void sa11x0_init_late(void);
> -
> -#define SET_BANK(__nr,__start,__size) \
> - mi->bank[__nr].start = (__start), \
> - mi->bank[__nr].size = (__size)
> -
> -extern void sa1110_mb_enable(void);
> -extern void sa1110_mb_disable(void);
> -
> -extern struct cpufreq_frequency_table sa11x0_freq_table[];
> -extern unsigned int sa11x0_getspeed(unsigned int cpu);
> -
> -struct flash_platform_data;
> -struct resource;
> -
> -void sa11x0_register_mtd(struct flash_platform_data *flash,
> - struct resource *res, int nr);
> -
> -struct mcp_plat_data;
> -void sa11x0_ppc_configure_mcp(void);
> -void sa11x0_register_mcp(struct mcp_plat_data *data);
> -
> -struct sa1100fb_mach_info;
> -void sa11x0_register_lcd(struct sa1100fb_mach_info *inf);
> -
> -#ifdef CONFIG_PM
> -int sa11x0_pm_init(void);
> -#else
> -static inline int sa11x0_pm_init(void) { return 0; }
> -#endif
> -
> -int sa11xx_clk_init(void);
> -
> -struct gpiod_lookup_table;
> -void sa11x0_register_pcmcia(int socket, struct gpiod_lookup_table *);
> -
> -struct software_node;
> -extern const struct software_node sa1100_gpiochip_node;
> -
> -struct fixed_voltage_config;
> -struct regulator_consumer_supply;
> -int sa11x0_register_fixed_regulator(int n, struct fixed_voltage_config *cfg,
> - struct regulator_consumer_supply *supplies, unsigned num_supplies,
> - bool uses_gpio);
> diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
> deleted file mode 100644
> index 59e9251a138e..000000000000
> --- a/arch/arm/mach-sa1100/h3600.c
> +++ /dev/null
> @@ -1,134 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Support for Compaq iPAQ H3600 handheld computer
> - *
> - * Copyright (c) 2000,1 Compaq Computer Corporation. (Author: Jamey Hicks)
> - * Copyright (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru>
> - */
> -
> -#include <linux/init.h>
> -#include <linux/kernel.h>
> -#include <linux/gpio/legacy.h>
> -
> -#include <video/sa1100fb.h>
> -
> -#include <asm/mach-types.h>
> -#include <asm/mach/arch.h>
> -
> -#include <mach/h3xxx.h>
> -#include <mach/irqs.h>
> -
> -#include "generic.h"
> -
> -static bool h3600_lcd_request(void)
> -{
> - static bool h3600_lcd_ok;
> - int rc;
> -
> - if (h3600_lcd_ok)
> - return true;
> -
> - rc = gpio_request(H3XXX_EGPIO_LCD_ON, "LCD power");
> - if (rc)
> - goto out;
> - rc = gpio_direction_output(H3XXX_EGPIO_LCD_ON, 0);
> - if (rc)
> - goto out_free_on;
> - rc = gpio_request(H3600_EGPIO_LCD_PCI, "LCD control");
> - if (rc)
> - goto out_free_on;
> - rc = gpio_direction_output(H3600_EGPIO_LCD_PCI, 0);
> - if (rc)
> - goto out_free_pci;
> - rc = gpio_request(H3600_EGPIO_LCD_5V_ON, "LCD 5v");
> - if (rc)
> - goto out_free_pci;
> - rc = gpio_direction_output(H3600_EGPIO_LCD_5V_ON, 0);
> - if (rc)
> - goto out_free_5v_on;
> - rc = gpio_request(H3600_EGPIO_LVDD_ON, "LCD 9v/-6.5v");
> - if (rc)
> - goto out_free_5v_on;
> - rc = gpio_direction_output(H3600_EGPIO_LVDD_ON, 0);
> - if (rc)
> - goto out_free_lvdd_on;
> -
> - goto out;
> -
> -out_free_lvdd_on:
> - gpio_free(H3600_EGPIO_LVDD_ON);
> -out_free_5v_on:
> - gpio_free(H3600_EGPIO_LCD_5V_ON);
> -out_free_pci:
> - gpio_free(H3600_EGPIO_LCD_PCI);
> -out_free_on:
> - gpio_free(H3XXX_EGPIO_LCD_ON);
> -out:
> - if (rc)
> - pr_err("%s: can't request GPIOs\n", __func__);
> - else
> - h3600_lcd_ok = true;
> -
> - return h3600_lcd_ok;
> -}
> -
> -static void h3600_lcd_power(int enable)
> -{
> - if (!h3600_lcd_request())
> - return;
> -
> - gpio_direction_output(H3XXX_EGPIO_LCD_ON, enable);
> - gpio_direction_output(H3600_EGPIO_LCD_PCI, enable);
> - gpio_direction_output(H3600_EGPIO_LCD_5V_ON, enable);
> - gpio_direction_output(H3600_EGPIO_LVDD_ON, enable);
> -}
> -
> -static const struct sa1100fb_rgb h3600_rgb_16 = {
> - .red = { .offset = 12, .length = 4, },
> - .green = { .offset = 7, .length = 4, },
> - .blue = { .offset = 1, .length = 4, },
> - .transp = { .offset = 0, .length = 0, },
> -};
> -
> -static struct sa1100fb_mach_info h3600_lcd_info = {
> - .pixclock = 174757, .bpp = 16,
> - .xres = 320, .yres = 240,
> -
> - .hsync_len = 3, .vsync_len = 3,
> - .left_margin = 12, .upper_margin = 10,
> - .right_margin = 17, .lower_margin = 1,
> -
> - .cmap_static = 1,
> -
> - .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
> - .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
> -
> - .rgb[RGB_16] = &h3600_rgb_16,
> -
> - .lcd_power = h3600_lcd_power,
> -};
> -
> -
> -static void __init h3600_map_io(void)
> -{
> - h3xxx_map_io();
> -}
> -
> -static void __init h3600_mach_init(void)
> -{
> - h3xxx_mach_init();
> -
> - sa11x0_register_lcd(&h3600_lcd_info);
> -}
> -
> -MACHINE_START(H3600, "Compaq iPAQ H3600")
> - .atag_offset = 0x100,
> - .map_io = h3600_map_io,
> - .nr_irqs = SA1100_NR_IRQS,
> - .init_irq = sa1100_init_irq,
> - .init_time = sa1100_timer_init,
> - .init_machine = h3600_mach_init,
> - .init_late = sa11x0_init_late,
> - .restart = sa11x0_restart,
> -MACHINE_END
> -
> diff --git a/arch/arm/mach-sa1100/h3xxx.c b/arch/arm/mach-sa1100/h3xxx.c
> deleted file mode 100644
> index 6f4c5d2be569..000000000000
> --- a/arch/arm/mach-sa1100/h3xxx.c
> +++ /dev/null
> @@ -1,305 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Support for Compaq iPAQ H3100 and H3600 handheld computers (common code)
> - *
> - * Copyright (c) 2000,1 Compaq Computer Corporation. (Author: Jamey Hicks)
> - * Copyright (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru>
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/gpio/machine.h>
> -#include <linux/gpio/legacy.h>
> -#include <linux/gpio_keys.h>
> -#include <linux/gpio/property.h>
> -#include <linux/gpio/consumer.h>
> -#include <linux/input.h>
> -#include <linux/property.h>
> -#include <linux/mtd/mtd.h>
> -#include <linux/mtd/partitions.h>
> -#include <linux/platform_data/gpio-htc-egpio.h>
> -#include <linux/platform_data/sa11x0-serial.h>
> -#include <linux/platform_device.h>
> -#include <linux/serial_core.h>
> -
> -#include <asm/mach/flash.h>
> -#include <asm/mach/map.h>
> -
> -#include <mach/h3xxx.h>
> -#include <mach/irqs.h>
> -
> -#include "generic.h"
> -
> -/*
> - * H3xxx flash support
> - */
> -static struct mtd_partition h3xxx_partitions[] = {
> - {
> - .name = "H3XXX boot firmware",
> - .size = 0x00040000,
> - .offset = 0,
> - .mask_flags = MTD_WRITEABLE, /* force read-only */
> - }, {
> - .name = "H3XXX rootfs",
> - .size = MTDPART_SIZ_FULL,
> - .offset = 0x00040000,
> - }
> -};
> -
> -static void h3xxx_set_vpp(int vpp)
> -{
> - gpio_set_value(H3XXX_EGPIO_VPP_ON, vpp);
> -}
> -
> -static int h3xxx_flash_init(void)
> -{
> - int err = gpio_request(H3XXX_EGPIO_VPP_ON, "Flash Vpp");
> - if (err) {
> - pr_err("%s: can't request H3XXX_EGPIO_VPP_ON\n", __func__);
> - return err;
> - }
> -
> - err = gpio_direction_output(H3XXX_EGPIO_VPP_ON, 0);
> - if (err)
> - gpio_free(H3XXX_EGPIO_VPP_ON);
> -
> - return err;
> -}
> -
> -static void h3xxx_flash_exit(void)
> -{
> - gpio_free(H3XXX_EGPIO_VPP_ON);
> -}
> -
> -static struct flash_platform_data h3xxx_flash_data = {
> - .map_name = "cfi_probe",
> - .set_vpp = h3xxx_set_vpp,
> - .init = h3xxx_flash_init,
> - .exit = h3xxx_flash_exit,
> - .parts = h3xxx_partitions,
> - .nr_parts = ARRAY_SIZE(h3xxx_partitions),
> -};
> -
> -static struct resource h3xxx_flash_resource =
> - DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
> -
> -
> -/*
> - * H3xxx uart support
> - */
> -static void h3xxx_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
> -{
> - if (port->mapbase == _Ser3UTCR0) {
> - if (!gpio_request(H3XXX_EGPIO_RS232_ON, "RS232 transceiver")) {
> - gpio_direction_output(H3XXX_EGPIO_RS232_ON, !state);
> - gpio_free(H3XXX_EGPIO_RS232_ON);
> - } else {
> - pr_err("%s: can't request H3XXX_EGPIO_RS232_ON\n",
> - __func__);
> - }
> - }
> -}
> -
> -/*
> - * Enable/Disable wake up events for this serial port.
> - * Obviously, we only support this on the normal COM port.
> - */
> -static int h3xxx_uart_set_wake(struct uart_port *port, u_int enable)
> -{
> - int err = -EINVAL;
> -
> - if (port->mapbase == _Ser3UTCR0) {
> - if (enable)
> - PWER |= PWER_GPIO23 | PWER_GPIO25; /* DCD and CTS */
> - else
> - PWER &= ~(PWER_GPIO23 | PWER_GPIO25); /* DCD and CTS */
> - err = 0;
> - }
> - return err;
> -}
> -
> -static struct sa1100_port_fns h3xxx_port_fns __initdata = {
> - .pm = h3xxx_uart_pm,
> - .set_wake = h3xxx_uart_set_wake,
> -};
> -
> -static struct gpiod_lookup_table h3xxx_uart3_gpio_table = {
> - .dev_id = "sa11x0-uart.3",
> - .table = {
> - GPIO_LOOKUP("gpio", H3XXX_GPIO_COM_DCD, "dcd", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("gpio", H3XXX_GPIO_COM_CTS, "cts", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("gpio", H3XXX_GPIO_COM_RTS, "rts", GPIO_ACTIVE_LOW),
> - { },
> - },
> -};
> -
> -/*
> - * EGPIO
> - */
> -
> -static struct resource egpio_resources[] = {
> - [0] = DEFINE_RES_MEM(H3600_EGPIO_PHYS, 0x4),
> -};
> -
> -static struct htc_egpio_chip egpio_chips[] = {
> - [0] = {
> - .reg_start = 0,
> - .gpio_base = H3XXX_EGPIO_BASE,
> - .num_gpios = 16,
> - .direction = HTC_EGPIO_OUTPUT,
> - .initial_values = 0x0080, /* H3XXX_EGPIO_RS232_ON */
> - },
> -};
> -
> -static struct htc_egpio_platform_data egpio_info = {
> - .reg_width = 16,
> - .bus_width = 16,
> - .chip = egpio_chips,
> - .num_chips = ARRAY_SIZE(egpio_chips),
> -};
> -
> -static struct platform_device h3xxx_egpio = {
> - .name = "htc-egpio",
> - .id = -1,
> - .resource = egpio_resources,
> - .num_resources = ARRAY_SIZE(egpio_resources),
> - .dev = {
> - .platform_data = &egpio_info,
> - },
> -};
> -
> -/*
> - * GPIO keys
> - */
> -
> -static const struct software_node h3xxx_gpio_keys_node = {
> - .name = "h3xxx-gpio-keys",
> -};
> -
> -static const struct property_entry h3xxx_power_key_props[] = {
> - PROPERTY_ENTRY_U32("linux,code", KEY_POWER),
> - PROPERTY_ENTRY_GPIO("gpios", &sa1100_gpiochip_node,
> - H3XXX_GPIO_PWR_BUTTON, GPIO_ACTIVE_LOW),
> - PROPERTY_ENTRY_STRING("label", "Power Button"),
> - PROPERTY_ENTRY_BOOL("wakeup-source"),
> - { }
> -};
> -
> -static const struct software_node h3xxx_power_key_node = {
> - .parent = &h3xxx_gpio_keys_node,
> - .properties = h3xxx_power_key_props,
> -};
> -
> -static const struct property_entry h3xxx_action_key_props[] = {
> - PROPERTY_ENTRY_U32("linux,code", KEY_ENTER),
> - PROPERTY_ENTRY_GPIO("gpios", &sa1100_gpiochip_node,
> - H3XXX_GPIO_ACTION_BUTTON, GPIO_ACTIVE_LOW),
> - PROPERTY_ENTRY_STRING("label", "Action button"),
> - { }
> -};
> -
> -static const struct software_node h3xxx_action_key_node = {
> - .parent = &h3xxx_gpio_keys_node,
> - .properties = h3xxx_action_key_props,
> -};
> -
> -static const struct software_node * const h3xxx_gpio_keys_swnodes[] __initconst = {
> - &h3xxx_gpio_keys_node,
> - &h3xxx_power_key_node,
> - &h3xxx_action_key_node,
> - NULL
> -};
> -
> -static const struct platform_device_info h3xxx_gpio_keys_dev_info __initconst = {
> - .name = "gpio-keys",
> - .id = PLATFORM_DEVID_NONE,
> - .swnode = &h3xxx_gpio_keys_node,
> -};
> -
> -static struct resource h3xxx_micro_resources[] = {
> - DEFINE_RES_MEM(0x80010000, SZ_4K),
> - DEFINE_RES_MEM(0x80020000, SZ_4K),
> - DEFINE_RES_IRQ(IRQ_Ser1UART),
> -};
> -
> -struct platform_device h3xxx_micro_asic = {
> - .name = "ipaq-h3xxx-micro",
> - .id = -1,
> - .resource = h3xxx_micro_resources,
> - .num_resources = ARRAY_SIZE(h3xxx_micro_resources),
> -};
> -
> -static struct platform_device *h3xxx_devices[] = {
> - &h3xxx_egpio,
> - &h3xxx_micro_asic,
> -};
> -
> -static struct gpiod_lookup_table h3xxx_pcmcia_gpio_table = {
> - .dev_id = "sa11x0-pcmcia",
> - .table = {
> - GPIO_LOOKUP("gpio", H3XXX_GPIO_PCMCIA_CD0,
> - "pcmcia0-detect", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("gpio", H3XXX_GPIO_PCMCIA_IRQ0,
> - "pcmcia0-ready", GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP("gpio", H3XXX_GPIO_PCMCIA_CD1,
> - "pcmcia1-detect", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("gpio", H3XXX_GPIO_PCMCIA_IRQ1,
> - "pcmcia1-ready", GPIO_ACTIVE_HIGH),
> - { },
> - },
> -};
> -
> -void __init h3xxx_mach_init(void)
> -{
> - gpiod_add_lookup_table(&h3xxx_pcmcia_gpio_table);
> - gpiod_add_lookup_table(&h3xxx_uart3_gpio_table);
> - sa1100_register_uart_fns(&h3xxx_port_fns);
> - sa11x0_register_mtd(&h3xxx_flash_data, &h3xxx_flash_resource, 1);
> - platform_add_devices(h3xxx_devices, ARRAY_SIZE(h3xxx_devices));
> - software_node_register_node_group(h3xxx_gpio_keys_swnodes);
> - platform_device_register_full(&h3xxx_gpio_keys_dev_info);
> -}
> -
> -static struct map_desc h3600_io_desc[] __initdata = {
> - { /* static memory bank 2 CS#2 */
> - .virtual = H3600_BANK_2_VIRT,
> - .pfn = __phys_to_pfn(SA1100_CS2_PHYS),
> - .length = 0x02800000,
> - .type = MT_DEVICE
> - }, { /* static memory bank 4 CS#4 */
> - .virtual = H3600_BANK_4_VIRT,
> - .pfn = __phys_to_pfn(SA1100_CS4_PHYS),
> - .length = 0x00800000,
> - .type = MT_DEVICE
> - }, { /* EGPIO 0 CS#5 */
> - .virtual = H3600_EGPIO_VIRT,
> - .pfn = __phys_to_pfn(H3600_EGPIO_PHYS),
> - .length = 0x01000000,
> - .type = MT_DEVICE
> - }
> -};
> -
> -/*
> - * Common map_io initialization
> - */
> -
> -void __init h3xxx_map_io(void)
> -{
> - sa1100_map_io();
> - iotable_init(h3600_io_desc, ARRAY_SIZE(h3600_io_desc));
> -
> - sa1100_register_uart(0, 3); /* Common serial port */
> -// sa1100_register_uart(1, 1); /* Microcontroller on 3100/3600 */
> -
> - /* Ensure those pins are outputs and driving low */
> - PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
> - PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
> -
> - /* Configure suspend conditions */
> - PGSR = 0;
> - PCFR = PCFR_OPDE;
> - PSDR = 0;
> -
> - GPCR = 0x0fffffff; /* All outputs are set low by default */
> - GPDR = 0; /* Configure all GPIOs as input */
> -}
> -
> diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
> deleted file mode 100644
> index 6e6ff3e18f0f..000000000000
> --- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
> +++ /dev/null
> @@ -1,1798 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * FILE SA-1100.h
> - *
> - * Version 1.2
> - * Author Copyright (c) Marc A. Viredaz, 1998
> - * DEC Western Research Laboratory, Palo Alto, CA
> - * Date January 1998 (April 1997)
> - * System StrongARM SA-1100
> - * Language C or ARM Assembly
> - * Purpose Definition of constants related to the StrongARM
> - * SA-1100 microprocessor (Advanced RISC Machine (ARM)
> - * architecture version 4). This file is based on the
> - * StrongARM SA-1100 data sheet version 2.2.
> - *
> - */
> -
> -
> -/* Be sure that virtual mapping is defined right */
> -#ifndef __ASM_ARCH_HARDWARE_H
> -#error You must include hardware.h not SA-1100.h
> -#endif
> -
> -#include "bitfield.h"
> -
> -/*
> - * SA1100 CS line to physical address
> - */
> -
> -#define SA1100_CS0_PHYS 0x00000000
> -#define SA1100_CS1_PHYS 0x08000000
> -#define SA1100_CS2_PHYS 0x10000000
> -#define SA1100_CS3_PHYS 0x18000000
> -#define SA1100_CS4_PHYS 0x40000000
> -#define SA1100_CS5_PHYS 0x48000000
> -
> -/*
> - * Personal Computer Memory Card International Association (PCMCIA) sockets
> - */
> -
> -#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
> -#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
> -#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
> -#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
> -#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
> -
> -#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
> -#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
> -#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
> -#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
> -
> -#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
> -#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
> -#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
> -#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
> -
> -#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
> - (0x20000000 + (Nb)*PCMCIASp)
> -#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
> -#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
> - (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
> -#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
> - (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
> -
> -#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
> -#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
> -#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
> -#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
> -
> -#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
> -#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
> -#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
> -#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
> -
> -
> -/*
> - * Universal Serial Bus (USB) Device Controller (UDC) control registers
> - *
> - * Registers
> - * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device
> - * Controller (UDC) Control Register (read/write).
> - * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device
> - * Controller (UDC) Address Register (read/write).
> - * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device
> - * Controller (UDC) Output Maximum Packet size register
> - * (read/write).
> - * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device
> - * Controller (UDC) Input Maximum Packet size register
> - * (read/write).
> - * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device
> - * Controller (UDC) Control/Status register end-point 0
> - * (read/write).
> - * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device
> - * Controller (UDC) Control/Status register end-point 1
> - * (output, read/write).
> - * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device
> - * Controller (UDC) Control/Status register end-point 2
> - * (input, read/write).
> - * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device
> - * Controller (UDC) Data register end-point 0
> - * (read/write).
> - * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device
> - * Controller (UDC) Write Count register end-point 0
> - * (read).
> - * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device
> - * Controller (UDC) Data Register (read/write).
> - * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device
> - * Controller (UDC) Status Register (read/write).
> - */
> -
> -#define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */
> -#define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */
> -#define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */
> -#define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */
> -#define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */
> -#define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */
> -#define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */
> -#define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */
> -#define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */
> -#define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */
> -#define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */
> -
> -#define UDCCR_UDD 0x00000001 /* UDC Disable */
> -#define UDCCR_UDA 0x00000002 /* UDC Active (read) */
> -#define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */
> -#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */
> - /* (disable) */
> -#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */
> - /* (disable) */
> -#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */
> - /* (disable) */
> -#define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */
> - /* (disable) */
> -#define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */
> -#define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */
> -
> -#define UDCAR_ADD Fld (7, 0) /* function ADDress */
> -
> -#define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
> - /* [byte] */
> -#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \
> - /* [1..256 byte] */ \
> - (((Size) - 1) << FShft (UDCOMP_OUTMAXP))
> -
> -#define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
> - /* [byte] */
> -#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \
> - /* [1..256 byte] */ \
> - (((Size) - 1) << FShft (UDCIMP_INMAXP))
> -
> -#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */
> -#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */
> -#define UDCCS0_SST 0x00000004 /* Sent STall */
> -#define UDCCS0_FST 0x00000008 /* Force STall */
> -#define UDCCS0_DE 0x00000010 /* Data End */
> -#define UDCCS0_SE 0x00000020 /* Setup End (read) */
> -#define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */
> - /* (write) */
> -#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */
> -
> -#define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */
> - /* Service request (read) */
> -#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */
> -#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */
> -#define UDCCS1_SST 0x00000008 /* Sent STall */
> -#define UDCCS1_FST 0x00000010 /* Force STall */
> -#define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */
> -
> -#define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */
> - /* Service request (read) */
> -#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */
> -#define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */
> -#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */
> -#define UDCCS2_SST 0x00000010 /* Sent STall */
> -#define UDCCS2_FST 0x00000020 /* Force STall */
> -
> -#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
> -
> -#define UDCWC_WC Fld (4, 0) /* Write Count */
> -
> -#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
> -
> -#define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */
> -#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */
> -#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */
> -#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */
> -#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */
> -#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */
> -
> -
> -/*
> - * Universal Asynchronous Receiver/Transmitter (UART) control registers
> - *
> - * Registers
> - * Ser1UTCR0 Serial port 1 Universal Asynchronous
> - * Receiver/Transmitter (UART) Control Register 0
> - * (read/write).
> - * Ser1UTCR1 Serial port 1 Universal Asynchronous
> - * Receiver/Transmitter (UART) Control Register 1
> - * (read/write).
> - * Ser1UTCR2 Serial port 1 Universal Asynchronous
> - * Receiver/Transmitter (UART) Control Register 2
> - * (read/write).
> - * Ser1UTCR3 Serial port 1 Universal Asynchronous
> - * Receiver/Transmitter (UART) Control Register 3
> - * (read/write).
> - * Ser1UTDR Serial port 1 Universal Asynchronous
> - * Receiver/Transmitter (UART) Data Register
> - * (read/write).
> - * Ser1UTSR0 Serial port 1 Universal Asynchronous
> - * Receiver/Transmitter (UART) Status Register 0
> - * (read/write).
> - * Ser1UTSR1 Serial port 1 Universal Asynchronous
> - * Receiver/Transmitter (UART) Status Register 1 (read).
> - *
> - * Ser2UTCR0 Serial port 2 Universal Asynchronous
> - * Receiver/Transmitter (UART) Control Register 0
> - * (read/write).
> - * Ser2UTCR1 Serial port 2 Universal Asynchronous
> - * Receiver/Transmitter (UART) Control Register 1
> - * (read/write).
> - * Ser2UTCR2 Serial port 2 Universal Asynchronous
> - * Receiver/Transmitter (UART) Control Register 2
> - * (read/write).
> - * Ser2UTCR3 Serial port 2 Universal Asynchronous
> - * Receiver/Transmitter (UART) Control Register 3
> - * (read/write).
> - * Ser2UTCR4 Serial port 2 Universal Asynchronous
> - * Receiver/Transmitter (UART) Control Register 4
> - * (read/write).
> - * Ser2UTDR Serial port 2 Universal Asynchronous
> - * Receiver/Transmitter (UART) Data Register
> - * (read/write).
> - * Ser2UTSR0 Serial port 2 Universal Asynchronous
> - * Receiver/Transmitter (UART) Status Register 0
> - * (read/write).
> - * Ser2UTSR1 Serial port 2 Universal Asynchronous
> - * Receiver/Transmitter (UART) Status Register 1 (read).
> - *
> - * Ser3UTCR0 Serial port 3 Universal Asynchronous
> - * Receiver/Transmitter (UART) Control Register 0
> - * (read/write).
> - * Ser3UTCR1 Serial port 3 Universal Asynchronous
> - * Receiver/Transmitter (UART) Control Register 1
> - * (read/write).
> - * Ser3UTCR2 Serial port 3 Universal Asynchronous
> - * Receiver/Transmitter (UART) Control Register 2
> - * (read/write).
> - * Ser3UTCR3 Serial port 3 Universal Asynchronous
> - * Receiver/Transmitter (UART) Control Register 3
> - * (read/write).
> - * Ser3UTDR Serial port 3 Universal Asynchronous
> - * Receiver/Transmitter (UART) Data Register
> - * (read/write).
> - * Ser3UTSR0 Serial port 3 Universal Asynchronous
> - * Receiver/Transmitter (UART) Status Register 0
> - * (read/write).
> - * Ser3UTSR1 Serial port 3 Universal Asynchronous
> - * Receiver/Transmitter (UART) Status Register 1 (read).
> - *
> - * Clocks
> - * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
> - * or 3.5795 MHz).
> - * fua, Tua Frequency, period of the UART communication.
> - */
> -
> -#define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */
> -#define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */
> -#define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */
> -#define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */
> -#define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */
> -#define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */
> -#define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */
> -#define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */
> -
> -#define Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */
> -#define Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */
> -#define Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */
> -#define Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */
> -#define Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */
> -#define Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */
> -#define Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */
> -
> -#define Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */
> -#define Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */
> -#define Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */
> -#define Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */
> -#define Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */
> -#define Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */
> -#define Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */
> -#define Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */
> -
> -#define Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */
> -#define Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */
> -#define Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */
> -#define Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */
> -#define Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */
> -#define Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */
> -#define Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */
> -
> -/* Those are still used in some places */
> -#define _Ser1UTCR0 __PREG(Ser1UTCR0)
> -#define _Ser2UTCR0 __PREG(Ser2UTCR0)
> -#define _Ser3UTCR0 __PREG(Ser3UTCR0)
> -
> -/* Register offsets */
> -#define UTCR0 0x00
> -#define UTCR1 0x04
> -#define UTCR2 0x08
> -#define UTCR3 0x0c
> -#define UTDR 0x14
> -#define UTSR0 0x1c
> -#define UTSR1 0x20
> -
> -#define UTCR0_PE 0x00000001 /* Parity Enable */
> -#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */
> -#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */
> -#define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */
> -#define UTCR0_SBS 0x00000004 /* Stop Bit Select */
> -#define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */
> -#define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */
> -#define UTCR0_DSS 0x00000008 /* Data Size Select */
> -#define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */
> -#define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */
> -#define UTCR0_SCE 0x00000010 /* Sample Clock Enable */
> - /* (ser. port 1: GPIO [18], */
> - /* ser. port 3: GPIO [20]) */
> -#define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */
> -#define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */
> -#define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */
> -#define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */
> -#define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */
> -#define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */
> -#define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \
> - (UTCR0_1StpBit + UTCR0_8BitData)
> -
> -#define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
> -#define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
> - /* fua = fxtl/(16*(BRD[11:0] + 1)) */
> - /* Tua = 16*(BRD [11:0] + 1)*Txtl */
> -#define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
> - (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
> - FShft (UTCR1_BRD))
> -#define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
> - (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
> - FShft (UTCR2_BRD))
> - /* fua = fxtl/(16*Floor (Div/16)) */
> - /* Tua = 16*Floor (Div/16)*Txtl */
> -#define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
> - (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
> - FShft (UTCR1_BRD))
> -#define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
> - (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
> - FShft (UTCR2_BRD))
> - /* fua = fxtl/(16*Ceil (Div/16)) */
> - /* Tua = 16*Ceil (Div/16)*Txtl */
> -
> -#define UTCR3_RXE 0x00000001 /* Receive Enable */
> -#define UTCR3_TXE 0x00000002 /* Transmit Enable */
> -#define UTCR3_BRK 0x00000004 /* BReaK mode */
> -#define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
> - /* more Interrupt Enable */
> -#define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
> - /* Interrupt Enable */
> -#define UTCR3_LBM 0x00000020 /* Look-Back Mode */
> -#define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \
> - /* TIE, LBM can be set or cleared) */ \
> - (UTCR3_RXE + UTCR3_TXE)
> -
> -#define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */
> - /* (HP-SIR) modulation Enable */
> -#define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */
> -#define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */
> -#define UTCR4_LPM 0x00000002 /* Low-Power Mode */
> -#define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */
> -#define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */
> -
> -#define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
> -#if 0 /* Hidden receive FIFO bits */
> -#define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */
> -#define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */
> -#define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
> -#endif /* 0 */
> -
> -#define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */
> - /* Service request (read) */
> -#define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */
> - /* more Service request (read) */
> -#define UTSR0_RID 0x00000004 /* Receiver IDle */
> -#define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */
> -#define UTSR0_REB 0x00000010 /* Receive End of Break */
> -#define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */
> -
> -#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
> -#define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */
> -#define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
> -#define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */
> -#define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */
> -#define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */
> -
> -
> -/*
> - * Synchronous Data Link Controller (SDLC) control registers
> - *
> - * Registers
> - * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC)
> - * Control Register 0 (read/write).
> - * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC)
> - * Control Register 1 (read/write).
> - * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC)
> - * Control Register 2 (read/write).
> - * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC)
> - * Control Register 3 (read/write).
> - * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC)
> - * Control Register 4 (read/write).
> - * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC)
> - * Data Register (read/write).
> - * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC)
> - * Status Register 0 (read/write).
> - * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC)
> - * Status Register 1 (read/write).
> - *
> - * Clocks
> - * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
> - * or 3.5795 MHz).
> - * fsd, Tsd Frequency, period of the SDLC communication.
> - */
> -
> -#define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */
> -#define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */
> -#define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */
> -#define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */
> -#define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */
> -#define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */
> -#define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */
> -#define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */
> -
> -#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */
> -#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */
> -#define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */
> -#define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */
> -#define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */
> -#define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */
> -#define SDCR0_LBM 0x00000004 /* Look-Back Mode */
> -#define SDCR0_BMS 0x00000008 /* Bit Modulation Select */
> -#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */
> -#define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */
> -#define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */
> -#define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */
> - /* (GPIO [16]) */
> -#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */
> -#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */
> -#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */
> -#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */
> -#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */
> -#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */
> -#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */
> -#define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */
> -
> -#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */
> - /* (GPIO [17]) */
> -#define SDCR1_TXE 0x00000002 /* Transmit Enable */
> -#define SDCR1_RXE 0x00000004 /* Receive Enable */
> -#define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
> - /* more Interrupt Enable */
> -#define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
> - /* Interrupt Enable */
> -#define SDCR1_AME 0x00000020 /* Address Match Enable */
> -#define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */
> -#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */
> -#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */
> -#define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */
> -
> -#define SDCR2_AMV Fld (8, 0) /* Address Match Value */
> -
> -#define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
> -#define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
> - /* fsd = fxtl/(16*(BRD[11:0] + 1)) */
> - /* Tsd = 16*(BRD[11:0] + 1)*Txtl */
> -#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
> - (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
> - FShft (SDCR3_BRD))
> -#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
> - (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
> - FShft (SDCR4_BRD))
> - /* fsd = fxtl/(16*Floor (Div/16)) */
> - /* Tsd = 16*Floor (Div/16)*Txtl */
> -#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
> - (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
> - FShft (SDCR3_BRD))
> -#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
> - (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
> - FShft (SDCR4_BRD))
> - /* fsd = fxtl/(16*Ceil (Div/16)) */
> - /* Tsd = 16*Ceil (Div/16)*Txtl */
> -
> -#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
> -#if 0 /* Hidden receive FIFO bits */
> -#define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
> -#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */
> -#define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
> -#endif /* 0 */
> -
> -#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */
> -#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
> -#define SDSR0_RAB 0x00000004 /* Receive ABort */
> -#define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
> - /* Service request (read) */
> -#define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */
> - /* more Service request (read) */
> -
> -#define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
> -#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */
> -#define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
> -#define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
> -#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */
> -#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
> -#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */
> -#define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */
> -
> -
> -/*
> - * High-Speed Serial to Parallel controller (HSSP) control registers
> - *
> - * Registers
> - * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel
> - * controller (HSSP) Control Register 0 (read/write).
> - * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel
> - * controller (HSSP) Control Register 1 (read/write).
> - * Ser2HSDR Serial port 2 High-Speed Serial to Parallel
> - * controller (HSSP) Data Register (read/write).
> - * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel
> - * controller (HSSP) Status Register 0 (read/write).
> - * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel
> - * controller (HSSP) Status Register 1 (read).
> - * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel
> - * controller (HSSP) Control Register 2 (read/write).
> - * [The HSCR2 register is only implemented in
> - * versions 2.0 (rev. = 8) and higher of the StrongARM
> - * SA-1100.]
> - */
> -
> -#define Ser2HSCR0 __REG(0x80040060) /* Ser. port 2 HSSP Control Reg. 0 */
> -#define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */
> -#define Ser2HSDR __REG(0x8004006C) /* Ser. port 2 HSSP Data Reg. */
> -#define Ser2HSSR0 __REG(0x80040074) /* Ser. port 2 HSSP Status Reg. 0 */
> -#define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */
> -#define Ser2HSCR2 __REG(0x90060028) /* Ser. port 2 HSSP Control Reg. 2 */
> -
> -#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */
> -#define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */
> -#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */
> -#define HSCR0_LBM 0x00000002 /* Look-Back Mode */
> -#define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */
> -#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */
> -#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */
> -#define HSCR0_TXE 0x00000008 /* Transmit Enable */
> -#define HSCR0_RXE 0x00000010 /* Receive Enable */
> -#define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */
> - /* more Interrupt Enable */
> -#define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */
> - /* Interrupt Enable */
> -#define HSCR0_AME 0x00000080 /* Address Match Enable */
> -
> -#define HSCR1_AMV Fld (8, 0) /* Address Match Value */
> -
> -#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
> -#if 0 /* Hidden receive FIFO bits */
> -#define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
> -#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */
> -#define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
> -#endif /* 0 */
> -
> -#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */
> -#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
> -#define HSSR0_RAB 0x00000004 /* Receive ABort */
> -#define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
> - /* Service request (read) */
> -#define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */
> - /* more Service request (read) */
> -#define HSSR0_FRE 0x00000020 /* receive FRaming Error */
> -
> -#define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
> -#define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */
> -#define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
> -#define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
> -#define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */
> -#define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */
> -#define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */
> -
> -#define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */
> -#define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */
> - /* (inverted) */
> -#define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */
> - /* (non-inverted) */
> -#define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */
> -#define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */
> - /* (inverted) */
> -#define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */
> - /* (non-inverted) */
> -
> -
> -/*
> - * Multi-media Communications Port (MCP) control registers
> - *
> - * Registers
> - * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP)
> - * Control Register 0 (read/write).
> - * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP)
> - * Data Register 0 (audio, read/write).
> - * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP)
> - * Data Register 1 (telecom, read/write).
> - * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP)
> - * Data Register 2 (CODEC registers, read/write).
> - * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP)
> - * Status Register (read/write).
> - * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP)
> - * Control Register 1 (read/write).
> - * [The MCCR1 register is only implemented in
> - * versions 2.0 (rev. = 8) and higher of the StrongARM
> - * SA-1100.]
> - *
> - * Clocks
> - * fmc, Tmc Frequency, period of the MCP communication (10 MHz,
> - * 12 MHz, or GPIO [21]).
> - * faud, Taud Frequency, period of the audio sampling.
> - * ftcm, Ttcm Frequency, period of the telecom sampling.
> - */
> -
> -#define Ser4MCCR0 __REG(0x80060000) /* Ser. port 4 MCP Control Reg. 0 */
> -#define Ser4MCDR0 __REG(0x80060008) /* Ser. port 4 MCP Data Reg. 0 (audio) */
> -#define Ser4MCDR1 __REG(0x8006000C) /* Ser. port 4 MCP Data Reg. 1 (telecom) */
> -#define Ser4MCDR2 __REG(0x80060010) /* Ser. port 4 MCP Data Reg. 2 (CODEC reg.) */
> -#define Ser4MCSR __REG(0x80060018) /* Ser. port 4 MCP Status Reg. */
> -#define Ser4MCCR1 __REG(0x90060030) /* Ser. port 4 MCP Control Reg. 1 */
> -
> -#define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */
> - /* [6..127] */
> - /* faud = fmc/(32*ASD) */
> - /* Taud = 32*ASD*Tmc */
> -#define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \
> - /* [192..4064] */ \
> - ((Div)/32 << FShft (MCCR0_ASD))
> - /* faud = fmc/(32*Floor (Div/32)) */
> - /* Taud = 32*Floor (Div/32)*Tmc */
> -#define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \
> - (((Div) + 31)/32 << FShft (MCCR0_ASD))
> - /* faud = fmc/(32*Ceil (Div/32)) */
> - /* Taud = 32*Ceil (Div/32)*Tmc */
> -#define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */
> - /* Divisor/32 [16..127] */
> - /* ftcm = fmc/(32*TSD) */
> - /* Ttcm = 32*TSD*Tmc */
> -#define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \
> - /* [512..4064] */ \
> - ((Div)/32 << FShft (MCCR0_TSD))
> - /* ftcm = fmc/(32*Floor (Div/32)) */
> - /* Ttcm = 32*Floor (Div/32)*Tmc */
> -#define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \
> - (((Div) + 31)/32 << FShft (MCCR0_TSD))
> - /* ftcm = fmc/(32*Ceil (Div/32)) */
> - /* Ttcm = 32*Ceil (Div/32)*Tmc */
> -#define MCCR0_MCE 0x00010000 /* MCP Enable */
> -#define MCCR0_ECS 0x00020000 /* External Clock Select */
> -#define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */
> -#define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */
> -#define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */
> - /* sampling/storing Mode */
> -#define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */
> -#define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */
> -#define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */
> - /* or less interrupt Enable */
> -#define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */
> - /* or more interrupt Enable */
> -#define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */
> - /* or less interrupt Enable */
> -#define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */
> - /* more interrupt Enable */
> -#define MCCR0_LBM 0x00800000 /* Look-Back Mode */
> -#define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */
> -#define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \
> - (((Div) - 1) << FShft (MCCR0_ECP))
> -
> -#define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */
> - /* FIFOs */
> -
> -#define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */
> - /* FIFOs */
> -
> - /* receive/transmit CODEC reg. */
> - /* FIFOs: */
> -#define MCDR2_DATA Fld (16, 0) /* reg. DATA */
> -#define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */
> -#define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */
> -#define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */
> -#define MCDR2_ADD Fld (4, 17) /* reg. ADDress */
> -
> -#define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */
> - /* or less Service request (read) */
> -#define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */
> - /* more Service request (read) */
> -#define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */
> - /* or less Service request (read) */
> -#define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */
> - /* or more Service request (read) */
> -#define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */
> -#define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */
> -#define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */
> -#define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */
> -#define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */
> - /* (read) */
> -#define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */
> - /* (read) */
> -#define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */
> - /* (read) */
> -#define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */
> - /* (read) */
> -#define MCSR_CWC 0x00001000 /* CODEC register Write Completed */
> - /* (read) */
> -#define MCSR_CRC 0x00002000 /* CODEC register Read Completed */
> - /* (read) */
> -#define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */
> -#define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */
> -
> -#define MCCR1_CFS 0x00100000 /* Clock Freq. Select */
> -#define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */
> - /* (11.981 MHz) */
> -#define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */
> - /* (9.585 MHz) */
> -
> -
> -/*
> - * Synchronous Serial Port (SSP) control registers
> - *
> - * Registers
> - * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control
> - * Register 0 (read/write).
> - * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control
> - * Register 1 (read/write).
> - * [Bits SPO and SP are only implemented in versions 2.0
> - * (rev. = 8) and higher of the StrongARM SA-1100.]
> - * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data
> - * Register (read/write).
> - * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status
> - * Register (read/write).
> - *
> - * Clocks
> - * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
> - * or 3.5795 MHz).
> - * fss, Tss Frequency, period of the SSP communication.
> - */
> -
> -#define Ser4SSCR0 __REG(0x80070060) /* Ser. port 4 SSP Control Reg. 0 */
> -#define Ser4SSCR1 __REG(0x80070064) /* Ser. port 4 SSP Control Reg. 1 */
> -#define Ser4SSDR __REG(0x8007006C) /* Ser. port 4 SSP Data Reg. */
> -#define Ser4SSSR __REG(0x80070074) /* Ser. port 4 SSP Status Reg. */
> -
> -#define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */
> -#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \
> - (((Size) - 1) << FShft (SSCR0_DSS))
> -#define SSCR0_FRF Fld (2, 4) /* FRame Format */
> -#define SSCR0_Motorola /* Motorola Serial Peripheral */ \
> - /* Interface (SPI) format */ \
> - (0 << FShft (SSCR0_FRF))
> -#define SSCR0_TI /* Texas Instruments Synchronous */ \
> - /* Serial format */ \
> - (1 << FShft (SSCR0_FRF))
> -#define SSCR0_National /* National Microwire format */ \
> - (2 << FShft (SSCR0_FRF))
> -#define SSCR0_SSE 0x00000080 /* SSP Enable */
> -#define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */
> - /* fss = fxtl/(2*(SCR + 1)) */
> - /* Tss = 2*(SCR + 1)*Txtl */
> -#define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \
> - (((Div) - 2)/2 << FShft (SSCR0_SCR))
> - /* fss = fxtl/(2*Floor (Div/2)) */
> - /* Tss = 2*Floor (Div/2)*Txtl */
> -#define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \
> - (((Div) - 1)/2 << FShft (SSCR0_SCR))
> - /* fss = fxtl/(2*Ceil (Div/2)) */
> - /* Tss = 2*Ceil (Div/2)*Txtl */
> -
> -#define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */
> - /* Interrupt Enable */
> -#define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */
> - /* Interrupt Enable */
> -#define SSCR1_LBM 0x00000004 /* Look-Back Mode */
> -#define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */
> -#define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */
> -#define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */
> -#define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */
> -#define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */
> - /* after frame (SFRM, 1st edge) */
> -#define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */
> - /* after frame (SFRM, 1st edge) */
> -#define SSCR1_ECS 0x00000020 /* External Clock Select */
> -#define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */
> -#define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */
> -
> -#define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */
> -
> -#define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */
> -#define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
> -#define SSSR_BSY 0x00000008 /* SSP BuSY (read) */
> -#define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */
> - /* Service request (read) */
> -#define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */
> - /* Service request (read) */
> -#define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */
> -
> -
> -/*
> - * Operating System (OS) timer control registers
> - *
> - * Registers
> - * OSMR0 Operating System (OS) timer Match Register 0
> - * (read/write).
> - * OSMR1 Operating System (OS) timer Match Register 1
> - * (read/write).
> - * OSMR2 Operating System (OS) timer Match Register 2
> - * (read/write).
> - * OSMR3 Operating System (OS) timer Match Register 3
> - * (read/write).
> - * OSCR Operating System (OS) timer Counter Register
> - * (read/write).
> - * OSSR Operating System (OS) timer Status Register
> - * (read/write).
> - * OWER Operating System (OS) timer Watch-dog Enable Register
> - * (read/write).
> - * OIER Operating System (OS) timer Interrupt Enable Register
> - * (read/write).
> - */
> -
> -#define OSMR0 io_p2v(0x90000000) /* OS timer Match Reg. 0 */
> -#define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */
> -#define OSMR2 io_p2v(0x90000008) /* OS timer Match Reg. 2 */
> -#define OSMR3 io_p2v(0x9000000c) /* OS timer Match Reg. 3 */
> -#define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */
> -#define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */
> -#define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */
> -#define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */
> -
> -#define OSSR_M(Nb) /* Match detected [0..3] */ \
> - (0x00000001 << (Nb))
> -#define OSSR_M0 OSSR_M (0) /* Match detected 0 */
> -#define OSSR_M1 OSSR_M (1) /* Match detected 1 */
> -#define OSSR_M2 OSSR_M (2) /* Match detected 2 */
> -#define OSSR_M3 OSSR_M (3) /* Match detected 3 */
> -
> -#define OWER_WME 0x00000001 /* Watch-dog Match Enable */
> - /* (set only) */
> -
> -#define OIER_E(Nb) /* match interrupt Enable [0..3] */ \
> - (0x00000001 << (Nb))
> -#define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */
> -#define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */
> -#define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */
> -#define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */
> -
> -
> -/*
> - * Power Manager (PM) control registers
> - *
> - * Registers
> - * PMCR Power Manager (PM) Control Register (read/write).
> - * PSSR Power Manager (PM) Sleep Status Register (read/write).
> - * PSPR Power Manager (PM) Scratch-Pad Register (read/write).
> - * PWER Power Manager (PM) Wake-up Enable Register
> - * (read/write).
> - * PCFR Power Manager (PM) general ConFiguration Register
> - * (read/write).
> - * PPCR Power Manager (PM) Phase-Locked Loop (PLL)
> - * Configuration Register (read/write).
> - * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO)
> - * Sleep state Register (read/write, see GPIO pins).
> - * POSR Power Manager (PM) Oscillator Status Register (read).
> - *
> - * Clocks
> - * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
> - * or 3.5795 MHz).
> - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
> - */
> -
> -#define PMCR __REG(0x90020000) /* PM Control Reg. */
> -#define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */
> -#define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */
> -#define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */
> -#define PCFR __REG(0x90020010) /* PM general ConFiguration Reg. */
> -#define PPCR __REG(0x90020014) /* PM PLL Configuration Reg. */
> -#define PGSR __REG(0x90020018) /* PM GPIO Sleep state Reg. */
> -#define POSR __REG(0x9002001C) /* PM Oscillator Status Reg. */
> -
> -#define PMCR_SF 0x00000001 /* Sleep Force (set only) */
> -
> -#define PSSR_SS 0x00000001 /* Software Sleep */
> -#define PSSR_BFS 0x00000002 /* Battery Fault Status */
> - /* (BATT_FAULT) */
> -#define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */
> -#define PSSR_DH 0x00000008 /* DRAM control Hold */
> -#define PSSR_PH 0x00000010 /* Peripheral control Hold */
> -
> -#define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */
> -#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
> -#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
> -#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
> -#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
> -#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
> -#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
> -#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
> -#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
> -#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
> -#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
> -#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
> -#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
> -#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
> -#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
> -#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
> -#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
> -#define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */
> -#define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */
> -#define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */
> -#define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */
> -#define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */
> -#define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */
> -#define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */
> -#define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */
> -#define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */
> -#define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */
> -#define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */
> -#define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */
> -#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
> -
> -#define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */
> -#define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */
> -#define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */
> -#define PCFR_FP 0x00000002 /* Float PCMCIA pins */
> -#define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */
> -#define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */
> -#define PCFR_FS 0x00000004 /* Float Static memory pins */
> -#define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */
> -#define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */
> -#define PCFR_FO 0x00000008 /* Force RTC oscillator */
> - /* (32.768 kHz) enable On */
> -
> -#define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */
> -#define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \
> - (0x00 << FShft (PPCR_CCF))
> -#define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \
> - (0x01 << FShft (PPCR_CCF))
> -#define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \
> - (0x02 << FShft (PPCR_CCF))
> -#define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \
> - (0x03 << FShft (PPCR_CCF))
> -#define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \
> - (0x04 << FShft (PPCR_CCF))
> -#define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \
> - (0x05 << FShft (PPCR_CCF))
> -#define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \
> - (0x06 << FShft (PPCR_CCF))
> -#define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \
> - (0x07 << FShft (PPCR_CCF))
> -#define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \
> - (0x08 << FShft (PPCR_CCF))
> -#define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \
> - (0x09 << FShft (PPCR_CCF))
> -#define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \
> - (0x0A << FShft (PPCR_CCF))
> -#define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \
> - (0x0B << FShft (PPCR_CCF))
> -#define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \
> - (0x0C << FShft (PPCR_CCF))
> -#define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \
> - (0x0D << FShft (PPCR_CCF))
> -#define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \
> - (0x0E << FShft (PPCR_CCF))
> -#define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \
> - (0x0F << FShft (PPCR_CCF))
> - /* 3.6864 MHz crystal (fxtl): */
> -#define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */
> -#define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */
> -#define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */
> -#define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */
> -#define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */
> -#define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */
> -#define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */
> -#define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */
> -#define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */
> -#define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */
> -#define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */
> -#define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */
> -#define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */
> -#define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */
> -#define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */
> -#define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */
> - /* 3.5795 MHz crystal (fxtl): */
> -#define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */
> -#define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */
> -#define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */
> -#define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */
> -#define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */
> -#define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */
> -#define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */
> -#define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */
> -#define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */
> -#define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */
> -#define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */
> -#define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */
> -#define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */
> -#define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */
> -#define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */
> -#define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */
> -
> -#define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */
> -
> -
> -/*
> - * Reset Controller (RC) control registers
> - *
> - * Registers
> - * RSRR Reset Controller (RC) Software Reset Register
> - * (read/write).
> - * RCSR Reset Controller (RC) Status Register (read/write).
> - */
> -
> -#define RSRR __REG(0x90030000) /* RC Software Reset Reg. */
> -#define RCSR __REG(0x90030004) /* RC Status Reg. */
> -
> -#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */
> -
> -#define RCSR_HWR 0x00000001 /* HardWare Reset */
> -#define RCSR_SWR 0x00000002 /* SoftWare Reset */
> -#define RCSR_WDR 0x00000004 /* Watch-Dog Reset */
> -#define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */
> -
> -
> -/*
> - * Test unit control registers
> - *
> - * Registers
> - * TUCR Test Unit Control Register (read/write).
> - */
> -
> -#define TUCR __REG(0x90030008) /* Test Unit Control Reg. */
> -
> -#define TUCR_TIC 0x00000040 /* TIC mode */
> -#define TUCR_TTST 0x00000080 /* Trim TeST mode */
> -#define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */
> - /* Check */
> -#define TUCR_PMD 0x00000200 /* Power Management Disable */
> -#define TUCR_MR 0x00000400 /* Memory Request mode */
> -#define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */
> -#define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */
> - /* grant (MBGNT) on GPIO [22:21] */
> -#define TUCR_CTB Fld (3, 20) /* Clock Test Bits */
> -#define TUCR_FDC 0x00800000 /* RTC Force Delete Count */
> -#define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */
> -#define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */
> -#define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */
> -#define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */
> -#define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \
> - (0 << FShft (TUCR_TSEL))
> -#define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \
> - (1 << FShft (TUCR_TSEL))
> -#define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \
> - (2 << FShft (TUCR_TSEL))
> -#define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \
> - (3 << FShft (TUCR_TSEL))
> -#define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \
> - /* Clocks on GPIO [26:27] */ \
> - (4 << FShft (TUCR_TSEL))
> -#define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \
> - /* (Alternative) */ \
> - (5 << FShft (TUCR_TSEL))
> -#define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \
> - (6 << FShft (TUCR_TSEL))
> -#define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \
> - (7 << FShft (TUCR_TSEL))
> -
> -
> -/*
> - * General-Purpose Input/Output (GPIO) control registers
> - *
> - * Registers
> - * GPLR General-Purpose Input/Output (GPIO) Pin Level
> - * Register (read).
> - * GPDR General-Purpose Input/Output (GPIO) Pin Direction
> - * Register (read/write).
> - * GPSR General-Purpose Input/Output (GPIO) Pin output Set
> - * Register (write).
> - * GPCR General-Purpose Input/Output (GPIO) Pin output Clear
> - * Register (write).
> - * GRER General-Purpose Input/Output (GPIO) Rising-Edge
> - * detect Register (read/write).
> - * GFER General-Purpose Input/Output (GPIO) Falling-Edge
> - * detect Register (read/write).
> - * GEDR General-Purpose Input/Output (GPIO) Edge Detect
> - * status Register (read/write).
> - * GAFR General-Purpose Input/Output (GPIO) Alternate
> - * Function Register (read/write).
> - *
> - * Clock
> - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
> - */
> -
> -#define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */
> -#define GPDR __REG(0x90040004) /* GPIO Pin Direction Reg. */
> -#define GPSR __REG(0x90040008) /* GPIO Pin output Set Reg. */
> -#define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */
> -#define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */
> -#define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */
> -#define GEDR __REG(0x90040018) /* GPIO Edge Detect status Reg. */
> -#define GAFR __REG(0x9004001C) /* GPIO Alternate Function Reg. */
> -
> -#define GPIO_MIN (0)
> -#define GPIO_MAX (27)
> -
> -#define GPIO_GPIO(Nb) /* GPIO [0..27] */ \
> - (0x00000001 << (Nb))
> -#define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */
> -#define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */
> -#define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */
> -#define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */
> -#define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */
> -#define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */
> -#define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */
> -#define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */
> -#define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */
> -#define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */
> -#define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */
> -#define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */
> -#define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */
> -#define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */
> -#define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */
> -#define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */
> -#define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */
> -#define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */
> -#define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */
> -#define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */
> -#define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */
> -#define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */
> -#define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */
> -#define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */
> -#define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */
> -#define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */
> -#define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */
> -#define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */
> -
> -#define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \
> - GPIO_GPIO ((Nb) - 6)
> -#define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */
> -#define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */
> -#define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */
> -#define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */
> -#define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */
> -#define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */
> -#define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */
> -#define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */
> - /* ser. port 4: */
> -#define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */
> -#define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */
> -#define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */
> -#define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */
> - /* ser. port 1: */
> -#define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */
> -#define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */
> -#define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */
> -#define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */
> -#define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */
> - /* ser. port 4: */
> -#define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */
> - /* ser. port 3: */
> -#define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */
> - /* ser. port 4: */
> -#define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */
> - /* test controller: */
> -#define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */
> -#define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */
> -#define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */
> -#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */
> -#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */
> -#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */
> -#define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */
> -#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */
> -
> -#define GPDR_In 0 /* Input */
> -#define GPDR_Out 1 /* Output */
> -
> -
> -/*
> - * Interrupt Controller (IC) control registers
> - *
> - * Registers
> - * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ)
> - * Pending register (read).
> - * ICMR Interrupt Controller (IC) Mask Register (read/write).
> - * ICLR Interrupt Controller (IC) Level Register (read/write).
> - * ICCR Interrupt Controller (IC) Control Register
> - * (read/write).
> - * [The ICCR register is only implemented in versions 2.0
> - * (rev. = 8) and higher of the StrongARM SA-1100.]
> - * ICFP Interrupt Controller (IC) Fast Interrupt reQuest
> - * (FIQ) Pending register (read).
> - * ICPR Interrupt Controller (IC) Pending Register (read).
> - * [The ICPR register is active low (inverted) in
> - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
> - * StrongARM SA-1100, it is active high (non-inverted) in
> - * versions 2.0 (rev. = 8) and higher.]
> - */
> -
> -#define ICIP __REG(0x90050000) /* IC IRQ Pending reg. */
> -#define ICMR __REG(0x90050004) /* IC Mask Reg. */
> -#define ICLR __REG(0x90050008) /* IC Level Reg. */
> -#define ICCR __REG(0x9005000C) /* IC Control Reg. */
> -#define ICFP __REG(0x90050010) /* IC FIQ Pending reg. */
> -#define ICPR __REG(0x90050020) /* IC Pending Reg. */
> -
> -#define IC_GPIO(Nb) /* GPIO [0..10] */ \
> - (0x00000001 << (Nb))
> -#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */
> -#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */
> -#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */
> -#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */
> -#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */
> -#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */
> -#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */
> -#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */
> -#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */
> -#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */
> -#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */
> -#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */
> -#define IC_LCD 0x00001000 /* LCD controller */
> -#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */
> -#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */
> -#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */
> -#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */
> -#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */
> -#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */
> -#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */
> -#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \
> - (0x00100000 << (Nb))
> -#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */
> -#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */
> -#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */
> -#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */
> -#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */
> -#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */
> -#define IC_OST(Nb) /* OS Timer match [0..3] */ \
> - (0x04000000 << (Nb))
> -#define IC_OST0 IC_OST (0) /* OS Timer match 0 */
> -#define IC_OST1 IC_OST (1) /* OS Timer match 1 */
> -#define IC_OST2 IC_OST (2) /* OS Timer match 2 */
> -#define IC_OST3 IC_OST (3) /* OS Timer match 3 */
> -#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */
> -#define IC_RTCAlrm 0x80000000 /* RTC Alarm */
> -
> -#define ICLR_IRQ 0 /* Interrupt ReQuest */
> -#define ICLR_FIQ 1 /* Fast Interrupt reQuest */
> -
> -#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */
> - /* Mask */
> -#define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */
> - /* (ICMR ignored) */
> -#define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */
> - /* enable (ICMR used) */
> -
> -
> -/*
> - * Peripheral Pin Controller (PPC) control registers
> - *
> - * Registers
> - * PPDR Peripheral Pin Controller (PPC) Pin Direction
> - * Register (read/write).
> - * PPSR Peripheral Pin Controller (PPC) Pin State Register
> - * (read/write).
> - * PPAR Peripheral Pin Controller (PPC) Pin Assignment
> - * Register (read/write).
> - * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin
> - * Direction Register (read/write).
> - * PPFR Peripheral Pin Controller (PPC) Pin Flag Register
> - * (read).
> - */
> -
> -#define PPDR __REG(0x90060000) /* PPC Pin Direction Reg. */
> -#define PPSR __REG(0x90060004) /* PPC Pin State Reg. */
> -#define PPAR __REG(0x90060008) /* PPC Pin Assignment Reg. */
> -#define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */
> -#define PPFR __REG(0x90060010) /* PPC Pin Flag Reg. */
> -
> -#define PPC_LDD(Nb) /* LCD Data [0..7] */ \
> - (0x00000001 << (Nb))
> -#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */
> -#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */
> -#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */
> -#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */
> -#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */
> -#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */
> -#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */
> -#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */
> -#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */
> -#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */
> -#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */
> -#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */
> - /* ser. port 1: */
> -#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */
> -#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */
> - /* ser. port 2: */
> -#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */
> -#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */
> - /* ser. port 3: */
> -#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */
> -#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */
> - /* ser. port 4: */
> -#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */
> -#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */
> -#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */
> -#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */
> -
> -#define PPDR_In 0 /* Input */
> -#define PPDR_Out 1 /* Output */
> -
> - /* ser. port 1: */
> -#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */
> -#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */
> -#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */
> - /* ser. port 4: */
> -#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */
> -#define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */
> - /* & SFRM_C */
> -#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */
> -
> -#define PSDR_OutL 0 /* Output Low in sleep mode */
> -#define PSDR_Flt 1 /* Floating (input) in sleep mode */
> -
> -#define PPFR_LCD 0x00000001 /* LCD controller */
> -#define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */
> -#define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */
> -#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */
> -#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */
> -#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */
> -#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */
> -#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */
> -#define PPFR_PerEn 0 /* Peripheral Enabled */
> -#define PPFR_PPCEn 1 /* PPC Enabled */
> -
> -
> -/*
> - * Dynamic Random-Access Memory (DRAM) control registers
> - *
> - * Registers
> - * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM)
> - * CoNFiGuration register (read/write).
> - * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM)
> - * Column Address Strobe (CAS) shift register 0
> - * (read/write).
> - * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM)
> - * Column Address Strobe (CAS) shift register 1
> - * (read/write).
> - * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM)
> - * Column Address Strobe (CAS) shift register 2
> - * (read/write).
> - *
> - * Clocks
> - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
> - * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
> - * fcas, Tcas Frequency, period of the DRAM CAS shift registers.
> - */
> -
> -#define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */
> -#define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */
> -#define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */
> -#define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */
> -
> -/* SA1100 MDCNFG values */
> -#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \
> - (0x00000001 << (Nb))
> -#define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */
> -#define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */
> -#define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */
> -#define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */
> -#define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */
> -#define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \
> - (((Add) - 9) << FShft (MDCNFG_DRAC))
> -#define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */
> - /* (fcas = fcpu/2) */
> -#define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */
> -#define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \
> - (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
> -#define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \
> - (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
> -#define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */
> -#define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \
> - (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
> -#define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \
> - (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
> -#define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */
> -#define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \
> - ((Tcpu) << FShft (MDCNFG_TDL))
> -#define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */
> - /* [Tmem] */
> -#define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \
> - /* [0..262136 Tcpu] */ \
> - ((Tcpu)/8 << FShft (MDCNFG_DRI))
> -
> -/* SA1110 MDCNFG values */
> -#define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */
> -#define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */
> -#define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */
> -#define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */
> -#define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */
> - /* bank 0/1 */
> -#define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */
> -#define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */
> -#define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/
> - /* deassertion 0/1 */
> -#define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */
> -#define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */
> -#define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */
> -#define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */
> -#define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */
> -#define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */
> - /* bank 0/1 */
> -#define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */
> -#define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */
> -#define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/
> - /* deassertion 0/1 */
> -#define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */
> -
> -
> -/*
> - * Static memory control registers
> - *
> - * Registers
> - * MSC0 Memory system: Static memory Control register 0
> - * (read/write).
> - * MSC1 Memory system: Static memory Control register 1
> - * (read/write).
> - *
> - * Clocks
> - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
> - * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
> - */
> -
> -#define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */
> -#define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */
> -#define MSC2 __REG(0xa000002c) /* Static memory Control reg. 2, not contiguous */
> -
> -#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \
> - Fld (16, ((Nb) Modulo 2)*16)
> -#define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */
> -#define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */
> -#define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */
> -#define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */
> -
> -#define MSC_RT Fld (2, 0) /* ROM/static memory Type */
> -#define MSC_NonBrst /* Non-Burst static memory */ \
> - (0 << FShft (MSC_RT))
> -#define MSC_SRAM /* 32-bit byte-writable SRAM */ \
> - (1 << FShft (MSC_RT))
> -#define MSC_Brst4 /* Burst-of-4 static memory */ \
> - (2 << FShft (MSC_RT))
> -#define MSC_Brst8 /* Burst-of-8 static memory */ \
> - (3 << FShft (MSC_RT))
> -#define MSC_RBW 0x0004 /* ROM/static memory Bus Width */
> -#define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */
> -#define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */
> -#define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */
> - /* First access - 1(.5) [Tmem] */
> -#define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \
> - /* static memory) [3..65 Tcpu] */ \
> - ((((Tcpu) - 3)/2) << FShft (MSC_RDF))
> -#define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \
> - ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
> -#define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \
> - /* static memory) [2..64 Tcpu] */ \
> - ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
> -#define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \
> - ((((Tcpu) - 1)/2) << FShft (MSC_RDF))
> -#define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */
> - /* Next access - 1 [Tmem] */
> -#define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \
> - /* static memory) [2..64 Tcpu] */ \
> - ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
> -#define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \
> - ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
> -#define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \
> - /* static memory) [2..64 Tcpu] */ \
> - ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
> -#define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \
> - ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
> -#define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */
> - /* time/2 [Tmem] */
> -#define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \
> - (((Tcpu)/4) << FShft (MSC_RRR))
> -#define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \
> - ((((Tcpu) + 3)/4) << FShft (MSC_RRR))
> -
> -
> -/*
> - * Personal Computer Memory Card International Association (PCMCIA) control
> - * register
> - *
> - * Register
> - * MECR Memory system: Expansion memory bus (PCMCIA)
> - * Configuration Register (read/write).
> - *
> - * Clocks
> - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
> - * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
> - * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK).
> - */
> -
> - /* Memory system: */
> -#define MECR __REG(0xA0000018) /* Expansion memory bus (PCMCIA) Configuration Reg. */
> -
> -#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \
> - Fld (15, (Nb)*16)
> -#define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */
> -#define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */
> -
> -#define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */
> -#define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \
> - ((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
> -#define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \
> - ((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
> -#define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */
> - /* [Tmem] */
> -#define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \
> - ((((Tcpu) - 2)/2) << FShft (MECR_BSA))
> -#define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \
> - ((((Tcpu) - 1)/2) << FShft (MECR_BSA))
> -#define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */
> -#define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \
> - ((((Tcpu) - 2)/2) << FShft (MECR_BSM))
> -#define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \
> - ((((Tcpu) - 1)/2) << FShft (MECR_BSM))
> -
> -/*
> - * On SA1110 only
> - */
> -
> -#define MDREFR __REG(0xA000001C)
> -
> -#define MDREFR_TRASR Fld (4, 0)
> -#define MDREFR_DRI Fld (12, 4)
> -#define MDREFR_E0PIN (1 << 16)
> -#define MDREFR_K0RUN (1 << 17)
> -#define MDREFR_K0DB2 (1 << 18)
> -#define MDREFR_E1PIN (1 << 20)
> -#define MDREFR_K1RUN (1 << 21)
> -#define MDREFR_K1DB2 (1 << 22)
> -#define MDREFR_K2RUN (1 << 25)
> -#define MDREFR_K2DB2 (1 << 26)
> -#define MDREFR_EAPD (1 << 28)
> -#define MDREFR_KAPD (1 << 29)
> -#define MDREFR_SLFRSH (1 << 31)
> -
> -
> -/*
> - * Direct Memory Access (DMA) control registers
> - */
> -#define DMA_SIZE (6 * 0x20)
> -#define DMA_PHYS 0xb0000000
> -
> -
> -/*
> - * Liquid Crystal Display (LCD) control registers
> - *
> - * Registers
> - * LCCR0 Liquid Crystal Display (LCD) Control Register 0
> - * (read/write).
> - * [Bits LDM, BAM, and ERM are only implemented in
> - * versions 2.0 (rev. = 8) and higher of the StrongARM
> - * SA-1100.]
> - * LCSR Liquid Crystal Display (LCD) Status Register
> - * (read/write).
> - * [Bit LDD can be only read in versions 1.0 (rev. = 1)
> - * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
> - * read and written (cleared) in versions 2.0 (rev. = 8)
> - * and higher.]
> - * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access
> - * (DMA) Base Address Register channel 1 (read/write).
> - * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access
> - * (DMA) Current Address Register channel 1 (read).
> - * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access
> - * (DMA) Base Address Register channel 2 (read/write).
> - * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access
> - * (DMA) Current Address Register channel 2 (read).
> - * LCCR1 Liquid Crystal Display (LCD) Control Register 1
> - * (read/write).
> - * [The LCCR1 register can be only written in
> - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
> - * StrongARM SA-1100, it can be written and read in
> - * versions 2.0 (rev. = 8) and higher.]
> - * LCCR2 Liquid Crystal Display (LCD) Control Register 2
> - * (read/write).
> - * [The LCCR1 register can be only written in
> - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
> - * StrongARM SA-1100, it can be written and read in
> - * versions 2.0 (rev. = 8) and higher.]
> - * LCCR3 Liquid Crystal Display (LCD) Control Register 3
> - * (read/write).
> - * [The LCCR1 register can be only written in
> - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
> - * StrongARM SA-1100, it can be written and read in
> - * versions 2.0 (rev. = 8) and higher. Bit PCP is only
> - * implemented in versions 2.0 (rev. = 8) and higher of
> - * the StrongARM SA-1100.]
> - *
> - * Clocks
> - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
> - * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
> - * fpix, Tpix Frequency, period of the pixel clock.
> - * fln, Tln Frequency, period of the line clock.
> - * fac, Tac Frequency, period of the AC bias clock.
> - */
> -
> -#define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */
> -#define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \
> - /* [byte] */ \
> - (16*LCD_PEntrySp)
> -#define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \
> - /* [byte] */ \
> - (256*LCD_PEntrySp)
> -#define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \
> - /* dummy-Palette Space [byte] */ \
> - (16*LCD_PEntrySp)
> -
> -#define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */
> -#define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */
> -#define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */
> -#define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */
> -#define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */
> -#define LCD_4Bit /* LCD 4-Bit pixel mode */ \
> - (0 << FShft (LCD_PBS))
> -#define LCD_8Bit /* LCD 8-Bit pixel mode */ \
> - (1 << FShft (LCD_PBS))
> -#define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \
> - (2 << FShft (LCD_PBS))
> -
> -#define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */
> -#define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */
> -#define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */
> -#define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */
> -#define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */
> -#define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */
> -#define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */
> -#define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */
> -#define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */
> -#define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */
> -#define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */
> -#define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */
> -#define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */
> -#define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */
> -#define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */
> -#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
> - /* (Alternative) */
> -
> -#define LCCR0_LEN 0x00000001 /* LCD ENable */
> -#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */
> -#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
> -#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
> -#define LCCR0_SDS 0x00000004 /* Single/Dual panel display */
> - /* Select */
> -#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
> -#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
> -#define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */
> - /* interrupt Mask (disable) */
> -#define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */
> - /* interrupt Mask (disable) */
> -#define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */
> - /* IUU, OOL, OUL, OOU, and OUU) */
> - /* interrupt Mask (disable) */
> -#define LCCR0_PAS 0x00000080 /* Passive/Active display Select */
> -#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
> -#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
> -#define LCCR0_BLE 0x00000100 /* Big/Little Endian select */
> -#define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */
> -#define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */
> -#define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */
> - /* display mode) */
> -#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
> - /* display */
> -#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
> - /* display */
> -#define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */
> - /* [Tmem] */
> -#define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \
> - /* [0..510 Tcpu] */ \
> - ((Tcpu)/2 << FShft (LCCR0_PDD))
> -
> -#define LCSR_LDD 0x00000001 /* LCD Disable Done */
> -#define LCSR_BAU 0x00000002 /* Base Address Update (read) */
> -#define LCSR_BER 0x00000004 /* Bus ERror */
> -#define LCSR_ABC 0x00000008 /* AC Bias clock Count */
> -#define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */
> - /* panel */
> -#define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */
> - /* panel */
> -#define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */
> - /* panel */
> -#define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */
> - /* panel */
> -#define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */
> - /* panel */
> -#define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */
> - /* panel */
> -#define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */
> - /* panel */
> -#define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */
> - /* panel */
> -
> -#define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */
> -#define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \
> - (((Pixel) - 16)/16 << FShft (LCCR1_PPL))
> -#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
> - /* pulse Width - 1 [Tpix] (L_LCLK) */
> -#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
> - /* pulse Width [1..64 Tpix] */ \
> - (((Tpix) - 1) << FShft (LCCR1_HSW))
> -#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
> - /* count - 1 [Tpix] */
> -#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
> - /* [1..256 Tpix] */ \
> - (((Tpix) - 1) << FShft (LCCR1_ELW))
> -#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
> - /* Wait count - 1 [Tpix] */
> -#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
> - /* [1..256 Tpix] */ \
> - (((Tpix) - 1) << FShft (LCCR1_BLW))
> -
> -#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
> -#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
> - (((Line) - 1) << FShft (LCCR2_LPP))
> -#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
> - /* Width - 1 [Tln] (L_FCLK) */
> -#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
> - /* Width [1..64 Tln] */ \
> - (((Tln) - 1) << FShft (LCCR2_VSW))
> -#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
> - /* count [Tln] */
> -#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
> - /* [0..255 Tln] */ \
> - ((Tln) << FShft (LCCR2_EFW))
> -#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
> - /* Wait count [Tln] */
> -#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
> - /* [0..255 Tln] */ \
> - ((Tln) << FShft (LCCR2_BFW))
> -
> -#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
> - /* [1..255] (L_PCLK) */
> - /* fpix = fcpu/(2*(PCD + 2)) */
> - /* Tpix = 2*(PCD + 2)*Tcpu */
> -#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \
> - (((Div) - 4)/2 << FShft (LCCR3_PCD))
> - /* fpix = fcpu/(2*Floor (Div/2)) */
> - /* Tpix = 2*Floor (Div/2)*Tcpu */
> -#define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \
> - (((Div) - 3)/2 << FShft (LCCR3_PCD))
> - /* fpix = fcpu/(2*Ceil (Div/2)) */
> - /* Tpix = 2*Ceil (Div/2)*Tcpu */
> -#define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */
> - /* [Tln] (L_BIAS) */
> -#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \
> - (((Div) - 2)/2 << FShft (LCCR3_ACB))
> - /* fac = fln/(2*Floor (Div/2)) */
> - /* Tac = 2*Floor (Div/2)*Tln */
> -#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \
> - (((Div) - 1)/2 << FShft (LCCR3_ACB))
> - /* fac = fln/(2*Ceil (Div/2)) */
> - /* Tac = 2*Ceil (Div/2)*Tln */
> -#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */
> - /* Interrupt */
> -#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \
> - /* Off */ \
> - (0 << FShft (LCCR3_API))
> -#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \
> - /* [1..15] */ \
> - ((Trans) << FShft (LCCR3_API))
> -#define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */
> - /* Polarity (L_FCLK) */
> -#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
> - /* active High */
> -#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
> - /* active Low */
> -#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */
> - /* pulse Polarity (L_LCLK) */
> -#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
> - /* pulse active High */
> -#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
> - /* pulse active Low */
> -#define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */
> -#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
> -#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
> -#define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */
> - /* active display mode) */
> -#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
> -#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
> diff --git a/arch/arm/mach-sa1100/include/mach/assabet.h b/arch/arm/mach-sa1100/include/mach/assabet.h
> deleted file mode 100644
> index 641a961653af..000000000000
> --- a/arch/arm/mach-sa1100/include/mach/assabet.h
> +++ /dev/null
> @@ -1,99 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * arch/arm/mach-sa1100/include/mach/assabet.h
> - *
> - * Created 2000/06/05 by Nicolas Pitre <nico@fluxnic.net>
> - *
> - * This file contains the hardware specific definitions for Assabet
> - * Only include this file from SA1100-specific files.
> - *
> - * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
> - * Definitions for Neponset added.
> - */
> -#ifndef __ASM_ARCH_ASSABET_H
> -#define __ASM_ARCH_ASSABET_H
> -
> -
> -/* System Configuration Register flags */
> -
> -#define ASSABET_SCR_SDRAM_LOW (1<<2) /* SDRAM size (low bit) */
> -#define ASSABET_SCR_SDRAM_HIGH (1<<3) /* SDRAM size (high bit) */
> -#define ASSABET_SCR_FLASH_LOW (1<<4) /* Flash size (low bit) */
> -#define ASSABET_SCR_FLASH_HIGH (1<<5) /* Flash size (high bit) */
> -#define ASSABET_SCR_GFX (1<<8) /* Graphics Accelerator (0 = present) */
> -#define ASSABET_SCR_SA1111 (1<<9) /* Neponset (0 = present) */
> -
> -#define ASSABET_SCR_INIT -1
> -
> -extern unsigned long SCR_value;
> -
> -#ifdef CONFIG_ASSABET_NEPONSET
> -#define machine_has_neponset() ((SCR_value & ASSABET_SCR_SA1111) == 0)
> -#else
> -#define machine_has_neponset() (0)
> -#endif
> -
> -/* Board Control Register */
> -
> -#define ASSABET_BCR_BASE 0xf1000000
> -#define ASSABET_BCR (*(volatile unsigned int *)(ASSABET_BCR_BASE))
> -
> -#define ASSABET_BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */
> -#define ASSABET_BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */
> -#define ASSABET_BCR_NGFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */
> -#define ASSABET_BCR_NCODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */
> -#define ASSABET_BCR_IRDA_FSEL (1<<3) /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */
> -#define ASSABET_BCR_IRDA_MD0 (1<<4) /* Range/Power select */
> -#define ASSABET_BCR_IRDA_MD1 (1<<5) /* Range/Power select */
> -#define ASSABET_BCR_STEREO_LB (1<<6) /* Stereo Loopback */
> -#define ASSABET_BCR_CF_BUS_OFF (1<<7) /* Compact Flash bus (0 = on, 1 = off (float)) */
> -#define ASSABET_BCR_AUDIO_ON (1<<8) /* Audio power on */
> -#define ASSABET_BCR_LIGHT_ON (1<<9) /* Backlight */
> -#define ASSABET_BCR_LCD_12RGB (1<<10) /* 0 = 16RGB, 1 = 12RGB */
> -#define ASSABET_BCR_LCD_ON (1<<11) /* LCD power on */
> -#define ASSABET_BCR_RS232EN (1<<12) /* RS232 transceiver enable */
> -#define ASSABET_BCR_LED_RED (1<<13) /* D9 (0 = on, 1 = off) */
> -#define ASSABET_BCR_LED_GREEN (1<<14) /* D8 (0 = on, 1 = off) */
> -#define ASSABET_BCR_VIB_ON (1<<15) /* Vibration motor (quiet alert) */
> -#define ASSABET_BCR_COM_DTR (1<<16) /* COMport Data Terminal Ready */
> -#define ASSABET_BCR_COM_RTS (1<<17) /* COMport Request To Send */
> -#define ASSABET_BCR_RAD_WU (1<<18) /* Radio wake up interrupt */
> -#define ASSABET_BCR_SMB_EN (1<<19) /* System management bus enable */
> -#define ASSABET_BCR_TV_IR_DEC (1<<20) /* TV IR Decode Enable (not implemented) */
> -#define ASSABET_BCR_QMUTE (1<<21) /* Quick Mute */
> -#define ASSABET_BCR_RAD_ON (1<<22) /* Radio Power On */
> -#define ASSABET_BCR_SPK_OFF (1<<23) /* 1 = Speaker amplifier power off */
> -
> -#ifdef CONFIG_SA1100_ASSABET
> -extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set);
> -#else
> -#define ASSABET_BCR_frob(x,y) do { } while (0)
> -#endif
> -
> -extern void assabet_uda1341_reset(int set);
> -
> -#define ASSABET_BCR_set(x) ASSABET_BCR_frob((x), (x))
> -#define ASSABET_BCR_clear(x) ASSABET_BCR_frob((x), 0)
> -
> -#define ASSABET_BSR_BASE 0xf1000000
> -#define ASSABET_BSR (*(volatile unsigned int*)(ASSABET_BSR_BASE))
> -
> -#define ASSABET_BSR_RS232_VALID (1 << 24)
> -#define ASSABET_BSR_COM_DCD (1 << 25)
> -#define ASSABET_BSR_COM_CTS (1 << 26)
> -#define ASSABET_BSR_COM_DSR (1 << 27)
> -#define ASSABET_BSR_RAD_CTS (1 << 28)
> -#define ASSABET_BSR_RAD_DSR (1 << 29)
> -#define ASSABET_BSR_RAD_DCD (1 << 30)
> -#define ASSABET_BSR_RAD_RI (1 << 31)
> -
> -
> -/* GPIOs (bitmasks) for which the generic definition doesn't say much */
> -#define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */
> -#define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */
> -#define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */
> -#define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */
> -#define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */
> -#define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */
> -
> -#endif
> diff --git a/arch/arm/mach-sa1100/include/mach/bitfield.h b/arch/arm/mach-sa1100/include/mach/bitfield.h
> deleted file mode 100644
> index f1f0e3387d9c..000000000000
> --- a/arch/arm/mach-sa1100/include/mach/bitfield.h
> +++ /dev/null
> @@ -1,113 +0,0 @@
> -/*
> - * FILE bitfield.h
> - *
> - * Version 1.1
> - * Author Copyright (c) Marc A. Viredaz, 1998
> - * DEC Western Research Laboratory, Palo Alto, CA
> - * Date April 1998 (April 1997)
> - * System Advanced RISC Machine (ARM)
> - * Language C or ARM Assembly
> - * Purpose Definition of macros to operate on bit fields.
> - */
> -
> -
> -
> -#ifndef __BITFIELD_H
> -#define __BITFIELD_H
> -
> -#ifndef __ASSEMBLY__
> -#define UData(Data) ((unsigned long) (Data))
> -#else
> -#define UData(Data) (Data)
> -#endif
> -
> -
> -/*
> - * MACRO: Fld
> - *
> - * Purpose
> - * The macro "Fld" encodes a bit field, given its size and its shift value
> - * with respect to bit 0.
> - *
> - * Note
> - * A more intuitive way to encode bit fields would have been to use their
> - * mask. However, extracting size and shift value information from a bit
> - * field's mask is cumbersome and might break the assembler (255-character
> - * line-size limit).
> - *
> - * Input
> - * Size Size of the bit field, in number of bits.
> - * Shft Shift value of the bit field with respect to bit 0.
> - *
> - * Output
> - * Fld Encoded bit field.
> - */
> -
> -#define Fld(Size, Shft) (((Size) << 16) + (Shft))
> -
> -
> -/*
> - * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
> - *
> - * Purpose
> - * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
> - * the size, shift value, mask, aligned mask, and first bit of a
> - * bit field.
> - *
> - * Input
> - * Field Encoded bit field (using the macro "Fld").
> - *
> - * Output
> - * FSize Size of the bit field, in number of bits.
> - * FShft Shift value of the bit field with respect to bit 0.
> - * FMsk Mask for the bit field.
> - * FAlnMsk Mask for the bit field, aligned on bit 0.
> - * F1stBit First bit of the bit field.
> - */
> -
> -#define FSize(Field) ((Field) >> 16)
> -#define FShft(Field) ((Field) & 0x0000FFFF)
> -#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
> -#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
> -#define F1stBit(Field) (UData (1) << FShft (Field))
> -
> -
> -/*
> - * MACRO: FInsrt
> - *
> - * Purpose
> - * The macro "FInsrt" inserts a value into a bit field by shifting the
> - * former appropriately.
> - *
> - * Input
> - * Value Bit-field value.
> - * Field Encoded bit field (using the macro "Fld").
> - *
> - * Output
> - * FInsrt Bit-field value positioned appropriately.
> - */
> -
> -#define FInsrt(Value, Field) \
> - (UData (Value) << FShft (Field))
> -
> -
> -/*
> - * MACRO: FExtr
> - *
> - * Purpose
> - * The macro "FExtr" extracts the value of a bit field by masking and
> - * shifting it appropriately.
> - *
> - * Input
> - * Data Data containing the bit-field to be extracted.
> - * Field Encoded bit field (using the macro "Fld").
> - *
> - * Output
> - * FExtr Bit-field value.
> - */
> -
> -#define FExtr(Data, Field) \
> - ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
> -
> -
> -#endif /* __BITFIELD_H */
> diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h
> deleted file mode 100644
> index c95273c9567b..000000000000
> --- a/arch/arm/mach-sa1100/include/mach/collie.h
> +++ /dev/null
> @@ -1,94 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * arch/arm/mach-sa1100/include/mach/collie.h
> - *
> - * This file contains the hardware specific definitions for Collie
> - * Only include this file from SA1100-specific files.
> - *
> - * ChangeLog:
> - * 04-06-2001 Lineo Japan, Inc.
> - * 04-16-2001 SHARP Corporation
> - * 07-07-2002 Chris Larson <clarson@digi.com>
> - *
> - */
> -#ifndef __ASM_ARCH_COLLIE_H
> -#define __ASM_ARCH_COLLIE_H
> -
> -#include "hardware.h" /* Gives GPIO_MAX */
> -
> -#define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1)
> -#define COLLIE_GPIO_CHARGE_ON (COLLIE_SCOOP_GPIO_BASE + 0)
> -#define COLLIE_SCP_DIAG_BOOT1 SCOOP_GPCR_PA12
> -#define COLLIE_SCP_DIAG_BOOT2 SCOOP_GPCR_PA13
> -#define COLLIE_SCP_MUTE_L SCOOP_GPCR_PA14
> -#define COLLIE_SCP_MUTE_R SCOOP_GPCR_PA15
> -#define COLLIE_SCP_5VON SCOOP_GPCR_PA16
> -#define COLLIE_SCP_AMP_ON SCOOP_GPCR_PA17
> -#define COLLIE_GPIO_VPEN (COLLIE_SCOOP_GPIO_BASE + 7)
> -#define COLLIE_SCP_LB_VOL_CHG SCOOP_GPCR_PA19
> -
> -#define COLLIE_SCOOP_IO_DIR (COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \
> - COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | \
> - COLLIE_SCP_LB_VOL_CHG)
> -#define COLLIE_SCOOP_IO_OUT (COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R)
> -
> -/* GPIOs for gpiolib */
> -
> -#define COLLIE_GPIO_ON_KEY (0)
> -#define COLLIE_GPIO_AC_IN (1)
> -#define COLLIE_GPIO_SDIO_INT (11)
> -#define COLLIE_GPIO_CF_IRQ (14)
> -#define COLLIE_GPIO_nREMOCON_INT (15)
> -#define COLLIE_GPIO_UCB1x00_RESET (16)
> -#define COLLIE_GPIO_nMIC_ON (17)
> -#define COLLIE_GPIO_nREMOCON_ON (18)
> -#define COLLIE_GPIO_CO (20)
> -#define COLLIE_GPIO_MCP_CLK (21)
> -#define COLLIE_GPIO_CF_CD (22)
> -#define COLLIE_GPIO_UCB1x00_IRQ (23)
> -#define COLLIE_GPIO_WAKEUP (24)
> -#define COLLIE_GPIO_GA_INT (25)
> -#define COLLIE_GPIO_MAIN_BAT_LOW (26)
> -
> -/* GPIO definitions for direct register access */
> -
> -#define _COLLIE_GPIO_ON_KEY GPIO_GPIO(0)
> -#define _COLLIE_GPIO_AC_IN GPIO_GPIO(1)
> -#define _COLLIE_GPIO_nREMOCON_INT GPIO_GPIO(15)
> -#define _COLLIE_GPIO_UCB1x00_RESET GPIO_GPIO(16)
> -#define _COLLIE_GPIO_nMIC_ON GPIO_GPIO(17)
> -#define _COLLIE_GPIO_nREMOCON_ON GPIO_GPIO(18)
> -#define _COLLIE_GPIO_CO GPIO_GPIO(20)
> -#define _COLLIE_GPIO_WAKEUP GPIO_GPIO(24)
> -/* Interrupts */
> -
> -#define COLLIE_IRQ_GPIO_ON_KEY IRQ_GPIO0
> -#define COLLIE_IRQ_GPIO_AC_IN IRQ_GPIO1
> -#define COLLIE_IRQ_GPIO_SDIO_IRQ IRQ_GPIO11
> -#define COLLIE_IRQ_GPIO_CF_IRQ IRQ_GPIO14
> -#define COLLIE_IRQ_GPIO_nREMOCON_INT IRQ_GPIO15
> -#define COLLIE_IRQ_GPIO_CO IRQ_GPIO20
> -#define COLLIE_IRQ_GPIO_CF_CD IRQ_GPIO22
> -#define COLLIE_IRQ_GPIO_UCB1x00_IRQ IRQ_GPIO23
> -#define COLLIE_IRQ_GPIO_WAKEUP IRQ_GPIO24
> -#define COLLIE_IRQ_GPIO_GA_INT IRQ_GPIO25
> -#define COLLIE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO26
> -
> -/* GPIO's on the TC35143AF (Toshiba Analog Frontend) */
> -#define COLLIE_TC35143_GPIO_BASE (GPIO_MAX + 13)
> -#define COLLIE_TC35143_GPIO_VERSION0 UCB_IO_0
> -#define COLLIE_TC35143_GPIO_TBL_CHK UCB_IO_1
> -#define COLLIE_TC35143_GPIO_VPEN_ON UCB_IO_2
> -#define COLLIE_GPIO_IR_ON (COLLIE_TC35143_GPIO_BASE + 3)
> -#define COLLIE_TC35143_GPIO_AMP_ON UCB_IO_4
> -#define COLLIE_TC35143_GPIO_VERSION1 UCB_IO_5
> -#define COLLIE_TC35143_GPIO_FS8KLPF UCB_IO_5
> -#define COLLIE_TC35143_GPIO_BUZZER_BIAS UCB_IO_6
> -#define COLLIE_GPIO_MBAT_ON (COLLIE_TC35143_GPIO_BASE + 7)
> -#define COLLIE_GPIO_BBAT_ON (COLLIE_TC35143_GPIO_BASE + 8)
> -#define COLLIE_GPIO_TMP_ON (COLLIE_TC35143_GPIO_BASE + 9)
> -#define COLLIE_TC35143_GPIO_IN (UCB_IO_0 | UCB_IO_2 | UCB_IO_5)
> -#define COLLIE_TC35143_GPIO_OUT (UCB_IO_1 | UCB_IO_3 | UCB_IO_4 \
> - | UCB_IO_6)
> -
> -#endif
> diff --git a/arch/arm/mach-sa1100/include/mach/generic.h b/arch/arm/mach-sa1100/include/mach/generic.h
> deleted file mode 100644
> index 665542e0c9e2..000000000000
> --- a/arch/arm/mach-sa1100/include/mach/generic.h
> +++ /dev/null
> @@ -1 +0,0 @@
> -#include "../../generic.h"
> diff --git a/arch/arm/mach-sa1100/include/mach/h3xxx.h b/arch/arm/mach-sa1100/include/mach/h3xxx.h
> deleted file mode 100644
> index 0ee2578e0006..000000000000
> --- a/arch/arm/mach-sa1100/include/mach/h3xxx.h
> +++ /dev/null
> @@ -1,81 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * Definitions for Compaq iPAQ H3100 and H3600 handheld computers
> - *
> - * (c) 2000 Compaq Computer Corporation. (Author: Jamey Hicks)
> - * (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru>
> - */
> -
> -#ifndef _INCLUDE_H3XXX_H_
> -#define _INCLUDE_H3XXX_H_
> -
> -#include "hardware.h" /* Gives GPIO_MAX */
> -
> -/* Physical memory regions corresponding to chip selects */
> -#define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000)
> -#define H3600_BANK_2_PHYS SA1100_CS2_PHYS
> -#define H3600_BANK_4_PHYS SA1100_CS4_PHYS
> -
> -/* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */
> -#define H3600_EGPIO_VIRT 0xf0000000
> -#define H3600_BANK_2_VIRT 0xf1000000
> -#define H3600_BANK_4_VIRT 0xf3800000
> -
> -/*
> - * gpiolib numbers for all iPAQs
> - */
> -#define H3XXX_GPIO_PWR_BUTTON 0
> -#define H3XXX_GPIO_PCMCIA_CD1 10
> -#define H3XXX_GPIO_PCMCIA_IRQ1 11
> -#define H3XXX_GPIO_PCMCIA_CD0 17
> -#define H3XXX_GPIO_ACTION_BUTTON 18
> -#define H3XXX_GPIO_SYS_CLK 19
> -#define H3XXX_GPIO_PCMCIA_IRQ0 21
> -#define H3XXX_GPIO_COM_DCD 23
> -#define H3XXX_GPIO_OPTION 24
> -#define H3XXX_GPIO_COM_CTS 25
> -#define H3XXX_GPIO_COM_RTS 26
> -
> -/* machine-specific gpios */
> -
> -#define H3100_GPIO_BT_ON 2
> -#define H3100_GPIO_QMUTE 4
> -#define H3100_GPIO_LCD_3V_ON 5
> -#define H3100_GPIO_AUD_ON 6
> -#define H3100_GPIO_AUD_PWR_ON 7
> -#define H3100_GPIO_IR_ON 8
> -#define H3100_GPIO_IR_FSEL 9
> -
> -#define H3600_GPIO_CLK_SET0 12 /* audio sample rate clock generator */
> -#define H3600_GPIO_CLK_SET1 13
> -#define H3600_GPIO_SOFT_RESET 20 /* also known as BATT_FAULT */
> -#define H3600_GPIO_OPT_LOCK 22
> -#define H3600_GPIO_OPT_DET 27
> -
> -
> -/* H3100 / 3600 EGPIO pins */
> -#define H3XXX_EGPIO_BASE (GPIO_MAX + 1)
> -
> -#define H3XXX_EGPIO_VPP_ON (H3XXX_EGPIO_BASE + 0)
> -#define H3XXX_EGPIO_CARD_RESET (H3XXX_EGPIO_BASE + 1) /* reset the attached pcmcia/compactflash card. active high. */
> -#define H3XXX_EGPIO_OPT_RESET (H3XXX_EGPIO_BASE + 2) /* reset the attached option pack. active high. */
> -#define H3XXX_EGPIO_CODEC_NRESET (H3XXX_EGPIO_BASE + 3) /* reset the onboard UDA1341. active low. */
> -#define H3XXX_EGPIO_OPT_NVRAM_ON (H3XXX_EGPIO_BASE + 4) /* apply power to optionpack nvram, active high. */
> -#define H3XXX_EGPIO_OPT_ON (H3XXX_EGPIO_BASE + 5) /* full power to option pack. active high. */
> -#define H3XXX_EGPIO_LCD_ON (H3XXX_EGPIO_BASE + 6) /* enable 3.3V to LCD. active high. */
> -#define H3XXX_EGPIO_RS232_ON (H3XXX_EGPIO_BASE + 7) /* UART3 transceiver force on. Active high. */
> -
> -/* H3600 only EGPIO pins */
> -#define H3600_EGPIO_LCD_PCI (H3XXX_EGPIO_BASE + 8) /* LCD control IC enable. active high. */
> -#define H3600_EGPIO_IR_ON (H3XXX_EGPIO_BASE + 9) /* apply power to IR module. active high. */
> -#define H3600_EGPIO_AUD_AMP_ON (H3XXX_EGPIO_BASE + 10) /* apply power to audio power amp. active high. */
> -#define H3600_EGPIO_AUD_PWR_ON (H3XXX_EGPIO_BASE + 11) /* apply power to reset of audio circuit. active high. */
> -#define H3600_EGPIO_QMUTE (H3XXX_EGPIO_BASE + 12) /* mute control for onboard UDA1341. active high. */
> -#define H3600_EGPIO_IR_FSEL (H3XXX_EGPIO_BASE + 13) /* IR speed select: 1->fast, 0->slow */
> -#define H3600_EGPIO_LCD_5V_ON (H3XXX_EGPIO_BASE + 14) /* enable 5V to LCD. active high. */
> -#define H3600_EGPIO_LVDD_ON (H3XXX_EGPIO_BASE + 15) /* enable 9V and -6.5V to LCD. */
> -
> -void __init h3xxx_map_io(void);
> -void __init h3xxx_mach_init(void);
> -
> -#endif /* _INCLUDE_H3XXX_H_ */
> diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
> deleted file mode 100644
> index 6f2dbdc28663..000000000000
> --- a/arch/arm/mach-sa1100/include/mach/hardware.h
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * arch/arm/mach-sa1100/include/mach/hardware.h
> - *
> - * Copyright (C) 1998 Nicolas Pitre <nico@fluxnic.net>
> - *
> - * This file contains the hardware definitions for SA1100 architecture
> - *
> - * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
> - * Definitions for SA1111 added.
> - */
> -
> -#ifndef __ASM_ARCH_HARDWARE_H
> -#define __ASM_ARCH_HARDWARE_H
> -
> -
> -#define UNCACHEABLE_ADDR 0xfa050000 /* ICIP */
> -
> -
> -/*
> - * SA1100 internal I/O mappings
> - *
> - * We have the following mapping:
> - * phys virt
> - * 80000000 f8000000
> - * 90000000 fa000000
> - * a0000000 fc000000
> - * b0000000 fe000000
> - */
> -
> -#define VIO_BASE 0xf8000000 /* virtual start of IO space */
> -#define VIO_SHIFT 3 /* x = IO space shrink power */
> -#define PIO_START 0x80000000 /* physical start of IO space */
> -
> -#define io_p2v( x ) \
> - IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
> -#define io_v2p( x ) \
> - ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
> -
> -#define __MREG(x) IOMEM(io_p2v(x))
> -
> -#ifndef __ASSEMBLY__
> -
> -# define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x)))
> -# define __PREG(x) (io_v2p((unsigned long)&(x)))
> -
> -#else
> -
> -# define __REG(x) io_p2v(x)
> -# define __PREG(x) io_v2p(x)
> -
> -#endif
> -
> -#include "SA-1100.h"
> -
> -#endif /* _ASM_ARCH_HARDWARE_H */
> diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h
> deleted file mode 100644
> index f4a41e665262..000000000000
> --- a/arch/arm/mach-sa1100/include/mach/irqs.h
> +++ /dev/null
> @@ -1,101 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * arch/arm/mach-sa1100/include/mach/irqs.h
> - *
> - * Copyright (C) 1996 Russell King
> - * Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus).
> - * Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation)
> - *
> - * 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs.
> - */
> -
> -#define IRQ_GPIO0_SC 1
> -#define IRQ_GPIO1_SC 2
> -#define IRQ_GPIO2_SC 3
> -#define IRQ_GPIO3_SC 4
> -#define IRQ_GPIO4_SC 5
> -#define IRQ_GPIO5_SC 6
> -#define IRQ_GPIO6_SC 7
> -#define IRQ_GPIO7_SC 8
> -#define IRQ_GPIO8_SC 9
> -#define IRQ_GPIO9_SC 10
> -#define IRQ_GPIO10_SC 11
> -#define IRQ_GPIO11_27 12
> -#define IRQ_LCD 13 /* LCD controller */
> -#define IRQ_Ser0UDC 14 /* Ser. port 0 UDC */
> -#define IRQ_Ser1SDLC 15 /* Ser. port 1 SDLC */
> -#define IRQ_Ser1UART 16 /* Ser. port 1 UART */
> -#define IRQ_Ser2ICP 17 /* Ser. port 2 ICP */
> -#define IRQ_Ser3UART 18 /* Ser. port 3 UART */
> -#define IRQ_Ser4MCP 19 /* Ser. port 4 MCP */
> -#define IRQ_Ser4SSP 20 /* Ser. port 4 SSP */
> -#define IRQ_DMA0 21 /* DMA controller channel 0 */
> -#define IRQ_DMA1 22 /* DMA controller channel 1 */
> -#define IRQ_DMA2 23 /* DMA controller channel 2 */
> -#define IRQ_DMA3 24 /* DMA controller channel 3 */
> -#define IRQ_DMA4 25 /* DMA controller channel 4 */
> -#define IRQ_DMA5 26 /* DMA controller channel 5 */
> -#define IRQ_OST0 27 /* OS Timer match 0 */
> -#define IRQ_OST1 28 /* OS Timer match 1 */
> -#define IRQ_OST2 29 /* OS Timer match 2 */
> -#define IRQ_OST3 30 /* OS Timer match 3 */
> -#define IRQ_RTC1Hz 31 /* RTC 1 Hz clock */
> -#define IRQ_RTCAlrm 32 /* RTC Alarm */
> -
> -#define IRQ_GPIO0 33
> -#define IRQ_GPIO1 34
> -#define IRQ_GPIO2 35
> -#define IRQ_GPIO3 36
> -#define IRQ_GPIO4 37
> -#define IRQ_GPIO5 38
> -#define IRQ_GPIO6 39
> -#define IRQ_GPIO7 40
> -#define IRQ_GPIO8 41
> -#define IRQ_GPIO9 42
> -#define IRQ_GPIO10 43
> -#define IRQ_GPIO11 44
> -#define IRQ_GPIO12 45
> -#define IRQ_GPIO13 46
> -#define IRQ_GPIO14 47
> -#define IRQ_GPIO15 48
> -#define IRQ_GPIO16 49
> -#define IRQ_GPIO17 50
> -#define IRQ_GPIO18 51
> -#define IRQ_GPIO19 52
> -#define IRQ_GPIO20 53
> -#define IRQ_GPIO21 54
> -#define IRQ_GPIO22 55
> -#define IRQ_GPIO23 56
> -#define IRQ_GPIO24 57
> -#define IRQ_GPIO25 58
> -#define IRQ_GPIO26 59
> -#define IRQ_GPIO27 60
> -
> -/*
> - * The next 16 interrupts are for board specific purposes. Since
> - * the kernel can only run on one machine at a time, we can re-use
> - * these. If you need more, increase IRQ_BOARD_END, but keep it
> - * within sensible limits. IRQs 61 to 76 are available.
> - */
> -#define IRQ_BOARD_START 61
> -#define IRQ_BOARD_END 77
> -
> -/*
> - * Figure out the MAX IRQ number.
> - *
> - * Neponset, SA1111 and UCB1x00 are sparse IRQ aware, so can dynamically
> - * allocate their IRQs above NR_IRQS.
> - *
> - * LoCoMo has 4 additional IRQs, but is not sparse IRQ aware, and so has
> - * to be included in the NR_IRQS calculation.
> - */
> -#ifdef CONFIG_SHARP_LOCOMO
> -#define NR_IRQS_LOCOMO 4
> -#else
> -#define NR_IRQS_LOCOMO 0
> -#endif
> -
> -#ifndef NR_IRQS
> -#define NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO)
> -#endif
> -#define SA1100_NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO)
> diff --git a/arch/arm/mach-sa1100/include/mach/jornada720.h b/arch/arm/mach-sa1100/include/mach/jornada720.h
> deleted file mode 100644
> index bb22fcab8c6c..000000000000
> --- a/arch/arm/mach-sa1100/include/mach/jornada720.h
> +++ /dev/null
> @@ -1,28 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * arch/arm/mach-sa1100/include/mach/jornada720.h
> - *
> - * SSP/MCU communication definitions for HP Jornada 710/720/728
> - *
> - * Copyright 2007,2008 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
> - * Copyright 2000 John Ankcorn <jca@lcs.mit.edu>
> - */
> -
> - /* HP Jornada 7xx microprocessor commands */
> -#define GETBATTERYDATA 0xc0
> -#define GETSCANKEYCODE 0x90
> -#define GETTOUCHSAMPLES 0xa0
> -#define GETCONTRAST 0xD0
> -#define SETCONTRAST 0xD1
> -#define GETBRIGHTNESS 0xD2
> -#define SETBRIGHTNESS 0xD3
> -#define CONTRASTOFF 0xD8
> -#define BRIGHTNESSOFF 0xD9
> -#define PWMOFF 0xDF
> -#define TXDUMMY 0x11
> -#define ERRORCODE 0x00
> -
> -extern void jornada_ssp_start(void);
> -extern void jornada_ssp_end(void);
> -extern int jornada_ssp_inout(u8 byte);
> -extern int jornada_ssp_byte(u8 byte);
> diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h
> deleted file mode 100644
> index 3b19296f5062..000000000000
> --- a/arch/arm/mach-sa1100/include/mach/memory.h
> +++ /dev/null
> @@ -1,37 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * arch/arm/mach-sa1100/include/mach/memory.h
> - *
> - * Copyright (C) 1999-2000 Nicolas Pitre <nico@fluxnic.net>
> - */
> -
> -#ifndef __ASM_ARCH_MEMORY_H
> -#define __ASM_ARCH_MEMORY_H
> -
> -#include <linux/sizes.h>
> -
> -/*
> - * Because of the wide memory address space between physical RAM banks on the
> - * SA1100, it's much convenient to use Linux's SparseMEM support to implement
> - * our memory map representation. Assuming all memory nodes have equal access
> - * characteristics, we then have generic discontiguous memory support.
> - *
> - * The sparsemem banks are matched with the physical memory bank addresses
> - * which are incidentally the same as virtual addresses.
> - *
> - * node 0: 0xc0000000 - 0xc7ffffff
> - * node 1: 0xc8000000 - 0xcfffffff
> - * node 2: 0xd0000000 - 0xd7ffffff
> - * node 3: 0xd8000000 - 0xdfffffff
> - */
> -#define MAX_PHYSMEM_BITS 32
> -#define SECTION_SIZE_BITS 27
> -
> -/*
> - * Cache flushing area - SA1100 zero bank
> - */
> -#define FLUSH_BASE_PHYS 0xe0000000
> -#define FLUSH_BASE 0xf5000000
> -#define FLUSH_BASE_MINICACHE 0xf5100000
> -
> -#endif
> diff --git a/arch/arm/mach-sa1100/include/mach/mtd-xip.h b/arch/arm/mach-sa1100/include/mach/mtd-xip.h
> deleted file mode 100644
> index 85e6a79112d2..000000000000
> --- a/arch/arm/mach-sa1100/include/mach/mtd-xip.h
> +++ /dev/null
> @@ -1,23 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * MTD primitives for XIP support. Architecture specific functions
> - *
> - * Do not include this file directly. It's included from linux/mtd/xip.h
> - *
> - * Author: Nicolas Pitre
> - * Created: Nov 2, 2004
> - * Copyright: (C) 2004 MontaVista Software, Inc.
> - */
> -
> -#ifndef __ARCH_SA1100_MTD_XIP_H__
> -#define __ARCH_SA1100_MTD_XIP_H__
> -
> -#include <mach/hardware.h>
> -
> -#define xip_irqpending() (ICIP & ICMR)
> -
> -/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
> -#define xip_currtime() readl_relaxed(OSCR)
> -#define xip_elapsed_since(x) (signed)((readl_relaxed(OSCR) - (x)) / 4)
> -
> -#endif /* __ARCH_SA1100_MTD_XIP_H__ */
> diff --git a/arch/arm/mach-sa1100/include/mach/neponset.h b/arch/arm/mach-sa1100/include/mach/neponset.h
> deleted file mode 100644
> index 18411cfdfe8e..000000000000
> --- a/arch/arm/mach-sa1100/include/mach/neponset.h
> +++ /dev/null
> @@ -1,31 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * arch/arm/mach-sa1100/include/mach/neponset.h
> - *
> - * Created 2000/06/05 by Nicolas Pitre <nico@fluxnic.net>
> - *
> - * This file contains the hardware specific definitions for Assabet
> - * Only include this file from SA1100-specific files.
> - *
> - * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
> - * Definitions for Neponset added.
> - */
> -#ifndef __ASM_ARCH_NEPONSET_H
> -#define __ASM_ARCH_NEPONSET_H
> -
> -/*
> - * Neponset definitions:
> - */
> -#define NCR_GP01_OFF (1<<0)
> -#define NCR_TP_PWR_EN (1<<1)
> -#define NCR_MS_PWR_EN (1<<2)
> -#define NCR_ENET_OSC_EN (1<<3)
> -#define NCR_SPI_KB_WK_UP (1<<4)
> -#define NCR_A0VPP (1<<5)
> -#define NCR_A1VPP (1<<6)
> -
> -void neponset_ncr_frob(unsigned int, unsigned int);
> -#define neponset_ncr_set(v) neponset_ncr_frob(0, v)
> -#define neponset_ncr_clear(v) neponset_ncr_frob(v, 0)
> -
> -#endif
> diff --git a/arch/arm/mach-sa1100/include/mach/reset.h b/arch/arm/mach-sa1100/include/mach/reset.h
> deleted file mode 100644
> index a6723d45ae2a..000000000000
> --- a/arch/arm/mach-sa1100/include/mach/reset.h
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -#ifndef __ASM_ARCH_RESET_H
> -#define __ASM_ARCH_RESET_H
> -
> -#include "hardware.h"
> -
> -#define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */
> -#define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */
> -#define RESET_STATUS_LOWPOWER (1 << 2) /* Exit from Low Power/Sleep */
> -#define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */
> -#define RESET_STATUS_ALL (0xf)
> -
> -static inline void clear_reset_status(unsigned int mask)
> -{
> - RCSR = mask;
> -}
> -
> -#endif /* __ASM_ARCH_RESET_H */
> diff --git a/arch/arm/mach-sa1100/include/mach/uncompress.h b/arch/arm/mach-sa1100/include/mach/uncompress.h
> deleted file mode 100644
> index f5eaa90a4576..000000000000
> --- a/arch/arm/mach-sa1100/include/mach/uncompress.h
> +++ /dev/null
> @@ -1,52 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * arch/arm/mach-sa1100/include/mach/uncompress.h
> - *
> - * (C) 1999 Nicolas Pitre <nico@fluxnic.net>
> - *
> - * Reorganised to be machine independent.
> - */
> -
> -#include "hardware.h"
> -
> -#define IOMEM(x) (x)
> -
> -/*
> - * The following code assumes the serial port has already been
> - * initialized by the bootloader. We search for the first enabled
> - * port in the most probable order. If you didn't setup a port in
> - * your bootloader then nothing will appear (which might be desired).
> - */
> -
> -#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
> -
> -static inline void putc(int c)
> -{
> - unsigned long serial_port;
> -
> - do {
> - serial_port = _Ser3UTCR0;
> - if (UART(UTCR3) & UTCR3_TXE) break;
> - serial_port = _Ser1UTCR0;
> - if (UART(UTCR3) & UTCR3_TXE) break;
> - serial_port = _Ser2UTCR0;
> - if (UART(UTCR3) & UTCR3_TXE) break;
> - return;
> - } while (0);
> -
> - /* wait for space in the UART's transmitter */
> - while (!(UART(UTSR1) & UTSR1_TNF))
> - barrier();
> -
> - /* send the character out. */
> - UART(UTDR) = c;
> -}
> -
> -static inline void flush(void)
> -{
> -}
> -
> -/*
> - * Nothing to do for these
> - */
> -#define arch_decomp_setup()
> diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
> deleted file mode 100644
> index e259298d9465..000000000000
> --- a/arch/arm/mach-sa1100/jornada720.c
> +++ /dev/null
> @@ -1,380 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * linux/arch/arm/mach-sa1100/jornada720.c
> - *
> - * HP Jornada720 init code
> - *
> - * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
> - * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
> - * Copyright (C) 2005 Michael Gernoth <michael@gernoth.net>
> - */
> -
> -#include <linux/init.h>
> -#include <linux/kernel.h>
> -#include <linux/tty.h>
> -#include <linux/delay.h>
> -#include <linux/gpio/machine.h>
> -#include <linux/platform_data/sa11x0-serial.h>
> -#include <linux/platform_device.h>
> -#include <linux/ioport.h>
> -#include <linux/mtd/mtd.h>
> -#include <linux/mtd/partitions.h>
> -#include <video/s1d13xxxfb.h>
> -
> -#include <asm/hardware/sa1111.h>
> -#include <asm/page.h>
> -#include <asm/mach-types.h>
> -#include <asm/setup.h>
> -#include <asm/mach/arch.h>
> -#include <asm/mach/flash.h>
> -#include <asm/mach/map.h>
> -
> -#include <mach/hardware.h>
> -#include <mach/irqs.h>
> -
> -#include "generic.h"
> -
> -/*
> - * HP Documentation referred in this file:
> - * http://www.jlime.com/downloads/development/docs/jornada7xx/jornada720.txt
> - */
> -
> -/* line 110 of HP's doc */
> -#define TUCR_VAL 0x20000400
> -
> -/* memory space (line 52 of HP's doc) */
> -#define SA1111REGSTART 0x40000000
> -#define SA1111REGLEN 0x00002000
> -#define EPSONREGSTART 0x48000000
> -#define EPSONREGLEN 0x00100000
> -#define EPSONFBSTART 0x48200000
> -/* 512kB framebuffer */
> -#define EPSONFBLEN 512*1024
> -
> -static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
> - /* line 344 of HP's doc */
> - {0x0001,0x00}, // Miscellaneous Register
> - {0x01FC,0x00}, // Display Mode Register
> - {0x0004,0x00}, // General IO Pins Configuration Register 0
> - {0x0005,0x00}, // General IO Pins Configuration Register 1
> - {0x0008,0x00}, // General IO Pins Control Register 0
> - {0x0009,0x00}, // General IO Pins Control Register 1
> - {0x0010,0x01}, // Memory Clock Configuration Register
> - {0x0014,0x11}, // LCD Pixel Clock Configuration Register
> - {0x0018,0x01}, // CRT/TV Pixel Clock Configuration Register
> - {0x001C,0x01}, // MediaPlug Clock Configuration Register
> - {0x001E,0x01}, // CPU To Memory Wait State Select Register
> - {0x0020,0x00}, // Memory Configuration Register
> - {0x0021,0x45}, // DRAM Refresh Rate Register
> - {0x002A,0x01}, // DRAM Timings Control Register 0
> - {0x002B,0x03}, // DRAM Timings Control Register 1
> - {0x0030,0x1c}, // Panel Type Register
> - {0x0031,0x00}, // MOD Rate Register
> - {0x0032,0x4F}, // LCD Horizontal Display Width Register
> - {0x0034,0x07}, // LCD Horizontal Non-Display Period Register
> - {0x0035,0x01}, // TFT FPLINE Start Position Register
> - {0x0036,0x0B}, // TFT FPLINE Pulse Width Register
> - {0x0038,0xEF}, // LCD Vertical Display Height Register 0
> - {0x0039,0x00}, // LCD Vertical Display Height Register 1
> - {0x003A,0x13}, // LCD Vertical Non-Display Period Register
> - {0x003B,0x0B}, // TFT FPFRAME Start Position Register
> - {0x003C,0x01}, // TFT FPFRAME Pulse Width Register
> - {0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
> - {0x0041,0x00}, // LCD Miscellaneous Register
> - {0x0042,0x00}, // LCD Display Start Address Register 0
> - {0x0043,0x00}, // LCD Display Start Address Register 1
> - {0x0044,0x00}, // LCD Display Start Address Register 2
> - {0x0046,0x80}, // LCD Memory Address Offset Register 0
> - {0x0047,0x02}, // LCD Memory Address Offset Register 1
> - {0x0048,0x00}, // LCD Pixel Panning Register
> - {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
> - {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
> - {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
> - {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
> - {0x0053,0x01}, // CRT/TV HRTC Start Position Register
> - {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
> - {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
> - {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
> - {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
> - {0x0059,0x09}, // CRT/TV VRTC Start Position Register
> - {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
> - {0x005B,0x10}, // TV Output Control Register
> - {0x0060,0x03}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
> - {0x0062,0x00}, // CRT/TV Display Start Address Register 0
> - {0x0063,0x00}, // CRT/TV Display Start Address Register 1
> - {0x0064,0x00}, // CRT/TV Display Start Address Register 2
> - {0x0066,0x40}, // CRT/TV Memory Address Offset Register 0
> - {0x0067,0x01}, // CRT/TV Memory Address Offset Register 1
> - {0x0068,0x00}, // CRT/TV Pixel Panning Register
> - {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
> - {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
> - {0x0070,0x00}, // LCD Ink/Cursor Control Register
> - {0x0071,0x01}, // LCD Ink/Cursor Start Address Register
> - {0x0072,0x00}, // LCD Cursor X Position Register 0
> - {0x0073,0x00}, // LCD Cursor X Position Register 1
> - {0x0074,0x00}, // LCD Cursor Y Position Register 0
> - {0x0075,0x00}, // LCD Cursor Y Position Register 1
> - {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
> - {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
> - {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
> - {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
> - {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
> - {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
> - {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
> - {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
> - {0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register
> - {0x0082,0x00}, // CRT/TV Cursor X Position Register 0
> - {0x0083,0x00}, // CRT/TV Cursor X Position Register 1
> - {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
> - {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
> - {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
> - {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
> - {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
> - {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
> - {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
> - {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
> - {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
> - {0x0100,0x00}, // BitBlt Control Register 0
> - {0x0101,0x00}, // BitBlt Control Register 1
> - {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
> - {0x0103,0x00}, // BitBlt Operation Register
> - {0x0104,0x00}, // BitBlt Source Start Address Register 0
> - {0x0105,0x00}, // BitBlt Source Start Address Register 1
> - {0x0106,0x00}, // BitBlt Source Start Address Register 2
> - {0x0108,0x00}, // BitBlt Destination Start Address Register 0
> - {0x0109,0x00}, // BitBlt Destination Start Address Register 1
> - {0x010A,0x00}, // BitBlt Destination Start Address Register 2
> - {0x010C,0x00}, // BitBlt Memory Address Offset Register 0
> - {0x010D,0x00}, // BitBlt Memory Address Offset Register 1
> - {0x0110,0x00}, // BitBlt Width Register 0
> - {0x0111,0x00}, // BitBlt Width Register 1
> - {0x0112,0x00}, // BitBlt Height Register 0
> - {0x0113,0x00}, // BitBlt Height Register 1
> - {0x0114,0x00}, // BitBlt Background Color Register 0
> - {0x0115,0x00}, // BitBlt Background Color Register 1
> - {0x0118,0x00}, // BitBlt Foreground Color Register 0
> - {0x0119,0x00}, // BitBlt Foreground Color Register 1
> - {0x01E0,0x00}, // Look-Up Table Mode Register
> - {0x01E2,0x00}, // Look-Up Table Address Register
> - /* not sure, wouldn't like to mess with the driver */
> - {0x01E4,0x00}, // Look-Up Table Data Register
> - /* jornada doc says 0x00, but I trust the driver */
> - {0x01F0,0x10}, // Power Save Configuration Register
> - {0x01F1,0x00}, // Power Save Status Register
> - {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
> - {0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
> -};
> -
> -static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
> - .initregs = s1d13xxxfb_initregs,
> - .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
> - .platform_init_video = NULL
> -};
> -
> -static struct resource s1d13xxxfb_resources[] = {
> - [0] = DEFINE_RES_MEM(EPSONFBSTART, EPSONFBLEN),
> - [1] = DEFINE_RES_MEM(EPSONREGSTART, EPSONREGLEN),
> -};
> -
> -static struct platform_device s1d13xxxfb_device = {
> - .name = S1D_DEVICENAME,
> - .id = 0,
> - .dev = {
> - .platform_data = &s1d13xxxfb_data,
> - },
> - .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
> - .resource = s1d13xxxfb_resources,
> -};
> -
> -static struct gpiod_lookup_table jornada_pcmcia_gpiod_table = {
> - .dev_id = "1800",
> - .table = {
> - GPIO_LOOKUP("sa1111", 0, "s0-power", GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP("sa1111", 1, "s1-power", GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP("sa1111", 2, "s0-3v", GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP("sa1111", 3, "s1-3v", GPIO_ACTIVE_HIGH),
> - { },
> - },
> -};
> -
> -static struct resource sa1111_resources[] = {
> - [0] = DEFINE_RES_MEM(SA1111REGSTART, SA1111REGLEN),
> - [1] = DEFINE_RES_IRQ(IRQ_GPIO1),
> -};
> -
> -static struct sa1111_platform_data sa1111_info = {
> - .disable_devs = SA1111_DEVID_PS2_MSE,
> -};
> -
> -static u64 sa1111_dmamask = 0xffffffffUL;
> -
> -static struct platform_device sa1111_device = {
> - .name = "sa1111",
> - .id = 0,
> - .dev = {
> - .dma_mask = &sa1111_dmamask,
> - .coherent_dma_mask = 0xffffffff,
> - .platform_data = &sa1111_info,
> - },
> - .num_resources = ARRAY_SIZE(sa1111_resources),
> - .resource = sa1111_resources,
> -};
> -
> -static struct platform_device jornada_ssp_device = {
> - .name = "jornada_ssp",
> - .id = -1,
> -};
> -
> -static struct resource jornada_kbd_resources[] = {
> - DEFINE_RES_IRQ(IRQ_GPIO0),
> -};
> -
> -static struct platform_device jornada_kbd_device = {
> - .name = "jornada720_kbd",
> - .id = -1,
> - .num_resources = ARRAY_SIZE(jornada_kbd_resources),
> - .resource = jornada_kbd_resources,
> -};
> -
> -static struct gpiod_lookup_table jornada_ts_gpiod_table = {
> - .dev_id = "jornada_ts",
> - .table = {
> - GPIO_LOOKUP("gpio", 9, "penup", GPIO_ACTIVE_HIGH),
> - },
> -};
> -
> -static struct platform_device jornada_ts_device = {
> - .name = "jornada_ts",
> - .id = -1,
> -};
> -
> -static struct platform_device *devices[] __initdata = {
> - &sa1111_device,
> - &jornada_ssp_device,
> - &s1d13xxxfb_device,
> - &jornada_kbd_device,
> - &jornada_ts_device,
> -};
> -
> -static int __init jornada720_init(void)
> -{
> - int ret = -ENODEV;
> -
> - if (machine_is_jornada720()) {
> - /* we want to use gpio20 as input to drive the clock of our uart 3 */
> - GPDR |= GPIO_GPIO20; /* Clear gpio20 pin as input */
> - TUCR = TUCR_VAL;
> - GPSR = GPIO_GPIO20; /* start gpio20 pin */
> - udelay(1);
> - GPCR = GPIO_GPIO20; /* stop gpio20 */
> - udelay(1);
> - GPSR = GPIO_GPIO20; /* restart gpio20 */
> - udelay(20); /* give it some time to restart */
> -
> - gpiod_add_lookup_table(&jornada_ts_gpiod_table);
> - gpiod_add_lookup_table(&jornada_pcmcia_gpiod_table);
> -
> - ret = platform_add_devices(devices, ARRAY_SIZE(devices));
> - }
> -
> - return ret;
> -}
> -
> -arch_initcall(jornada720_init);
> -
> -static struct map_desc jornada720_io_desc[] __initdata = {
> - { /* Epson registers */
> - .virtual = 0xf0000000,
> - .pfn = __phys_to_pfn(EPSONREGSTART),
> - .length = EPSONREGLEN,
> - .type = MT_DEVICE
> - }, { /* Epson frame buffer */
> - .virtual = 0xf1000000,
> - .pfn = __phys_to_pfn(EPSONFBSTART),
> - .length = EPSONFBLEN,
> - .type = MT_DEVICE
> - }
> -};
> -
> -static void __init jornada720_map_io(void)
> -{
> - sa1100_map_io();
> - iotable_init(jornada720_io_desc, ARRAY_SIZE(jornada720_io_desc));
> -
> - sa1100_register_uart(0, 3);
> - sa1100_register_uart(1, 1);
> -}
> -
> -static struct mtd_partition jornada720_partitions[] = {
> - {
> - .name = "JORNADA720 boot firmware",
> - .size = 0x00040000,
> - .offset = 0,
> - .mask_flags = MTD_WRITEABLE, /* force read-only */
> - }, {
> - .name = "JORNADA720 kernel",
> - .size = 0x000c0000,
> - .offset = 0x00040000,
> - }, {
> - .name = "JORNADA720 params",
> - .size = 0x00040000,
> - .offset = 0x00100000,
> - }, {
> - .name = "JORNADA720 initrd",
> - .size = 0x00100000,
> - .offset = 0x00140000,
> - }, {
> - .name = "JORNADA720 root cramfs",
> - .size = 0x00300000,
> - .offset = 0x00240000,
> - }, {
> - .name = "JORNADA720 usr cramfs",
> - .size = 0x00800000,
> - .offset = 0x00540000,
> - }, {
> - .name = "JORNADA720 usr local",
> - .size = 0, /* will expand to the end of the flash */
> - .offset = 0x00d00000,
> - }
> -};
> -
> -static void jornada720_set_vpp(int vpp)
> -{
> - if (vpp)
> - /* enabling flash write (line 470 of HP's doc) */
> - PPSR |= PPC_LDD7;
> - else
> - /* disabling flash write (line 470 of HP's doc) */
> - PPSR &= ~PPC_LDD7;
> - PPDR |= PPC_LDD7;
> -}
> -
> -static struct flash_platform_data jornada720_flash_data = {
> - .map_name = "cfi_probe",
> - .set_vpp = jornada720_set_vpp,
> - .parts = jornada720_partitions,
> - .nr_parts = ARRAY_SIZE(jornada720_partitions),
> -};
> -
> -static struct resource jornada720_flash_resource =
> - DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
> -
> -static void __init jornada720_mach_init(void)
> -{
> - sa11x0_register_mtd(&jornada720_flash_data, &jornada720_flash_resource, 1);
> -}
> -
> -MACHINE_START(JORNADA720, "HP Jornada 720")
> - /* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */
> - .atag_offset = 0x100,
> - .map_io = jornada720_map_io,
> - .nr_irqs = SA1100_NR_IRQS,
> - .init_irq = sa1100_init_irq,
> - .init_time = sa1100_timer_init,
> - .init_machine = jornada720_mach_init,
> - .init_late = sa11x0_init_late,
> -#ifdef CONFIG_SA1111
> - .dma_zone_size = SZ_1M,
> -#endif
> - .restart = sa11x0_restart,
> -MACHINE_END
> diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
> deleted file mode 100644
> index d94810217095..000000000000
> --- a/arch/arm/mach-sa1100/jornada720_ssp.c
> +++ /dev/null
> @@ -1,202 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * arch/arm/mac-sa1100/jornada720_ssp.c
> - *
> - * Copyright (C) 2006/2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
> - * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
> - *
> - * SSP driver for the HP Jornada 710/720/728
> - */
> -
> -#include <linux/delay.h>
> -#include <linux/errno.h>
> -#include <linux/init.h>
> -#include <linux/kernel.h>
> -#include <linux/module.h>
> -#include <linux/platform_device.h>
> -#include <linux/sched.h>
> -#include <linux/io.h>
> -
> -#include <mach/hardware.h>
> -#include <mach/jornada720.h>
> -#include <asm/hardware/ssp.h>
> -
> -static DEFINE_SPINLOCK(jornada_ssp_lock);
> -static unsigned long jornada_ssp_flags;
> -
> -/**
> - * jornada_ssp_reverse - reverses input byte
> - * @byte: input byte to reverse
> - *
> - * we need to reverse all data we receive from the mcu due to its physical location
> - * returns : 01110111 -> 11101110
> - */
> -inline u8 jornada_ssp_reverse(u8 byte)
> -{
> - return
> - ((0x80 & byte) >> 7) |
> - ((0x40 & byte) >> 5) |
> - ((0x20 & byte) >> 3) |
> - ((0x10 & byte) >> 1) |
> - ((0x08 & byte) << 1) |
> - ((0x04 & byte) << 3) |
> - ((0x02 & byte) << 5) |
> - ((0x01 & byte) << 7);
> -};
> -EXPORT_SYMBOL(jornada_ssp_reverse);
> -
> -/**
> - * jornada_ssp_byte - waits for ready ssp bus and sends byte
> - * @byte: input byte to transmit
> - *
> - * waits for fifo buffer to clear and then transmits, if it doesn't then we will
> - * timeout after <timeout> rounds. Needs mcu running before its called.
> - *
> - * returns : %mcu output on success
> - * : %-ETIMEDOUT on timeout
> - */
> -int jornada_ssp_byte(u8 byte)
> -{
> - int timeout = 400000;
> - u16 ret;
> -
> - while ((GPLR & GPIO_GPIO10)) {
> - if (!--timeout) {
> - printk(KERN_WARNING "SSP: timeout while waiting for transmit\n");
> - return -ETIMEDOUT;
> - }
> - cpu_relax();
> - }
> -
> - ret = jornada_ssp_reverse(byte) << 8;
> -
> - ssp_write_word(ret);
> - ssp_read_word(&ret);
> -
> - return jornada_ssp_reverse(ret);
> -};
> -EXPORT_SYMBOL(jornada_ssp_byte);
> -
> -/**
> - * jornada_ssp_inout - decide if input is command or trading byte
> - * @byte: input byte to send (may be %TXDUMMY)
> - *
> - * returns : (jornada_ssp_byte(byte)) on success
> - * : %-ETIMEDOUT on timeout failure
> - */
> -int jornada_ssp_inout(u8 byte)
> -{
> - int ret, i;
> -
> - /* true means command byte */
> - if (byte != TXDUMMY) {
> - ret = jornada_ssp_byte(byte);
> - /* Proper return to commands is TxDummy */
> - if (ret != TXDUMMY) {
> - for (i = 0; i < 256; i++)/* flushing bus */
> - if (jornada_ssp_byte(TXDUMMY) == -1)
> - break;
> - return -ETIMEDOUT;
> - }
> - } else /* Exchange TxDummy for data */
> - ret = jornada_ssp_byte(TXDUMMY);
> -
> - return ret;
> -};
> -EXPORT_SYMBOL(jornada_ssp_inout);
> -
> -/**
> - * jornada_ssp_start - enable mcu
> - *
> - */
> -void jornada_ssp_start(void)
> -{
> - spin_lock_irqsave(&jornada_ssp_lock, jornada_ssp_flags);
> - GPCR = GPIO_GPIO25;
> - udelay(50);
> - return;
> -};
> -EXPORT_SYMBOL(jornada_ssp_start);
> -
> -/**
> - * jornada_ssp_end - disable mcu and turn off lock
> - *
> - */
> -void jornada_ssp_end(void)
> -{
> - GPSR = GPIO_GPIO25;
> - spin_unlock_irqrestore(&jornada_ssp_lock, jornada_ssp_flags);
> - return;
> -};
> -EXPORT_SYMBOL(jornada_ssp_end);
> -
> -static int jornada_ssp_probe(struct platform_device *dev)
> -{
> - int ret;
> -
> - GPSR = GPIO_GPIO25;
> -
> - ret = ssp_init();
> -
> - /* worked fine, lets not bother with anything else */
> - if (!ret) {
> - printk(KERN_INFO "SSP: device initialized with irq\n");
> - return ret;
> - }
> -
> - printk(KERN_WARNING "SSP: initialization failed, trying non-irq solution \n");
> -
> - /* init of Serial 4 port */
> - Ser4MCCR0 = 0;
> - Ser4SSCR0 = 0x0387;
> - Ser4SSCR1 = 0x18;
> -
> - /* clear out any left over data */
> - ssp_flush();
> -
> - /* enable MCU */
> - jornada_ssp_start();
> -
> - /* see if return value makes sense */
> - ret = jornada_ssp_inout(GETBRIGHTNESS);
> -
> - /* seems like it worked, just feed it with TxDummy to get rid of data */
> - if (ret == TXDUMMY)
> - jornada_ssp_inout(TXDUMMY);
> -
> - jornada_ssp_end();
> -
> - /* failed, lets just kill everything */
> - if (ret == -ETIMEDOUT) {
> - printk(KERN_WARNING "SSP: attempts failed, bailing\n");
> - ssp_exit();
> - return -ENODEV;
> - }
> -
> - /* all fine */
> - printk(KERN_INFO "SSP: device initialized\n");
> - return 0;
> -};
> -
> -static void jornada_ssp_remove(struct platform_device *dev)
> -{
> - /* Note that this doesn't actually remove the driver, since theres nothing to remove
> - * It just makes sure everything is turned off */
> - GPSR = GPIO_GPIO25;
> - ssp_exit();
> -};
> -
> -struct platform_driver jornadassp_driver = {
> - .probe = jornada_ssp_probe,
> - .remove = jornada_ssp_remove,
> - .driver = {
> - .name = "jornada_ssp",
> - },
> -};
> -
> -static int __init jornada_ssp_init(void)
> -{
> - return platform_driver_register(&jornadassp_driver);
> -}
> -
> -module_init(jornada_ssp_init);
> diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
> deleted file mode 100644
> index 9e8a3284a6cf..000000000000
> --- a/arch/arm/mach-sa1100/neponset.c
> +++ /dev/null
> @@ -1,438 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * linux/arch/arm/mach-sa1100/neponset.c
> - */
> -#include <linux/err.h>
> -#include <linux/gpio/driver.h>
> -#include <linux/gpio/gpio-reg.h>
> -#include <linux/gpio/machine.h>
> -#include <linux/init.h>
> -#include <linux/ioport.h>
> -#include <linux/irq.h>
> -#include <linux/kernel.h>
> -#include <linux/module.h>
> -#include <linux/platform_device.h>
> -#include <linux/pm.h>
> -#include <linux/serial_core.h>
> -#include <linux/slab.h>
> -#include <linux/smc91x.h>
> -
> -#include <asm/mach-types.h>
> -#include <asm/mach/map.h>
> -#include <asm/hardware/sa1111.h>
> -#include <linux/sizes.h>
> -
> -#include <mach/hardware.h>
> -#include <mach/assabet.h>
> -#include <mach/neponset.h>
> -#include <mach/irqs.h>
> -
> -#define NEP_IRQ_SMC91X 0
> -#define NEP_IRQ_USAR 1
> -#define NEP_IRQ_SA1111 2
> -#define NEP_IRQ_NR 3
> -
> -#define WHOAMI 0x00
> -#define LEDS 0x10
> -#define SWPK 0x20
> -#define IRR 0x24
> -#define KP_Y_IN 0x80
> -#define KP_X_OUT 0x90
> -#define NCR_0 0xa0
> -#define MDM_CTL_0 0xb0
> -#define MDM_CTL_1 0xb4
> -#define AUD_CTL 0xc0
> -
> -#define IRR_ETHERNET (1 << 0)
> -#define IRR_USAR (1 << 1)
> -#define IRR_SA1111 (1 << 2)
> -
> -#define NCR_NGPIO 7
> -#define MDM_CTL0_NGPIO 4
> -#define MDM_CTL1_NGPIO 6
> -#define AUD_NGPIO 2
> -
> -extern void sa1110_mb_disable(void);
> -
> -#define to_neponset_gpio_chip(x) container_of(x, struct neponset_gpio_chip, gc)
> -
> -static const char *neponset_ncr_names[] = {
> - "gp01_off", "tp_power", "ms_power", "enet_osc",
> - "spi_kb_wk_up", "a0vpp", "a1vpp"
> -};
> -
> -static const char *neponset_mdmctl0_names[] = {
> - "rts3", "dtr3", "rts1", "dtr1",
> -};
> -
> -static const char *neponset_mdmctl1_names[] = {
> - "cts3", "dsr3", "dcd3", "cts1", "dsr1", "dcd1"
> -};
> -
> -static const char *neponset_aud_names[] = {
> - "sel_1341", "mute_1341",
> -};
> -
> -struct neponset_drvdata {
> - void __iomem *base;
> - struct platform_device *sa1111;
> - struct platform_device *smc91x;
> - unsigned irq_base;
> - struct gpio_chip *gpio[4];
> -};
> -
> -static struct gpiod_lookup_table neponset_uart1_gpio_table = {
> - .dev_id = "sa11x0-uart.1",
> - .table = {
> - GPIO_LOOKUP("neponset-mdm-ctl0", 2, "rts", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("neponset-mdm-ctl0", 3, "dtr", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("neponset-mdm-ctl1", 3, "cts", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("neponset-mdm-ctl1", 4, "dsr", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("neponset-mdm-ctl1", 5, "dcd", GPIO_ACTIVE_LOW),
> - { },
> - },
> -};
> -
> -static struct gpiod_lookup_table neponset_uart3_gpio_table = {
> - .dev_id = "sa11x0-uart.3",
> - .table = {
> - GPIO_LOOKUP("neponset-mdm-ctl0", 0, "rts", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("neponset-mdm-ctl0", 1, "dtr", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("neponset-mdm-ctl1", 0, "cts", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("neponset-mdm-ctl1", 1, "dsr", GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP("neponset-mdm-ctl1", 2, "dcd", GPIO_ACTIVE_LOW),
> - { },
> - },
> -};
> -
> -static struct gpiod_lookup_table neponset_pcmcia_table = {
> - .dev_id = "1800",
> - .table = {
> - GPIO_LOOKUP("sa1111", 1, "a0vcc", GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP("sa1111", 0, "a1vcc", GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP("neponset-ncr", 5, "a0vpp", GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP("neponset-ncr", 6, "a1vpp", GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP("sa1111", 2, "b0vcc", GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP("sa1111", 3, "b1vcc", GPIO_ACTIVE_HIGH),
> - { },
> - },
> -};
> -
> -static struct neponset_drvdata *nep;
> -
> -void neponset_ncr_frob(unsigned int mask, unsigned int val)
> -{
> - struct neponset_drvdata *n = nep;
> - unsigned long m = mask, v = val;
> -
> - if (nep)
> - n->gpio[0]->set_multiple(n->gpio[0], &m, &v);
> - else
> - WARN(1, "nep unset\n");
> -}
> -EXPORT_SYMBOL(neponset_ncr_frob);
> -
> -/*
> - * Install handler for Neponset IRQ. Note that we have to loop here
> - * since the ETHERNET and USAR IRQs are level based, and we need to
> - * ensure that the IRQ signal is deasserted before returning. This
> - * is rather unfortunate.
> - */
> -static void neponset_irq_handler(struct irq_desc *desc)
> -{
> - struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
> - unsigned int irr;
> -
> - while (1) {
> - /*
> - * Acknowledge the parent IRQ.
> - */
> - desc->irq_data.chip->irq_ack(&desc->irq_data);
> -
> - /*
> - * Read the interrupt reason register. Let's have all
> - * active IRQ bits high. Note: there is a typo in the
> - * Neponset user's guide for the SA1111 IRR level.
> - */
> - irr = readb_relaxed(d->base + IRR);
> - irr ^= IRR_ETHERNET | IRR_USAR;
> -
> - if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
> - break;
> -
> - /*
> - * Since there is no individual mask, we have to
> - * mask the parent IRQ. This is safe, since we'll
> - * recheck the register for any pending IRQs.
> - */
> - if (irr & (IRR_ETHERNET | IRR_USAR)) {
> - desc->irq_data.chip->irq_mask(&desc->irq_data);
> -
> - /*
> - * Ack the interrupt now to prevent re-entering
> - * this neponset handler. Again, this is safe
> - * since we'll check the IRR register prior to
> - * leaving.
> - */
> - desc->irq_data.chip->irq_ack(&desc->irq_data);
> -
> - if (irr & IRR_ETHERNET)
> - generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X);
> -
> - if (irr & IRR_USAR)
> - generic_handle_irq(d->irq_base + NEP_IRQ_USAR);
> -
> - desc->irq_data.chip->irq_unmask(&desc->irq_data);
> - }
> -
> - if (irr & IRR_SA1111)
> - generic_handle_irq(d->irq_base + NEP_IRQ_SA1111);
> - }
> -}
> -
> -/* Yes, we really do not have any kind of masking or unmasking */
> -static void nochip_noop(struct irq_data *irq)
> -{
> -}
> -
> -static struct irq_chip nochip = {
> - .name = "neponset",
> - .irq_ack = nochip_noop,
> - .irq_mask = nochip_noop,
> - .irq_unmask = nochip_noop,
> -};
> -
> -static int neponset_init_gpio(struct gpio_chip **gcp,
> - struct device *dev, const char *label, void __iomem *reg,
> - unsigned num, bool in, const char *const * names)
> -{
> - struct gpio_chip *gc;
> -
> - gc = gpio_reg_init(dev, reg, -1, num, label, in ? 0xffffffff : 0,
> - readl_relaxed(reg), names, NULL, NULL);
> - if (IS_ERR(gc))
> - return PTR_ERR(gc);
> -
> - *gcp = gc;
> -
> - return 0;
> -}
> -
> -static struct sa1111_platform_data sa1111_info = {
> - .disable_devs = SA1111_DEVID_PS2_MSE,
> -};
> -
> -static int neponset_probe(struct platform_device *dev)
> -{
> - struct neponset_drvdata *d;
> - struct resource *nep_res, *sa1111_res, *smc91x_res;
> - struct resource sa1111_resources[] = {
> - DEFINE_RES_MEM(0x40000000, SZ_8K),
> - { .flags = IORESOURCE_IRQ },
> - };
> - struct platform_device_info sa1111_devinfo = {
> - .parent = &dev->dev,
> - .name = "sa1111",
> - .id = 0,
> - .res = sa1111_resources,
> - .num_res = ARRAY_SIZE(sa1111_resources),
> - .data = &sa1111_info,
> - .size_data = sizeof(sa1111_info),
> - .dma_mask = 0xffffffffUL,
> - };
> - struct resource smc91x_resources[] = {
> - DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
> - 0x02000000, "smc91x-regs"),
> - DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
> - 0x02000000, "smc91x-attrib"),
> - { .flags = IORESOURCE_IRQ },
> - };
> - struct smc91x_platdata smc91x_platdata = {
> - .flags = SMC91X_USE_8BIT | SMC91X_IO_SHIFT_2 | SMC91X_NOWAIT,
> - };
> - struct platform_device_info smc91x_devinfo = {
> - .parent = &dev->dev,
> - .name = "smc91x",
> - .id = 0,
> - .res = smc91x_resources,
> - .num_res = ARRAY_SIZE(smc91x_resources),
> - .data = &smc91x_platdata,
> - .size_data = sizeof(smc91x_platdata),
> - };
> - int ret, irq;
> -
> - if (nep)
> - return -EBUSY;
> -
> - irq = ret = platform_get_irq(dev, 0);
> - if (ret < 0)
> - goto err_alloc;
> -
> - nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
> - smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
> - sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
> - if (!nep_res || !smc91x_res || !sa1111_res) {
> - ret = -ENXIO;
> - goto err_alloc;
> - }
> -
> - d = kzalloc_obj(*d);
> - if (!d) {
> - ret = -ENOMEM;
> - goto err_alloc;
> - }
> -
> - d->base = ioremap(nep_res->start, SZ_4K);
> - if (!d->base) {
> - ret = -ENOMEM;
> - goto err_ioremap;
> - }
> -
> - if (readb_relaxed(d->base + WHOAMI) != 0x11) {
> - dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
> - readb_relaxed(d->base + WHOAMI));
> - ret = -ENODEV;
> - goto err_id;
> - }
> -
> - ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
> - if (ret <= 0) {
> - dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
> - NEP_IRQ_NR, ret);
> - if (ret == 0)
> - ret = -ENOMEM;
> - goto err_irq_alloc;
> - }
> -
> - d->irq_base = ret;
> -
> - irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
> - handle_simple_irq);
> - irq_clear_status_flags(d->irq_base + NEP_IRQ_SMC91X, IRQ_NOREQUEST | IRQ_NOPROBE);
> - irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
> - handle_simple_irq);
> - irq_clear_status_flags(d->irq_base + NEP_IRQ_USAR, IRQ_NOREQUEST | IRQ_NOPROBE);
> - irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);
> -
> - irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
> - irq_set_chained_handler_and_data(irq, neponset_irq_handler, d);
> -
> - /* Disable GPIO 0/1 drivers so the buttons work on the Assabet */
> - writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0);
> -
> - neponset_init_gpio(&d->gpio[0], &dev->dev, "neponset-ncr",
> - d->base + NCR_0, NCR_NGPIO, false,
> - neponset_ncr_names);
> - neponset_init_gpio(&d->gpio[1], &dev->dev, "neponset-mdm-ctl0",
> - d->base + MDM_CTL_0, MDM_CTL0_NGPIO, false,
> - neponset_mdmctl0_names);
> - neponset_init_gpio(&d->gpio[2], &dev->dev, "neponset-mdm-ctl1",
> - d->base + MDM_CTL_1, MDM_CTL1_NGPIO, true,
> - neponset_mdmctl1_names);
> - neponset_init_gpio(&d->gpio[3], &dev->dev, "neponset-aud-ctl",
> - d->base + AUD_CTL, AUD_NGPIO, false,
> - neponset_aud_names);
> -
> - gpiod_add_lookup_table(&neponset_uart1_gpio_table);
> - gpiod_add_lookup_table(&neponset_uart3_gpio_table);
> - gpiod_add_lookup_table(&neponset_pcmcia_table);
> -
> - /*
> - * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately
> - * something on the Neponset activates this IRQ on sleep (eth?)
> - */
> -#if 0
> - enable_irq_wake(irq);
> -#endif
> -
> - dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n",
> - d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
> - nep = d;
> -
> - /* Ensure that the memory bus request/grant signals are setup */
> - sa1110_mb_disable();
> -
> - sa1111_resources[0].parent = sa1111_res;
> - sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111;
> - sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111;
> - d->sa1111 = platform_device_register_full(&sa1111_devinfo);
> -
> - smc91x_resources[0].parent = smc91x_res;
> - smc91x_resources[1].parent = smc91x_res;
> - smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
> - smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
> - d->smc91x = platform_device_register_full(&smc91x_devinfo);
> -
> - platform_set_drvdata(dev, d);
> -
> - return 0;
> -
> - err_irq_alloc:
> - err_id:
> - iounmap(d->base);
> - err_ioremap:
> - kfree(d);
> - err_alloc:
> - return ret;
> -}
> -
> -static void neponset_remove(struct platform_device *dev)
> -{
> - struct neponset_drvdata *d = platform_get_drvdata(dev);
> - int irq = platform_get_irq(dev, 0);
> -
> - if (!IS_ERR(d->sa1111))
> - platform_device_unregister(d->sa1111);
> - if (!IS_ERR(d->smc91x))
> - platform_device_unregister(d->smc91x);
> -
> - gpiod_remove_lookup_table(&neponset_pcmcia_table);
> - gpiod_remove_lookup_table(&neponset_uart3_gpio_table);
> - gpiod_remove_lookup_table(&neponset_uart1_gpio_table);
> -
> - irq_set_chained_handler(irq, NULL);
> - irq_free_descs(d->irq_base, NEP_IRQ_NR);
> - nep = NULL;
> - iounmap(d->base);
> - kfree(d);
> -}
> -
> -#ifdef CONFIG_PM_SLEEP
> -static int neponset_resume(struct device *dev)
> -{
> - struct neponset_drvdata *d = dev_get_drvdata(dev);
> - int i, ret = 0;
> -
> - for (i = 0; i < ARRAY_SIZE(d->gpio); i++) {
> - ret = gpio_reg_resume(d->gpio[i]);
> - if (ret)
> - break;
> - }
> -
> - return ret;
> -}
> -
> -static const struct dev_pm_ops neponset_pm_ops = {
> - .resume_noirq = neponset_resume,
> - .restore_noirq = neponset_resume,
> -};
> -#define PM_OPS &neponset_pm_ops
> -#else
> -#define PM_OPS NULL
> -#endif
> -
> -static struct platform_driver neponset_device_driver = {
> - .probe = neponset_probe,
> - .remove = neponset_remove,
> - .driver = {
> - .name = "neponset",
> - .pm = PM_OPS,
> - },
> -};
> -
> -static int __init neponset_init(void)
> -{
> - return platform_driver_register(&neponset_device_driver);
> -}
> -
> -subsys_initcall(neponset_init);
> diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
> deleted file mode 100644
> index 9495fc109baa..000000000000
> --- a/arch/arm/mach-sa1100/pm.c
> +++ /dev/null
> @@ -1,128 +0,0 @@
> -/*
> - * SA1100 Power Management Routines
> - *
> - * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License.
> - *
> - * History:
> - *
> - * 2001-02-06: Cliff Brake Initial code
> - *
> - * 2001-02-25: Sukjae Cho <sjcho@east.isi.edu> &
> - * Chester Kuo <chester@linux.org.tw>
> - * Save more value for the resume function! Support
> - * Bitsy/Assabet/Freebird board
> - *
> - * 2001-08-29: Nicolas Pitre <nico@fluxnic.net>
> - * Cleaned up, pushed platform dependent stuff
> - * in the platform specific files.
> - *
> - * 2002-05-27: Nicolas Pitre Killed sleep.h and the kmalloced save array.
> - * Storage is local on the stack now.
> - */
> -#include <linux/init.h>
> -#include <linux/io.h>
> -#include <linux/suspend.h>
> -#include <linux/errno.h>
> -#include <linux/time.h>
> -
> -#include <mach/hardware.h>
> -#include <asm/page.h>
> -#include <asm/suspend.h>
> -#include <asm/mach/time.h>
> -
> -#include "generic.h"
> -
> -extern int sa1100_finish_suspend(unsigned long);
> -
> -#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
> -#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
> -
> -/*
> - * List of global SA11x0 peripheral registers to preserve.
> - * More ones like CP and general purpose register values are preserved
> - * on the stack and then the stack pointer is stored last in sleep.S.
> - */
> -enum { SLEEP_SAVE_GPDR, SLEEP_SAVE_GAFR,
> - SLEEP_SAVE_PPDR, SLEEP_SAVE_PPSR, SLEEP_SAVE_PPAR, SLEEP_SAVE_PSDR,
> -
> - SLEEP_SAVE_Ser1SDCR0,
> -
> - SLEEP_SAVE_COUNT
> -};
> -
> -
> -static int sa11x0_pm_enter(suspend_state_t state)
> -{
> - unsigned long gpio, sleep_save[SLEEP_SAVE_COUNT];
> -
> - gpio = GPLR;
> -
> - /* save vital registers */
> - SAVE(GPDR);
> - SAVE(GAFR);
> -
> - SAVE(PPDR);
> - SAVE(PPSR);
> - SAVE(PPAR);
> - SAVE(PSDR);
> -
> - SAVE(Ser1SDCR0);
> -
> - /* Clear previous reset status */
> - RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR;
> -
> - /* set resume return address */
> - PSPR = __pa_symbol(cpu_resume);
> -
> - /* go zzz */
> - cpu_suspend(0, sa1100_finish_suspend);
> -
> - /*
> - * Ensure not to come back here if it wasn't intended
> - */
> - RCSR = RCSR_SMR;
> - PSPR = 0;
> -
> - /*
> - * Ensure interrupt sources are disabled; we will re-init
> - * the interrupt subsystem via the device manager.
> - */
> - ICLR = 0;
> - ICCR = 1;
> - ICMR = 0;
> -
> - /* restore registers */
> - RESTORE(GPDR);
> - RESTORE(GAFR);
> -
> - RESTORE(PPDR);
> - RESTORE(PPSR);
> - RESTORE(PPAR);
> - RESTORE(PSDR);
> -
> - RESTORE(Ser1SDCR0);
> -
> - GPSR = gpio;
> - GPCR = ~gpio;
> -
> - /*
> - * Clear the peripheral sleep-hold bit.
> - */
> - PSSR = PSSR_PH;
> -
> - return 0;
> -}
> -
> -static const struct platform_suspend_ops sa11x0_pm_ops = {
> - .enter = sa11x0_pm_enter,
> - .valid = suspend_valid_only_mem,
> -};
> -
> -int __init sa11x0_pm_init(void)
> -{
> - suspend_set_ops(&sa11x0_pm_ops);
> - return 0;
> -}
> diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
> deleted file mode 100644
> index 85863741ef8b..000000000000
> --- a/arch/arm/mach-sa1100/sleep.S
> +++ /dev/null
> @@ -1,143 +0,0 @@
> -/*
> - * SA11x0 Assembler Sleep/WakeUp Management Routines
> - *
> - * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License.
> - *
> - * History:
> - *
> - * 2001-02-06: Cliff Brake Initial code
> - *
> - * 2001-08-29: Nicolas Pitre Simplified.
> - *
> - * 2002-05-27: Nicolas Pitre Revisited, more cleanup and simplification.
> - * Storage is on the stack now.
> - */
> -
> -#include <linux/linkage.h>
> -#include <asm/assembler.h>
> -#include <mach/hardware.h>
> -
> - .text
> -/*
> - * sa1100_finish_suspend()
> - *
> - * Causes sa11x0 to enter sleep state
> - *
> - * Must be aligned to a cacheline.
> - */
> - .balign 32
> -ENTRY(sa1100_finish_suspend)
> - @ disable clock switching
> - mcr p15, 0, r1, c15, c2, 2
> -
> - ldr r6, =MDREFR
> - ldr r4, [r6]
> - orr r4, r4, #MDREFR_K1DB2
> - ldr r5, =PPCR
> -
> - @ Pre-load __loop_udelay into the I-cache
> - mov r0, #1
> - bl __loop_udelay
> - mov r0, r0
> -
> - @ The following must all exist in a single cache line to
> - @ avoid accessing memory until this sequence is complete,
> - @ otherwise we occasionally hang.
> -
> - @ Adjust memory timing before lowering CPU clock
> - str r4, [r6]
> -
> - @ delay 90us and set CPU PLL to lowest speed
> - @ fixes resume problem on high speed SA1110
> - mov r0, #90
> - bl __loop_udelay
> - mov r1, #0
> - str r1, [r5]
> - mov r0, #90
> - bl __loop_udelay
> -
> - /*
> - * SA1110 SDRAM controller workaround. register values:
> - *
> - * r0 = &MSC0
> - * r1 = &MSC1
> - * r2 = &MSC2
> - * r3 = MSC0 value
> - * r4 = MSC1 value
> - * r5 = MSC2 value
> - * r6 = &MDREFR
> - * r7 = first MDREFR value
> - * r8 = second MDREFR value
> - * r9 = &MDCNFG
> - * r10 = MDCNFG value
> - * r11 = third MDREFR value
> - * r12 = &PMCR
> - * r13 = PMCR value (1)
> - */
> -
> - ldr r0, =MSC0
> - ldr r1, =MSC1
> - ldr r2, =MSC2
> -
> - ldr r3, [r0]
> - bic r3, r3, #FMsk(MSC_RT)
> - bic r3, r3, #FMsk(MSC_RT)<<16
> -
> - ldr r4, [r1]
> - bic r4, r4, #FMsk(MSC_RT)
> - bic r4, r4, #FMsk(MSC_RT)<<16
> -
> - ldr r5, [r2]
> - bic r5, r5, #FMsk(MSC_RT)
> - bic r5, r5, #FMsk(MSC_RT)<<16
> -
> - ldr r7, [r6]
> - bic r7, r7, #0x0000FF00
> - bic r7, r7, #0x000000F0
> - orr r8, r7, #MDREFR_SLFRSH
> -
> - ldr r9, =MDCNFG
> - ldr r10, [r9]
> - bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1)
> - bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3)
> -
> - bic r11, r8, #MDREFR_SLFRSH
> - bic r11, r11, #MDREFR_E1PIN
> -
> - ldr r12, =PMCR
> -
> - mov r13, #PMCR_SF
> -
> - b sa1110_sdram_controller_fix
> -
> - .align 5
> -sa1110_sdram_controller_fix:
> -
> - @ Step 1 clear RT field of all MSCx registers
> - str r3, [r0]
> - str r4, [r1]
> - str r5, [r2]
> -
> - @ Step 2 clear DRI field in MDREFR
> - str r7, [r6]
> -
> - @ Step 3 set SLFRSH bit in MDREFR
> - str r8, [r6]
> -
> - @ Step 4 clear DE bis in MDCNFG
> - str r10, [r9]
> -
> - @ Step 5 clear DRAM refresh control register
> - str r11, [r6]
> -
> - @ Wow, now the hardware suspend request pins can be used, that makes them functional for
> - @ about 7 ns out of the entire time that the CPU is running!
> -
> - @ Step 6 set force sleep bit in PMCR
> -
> - str r13, [r12]
> -
> -20: b 20b @ loop waiting for sleep
> diff --git a/arch/arm/mach-sa1100/ssp.c b/arch/arm/mach-sa1100/ssp.c
> deleted file mode 100644
> index 613fd767afcf..000000000000
> --- a/arch/arm/mach-sa1100/ssp.c
> +++ /dev/null
> @@ -1,240 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * linux/arch/arm/mach-sa1100/ssp.c
> - *
> - * Copyright (C) 2003 Russell King.
> - *
> - * Generic SSP driver. This provides the generic core for simple
> - * IO-based SSP applications.
> - */
> -#include <linux/module.h>
> -#include <linux/kernel.h>
> -#include <linux/sched.h>
> -#include <linux/errno.h>
> -#include <linux/interrupt.h>
> -#include <linux/ioport.h>
> -#include <linux/init.h>
> -#include <linux/io.h>
> -
> -#include <mach/hardware.h>
> -#include <mach/irqs.h>
> -#include <asm/hardware/ssp.h>
> -
> -#define TIMEOUT 100000
> -
> -static irqreturn_t ssp_interrupt(int irq, void *dev_id)
> -{
> - unsigned int status = Ser4SSSR;
> -
> - if (status & SSSR_ROR)
> - printk(KERN_WARNING "SSP: receiver overrun\n");
> -
> - Ser4SSSR = SSSR_ROR;
> -
> - return status ? IRQ_HANDLED : IRQ_NONE;
> -}
> -
> -/**
> - * ssp_write_word - write a word to the SSP port
> - * @data: 16-bit, MSB justified data to write.
> - *
> - * Wait for a free entry in the SSP transmit FIFO, and write a data
> - * word to the SSP port. Wait for the SSP port to start sending
> - * the data.
> - *
> - * The caller is expected to perform the necessary locking.
> - *
> - * Returns:
> - * %-ETIMEDOUT timeout occurred
> - * 0 success
> - */
> -int ssp_write_word(u16 data)
> -{
> - int timeout = TIMEOUT;
> -
> - while (!(Ser4SSSR & SSSR_TNF)) {
> - if (!--timeout)
> - return -ETIMEDOUT;
> - cpu_relax();
> - }
> -
> - Ser4SSDR = data;
> -
> - timeout = TIMEOUT;
> - while (!(Ser4SSSR & SSSR_BSY)) {
> - if (!--timeout)
> - return -ETIMEDOUT;
> - cpu_relax();
> - }
> -
> - return 0;
> -}
> -
> -/**
> - * ssp_read_word - read a word from the SSP port
> - *
> - * Wait for a data word in the SSP receive FIFO, and return the
> - * received data. Data is LSB justified.
> - *
> - * Note: Currently, if data is not expected to be received, this
> - * function will wait for ever.
> - *
> - * The caller is expected to perform the necessary locking.
> - *
> - * Returns:
> - * %-ETIMEDOUT timeout occurred
> - * 16-bit data success
> - */
> -int ssp_read_word(u16 *data)
> -{
> - int timeout = TIMEOUT;
> -
> - while (!(Ser4SSSR & SSSR_RNE)) {
> - if (!--timeout)
> - return -ETIMEDOUT;
> - cpu_relax();
> - }
> -
> - *data = (u16)Ser4SSDR;
> -
> - return 0;
> -}
> -
> -/**
> - * ssp_flush - flush the transmit and receive FIFOs
> - *
> - * Wait for the SSP to idle, and ensure that the receive FIFO
> - * is empty.
> - *
> - * The caller is expected to perform the necessary locking.
> - *
> - * Returns:
> - * %-ETIMEDOUT timeout occurred
> - * 0 success
> - */
> -int ssp_flush(void)
> -{
> - int timeout = TIMEOUT * 2;
> -
> - do {
> - while (Ser4SSSR & SSSR_RNE) {
> - if (!--timeout)
> - return -ETIMEDOUT;
> - (void) Ser4SSDR;
> - }
> - if (!--timeout)
> - return -ETIMEDOUT;
> - } while (Ser4SSSR & SSSR_BSY);
> -
> - return 0;
> -}
> -
> -/**
> - * ssp_enable - enable the SSP port
> - *
> - * Turn on the SSP port.
> - */
> -void ssp_enable(void)
> -{
> - Ser4SSCR0 |= SSCR0_SSE;
> -}
> -
> -/**
> - * ssp_disable - shut down the SSP port
> - *
> - * Turn off the SSP port, optionally powering it down.
> - */
> -void ssp_disable(void)
> -{
> - Ser4SSCR0 &= ~SSCR0_SSE;
> -}
> -
> -/**
> - * ssp_save_state - save the SSP configuration
> - * @ssp: pointer to structure to save SSP configuration
> - *
> - * Save the configured SSP state for suspend.
> - */
> -void ssp_save_state(struct ssp_state *ssp)
> -{
> - ssp->cr0 = Ser4SSCR0;
> - ssp->cr1 = Ser4SSCR1;
> -
> - Ser4SSCR0 &= ~SSCR0_SSE;
> -}
> -
> -/**
> - * ssp_restore_state - restore a previously saved SSP configuration
> - * @ssp: pointer to configuration saved by ssp_save_state
> - *
> - * Restore the SSP configuration saved previously by ssp_save_state.
> - */
> -void ssp_restore_state(struct ssp_state *ssp)
> -{
> - Ser4SSSR = SSSR_ROR;
> -
> - Ser4SSCR0 = ssp->cr0 & ~SSCR0_SSE;
> - Ser4SSCR1 = ssp->cr1;
> - Ser4SSCR0 = ssp->cr0;
> -}
> -
> -/**
> - * ssp_init - setup the SSP port
> - *
> - * initialise and claim resources for the SSP port.
> - *
> - * Returns:
> - * %-ENODEV if the SSP port is unavailable
> - * %-EBUSY if the resources are already in use
> - * %0 on success
> - */
> -int ssp_init(void)
> -{
> - int ret;
> -
> - if (!(PPAR & PPAR_SPR) && (Ser4MCCR0 & MCCR0_MCE))
> - return -ENODEV;
> -
> - if (!request_mem_region(__PREG(Ser4SSCR0), 0x18, "SSP")) {
> - return -EBUSY;
> - }
> -
> - Ser4SSSR = SSSR_ROR;
> -
> - ret = request_irq(IRQ_Ser4SSP, ssp_interrupt, 0, "SSP", NULL);
> - if (ret)
> - goto out_region;
> -
> - return 0;
> -
> - out_region:
> - release_mem_region(__PREG(Ser4SSCR0), 0x18);
> - return ret;
> -}
> -
> -/**
> - * ssp_exit - undo the effects of ssp_init
> - *
> - * release and free resources for the SSP port.
> - */
> -void ssp_exit(void)
> -{
> - Ser4SSCR0 &= ~SSCR0_SSE;
> -
> - free_irq(IRQ_Ser4SSP, NULL);
> - release_mem_region(__PREG(Ser4SSCR0), 0x18);
> -}
> -
> -MODULE_AUTHOR("Russell King");
> -MODULE_DESCRIPTION("SA11x0 SSP PIO driver");
> -MODULE_LICENSE("GPL");
> -
> -EXPORT_SYMBOL(ssp_write_word);
> -EXPORT_SYMBOL(ssp_read_word);
> -EXPORT_SYMBOL(ssp_flush);
> -EXPORT_SYMBOL(ssp_enable);
> -EXPORT_SYMBOL(ssp_disable);
> -EXPORT_SYMBOL(ssp_save_state);
> -EXPORT_SYMBOL(ssp_restore_state);
> -EXPORT_SYMBOL(ssp_init);
> -EXPORT_SYMBOL(ssp_exit);
> diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
> index 0cc1bf04686d..bf94f2718293 100644
> --- a/arch/arm/mm/init.c
> +++ b/arch/arm/mm/init.c
> @@ -226,11 +226,6 @@ void __init arch_mm_preinit(void)
> swiotlb_init(max_pfn > arm_dma_pfn_limit, SWIOTLB_VERBOSE);
> #endif
>
> -#ifdef CONFIG_SA1111
> - /* now that our DMA memory is actually so designated, we can free it */
> - memblock_phys_free(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
> -#endif
> -
> /*
> * Check boundaries twice: Some fundamental inconsistencies can
> * be detected at build time already.
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index 23b87b5ef7f1..350f6dcc24cc 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -1339,14 +1339,6 @@ void __init arm_mm_memblock_reserve(void)
> * and can only be in node 0.
> */
> memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
> -
> -#ifdef CONFIG_SA1111
> - /*
> - * Because of the SA1111 DMA bug, we want to preserve our
> - * precious DMA-able memory...
> - */
> - memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
> -#endif
> }
>
> /*
> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
> index 05b9233b9418..55ffee3d75ce 100644
> --- a/drivers/rtc/Kconfig
> +++ b/drivers/rtc/Kconfig
> @@ -1541,8 +1541,8 @@ config RTC_DRV_EP93XX
> will be called rtc-ep93xx.
>
> config RTC_DRV_SA1100
> - tristate "SA11x0/PXA2xx/PXA910"
> - depends on ARCH_SA1100 || ARCH_PXA || ARCH_MMP
> + tristate "PXA2xx/PXA910"
> + depends on ARCH_PXA || ARCH_MMP
> help
> If you say Y here you will get access to the real time clock
> built into your SA11x0 or PXA2xx CPU.
> diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c
> index 26b2f4184ecc..dc98484dbe27 100644
> --- a/drivers/rtc/rtc-sa1100.c
> +++ b/drivers/rtc/rtc-sa1100.c
> @@ -275,18 +275,10 @@ static int sa1100_rtc_probe(struct platform_device *pdev)
> if (IS_ERR(base))
> return PTR_ERR(base);
>
> - if (IS_ENABLED(CONFIG_ARCH_SA1100) ||
> - of_device_is_compatible(pdev->dev.of_node, "mrvl,sa1100-rtc")) {
> - info->rcnr = base + 0x04;
> - info->rtsr = base + 0x10;
> - info->rtar = base + 0x00;
> - info->rttr = base + 0x08;
> - } else {
> - info->rcnr = base + 0x0;
> - info->rtsr = base + 0x8;
> - info->rtar = base + 0x4;
> - info->rttr = base + 0xc;
> - }
> + info->rcnr = base + 0x0;
> + info->rtsr = base + 0x8;
> + info->rtar = base + 0x4;
> + info->rttr = base + 0xc;
>
> platform_set_drvdata(pdev, info);
> device_init_wakeup(&pdev->dev, true);
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index f7d0a0c2c0ef..0ab0dcc6d27d 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -614,16 +614,16 @@ config S3C2410_WATCHDOG
> be called s3c2410_wdt.
>
> config SA1100_WATCHDOG
> - tristate "SA1100/PXA2xx watchdog"
> - depends on ARCH_SA1100 || ARCH_PXA || COMPILE_TEST
> + tristate "PXA2xx watchdog"
> + depends on ARCH_PXA || COMPILE_TEST
> help
> - Watchdog timer embedded into SA11x0 and PXA2xx chips. This will
> - reboot your system when timeout is reached.
> + Watchdog timer embedded PXA2xx chips. This will reboot your
> + system when timeout is reached.
>
> NOTE: once enabled, this timer cannot be disabled.
>
> - To compile this driver as a module, choose M here: the
> - module will be called sa1100_wdt.
> + To compile this driver as a module, choose M here: the module
> + will be called sa1100_wdt.
>
> config DW_WATCHDOG
> tristate "Synopsys DesignWare watchdog"
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 01/13] ARM: remove sa1100 platform
2026-09-08 20:36 ` Nicolas Pitre
@ 2026-09-08 21:26 ` David Laight
2026-09-08 21:32 ` Arnd Bergmann
1 sibling, 0 replies; 70+ messages in thread
From: David Laight @ 2026-09-08 21:26 UTC (permalink / raw)
To: Nicolas Pitre
Cc: Arnd Bergmann, Krzysztof Kozlowski, Alexandre Belloni,
Linus Walleij, Russell King, Drew Fustini, Arnd Bergmann,
Rob Herring, Conor Dooley, Liviu Dudau, Sudeep Holla,
Lorenzo Pieralisi, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Vladimir Zapolskiy,
Stefan Agner, Maxime Coquelin, Alexandre Torgue, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Nicolas Ferre, Claudiu Beznea, Andrew Lunn,
Sebastian Hesselbarth, Gregory Clement, Robert Jarzmik,
Kristoffer Ericson, Ethan Nelson-Moore, Geert Uytterhoeven,
Alexander Sverdlin, Shawn Guo, Karl Mehltretter,
David Hildenbrand (Arm),
linux-doc, linux-kernel, linux-arm-kernel, devicetree, imx,
linux-stm32, linux-omap, Guenter Roeck
On Tue, 8 Sep 2026 16:36:47 -0400 (EDT)
Nicolas Pitre <nico@fluxnic.net> wrote:
> On Tue, 8 Sep 2026, Arnd Bergmann wrote:
>
> > From: Arnd Bergmann <arnd@arndb.de>
> >
> > Most sa1100 platforms were removed a few years, with the remaining
> > ones left as a starting point for a conversion to devicetree.
> >
> > Nothing ever happened on that front, so remove the rest now,
> > including the sa1111 and locomo drivers that were once shared
> > with pxa but are already sa1100-exclusive now.
>
> The SA1100 was the starting point of my career. Feels strange how much
> time has passed.
>
> I parted with such hardware a long time ago in any case.
I failed to 'steal' a J-Slate when I left Tadpole.
(a very early 'tablet' computer with an LCD panel)
So I don't have one either.
Although that ran VxWorks and rtx-windows (after I patched bits so it worked!).
David
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 01/13] ARM: remove sa1100 platform
2026-09-08 20:36 ` Nicolas Pitre
2026-09-08 21:26 ` David Laight
@ 2026-09-08 21:32 ` Arnd Bergmann
1 sibling, 0 replies; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 21:32 UTC (permalink / raw)
To: Nicolas Pitre, Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, A. Sverdlin, Shawn Guo, Karl Mehltretter,
David Hildenbrand (Red Hat),
linux-doc, linux-kernel, linux-arm-kernel, devicetree, imx,
linux-stm32, Linux-OMAP, Guenter Roeck
On Tue, Sep 8, 2026, at 22:36, Nicolas Pitre wrote:
> On Tue, 8 Sep 2026, Arnd Bergmann wrote:
>
>> From: Arnd Bergmann <arnd@arndb.de>
>>
>> Most sa1100 platforms were removed a few years, with the remaining
>> ones left as a starting point for a conversion to devicetree.
>>
>> Nothing ever happened on that front, so remove the rest now,
>> including the sa1111 and locomo drivers that were once shared
>> with pxa but are already sa1100-exclusive now.
>
> The SA1100 was the starting point of my career. Feels strange how much
> time has passed.
Indeed, same for me: my first paid job involved both SA1100 and
the i486 compatible AMD Élan SoC that was also removed this year.
> I parted with such hardware a long time ago in any case.
>
> Acked-by: Nicolas Pitre <nico@fluxnic.net>
Thanks,
Arnd
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH 02/13] ARM: remove footbridge
2026-09-08 15:27 [PATCH 00/13] ARM: deprecated platform removal Arnd Bergmann
2026-09-08 15:27 ` [PATCH 01/13] ARM: remove sa1100 platform Arnd Bergmann
@ 2026-09-08 15:27 ` Arnd Bergmann
2026-09-08 17:27 ` Linus Walleij
2026-09-08 15:27 ` [PATCH 03/13] ARM: remove riscpc Arnd Bergmann
` (11 subsequent siblings)
13 siblings, 1 reply; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 15:27 UTC (permalink / raw)
To: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Ralph Siemsen,
Helge Deller, dri-devel
From: Arnd Bergmann <arnd@arndb.de>
Footbridge was deprecated in 7.3 to be removed along with the other
StrongARM platforms and most remaining board files.
The main machine here is the NetWinder, which was a popular Arm based
desktop PC in the late 1990s and contributed to Arm's later success as
an embedded Linux platform, but was discontinued over 25 years ago and
is no longer all that useful.
I previously tried to convert this to devicetree in a sensible way but
gave up due to the platform being too different from modern SoC based
targets.
Cc: Russell King <linux@armlinux.org.uk>
Cc: Ralph Siemsen <ralphs@netwinder.org>
Cc: Helge Deller <deller@gmx.de>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
Documentation/arch/arm/index.rst | 1 -
Documentation/arch/arm/netwinder.rst | 85 --
MAINTAINERS | 8 -
arch/arm/Kconfig | 17 +-
arch/arm/Kconfig.debug | 27 +-
arch/arm/Makefile | 2 -
arch/arm/boot/bootp/Makefile | 1 -
| 114 ---
arch/arm/configs/netwinder_defconfig | 88 --
arch/arm/include/asm/hardware/dec21285.h | 138 ----
arch/arm/include/asm/mach/pci.h | 14 -
arch/arm/include/debug/dc21285.S | 41 -
arch/arm/kernel/atags_parse.c | 18 -
arch/arm/kernel/bios32.c | 12 -
arch/arm/kernel/head.S | 10 -
| 57 --
| 18 -
| 280 -------
| 15 -
| 136 ---
| 360 --------
| 230 ------
| 48 --
| 124 ---
| 90 --
| 97 ---
| 18 -
| 26 -
| 34 -
| 177 ----
| 57 --
| 36 -
| 94 ---
| 772 ------------------
| 62 --
drivers/video/console/Kconfig | 6 +-
drivers/video/console/dummycon.c | 6 -
drivers/video/fbdev/cyber2000fb.c | 10 -
38 files changed, 12 insertions(+), 3317 deletions(-)
delete mode 100644 Documentation/arch/arm/netwinder.rst
delete mode 100644 arch/arm/configs/footbridge_defconfig
delete mode 100644 arch/arm/configs/netwinder_defconfig
delete mode 100644 arch/arm/include/asm/hardware/dec21285.h
delete mode 100644 arch/arm/include/debug/dc21285.S
delete mode 100644 arch/arm/mach-footbridge/Kconfig
delete mode 100644 arch/arm/mach-footbridge/Makefile
delete mode 100644 arch/arm/mach-footbridge/common.c
delete mode 100644 arch/arm/mach-footbridge/common.h
delete mode 100644 arch/arm/mach-footbridge/dc21285-timer.c
delete mode 100644 arch/arm/mach-footbridge/dc21285.c
delete mode 100644 arch/arm/mach-footbridge/dma-isa.c
delete mode 100644 arch/arm/mach-footbridge/ebsa285-pci.c
delete mode 100644 arch/arm/mach-footbridge/ebsa285.c
delete mode 100644 arch/arm/mach-footbridge/include/mach/hardware.h
delete mode 100644 arch/arm/mach-footbridge/include/mach/irqs.h
delete mode 100644 arch/arm/mach-footbridge/include/mach/isa-dma.h
delete mode 100644 arch/arm/mach-footbridge/include/mach/memory.h
delete mode 100644 arch/arm/mach-footbridge/include/mach/uncompress.h
delete mode 100644 arch/arm/mach-footbridge/isa-irq.c
delete mode 100644 arch/arm/mach-footbridge/isa-rtc.c
delete mode 100644 arch/arm/mach-footbridge/isa-timer.c
delete mode 100644 arch/arm/mach-footbridge/isa.c
delete mode 100644 arch/arm/mach-footbridge/netwinder-hw.c
delete mode 100644 arch/arm/mach-footbridge/netwinder-pci.c
diff --git a/Documentation/arch/arm/index.rst b/Documentation/arch/arm/index.rst
index a292b8ac41ce..17d6a5bbfc26 100644
--- a/Documentation/arch/arm/index.rst
+++ b/Documentation/arch/arm/index.rst
@@ -38,7 +38,6 @@ SoC-specific documents
marvell
microchip
- netwinder
nwfpe/index
keystone/overview
diff --git a/Documentation/arch/arm/netwinder.rst b/Documentation/arch/arm/netwinder.rst
deleted file mode 100644
index 8eab66caa2ac..000000000000
--- a/Documentation/arch/arm/netwinder.rst
+++ /dev/null
@@ -1,85 +0,0 @@
-================================
-NetWinder specific documentation
-================================
-
-The NetWinder is a small low-power computer, primarily designed
-to run Linux. It is based around the StrongARM RISC processor,
-DC21285 PCI bridge, with PC-type hardware glued around it.
-
-Port usage
-==========
-
-======= ====== ===============================
-Min Max Description
-======= ====== ===============================
-0x0000 0x000f DMA1
-0x0020 0x0021 PIC1
-0x0060 0x006f Keyboard
-0x0070 0x007f RTC
-0x0080 0x0087 DMA1
-0x0088 0x008f DMA2
-0x00a0 0x00a3 PIC2
-0x00c0 0x00df DMA2
-0x0180 0x0187 IRDA
-0x01f0 0x01f6 ide0
-0x0201 Game port
-0x0203 RWA010 configuration read
-0x0220 ? SoundBlaster
-0x0250 ? WaveArtist
-0x0279 RWA010 configuration index
-0x02f8 0x02ff Serial ttyS1
-0x0300 0x031f Ether10
-0x0338 GPIO1
-0x033a GPIO2
-0x0370 0x0371 W83977F configuration registers
-0x0388 ? AdLib
-0x03c0 0x03df VGA
-0x03f6 ide0
-0x03f8 0x03ff Serial ttyS0
-0x0400 0x0408 DC21143
-0x0480 0x0487 DMA1
-0x0488 0x048f DMA2
-0x0a79 RWA010 configuration write
-0xe800 0xe80f ide0/ide1 BM DMA
-======= ====== ===============================
-
-
-Interrupt usage
-===============
-
-======= ======= ========================
-IRQ type Description
-======= ======= ========================
- 0 ISA 100Hz timer
- 1 ISA Keyboard
- 2 ISA cascade
- 3 ISA Serial ttyS1
- 4 ISA Serial ttyS0
- 5 ISA PS/2 mouse
- 6 ISA IRDA
- 7 ISA Printer
- 8 ISA RTC alarm
- 9 ISA
-10 ISA GP10 (Orange reset button)
-11 ISA
-12 ISA WaveArtist
-13 ISA
-14 ISA hda1
-15 ISA
-======= ======= ========================
-
-DMA usage
-=========
-
-======= ======= ===========
-DMA type Description
-======= ======= ===========
- 0 ISA IRDA
- 1 ISA
- 2 ISA cascade
- 3 ISA WaveArtist
- 4 ISA
- 5 ISA
- 6 ISA
- 7 ISA WaveArtist
-======= ======= ===========
diff --git a/MAINTAINERS b/MAINTAINERS
index fd213c4bc257..4380d5660402 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2924,14 +2924,6 @@ S: Maintained
T: git git://git.berlios.de/gemini-board
F: arch/arm/mm/*-fa*
-ARM/FOOTBRIDGE ARCHITECTURE
-M: Russell King <linux@armlinux.org.uk>
-L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-S: Maintained
-W: http://www.armlinux.org.uk/
-F: arch/arm/include/asm/hardware/dec21285.h
-F: arch/arm/mach-footbridge/
-
ARM/FREESCALE IMX / MXC / LAYERSCAPE ARM ARCHITECTURE
M: Frank Li <Frank.Li@nxp.com>
M: Sascha Hauer <s.hauer@pengutronix.de>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7f4c2973d630..c3d6b8abc815 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -55,7 +55,7 @@ config ARM
select ARCH_WANT_LD_ORPHAN_WARN
select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
select BUILDTIME_TABLE_SORT if MMU
- select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE)
+ select COMMON_CLK if !ARCH_RPC
select CLONE_BACKWARDS
select CPU_PM if SUSPEND || CPU_IDLE
select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
@@ -155,13 +155,13 @@ config ARM
select PCI_SYSCALL if PCI
select PERF_USE_VMALLOC
select RTC_LIB
- select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC)
+ select SPARSE_IRQ if !ARCH_RPC
select SYS_SUPPORTS_APM_EMULATION
select THREAD_INFO_IN_TASK
select TIMER_OF if OF
select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
- select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC)
+ select USE_OF if !ARCH_RPC
# Above selects are sorted alphabetically; please add new ones
# according to that. Thanks.
help
@@ -295,7 +295,6 @@ config PHYS_OFFSET
hex "Physical address of main memory" if MMU
depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR
default DRAM_BASE if !MMU
- default 0x00000000 if ARCH_FOOTBRIDGE
default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
default 0xa0000000 if ARCH_PXA
default 0xc0000000 if ARCH_EP93XX
@@ -338,7 +337,7 @@ config ARCH_MMAP_RND_BITS_MAX
config ARCH_MULTIPLATFORM
bool "Require kernel to be portable to multiple machines" if EXPERT
- depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC)
+ depends on MMU && !ARCH_RPC
default y
help
In general, all Arm machines can be supported in a single
@@ -380,14 +379,10 @@ source "arch/arm/mach-davinci/Kconfig"
source "arch/arm/mach-digicolor/Kconfig"
-source "arch/arm/mach-dove/Kconfig"
-
source "arch/arm/mach-ep93xx/Kconfig"
source "arch/arm/mach-exynos/Kconfig"
-source "arch/arm/mach-footbridge/Kconfig"
-
source "arch/arm/mach-gemini/Kconfig"
source "arch/arm/mach-highbank/Kconfig"
@@ -1199,7 +1194,7 @@ config ARCH_FLATMEM_ENABLE
def_bool !ARCH_RPC
config ARCH_SPARSEMEM_ENABLE
- def_bool !ARCH_FOOTBRIDGE
+ def_bool y
select SPARSEMEM_STATIC if SPARSEMEM
config HIGHMEM
@@ -1599,7 +1594,7 @@ config ARCH_DEFAULT_CRASH_DUMP
config AUTO_ZRELADDR
bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM
- default !(ARCH_FOOTBRIDGE || ARCH_RPC)
+ default !ARCH_RPC
help
ZRELADDR is the physical address where the decompressed kernel
image will be placed. If AUTO_ZRELADDR is selected, the address
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index ad0feced4369..f2a80955b7a0 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -324,13 +324,6 @@ choice
Say Y here if you want the debug print routines to direct
their output to UART2 serial port on DaVinci DA8XX devices.
- config DEBUG_DC21285_PORT
- bool "Kernel low-level debugging messages via footbridge serial port"
- depends on FOOTBRIDGE
- help
- Say Y here if you want the debug print routines to direct
- their output to the serial port in the DC21285 (Footbridge).
-
config DEBUG_DIGICOLOR_UA0
bool "Kernel low-level debugging messages via Digicolor UA0"
depends on ARCH_DIGICOLOR
@@ -346,14 +339,6 @@ choice
Say Y here if you want kernel low-level debugging support
on Cirrus Logic EP93xx based platforms.
- config DEBUG_FOOTBRIDGE_COM1
- bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
- depends on FOOTBRIDGE
- select DEBUG_UART_8250
- help
- Say Y here if you want the debug print routines to direct
- their output to the 8250 at PCI COM1.
-
config DEBUG_GEMINI
bool "Kernel low-level debugging messages via Cortina Systems Gemini UART"
depends on ARCH_GEMINI
@@ -1461,7 +1446,7 @@ config DEBUG_STM32_UART
config DEBUG_UART_FLOW_CONTROL
bool "Enable flow control (CTS) for the debug UART"
depends on DEBUG_LL
- default y if DEBUG_FOOTBRIDGE_COM1 || DEBUG_GEMINI || ARCH_RPC
+ default y if DEBUG_GEMINI || ARCH_RPC
help
Some UART ports are connected to terminals that will use modem
control signals to indicate whether they are ready to receive text.
@@ -1476,7 +1461,6 @@ config DEBUG_LL_INCLUDE
default "debug/at91.S" if DEBUG_AT91_UART
default "debug/asm9260.S" if DEBUG_ASM9260_UART
default "debug/clps711x.S" if DEBUG_CLPS711X_UART1 || DEBUG_CLPS711X_UART2
- default "debug/dc21285.S" if DEBUG_DC21285_PORT
default "debug/meson.S" if DEBUG_MESON_UARTAO
default "debug/pl01x.S" if DEBUG_LL_UART_PL01X || DEBUG_UART_PL01X
default "debug/exynos.S" if DEBUG_EXYNOS_UART
@@ -1590,7 +1574,6 @@ config DEBUG_UART_PHYS
default 0x4806e000 if DEBUG_OMAP2UART3 || DEBUG_OMAP4UART4
default 0x49020000 if DEBUG_OMAP3UART3
default 0x49042000 if DEBUG_OMAP3UART4
- default 0x7c0003f8 if DEBUG_FOOTBRIDGE_COM1
default 0x7f005000 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART0
default 0x7f005400 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART1
default 0x7f005800 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART2
@@ -1748,7 +1731,6 @@ config DEBUG_UART_VIRT
default 0xfed64000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
default 0xfed68000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3
default 0xfedc0000 if DEBUG_EP93XX
- default 0xfee003f8 if DEBUG_FOOTBRIDGE_COM1
default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
default 0xfec00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
default 0xfec00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
@@ -1771,8 +1753,7 @@ config DEBUG_UART_VIRT
config DEBUG_UART_8250_SHIFT
int "Register offset shift for the 8250 debug UART"
depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
- default 0 if DEBUG_FOOTBRIDGE_COM1 || DEBUG_BCM_5301X || \
- DEBUG_BCM_HR2
+ default 0 if DEBUG_BCM_5301X || DEBUG_BCM_HR2
default 3 if DEBUG_MSTARV7_PMUART
default 2
@@ -1798,7 +1779,7 @@ config DEBUG_UART_8250_PALMCHIP
config DEBUG_UNCOMPRESS
bool "Enable decompressor debugging via DEBUG_LL output"
depends on !ARCH_MULTIPLATFORM
- depends on !(ARCH_FOOTBRIDGE || ARCH_RPC)
+ depends on !ARCH_RPC
depends on DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
(!DEBUG_TEGRA_UART || !ZBOOT_ROM) && \
!DEBUG_BRCMSTB_UART && !DEBUG_SEMIHOSTING
@@ -1808,7 +1789,7 @@ config DEBUG_UNCOMPRESS
config UNCOMPRESS_INCLUDE
string
- default "mach/uncompress.h" if ARCH_FOOTBRIDGE || ARCH_RPC
+ default "mach/uncompress.h" if ARCH_RPC
default "debug/uncompress.h"
config EARLY_PRINTK
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ea3da21202c8..f5bc9ad7f6f5 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -181,7 +181,6 @@ machine-$(CONFIG_ARCH_DAVINCI) += davinci
machine-$(CONFIG_ARCH_DIGICOLOR) += digicolor
machine-$(CONFIG_ARCH_DOVE) += dove
machine-$(CONFIG_ARCH_EXYNOS) += exynos
-machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge
machine-$(CONFIG_ARCH_GEMINI) += gemini
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_HISI) += hisi
@@ -225,7 +224,6 @@ machine-$(CONFIG_PLAT_SPEAR) += spear
# legacy platforms provide their own mach/*.h headers globally,
# these three are mutually exclusive
-machdirs-$(CONFIG_ARCH_FOOTBRIDGE) += arch/arm/mach-footbridge
machdirs-$(CONFIG_ARCH_RPC) += arch/arm/mach-rpc
KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%/include,$(machdirs-y))
diff --git a/arch/arm/boot/bootp/Makefile b/arch/arm/boot/bootp/Makefile
index a1a1f4bec783..12c61684b97f 100644
--- a/arch/arm/boot/bootp/Makefile
+++ b/arch/arm/boot/bootp/Makefile
@@ -19,7 +19,6 @@ add_hex = $(shell printf 0x%x $$(( $(1) + $(2) )) )
PARAMS_PHYS := $(call add_hex, $(PHYS_OFFSET), 0x100)
# guess an initrd location if possible
-initrd_offset-$(CONFIG_ARCH_FOOTBRIDGE) += 0x00800000
initrd_offset-$(CONFIG_ARCH_RPC) += 0x08000000
INITRD_OFFSET := $(initrd_offset-y)
ifdef INITRD_OFFSET
diff --git a/arch/arm/configs/footbridge_defconfig b/arch/arm/configs/footbridge_defconfig
deleted file mode 100644
index 7fa556fb6cf4..000000000000
--- a/arch/arm/configs/footbridge_defconfig
+++ /dev/null
@@ -1,114 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_HOTPLUG is not set
-CONFIG_ARCH_MULTI_V4=y
-# CONFIG_ARCH_MULTI_V7 is not set
-CONFIG_ARCH_FOOTBRIDGE=y
-CONFIG_ARCH_EBSA285_HOST=y
-CONFIG_ARCH_NETWINDER=y
-CONFIG_ATAGS=y
-CONFIG_FPE_NWFPE=y
-CONFIG_FPE_NWFPE_XP=y
-# CONFIG_AEABI is not set
-CONFIG_MODULES=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_ACORN_PARTITION=y
-CONFIG_ACORN_PARTITION_ADFS=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_IPV6 is not set
-CONFIG_ATM=y
-CONFIG_PARPORT=y
-CONFIG_PARPORT_PC=y
-CONFIG_PARPORT_PC_FIFO=y
-CONFIG_PARPORT_1284=y
-CONFIG_PNP=y
-CONFIG_ISAPNP=y
-CONFIG_PARIDE=m
-CONFIG_PARIDE_PD=m
-CONFIG_PARIDE_PCD=m
-CONFIG_PARIDE_PF=m
-CONFIG_PARIDE_PT=m
-CONFIG_PARIDE_PG=m
-CONFIG_PARIDE_ATEN=m
-CONFIG_PARIDE_BPCK=m
-CONFIG_PARIDE_COMM=m
-CONFIG_PARIDE_DSTR=m
-CONFIG_PARIDE_FIT2=m
-CONFIG_PARIDE_FIT3=m
-CONFIG_PARIDE_EPAT=m
-CONFIG_PARIDE_EPIA=m
-CONFIG_PARIDE_FRIQ=m
-CONFIG_PARIDE_FRPW=m
-CONFIG_PARIDE_KBIC=m
-CONFIG_PARIDE_KTTI=m
-CONFIG_PARIDE_ON20=m
-CONFIG_PARIDE_ON26=m
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_VENDOR_3COM=y
-CONFIG_VORTEX=y
-CONFIG_NET_PCI=y
-CONFIG_NE2K_PCI=y
-CONFIG_PPP=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPPOE=m
-CONFIG_PPP_ASYNC=m
-CONFIG_SLIP=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_SERIAL_21285=y
-CONFIG_SERIAL_21285_CONSOLE=y
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_PRINTER=m
-CONFIG_DS1620=y
-CONFIG_NWBUTTON=y
-CONFIG_NWBUTTON_REBOOT=y
-CONFIG_NWFLASH=m
-CONFIG_I2C=m
-CONFIG_WATCHDOG=y
-CONFIG_SOFT_WATCHDOG=y
-CONFIG_21285_WATCHDOG=m
-CONFIG_977_WATCHDOG=m
-CONFIG_FB=y
-CONFIG_FB_CYBER2000=y
-CONFIG_SOUND=m
-# CONFIG_USB_HID is not set
-CONFIG_USB=m
-CONFIG_USB_MON=m
-CONFIG_USB_PRINTER=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_EXT2_FS=y
-CONFIG_AUTOFS_FS=y
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_ADFS_FS=m
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/netwinder_defconfig b/arch/arm/configs/netwinder_defconfig
deleted file mode 100644
index 77d4a2b5916b..000000000000
--- a/arch/arm/configs/netwinder_defconfig
+++ /dev/null
@@ -1,88 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EXPERT=y
-CONFIG_ARCH_MULTI_V4=y
-# CONFIG_ARCH_MULTI_V7 is not set
-CONFIG_ARCH_FOOTBRIDGE=y
-CONFIG_ARCH_NETWINDER=y
-# CONFIG_AEABI is not set
-CONFIG_ATAGS=y
-CONFIG_DEPRECATED_PARAM_STRUCT=y
-CONFIG_CMDLINE="root=0x801"
-CONFIG_FPE_NWFPE=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_PARPORT=y
-CONFIG_PARPORT_PC=y
-CONFIG_PARPORT_PC_SUPERIO=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_ATA=y
-CONFIG_PATA_WINBOND=y
-CONFIG_NETDEVICES=y
-CONFIG_MII=y
-CONFIG_NET_TULIP=y
-CONFIG_TULIP=y
-CONFIG_TULIP_MMIO=y
-CONFIG_NET_PCI=y
-CONFIG_NE2K_PCI=y
-CONFIG_MOUSE_SERIAL=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_PRINTER=y
-CONFIG_DS1620=y
-CONFIG_NWBUTTON=y
-CONFIG_NWBUTTON_REBOOT=y
-CONFIG_NWFLASH=y
-CONFIG_WATCHDOG=y
-CONFIG_977_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FB_CYBER2000=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_SOUND=y
-CONFIG_SOUND_PRIME=y
-CONFIG_SOUND_OSS=y
-CONFIG_SOUND_TRACEINIT=y
-CONFIG_SOUND_DMAP=y
-CONFIG_SOUND_YM3812=y
-CONFIG_SOUND_WAVEARTIST=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_EXT2_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=y
-CONFIG_SMB_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_852=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/include/asm/hardware/dec21285.h b/arch/arm/include/asm/hardware/dec21285.h
deleted file mode 100644
index 894f2a635cbb..000000000000
--- a/arch/arm/include/asm/hardware/dec21285.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/include/asm/hardware/dec21285.h
- *
- * Copyright (C) 1998 Russell King
- *
- * DC21285 registers
- */
-#define DC21285_PCI_IACK 0x79000000
-#define DC21285_ARMCSR_BASE 0x42000000
-#define DC21285_PCI_TYPE_0_CONFIG 0x7b000000
-#define DC21285_PCI_TYPE_1_CONFIG 0x7a000000
-#define DC21285_OUTBOUND_WRITE_FLUSH 0x78000000
-#define DC21285_FLASH 0x41000000
-#define DC21285_PCI_IO 0x7c000000
-#define DC21285_PCI_MEM 0x80000000
-
-#ifndef __ASSEMBLY__
-#include <mach/hardware.h>
-#define DC21285_IO(x) ((volatile unsigned long *)(ARMCSR_BASE+(x)))
-#else
-#define DC21285_IO(x) (x)
-#endif
-
-/*
- * The footbridge is programmed to expose the system RAM at 0xe0000000.
- * The requirement is that the RAM isn't placed at bus address 0, which
- * would clash with VGA cards.
- */
-#define BUS_OFFSET 0xe0000000
-
-#define CSR_PCICMD DC21285_IO(0x0004)
-#define CSR_CLASSREV DC21285_IO(0x0008)
-#define CSR_PCICACHELINESIZE DC21285_IO(0x000c)
-#define CSR_PCICSRBASE DC21285_IO(0x0010)
-#define CSR_PCICSRIOBASE DC21285_IO(0x0014)
-#define CSR_PCISDRAMBASE DC21285_IO(0x0018)
-#define CSR_PCIROMBASE DC21285_IO(0x0030)
-#define CSR_MBOX0 DC21285_IO(0x0050)
-#define CSR_MBOX1 DC21285_IO(0x0054)
-#define CSR_MBOX2 DC21285_IO(0x0058)
-#define CSR_MBOX3 DC21285_IO(0x005c)
-#define CSR_DOORBELL DC21285_IO(0x0060)
-#define CSR_DOORBELL_SETUP DC21285_IO(0x0064)
-#define CSR_ROMWRITEREG DC21285_IO(0x0068)
-#define CSR_CSRBASEMASK DC21285_IO(0x00f8)
-#define CSR_CSRBASEOFFSET DC21285_IO(0x00fc)
-#define CSR_SDRAMBASEMASK DC21285_IO(0x0100)
-#define CSR_SDRAMBASEOFFSET DC21285_IO(0x0104)
-#define CSR_ROMBASEMASK DC21285_IO(0x0108)
-#define CSR_SDRAMTIMING DC21285_IO(0x010c)
-#define CSR_SDRAMADDRSIZE0 DC21285_IO(0x0110)
-#define CSR_SDRAMADDRSIZE1 DC21285_IO(0x0114)
-#define CSR_SDRAMADDRSIZE2 DC21285_IO(0x0118)
-#define CSR_SDRAMADDRSIZE3 DC21285_IO(0x011c)
-#define CSR_I2O_INFREEHEAD DC21285_IO(0x0120)
-#define CSR_I2O_INPOSTTAIL DC21285_IO(0x0124)
-#define CSR_I2O_OUTPOSTHEAD DC21285_IO(0x0128)
-#define CSR_I2O_OUTFREETAIL DC21285_IO(0x012c)
-#define CSR_I2O_INFREECOUNT DC21285_IO(0x0130)
-#define CSR_I2O_OUTPOSTCOUNT DC21285_IO(0x0134)
-#define CSR_I2O_INPOSTCOUNT DC21285_IO(0x0138)
-#define CSR_SA110_CNTL DC21285_IO(0x013c)
-#define SA110_CNTL_INITCMPLETE (1 << 0)
-#define SA110_CNTL_ASSERTSERR (1 << 1)
-#define SA110_CNTL_RXSERR (1 << 3)
-#define SA110_CNTL_SA110DRAMPARITY (1 << 4)
-#define SA110_CNTL_PCISDRAMPARITY (1 << 5)
-#define SA110_CNTL_DMASDRAMPARITY (1 << 6)
-#define SA110_CNTL_DISCARDTIMER (1 << 8)
-#define SA110_CNTL_PCINRESET (1 << 9)
-#define SA110_CNTL_I2O_256 (0 << 10)
-#define SA110_CNTL_I20_512 (1 << 10)
-#define SA110_CNTL_I2O_1024 (2 << 10)
-#define SA110_CNTL_I2O_2048 (3 << 10)
-#define SA110_CNTL_I2O_4096 (4 << 10)
-#define SA110_CNTL_I2O_8192 (5 << 10)
-#define SA110_CNTL_I2O_16384 (6 << 10)
-#define SA110_CNTL_I2O_32768 (7 << 10)
-#define SA110_CNTL_WATCHDOG (1 << 13)
-#define SA110_CNTL_ROMWIDTH_UNDEF (0 << 14)
-#define SA110_CNTL_ROMWIDTH_16 (1 << 14)
-#define SA110_CNTL_ROMWIDTH_32 (2 << 14)
-#define SA110_CNTL_ROMWIDTH_8 (3 << 14)
-#define SA110_CNTL_ROMACCESSTIME(x) ((x)<<16)
-#define SA110_CNTL_ROMBURSTTIME(x) ((x)<<20)
-#define SA110_CNTL_ROMTRISTATETIME(x) ((x)<<24)
-#define SA110_CNTL_XCSDIR(x) ((x)<<28)
-#define SA110_CNTL_PCICFN (1 << 31)
-
-#define CSR_PCIADDR_EXTN DC21285_IO(0x0140)
-#define CSR_PREFETCHMEMRANGE DC21285_IO(0x0144)
-#define CSR_XBUS_CYCLE DC21285_IO(0x0148)
-#define CSR_XBUS_IOSTROBE DC21285_IO(0x014c)
-#define CSR_DOORBELL_PCI DC21285_IO(0x0150)
-#define CSR_DOORBELL_SA110 DC21285_IO(0x0154)
-#define CSR_UARTDR DC21285_IO(0x0160)
-#define CSR_RXSTAT DC21285_IO(0x0164)
-#define CSR_H_UBRLCR DC21285_IO(0x0168)
-#define CSR_M_UBRLCR DC21285_IO(0x016c)
-#define CSR_L_UBRLCR DC21285_IO(0x0170)
-#define CSR_UARTCON DC21285_IO(0x0174)
-#define CSR_UARTFLG DC21285_IO(0x0178)
-#define CSR_IRQ_STATUS DC21285_IO(0x0180)
-#define CSR_IRQ_RAWSTATUS DC21285_IO(0x0184)
-#define CSR_IRQ_ENABLE DC21285_IO(0x0188)
-#define CSR_IRQ_DISABLE DC21285_IO(0x018c)
-#define CSR_IRQ_SOFT DC21285_IO(0x0190)
-#define CSR_FIQ_STATUS DC21285_IO(0x0280)
-#define CSR_FIQ_RAWSTATUS DC21285_IO(0x0284)
-#define CSR_FIQ_ENABLE DC21285_IO(0x0288)
-#define CSR_FIQ_DISABLE DC21285_IO(0x028c)
-#define CSR_FIQ_SOFT DC21285_IO(0x0290)
-#define CSR_TIMER1_LOAD DC21285_IO(0x0300)
-#define CSR_TIMER1_VALUE DC21285_IO(0x0304)
-#define CSR_TIMER1_CNTL DC21285_IO(0x0308)
-#define CSR_TIMER1_CLR DC21285_IO(0x030c)
-#define CSR_TIMER2_LOAD DC21285_IO(0x0320)
-#define CSR_TIMER2_VALUE DC21285_IO(0x0324)
-#define CSR_TIMER2_CNTL DC21285_IO(0x0328)
-#define CSR_TIMER2_CLR DC21285_IO(0x032c)
-#define CSR_TIMER3_LOAD DC21285_IO(0x0340)
-#define CSR_TIMER3_VALUE DC21285_IO(0x0344)
-#define CSR_TIMER3_CNTL DC21285_IO(0x0348)
-#define CSR_TIMER3_CLR DC21285_IO(0x034c)
-#define CSR_TIMER4_LOAD DC21285_IO(0x0360)
-#define CSR_TIMER4_VALUE DC21285_IO(0x0364)
-#define CSR_TIMER4_CNTL DC21285_IO(0x0368)
-#define CSR_TIMER4_CLR DC21285_IO(0x036c)
-
-#define TIMER_CNTL_ENABLE (1 << 7)
-#define TIMER_CNTL_AUTORELOAD (1 << 6)
-#define TIMER_CNTL_DIV1 (0)
-#define TIMER_CNTL_DIV16 (1 << 2)
-#define TIMER_CNTL_DIV256 (2 << 2)
-#define TIMER_CNTL_CNTEXT (3 << 2)
-
-
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index ea9bd08895b7..78f2318ed000 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -61,15 +61,6 @@ static inline void pci_common_init(struct hw_pci *hw)
pci_common_init_dev(NULL, hw);
}
-/*
- * Setup early fixed I/O mapping.
- */
-#if defined(CONFIG_PCI)
-extern void pci_map_io_early(unsigned long pfn);
-#else
-static inline void pci_map_io_early(unsigned long pfn) {}
-#endif
-
/*
* PCI controllers
*/
@@ -78,9 +69,4 @@ extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
extern void iop3xx_pci_preinit(void);
extern void iop3xx_pci_preinit_cond(void);
-extern struct pci_ops dc21285_ops;
-extern int dc21285_setup(int nr, struct pci_sys_data *);
-extern void dc21285_preinit(void);
-extern void dc21285_postinit(void);
-
#endif /* __ASM_MACH_PCI_H */
diff --git a/arch/arm/include/debug/dc21285.S b/arch/arm/include/debug/dc21285.S
deleted file mode 100644
index 4ec0e5e31704..000000000000
--- a/arch/arm/include/debug/dc21285.S
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* arch/arm/mach-footbridge/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- * Copyright (C) 1994-1999 Russell King
- * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
-*/
-
-#include <asm/hardware/dec21285.h>
-
-#include <mach/hardware.h>
- /* For EBSA285 debugging */
- .equ dc21285_high, ARMCSR_BASE & 0xff000000
- .equ dc21285_low, ARMCSR_BASE & 0x00ffffff
-
- .macro addruart, rp, rv, tmp
- .if dc21285_low
- mov \rp, #dc21285_low
- .else
- mov \rp, #0
- .endif
- orr \rv, \rp, #dc21285_high
- orr \rp, \rp, #0x42000000
- .endm
-
- .macro senduart,rd,rx
- str \rd, [\rx, #0x160] @ UARTDR
- .endm
-
- .macro busyuart,rd,rx
-1001: ldr \rd, [\rx, #0x178] @ UARTFLG
- tst \rd, #1 << 3
- bne 1001b
- .endm
-
- .macro waituartcts,rd,rx
- .endm
-
- .macro waituarttxrdy,rd,rx
- .endm
diff --git a/arch/arm/kernel/atags_parse.c b/arch/arm/kernel/atags_parse.c
index 4ec591bde3df..9865ec7f90d9 100644
--- a/arch/arm/kernel/atags_parse.c
+++ b/arch/arm/kernel/atags_parse.c
@@ -69,24 +69,6 @@ static int __init parse_tag_mem32(const struct tag *tag)
__tagtable(ATAG_MEM, parse_tag_mem32);
-#if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_VGA_CONSOLE)
-static int __init parse_tag_videotext(const struct tag *tag)
-{
- vgacon_screen_info.orig_x = tag->u.videotext.x;
- vgacon_screen_info.orig_y = tag->u.videotext.y;
- vgacon_screen_info.orig_video_page = tag->u.videotext.video_page;
- vgacon_screen_info.orig_video_mode = tag->u.videotext.video_mode;
- vgacon_screen_info.orig_video_cols = tag->u.videotext.video_cols;
- vgacon_screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx;
- vgacon_screen_info.orig_video_lines = tag->u.videotext.video_lines;
- vgacon_screen_info.orig_video_isVGA = tag->u.videotext.video_isvga;
- vgacon_screen_info.orig_video_points = tag->u.videotext.video_points;
- return 0;
-}
-
-__tagtable(ATAG_VIDEOTEXT, parse_tag_videotext);
-#endif
-
#ifdef CONFIG_BLK_DEV_RAM
static int __init parse_tag_ramdisk(const struct tag *tag)
{
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index ac0e890510da..6256b75f8285 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -582,15 +582,3 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
return start;
}
-
-void __init pci_map_io_early(unsigned long pfn)
-{
- struct map_desc pci_io_desc = {
- .virtual = PCI_IO_VIRT_BASE,
- .type = MT_DEVICE,
- .length = SZ_64K,
- };
-
- pci_io_desc.pfn = pfn;
- iotable_init(&pci_io_desc, 1);
-}
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index f22c50d4bd41..b12fe41e579b 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -347,16 +347,6 @@ __create_page_tables:
/* we don't need any serial debugging mappings */
ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
#endif
-
-#if defined(CONFIG_ARCH_NETWINDER)
- /*
- * If we're using the NetWinder or CATS, we also need to map
- * in the 16550-type serial port for the debug messages
- */
- add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
- orr r3, r7, #0x7c000000
- str r3, [r0]
-#endif
#ifdef CONFIG_ARCH_RPC
/*
* Map in screen at 0x02000000 & SCREEN2_BASE
diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig
deleted file mode 100644
index 96a74d447028..000000000000
--- a/arch/arm/mach-footbridge/Kconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-menuconfig ARCH_FOOTBRIDGE
- bool "FootBridge Implementations (DEPRECATED)"
- depends on ARCH_MULTI_V4 && !(ARCH_MULTI_V4T || ARCH_MULTI_V5)
- depends on !(ARCH_MOXART || ARCH_GEMINI || ARCH_SA1100)
- depends on ATAGS
- depends on CPU_LITTLE_ENDIAN
- depends on MMU
- select ARCH_NO_SG_CHAIN
- select CPU_SA110
- select FOOTBRIDGE
- select NEED_MACH_MEMORY_H
- help
- Support for systems based on the DC21285 companion chip
- ("FootBridge"), used in the EBSA285 and the Rebel NetWinder.
-
- Support for these machines will go away in 2027,
- unless there are any remaining users that speak up.
-
-if ARCH_FOOTBRIDGE
-
-config ARCH_EBSA285_HOST
- bool "EBSA285 (host mode)"
- select ARCH_EBSA285
- select ISA
- select ARCH_MAY_HAVE_PC_FDC
- select FORCE_PCI
- help
- Say Y here if you intend to run this kernel on the EBSA285 card
- in host ("central function") mode.
-
- Saying N will reduce the size of the Footbridge kernel.
-
-config ARCH_NETWINDER
- bool "NetWinder"
- select CLKEVT_I8253
- select CLKSRC_I8253
- select ISA
- select FORCE_PCI
- help
- Say Y here if you intend to run this kernel on the Rebel.COM
- NetWinder. Information about this machine can be found at:
-
- <http://www.netwinder.org/>
-
- Saying N will reduce the size of the Footbridge kernel.
-
-# Footbridge support
-config FOOTBRIDGE
- def_bool y
- select ARCH_MIGHT_HAVE_PC_SERIO
- select ISA_DMA_API
-
-config ARCH_EBSA285
- bool
-
-endif
diff --git a/arch/arm/mach-footbridge/Makefile b/arch/arm/mach-footbridge/Makefile
deleted file mode 100644
index 1553cc01b45c..000000000000
--- a/arch/arm/mach-footbridge/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-obj-y := common.o isa-irq.o isa.o isa-rtc.o dma-isa.o
-
-pci-y += dc21285.o
-pci-$(CONFIG_ARCH_EBSA285) += ebsa285-pci.o
-pci-$(CONFIG_ARCH_NETWINDER) += netwinder-pci.o
-
-obj-$(CONFIG_ARCH_EBSA285) += ebsa285.o dc21285-timer.o
-obj-$(CONFIG_ARCH_NETWINDER) += netwinder-hw.o isa-timer.o
-
-obj-$(CONFIG_PCI) +=$(pci-y)
-
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
deleted file mode 100644
index 85c598708c10..000000000000
--- a/arch/arm/mach-footbridge/common.c
+++ /dev/null
@@ -1,280 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-footbridge/common.c
- *
- * Copyright (C) 1998-2000 Russell King, Dave Gilbert.
- */
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/ioport.h>
-#include <linux/list.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-#include <linux/dma-direct.h>
-#include <video/vga.h>
-
-#include <asm/page.h>
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <asm/setup.h>
-#include <asm/system_misc.h>
-#include <asm/hardware/dec21285.h>
-
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-#include <asm/mach/pci.h>
-
-#include "common.h"
-
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <asm/hardware/dec21285.h>
-
-static int dc21285_get_irq(void)
-{
- void __iomem *irqstatus = (void __iomem *)CSR_IRQ_STATUS;
- u32 mask = readl(irqstatus);
-
- if (mask & IRQ_MASK_SDRAMPARITY)
- return IRQ_SDRAMPARITY;
-
- if (mask & IRQ_MASK_UART_RX)
- return IRQ_CONRX;
-
- if (mask & IRQ_MASK_DMA1)
- return IRQ_DMA1;
-
- if (mask & IRQ_MASK_DMA2)
- return IRQ_DMA2;
-
- if (mask & IRQ_MASK_IN0)
- return IRQ_IN0;
-
- if (mask & IRQ_MASK_IN1)
- return IRQ_IN1;
-
- if (mask & IRQ_MASK_IN2)
- return IRQ_IN2;
-
- if (mask & IRQ_MASK_IN3)
- return IRQ_IN3;
-
- if (mask & IRQ_MASK_PCI)
- return IRQ_PCI;
-
- if (mask & IRQ_MASK_DOORBELLHOST)
- return IRQ_DOORBELLHOST;
-
- if (mask & IRQ_MASK_I2OINPOST)
- return IRQ_I2OINPOST;
-
- if (mask & IRQ_MASK_TIMER1)
- return IRQ_TIMER1;
-
- if (mask & IRQ_MASK_TIMER2)
- return IRQ_TIMER2;
-
- if (mask & IRQ_MASK_TIMER3)
- return IRQ_TIMER3;
-
- if (mask & IRQ_MASK_UART_TX)
- return IRQ_CONTX;
-
- if (mask & IRQ_MASK_PCI_ABORT)
- return IRQ_PCI_ABORT;
-
- if (mask & IRQ_MASK_PCI_SERR)
- return IRQ_PCI_SERR;
-
- if (mask & IRQ_MASK_DISCARD_TIMER)
- return IRQ_DISCARD_TIMER;
-
- if (mask & IRQ_MASK_PCI_DPERR)
- return IRQ_PCI_DPERR;
-
- if (mask & IRQ_MASK_PCI_PERR)
- return IRQ_PCI_PERR;
-
- return 0;
-}
-
-static void dc21285_handle_irq(struct pt_regs *regs)
-{
- int irq;
- do {
- irq = dc21285_get_irq();
- if (!irq)
- break;
-
- generic_handle_irq(irq);
- } while (1);
-}
-
-
-unsigned int mem_fclk_21285 = 50000000;
-
-EXPORT_SYMBOL(mem_fclk_21285);
-
-static int __init early_fclk(char *arg)
-{
- mem_fclk_21285 = simple_strtoul(arg, NULL, 0);
- return 0;
-}
-
-early_param("mem_fclk_21285", early_fclk);
-
-static int __init parse_tag_memclk(const struct tag *tag)
-{
- mem_fclk_21285 = tag->u.memclk.fmemclk;
- return 0;
-}
-
-__tagtable(ATAG_MEMCLK, parse_tag_memclk);
-
-/*
- * Footbridge IRQ translation table
- * Converts from our IRQ numbers into FootBridge masks
- */
-static const int fb_irq_mask[] = {
- IRQ_MASK_UART_RX, /* 0 */
- IRQ_MASK_UART_TX, /* 1 */
- IRQ_MASK_TIMER1, /* 2 */
- IRQ_MASK_TIMER2, /* 3 */
- IRQ_MASK_TIMER3, /* 4 */
- IRQ_MASK_IN0, /* 5 */
- IRQ_MASK_IN1, /* 6 */
- IRQ_MASK_IN2, /* 7 */
- IRQ_MASK_IN3, /* 8 */
- IRQ_MASK_DOORBELLHOST, /* 9 */
- IRQ_MASK_DMA1, /* 10 */
- IRQ_MASK_DMA2, /* 11 */
- IRQ_MASK_PCI, /* 12 */
- IRQ_MASK_SDRAMPARITY, /* 13 */
- IRQ_MASK_I2OINPOST, /* 14 */
- IRQ_MASK_PCI_ABORT, /* 15 */
- IRQ_MASK_PCI_SERR, /* 16 */
- IRQ_MASK_DISCARD_TIMER, /* 17 */
- IRQ_MASK_PCI_DPERR, /* 18 */
- IRQ_MASK_PCI_PERR, /* 19 */
-};
-
-static void fb_mask_irq(struct irq_data *d)
-{
- *CSR_IRQ_DISABLE = fb_irq_mask[_DC21285_INR(d->irq)];
-}
-
-static void fb_unmask_irq(struct irq_data *d)
-{
- *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(d->irq)];
-}
-
-static struct irq_chip fb_chip = {
- .irq_ack = fb_mask_irq,
- .irq_mask = fb_mask_irq,
- .irq_unmask = fb_unmask_irq,
-};
-
-static void __init __fb_init_irq(void)
-{
- unsigned int irq;
-
- /*
- * setup DC21285 IRQs
- */
- *CSR_IRQ_DISABLE = -1;
- *CSR_FIQ_DISABLE = -1;
-
- for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
- irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq);
- irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
- }
-}
-
-void __init footbridge_init_irq(void)
-{
- set_handle_irq(dc21285_handle_irq);
-
- __fb_init_irq();
-
- if (machine_is_ebsa285())
- /* The following is dependent on which slot
- * you plug the Southbridge card into. We
- * currently assume that you plug it into
- * the right-hand most slot.
- */
- isa_init_irq(IRQ_PCI);
-
- if (machine_is_netwinder())
- isa_init_irq(IRQ_IN3);
-}
-
-/*
- * Common mapping for all systems. Note that the outbound write flush is
- * commented out since there is a "No Fix" problem with it. Not mapping
- * it means that we have extra bullet protection on our feet.
- */
-static struct map_desc ebsa285_host_io_desc[] __initdata = {
- {
- .virtual = ARMCSR_BASE,
- .pfn = __phys_to_pfn(DC21285_ARMCSR_BASE),
- .length = ARMCSR_SIZE,
- .type = MT_DEVICE,
- },
- {
- .virtual = PCIMEM_BASE,
- .pfn = __phys_to_pfn(DC21285_PCI_MEM),
- .length = PCIMEM_SIZE,
- .type = MT_DEVICE,
- }, {
- .virtual = PCICFG0_BASE,
- .pfn = __phys_to_pfn(DC21285_PCI_TYPE_0_CONFIG),
- .length = PCICFG0_SIZE,
- .type = MT_DEVICE,
- }, {
- .virtual = PCICFG1_BASE,
- .pfn = __phys_to_pfn(DC21285_PCI_TYPE_1_CONFIG),
- .length = PCICFG1_SIZE,
- .type = MT_DEVICE,
- }, {
- .virtual = PCIIACK_BASE,
- .pfn = __phys_to_pfn(DC21285_PCI_IACK),
- .length = PCIIACK_SIZE,
- .type = MT_DEVICE,
- },
-};
-
-void __init footbridge_map_io(void)
-{
- iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
- pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
- vga_base = PCIMEM_BASE;
-}
-
-void footbridge_restart(enum reboot_mode mode, const char *cmd)
-{
- if (mode == REBOOT_SOFT) {
- /* Jump into the ROM */
- soft_restart(0x41000000);
- } else {
- /*
- * Force the watchdog to do a CPU reset.
- *
- * After making sure that the watchdog is disabled
- * (so we can change the timer registers) we first
- * enable the timer to autoreload itself. Next, the
- * timer interval is set really short and any
- * current interrupt request is cleared (so we can
- * see an edge transition). Finally, TIMER4 is
- * enabled as the watchdog.
- */
- *CSR_SA110_CNTL &= ~(1 << 13);
- *CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE |
- TIMER_CNTL_AUTORELOAD |
- TIMER_CNTL_DIV16;
- *CSR_TIMER4_LOAD = 0x2;
- *CSR_TIMER4_CLR = 0;
- *CSR_SA110_CNTL |= (1 << 13);
- }
-}
diff --git a/arch/arm/mach-footbridge/common.h b/arch/arm/mach-footbridge/common.h
deleted file mode 100644
index e12587db59c4..000000000000
--- a/arch/arm/mach-footbridge/common.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include <linux/reboot.h>
-
-extern void footbridge_timer_init(void);
-extern void isa_timer_init(void);
-
-extern void isa_rtc_init(void);
-
-extern void footbridge_map_io(void);
-extern void footbridge_init_irq(void);
-
-extern void isa_init_irq(unsigned int irq);
-extern void footbridge_restart(enum reboot_mode, const char *);
-
-extern void footbridge_sched_clock(void);
diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c
deleted file mode 100644
index 2908c9ef3c9b..000000000000
--- a/arch/arm/mach-footbridge/dc21285-timer.c
+++ /dev/null
@@ -1,136 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/arm/mach-footbridge/dc21285-timer.c
- *
- * Copyright (C) 1998 Russell King.
- * Copyright (C) 1998 Phil Blundell
- */
-#include <linux/clockchips.h>
-#include <linux/clocksource.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/sched_clock.h>
-
-#include <asm/irq.h>
-
-#include <asm/hardware/dec21285.h>
-#include <asm/mach/time.h>
-#include <asm/system_info.h>
-
-#include "common.h"
-
-static u64 cksrc_dc21285_read(struct clocksource *cs)
-{
- return cs->mask - *CSR_TIMER2_VALUE;
-}
-
-static int cksrc_dc21285_enable(struct clocksource *cs)
-{
- *CSR_TIMER2_LOAD = cs->mask;
- *CSR_TIMER2_CLR = 0;
- *CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
- return 0;
-}
-
-static void cksrc_dc21285_disable(struct clocksource *cs)
-{
- *CSR_TIMER2_CNTL = 0;
-}
-
-static struct clocksource cksrc_dc21285 = {
- .name = "dc21285_timer2",
- .rating = 200,
- .read = cksrc_dc21285_read,
- .enable = cksrc_dc21285_enable,
- .disable = cksrc_dc21285_disable,
- .mask = CLOCKSOURCE_MASK(24),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static int ckevt_dc21285_set_next_event(unsigned long delta,
- struct clock_event_device *c)
-{
- *CSR_TIMER1_CLR = 0;
- *CSR_TIMER1_LOAD = delta;
- *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
-
- return 0;
-}
-
-static int ckevt_dc21285_shutdown(struct clock_event_device *c)
-{
- *CSR_TIMER1_CNTL = 0;
- return 0;
-}
-
-static int ckevt_dc21285_set_periodic(struct clock_event_device *c)
-{
- *CSR_TIMER1_CLR = 0;
- *CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
- *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD |
- TIMER_CNTL_DIV16;
- return 0;
-}
-
-static struct clock_event_device ckevt_dc21285 = {
- .name = "dc21285_timer1",
- .features = CLOCK_EVT_FEAT_PERIODIC |
- CLOCK_EVT_FEAT_ONESHOT,
- .rating = 200,
- .irq = IRQ_TIMER1,
- .set_next_event = ckevt_dc21285_set_next_event,
- .set_state_shutdown = ckevt_dc21285_shutdown,
- .set_state_periodic = ckevt_dc21285_set_periodic,
- .set_state_oneshot = ckevt_dc21285_shutdown,
- .tick_resume = ckevt_dc21285_set_periodic,
-};
-
-static irqreturn_t timer1_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *ce = dev_id;
-
- *CSR_TIMER1_CLR = 0;
-
- /* Stop the timer if in one-shot mode */
- if (clockevent_state_oneshot(ce))
- *CSR_TIMER1_CNTL = 0;
-
- ce->event_handler(ce);
-
- return IRQ_HANDLED;
-}
-
-/*
- * Set up timer interrupt.
- */
-void __init footbridge_timer_init(void)
-{
- struct clock_event_device *ce = &ckevt_dc21285;
- unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
-
- clocksource_register_hz(&cksrc_dc21285, rate);
-
- if (request_irq(ce->irq, timer1_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
- "dc21285_timer1", &ckevt_dc21285))
- pr_err("Failed to request irq %d (dc21285_timer1)", ce->irq);
-
- ce->cpumask = cpumask_of(smp_processor_id());
- clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
-}
-
-static u64 notrace footbridge_read_sched_clock(void)
-{
- return ~*CSR_TIMER3_VALUE;
-}
-
-void __init footbridge_sched_clock(void)
-{
- unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
-
- *CSR_TIMER3_LOAD = 0;
- *CSR_TIMER3_CLR = 0;
- *CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
-
- sched_clock_register(footbridge_read_sched_clock, 24, rate);
-}
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
deleted file mode 100644
index e1b336624883..000000000000
--- a/arch/arm/mach-footbridge/dc21285.c
+++ /dev/null
@@ -1,360 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/kernel/dec21285.c: PCI functions for DC21285
- *
- * Copyright (C) 1998-2001 Russell King
- * Copyright (C) 1998-2000 Phil Blundell
- */
-#include <linux/dma-map-ops.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/interrupt.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-
-#include <asm/irq.h>
-#include <asm/mach/pci.h>
-#include <asm/hardware/dec21285.h>
-
-#define MAX_SLOTS 21
-
-#define PCICMD_ABORT ((PCI_STATUS_REC_MASTER_ABORT| \
- PCI_STATUS_REC_TARGET_ABORT)<<16)
-
-#define PCICMD_ERROR_BITS ((PCI_STATUS_DETECTED_PARITY | \
- PCI_STATUS_REC_MASTER_ABORT | \
- PCI_STATUS_REC_TARGET_ABORT | \
- PCI_STATUS_PARITY) << 16)
-
-extern int setup_arm_irq(int, struct irqaction *);
-
-static unsigned long
-dc21285_base_address(struct pci_bus *bus, unsigned int devfn)
-{
- unsigned long addr = 0;
-
- if (bus->number == 0) {
- if (PCI_SLOT(devfn) == 0)
- /*
- * For devfn 0, point at the 21285
- */
- addr = ARMCSR_BASE;
- else {
- devfn -= 1 << 3;
-
- if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
- addr = PCICFG0_BASE | 0xc00000 | (devfn << 8);
- }
- } else
- addr = PCICFG1_BASE | (bus->number << 16) | (devfn << 8);
-
- return addr;
-}
-
-static int
-dc21285_read_config(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 *value)
-{
- unsigned long addr = dc21285_base_address(bus, devfn);
- u32 v = 0xffffffff;
-
- if (addr)
- switch (size) {
- case 1:
- asm volatile("ldrb %0, [%1, %2]"
- : "=r" (v) : "r" (addr), "r" (where) : "cc");
- break;
- case 2:
- asm volatile("ldrh %0, [%1, %2]"
- : "=r" (v) : "r" (addr), "r" (where) : "cc");
- break;
- case 4:
- asm volatile("ldr %0, [%1, %2]"
- : "=r" (v) : "r" (addr), "r" (where) : "cc");
- break;
- }
-
- *value = v;
-
- v = *CSR_PCICMD;
- if (v & PCICMD_ABORT) {
- *CSR_PCICMD = v & (0xffff|PCICMD_ABORT);
- return -1;
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-dc21285_write_config(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 value)
-{
- unsigned long addr = dc21285_base_address(bus, devfn);
- u32 v;
-
- if (addr)
- switch (size) {
- case 1:
- asm volatile("strb %0, [%1, %2]"
- : : "r" (value), "r" (addr), "r" (where)
- : "cc");
- break;
- case 2:
- asm volatile("strh %0, [%1, %2]"
- : : "r" (value), "r" (addr), "r" (where)
- : "cc");
- break;
- case 4:
- asm volatile("str %0, [%1, %2]"
- : : "r" (value), "r" (addr), "r" (where)
- : "cc");
- break;
- }
-
- v = *CSR_PCICMD;
- if (v & PCICMD_ABORT) {
- *CSR_PCICMD = v & (0xffff|PCICMD_ABORT);
- return -1;
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-struct pci_ops dc21285_ops = {
- .read = dc21285_read_config,
- .write = dc21285_write_config,
-};
-
-static struct timer_list serr_timer;
-static struct timer_list perr_timer;
-
-static void dc21285_enable_error(struct timer_list *timer)
-{
- timer_delete(timer);
-
- if (timer == &serr_timer)
- enable_irq(IRQ_PCI_SERR);
- else if (timer == &perr_timer)
- enable_irq(IRQ_PCI_PERR);
-}
-
-/*
- * Warn on PCI errors.
- */
-static irqreturn_t dc21285_abort_irq(int irq, void *dev_id)
-{
- unsigned int cmd;
- unsigned int status;
-
- cmd = *CSR_PCICMD;
- status = cmd >> 16;
- cmd = cmd & 0xffff;
-
- if (status & PCI_STATUS_REC_MASTER_ABORT) {
- printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n",
- instruction_pointer(get_irq_regs()));
- cmd |= PCI_STATUS_REC_MASTER_ABORT << 16;
- }
-
- if (status & PCI_STATUS_REC_TARGET_ABORT) {
- printk(KERN_DEBUG "PCI: target abort: ");
- pcibios_report_status(PCI_STATUS_REC_MASTER_ABORT |
- PCI_STATUS_SIG_TARGET_ABORT |
- PCI_STATUS_REC_TARGET_ABORT, 1);
- printk("\n");
-
- cmd |= PCI_STATUS_REC_TARGET_ABORT << 16;
- }
-
- *CSR_PCICMD = cmd;
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t dc21285_serr_irq(int irq, void *dev_id)
-{
- struct timer_list *timer = dev_id;
- unsigned int cntl;
-
- printk(KERN_DEBUG "PCI: system error received: ");
- pcibios_report_status(PCI_STATUS_SIG_SYSTEM_ERROR, 1);
- printk("\n");
-
- cntl = *CSR_SA110_CNTL & 0xffffdf07;
- *CSR_SA110_CNTL = cntl | SA110_CNTL_RXSERR;
-
- /*
- * back off this interrupt
- */
- disable_irq(irq);
- timer->expires = jiffies + HZ;
- add_timer(timer);
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t dc21285_discard_irq(int irq, void *dev_id)
-{
- printk(KERN_DEBUG "PCI: discard timer expired\n");
- *CSR_SA110_CNTL &= 0xffffde07;
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t dc21285_dparity_irq(int irq, void *dev_id)
-{
- unsigned int cmd;
-
- printk(KERN_DEBUG "PCI: data parity error detected: ");
- pcibios_report_status(PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY, 1);
- printk("\n");
-
- cmd = *CSR_PCICMD & 0xffff;
- *CSR_PCICMD = cmd | 1 << 24;
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t dc21285_parity_irq(int irq, void *dev_id)
-{
- struct timer_list *timer = dev_id;
- unsigned int cmd;
-
- printk(KERN_DEBUG "PCI: parity error detected: ");
- pcibios_report_status(PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY, 1);
- printk("\n");
-
- cmd = *CSR_PCICMD & 0xffff;
- *CSR_PCICMD = cmd | 1 << 31;
-
- /*
- * back off this interrupt
- */
- disable_irq(irq);
- timer->expires = jiffies + HZ;
- add_timer(timer);
-
- return IRQ_HANDLED;
-}
-
-static int dc21285_pci_bus_notifier(struct notifier_block *nb,
- unsigned long action,
- void *data)
-{
- if (action != BUS_NOTIFY_ADD_DEVICE)
- return NOTIFY_DONE;
-
- dma_direct_set_offset(data, PHYS_OFFSET, BUS_OFFSET, SZ_256M);
-
- return NOTIFY_OK;
-}
-
-static struct notifier_block dc21285_pci_bus_nb = {
- .notifier_call = dc21285_pci_bus_notifier,
-};
-
-int __init dc21285_setup(int nr, struct pci_sys_data *sys)
-{
- struct resource *res;
-
- res = kzalloc_objs(struct resource, 2);
- if (!res) {
- printk("out of memory for root bus resources");
- return 0;
- }
-
- res[0].flags = IORESOURCE_MEM;
- res[0].name = "Footbridge non-prefetch";
- res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
- res[1].name = "Footbridge prefetch";
-
- allocate_resource(&iomem_resource, &res[1], 0x20000000,
- 0xa0000000, 0xffffffff, 0x20000000, NULL, NULL);
- allocate_resource(&iomem_resource, &res[0], 0x40000000,
- 0x80000000, 0xffffffff, 0x40000000, NULL, NULL);
-
- sys->mem_offset = DC21285_PCI_MEM;
-
- pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset);
- pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
-
- bus_register_notifier(&pci_bus_type, &dc21285_pci_bus_nb);
-
- return 1;
-}
-
-#define dc21285_request_irq(_a, _b, _c, _d, _e) \
- WARN_ON(request_irq(_a, _b, _c, _d, _e) < 0)
-
-void __init dc21285_preinit(void)
-{
- unsigned int mem_size, mem_mask;
-
- pcibios_min_mem = 0x81000000;
-
- mem_size = (unsigned int)high_memory - PAGE_OFFSET;
- for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
- if (mem_mask >= mem_size)
- break;
-
- /*
- * These registers need to be set up whether we're the
- * central function or not.
- */
- *CSR_SDRAMBASEMASK = (mem_mask - 1) & 0x0ffc0000;
- *CSR_SDRAMBASEOFFSET = 0;
- *CSR_ROMBASEMASK = 0x80000000;
- *CSR_CSRBASEMASK = 0;
- *CSR_CSRBASEOFFSET = 0;
- *CSR_PCIADDR_EXTN = 0;
-
- printk(KERN_INFO "PCI: DC21285 footbridge, revision %02lX, in "
- "central function mode\n", *CSR_CLASSREV & 0xff);
-
- /*
- * Clear any existing errors - we aren't
- * interested in historical data...
- */
- *CSR_SA110_CNTL = (*CSR_SA110_CNTL & 0xffffde07) | SA110_CNTL_RXSERR;
- *CSR_PCICMD = (*CSR_PCICMD & 0xffff) | PCICMD_ERROR_BITS;
-
- timer_setup(&serr_timer, dc21285_enable_error, 0);
- timer_setup(&perr_timer, dc21285_enable_error, 0);
-
- /*
- * We don't care if these fail.
- */
- dc21285_request_irq(IRQ_PCI_SERR, dc21285_serr_irq, 0,
- "PCI system error", &serr_timer);
- dc21285_request_irq(IRQ_PCI_PERR, dc21285_parity_irq, 0,
- "PCI parity error", &perr_timer);
- dc21285_request_irq(IRQ_PCI_ABORT, dc21285_abort_irq, 0,
- "PCI abort", NULL);
- dc21285_request_irq(IRQ_DISCARD_TIMER, dc21285_discard_irq, 0,
- "Discard timer", NULL);
- dc21285_request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, 0,
- "PCI data parity", NULL);
-
- /*
- * Map our SDRAM at a known address in PCI space, just in case
- * the firmware had other ideas. Using a nonzero base is
- * necessary, since some VGA cards forcefully use PCI addresses
- * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
- */
- *CSR_PCICSRBASE = 0xf4000000;
- *CSR_PCICSRIOBASE = 0;
- *CSR_PCISDRAMBASE = BUS_OFFSET;
- *CSR_PCIROMBASE = 0;
- *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
- PCI_COMMAND_INVALIDATE | PCICMD_ERROR_BITS;
-}
-
-void __init dc21285_postinit(void)
-{
- register_isa_ports(DC21285_PCI_MEM, DC21285_PCI_IO, 0);
-}
diff --git a/arch/arm/mach-footbridge/dma-isa.c b/arch/arm/mach-footbridge/dma-isa.c
deleted file mode 100644
index 937f5376d5e7..000000000000
--- a/arch/arm/mach-footbridge/dma-isa.c
+++ /dev/null
@@ -1,230 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 1999-2000 Russell King
- *
- * ISA DMA primitives
- * Taken from various sources, including:
- * linux/include/asm/dma.h: Defines for using and allocating dma channels.
- * Written by Hennus Bergman, 1992.
- * High DMA channel support & info by Hannu Savolainen and John Boyd,
- * Nov. 1992.
- * arch/arm/kernel/dma-ebsa285.c
- * Copyright (C) 1998 Phil Blundell
- */
-#include <linux/dma-map-ops.h>
-#include <linux/ioport.h>
-#include <linux/init.h>
-#include <linux/dma-mapping.h>
-#include <linux/io.h>
-
-#include <asm/dma.h>
-#include <asm/mach/dma.h>
-#include <asm/hardware/dec21285.h>
-
-#define ISA_DMA_MASK 0
-#define ISA_DMA_MODE 1
-#define ISA_DMA_CLRFF 2
-#define ISA_DMA_PGHI 3
-#define ISA_DMA_PGLO 4
-#define ISA_DMA_ADDR 5
-#define ISA_DMA_COUNT 6
-
-static unsigned int isa_dma_port[8][7] = {
- /* MASK MODE CLRFF PAGE_HI PAGE_LO ADDR COUNT */
- { 0x0a, 0x0b, 0x0c, 0x487, 0x087, 0x00, 0x01 },
- { 0x0a, 0x0b, 0x0c, 0x483, 0x083, 0x02, 0x03 },
- { 0x0a, 0x0b, 0x0c, 0x481, 0x081, 0x04, 0x05 },
- { 0x0a, 0x0b, 0x0c, 0x482, 0x082, 0x06, 0x07 },
- { 0xd4, 0xd6, 0xd8, 0x000, 0x000, 0xc0, 0xc2 },
- { 0xd4, 0xd6, 0xd8, 0x48b, 0x08b, 0xc4, 0xc6 },
- { 0xd4, 0xd6, 0xd8, 0x489, 0x089, 0xc8, 0xca },
- { 0xd4, 0xd6, 0xd8, 0x48a, 0x08a, 0xcc, 0xce }
-};
-
-static int isa_get_dma_residue(unsigned int chan, dma_t *dma)
-{
- unsigned int io_port = isa_dma_port[chan][ISA_DMA_COUNT];
- int count;
-
- count = 1 + inb(io_port);
- count |= inb(io_port) << 8;
-
- return chan < 4 ? count : (count << 1);
-}
-
-static struct device isa_dma_dev = {
- .init_name = "fallback device",
- .coherent_dma_mask = ~(dma_addr_t)0,
- .dma_mask = &isa_dma_dev.coherent_dma_mask,
-};
-
-static void isa_enable_dma(unsigned int chan, dma_t *dma)
-{
- if (dma->invalid) {
- unsigned long address, length;
- unsigned int mode;
- enum dma_data_direction direction;
-
- mode = (chan & 3) | dma->dma_mode;
- switch (dma->dma_mode & DMA_MODE_MASK) {
- case DMA_MODE_READ:
- direction = DMA_FROM_DEVICE;
- break;
-
- case DMA_MODE_WRITE:
- direction = DMA_TO_DEVICE;
- break;
-
- case DMA_MODE_CASCADE:
- direction = DMA_BIDIRECTIONAL;
- break;
-
- default:
- direction = DMA_NONE;
- break;
- }
-
- if (!dma->sg) {
- /*
- * Cope with ISA-style drivers which expect cache
- * coherence.
- */
- dma->sg = &dma->buf;
- dma->sgcount = 1;
- dma->buf.length = dma->count;
- dma->buf.dma_address = dma_map_single(&isa_dma_dev,
- dma->addr, dma->count,
- direction);
- }
-
- address = dma->buf.dma_address;
- length = dma->buf.length - 1;
-
- outb(address >> 16, isa_dma_port[chan][ISA_DMA_PGLO]);
- outb(address >> 24, isa_dma_port[chan][ISA_DMA_PGHI]);
-
- if (chan >= 4) {
- address >>= 1;
- length >>= 1;
- }
-
- outb(0, isa_dma_port[chan][ISA_DMA_CLRFF]);
-
- outb(address, isa_dma_port[chan][ISA_DMA_ADDR]);
- outb(address >> 8, isa_dma_port[chan][ISA_DMA_ADDR]);
-
- outb(length, isa_dma_port[chan][ISA_DMA_COUNT]);
- outb(length >> 8, isa_dma_port[chan][ISA_DMA_COUNT]);
-
- outb(mode, isa_dma_port[chan][ISA_DMA_MODE]);
- dma->invalid = 0;
- }
- outb(chan & 3, isa_dma_port[chan][ISA_DMA_MASK]);
-}
-
-static void isa_disable_dma(unsigned int chan, dma_t *dma)
-{
- outb(chan | 4, isa_dma_port[chan][ISA_DMA_MASK]);
-}
-
-static struct dma_ops isa_dma_ops = {
- .type = "ISA",
- .enable = isa_enable_dma,
- .disable = isa_disable_dma,
- .residue = isa_get_dma_residue,
-};
-
-static struct resource dma_resources[] = { {
- .name = "dma1",
- .start = 0x0000,
- .end = 0x000f
-}, {
- .name = "dma low page",
- .start = 0x0080,
- .end = 0x008f
-}, {
- .name = "dma2",
- .start = 0x00c0,
- .end = 0x00df
-}, {
- .name = "dma high page",
- .start = 0x0480,
- .end = 0x048f
-} };
-
-static dma_t isa_dma[8];
-
-/*
- * ISA DMA always starts at channel 0
- */
-static int __init isa_dma_init(void)
-{
- /*
- * Try to autodetect presence of an ISA DMA controller.
- * We do some minimal initialisation, and check that
- * channel 0's DMA address registers are writeable.
- */
- outb(0xff, 0x0d);
- outb(0xff, 0xda);
-
- /*
- * Write high and low address, and then read them back
- * in the same order.
- */
- outb(0x55, 0x00);
- outb(0xaa, 0x00);
-
- if (inb(0) == 0x55 && inb(0) == 0xaa) {
- unsigned int chan, i;
-
- for (chan = 0; chan < 8; chan++) {
- isa_dma[chan].d_ops = &isa_dma_ops;
- isa_disable_dma(chan, NULL);
- }
-
- outb(0x40, 0x0b);
- outb(0x41, 0x0b);
- outb(0x42, 0x0b);
- outb(0x43, 0x0b);
-
- outb(0xc0, 0xd6);
- outb(0x41, 0xd6);
- outb(0x42, 0xd6);
- outb(0x43, 0xd6);
-
- outb(0, 0xd4);
-
- outb(0x10, 0x08);
- outb(0x10, 0xd0);
-
- /*
- * Is this correct? According to my documentation, it
- * doesn't appear to be. It should be:
- * outb(0x3f, 0x40b); outb(0x3f, 0x4d6);
- */
- outb(0x30, 0x40b);
- outb(0x31, 0x40b);
- outb(0x32, 0x40b);
- outb(0x33, 0x40b);
- outb(0x31, 0x4d6);
- outb(0x32, 0x4d6);
- outb(0x33, 0x4d6);
-
- for (i = 0; i < ARRAY_SIZE(dma_resources); i++)
- request_resource(&ioport_resource, dma_resources + i);
-
- for (chan = 0; chan < 8; chan++) {
- int ret = isa_dma_add(chan, &isa_dma[chan]);
- if (ret)
- pr_err("ISADMA%u: unable to register: %d\n",
- chan, ret);
- }
-
- request_dma(DMA_ISA_CASCADE, "cascade");
- }
-
- dma_direct_set_offset(&isa_dma_dev, PHYS_OFFSET, BUS_OFFSET, SZ_256M);
-
- return 0;
-}
-core_initcall(isa_dma_init);
diff --git a/arch/arm/mach-footbridge/ebsa285-pci.c b/arch/arm/mach-footbridge/ebsa285-pci.c
deleted file mode 100644
index c3f280d08fa7..000000000000
--- a/arch/arm/mach-footbridge/ebsa285-pci.c
+++ /dev/null
@@ -1,48 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/arm/mach-footbridge/ebsa285-pci.c
- *
- * PCI bios-type initialisation for PCI machines
- *
- * Bits taken from various places.
- */
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-
-#include <asm/irq.h>
-#include <asm/mach/pci.h>
-#include <asm/mach-types.h>
-
-static int irqmap_ebsa285[] = { IRQ_IN3, IRQ_IN1, IRQ_IN0, IRQ_PCI };
-
-static int ebsa285_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- if (dev->vendor == PCI_VENDOR_ID_CONTAQ &&
- dev->device == PCI_DEVICE_ID_CONTAQ_82C693)
- switch (PCI_FUNC(dev->devfn)) {
- case 1: return 14;
- case 2: return 15;
- case 3: return 12;
- }
-
- return irqmap_ebsa285[(slot + pin) & 3];
-}
-
-static struct hw_pci ebsa285_pci __initdata = {
- .map_irq = ebsa285_map_irq,
- .nr_controllers = 1,
- .ops = &dc21285_ops,
- .setup = dc21285_setup,
- .preinit = dc21285_preinit,
- .postinit = dc21285_postinit,
-};
-
-static int __init ebsa285_init_pci(void)
-{
- if (machine_is_ebsa285())
- pci_common_init(&ebsa285_pci);
- return 0;
-}
-
-subsys_initcall(ebsa285_init_pci);
diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c
deleted file mode 100644
index 1cb7d674bc81..000000000000
--- a/arch/arm/mach-footbridge/ebsa285.c
+++ /dev/null
@@ -1,124 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/arm/mach-footbridge/ebsa285.c
- *
- * EBSA285 machine fixup
- */
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-#include <linux/slab.h>
-#include <linux/leds.h>
-
-#include <asm/hardware/dec21285.h>
-#include <asm/mach-types.h>
-
-#include <asm/mach/arch.h>
-
-#include "common.h"
-
-/* LEDs */
-#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
-#define XBUS_AMBER_L BIT(0)
-#define XBUS_GREEN_L BIT(1)
-#define XBUS_RED_L BIT(2)
-#define XBUS_TOGGLE BIT(7)
-
-struct ebsa285_led {
- struct led_classdev cdev;
- u8 mask;
-};
-
-/*
- * The triggers lines up below will only be used if the
- * LED triggers are compiled in.
- */
-static const struct {
- const char *name;
- const char *trigger;
-} ebsa285_leds[] = {
- { "ebsa285:amber", "cpu0", },
- { "ebsa285:green", "heartbeat", },
- { "ebsa285:red",},
-};
-
-static unsigned char hw_led_state;
-static void __iomem *xbus;
-
-static void ebsa285_led_set(struct led_classdev *cdev,
- enum led_brightness b)
-{
- struct ebsa285_led *led = container_of(cdev,
- struct ebsa285_led, cdev);
-
- if (b == LED_OFF)
- hw_led_state |= led->mask;
- else
- hw_led_state &= ~led->mask;
- writeb(hw_led_state, xbus);
-}
-
-static enum led_brightness ebsa285_led_get(struct led_classdev *cdev)
-{
- struct ebsa285_led *led = container_of(cdev,
- struct ebsa285_led, cdev);
-
- return hw_led_state & led->mask ? LED_OFF : LED_FULL;
-}
-
-static int __init ebsa285_leds_init(void)
-{
- int i;
-
- if (!machine_is_ebsa285())
- return -ENODEV;
-
- xbus = ioremap(XBUS_CS2, SZ_4K);
- if (!xbus)
- return -ENOMEM;
-
- /* 3 LEDS all off */
- hw_led_state = XBUS_AMBER_L | XBUS_GREEN_L | XBUS_RED_L;
- writeb(hw_led_state, xbus);
-
- for (i = 0; i < ARRAY_SIZE(ebsa285_leds); i++) {
- struct ebsa285_led *led;
-
- led = kzalloc_obj(*led);
- if (!led)
- break;
-
- led->cdev.name = ebsa285_leds[i].name;
- led->cdev.brightness_set = ebsa285_led_set;
- led->cdev.brightness_get = ebsa285_led_get;
- led->cdev.default_trigger = ebsa285_leds[i].trigger;
- led->mask = BIT(i);
-
- if (led_classdev_register(NULL, &led->cdev) < 0) {
- kfree(led);
- break;
- }
- }
-
- return 0;
-}
-
-/*
- * Since we may have triggers on any subsystem, defer registration
- * until after subsystem_init.
- */
-fs_initcall(ebsa285_leds_init);
-#endif
-
-MACHINE_START(EBSA285, "EBSA285")
- /* Maintainer: Russell King */
- .atag_offset = 0x100,
- .video_start = 0x000a0000,
- .video_end = 0x000bffff,
- .map_io = footbridge_map_io,
- .init_early = footbridge_sched_clock,
- .init_irq = footbridge_init_irq,
- .init_time = footbridge_timer_init,
- .restart = footbridge_restart,
-MACHINE_END
-
diff --git a/arch/arm/mach-footbridge/include/mach/hardware.h b/arch/arm/mach-footbridge/include/mach/hardware.h
deleted file mode 100644
index 985ad3a95671..000000000000
--- a/arch/arm/mach-footbridge/include/mach/hardware.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-footbridge/include/mach/hardware.h
- *
- * Copyright (C) 1998-1999 Russell King.
- *
- * This file contains the hardware definitions of the EBSA-285.
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/* Virtual Physical Size
- * 0xff800000 0x40000000 1MB X-Bus
- * 0xff000000 0x7c000000 1MB PCI I/O space
- * 0xfe000000 0x42000000 1MB CSR
- * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
- * 0xfc000000 0x79000000 1MB PCI IACK/special space
- * 0xfb000000 0x7a000000 16MB PCI Config type 1
- * 0xfa000000 0x7b000000 16MB PCI Config type 0
- * 0xf9000000 0x50000000 1MB Cache flush
- * 0xf0000000 0x80000000 16MB ISA memory
- */
-
-#define XBUS_SIZE 0x00100000
-#define XBUS_BASE 0xff800000
-
-#define ARMCSR_SIZE 0x00100000
-#define ARMCSR_BASE 0xfe000000
-
-#define WFLUSH_SIZE 0x00100000
-#define WFLUSH_BASE 0xfd000000
-
-#define PCIIACK_SIZE 0x00100000
-#define PCIIACK_BASE 0xfc000000
-
-#define PCICFG1_SIZE 0x01000000
-#define PCICFG1_BASE 0xfb000000
-
-#define PCICFG0_SIZE 0x01000000
-#define PCICFG0_BASE 0xfa000000
-
-#define PCIMEM_SIZE 0x01000000
-#define PCIMEM_BASE 0xf0000000
-
-#define XBUS_CS2 0x40012000
-
-#define XBUS_SWITCH ((volatile unsigned char *)(XBUS_BASE + 0x12000))
-#define XBUS_SWITCH_SWITCH ((*XBUS_SWITCH) & 15)
-#define XBUS_SWITCH_J17_13 ((*XBUS_SWITCH) & (1 << 4))
-#define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5))
-#define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6))
-
-#define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108) /* CSR_ROMBASEMASK */
-
-
-/* PIC irq control */
-#define PIC_LO 0x20
-#define PIC_MASK_LO 0x21
-#define PIC_HI 0xA0
-#define PIC_MASK_HI 0xA1
-
-/* GPIO pins */
-#define GPIO_CCLK 0x800
-#define GPIO_DSCLK 0x400
-#define GPIO_E2CLK 0x200
-#define GPIO_IOLOAD 0x100
-#define GPIO_RED_LED 0x080
-#define GPIO_WDTIMER 0x040
-#define GPIO_DATA 0x020
-#define GPIO_IOCLK 0x010
-#define GPIO_DONE 0x008
-#define GPIO_FAN 0x004
-#define GPIO_GREEN_LED 0x002
-#define GPIO_RESET 0x001
-
-/* CPLD pins */
-#define CPLD_DS_ENABLE 8
-#define CPLD_7111_DISABLE 4
-#define CPLD_UNMUTE 2
-#define CPLD_FLASH_WR_ENABLE 1
-
-#ifndef __ASSEMBLY__
-extern raw_spinlock_t nw_gpio_lock;
-extern void nw_gpio_modify_op(unsigned int mask, unsigned int set);
-extern void nw_gpio_modify_io(unsigned int mask, unsigned int in);
-extern unsigned int nw_gpio_read(void);
-extern void nw_cpld_modify(unsigned int mask, unsigned int set);
-#endif
-
-#endif
diff --git a/arch/arm/mach-footbridge/include/mach/irqs.h b/arch/arm/mach-footbridge/include/mach/irqs.h
deleted file mode 100644
index a5f41846ab9c..000000000000
--- a/arch/arm/mach-footbridge/include/mach/irqs.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/mach-footbridge/include/mach/irqs.h
- *
- * Copyright (C) 1998 Russell King
- * Copyright (C) 1998 Phil Blundell
- *
- * Changelog:
- * 20-Jan-1998 RMK Started merge of EBSA286, CATS and NetWinder
- * 01-Feb-1999 PJB ISA IRQs start at 0 not 16
- */
-#include <asm/mach-types.h>
-
-#define NR_IRQS 36
-#define NR_DC21285_IRQS 16
-
-#define _ISA_IRQ(x) (0 + (x))
-#define _ISA_INR(x) ((x) - 0)
-#define _DC21285_IRQ(x) (16 + (x))
-#define _DC21285_INR(x) ((x) - 16)
-
-/*
- * This is a list of all interrupts that the 21285
- * can generate and we handle.
- */
-#define IRQ_CONRX _DC21285_IRQ(0)
-#define IRQ_CONTX _DC21285_IRQ(1)
-#define IRQ_TIMER1 _DC21285_IRQ(2)
-#define IRQ_TIMER2 _DC21285_IRQ(3)
-#define IRQ_TIMER3 _DC21285_IRQ(4)
-#define IRQ_IN0 _DC21285_IRQ(5)
-#define IRQ_IN1 _DC21285_IRQ(6)
-#define IRQ_IN2 _DC21285_IRQ(7)
-#define IRQ_IN3 _DC21285_IRQ(8)
-#define IRQ_DOORBELLHOST _DC21285_IRQ(9)
-#define IRQ_DMA1 _DC21285_IRQ(10)
-#define IRQ_DMA2 _DC21285_IRQ(11)
-#define IRQ_PCI _DC21285_IRQ(12)
-#define IRQ_SDRAMPARITY _DC21285_IRQ(13)
-#define IRQ_I2OINPOST _DC21285_IRQ(14)
-#define IRQ_PCI_ABORT _DC21285_IRQ(15)
-#define IRQ_PCI_SERR _DC21285_IRQ(16)
-#define IRQ_DISCARD_TIMER _DC21285_IRQ(17)
-#define IRQ_PCI_DPERR _DC21285_IRQ(18)
-#define IRQ_PCI_PERR _DC21285_IRQ(19)
-
-#define IRQ_ISA_TIMER _ISA_IRQ(0)
-#define IRQ_ISA_KEYBOARD _ISA_IRQ(1)
-#define IRQ_ISA_CASCADE _ISA_IRQ(2)
-#define IRQ_ISA_UART2 _ISA_IRQ(3)
-#define IRQ_ISA_UART _ISA_IRQ(4)
-#define IRQ_ISA_FLOPPY _ISA_IRQ(6)
-#define IRQ_ISA_PRINTER _ISA_IRQ(7)
-#define IRQ_ISA_RTC_ALARM _ISA_IRQ(8)
-#define IRQ_ISA_2 _ISA_IRQ(9)
-#define IRQ_ISA_PS2MOUSE _ISA_IRQ(12)
-#define IRQ_ISA_HARDDISK1 _ISA_IRQ(14)
-#define IRQ_ISA_HARDDISK2 _ISA_IRQ(15)
-
-#define IRQ_MASK_UART_RX (1 << 2)
-#define IRQ_MASK_UART_TX (1 << 3)
-#define IRQ_MASK_TIMER1 (1 << 4)
-#define IRQ_MASK_TIMER2 (1 << 5)
-#define IRQ_MASK_TIMER3 (1 << 6)
-#define IRQ_MASK_IN0 (1 << 8)
-#define IRQ_MASK_IN1 (1 << 9)
-#define IRQ_MASK_IN2 (1 << 10)
-#define IRQ_MASK_IN3 (1 << 11)
-#define IRQ_MASK_DOORBELLHOST (1 << 15)
-#define IRQ_MASK_DMA1 (1 << 16)
-#define IRQ_MASK_DMA2 (1 << 17)
-#define IRQ_MASK_PCI (1 << 18)
-#define IRQ_MASK_SDRAMPARITY (1 << 24)
-#define IRQ_MASK_I2OINPOST (1 << 25)
-#define IRQ_MASK_PCI_ABORT ((1 << 29) | (1 << 30))
-#define IRQ_MASK_PCI_SERR (1 << 23)
-#define IRQ_MASK_DISCARD_TIMER (1 << 27)
-#define IRQ_MASK_PCI_DPERR (1 << 28)
-#define IRQ_MASK_PCI_PERR (1 << 31)
-
-/*
- * Netwinder interrupt allocations
- */
-#define IRQ_NETWINDER_ETHER10 IRQ_IN0
-#define IRQ_NETWINDER_ETHER100 IRQ_IN1
-#define IRQ_NETWINDER_VIDCOMP IRQ_IN2
-#define IRQ_NETWINDER_PS2MOUSE _ISA_IRQ(5)
-#define IRQ_NETWINDER_IR _ISA_IRQ(6)
-#define IRQ_NETWINDER_BUTTON _ISA_IRQ(10)
-#define IRQ_NETWINDER_VGA _ISA_IRQ(11)
-#define IRQ_NETWINDER_SOUND _ISA_IRQ(12)
-
-#define I8042_KBD_IRQ IRQ_ISA_KEYBOARD
-#define I8042_AUX_IRQ (machine_is_netwinder() ? IRQ_NETWINDER_PS2MOUSE : IRQ_ISA_PS2MOUSE)
-#define IRQ_FLOPPYDISK IRQ_ISA_FLOPPY
-
-#define irq_canonicalize(_i) (((_i) == IRQ_ISA_CASCADE) ? IRQ_ISA_2 : _i)
diff --git a/arch/arm/mach-footbridge/include/mach/isa-dma.h b/arch/arm/mach-footbridge/include/mach/isa-dma.h
deleted file mode 100644
index b10731a1f66a..000000000000
--- a/arch/arm/mach-footbridge/include/mach/isa-dma.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/mach-footbridge/include/mach/isa-dma.h
- *
- * Architecture DMA routines
- *
- * Copyright (C) 1998,1999 Russell King
- * Copyright (C) 1998,1999 Philip Blundell
- */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-#define MAX_DMA_CHANNELS 8
-
-#define DMA_FLOPPY (2)
-#define DMA_ISA_CASCADE (4)
-
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-footbridge/include/mach/memory.h b/arch/arm/mach-footbridge/include/mach/memory.h
deleted file mode 100644
index 9516877667d7..000000000000
--- a/arch/arm/mach-footbridge/include/mach/memory.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-footbridge/include/mach/memory.h
- *
- * Copyright (C) 1996-1999 Russell King.
- *
- * Changelog:
- * 20-Oct-1996 RMK Created
- * 31-Dec-1997 RMK Fixed definitions to reduce warnings.
- * 17-May-1998 DAG Added __virt_to_bus and __bus_to_virt functions.
- * 21-Nov-1998 RMK Changed __virt_to_bus and __bus_to_virt to macros.
- * 21-Mar-1999 RMK Added PAGE_OFFSET for co285 architecture.
- * Renamed to memory.h
- * Moved PAGE_OFFSET and TASK_SIZE here
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Cache flushing area.
- */
-#define FLUSH_BASE 0xf9000000
-
-#define FLUSH_BASE_PHYS 0x50000000
-
-#endif
diff --git a/arch/arm/mach-footbridge/include/mach/uncompress.h b/arch/arm/mach-footbridge/include/mach/uncompress.h
deleted file mode 100644
index 28b577e29db3..000000000000
--- a/arch/arm/mach-footbridge/include/mach/uncompress.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-footbridge/include/mach/uncompress.h
- *
- * Copyright (C) 1996-1999 Russell King
- */
-#include <asm/mach-types.h>
-
-/*
- * Note! This could cause problems on the NetWinder
- */
-#define DC21285_BASE ((volatile unsigned int *)0x42000160)
-#define SER0_BASE ((volatile unsigned char *)0x7c0003f8)
-
-static inline void putc(char c)
-{
- if (machine_is_netwinder()) {
- while ((SER0_BASE[5] & 0x60) != 0x60)
- barrier();
- SER0_BASE[0] = c;
- } else {
- while (DC21285_BASE[6] & 8);
- DC21285_BASE[0] = c;
- }
-}
-
-static inline void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c
deleted file mode 100644
index 48c7b3efd555..000000000000
--- a/arch/arm/mach-footbridge/isa-irq.c
+++ /dev/null
@@ -1,177 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-footbridge/irq.c
- *
- * Copyright (C) 1996-2000 Russell King
- *
- * Changelog:
- * 22-Aug-1998 RMK Restructured IRQ routines
- * 03-Sep-1998 PJB Merged CATS support
- * 20-Jan-1998 RMK Started merge of EBSA286, CATS and NetWinder
- * 26-Jan-1999 PJB Don't use IACK on CATS
- * 16-Mar-1999 RMK Added autodetect of ISA PICs
- */
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/hardware.h>
-#include <asm/hardware/dec21285.h>
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include "common.h"
-
-static void isa_mask_pic_lo_irq(struct irq_data *d)
-{
- unsigned int mask = 1 << (d->irq & 7);
-
- outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO);
-}
-
-static void isa_ack_pic_lo_irq(struct irq_data *d)
-{
- unsigned int mask = 1 << (d->irq & 7);
-
- outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO);
- outb(0x20, PIC_LO);
-}
-
-static void isa_unmask_pic_lo_irq(struct irq_data *d)
-{
- unsigned int mask = 1 << (d->irq & 7);
-
- outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO);
-}
-
-static struct irq_chip isa_lo_chip = {
- .irq_ack = isa_ack_pic_lo_irq,
- .irq_mask = isa_mask_pic_lo_irq,
- .irq_unmask = isa_unmask_pic_lo_irq,
-};
-
-static void isa_mask_pic_hi_irq(struct irq_data *d)
-{
- unsigned int mask = 1 << (d->irq & 7);
-
- outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI);
-}
-
-static void isa_ack_pic_hi_irq(struct irq_data *d)
-{
- unsigned int mask = 1 << (d->irq & 7);
-
- outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI);
- outb(0x62, PIC_LO);
- outb(0x20, PIC_HI);
-}
-
-static void isa_unmask_pic_hi_irq(struct irq_data *d)
-{
- unsigned int mask = 1 << (d->irq & 7);
-
- outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI);
-}
-
-static struct irq_chip isa_hi_chip = {
- .irq_ack = isa_ack_pic_hi_irq,
- .irq_mask = isa_mask_pic_hi_irq,
- .irq_unmask = isa_unmask_pic_hi_irq,
-};
-
-static void isa_irq_handler(struct irq_desc *desc)
-{
- unsigned int isa_irq = *(unsigned char *)PCIIACK_BASE;
-
- if (isa_irq < _ISA_IRQ(0) || isa_irq >= _ISA_IRQ(16)) {
- handle_bad_irq(desc);
- return;
- }
-
- generic_handle_irq(isa_irq);
-}
-
-static struct resource pic1_resource = {
- .name = "pic1",
- .start = 0x20,
- .end = 0x3f,
-};
-
-static struct resource pic2_resource = {
- .name = "pic2",
- .start = 0xa0,
- .end = 0xbf,
-};
-
-void __init isa_init_irq(unsigned int host_irq)
-{
- unsigned int irq;
-
- /*
- * Setup, and then probe for an ISA PIC
- * If the PIC is not there, then we
- * ignore the PIC.
- */
- outb(0x11, PIC_LO);
- outb(_ISA_IRQ(0), PIC_MASK_LO); /* IRQ number */
- outb(0x04, PIC_MASK_LO); /* Slave on Ch2 */
- outb(0x01, PIC_MASK_LO); /* x86 */
- outb(0xf5, PIC_MASK_LO); /* pattern: 11110101 */
-
- outb(0x11, PIC_HI);
- outb(_ISA_IRQ(8), PIC_MASK_HI); /* IRQ number */
- outb(0x02, PIC_MASK_HI); /* Slave on Ch1 */
- outb(0x01, PIC_MASK_HI); /* x86 */
- outb(0xfa, PIC_MASK_HI); /* pattern: 11111010 */
-
- outb(0x0b, PIC_LO);
- outb(0x0b, PIC_HI);
-
- if (inb(PIC_MASK_LO) == 0xf5 && inb(PIC_MASK_HI) == 0xfa) {
- outb(0xff, PIC_MASK_LO);/* mask all IRQs */
- outb(0xff, PIC_MASK_HI);/* mask all IRQs */
- } else {
- printk(KERN_INFO "IRQ: ISA PIC not found\n");
- host_irq = (unsigned int)-1;
- }
-
- if (host_irq != (unsigned int)-1) {
- for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
- irq_set_chip_and_handler(irq, &isa_lo_chip,
- handle_level_irq);
- irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
- }
-
- for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
- irq_set_chip_and_handler(irq, &isa_hi_chip,
- handle_level_irq);
- irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
- }
-
- request_resource(&ioport_resource, &pic1_resource);
- request_resource(&ioport_resource, &pic2_resource);
-
- irq = IRQ_ISA_CASCADE;
- if (request_irq(irq, no_action, 0, "cascade", NULL))
- pr_err("Failed to request irq %u (cascade)\n", irq);
-
- irq_set_chained_handler(host_irq, isa_irq_handler);
-
- /*
- * On the NetWinder, don't automatically
- * enable ISA IRQ11 when it is requested.
- * There appears to be a missing pull-up
- * resistor on this line.
- */
- if (machine_is_netwinder())
- irq_modify_status(_ISA_IRQ(11),
- IRQ_NOREQUEST | IRQ_NOPROBE, IRQ_NOAUTOEN);
- }
-}
-
-
diff --git a/arch/arm/mach-footbridge/isa-rtc.c b/arch/arm/mach-footbridge/isa-rtc.c
deleted file mode 100644
index 237b828dd2f1..000000000000
--- a/arch/arm/mach-footbridge/isa-rtc.c
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/arm/mach-footbridge/isa-rtc.c
- *
- * Copyright (C) 1998 Russell King.
- * Copyright (C) 1998 Phil Blundell
- *
- * CATS has a real-time clock, though the evaluation board doesn't.
- *
- * Changelog:
- * 21-Mar-1998 RMK Created
- * 27-Aug-1998 PJB CATS support
- * 28-Dec-1998 APH Made leds optional
- * 20-Jan-1999 RMK Started merge of EBSA285, CATS and NetWinder
- * 16-Mar-1999 RMK More support for EBSA285-like machines with RTCs in
- */
-
-#define RTC_PORT(x) (0x70+(x))
-#define RTC_ALWAYS_BCD 0
-
-#include <linux/init.h>
-#include <linux/mc146818rtc.h>
-#include <linux/io.h>
-
-#include "common.h"
-
-void __init isa_rtc_init(void)
-{
- int reg_d, reg_b;
-
- /*
- * Probe for the RTC.
- */
- reg_d = CMOS_READ(RTC_REG_D);
-
- /*
- * make sure the divider is set
- */
- CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_REG_A);
-
- /*
- * Set control reg B
- * (24 hour mode, update enabled)
- */
- reg_b = CMOS_READ(RTC_REG_B) & 0x7f;
- reg_b |= 2;
- CMOS_WRITE(reg_b, RTC_REG_B);
-
- if ((CMOS_READ(RTC_REG_A) & 0x7f) == RTC_REF_CLCK_32KHZ &&
- CMOS_READ(RTC_REG_B) == reg_b) {
- /*
- * We have a RTC. Check the battery
- */
- if ((reg_d & 0x80) == 0)
- printk(KERN_WARNING "RTC: *** warning: CMOS battery bad\n");
- }
-}
diff --git a/arch/arm/mach-footbridge/isa-timer.c b/arch/arm/mach-footbridge/isa-timer.c
deleted file mode 100644
index 723e3eae995d..000000000000
--- a/arch/arm/mach-footbridge/isa-timer.c
+++ /dev/null
@@ -1,36 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/arm/mach-footbridge/isa-timer.c
- *
- * Copyright (C) 1998 Russell King.
- * Copyright (C) 1998 Phil Blundell
- */
-#include <linux/clockchips.h>
-#include <linux/i8253.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/spinlock.h>
-#include <linux/timex.h>
-
-#include <asm/irq.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-
-static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *ce = dev_id;
- ce->event_handler(ce);
- return IRQ_HANDLED;
-}
-
-void __init isa_timer_init(void)
-{
- clocksource_i8253_init();
-
- if (request_irq(i8253_clockevent.irq, pit_timer_interrupt,
- IRQF_TIMER | IRQF_IRQPOLL, "pit", &i8253_clockevent))
- pr_err("Failed to request irq %d(pit)\n", i8253_clockevent.irq);
- clockevent_i8253_init(false);
-}
diff --git a/arch/arm/mach-footbridge/isa.c b/arch/arm/mach-footbridge/isa.c
deleted file mode 100644
index 84caccddce44..000000000000
--- a/arch/arm/mach-footbridge/isa.c
+++ /dev/null
@@ -1,94 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-footbridge/isa.c
- *
- * Copyright (C) 2004 Russell King.
- */
-#include <linux/init.h>
-#include <linux/serial_8250.h>
-
-#include <asm/irq.h>
-#include <asm/hardware/dec21285.h>
-
-#include "common.h"
-
-static struct resource rtc_resources[] = {
- [0] = {
- .start = 0x70,
- .end = 0x73,
- .flags = IORESOURCE_IO,
- },
- [1] = {
- .start = IRQ_ISA_RTC_ALARM,
- .end = IRQ_ISA_RTC_ALARM,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device rtc_device = {
- .name = "rtc_cmos",
- .id = -1,
- .resource = rtc_resources,
- .num_resources = ARRAY_SIZE(rtc_resources),
-};
-
-static struct resource serial_resources[] = {
- [0] = {
- .start = 0x3f8,
- .end = 0x3ff,
- .flags = IORESOURCE_IO,
- },
- [1] = {
- .start = 0x2f8,
- .end = 0x2ff,
- .flags = IORESOURCE_IO,
- },
-};
-
-static struct plat_serial8250_port serial_platform_data[] = {
- {
- .iobase = 0x3f8,
- .irq = IRQ_ISA_UART,
- .uartclk = 1843200,
- .regshift = 0,
- .iotype = UPIO_PORT,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
- },
- {
- .iobase = 0x2f8,
- .irq = IRQ_ISA_UART2,
- .uartclk = 1843200,
- .regshift = 0,
- .iotype = UPIO_PORT,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
- },
- { },
-};
-
-static struct platform_device serial_device = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = serial_platform_data,
- },
- .resource = serial_resources,
- .num_resources = ARRAY_SIZE(serial_resources),
-};
-
-static int __init footbridge_isa_init(void)
-{
- int err = 0;
-
- /* Personal server doesn't have RTC */
- isa_rtc_init();
- err = platform_device_register(&rtc_device);
- if (err)
- printk(KERN_ERR "Unable to register RTC device: %d\n", err);
-
- err = platform_device_register(&serial_device);
- if (err)
- printk(KERN_ERR "Unable to register serial device: %d\n", err);
- return 0;
-}
-
-arch_initcall(footbridge_isa_init);
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
deleted file mode 100644
index c024eefd4978..000000000000
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ /dev/null
@@ -1,772 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/arm/mach-footbridge/netwinder-hw.c
- *
- * Netwinder machine fixup
- *
- * Copyright (C) 1998, 1999 Russell King, Phil Blundell
- */
-#include <linux/module.h>
-#include <linux/ioport.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-#include <linux/slab.h>
-#include <linux/leds.h>
-
-#include <asm/hardware/dec21285.h>
-#include <asm/mach-types.h>
-#include <asm/setup.h>
-#include <asm/system_misc.h>
-
-#include <asm/mach/arch.h>
-
-#include "common.h"
-
-#define IRDA_IO_BASE 0x180
-#define GP1_IO_BASE 0x338
-#define GP2_IO_BASE 0x33a
-
-/*
- * Winbond WB83977F accessibility stuff
- */
-static inline void wb977_open(void)
-{
- outb(0x87, 0x370);
- outb(0x87, 0x370);
-}
-
-static inline void wb977_close(void)
-{
- outb(0xaa, 0x370);
-}
-
-static inline void wb977_wb(int reg, int val)
-{
- outb(reg, 0x370);
- outb(val, 0x371);
-}
-
-static inline void wb977_ww(int reg, int val)
-{
- outb(reg, 0x370);
- outb(val >> 8, 0x371);
- outb(reg + 1, 0x370);
- outb(val & 255, 0x371);
-}
-
-#define wb977_device_select(dev) wb977_wb(0x07, dev)
-#define wb977_device_disable() wb977_wb(0x30, 0x00)
-#define wb977_device_enable() wb977_wb(0x30, 0x01)
-
-/*
- * This is a lock for accessing ports GP1_IO_BASE and GP2_IO_BASE
- */
-DEFINE_RAW_SPINLOCK(nw_gpio_lock);
-EXPORT_SYMBOL(nw_gpio_lock);
-
-static unsigned int current_gpio_op;
-static unsigned int current_gpio_io;
-static unsigned int current_cpld;
-
-void nw_gpio_modify_op(unsigned int mask, unsigned int set)
-{
- unsigned int new_gpio, changed;
-
- new_gpio = (current_gpio_op & ~mask) | set;
- changed = new_gpio ^ current_gpio_op;
- current_gpio_op = new_gpio;
-
- if (changed & 0xff)
- outb(new_gpio, GP1_IO_BASE);
- if (changed & 0xff00)
- outb(new_gpio >> 8, GP2_IO_BASE);
-}
-EXPORT_SYMBOL(nw_gpio_modify_op);
-
-static inline void __gpio_modify_io(int mask, int in)
-{
- unsigned int new_gpio, changed;
- int port;
-
- new_gpio = (current_gpio_io & ~mask) | in;
- changed = new_gpio ^ current_gpio_io;
- current_gpio_io = new_gpio;
-
- changed >>= 1;
- new_gpio >>= 1;
-
- wb977_device_select(7);
-
- for (port = 0xe1; changed && port < 0xe8; changed >>= 1) {
- wb977_wb(port, new_gpio & 1);
-
- port += 1;
- new_gpio >>= 1;
- }
-
- wb977_device_select(8);
-
- for (port = 0xe8; changed && port < 0xec; changed >>= 1) {
- wb977_wb(port, new_gpio & 1);
-
- port += 1;
- new_gpio >>= 1;
- }
-}
-
-void nw_gpio_modify_io(unsigned int mask, unsigned int in)
-{
- /* Open up the SuperIO chip */
- wb977_open();
-
- __gpio_modify_io(mask, in);
-
- /* Close up the EFER gate */
- wb977_close();
-}
-EXPORT_SYMBOL(nw_gpio_modify_io);
-
-unsigned int nw_gpio_read(void)
-{
- return inb(GP1_IO_BASE) | inb(GP2_IO_BASE) << 8;
-}
-EXPORT_SYMBOL(nw_gpio_read);
-
-/*
- * Initialise the Winbond W83977F global registers
- */
-static inline void wb977_init_global(void)
-{
- /*
- * Enable R/W config registers
- */
- wb977_wb(0x26, 0x40);
-
- /*
- * Power down FDC (not used)
- */
- wb977_wb(0x22, 0xfe);
-
- /*
- * GP12, GP11, CIRRX, IRRXH, GP10
- */
- wb977_wb(0x2a, 0xc1);
-
- /*
- * GP23, GP22, GP21, GP20, GP13
- */
- wb977_wb(0x2b, 0x6b);
-
- /*
- * GP17, GP16, GP15, GP14
- */
- wb977_wb(0x2c, 0x55);
-}
-
-/*
- * Initialise the Winbond W83977F printer port
- */
-static inline void wb977_init_printer(void)
-{
- wb977_device_select(1);
-
- /*
- * mode 1 == EPP
- */
- wb977_wb(0xf0, 0x01);
-}
-
-/*
- * Initialise the Winbond W83977F keyboard controller
- */
-static inline void wb977_init_keyboard(void)
-{
- wb977_device_select(5);
-
- /*
- * Keyboard controller address
- */
- wb977_ww(0x60, 0x0060);
- wb977_ww(0x62, 0x0064);
-
- /*
- * Keyboard IRQ 1, active high, edge trigger
- */
- wb977_wb(0x70, 1);
- wb977_wb(0x71, 0x02);
-
- /*
- * Mouse IRQ 5, active high, edge trigger
- */
- wb977_wb(0x72, 5);
- wb977_wb(0x73, 0x02);
-
- /*
- * KBC 8MHz
- */
- wb977_wb(0xf0, 0x40);
-
- /*
- * Enable device
- */
- wb977_device_enable();
-}
-
-/*
- * Initialise the Winbond W83977F Infra-Red device
- */
-static inline void wb977_init_irda(void)
-{
- wb977_device_select(6);
-
- /*
- * IR base address
- */
- wb977_ww(0x60, IRDA_IO_BASE);
-
- /*
- * IRDA IRQ 6, active high, edge trigger
- */
- wb977_wb(0x70, 6);
- wb977_wb(0x71, 0x02);
-
- /*
- * RX DMA - ISA DMA 0
- */
- wb977_wb(0x74, 0x00);
-
- /*
- * TX DMA - Disable Tx DMA
- */
- wb977_wb(0x75, 0x04);
-
- /*
- * Append CRC, Enable bank selection
- */
- wb977_wb(0xf0, 0x03);
-
- /*
- * Enable device
- */
- wb977_device_enable();
-}
-
-/*
- * Initialise Winbond W83977F general purpose IO
- */
-static inline void wb977_init_gpio(void)
-{
- unsigned long flags;
-
- /*
- * Set up initial I/O definitions
- */
- current_gpio_io = -1;
- __gpio_modify_io(-1, GPIO_DONE | GPIO_WDTIMER);
-
- wb977_device_select(7);
-
- /*
- * Group1 base address
- */
- wb977_ww(0x60, GP1_IO_BASE);
- wb977_ww(0x62, 0);
- wb977_ww(0x64, 0);
-
- /*
- * GP10 (Orage button) IRQ 10, active high, edge trigger
- */
- wb977_wb(0x70, 10);
- wb977_wb(0x71, 0x02);
-
- /*
- * GP10: Debounce filter enabled, IRQ, input
- */
- wb977_wb(0xe0, 0x19);
-
- /*
- * Enable Group1
- */
- wb977_device_enable();
-
- wb977_device_select(8);
-
- /*
- * Group2 base address
- */
- wb977_ww(0x60, GP2_IO_BASE);
-
- /*
- * Clear watchdog timer regs
- * - timer disable
- */
- wb977_wb(0xf2, 0x00);
-
- /*
- * - disable LED, no mouse nor keyboard IRQ
- */
- wb977_wb(0xf3, 0x00);
-
- /*
- * - timer counting, disable power LED, disable timeouot
- */
- wb977_wb(0xf4, 0x00);
-
- /*
- * Enable group2
- */
- wb977_device_enable();
-
- /*
- * Set Group1/Group2 outputs
- */
- raw_spin_lock_irqsave(&nw_gpio_lock, flags);
- nw_gpio_modify_op(-1, GPIO_RED_LED | GPIO_FAN);
- raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
-}
-
-/*
- * Initialise the Winbond W83977F chip.
- */
-static void __init wb977_init(void)
-{
- request_region(0x370, 2, "W83977AF configuration");
-
- /*
- * Open up the SuperIO chip
- */
- wb977_open();
-
- /*
- * Initialise the global registers
- */
- wb977_init_global();
-
- /*
- * Initialise the various devices in
- * the multi-IO chip.
- */
- wb977_init_printer();
- wb977_init_keyboard();
- wb977_init_irda();
- wb977_init_gpio();
-
- /*
- * Close up the EFER gate
- */
- wb977_close();
-}
-
-void nw_cpld_modify(unsigned int mask, unsigned int set)
-{
- int msk;
-
- current_cpld = (current_cpld & ~mask) | set;
-
- nw_gpio_modify_io(GPIO_DATA | GPIO_IOCLK | GPIO_IOLOAD, 0);
- nw_gpio_modify_op(GPIO_IOLOAD, 0);
-
- for (msk = 8; msk; msk >>= 1) {
- int bit = current_cpld & msk;
-
- nw_gpio_modify_op(GPIO_DATA | GPIO_IOCLK, bit ? GPIO_DATA : 0);
- nw_gpio_modify_op(GPIO_IOCLK, GPIO_IOCLK);
- }
-
- nw_gpio_modify_op(GPIO_IOCLK|GPIO_DATA, 0);
- nw_gpio_modify_op(GPIO_IOLOAD|GPIO_DSCLK, GPIO_IOLOAD|GPIO_DSCLK);
- nw_gpio_modify_op(GPIO_IOLOAD, 0);
-}
-EXPORT_SYMBOL(nw_cpld_modify);
-
-static void __init cpld_init(void)
-{
- unsigned long flags;
-
- raw_spin_lock_irqsave(&nw_gpio_lock, flags);
- nw_cpld_modify(-1, CPLD_UNMUTE | CPLD_7111_DISABLE);
- raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
-}
-
-static unsigned char rwa_unlock[] __initdata =
-{ 0x00, 0x00, 0x6a, 0xb5, 0xda, 0xed, 0xf6, 0xfb, 0x7d, 0xbe, 0xdf, 0x6f, 0x37, 0x1b,
- 0x0d, 0x86, 0xc3, 0x61, 0xb0, 0x58, 0x2c, 0x16, 0x8b, 0x45, 0xa2, 0xd1, 0xe8, 0x74,
- 0x3a, 0x9d, 0xce, 0xe7, 0x73, 0x39 };
-
-#ifndef DEBUG
-#define dprintk(x...)
-#else
-#define dprintk(x...) printk(x)
-#endif
-
-#define WRITE_RWA(r,v) do { outb((r), 0x279); udelay(10); outb((v), 0xa79); } while (0)
-
-static inline void rwa010_unlock(void)
-{
- int i;
-
- WRITE_RWA(2, 2);
- mdelay(10);
-
- for (i = 0; i < sizeof(rwa_unlock); i++) {
- outb(rwa_unlock[i], 0x279);
- udelay(10);
- }
-}
-
-static inline void rwa010_read_ident(void)
-{
- unsigned char si[9];
- int i, j;
-
- WRITE_RWA(3, 0);
- WRITE_RWA(0, 128);
-
- outb(1, 0x279);
-
- mdelay(1);
-
- dprintk("Identifier: ");
- for (i = 0; i < 9; i++) {
- si[i] = 0;
- for (j = 0; j < 8; j++) {
- int bit;
- udelay(250);
- inb(0x203);
- udelay(250);
- bit = inb(0x203);
- dprintk("%02X ", bit);
- bit = (bit == 0xaa) ? 1 : 0;
- si[i] |= bit << j;
- }
- dprintk("(%02X) ", si[i]);
- }
- dprintk("\n");
-}
-
-static inline void rwa010_global_init(void)
-{
- WRITE_RWA(6, 2); // Assign a card no = 2
-
- dprintk("Card no = %d\n", inb(0x203));
-
- /* disable the modem section of the chip */
- WRITE_RWA(7, 3);
- WRITE_RWA(0x30, 0);
-
- /* disable the cdrom section of the chip */
- WRITE_RWA(7, 4);
- WRITE_RWA(0x30, 0);
-
- /* disable the MPU-401 section of the chip */
- WRITE_RWA(7, 2);
- WRITE_RWA(0x30, 0);
-}
-
-static inline void rwa010_game_port_init(void)
-{
- int i;
-
- WRITE_RWA(7, 5);
-
- dprintk("Slider base: ");
- WRITE_RWA(0x61, 1);
- i = inb(0x203);
-
- WRITE_RWA(0x60, 2);
- dprintk("%02X%02X (201)\n", inb(0x203), i);
-
- WRITE_RWA(0x30, 1);
-}
-
-static inline void rwa010_waveartist_init(int base, int irq, int dma)
-{
- int i;
-
- WRITE_RWA(7, 0);
-
- dprintk("WaveArtist base: ");
- WRITE_RWA(0x61, base & 255);
- i = inb(0x203);
-
- WRITE_RWA(0x60, base >> 8);
- dprintk("%02X%02X (%X),", inb(0x203), i, base);
-
- WRITE_RWA(0x70, irq);
- dprintk(" irq: %d (%d),", inb(0x203), irq);
-
- WRITE_RWA(0x74, dma);
- dprintk(" dma: %d (%d)\n", inb(0x203), dma);
-
- WRITE_RWA(0x30, 1);
-}
-
-static inline void rwa010_soundblaster_init(int sb_base, int al_base, int irq, int dma)
-{
- int i;
-
- WRITE_RWA(7, 1);
-
- dprintk("SoundBlaster base: ");
- WRITE_RWA(0x61, sb_base & 255);
- i = inb(0x203);
-
- WRITE_RWA(0x60, sb_base >> 8);
- dprintk("%02X%02X (%X),", inb(0x203), i, sb_base);
-
- dprintk(" irq: ");
- WRITE_RWA(0x70, irq);
- dprintk("%d (%d),", inb(0x203), irq);
-
- dprintk(" 8-bit DMA: ");
- WRITE_RWA(0x74, dma);
- dprintk("%d (%d)\n", inb(0x203), dma);
-
- dprintk("AdLib base: ");
- WRITE_RWA(0x63, al_base & 255);
- i = inb(0x203);
-
- WRITE_RWA(0x62, al_base >> 8);
- dprintk("%02X%02X (%X)\n", inb(0x203), i, al_base);
-
- WRITE_RWA(0x30, 1);
-}
-
-static void rwa010_soundblaster_reset(void)
-{
- int i;
-
- outb(1, 0x226);
- udelay(3);
- outb(0, 0x226);
-
- for (i = 0; i < 5; i++) {
- if (inb(0x22e) & 0x80)
- break;
- mdelay(1);
- }
- if (i == 5)
- printk("SoundBlaster: DSP reset failed\n");
-
- dprintk("SoundBlaster DSP reset: %02X (AA)\n", inb(0x22a));
-
- for (i = 0; i < 5; i++) {
- if ((inb(0x22c) & 0x80) == 0)
- break;
- mdelay(1);
- }
-
- if (i == 5)
- printk("SoundBlaster: DSP not ready\n");
- else {
- outb(0xe1, 0x22c);
-
- dprintk("SoundBlaster DSP id: ");
- i = inb(0x22a);
- udelay(1);
- i |= inb(0x22a) << 8;
- dprintk("%04X\n", i);
-
- for (i = 0; i < 5; i++) {
- if ((inb(0x22c) & 0x80) == 0)
- break;
- mdelay(1);
- }
-
- if (i == 5)
- printk("SoundBlaster: could not turn speaker off\n");
-
- outb(0xd3, 0x22c);
- }
-
- /* turn on OPL3 */
- outb(5, 0x38a);
- outb(1, 0x38b);
-}
-
-static void __init rwa010_init(void)
-{
- rwa010_unlock();
- rwa010_read_ident();
- rwa010_global_init();
- rwa010_game_port_init();
- rwa010_waveartist_init(0x250, 3, 7);
- rwa010_soundblaster_init(0x220, 0x388, 3, 1);
- rwa010_soundblaster_reset();
-}
-
-/*
- * Initialise any other hardware after we've got the PCI bus
- * initialised. We may need the PCI bus to talk to this other
- * hardware.
- */
-static int __init nw_hw_init(void)
-{
- if (machine_is_netwinder()) {
- wb977_init();
- cpld_init();
- rwa010_init();
- }
- return 0;
-}
-
-__initcall(nw_hw_init);
-
-/*
- * Older NeTTroms either do not provide a parameters
- * page, or they don't supply correct information in
- * the parameter page.
- */
-static void __init
-fixup_netwinder(struct tag *tags, char **cmdline)
-{
-#ifdef CONFIG_ISAPNP
- extern int isapnp_disable;
-
- /*
- * We must not use the kernels ISAPnP code
- * on the NetWinder - it will reset the settings
- * for the WaveArtist chip and render it inoperable.
- */
- isapnp_disable = 1;
-#endif
-}
-
-static void netwinder_restart(enum reboot_mode mode, const char *cmd)
-{
- if (mode == REBOOT_SOFT) {
- /* Jump into the ROM */
- soft_restart(0x41000000);
- } else {
- local_irq_disable();
- local_fiq_disable();
-
- /* open up the SuperIO chip */
- outb(0x87, 0x370);
- outb(0x87, 0x370);
-
- /* aux function group 1 (logical device 7) */
- outb(0x07, 0x370);
- outb(0x07, 0x371);
-
- /* set GP16 for WD-TIMER output */
- outb(0xe6, 0x370);
- outb(0x00, 0x371);
-
- /* set a RED LED and toggle WD_TIMER for rebooting */
- outb(0xc4, 0x338);
- }
-}
-
-/* LEDs */
-#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
-struct netwinder_led {
- struct led_classdev cdev;
- u8 mask;
-};
-
-/*
- * The triggers lines up below will only be used if the
- * LED triggers are compiled in.
- */
-static const struct {
- const char *name;
- const char *trigger;
-} netwinder_leds[] = {
- { "netwinder:green", "heartbeat", },
- { "netwinder:red", "cpu0", },
-};
-
-/*
- * The LED control in Netwinder is reversed:
- * - setting bit means turn off LED
- * - clearing bit means turn on LED
- */
-static void netwinder_led_set(struct led_classdev *cdev,
- enum led_brightness b)
-{
- struct netwinder_led *led = container_of(cdev,
- struct netwinder_led, cdev);
- unsigned long flags;
- u32 reg;
-
- raw_spin_lock_irqsave(&nw_gpio_lock, flags);
- reg = nw_gpio_read();
- if (b != LED_OFF)
- reg &= ~led->mask;
- else
- reg |= led->mask;
- nw_gpio_modify_op(led->mask, reg);
- raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
-}
-
-static enum led_brightness netwinder_led_get(struct led_classdev *cdev)
-{
- struct netwinder_led *led = container_of(cdev,
- struct netwinder_led, cdev);
- unsigned long flags;
- u32 reg;
-
- raw_spin_lock_irqsave(&nw_gpio_lock, flags);
- reg = nw_gpio_read();
- raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
-
- return (reg & led->mask) ? LED_OFF : LED_FULL;
-}
-
-static int __init netwinder_leds_init(void)
-{
- int i;
-
- if (!machine_is_netwinder())
- return -ENODEV;
-
- for (i = 0; i < ARRAY_SIZE(netwinder_leds); i++) {
- struct netwinder_led *led;
-
- led = kzalloc_obj(*led);
- if (!led)
- break;
-
- led->cdev.name = netwinder_leds[i].name;
- led->cdev.brightness_set = netwinder_led_set;
- led->cdev.brightness_get = netwinder_led_get;
- led->cdev.default_trigger = netwinder_leds[i].trigger;
-
- if (i == 0)
- led->mask = GPIO_GREEN_LED;
- else
- led->mask = GPIO_RED_LED;
-
- if (led_classdev_register(NULL, &led->cdev) < 0) {
- kfree(led);
- break;
- }
- }
-
- return 0;
-}
-
-/*
- * Since we may have triggers on any subsystem, defer registration
- * until after subsystem_init.
- */
-fs_initcall(netwinder_leds_init);
-#endif
-
-MACHINE_START(NETWINDER, "Rebel-NetWinder")
- /* Maintainer: Russell King/Rebel.com */
- .atag_offset = 0x100,
- .video_start = 0x000a0000,
- .video_end = 0x000bffff,
- .reserve_lp0 = 1,
- .reserve_lp2 = 1,
- .fixup = fixup_netwinder,
- .map_io = footbridge_map_io,
- .init_irq = footbridge_init_irq,
- .init_time = isa_timer_init,
- .restart = netwinder_restart,
-MACHINE_END
diff --git a/arch/arm/mach-footbridge/netwinder-pci.c b/arch/arm/mach-footbridge/netwinder-pci.c
deleted file mode 100644
index e8304392074b..000000000000
--- a/arch/arm/mach-footbridge/netwinder-pci.c
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/arm/mach-footbridge/netwinder-pci.c
- *
- * PCI bios-type initialisation for PCI machines
- *
- * Bits taken from various places.
- */
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-
-#include <asm/irq.h>
-#include <asm/mach/pci.h>
-#include <asm/mach-types.h>
-
-/*
- * We now use the slot ID instead of the device identifiers to select
- * which interrupt is routed where.
- */
-static int netwinder_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- switch (slot) {
- case 0: /* host bridge */
- return 0;
-
- case 9: /* CyberPro */
- return IRQ_NETWINDER_VGA;
-
- case 10: /* DC21143 */
- return IRQ_NETWINDER_ETHER100;
-
- case 12: /* Winbond 553 */
- return IRQ_ISA_HARDDISK1;
-
- case 13: /* Winbond 89C940F */
- return IRQ_NETWINDER_ETHER10;
-
- default:
- printk(KERN_ERR "PCI: unknown device in slot %s\n",
- pci_name(dev));
- return 0;
- }
-}
-
-static struct hw_pci netwinder_pci __initdata = {
- .map_irq = netwinder_map_irq,
- .nr_controllers = 1,
- .ops = &dc21285_ops,
- .setup = dc21285_setup,
- .preinit = dc21285_preinit,
- .postinit = dc21285_postinit,
-};
-
-static int __init netwinder_pci_init(void)
-{
- if (machine_is_netwinder())
- pci_common_init(&netwinder_pci);
- return 0;
-}
-
-subsys_initcall(netwinder_pci_init);
diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig
index 9f81af3506da..d8e3d307f50f 100644
--- a/drivers/video/console/Kconfig
+++ b/drivers/video/console/Kconfig
@@ -8,7 +8,6 @@ menu "Console display driver support"
config VGA_CONSOLE
bool "VGA text console" if EXPERT || !X86
depends on ALPHA || X86 || \
- (ARM && ARCH_FOOTBRIDGE) || \
(MIPS && (MIPS_MALTA || SIBYTE_BCM112X || SIBYTE_SB1250 || SIBYTE_BCM1x80 || SNI_RM))
select APERTURE_HELPERS if (DRM || FB || VFIO_PCI_CORE)
default y
@@ -36,7 +35,7 @@ config DUMMY_CONSOLE
config DUMMY_CONSOLE_COLUMNS
int "Initial number of console screen columns"
- depends on DUMMY_CONSOLE && !(ARCH_FOOTBRIDGE && VGA_CONSOLE)
+ depends on DUMMY_CONSOLE
default 160 if PARISC
default 80
help
@@ -46,9 +45,8 @@ config DUMMY_CONSOLE_COLUMNS
config DUMMY_CONSOLE_ROWS
int "Initial number of console screen rows"
- depends on DUMMY_CONSOLE && !(ARCH_FOOTBRIDGE && VGA_CONSOLE)
+ depends on DUMMY_CONSOLE
default 64 if PARISC
- default 30 if ARM
default 25
help
On PA-RISC, the default value is 64, which should fit a 1280x1024
diff --git a/drivers/video/console/dummycon.c b/drivers/video/console/dummycon.c
index 7d02470f19b9..48ebbc5bf6a8 100644
--- a/drivers/video/console/dummycon.c
+++ b/drivers/video/console/dummycon.c
@@ -18,15 +18,9 @@
* Dummy console driver
*/
-#if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_VGA_CONSOLE)
-#include <asm/vga.h>
-#define DUMMY_COLUMNS vgacon_screen_info.orig_video_cols
-#define DUMMY_ROWS vgacon_screen_info.orig_video_lines
-#else
/* set by Kconfig. Use 80x25 for 640x480 and 160x64 for 1280x1024 */
#define DUMMY_COLUMNS CONFIG_DUMMY_CONSOLE_COLUMNS
#define DUMMY_ROWS CONFIG_DUMMY_CONSOLE_ROWS
-#endif
#ifdef CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER
/* These are both protected by the console_lock */
diff --git a/drivers/video/fbdev/cyber2000fb.c b/drivers/video/fbdev/cyber2000fb.c
index 5c7349722125..aa15c7be4fa5 100644
--- a/drivers/video/fbdev/cyber2000fb.c
+++ b/drivers/video/fbdev/cyber2000fb.c
@@ -1723,16 +1723,6 @@ static int cyberpro_pci_probe(struct pci_dev *dev,
cfb->mclk_mult = cyber2000_grphr(EXT_MCLK_MULT, cfb);
cfb->mclk_div = cyber2000_grphr(EXT_MCLK_DIV, cfb);
-#ifdef __arm__
- /*
- * MCLK on the NetWinder and the Shark is fixed at 75MHz
- */
- if (machine_is_netwinder()) {
- cfb->mclk_mult = 0xdb;
- cfb->mclk_div = 0x54;
- }
-#endif
-
err = cyberpro_common_probe(cfb);
if (err)
goto failed;
--
2.53.0
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 02/13] ARM: remove footbridge
2026-09-08 15:27 ` [PATCH 02/13] ARM: remove footbridge Arnd Bergmann
@ 2026-09-08 17:27 ` Linus Walleij
2026-09-09 15:09 ` Ralph Siemsen
0 siblings, 1 reply; 70+ messages in thread
From: Linus Walleij @ 2026-09-08 17:27 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Russell King,
Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Ralph Siemsen,
Helge Deller, dri-devel
On Tue, Sep 8, 2026 at 5:28 PM Arnd Bergmann <arnd@kernel.org> wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> Footbridge was deprecated in 7.3 to be removed along with the other
> StrongARM platforms and most remaining board files.
>
> The main machine here is the NetWinder, which was a popular Arm based
> desktop PC in the late 1990s and contributed to Arm's later success as
> an embedded Linux platform, but was discontinued over 25 years ago and
> is no longer all that useful.
>
> I previously tried to convert this to devicetree in a sensible way but
> gave up due to the platform being too different from modern SoC based
> targets.
>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Ralph Siemsen <ralphs@netwinder.org>
> Cc: Helge Deller <deller@gmx.de>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linusw@kernel.org>
I have one of those machines and it boot mainline but I
certainly consider it a paperweight at this point, I can't use
it for anything useful.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 02/13] ARM: remove footbridge
2026-09-08 17:27 ` Linus Walleij
@ 2026-09-09 15:09 ` Ralph Siemsen
0 siblings, 0 replies; 70+ messages in thread
From: Ralph Siemsen @ 2026-09-09 15:09 UTC (permalink / raw)
To: Linus Walleij
Cc: Arnd Bergmann, Krzysztof Kozlowski, Alexandre Belloni,
Russell King, Drew Fustini, Arnd Bergmann, Rob Herring,
Conor Dooley, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Helge Deller,
dri-devel
On Tue, Sep 08, 2026 at 07:27:48PM +0200, Linus Walleij wrote:
>On Tue, Sep 8, 2026 at 5:28 PM Arnd Bergmann <arnd@kernel.org> wrote:
>
>> From: Arnd Bergmann <arnd@arndb.de>
>>
>> Footbridge was deprecated in 7.3 to be removed along with the other
>> StrongARM platforms and most remaining board files.
>>
>> The main machine here is the NetWinder, which was a popular Arm based
>> desktop PC in the late 1990s and contributed to Arm's later success as
>> an embedded Linux platform, but was discontinued over 25 years ago and
>> is no longer all that useful.
>>
>> I previously tried to convert this to devicetree in a sensible way but
>> gave up due to the platform being too different from modern SoC based
>> targets.
>>
>> Cc: Russell King <linux@armlinux.org.uk>
>> Cc: Ralph Siemsen <ralphs@netwinder.org>
>> Cc: Helge Deller <deller@gmx.de>
>> Cc: dri-devel@lists.freedesktop.org
>> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>
>Acked-by: Linus Walleij <linusw@kernel.org>
>
>I have one of those machines and it boot mainline but I
>certainly consider it a paperweight at this point, I can't use
>it for anything useful.
Likewise, I have a NetWinder machine which has occasionally booted a
mainline kernel, along with fairly current buildroot initramfs. It has
been surprisingly smooth sailing, even the bx/bl compiler troubles seem
to have been sorted out these days.
It's a bit sad to see it go, in particular since it all works. But the
reality is that nobody seems to be running this hardware anymore, and
there is no community of active users anymore.
Acked-by: Ralph Siemsen <ralphs@netwinder.org>
Regards,
-Ralph
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH 03/13] ARM: remove riscpc
2026-09-08 15:27 [PATCH 00/13] ARM: deprecated platform removal Arnd Bergmann
2026-09-08 15:27 ` [PATCH 01/13] ARM: remove sa1100 platform Arnd Bergmann
2026-09-08 15:27 ` [PATCH 02/13] ARM: remove footbridge Arnd Bergmann
@ 2026-09-08 15:27 ` Arnd Bergmann
2026-09-09 8:04 ` Thomas Zimmermann
2026-09-09 16:42 ` Bart Van Assche
2026-09-08 15:27 ` [PATCH 04/13] ARM: remove legacy pxa board files Arnd Bergmann
` (10 subsequent siblings)
13 siblings, 2 replies; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 15:27 UTC (permalink / raw)
To: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Ian Molton, Jens Axboe,
Helge Deller, Thomas Zimmermann, Paul E. McKenney, linux-block,
linux-serial, linux-fbdev
From: Arnd Bergmann <arnd@arndb.de>
The Acorn Risc PC is the oldest still support Arm machine in the kernel,
originally shipped with an ARMv3 ARM610 support in 1994, it later allowed
faster StrongARM CPUs.
The main limitation here is the CPU bus that does not allow 16-bit
wide data transfers and hence requires the kernel to be built with the
-march=armv3 compiler option that was discontinued in gcc-9.
As gcc-8 is barely supported for compiling the kernel, this one
will not see another LTS kernel release, so remove it now.
Cc: Russell King <linux@armlinux.org.uk>
Cc: Ian Molton <spyro@f2s.com>
Cc: Jens Axboe <axboe@kernel.dk>
Cc: Helge Deller <deller@gmx.de>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: Karl Mehltretter <kmehltretter@gmail.com>
Cc: "Paul E. McKenney" <paulmck@kernel.org>
Cc: linux-block@vger.kernel.org
Cc: linux-serial@vger.kernel.org
Cc: linux-fbdev@vger.kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
MAINTAINERS | 20 -
arch/arm/Kconfig | 33 +-
arch/arm/Kconfig.debug | 8 +-
arch/arm/boot/bootp/Makefile | 2 -
arch/arm/boot/compressed/Makefile | 4 -
arch/arm/boot/compressed/font.c | 2 -
arch/arm/boot/compressed/head.S | 8 -
arch/arm/boot/compressed/ll_char_wr.S | 131 ---
arch/arm/configs/rpc_defconfig | 127 --
arch/arm/include/asm/ecard.h | 219 ----
arch/arm/include/asm/hardware/ioc.h | 69 --
arch/arm/include/asm/hardware/iomd.h | 182 ---
arch/arm/include/asm/hardware/memc.h | 23 -
arch/arm/include/asm/io.h | 5 +-
arch/arm/include/asm/memory.h | 3 -
arch/arm/kernel/head-common.S | 13 -
arch/arm/kernel/head.S | 12 -
arch/arm/lib/delay-loop.S | 4 -
arch/arm/mach-rpc/Kconfig | 24 -
arch/arm/mach-rpc/Makefile | 9 -
arch/arm/mach-rpc/dma.c | 393 -------
arch/arm/mach-rpc/ecard-loader.S | 40 -
arch/arm/mach-rpc/ecard.c | 1146 -------------------
arch/arm/mach-rpc/ecard.h | 66 --
arch/arm/mach-rpc/fiq.S | 18 -
arch/arm/mach-rpc/floppydma.S | 29 -
arch/arm/mach-rpc/include/mach/acornfb.h | 137 ---
arch/arm/mach-rpc/include/mach/hardware.h | 73 --
arch/arm/mach-rpc/include/mach/io.h | 28 -
arch/arm/mach-rpc/include/mach/irqs.h | 42 -
arch/arm/mach-rpc/include/mach/isa-dma.h | 26 -
arch/arm/mach-rpc/include/mach/memory.h | 32 -
arch/arm/mach-rpc/include/mach/uncompress.h | 181 ---
arch/arm/mach-rpc/io-acorn.S | 28 -
arch/arm/mach-rpc/irq.c | 226 ----
arch/arm/mach-rpc/riscpc.c | 225 ----
arch/arm/mach-rpc/time.c | 97 --
arch/arm/mm/mmu.c | 2 +-
block/partitions/Kconfig | 7 -
drivers/tty/vt/keyboard.c | 2 +-
lib/fonts/font_acorn_8x8.c | 4 -
41 files changed, 12 insertions(+), 3688 deletions(-)
delete mode 100644 arch/arm/boot/compressed/font.c
delete mode 100644 arch/arm/boot/compressed/ll_char_wr.S
delete mode 100644 arch/arm/configs/rpc_defconfig
delete mode 100644 arch/arm/include/asm/ecard.h
delete mode 100644 arch/arm/include/asm/hardware/ioc.h
delete mode 100644 arch/arm/include/asm/hardware/iomd.h
delete mode 100644 arch/arm/include/asm/hardware/memc.h
delete mode 100644 arch/arm/mach-rpc/Kconfig
delete mode 100644 arch/arm/mach-rpc/Makefile
delete mode 100644 arch/arm/mach-rpc/dma.c
delete mode 100644 arch/arm/mach-rpc/ecard-loader.S
delete mode 100644 arch/arm/mach-rpc/ecard.c
delete mode 100644 arch/arm/mach-rpc/ecard.h
delete mode 100644 arch/arm/mach-rpc/fiq.S
delete mode 100644 arch/arm/mach-rpc/floppydma.S
delete mode 100644 arch/arm/mach-rpc/include/mach/acornfb.h
delete mode 100644 arch/arm/mach-rpc/include/mach/hardware.h
delete mode 100644 arch/arm/mach-rpc/include/mach/io.h
delete mode 100644 arch/arm/mach-rpc/include/mach/irqs.h
delete mode 100644 arch/arm/mach-rpc/include/mach/isa-dma.h
delete mode 100644 arch/arm/mach-rpc/include/mach/memory.h
delete mode 100644 arch/arm/mach-rpc/include/mach/uncompress.h
delete mode 100644 arch/arm/mach-rpc/io-acorn.S
delete mode 100644 arch/arm/mach-rpc/irq.c
delete mode 100644 arch/arm/mach-rpc/riscpc.c
delete mode 100644 arch/arm/mach-rpc/time.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 4380d5660402..6e8fe7640064 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2350,12 +2350,6 @@ F: Documentation/devicetree/bindings/display/arm,malidp.yaml
F: Documentation/gpu/afbc.rst
F: drivers/gpu/drm/arm/
-ARM MFM AND FLOPPY DRIVERS
-M: Ian Molton <spyro@f2s.com>
-S: Maintained
-F: arch/arm/include/asm/floppy.h
-F: arch/arm/mach-rpc/floppydma.S
-
ARM PMU PROFILING AND DEBUGGING
M: Will Deacon <will@kernel.org>
M: Mark Rutland <mark.rutland@arm.com>
@@ -3494,20 +3488,6 @@ F: include/linux/soc/renesas/
N: rcar
K: \brenesas,
-ARM/RISCPC ARCHITECTURE
-M: Russell King <linux@armlinux.org.uk>
-L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-S: Maintained
-W: http://www.armlinux.org.uk/
-F: arch/arm/include/asm/hardware/ioc.h
-F: arch/arm/include/asm/hardware/iomd.h
-F: arch/arm/include/asm/hardware/memc.h
-F: arch/arm/mach-rpc/
-F: drivers/net/ethernet/8390/etherh.c
-F: drivers/net/ethernet/i825xx/ether1*
-F: drivers/net/ethernet/seeq/ether3*
-F: drivers/scsi/arm/
-
ARM/Rockchip SoC support
M: Heiko Stuebner <heiko@sntech.de>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c3d6b8abc815..5770deca136d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -55,7 +55,7 @@ config ARM
select ARCH_WANT_LD_ORPHAN_WARN
select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
select BUILDTIME_TABLE_SORT if MMU
- select COMMON_CLK if !ARCH_RPC
+ select COMMON_CLK
select CLONE_BACKWARDS
select CPU_PM if SUSPEND || CPU_IDLE
select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
@@ -155,13 +155,13 @@ config ARM
select PCI_SYSCALL if PCI
select PERF_USE_VMALLOC
select RTC_LIB
- select SPARSE_IRQ if !ARCH_RPC
+ select SPARSE_IRQ
select SYS_SUPPORTS_APM_EMULATION
select THREAD_INFO_IN_TASK
select TIMER_OF if OF
select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
- select USE_OF if !ARCH_RPC
+ select USE_OF
# Above selects are sorted alphabetically; please add new ones
# according to that. Thanks.
help
@@ -277,25 +277,11 @@ config ARM_PATCH_PHYS_VIRT
this feature (eg, building a kernel for a single machine) and
you need to shrink the kernel to the minimal size.
-config NEED_MACH_IO_H
- bool
- help
- Select this when mach/io.h is required to provide special
- definitions for this platform. The need for mach/io.h should
- be avoided when possible.
-
-config NEED_MACH_MEMORY_H
- bool
- help
- Select this when mach/memory.h is required to provide special
- definitions for this platform. The need for mach/memory.h should
- be avoided when possible.
-
config PHYS_OFFSET
hex "Physical address of main memory" if MMU
depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR
default DRAM_BASE if !MMU
- default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
+ default 0x10000000 if ARCH_OMAP1
default 0xa0000000 if ARCH_PXA
default 0xc0000000 if ARCH_EP93XX
default 0
@@ -337,7 +323,7 @@ config ARCH_MMAP_RND_BITS_MAX
config ARCH_MULTIPLATFORM
bool "Require kernel to be portable to multiple machines" if EXPERT
- depends on MMU && !ARCH_RPC
+ depends on MMU
default y
help
In general, all Arm machines can be supported in a single
@@ -429,8 +415,6 @@ source "arch/arm/mach-qcom/Kconfig"
source "arch/arm/mach-realtek/Kconfig"
-source "arch/arm/mach-rpc/Kconfig"
-
source "arch/arm/mach-rockchip/Kconfig"
source "arch/arm/mach-s3c/Kconfig"
@@ -490,9 +474,6 @@ config ARCH_MPS2
This platform is scheduled for removal in early 2027
# Definitions to make life easier
-config ARCH_ACORN
- bool
-
config PLAT_ORION
bool
select CLKSRC_MMIO
@@ -1191,7 +1172,7 @@ config ARCH_SELECT_MEMORY_MODEL
def_bool y
config ARCH_FLATMEM_ENABLE
- def_bool !ARCH_RPC
+ def_bool y
config ARCH_SPARSEMEM_ENABLE
def_bool y
@@ -1594,7 +1575,7 @@ config ARCH_DEFAULT_CRASH_DUMP
config AUTO_ZRELADDR
bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM
- default !ARCH_RPC
+ default y
help
ZRELADDR is the physical address where the decompressed kernel
image will be placed. If AUTO_ZRELADDR is selected, the address
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index f2a80955b7a0..56c090840c5a 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1446,7 +1446,7 @@ config DEBUG_STM32_UART
config DEBUG_UART_FLOW_CONTROL
bool "Enable flow control (CTS) for the debug UART"
depends on DEBUG_LL
- default y if DEBUG_GEMINI || ARCH_RPC
+ default y if DEBUG_GEMINI
help
Some UART ports are connected to terminals that will use modem
control signals to indicate whether they are ready to receive text.
@@ -1516,7 +1516,7 @@ config DEBUG_UART_PL01X
# Compatibility options for 8250
config DEBUG_UART_8250
- def_bool ARCH_IXP4XX || ARCH_RPC
+ def_bool ARCH_IXP4XX
config DEBUG_UART_PHYS
hex "Physical base address of debug UART"
@@ -1527,7 +1527,6 @@ config DEBUG_UART_PHYS
default 0x01f02800 if DEBUG_SUNXI_R_UART
default 0x02530c00 if DEBUG_KEYSTONE_UART0
default 0x02531000 if DEBUG_KEYSTONE_UART1
- default 0x03010fe0 if ARCH_RPC
default 0x07000000 if DEBUG_SUN9I_UART0
default 0x09530000 if DEBUG_STIH418_SBC_ASC0
default 0x10009000 if DEBUG_REALVIEW_STD_PORT || \
@@ -1654,7 +1653,6 @@ config DEBUG_UART_VIRT
default 0xc881f000 if DEBUG_RV1108_UART2
default 0xc8821000 if DEBUG_RV1108_UART1
default 0xc8912000 if DEBUG_RV1108_UART0
- default 0xe0010fe0 if ARCH_RPC
default 0xe0824200 if DEBUG_AT91_SAMA7G5_FLEXCOM3
default 0xf0010000 if DEBUG_ASM9260_UART
default 0xf0100000 if DEBUG_DIGICOLOR_UA0
@@ -1779,7 +1777,6 @@ config DEBUG_UART_8250_PALMCHIP
config DEBUG_UNCOMPRESS
bool "Enable decompressor debugging via DEBUG_LL output"
depends on !ARCH_MULTIPLATFORM
- depends on !ARCH_RPC
depends on DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
(!DEBUG_TEGRA_UART || !ZBOOT_ROM) && \
!DEBUG_BRCMSTB_UART && !DEBUG_SEMIHOSTING
@@ -1789,7 +1786,6 @@ config DEBUG_UNCOMPRESS
config UNCOMPRESS_INCLUDE
string
- default "mach/uncompress.h" if ARCH_RPC
default "debug/uncompress.h"
config EARLY_PRINTK
diff --git a/arch/arm/boot/bootp/Makefile b/arch/arm/boot/bootp/Makefile
index 12c61684b97f..1e47bf10069d 100644
--- a/arch/arm/boot/bootp/Makefile
+++ b/arch/arm/boot/bootp/Makefile
@@ -19,8 +19,6 @@ add_hex = $(shell printf 0x%x $$(( $(1) + $(2) )) )
PARAMS_PHYS := $(call add_hex, $(PHYS_OFFSET), 0x100)
# guess an initrd location if possible
-initrd_offset-$(CONFIG_ARCH_RPC) += 0x08000000
-INITRD_OFFSET := $(initrd_offset-y)
ifdef INITRD_OFFSET
INITRD_PHYS := $(call add_hex, $(PHYS_OFFSET), $(INITRD_OFFSET))
endif
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index d8d81ba741a2..32def10f5e03 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -25,10 +25,6 @@ endif
#
# Architecture dependencies
#
-ifeq ($(CONFIG_ARCH_ACORN),y)
-OBJS += ll_char_wr.o font.o
-endif
-
ifeq ($(CONFIG_CPU_XSCALE),y)
OBJS += head-xscale.o
endif
diff --git a/arch/arm/boot/compressed/font.c b/arch/arm/boot/compressed/font.c
deleted file mode 100644
index 46a677649db4..000000000000
--- a/arch/arm/boot/compressed/font.c
+++ /dev/null
@@ -1,2 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-#include "../../../../lib/fonts/font_acorn_8x8.c"
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 845abffbc2d6..af579905b630 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -668,14 +668,6 @@ LC1: .word .L_user_stack_end - LC1 @ sp
.Linflated_image_size_offset:
.long (input_data_end - 4) - .
-#ifdef CONFIG_ARCH_RPC
- .globl params
-params: ldr r0, =0x10000100 @ params_phys for RPC
- mov pc, lr
- .ltorg
- .align
-#endif
-
/*
* dcache_line_size - get the minimum D-cache line size from the CTR register
* on ARMv7.
diff --git a/arch/arm/boot/compressed/ll_char_wr.S b/arch/arm/boot/compressed/ll_char_wr.S
deleted file mode 100644
index 1ec8cb2898b1..000000000000
--- a/arch/arm/boot/compressed/ll_char_wr.S
+++ /dev/null
@@ -1,131 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * linux/arch/arm/lib/ll_char_wr.S
- *
- * Copyright (C) 1995, 1996 Russell King.
- *
- * Speedups & 1bpp code (C) 1996 Philip Blundell & Russell King.
- *
- * 10-04-96 RMK Various cleanups & reduced register usage.
- * 08-04-98 RMK Shifts re-ordered
- */
-
-@ Regs: [] = corruptible
-@ {} = used
-@ () = do not use
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
- .text
-
-LC0: .word LC0
- .word bytes_per_char_h
- .word video_size_row
- .word acorndata_8x8
- .word con_charconvtable
-
-/*
- * r0 = ptr
- * r1 = char
- * r2 = white
- */
-ENTRY(ll_write_char)
- stmfd sp!, {r4 - r7, lr}
-@
-@ Smashable regs: {r0 - r3}, [r4 - r7], (r8 - fp), [ip], (sp), [lr], (pc)
-@
- /*
- * calculate offset into character table
- */
- mov r1, r1, lsl #3
- /*
- * calculate offset required for each row.
- */
- adr ip, LC0
- ldmia ip, {r3, r4, r5, r6, lr}
- sub ip, ip, r3
- add r6, r6, ip
- add lr, lr, ip
- ldr r4, [r4, ip]
- ldr r5, [r5, ip]
- /*
- * Go to resolution-dependent routine...
- */
- cmp r4, #4
- blt Lrow1bpp
- add r0, r0, r5, lsl #3 @ Move to bottom of character
- orr r1, r1, #7
- ldrb r7, [r6, r1]
- teq r4, #8
- beq Lrow8bpplp
-@
-@ Smashable regs: {r0 - r3}, [r4], {r5 - r7}, (r8 - fp), [ip], (sp), {lr}, (pc)
-@
-Lrow4bpplp:
- ldr r7, [lr, r7, lsl #2]
- mul r7, r2, r7
- sub r1, r1, #1 @ avoid using r7 directly after
- str r7, [r0, -r5]!
- ldrb r7, [r6, r1]
- ldr r7, [lr, r7, lsl #2]
- mul r7, r2, r7
- tst r1, #7 @ avoid using r7 directly after
- str r7, [r0, -r5]!
- subne r1, r1, #1
- ldrbne r7, [r6, r1]
- bne Lrow4bpplp
- ldmfd sp!, {r4 - r7, pc}
-
-@
-@ Smashable regs: {r0 - r3}, [r4], {r5 - r7}, (r8 - fp), [ip], (sp), {lr}, (pc)
-@
-Lrow8bpplp:
- mov ip, r7, lsr #4
- ldr ip, [lr, ip, lsl #2]
- mul r4, r2, ip
- and ip, r7, #15 @ avoid r4
- ldr ip, [lr, ip, lsl #2] @ avoid r4
- mul ip, r2, ip @ avoid r4
- sub r1, r1, #1 @ avoid ip
- sub r0, r0, r5 @ avoid ip
- stmia r0, {r4, ip}
- ldrb r7, [r6, r1]
- mov ip, r7, lsr #4
- ldr ip, [lr, ip, lsl #2]
- mul r4, r2, ip
- and ip, r7, #15 @ avoid r4
- ldr ip, [lr, ip, lsl #2] @ avoid r4
- mul ip, r2, ip @ avoid r4
- tst r1, #7 @ avoid ip
- sub r0, r0, r5 @ avoid ip
- stmia r0, {r4, ip}
- subne r1, r1, #1
- ldrbne r7, [r6, r1]
- bne Lrow8bpplp
- ldmfd sp!, {r4 - r7, pc}
-
-@
-@ Smashable regs: {r0 - r3}, [r4], {r5, r6}, [r7], (r8 - fp), [ip], (sp), [lr], (pc)
-@
-Lrow1bpp:
- add r6, r6, r1
- ldmia r6, {r4, r7}
- strb r4, [r0], r5
- mov r4, r4, lsr #8
- strb r4, [r0], r5
- mov r4, r4, lsr #8
- strb r4, [r0], r5
- mov r4, r4, lsr #8
- strb r4, [r0], r5
- strb r7, [r0], r5
- mov r7, r7, lsr #8
- strb r7, [r0], r5
- mov r7, r7, lsr #8
- strb r7, [r0], r5
- mov r7, r7, lsr #8
- strb r7, [r0], r5
- ldmfd sp!, {r4 - r7, pc}
-
- .bss
-ENTRY(con_charconvtable)
- .space 1024
diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig
deleted file mode 100644
index edb52d56f679..000000000000
--- a/arch/arm/configs/rpc_defconfig
+++ /dev/null
@@ -1,127 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_ARCH_MULTI_V4=y
-# CONFIG_ARCH_MULTI_V7 is not set
-CONFIG_ARCH_RPC=y
-CONFIG_CPU_SA110=y
-CONFIG_FPE_NWFPE=y
-# CONFIG_AEABI is not set
-CONFIG_ATAGS=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET6_XFRM_MODE_BEET is not set
-CONFIG_PARPORT=y
-CONFIG_PARPORT_PC=y
-CONFIG_PARPORT_PC_FIFO=y
-CONFIG_BLK_DEV_FD=y
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-CONFIG_BLK_DEV_SR=y
-CONFIG_CHR_DEV_SG=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_ARXESCSI=m
-CONFIG_SCSI_CUMANA_2=m
-CONFIG_SCSI_EESOXSCSI=m
-CONFIG_SCSI_POWERTECSCSI=y
-CONFIG_SCSI_CUMANA_1=m
-CONFIG_SCSI_OAK1=m
-CONFIG_ATA=y
-CONFIG_PATA_ICSIDE=y
-CONFIG_PATA_PLATFORM=y
-CONFIG_NETDEVICES=y
-CONFIG_ARM_ETHER1=y
-CONFIG_ARM_ETHER3=y
-CONFIG_ARM_ETHERH=y
-CONFIG_PPP=m
-CONFIG_PPPOE=m
-CONFIG_INPUT_EVDEV=y
-# CONFIG_MOUSE_PS2 is not set
-CONFIG_MOUSE_RISCPC=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_LEGACY_PTY_COUNT=64
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=16
-CONFIG_SERIAL_8250_RUNTIME_UARTS=8
-CONFIG_SERIAL_8250_ACORN=y
-CONFIG_PRINTER=m
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_ACORN=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_SOUND=m
-CONFIG_SOUND_PRIME=m
-CONFIG_SOUND_OSS=m
-CONFIG_SOUND_VIDC=m
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_PCF8583=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT4_FS=y
-CONFIG_AUTOFS_FS=m
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_ADFS_FS=y
-CONFIG_NFS_FS=y
-# CONFIG_ACORN_PARTITION_CUMANA is not set
-# CONFIG_ACORN_PARTITION_EESOX is not set
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_FONTS=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_ACORN_8x8=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_UART_8250=y
diff --git a/arch/arm/include/asm/ecard.h b/arch/arm/include/asm/ecard.h
deleted file mode 100644
index 7cbe001bf9cc..000000000000
--- a/arch/arm/include/asm/ecard.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/include/asm/ecard.h
- *
- * definitions for expansion cards
- *
- * This is a new system as from Linux 1.2.3
- *
- * Changelog:
- * 11-12-1996 RMK Further minor improvements
- * 12-09-1997 RMK Added interrupt enable/disable for card level
- *
- * Reference: Acorns Risc OS 3 Programmers Reference Manuals.
- */
-
-#ifndef __ASM_ECARD_H
-#define __ASM_ECARD_H
-
-/*
- * Currently understood cards (but not necessarily
- * supported):
- * Manufacturer Product ID
- */
-#define MANU_ACORN 0x0000
-#define PROD_ACORN_SCSI 0x0002
-#define PROD_ACORN_ETHER1 0x0003
-#define PROD_ACORN_MFM 0x000b
-
-#define MANU_ANT2 0x0011
-#define PROD_ANT_ETHER3 0x00a4
-
-#define MANU_ATOMWIDE 0x0017
-#define PROD_ATOMWIDE_3PSERIAL 0x0090
-
-#define MANU_IRLAM_INSTRUMENTS 0x001f
-#define MANU_IRLAM_INSTRUMENTS_ETHERN 0x5678
-
-#define MANU_OAK 0x0021
-#define PROD_OAK_SCSI 0x0058
-
-#define MANU_MORLEY 0x002b
-#define PROD_MORLEY_SCSI_UNCACHED 0x0067
-
-#define MANU_CUMANA 0x003a
-#define PROD_CUMANA_SCSI_2 0x003a
-#define PROD_CUMANA_SCSI_1 0x00a0
-
-#define MANU_ICS 0x003c
-#define PROD_ICS_IDE 0x00ae
-
-#define MANU_ICS2 0x003d
-#define PROD_ICS2_IDE 0x00ae
-
-#define MANU_SERPORT 0x003f
-#define PROD_SERPORT_DSPORT 0x00b9
-
-#define MANU_ARXE 0x0041
-#define PROD_ARXE_SCSI 0x00be
-
-#define MANU_I3 0x0046
-#define PROD_I3_ETHERLAN500 0x00d4
-#define PROD_I3_ETHERLAN600 0x00ec
-#define PROD_I3_ETHERLAN600A 0x011e
-
-#define MANU_ANT 0x0053
-#define PROD_ANT_ETHERM 0x00d8
-#define PROD_ANT_ETHERB 0x00e4
-
-#define MANU_ALSYSTEMS 0x005b
-#define PROD_ALSYS_SCSIATAPI 0x0107
-
-#define MANU_MCS 0x0063
-#define PROD_MCS_CONNECT32 0x0125
-
-#define MANU_EESOX 0x0064
-#define PROD_EESOX_SCSI2 0x008c
-
-#define MANU_YELLOWSTONE 0x0096
-#define PROD_YELLOWSTONE_RAPIDE32 0x0120
-
-#ifdef ECARD_C
-#define CONST
-#else
-#define CONST const
-#endif
-
-#define MAX_ECARDS 9
-
-struct ecard_id { /* Card ID structure */
- unsigned short manufacturer;
- unsigned short product;
- void *data;
-};
-
-struct in_ecid { /* Packed card ID information */
- unsigned short product; /* Product code */
- unsigned short manufacturer; /* Manufacturer code */
- unsigned char id:4; /* Simple ID */
- unsigned char cd:1; /* Chunk dir present */
- unsigned char is:1; /* Interrupt status pointers */
- unsigned char w:2; /* Width */
- unsigned char country; /* Country */
- unsigned char irqmask; /* IRQ mask */
- unsigned char fiqmask; /* FIQ mask */
- unsigned long irqoff; /* IRQ offset */
- unsigned long fiqoff; /* FIQ offset */
-};
-
-typedef struct expansion_card ecard_t;
-typedef unsigned long *loader_t;
-
-typedef struct expansion_card_ops { /* Card handler routines */
- void (*irqenable)(ecard_t *ec, int irqnr);
- void (*irqdisable)(ecard_t *ec, int irqnr);
- int (*irqpending)(ecard_t *ec);
- void (*fiqenable)(ecard_t *ec, int fiqnr);
- void (*fiqdisable)(ecard_t *ec, int fiqnr);
- int (*fiqpending)(ecard_t *ec);
-} expansioncard_ops_t;
-
-#define ECARD_NUM_RESOURCES (6)
-
-#define ECARD_RES_IOCSLOW (0)
-#define ECARD_RES_IOCMEDIUM (1)
-#define ECARD_RES_IOCFAST (2)
-#define ECARD_RES_IOCSYNC (3)
-#define ECARD_RES_MEMC (4)
-#define ECARD_RES_EASI (5)
-
-#define ecard_resource_start(ec,nr) ((ec)->resource[nr].start)
-#define ecard_resource_end(ec,nr) ((ec)->resource[nr].end)
-#define ecard_resource_len(ec,nr) ((ec)->resource[nr].end - \
- (ec)->resource[nr].start + 1)
-#define ecard_resource_flags(ec,nr) ((ec)->resource[nr].flags)
-
-/*
- * This contains all the info needed on an expansion card
- */
-struct expansion_card {
- struct expansion_card *next;
-
- struct device dev;
- struct resource resource[ECARD_NUM_RESOURCES];
-
- /* Public data */
- void __iomem *irqaddr; /* address of IRQ register */
- void __iomem *fiqaddr; /* address of FIQ register */
- unsigned char irqmask; /* IRQ mask */
- unsigned char fiqmask; /* FIQ mask */
- unsigned char claimed; /* Card claimed? */
- unsigned char easi; /* EASI card */
-
- void *irq_data; /* Data for use for IRQ by card */
- void *fiq_data; /* Data for use for FIQ by card */
- const expansioncard_ops_t *ops; /* Enable/Disable Ops for card */
-
- CONST unsigned int slot_no; /* Slot number */
- CONST unsigned int dma; /* DMA number (for request_dma) */
- CONST unsigned int irq; /* IRQ number (for request_irq) */
- CONST unsigned int fiq; /* FIQ number (for request_irq) */
- CONST struct in_ecid cid; /* Card Identification */
-
- /* Private internal data */
- const char *card_desc; /* Card description */
- CONST loader_t loader; /* loader program */
- u64 dma_mask;
-};
-
-void ecard_setirq(struct expansion_card *ec, const struct expansion_card_ops *ops, void *irq_data);
-
-struct in_chunk_dir {
- unsigned int start_offset;
- union {
- unsigned char string[256];
- unsigned char data[1];
- } d;
-};
-
-/*
- * Read a chunk from an expansion card
- * cd : where to put read data
- * ec : expansion card info struct
- * id : id number to find
- * num: (n+1)'th id to find.
- */
-extern int ecard_readchunk (struct in_chunk_dir *cd, struct expansion_card *ec, int id, int num);
-
-/*
- * Request and release ecard resources
- */
-extern int ecard_request_resources(struct expansion_card *ec);
-extern void ecard_release_resources(struct expansion_card *ec);
-
-void __iomem *ecardm_iomap(struct expansion_card *ec, unsigned int res,
- unsigned long offset, unsigned long maxsize);
-#define ecardm_iounmap(__ec, __addr) devm_iounmap(&(__ec)->dev, __addr)
-
-extern const struct bus_type ecard_bus_type;
-
-#define ECARD_DEV(_d) container_of((_d), struct expansion_card, dev)
-
-struct ecard_driver {
- int (*probe)(struct expansion_card *, const struct ecard_id *id);
- void (*remove)(struct expansion_card *);
- void (*shutdown)(struct expansion_card *);
- const struct ecard_id *id_table;
- unsigned int id;
- struct device_driver drv;
-};
-
-#define ECARD_DRV(_d) container_of((_d), struct ecard_driver, drv)
-
-#define ecard_set_drvdata(ec,data) dev_set_drvdata(&(ec)->dev, (data))
-#define ecard_get_drvdata(ec) dev_get_drvdata(&(ec)->dev)
-
-int ecard_register_driver(struct ecard_driver *);
-void ecard_remove_driver(struct ecard_driver *);
-
-#endif
diff --git a/arch/arm/include/asm/hardware/ioc.h b/arch/arm/include/asm/hardware/ioc.h
deleted file mode 100644
index 6edd27fcd048..000000000000
--- a/arch/arm/include/asm/hardware/ioc.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/include/asm/hardware/ioc.h
- *
- * Copyright (C) Russell King
- *
- * Use these macros to read/write the IOC. All it does is perform the actual
- * read/write.
- */
-#ifndef __ASMARM_HARDWARE_IOC_H
-#define __ASMARM_HARDWARE_IOC_H
-
-#ifndef __ASSEMBLY__
-
-/*
- * We use __raw_base variants here so that we give the compiler the
- * chance to keep IOC_BASE in a register.
- */
-#define ioc_readb(off) __raw_readb(IOC_BASE + (off))
-#define ioc_writeb(val,off) __raw_writeb(val, IOC_BASE + (off))
-
-#endif
-
-#define IOC_CONTROL (0x00)
-#define IOC_KARTTX (0x04)
-#define IOC_KARTRX (0x04)
-
-#define IOC_IRQSTATA (0x10)
-#define IOC_IRQREQA (0x14)
-#define IOC_IRQCLRA (0x14)
-#define IOC_IRQMASKA (0x18)
-
-#define IOC_IRQSTATB (0x20)
-#define IOC_IRQREQB (0x24)
-#define IOC_IRQMASKB (0x28)
-
-#define IOC_FIQSTAT (0x30)
-#define IOC_FIQREQ (0x34)
-#define IOC_FIQMASK (0x38)
-
-#define IOC_T0CNTL (0x40)
-#define IOC_T0LTCHL (0x40)
-#define IOC_T0CNTH (0x44)
-#define IOC_T0LTCHH (0x44)
-#define IOC_T0GO (0x48)
-#define IOC_T0LATCH (0x4c)
-
-#define IOC_T1CNTL (0x50)
-#define IOC_T1LTCHL (0x50)
-#define IOC_T1CNTH (0x54)
-#define IOC_T1LTCHH (0x54)
-#define IOC_T1GO (0x58)
-#define IOC_T1LATCH (0x5c)
-
-#define IOC_T2CNTL (0x60)
-#define IOC_T2LTCHL (0x60)
-#define IOC_T2CNTH (0x64)
-#define IOC_T2LTCHH (0x64)
-#define IOC_T2GO (0x68)
-#define IOC_T2LATCH (0x6c)
-
-#define IOC_T3CNTL (0x70)
-#define IOC_T3LTCHL (0x70)
-#define IOC_T3CNTH (0x74)
-#define IOC_T3LTCHH (0x74)
-#define IOC_T3GO (0x78)
-#define IOC_T3LATCH (0x7c)
-
-#endif
diff --git a/arch/arm/include/asm/hardware/iomd.h b/arch/arm/include/asm/hardware/iomd.h
deleted file mode 100644
index 53006ba5350f..000000000000
--- a/arch/arm/include/asm/hardware/iomd.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/include/asm/hardware/iomd.h
- *
- * Copyright (C) 1999 Russell King
- *
- * This file contains information out the IOMD ASIC used in the
- * Acorn RiscPC and subsequently integrated into the CLPS7500 chips.
- */
-#ifndef __ASMARM_HARDWARE_IOMD_H
-#define __ASMARM_HARDWARE_IOMD_H
-
-
-#ifndef __ASSEMBLY__
-
-/*
- * We use __raw_base variants here so that we give the compiler the
- * chance to keep IOC_BASE in a register.
- */
-#define iomd_readb(off) __raw_readb(IOMD_BASE + (off))
-#define iomd_readl(off) __raw_readl(IOMD_BASE + (off))
-#define iomd_writeb(val,off) __raw_writeb(val, IOMD_BASE + (off))
-#define iomd_writel(val,off) __raw_writel(val, IOMD_BASE + (off))
-
-#endif
-
-#define IOMD_CONTROL (0x000)
-#define IOMD_KARTTX (0x004)
-#define IOMD_KARTRX (0x004)
-#define IOMD_KCTRL (0x008)
-
-#define IOMD_IRQSTATA (0x010)
-#define IOMD_IRQREQA (0x014)
-#define IOMD_IRQCLRA (0x014)
-#define IOMD_IRQMASKA (0x018)
-
-#define IOMD_IRQSTATB (0x020)
-#define IOMD_IRQREQB (0x024)
-#define IOMD_IRQMASKB (0x028)
-
-#define IOMD_FIQSTAT (0x030)
-#define IOMD_FIQREQ (0x034)
-#define IOMD_FIQMASK (0x038)
-
-#define IOMD_T0CNTL (0x040)
-#define IOMD_T0LTCHL (0x040)
-#define IOMD_T0CNTH (0x044)
-#define IOMD_T0LTCHH (0x044)
-#define IOMD_T0GO (0x048)
-#define IOMD_T0LATCH (0x04c)
-
-#define IOMD_T1CNTL (0x050)
-#define IOMD_T1LTCHL (0x050)
-#define IOMD_T1CNTH (0x054)
-#define IOMD_T1LTCHH (0x054)
-#define IOMD_T1GO (0x058)
-#define IOMD_T1LATCH (0x05c)
-
-#define IOMD_ROMCR0 (0x080)
-#define IOMD_ROMCR1 (0x084)
-#ifdef CONFIG_ARCH_RPC
-#define IOMD_DRAMCR (0x088)
-#endif
-#define IOMD_REFCR (0x08C)
-
-#define IOMD_FSIZE (0x090)
-#define IOMD_ID0 (0x094)
-#define IOMD_ID1 (0x098)
-#define IOMD_VERSION (0x09C)
-
-#ifdef CONFIG_ARCH_RPC
-#define IOMD_MOUSEX (0x0A0)
-#define IOMD_MOUSEY (0x0A4)
-#endif
-
-#ifdef CONFIG_ARCH_RPC
-#define IOMD_DMATCR (0x0C0)
-#endif
-#define IOMD_IOTCR (0x0C4)
-#define IOMD_ECTCR (0x0C8)
-#ifdef CONFIG_ARCH_RPC
-#define IOMD_DMAEXT (0x0CC)
-#endif
-
-#ifdef CONFIG_ARCH_RPC
-#define DMA_EXT_IO0 1
-#define DMA_EXT_IO1 2
-#define DMA_EXT_IO2 4
-#define DMA_EXT_IO3 8
-
-#define IOMD_IO0CURA (0x100)
-#define IOMD_IO0ENDA (0x104)
-#define IOMD_IO0CURB (0x108)
-#define IOMD_IO0ENDB (0x10C)
-#define IOMD_IO0CR (0x110)
-#define IOMD_IO0ST (0x114)
-
-#define IOMD_IO1CURA (0x120)
-#define IOMD_IO1ENDA (0x124)
-#define IOMD_IO1CURB (0x128)
-#define IOMD_IO1ENDB (0x12C)
-#define IOMD_IO1CR (0x130)
-#define IOMD_IO1ST (0x134)
-
-#define IOMD_IO2CURA (0x140)
-#define IOMD_IO2ENDA (0x144)
-#define IOMD_IO2CURB (0x148)
-#define IOMD_IO2ENDB (0x14C)
-#define IOMD_IO2CR (0x150)
-#define IOMD_IO2ST (0x154)
-
-#define IOMD_IO3CURA (0x160)
-#define IOMD_IO3ENDA (0x164)
-#define IOMD_IO3CURB (0x168)
-#define IOMD_IO3ENDB (0x16C)
-#define IOMD_IO3CR (0x170)
-#define IOMD_IO3ST (0x174)
-#endif
-
-#define IOMD_SD0CURA (0x180)
-#define IOMD_SD0ENDA (0x184)
-#define IOMD_SD0CURB (0x188)
-#define IOMD_SD0ENDB (0x18C)
-#define IOMD_SD0CR (0x190)
-#define IOMD_SD0ST (0x194)
-
-#ifdef CONFIG_ARCH_RPC
-#define IOMD_SD1CURA (0x1A0)
-#define IOMD_SD1ENDA (0x1A4)
-#define IOMD_SD1CURB (0x1A8)
-#define IOMD_SD1ENDB (0x1AC)
-#define IOMD_SD1CR (0x1B0)
-#define IOMD_SD1ST (0x1B4)
-#endif
-
-#define IOMD_CURSCUR (0x1C0)
-#define IOMD_CURSINIT (0x1C4)
-
-#define IOMD_VIDCUR (0x1D0)
-#define IOMD_VIDEND (0x1D4)
-#define IOMD_VIDSTART (0x1D8)
-#define IOMD_VIDINIT (0x1DC)
-#define IOMD_VIDCR (0x1E0)
-
-#define IOMD_DMASTAT (0x1F0)
-#define IOMD_DMAREQ (0x1F4)
-#define IOMD_DMAMASK (0x1F8)
-
-#define DMA_END_S (1 << 31)
-#define DMA_END_L (1 << 30)
-
-#define DMA_CR_C 0x80
-#define DMA_CR_D 0x40
-#define DMA_CR_E 0x20
-
-#define DMA_ST_OFL 4
-#define DMA_ST_INT 2
-#define DMA_ST_AB 1
-
-/*
- * DMA (MEMC) compatibility
- */
-#define HALF_SAM vram_half_sam
-#define VDMA_ALIGNMENT (HALF_SAM * 2)
-#define VDMA_XFERSIZE (HALF_SAM)
-#define VDMA_INIT IOMD_VIDINIT
-#define VDMA_START IOMD_VIDSTART
-#define VDMA_END IOMD_VIDEND
-
-#ifndef __ASSEMBLY__
-extern unsigned int vram_half_sam;
-#define video_set_dma(start,end,offset) \
-do { \
- outl (SCREEN_START + start, VDMA_START); \
- outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END); \
- if (offset >= end - VDMA_XFERSIZE) \
- offset |= 0x40000000; \
- outl (SCREEN_START + offset, VDMA_INIT); \
-} while (0)
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/hardware/memc.h b/arch/arm/include/asm/hardware/memc.h
deleted file mode 100644
index 1d4ebe0a9678..000000000000
--- a/arch/arm/include/asm/hardware/memc.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/include/asm/hardware/memc.h
- *
- * Copyright (C) Russell King.
- */
-#define VDMA_ALIGNMENT PAGE_SIZE
-#define VDMA_XFERSIZE 16
-#define VDMA_INIT 0
-#define VDMA_START 1
-#define VDMA_END 2
-
-#ifndef __ASSEMBLY__
-extern void memc_write(unsigned int reg, unsigned long val);
-
-#define video_set_dma(start,end,offset) \
-do { \
- memc_write (VDMA_START, (start >> 2)); \
- memc_write (VDMA_END, (end - VDMA_XFERSIZE) >> 2); \
- memc_write (VDMA_INIT, (offset >> 2)); \
-} while (0)
-
-#endif
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index e6bd9e79737c..c3661af2ca2a 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -207,16 +207,13 @@ void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size);
/*
* Now, pick up the machine-defined IO definitions
*/
-#ifdef CONFIG_NEED_MACH_IO_H
-#include <mach/io.h>
-#else
#if IS_ENABLED(CONFIG_PCMCIA) || defined(CONFIG_PCI)
#define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
#else
#define IO_SPACE_LIMIT ((resource_size_t)0)
#endif
+
#define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
-#endif
/*
* IO port access primitives
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 7c2fa7dcec6d..e10363ebdd1f 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -20,9 +20,6 @@
#include <linux/types.h>
#include <linux/sizes.h>
-#ifdef CONFIG_NEED_MACH_MEMORY_H
-#include <mach/memory.h>
-#endif
#include <asm/kasan_def.h>
/*
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 42cae73fcc19..3cbbcdb63f7d 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -221,19 +221,6 @@ str_p2: .asciz ").\n"
ENDPROC(__error_p)
__error:
-#ifdef CONFIG_ARCH_RPC
-/*
- * Turn the screen red on a error - RiscPC only.
- */
- mov r0, #0x02000000
- mov r3, #0x11
- orr r3, r3, r3, lsl #8
- orr r3, r3, r3, lsl #16
- str r3, [r0], #4
- str r3, [r0], #4
- str r3, [r0], #4
- str r3, [r0], #4
-#endif
1: mov r0, r0
b 1b
ENDPROC(__error)
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index b12fe41e579b..2ffaea2c4c9b 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -347,18 +347,6 @@ __create_page_tables:
/* we don't need any serial debugging mappings */
ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
#endif
-#ifdef CONFIG_ARCH_RPC
- /*
- * Map in screen at 0x02000000 & SCREEN2_BASE
- * Similar reasons here - for debug. This is
- * only for Acorn RiscPC architectures.
- */
- add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
- orr r3, r7, #0x02000000
- str r3, [r0]
- add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
- str r3, [r0]
-#endif
#endif
#ifdef CONFIG_ARM_LPAE
sub r4, r4, #0x1000 @ point to the PGD table
diff --git a/arch/arm/lib/delay-loop.S b/arch/arm/lib/delay-loop.S
index 33b08ca1c242..56f9eea56268 100644
--- a/arch/arm/lib/delay-loop.S
+++ b/arch/arm/lib/delay-loop.S
@@ -9,10 +9,6 @@
#include <asm/assembler.h>
#include <asm/delay.h>
-#ifdef CONFIG_ARCH_RPC
- .arch armv4
-#endif
-
.text
.LC0: .word loops_per_jiffy
diff --git a/arch/arm/mach-rpc/Kconfig b/arch/arm/mach-rpc/Kconfig
deleted file mode 100644
index 60b3823b690c..000000000000
--- a/arch/arm/mach-rpc/Kconfig
+++ /dev/null
@@ -1,24 +0,0 @@
-config ARCH_RPC
- bool "RiscPC (DEPRECATED)"
- depends on ARCH_MULTI_V4 && !(ARCH_MULTI_V4T || ARCH_MULTI_V5)
- depends on !(ARCH_FOOTBRIDGE || ARCH_SA1100 || ARCH_MOXART || ARCH_GEMINI)
- depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000
- depends on CPU_LITTLE_ENDIAN
- depends on ATAGS
- depends on MMU
- select ARCH_ACORN
- select ARCH_MAY_HAVE_PC_FDC
- select CPU_SA110
- select FIQ
- select HAVE_PATA_PLATFORM
- select ISA_DMA_API
- select LEGACY_TIMER_TICK
- select NEED_MACH_IO_H
- select NEED_MACH_MEMORY_H
- select NO_IOPORT_MAP
- help
- On the Acorn Risc-PC, Linux can support the internal IDE disk and
- CD-ROM interface, serial and parallel port, and the floppy drive.
-
- Support for these machines will go away in 2027,
- unless there are any remaining users that speak up.
diff --git a/arch/arm/mach-rpc/Makefile b/arch/arm/mach-rpc/Makefile
deleted file mode 100644
index 90a645a18444..000000000000
--- a/arch/arm/mach-rpc/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-obj-y :=dma.o ecard.o ecard-loader.o fiq.o floppydma.o io-acorn.o irq.o \
- riscpc.o time.o
diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c
deleted file mode 100644
index 50e0f97afd75..000000000000
--- a/arch/arm/mach-rpc/dma.c
+++ /dev/null
@@ -1,393 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-rpc/dma.c
- *
- * Copyright (C) 1998 Russell King
- *
- * DMA functions specific to RiscPC architecture
- */
-#include <linux/mman.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/dma-mapping.h>
-#include <linux/io.h>
-
-#include <asm/page.h>
-#include <asm/dma.h>
-#include <asm/fiq.h>
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <linux/uaccess.h>
-
-#include <asm/mach/dma.h>
-#include <asm/hardware/iomd.h>
-
-struct iomd_dma {
- struct dma_struct dma;
- void __iomem *base; /* Controller base address */
- int irq; /* Controller IRQ */
- unsigned int state;
- dma_addr_t cur_addr;
- unsigned int cur_len;
- dma_addr_t dma_addr;
- unsigned int dma_len;
-};
-
-#if 0
-typedef enum {
- dma_size_8 = 1,
- dma_size_16 = 2,
- dma_size_32 = 4,
- dma_size_128 = 16
-} dma_size_t;
-#endif
-
-#define TRANSFER_SIZE 2
-
-#define CURA (0)
-#define ENDA (IOMD_IO0ENDA - IOMD_IO0CURA)
-#define CURB (IOMD_IO0CURB - IOMD_IO0CURA)
-#define ENDB (IOMD_IO0ENDB - IOMD_IO0CURA)
-#define CR (IOMD_IO0CR - IOMD_IO0CURA)
-#define ST (IOMD_IO0ST - IOMD_IO0CURA)
-
-static void iomd_get_next_sg(struct iomd_dma *idma)
-{
- unsigned long end, offset, flags = 0;
-
- if (idma->dma.sg) {
- idma->cur_addr = idma->dma_addr;
- offset = idma->cur_addr & ~PAGE_MASK;
-
- end = offset + idma->dma_len;
-
- if (end > PAGE_SIZE)
- end = PAGE_SIZE;
-
- if (offset + TRANSFER_SIZE >= end)
- flags |= DMA_END_L;
-
- idma->cur_len = end - TRANSFER_SIZE;
-
- idma->dma_len -= end - offset;
- idma->dma_addr += end - offset;
-
- if (idma->dma_len == 0) {
- if (idma->dma.sgcount > 1) {
- idma->dma.sg = sg_next(idma->dma.sg);
- idma->dma_addr = idma->dma.sg->dma_address;
- idma->dma_len = idma->dma.sg->length;
- idma->dma.sgcount--;
- } else {
- idma->dma.sg = NULL;
- flags |= DMA_END_S;
- }
- }
- } else {
- flags = DMA_END_S | DMA_END_L;
- idma->cur_addr = 0;
- idma->cur_len = 0;
- }
-
- idma->cur_len |= flags;
-}
-
-static irqreturn_t iomd_dma_handle(int irq, void *dev_id)
-{
- struct iomd_dma *idma = dev_id;
- void __iomem *base = idma->base;
- unsigned int state = idma->state;
- unsigned int status, cur, end;
-
- do {
- status = readb(base + ST);
- if (!(status & DMA_ST_INT))
- goto out;
-
- if ((state ^ status) & DMA_ST_AB)
- iomd_get_next_sg(idma);
-
- // This efficiently implements state = OFL != AB ? AB : 0
- state = ((status >> 2) ^ status) & DMA_ST_AB;
- if (state) {
- cur = CURA;
- end = ENDA;
- } else {
- cur = CURB;
- end = ENDB;
- }
- writel(idma->cur_addr, base + cur);
- writel(idma->cur_len, base + end);
-
- if (status & DMA_ST_OFL &&
- idma->cur_len == (DMA_END_S|DMA_END_L))
- break;
- } while (1);
-
- state = ~DMA_ST_AB;
- disable_irq_nosync(irq);
-out:
- idma->state = state;
- return IRQ_HANDLED;
-}
-
-static int iomd_request_dma(unsigned int chan, dma_t *dma)
-{
- struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
-
- return request_irq(idma->irq, iomd_dma_handle,
- 0, idma->dma.device_id, idma);
-}
-
-static void iomd_free_dma(unsigned int chan, dma_t *dma)
-{
- struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
-
- free_irq(idma->irq, idma);
-}
-
-static struct device isa_dma_dev = {
- .init_name = "fallback device",
- .coherent_dma_mask = ~(dma_addr_t)0,
- .dma_mask = &isa_dma_dev.coherent_dma_mask,
-};
-
-static void iomd_enable_dma(unsigned int chan, dma_t *dma)
-{
- struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
- void __iomem *base = idma->base;
- unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E;
-
- if (idma->dma.invalid) {
- idma->dma.invalid = 0;
-
- /*
- * Cope with ISA-style drivers which expect cache
- * coherence.
- */
- if (!idma->dma.sg) {
- idma->dma.sg = &idma->dma.buf;
- idma->dma.sgcount = 1;
- idma->dma.buf.length = idma->dma.count;
- idma->dma.buf.dma_address = dma_map_single(&isa_dma_dev,
- idma->dma.addr, idma->dma.count,
- idma->dma.dma_mode == DMA_MODE_READ ?
- DMA_FROM_DEVICE : DMA_TO_DEVICE);
- }
-
- idma->dma_addr = idma->dma.sg->dma_address;
- idma->dma_len = idma->dma.sg->length;
-
- writeb(DMA_CR_C, base + CR);
- idma->state = DMA_ST_AB;
- }
-
- if (idma->dma.dma_mode == DMA_MODE_READ)
- ctrl |= DMA_CR_D;
-
- writeb(ctrl, base + CR);
- enable_irq(idma->irq);
-}
-
-static void iomd_disable_dma(unsigned int chan, dma_t *dma)
-{
- struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
- void __iomem *base = idma->base;
- unsigned long flags;
-
- local_irq_save(flags);
- if (idma->state != ~DMA_ST_AB)
- disable_irq(idma->irq);
- writeb(0, base + CR);
- local_irq_restore(flags);
-}
-
-static int iomd_set_dma_speed(unsigned int chan, dma_t *dma, int cycle)
-{
- int tcr, speed;
-
- if (cycle < 188)
- speed = 3;
- else if (cycle <= 250)
- speed = 2;
- else if (cycle < 438)
- speed = 1;
- else
- speed = 0;
-
- tcr = iomd_readb(IOMD_DMATCR);
- speed &= 3;
-
- switch (chan) {
- case DMA_0:
- tcr = (tcr & ~0x03) | speed;
- break;
-
- case DMA_1:
- tcr = (tcr & ~0x0c) | (speed << 2);
- break;
-
- case DMA_2:
- tcr = (tcr & ~0x30) | (speed << 4);
- break;
-
- case DMA_3:
- tcr = (tcr & ~0xc0) | (speed << 6);
- break;
-
- default:
- break;
- }
-
- iomd_writeb(tcr, IOMD_DMATCR);
-
- return speed;
-}
-
-static struct dma_ops iomd_dma_ops = {
- .type = "IOMD",
- .request = iomd_request_dma,
- .free = iomd_free_dma,
- .enable = iomd_enable_dma,
- .disable = iomd_disable_dma,
- .setspeed = iomd_set_dma_speed,
-};
-
-static struct fiq_handler fh = {
- .name = "floppydma"
-};
-
-struct floppy_dma {
- struct dma_struct dma;
- unsigned int fiq;
-};
-
-static void floppy_enable_dma(unsigned int chan, dma_t *dma)
-{
- struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma);
- void *fiqhandler_start;
- unsigned int fiqhandler_length;
- struct pt_regs regs;
-
- if (fdma->dma.sg)
- BUG();
-
- if (fdma->dma.dma_mode == DMA_MODE_READ) {
- extern unsigned char floppy_fiqin_start, floppy_fiqin_end;
- fiqhandler_start = &floppy_fiqin_start;
- fiqhandler_length = &floppy_fiqin_end - &floppy_fiqin_start;
- } else {
- extern unsigned char floppy_fiqout_start, floppy_fiqout_end;
- fiqhandler_start = &floppy_fiqout_start;
- fiqhandler_length = &floppy_fiqout_end - &floppy_fiqout_start;
- }
-
- regs.ARM_r9 = fdma->dma.count;
- regs.ARM_r10 = (unsigned long)fdma->dma.addr;
- regs.ARM_fp = (unsigned long)FLOPPYDMA_BASE;
-
- if (claim_fiq(&fh)) {
- printk("floppydma: couldn't claim FIQ.\n");
- return;
- }
-
- set_fiq_handler(fiqhandler_start, fiqhandler_length);
- set_fiq_regs(®s);
- enable_fiq(fdma->fiq);
-}
-
-static void floppy_disable_dma(unsigned int chan, dma_t *dma)
-{
- struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma);
- disable_fiq(fdma->fiq);
- release_fiq(&fh);
-}
-
-static int floppy_get_residue(unsigned int chan, dma_t *dma)
-{
- struct pt_regs regs;
- get_fiq_regs(®s);
- return regs.ARM_r9;
-}
-
-static struct dma_ops floppy_dma_ops = {
- .type = "FIQDMA",
- .enable = floppy_enable_dma,
- .disable = floppy_disable_dma,
- .residue = floppy_get_residue,
-};
-
-/*
- * This is virtual DMA - we don't need anything here.
- */
-static void sound_enable_disable_dma(unsigned int chan, dma_t *dma)
-{
-}
-
-static struct dma_ops sound_dma_ops = {
- .type = "VIRTUAL",
- .enable = sound_enable_disable_dma,
- .disable = sound_enable_disable_dma,
-};
-
-static struct iomd_dma iomd_dma[6];
-
-static struct floppy_dma floppy_dma = {
- .dma = {
- .d_ops = &floppy_dma_ops,
- },
- .fiq = FIQ_FLOPPYDATA,
-};
-
-static dma_t sound_dma = {
- .d_ops = &sound_dma_ops,
-};
-
-static int __init rpc_dma_init(void)
-{
- unsigned int i;
- int ret;
-
- iomd_writeb(0, IOMD_IO0CR);
- iomd_writeb(0, IOMD_IO1CR);
- iomd_writeb(0, IOMD_IO2CR);
- iomd_writeb(0, IOMD_IO3CR);
-
- iomd_writeb(0xa0, IOMD_DMATCR);
-
- /*
- * Setup DMA channels 2,3 to be for podules
- * and channels 0,1 for internal devices
- */
- iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT);
-
- iomd_dma[DMA_0].base = IOMD_BASE + IOMD_IO0CURA;
- iomd_dma[DMA_0].irq = IRQ_DMA0;
- iomd_dma[DMA_1].base = IOMD_BASE + IOMD_IO1CURA;
- iomd_dma[DMA_1].irq = IRQ_DMA1;
- iomd_dma[DMA_2].base = IOMD_BASE + IOMD_IO2CURA;
- iomd_dma[DMA_2].irq = IRQ_DMA2;
- iomd_dma[DMA_3].base = IOMD_BASE + IOMD_IO3CURA;
- iomd_dma[DMA_3].irq = IRQ_DMA3;
- iomd_dma[DMA_S0].base = IOMD_BASE + IOMD_SD0CURA;
- iomd_dma[DMA_S0].irq = IRQ_DMAS0;
- iomd_dma[DMA_S1].base = IOMD_BASE + IOMD_SD1CURA;
- iomd_dma[DMA_S1].irq = IRQ_DMAS1;
-
- for (i = DMA_0; i <= DMA_S1; i++) {
- iomd_dma[i].dma.d_ops = &iomd_dma_ops;
-
- ret = isa_dma_add(i, &iomd_dma[i].dma);
- if (ret)
- printk("IOMDDMA%u: unable to register: %d\n", i, ret);
- }
-
- ret = isa_dma_add(DMA_VIRTUAL_FLOPPY, &floppy_dma.dma);
- if (ret)
- printk("IOMDFLOPPY: unable to register: %d\n", ret);
- ret = isa_dma_add(DMA_VIRTUAL_SOUND, &sound_dma);
- if (ret)
- printk("IOMDSOUND: unable to register: %d\n", ret);
- return 0;
-}
-core_initcall(rpc_dma_init);
diff --git a/arch/arm/mach-rpc/ecard-loader.S b/arch/arm/mach-rpc/ecard-loader.S
deleted file mode 100644
index eb8ac0412da6..000000000000
--- a/arch/arm/mach-rpc/ecard-loader.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * linux/arch/arm/lib/ecard.S
- *
- * Copyright (C) 1995, 1996 Russell King
- *
- * 27/03/03 Ian Molton Clean up CONFIG_CPU
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-
-#define CPSR2SPSR(rt) \
- mrs rt, cpsr; \
- msr spsr_cxsf, rt
-
-@ Purpose: call an expansion card loader to read bytes.
-@ Proto : char read_loader(int offset, char *card_base, char *loader);
-@ Returns: byte read
-
-ENTRY(ecard_loader_read)
- stmfd sp!, {r4 - r12, lr}
- mov r11, r1
- mov r1, r0
- CPSR2SPSR(r0)
- mov lr, pc
- mov pc, r2
- ldmfd sp!, {r4 - r12, pc}
-
-@ Purpose: call an expansion card loader to reset the card
-@ Proto : void read_loader(int card_base, char *loader);
-@ Returns: byte read
-
-ENTRY(ecard_loader_reset)
- stmfd sp!, {r4 - r12, lr}
- mov r11, r0
- CPSR2SPSR(r0)
- mov lr, pc
- add pc, r1, #8
- ldmfd sp!, {r4 - r12, pc}
-
diff --git a/arch/arm/mach-rpc/ecard.c b/arch/arm/mach-rpc/ecard.c
deleted file mode 100644
index 972465840548..000000000000
--- a/arch/arm/mach-rpc/ecard.c
+++ /dev/null
@@ -1,1146 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/kernel/ecard.c
- *
- * Copyright 1995-2001 Russell King
- *
- * Find all installed expansion cards, and handle interrupts from them.
- *
- * Created from information from Acorns RiscOS3 PRMs
- *
- * 08-Dec-1996 RMK Added code for the 9'th expansion card - the ether
- * podule slot.
- * 06-May-1997 RMK Added blacklist for cards whose loader doesn't work.
- * 12-Sep-1997 RMK Created new handling of interrupt enables/disables
- * - cards can now register their own routine to control
- * interrupts (recommended).
- * 29-Sep-1997 RMK Expansion card interrupt hardware not being re-enabled
- * on reset from Linux. (Caused cards not to respond
- * under RiscOS without hard reset).
- * 15-Feb-1998 RMK Added DMA support
- * 12-Sep-1998 RMK Added EASI support
- * 10-Jan-1999 RMK Run loaders in a simulated RISC OS environment.
- * 17-Apr-1999 RMK Support for EASI Type C cycles.
- */
-#define ECARD_C
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/sched/mm.h>
-#include <linux/interrupt.h>
-#include <linux/completion.h>
-#include <linux/reboot.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/device.h>
-#include <linux/init.h>
-#include <linux/mutex.h>
-#include <linux/kthread.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <asm/dma.h>
-#include <asm/ecard.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/mmu_context.h>
-#include <asm/mach/irq.h>
-#include <asm/tlbflush.h>
-
-#include "ecard.h"
-
-struct ecard_request {
- void (*fn)(struct ecard_request *);
- ecard_t *ec;
- unsigned int address;
- unsigned int length;
- unsigned int use_loader;
- void *buffer;
- struct completion *complete;
-};
-
-struct expcard_quirklist {
- unsigned short manufacturer;
- unsigned short product;
- const char *type;
- void (*init)(ecard_t *ec);
-};
-
-static ecard_t *cards;
-static ecard_t *slot_to_expcard[MAX_ECARDS];
-static unsigned int ectcr;
-
-static void atomwide_3p_quirk(ecard_t *ec);
-
-/* List of descriptions of cards which don't have an extended
- * identification, or chunk directories containing a description.
- */
-static struct expcard_quirklist quirklist[] __initdata = {
- { MANU_ACORN, PROD_ACORN_ETHER1, "Acorn Ether1" },
- { MANU_ATOMWIDE, PROD_ATOMWIDE_3PSERIAL, NULL, atomwide_3p_quirk },
-};
-
-asmlinkage extern int
-ecard_loader_reset(unsigned long base, loader_t loader);
-asmlinkage extern int
-ecard_loader_read(int off, unsigned long base, loader_t loader);
-
-static inline unsigned short ecard_getu16(unsigned char *v)
-{
- return v[0] | v[1] << 8;
-}
-
-static inline signed long ecard_gets24(unsigned char *v)
-{
- return v[0] | v[1] << 8 | v[2] << 16 | ((v[2] & 0x80) ? 0xff000000 : 0);
-}
-
-static inline ecard_t *slot_to_ecard(unsigned int slot)
-{
- return slot < MAX_ECARDS ? slot_to_expcard[slot] : NULL;
-}
-
-/* ===================== Expansion card daemon ======================== */
-/*
- * Since the loader programs on the expansion cards need to be run
- * in a specific environment, create a separate task with this
- * environment up, and pass requests to this task as and when we
- * need to.
- *
- * This should allow 99% of loaders to be called from Linux.
- *
- * From a security standpoint, we trust the card vendors. This
- * may be a misplaced trust.
- */
-static void ecard_task_reset(struct ecard_request *req)
-{
- struct expansion_card *ec = req->ec;
- struct resource *res;
-
- res = ec->slot_no == 8
- ? &ec->resource[ECARD_RES_MEMC]
- : ec->easi
- ? &ec->resource[ECARD_RES_EASI]
- : &ec->resource[ECARD_RES_IOCSYNC];
-
- ecard_loader_reset(res->start, ec->loader);
-}
-
-static void ecard_task_readbytes(struct ecard_request *req)
-{
- struct expansion_card *ec = req->ec;
- unsigned char *buf = req->buffer;
- unsigned int len = req->length;
- unsigned int off = req->address;
-
- if (ec->slot_no == 8) {
- void __iomem *base = (void __iomem *)
- ec->resource[ECARD_RES_MEMC].start;
-
- /*
- * The card maintains an index which increments the address
- * into a 4096-byte page on each access. We need to keep
- * track of the counter.
- */
- static unsigned int index;
- unsigned int page;
-
- page = (off >> 12) * 4;
- if (page > 256 * 4)
- return;
-
- off &= 4095;
-
- /*
- * If we are reading offset 0, or our current index is
- * greater than the offset, reset the hardware index counter.
- */
- if (off == 0 || index > off) {
- writeb(0, base);
- index = 0;
- }
-
- /*
- * Increment the hardware index counter until we get to the
- * required offset. The read bytes are discarded.
- */
- while (index < off) {
- readb(base + page);
- index += 1;
- }
-
- while (len--) {
- *buf++ = readb(base + page);
- index += 1;
- }
- } else {
- unsigned long base = (ec->easi
- ? &ec->resource[ECARD_RES_EASI]
- : &ec->resource[ECARD_RES_IOCSYNC])->start;
- void __iomem *pbase = (void __iomem *)base;
-
- if (!req->use_loader || !ec->loader) {
- off *= 4;
- while (len--) {
- *buf++ = readb(pbase + off);
- off += 4;
- }
- } else {
- while(len--) {
- /*
- * The following is required by some
- * expansion card loader programs.
- */
- *(unsigned long *)0x108 = 0;
- *buf++ = ecard_loader_read(off++, base,
- ec->loader);
- }
- }
- }
-
-}
-
-static DECLARE_WAIT_QUEUE_HEAD(ecard_wait);
-static struct ecard_request *ecard_req;
-static DEFINE_MUTEX(ecard_mutex);
-
-/*
- * Set up the expansion card daemon's page tables.
- */
-static void ecard_init_pgtables(struct mm_struct *mm)
-{
- struct vm_area_struct vma = TLB_FLUSH_VMA(mm, VM_EXEC);
-
- /* We want to set up the page tables for the following mapping:
- * Virtual Physical
- * 0x03000000 0x03000000
- * 0x03010000 unmapped
- * 0x03210000 0x03210000
- * 0x03400000 unmapped
- * 0x08000000 0x08000000
- * 0x10000000 unmapped
- *
- * FIXME: we don't follow this 100% yet.
- */
- pgd_t *src_pgd, *dst_pgd;
-
- src_pgd = pgd_offset(mm, (unsigned long)IO_BASE);
- dst_pgd = pgd_offset(mm, IO_START);
-
- memcpy(dst_pgd, src_pgd, sizeof(pgd_t) * (IO_SIZE / PGDIR_SIZE));
-
- src_pgd = pgd_offset(mm, (unsigned long)EASI_BASE);
- dst_pgd = pgd_offset(mm, EASI_START);
-
- memcpy(dst_pgd, src_pgd, sizeof(pgd_t) * (EASI_SIZE / PGDIR_SIZE));
-
- flush_tlb_range(&vma, IO_START, IO_START + IO_SIZE);
- flush_tlb_range(&vma, EASI_START, EASI_START + EASI_SIZE);
-}
-
-static int ecard_init_mm(void)
-{
- struct mm_struct * mm = mm_alloc();
- struct mm_struct *active_mm = current->active_mm;
-
- if (!mm)
- return -ENOMEM;
-
- current->mm = mm;
- current->active_mm = mm;
- activate_mm(active_mm, mm);
- mmdrop_lazy_tlb(active_mm);
- ecard_init_pgtables(mm);
- return 0;
-}
-
-static int
-ecard_task(void * unused)
-{
- /*
- * Allocate a mm. We're not a lazy-TLB kernel task since we need
- * to set page table entries where the user space would be. Note
- * that this also creates the page tables. Failure is not an
- * option here.
- */
- if (ecard_init_mm())
- panic("kecardd: unable to alloc mm\n");
-
- while (1) {
- struct ecard_request *req;
-
- wait_event_interruptible(ecard_wait, ecard_req != NULL);
-
- req = xchg(&ecard_req, NULL);
- if (req != NULL) {
- req->fn(req);
- complete(req->complete);
- }
- }
-}
-
-/*
- * Wake the expansion card daemon to action our request.
- *
- * FIXME: The test here is not sufficient to detect if the
- * kcardd is running.
- */
-static void ecard_call(struct ecard_request *req)
-{
- DECLARE_COMPLETION_ONSTACK(completion);
-
- req->complete = &completion;
-
- mutex_lock(&ecard_mutex);
- ecard_req = req;
- wake_up(&ecard_wait);
-
- /*
- * Now wait for kecardd to run.
- */
- wait_for_completion(&completion);
- mutex_unlock(&ecard_mutex);
-}
-
-/* ======================= Mid-level card control ===================== */
-
-static void
-ecard_readbytes(void *addr, ecard_t *ec, int off, int len, int useld)
-{
- struct ecard_request req;
-
- req.fn = ecard_task_readbytes;
- req.ec = ec;
- req.address = off;
- req.length = len;
- req.use_loader = useld;
- req.buffer = addr;
-
- ecard_call(&req);
-}
-
-int ecard_readchunk(struct in_chunk_dir *cd, ecard_t *ec, int id, int num)
-{
- struct ex_chunk_dir excd;
- int index = 16;
- int useld = 0;
-
- if (!ec->cid.cd)
- return 0;
-
- while(1) {
- ecard_readbytes(&excd, ec, index, 8, useld);
- index += 8;
- if (c_id(&excd) == 0) {
- if (!useld && ec->loader) {
- useld = 1;
- index = 0;
- continue;
- }
- return 0;
- }
- if (c_id(&excd) == 0xf0) { /* link */
- index = c_start(&excd);
- continue;
- }
- if (c_id(&excd) == 0x80) { /* loader */
- if (!ec->loader) {
- ec->loader = kmalloc(c_len(&excd),
- GFP_KERNEL);
- if (ec->loader)
- ecard_readbytes(ec->loader, ec,
- (int)c_start(&excd),
- c_len(&excd), useld);
- else
- return 0;
- }
- continue;
- }
- if (c_id(&excd) == id && num-- == 0)
- break;
- }
-
- if (c_id(&excd) & 0x80) {
- switch (c_id(&excd) & 0x70) {
- case 0x70:
- ecard_readbytes((unsigned char *)excd.d.string, ec,
- (int)c_start(&excd), c_len(&excd),
- useld);
- break;
- case 0x00:
- break;
- }
- }
- cd->start_offset = c_start(&excd);
- memcpy(cd->d.string, excd.d.string, 256);
- return 1;
-}
-
-/* ======================= Interrupt control ============================ */
-
-static void ecard_def_irq_enable(ecard_t *ec, int irqnr)
-{
-}
-
-static void ecard_def_irq_disable(ecard_t *ec, int irqnr)
-{
-}
-
-static int ecard_def_irq_pending(ecard_t *ec)
-{
- return !ec->irqmask || readb(ec->irqaddr) & ec->irqmask;
-}
-
-static void ecard_def_fiq_enable(ecard_t *ec, int fiqnr)
-{
- panic("ecard_def_fiq_enable called - impossible");
-}
-
-static void ecard_def_fiq_disable(ecard_t *ec, int fiqnr)
-{
- panic("ecard_def_fiq_disable called - impossible");
-}
-
-static int ecard_def_fiq_pending(ecard_t *ec)
-{
- return !ec->fiqmask || readb(ec->fiqaddr) & ec->fiqmask;
-}
-
-static expansioncard_ops_t ecard_default_ops = {
- ecard_def_irq_enable,
- ecard_def_irq_disable,
- ecard_def_irq_pending,
- ecard_def_fiq_enable,
- ecard_def_fiq_disable,
- ecard_def_fiq_pending
-};
-
-/*
- * Enable and disable interrupts from expansion cards.
- * (interrupts are disabled for these functions).
- *
- * They are not meant to be called directly, but via enable/disable_irq.
- */
-static void ecard_irq_unmask(struct irq_data *d)
-{
- ecard_t *ec = irq_data_get_irq_chip_data(d);
-
- if (ec) {
- if (!ec->ops)
- ec->ops = &ecard_default_ops;
-
- if (ec->claimed && ec->ops->irqenable)
- ec->ops->irqenable(ec, d->irq);
- else
- printk(KERN_ERR "ecard: rejecting request to "
- "enable IRQs for %d\n", d->irq);
- }
-}
-
-static void ecard_irq_mask(struct irq_data *d)
-{
- ecard_t *ec = irq_data_get_irq_chip_data(d);
-
- if (ec) {
- if (!ec->ops)
- ec->ops = &ecard_default_ops;
-
- if (ec->ops && ec->ops->irqdisable)
- ec->ops->irqdisable(ec, d->irq);
- }
-}
-
-static struct irq_chip ecard_chip = {
- .name = "ECARD",
- .irq_ack = ecard_irq_mask,
- .irq_mask = ecard_irq_mask,
- .irq_unmask = ecard_irq_unmask,
-};
-
-void ecard_enablefiq(unsigned int fiqnr)
-{
- ecard_t *ec = slot_to_ecard(fiqnr);
-
- if (ec) {
- if (!ec->ops)
- ec->ops = &ecard_default_ops;
-
- if (ec->claimed && ec->ops->fiqenable)
- ec->ops->fiqenable(ec, fiqnr);
- else
- printk(KERN_ERR "ecard: rejecting request to "
- "enable FIQs for %d\n", fiqnr);
- }
-}
-
-void ecard_disablefiq(unsigned int fiqnr)
-{
- ecard_t *ec = slot_to_ecard(fiqnr);
-
- if (ec) {
- if (!ec->ops)
- ec->ops = &ecard_default_ops;
-
- if (ec->ops->fiqdisable)
- ec->ops->fiqdisable(ec, fiqnr);
- }
-}
-
-static void ecard_dump_irq_state(void)
-{
- ecard_t *ec;
-
- printk("Expansion card IRQ state:\n");
-
- for (ec = cards; ec; ec = ec->next) {
- const char *claimed;
-
- if (ec->slot_no == 8)
- continue;
-
- claimed = ec->claimed ? "" : "not ";
-
- if (ec->ops && ec->ops->irqpending &&
- ec->ops != &ecard_default_ops)
- printk(" %d: %sclaimed irq %spending\n",
- ec->slot_no, claimed,
- ec->ops->irqpending(ec) ? "" : "not ");
- else
- printk(" %d: %sclaimed irqaddr %p, mask = %02X, status = %02X\n",
- ec->slot_no, claimed,
- ec->irqaddr, ec->irqmask, readb(ec->irqaddr));
- }
-}
-
-static void ecard_check_lockup(struct irq_desc *desc)
-{
- static unsigned long last;
- static int lockup;
-
- /*
- * If the timer interrupt has not run since the last million
- * unrecognised expansion card interrupts, then there is
- * something seriously wrong. Disable the expansion card
- * interrupts so at least we can continue.
- *
- * Maybe we ought to start a timer to re-enable them some time
- * later?
- */
- if (last == jiffies) {
- lockup += 1;
- if (lockup > 1000000) {
- printk(KERN_ERR "\nInterrupt lockup detected - "
- "disabling all expansion card interrupts\n");
-
- desc->irq_data.chip->irq_mask(&desc->irq_data);
- ecard_dump_irq_state();
- }
- } else
- lockup = 0;
-
- /*
- * If we did not recognise the source of this interrupt,
- * warn the user, but don't flood the user with these messages.
- */
- if (!last || time_after(jiffies, last + 5*HZ)) {
- last = jiffies;
- printk(KERN_WARNING "Unrecognised interrupt from backplane\n");
- ecard_dump_irq_state();
- }
-}
-
-static void ecard_irq_handler(struct irq_desc *desc)
-{
- ecard_t *ec;
- int called = 0;
-
- desc->irq_data.chip->irq_mask(&desc->irq_data);
- for (ec = cards; ec; ec = ec->next) {
- int pending;
-
- if (!ec->claimed || !ec->irq || ec->slot_no == 8)
- continue;
-
- if (ec->ops && ec->ops->irqpending)
- pending = ec->ops->irqpending(ec);
- else
- pending = ecard_default_ops.irqpending(ec);
-
- if (pending) {
- generic_handle_irq(ec->irq);
- called ++;
- }
- }
- desc->irq_data.chip->irq_unmask(&desc->irq_data);
-
- if (called == 0)
- ecard_check_lockup(desc);
-}
-
-static void __iomem *__ecard_address(ecard_t *ec, card_type_t type, card_speed_t speed)
-{
- void __iomem *address = NULL;
- int slot = ec->slot_no;
-
- if (ec->slot_no == 8)
- return ECARD_MEMC8_BASE;
-
- ectcr &= ~(1 << slot);
-
- switch (type) {
- case ECARD_MEMC:
- if (slot < 4)
- address = ECARD_MEMC_BASE + (slot << 14);
- break;
-
- case ECARD_IOC:
- if (slot < 4)
- address = ECARD_IOC_BASE + (slot << 14);
- else
- address = ECARD_IOC4_BASE + ((slot - 4) << 14);
- if (address)
- address += speed << 19;
- break;
-
- case ECARD_EASI:
- address = ECARD_EASI_BASE + (slot << 24);
- if (speed == ECARD_FAST)
- ectcr |= 1 << slot;
- break;
-
- default:
- break;
- }
-
-#ifdef IOMD_ECTCR
- iomd_writeb(ectcr, IOMD_ECTCR);
-#endif
- return address;
-}
-
-static int ecard_prints(struct seq_file *m, ecard_t *ec)
-{
- seq_printf(m, " %d: %s ", ec->slot_no, ec->easi ? "EASI" : " ");
-
- if (ec->cid.id == 0) {
- struct in_chunk_dir incd;
-
- seq_printf(m, "[%04X:%04X] ",
- ec->cid.manufacturer, ec->cid.product);
-
- if (!ec->card_desc && ec->cid.cd &&
- ecard_readchunk(&incd, ec, 0xf5, 0)) {
- ec->card_desc = kmalloc(strlen(incd.d.string)+1, GFP_KERNEL);
-
- if (ec->card_desc)
- strcpy((char *)ec->card_desc, incd.d.string);
- }
-
- seq_printf(m, "%s\n", ec->card_desc ? ec->card_desc : "*unknown*");
- } else
- seq_printf(m, "Simple card %d\n", ec->cid.id);
-
- return 0;
-}
-
-static int ecard_devices_proc_show(struct seq_file *m, void *v)
-{
- ecard_t *ec = cards;
-
- while (ec) {
- ecard_prints(m, ec);
- ec = ec->next;
- }
- return 0;
-}
-
-static struct proc_dir_entry *proc_bus_ecard_dir = NULL;
-
-static void ecard_proc_init(void)
-{
- proc_bus_ecard_dir = proc_mkdir("bus/ecard", NULL);
- proc_create_single("devices", 0, proc_bus_ecard_dir,
- ecard_devices_proc_show);
-}
-
-#define ec_set_resource(ec,nr,st,sz) \
- do { \
- (ec)->resource[nr].name = dev_name(&ec->dev); \
- (ec)->resource[nr].start = st; \
- (ec)->resource[nr].end = (st) + (sz) - 1; \
- (ec)->resource[nr].flags = IORESOURCE_MEM; \
- } while (0)
-
-static void __init ecard_free_card(struct expansion_card *ec)
-{
- int i;
-
- for (i = 0; i < ECARD_NUM_RESOURCES; i++)
- if (ec->resource[i].flags)
- release_resource(&ec->resource[i]);
-
- kfree(ec);
-}
-
-static struct expansion_card *__init ecard_alloc_card(int type, int slot)
-{
- struct expansion_card *ec;
- unsigned long base;
- int i;
-
- ec = kzalloc_obj(ecard_t);
- if (!ec) {
- ec = ERR_PTR(-ENOMEM);
- goto nomem;
- }
-
- ec->slot_no = slot;
- ec->easi = type == ECARD_EASI;
- ec->irq = 0;
- ec->fiq = 0;
- ec->dma = NO_DMA;
- ec->ops = &ecard_default_ops;
-
- dev_set_name(&ec->dev, "ecard%d", slot);
- ec->dev.parent = NULL;
- ec->dev.bus = &ecard_bus_type;
- ec->dev.dma_mask = &ec->dma_mask;
- ec->dma_mask = (u64)0xffffffff;
- ec->dev.coherent_dma_mask = ec->dma_mask;
-
- if (slot < 4) {
- ec_set_resource(ec, ECARD_RES_MEMC,
- PODSLOT_MEMC_BASE + (slot << 14),
- PODSLOT_MEMC_SIZE);
- base = PODSLOT_IOC0_BASE + (slot << 14);
- } else
- base = PODSLOT_IOC4_BASE + ((slot - 4) << 14);
-
-#ifdef CONFIG_ARCH_RPC
- if (slot < 8) {
- ec_set_resource(ec, ECARD_RES_EASI,
- PODSLOT_EASI_BASE + (slot << 24),
- PODSLOT_EASI_SIZE);
- }
-
- if (slot == 8) {
- ec_set_resource(ec, ECARD_RES_MEMC, NETSLOT_BASE, NETSLOT_SIZE);
- } else
-#endif
-
- for (i = 0; i <= ECARD_RES_IOCSYNC - ECARD_RES_IOCSLOW; i++)
- ec_set_resource(ec, i + ECARD_RES_IOCSLOW,
- base + (i << 19), PODSLOT_IOC_SIZE);
-
- for (i = 0; i < ECARD_NUM_RESOURCES; i++) {
- if (ec->resource[i].flags &&
- request_resource(&iomem_resource, &ec->resource[i])) {
- dev_err(&ec->dev, "resource(s) not available\n");
- ec->resource[i].end -= ec->resource[i].start;
- ec->resource[i].start = 0;
- ec->resource[i].flags = 0;
- }
- }
-
- nomem:
- return ec;
-}
-
-static ssize_t irq_show(struct device *dev, struct device_attribute *attr, char *buf)
-{
- struct expansion_card *ec = ECARD_DEV(dev);
- return sprintf(buf, "%u\n", ec->irq);
-}
-static DEVICE_ATTR_RO(irq);
-
-static ssize_t dma_show(struct device *dev, struct device_attribute *attr, char *buf)
-{
- struct expansion_card *ec = ECARD_DEV(dev);
- return sprintf(buf, "%u\n", ec->dma);
-}
-static DEVICE_ATTR_RO(dma);
-
-static ssize_t resource_show(struct device *dev, struct device_attribute *attr, char *buf)
-{
- struct expansion_card *ec = ECARD_DEV(dev);
- char *str = buf;
- int i;
-
- for (i = 0; i < ECARD_NUM_RESOURCES; i++)
- str += sprintf(str, "%08x %08x %08lx\n",
- ec->resource[i].start,
- ec->resource[i].end,
- ec->resource[i].flags);
-
- return str - buf;
-}
-static DEVICE_ATTR_RO(resource);
-
-static ssize_t vendor_show(struct device *dev, struct device_attribute *attr, char *buf)
-{
- struct expansion_card *ec = ECARD_DEV(dev);
- return sprintf(buf, "%u\n", ec->cid.manufacturer);
-}
-static DEVICE_ATTR_RO(vendor);
-
-static ssize_t device_show(struct device *dev, struct device_attribute *attr, char *buf)
-{
- struct expansion_card *ec = ECARD_DEV(dev);
- return sprintf(buf, "%u\n", ec->cid.product);
-}
-static DEVICE_ATTR_RO(device);
-
-static ssize_t type_show(struct device *dev, struct device_attribute *attr, char *buf)
-{
- struct expansion_card *ec = ECARD_DEV(dev);
- return sprintf(buf, "%s\n", ec->easi ? "EASI" : "IOC");
-}
-static DEVICE_ATTR_RO(type);
-
-static struct attribute *ecard_dev_attrs[] = {
- &dev_attr_device.attr,
- &dev_attr_dma.attr,
- &dev_attr_irq.attr,
- &dev_attr_resource.attr,
- &dev_attr_type.attr,
- &dev_attr_vendor.attr,
- NULL,
-};
-ATTRIBUTE_GROUPS(ecard_dev);
-
-int ecard_request_resources(struct expansion_card *ec)
-{
- int i, err = 0;
-
- for (i = 0; i < ECARD_NUM_RESOURCES; i++) {
- if (ecard_resource_end(ec, i) &&
- !request_mem_region(ecard_resource_start(ec, i),
- ecard_resource_len(ec, i),
- ec->dev.driver->name)) {
- err = -EBUSY;
- break;
- }
- }
-
- if (err) {
- while (i--)
- if (ecard_resource_end(ec, i))
- release_mem_region(ecard_resource_start(ec, i),
- ecard_resource_len(ec, i));
- }
- return err;
-}
-EXPORT_SYMBOL(ecard_request_resources);
-
-void ecard_release_resources(struct expansion_card *ec)
-{
- int i;
-
- for (i = 0; i < ECARD_NUM_RESOURCES; i++)
- if (ecard_resource_end(ec, i))
- release_mem_region(ecard_resource_start(ec, i),
- ecard_resource_len(ec, i));
-}
-EXPORT_SYMBOL(ecard_release_resources);
-
-void ecard_setirq(struct expansion_card *ec, const struct expansion_card_ops *ops, void *irq_data)
-{
- ec->irq_data = irq_data;
- barrier();
- ec->ops = ops;
-}
-EXPORT_SYMBOL(ecard_setirq);
-
-void __iomem *ecardm_iomap(struct expansion_card *ec, unsigned int res,
- unsigned long offset, unsigned long maxsize)
-{
- unsigned long start = ecard_resource_start(ec, res);
- unsigned long end = ecard_resource_end(ec, res);
-
- if (offset > (end - start))
- return NULL;
-
- start += offset;
- if (maxsize && end - start > maxsize)
- end = start + maxsize;
-
- return devm_ioremap(&ec->dev, start, end - start);
-}
-EXPORT_SYMBOL(ecardm_iomap);
-
-static void atomwide_3p_quirk(ecard_t *ec)
-{
- void __iomem *addr = __ecard_address(ec, ECARD_IOC, ECARD_SYNC);
- unsigned int i;
-
- /* Disable interrupts on each port */
- for (i = 0x2000; i <= 0x2800; i += 0x0400)
- writeb(0, addr + i + 4);
-}
-
-/*
- * Probe for an expansion card.
- *
- * If bit 1 of the first byte of the card is set, then the
- * card does not exist.
- */
-static int __init ecard_probe(int slot, unsigned irq, card_type_t type)
-{
- ecard_t **ecp;
- ecard_t *ec;
- struct ex_ecid cid;
- void __iomem *addr;
- int i, rc;
-
- ec = ecard_alloc_card(type, slot);
- if (IS_ERR(ec)) {
- rc = PTR_ERR(ec);
- goto nomem;
- }
-
- rc = -ENODEV;
- if ((addr = __ecard_address(ec, type, ECARD_SYNC)) == NULL)
- goto nodev;
-
- cid.r_zero = 1;
- ecard_readbytes(&cid, ec, 0, 16, 0);
- if (cid.r_zero)
- goto nodev;
-
- ec->cid.id = cid.r_id;
- ec->cid.cd = cid.r_cd;
- ec->cid.is = cid.r_is;
- ec->cid.w = cid.r_w;
- ec->cid.manufacturer = ecard_getu16(cid.r_manu);
- ec->cid.product = ecard_getu16(cid.r_prod);
- ec->cid.country = cid.r_country;
- ec->cid.irqmask = cid.r_irqmask;
- ec->cid.irqoff = ecard_gets24(cid.r_irqoff);
- ec->cid.fiqmask = cid.r_fiqmask;
- ec->cid.fiqoff = ecard_gets24(cid.r_fiqoff);
- ec->fiqaddr =
- ec->irqaddr = addr;
-
- if (ec->cid.is) {
- ec->irqmask = ec->cid.irqmask;
- ec->irqaddr += ec->cid.irqoff;
- ec->fiqmask = ec->cid.fiqmask;
- ec->fiqaddr += ec->cid.fiqoff;
- } else {
- ec->irqmask = 1;
- ec->fiqmask = 4;
- }
-
- for (i = 0; i < ARRAY_SIZE(quirklist); i++)
- if (quirklist[i].manufacturer == ec->cid.manufacturer &&
- quirklist[i].product == ec->cid.product) {
- if (quirklist[i].type)
- ec->card_desc = quirklist[i].type;
- if (quirklist[i].init)
- quirklist[i].init(ec);
- break;
- }
-
- ec->irq = irq;
-
- /*
- * hook the interrupt handlers
- */
- if (slot < 8) {
- irq_set_chip_and_handler(ec->irq, &ecard_chip,
- handle_level_irq);
- irq_set_chip_data(ec->irq, ec);
- irq_clear_status_flags(ec->irq, IRQ_NOREQUEST);
- }
-
-#ifdef CONFIG_ARCH_RPC
- /* On RiscPC, only first two slots have DMA capability */
- if (slot < 2)
- ec->dma = 2 + slot;
-#endif
-
- for (ecp = &cards; *ecp; ecp = &(*ecp)->next);
-
- *ecp = ec;
- slot_to_expcard[slot] = ec;
-
- rc = device_register(&ec->dev);
- if (rc)
- goto nodev;
-
- return 0;
-
- nodev:
- ecard_free_card(ec);
- nomem:
- return rc;
-}
-
-/*
- * Initialise the expansion card system.
- * Locate all hardware - interrupt management and
- * actual cards.
- */
-static int __init ecard_init(void)
-{
- struct task_struct *task;
- int slot, irqbase;
-
- irqbase = irq_alloc_descs(-1, 0, 8, -1);
- if (irqbase < 0)
- return irqbase;
-
- task = kthread_run(ecard_task, NULL, "kecardd");
- if (IS_ERR(task)) {
- printk(KERN_ERR "Ecard: unable to create kernel thread: %ld\n",
- PTR_ERR(task));
- irq_free_descs(irqbase, 8);
- return PTR_ERR(task);
- }
-
- printk("Probing expansion cards\n");
-
- for (slot = 0; slot < 8; slot ++) {
- if (ecard_probe(slot, irqbase + slot, ECARD_EASI) == -ENODEV)
- ecard_probe(slot, irqbase + slot, ECARD_IOC);
- }
-
- ecard_probe(8, 11, ECARD_IOC);
-
- irq_set_chained_handler(IRQ_EXPANSIONCARD, ecard_irq_handler);
-
- ecard_proc_init();
-
- return 0;
-}
-
-subsys_initcall(ecard_init);
-
-/*
- * ECARD "bus"
- */
-static const struct ecard_id *
-ecard_match_device(const struct ecard_id *ids, struct expansion_card *ec)
-{
- int i;
-
- for (i = 0; ids[i].manufacturer != 65535; i++)
- if (ec->cid.manufacturer == ids[i].manufacturer &&
- ec->cid.product == ids[i].product)
- return ids + i;
-
- return NULL;
-}
-
-static int ecard_drv_probe(struct device *dev)
-{
- struct expansion_card *ec = ECARD_DEV(dev);
- struct ecard_driver *drv = ECARD_DRV(dev->driver);
- const struct ecard_id *id;
- int ret;
-
- id = ecard_match_device(drv->id_table, ec);
-
- ec->claimed = 1;
- ret = drv->probe(ec, id);
- if (ret)
- ec->claimed = 0;
- return ret;
-}
-
-static void ecard_drv_remove(struct device *dev)
-{
- struct expansion_card *ec = ECARD_DEV(dev);
- struct ecard_driver *drv = ECARD_DRV(dev->driver);
-
- drv->remove(ec);
- ec->claimed = 0;
-
- /*
- * Restore the default operations. We ensure that the
- * ops are set before we change the data.
- */
- ec->ops = &ecard_default_ops;
- barrier();
- ec->irq_data = NULL;
-}
-
-/*
- * Before rebooting, we must make sure that the expansion card is in a
- * sensible state, so it can be re-detected. This means that the first
- * page of the ROM must be visible. We call the expansion cards reset
- * handler, if any.
- */
-static void ecard_drv_shutdown(struct device *dev)
-{
- struct expansion_card *ec = ECARD_DEV(dev);
- struct ecard_driver *drv = ECARD_DRV(dev->driver);
- struct ecard_request req;
-
- if (dev->driver) {
- if (drv->shutdown)
- drv->shutdown(ec);
- ec->claimed = 0;
- }
-
- /*
- * If this card has a loader, call the reset handler.
- */
- if (ec->loader) {
- req.fn = ecard_task_reset;
- req.ec = ec;
- ecard_call(&req);
- }
-}
-
-int ecard_register_driver(struct ecard_driver *drv)
-{
- drv->drv.bus = &ecard_bus_type;
-
- return driver_register(&drv->drv);
-}
-
-void ecard_remove_driver(struct ecard_driver *drv)
-{
- driver_unregister(&drv->drv);
-}
-
-static int ecard_match(struct device *_dev, const struct device_driver *_drv)
-{
- struct expansion_card *ec = ECARD_DEV(_dev);
- struct ecard_driver *drv = ECARD_DRV(_drv);
- int ret;
-
- if (drv->id_table) {
- ret = ecard_match_device(drv->id_table, ec) != NULL;
- } else {
- ret = ec->cid.id == drv->id;
- }
-
- return ret;
-}
-
-const struct bus_type ecard_bus_type = {
- .name = "ecard",
- .dev_groups = ecard_dev_groups,
- .match = ecard_match,
- .probe = ecard_drv_probe,
- .remove = ecard_drv_remove,
- .shutdown = ecard_drv_shutdown,
-};
-
-static int ecard_bus_init(void)
-{
- return bus_register(&ecard_bus_type);
-}
-
-postcore_initcall(ecard_bus_init);
-
-EXPORT_SYMBOL(ecard_readchunk);
-EXPORT_SYMBOL(ecard_register_driver);
-EXPORT_SYMBOL(ecard_remove_driver);
-EXPORT_SYMBOL(ecard_bus_type);
diff --git a/arch/arm/mach-rpc/ecard.h b/arch/arm/mach-rpc/ecard.h
deleted file mode 100644
index 873dd3d9f274..000000000000
--- a/arch/arm/mach-rpc/ecard.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * ecard.h
- *
- * Copyright 2007 Russell King
- */
-
-/* Definitions internal to ecard.c - for it's use only!!
- *
- * External expansion card header as read from the card
- */
-struct ex_ecid {
- unsigned char r_irq:1;
- unsigned char r_zero:1;
- unsigned char r_fiq:1;
- unsigned char r_id:4;
- unsigned char r_a:1;
-
- unsigned char r_cd:1;
- unsigned char r_is:1;
- unsigned char r_w:2;
- unsigned char r_r1:4;
-
- unsigned char r_r2:8;
-
- unsigned char r_prod[2];
-
- unsigned char r_manu[2];
-
- unsigned char r_country;
-
- unsigned char r_fiqmask;
- unsigned char r_fiqoff[3];
-
- unsigned char r_irqmask;
- unsigned char r_irqoff[3];
-};
-
-/*
- * Chunk directory entry as read from the card
- */
-struct ex_chunk_dir {
- unsigned char r_id;
- unsigned char r_len[3];
- unsigned long r_start;
- union {
- char string[256];
- char data[1];
- } d;
-#define c_id(x) ((x)->r_id)
-#define c_len(x) ((x)->r_len[0]|((x)->r_len[1]<<8)|((x)->r_len[2]<<16))
-#define c_start(x) ((x)->r_start)
-};
-
-typedef enum ecard_type { /* Cards address space */
- ECARD_IOC,
- ECARD_MEMC,
- ECARD_EASI
-} card_type_t;
-
-typedef enum { /* Speed for ECARD_IOC space */
- ECARD_SLOW = 0,
- ECARD_MEDIUM = 1,
- ECARD_FAST = 2,
- ECARD_SYNC = 3
-} card_speed_t;
diff --git a/arch/arm/mach-rpc/fiq.S b/arch/arm/mach-rpc/fiq.S
deleted file mode 100644
index 087bdf4bc093..000000000000
--- a/arch/arm/mach-rpc/fiq.S
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <mach/hardware.h>
-
- .equ ioc_base_high, IOC_BASE & 0xff000000
- .equ ioc_base_low, IOC_BASE & 0x00ff0000
-
- .text
- .global rpc_default_fiq_end
-ENTRY(rpc_default_fiq_start)
- mov r12, #ioc_base_high
- .if ioc_base_low
- orr r12, r12, #ioc_base_low
- .endif
- strb r12, [r12, #0x38] @ Disable FIQ register
- subs pc, lr, #4
-rpc_default_fiq_end:
diff --git a/arch/arm/mach-rpc/floppydma.S b/arch/arm/mach-rpc/floppydma.S
deleted file mode 100644
index 6698b83050dc..000000000000
--- a/arch/arm/mach-rpc/floppydma.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * linux/arch/arm/lib/floppydma.S
- *
- * Copyright (C) 1995, 1996 Russell King
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
- .text
-
- .global floppy_fiqin_end
-ENTRY(floppy_fiqin_start)
- subs r9, r9, #1
- ldrbgt r12, [r11, #-4]
- ldrble r12, [r11], #0
- strb r12, [r10], #1
- subs pc, lr, #4
-floppy_fiqin_end:
-
- .global floppy_fiqout_end
-ENTRY(floppy_fiqout_start)
- subs r9, r9, #1
- ldrbge r12, [r10], #1
- movlt r12, #0
- strble r12, [r11], #0
- subsle pc, lr, #4
- strb r12, [r11, #-4]
- subs pc, lr, #4
-floppy_fiqout_end:
diff --git a/arch/arm/mach-rpc/include/mach/acornfb.h b/arch/arm/mach-rpc/include/mach/acornfb.h
deleted file mode 100644
index 2bf18ab3d699..000000000000
--- a/arch/arm/mach-rpc/include/mach/acornfb.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-rpc/include/mach/acornfb.h
- *
- * Copyright (C) 1999 Russell King
- *
- * AcornFB architecture specific code
- */
-
-#define acornfb_bandwidth(var) ((var)->pixclock * 8 / (var)->bits_per_pixel)
-
-static inline int
-acornfb_valid_pixrate(struct fb_var_screeninfo *var)
-{
- u_long limit;
-
- if (!var->pixclock)
- return 0;
-
- /*
- * Limits below are taken from RISC OS bandwidthlimit file
- */
- if (current_par.using_vram) {
- if (current_par.vram_half_sam == 2048)
- limit = 6578;
- else
- limit = 13157;
- } else {
- limit = 26315;
- }
-
- return acornfb_bandwidth(var) >= limit;
-}
-
-/*
- * Try to find the best PLL parameters for the pixel clock.
- * This algorithm seems to give best predictable results,
- * and produces the same values as detailed in the VIDC20
- * data sheet.
- */
-static inline u_int
-acornfb_vidc20_find_pll(u_int pixclk)
-{
- u_int r, best_r = 2, best_v = 2;
- int best_d = 0x7fffffff;
-
- for (r = 2; r <= 32; r++) {
- u_int rr, v, p;
- int d;
-
- rr = 41667 * r;
-
- v = (rr + pixclk / 2) / pixclk;
-
- if (v > 32 || v < 2)
- continue;
-
- p = (rr + v / 2) / v;
-
- d = pixclk - p;
-
- if (d < 0)
- d = -d;
-
- if (d < best_d) {
- best_d = d;
- best_v = v - 1;
- best_r = r - 1;
- }
-
- if (d == 0)
- break;
- }
-
- return best_v << 8 | best_r;
-}
-
-static inline void
-acornfb_vidc20_find_rates(struct vidc_timing *vidc,
- struct fb_var_screeninfo *var)
-{
- u_int div;
-
- /* Select pixel-clock divisor to keep PLL in range */
- div = var->pixclock / 9090; /*9921*/
-
- /* Limit divisor */
- if (div == 0)
- div = 1;
- if (div > 8)
- div = 8;
-
- /* Encode divisor to VIDC20 setting */
- switch (div) {
- case 1: vidc->control |= VIDC20_CTRL_PIX_CK; break;
- case 2: vidc->control |= VIDC20_CTRL_PIX_CK2; break;
- case 3: vidc->control |= VIDC20_CTRL_PIX_CK3; break;
- case 4: vidc->control |= VIDC20_CTRL_PIX_CK4; break;
- case 5: vidc->control |= VIDC20_CTRL_PIX_CK5; break;
- case 6: vidc->control |= VIDC20_CTRL_PIX_CK6; break;
- case 7: vidc->control |= VIDC20_CTRL_PIX_CK7; break;
- case 8: vidc->control |= VIDC20_CTRL_PIX_CK8; break;
- }
-
- /*
- * With VRAM, the FIFO can be set to the highest possible setting
- * because there are no latency considerations for other memory
- * accesses. However, in 64 bit bus mode the FIFO preload value
- * must not be set to VIDC20_CTRL_FIFO_28 because this will let
- * the FIFO overflow. See VIDC20 manual page 33 (6.0 Setting the
- * FIFO preload value).
- */
- if (current_par.using_vram) {
- if (current_par.vram_half_sam == 2048)
- vidc->control |= VIDC20_CTRL_FIFO_24;
- else
- vidc->control |= VIDC20_CTRL_FIFO_28;
- } else {
- unsigned long bandwidth = acornfb_bandwidth(var);
-
- /* Encode bandwidth as VIDC20 setting */
- if (bandwidth > 33334) /* < 30.0MB/s */
- vidc->control |= VIDC20_CTRL_FIFO_16;
- else if (bandwidth > 26666) /* < 37.5MB/s */
- vidc->control |= VIDC20_CTRL_FIFO_20;
- else if (bandwidth > 22222) /* < 45.0MB/s */
- vidc->control |= VIDC20_CTRL_FIFO_24;
- else /* > 45.0MB/s */
- vidc->control |= VIDC20_CTRL_FIFO_28;
- }
-
- /* Find the PLL values */
- vidc->pll_ctl = acornfb_vidc20_find_pll(var->pixclock / div);
-}
-
-#define acornfb_default_control() (VIDC20_CTRL_PIX_VCLK)
-#define acornfb_default_econtrol() (VIDC20_ECTL_DAC | VIDC20_ECTL_REG(3))
diff --git a/arch/arm/mach-rpc/include/mach/hardware.h b/arch/arm/mach-rpc/include/mach/hardware.h
deleted file mode 100644
index 6f197706f979..000000000000
--- a/arch/arm/mach-rpc/include/mach/hardware.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-rpc/include/mach/hardware.h
- *
- * Copyright (C) 1996-1999 Russell King.
- *
- * This file contains the hardware definitions of the RiscPC series machines.
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <mach/memory.h>
-
-/*
- * What hardware must be present
- */
-#define HAS_IOMD
-#define HAS_VIDC20
-
-/* Hardware addresses of major areas.
- * *_START is the physical address
- * *_SIZE is the size of the region
- * *_BASE is the virtual address
- */
-#define RPC_RAM_SIZE 0x10000000
-#define RPC_RAM_START 0x10000000
-
-#define EASI_SIZE 0x08000000 /* EASI I/O */
-#define EASI_START 0x08000000
-#define EASI_BASE IOMEM(0xe5000000)
-
-#define IO_START 0x03000000 /* I/O */
-#define IO_SIZE 0x01000000
-#define IO_BASE IOMEM(0xe0000000)
-
-#define SCREEN_START 0x02000000 /* VRAM */
-#define SCREEN_END 0xdfc00000
-#define SCREEN_BASE 0xdf800000
-
-#define UNCACHEABLE_ADDR (FLUSH_BASE + 0x10000)
-
-/*
- * IO Addresses
- */
-#define ECARD_EASI_BASE (EASI_BASE)
-#define VIDC_BASE (IO_BASE + 0x00400000)
-#define EXPMASK_BASE (IO_BASE + 0x00360000)
-#define ECARD_IOC4_BASE (IO_BASE + 0x00270000)
-#define ECARD_IOC_BASE (IO_BASE + 0x00240000)
-#define IOMD_BASE (IO_BASE + 0x00200000)
-#define IOC_BASE (IO_BASE + 0x00200000)
-#define ECARD_MEMC8_BASE (IO_BASE + 0x0002b000)
-#define FLOPPYDMA_BASE (IO_BASE + 0x0002a000)
-#define PCIO_BASE (IO_BASE + 0x00010000)
-#define ECARD_MEMC_BASE (IO_BASE + 0x00000000)
-
-#define vidc_writel(val) __raw_writel(val, VIDC_BASE)
-
-#define NETSLOT_BASE 0x0302b000
-#define NETSLOT_SIZE 0x00001000
-
-#define PODSLOT_IOC0_BASE 0x03240000
-#define PODSLOT_IOC4_BASE 0x03270000
-#define PODSLOT_IOC_SIZE (1 << 14)
-#define PODSLOT_MEMC_BASE 0x03000000
-#define PODSLOT_MEMC_SIZE (1 << 14)
-#define PODSLOT_EASI_BASE 0x08000000
-#define PODSLOT_EASI_SIZE (1 << 24)
-
-#define EXPMASK_STATUS (EXPMASK_BASE + 0x00)
-#define EXPMASK_ENABLE (EXPMASK_BASE + 0x04)
-
-#endif
diff --git a/arch/arm/mach-rpc/include/mach/io.h b/arch/arm/mach-rpc/include/mach/io.h
deleted file mode 100644
index 8a8f28406691..000000000000
--- a/arch/arm/mach-rpc/include/mach/io.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-rpc/include/mach/io.h
- *
- * Copyright (C) 1997 Russell King
- *
- * Modifications:
- * 06-Dec-1997 RMK Created.
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <mach/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffff
-
-/*
- * We need PC style IO addressing for:
- * - floppy (at 0x3f2,0x3f4,0x3f5,0x3f7)
- * - parport (at 0x278-0x27a, 0x27b-0x27f, 0x778-0x77a)
- * - 8250 serial (only for compile)
- *
- * These peripherals are found in an area of MMIO which looks very much
- * like an ISA bus, but with registers at the low byte of each word.
- */
-#define __io(a) (PCIO_BASE + ((a) << 2))
-
-#endif
diff --git a/arch/arm/mach-rpc/include/mach/irqs.h b/arch/arm/mach-rpc/include/mach/irqs.h
deleted file mode 100644
index 0c3428fd9729..000000000000
--- a/arch/arm/mach-rpc/include/mach/irqs.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-rpc/include/mach/irqs.h
- *
- * Copyright (C) 1996 Russell King
- */
-
-#define IRQ_PRINTER 0
-#define IRQ_BATLOW 1
-#define IRQ_FLOPPYINDEX 2
-#define IRQ_VSYNCPULSE 3
-#define IRQ_POWERON 4
-#define IRQ_TIMER0 5
-#define IRQ_TIMER1 6
-#define IRQ_IMMEDIATE 7
-#define IRQ_EXPCARDFIQ 8
-#define IRQ_HARDDISK 9
-#define IRQ_SERIALPORT 10
-#define IRQ_FLOPPYDISK 12
-#define IRQ_EXPANSIONCARD 13
-#define IRQ_KEYBOARDTX 14
-#define IRQ_KEYBOARDRX 15
-
-#define IRQ_DMA0 16
-#define IRQ_DMA1 17
-#define IRQ_DMA2 18
-#define IRQ_DMA3 19
-#define IRQ_DMAS0 20
-#define IRQ_DMAS1 21
-
-#define FIQ_FLOPPYDATA 0
-#define FIQ_ECONET 2
-#define FIQ_SERIALPORT 4
-#define FIQ_EXPANSIONCARD 6
-#define FIQ_FORCE 7
-
-/*
- * This is the offset of the FIQ "IRQ" numbers
- */
-#define FIQ_START 64
-
-#define NR_IRQS 128
diff --git a/arch/arm/mach-rpc/include/mach/isa-dma.h b/arch/arm/mach-rpc/include/mach/isa-dma.h
deleted file mode 100644
index d9c3af1ef718..000000000000
--- a/arch/arm/mach-rpc/include/mach/isa-dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-rpc/include/mach/isa-dma.h
- *
- * Copyright (C) 1997 Russell King
- */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-#define MAX_DMA_CHANNELS 8
-
-#define DMA_0 0
-#define DMA_1 1
-#define DMA_2 2
-#define DMA_3 3
-#define DMA_S0 4
-#define DMA_S1 5
-#define DMA_VIRTUAL_FLOPPY 6
-#define DMA_VIRTUAL_SOUND 7
-
-#define DMA_FLOPPY DMA_VIRTUAL_FLOPPY
-
-#define IOMD_DMA_BOUNDARY (PAGE_SIZE - 1)
-
-#endif /* _ASM_ARCH_DMA_H */
-
diff --git a/arch/arm/mach-rpc/include/mach/memory.h b/arch/arm/mach-rpc/include/mach/memory.h
deleted file mode 100644
index a586eb31b18d..000000000000
--- a/arch/arm/mach-rpc/include/mach/memory.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-rpc/include/mach/memory.h
- *
- * Copyright (C) 1996,1997,1998 Russell King.
- *
- * Changelog:
- * 20-Oct-1996 RMK Created
- * 31-Dec-1997 RMK Fixed definitions to reduce warnings
- * 11-Jan-1998 RMK Uninlined to reduce hits on cache
- * 08-Feb-1998 RMK Added __virt_to_bus and __bus_to_virt
- * 21-Mar-1999 RMK Renamed to memory.h
- * RMK Added TASK_SIZE and PAGE_OFFSET
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Cache flushing area - ROM
- */
-#define FLUSH_BASE_PHYS 0x00000000
-#define FLUSH_BASE 0xdf000000
-
-/*
- * Sparsemem support. Each section is a maximum of 64MB. The sections
- * are offset by 128MB and can cover 128MB, so that gives us a maximum
- * of 29 physmem bits.
- */
-#define MAX_PHYSMEM_BITS 29
-#define SECTION_SIZE_BITS 26
-
-#endif
diff --git a/arch/arm/mach-rpc/include/mach/uncompress.h b/arch/arm/mach-rpc/include/mach/uncompress.h
deleted file mode 100644
index 1fbe7eb956fd..000000000000
--- a/arch/arm/mach-rpc/include/mach/uncompress.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-rpc/include/mach/uncompress.h
- *
- * Copyright (C) 1996 Russell King
- */
-#define VIDMEM ((char *)SCREEN_START)
-
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/page.h>
-
-int video_size_row;
-unsigned char bytes_per_char_h;
-extern unsigned long con_charconvtable[256];
-
-struct param_struct {
- unsigned long page_size;
- unsigned long nr_pages;
- unsigned long ramdisk_size;
- unsigned long mountrootrdonly;
- unsigned long rootdev;
- unsigned long video_num_cols;
- unsigned long video_num_rows;
- unsigned long video_x;
- unsigned long video_y;
- unsigned long memc_control_reg;
- unsigned char sounddefault;
- unsigned char adfsdrives;
- unsigned char bytes_per_char_h;
- unsigned char bytes_per_char_v;
- unsigned long unused[256/4-11];
-};
-
-static const unsigned long palette_4[16] = {
- 0x00000000,
- 0x000000cc,
- 0x0000cc00, /* Green */
- 0x0000cccc, /* Yellow */
- 0x00cc0000, /* Blue */
- 0x00cc00cc, /* Magenta */
- 0x00cccc00, /* Cyan */
- 0x00cccccc, /* White */
- 0x00000000,
- 0x000000ff,
- 0x0000ff00,
- 0x0000ffff,
- 0x00ff0000,
- 0x00ff00ff,
- 0x00ffff00,
- 0x00ffffff
-};
-
-#define palette_setpixel(p) *(unsigned long *)(IO_START+0x00400000) = 0x10000000|((p) & 255)
-#define palette_write(v) *(unsigned long *)(IO_START+0x00400000) = 0x00000000|((v) & 0x00ffffff)
-
-/*
- * params_phys is a linker defined symbol - see
- * arch/arm/boot/compressed/Makefile
- */
-extern __attribute__((pure)) struct param_struct *params(void);
-#define params (params())
-
-#ifndef STANDALONE_DEBUG
-unsigned long video_num_cols;
-unsigned long video_num_rows;
-unsigned long video_x;
-unsigned long video_y;
-unsigned char bytes_per_char_v;
-int white;
-
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
- extern void ll_write_char(char *, char c, char white);
- int x,y;
- char *ptr;
-
- x = video_x;
- y = video_y;
-
- if (c == '\n') {
- if (++y >= video_num_rows)
- y--;
- } else if (c == '\r') {
- x = 0;
- } else {
- ptr = VIDMEM + ((y*video_num_cols*bytes_per_char_v+x)*bytes_per_char_h);
- ll_write_char(ptr, c, white);
- if (++x >= video_num_cols) {
- x = 0;
- if ( ++y >= video_num_rows ) {
- y--;
- }
- }
- }
-
- video_x = x;
- video_y = y;
-}
-
-static inline void flush(void)
-{
-}
-
-/*
- * Setup for decompression
- */
-static void arch_decomp_setup(void)
-{
- int i;
- struct tag *t = (struct tag *)params;
- unsigned int nr_pages = 0, page_size = PAGE_SIZE;
-
- if (t->hdr.tag == ATAG_CORE) {
- for (; t->hdr.size; t = tag_next(t)) {
- if (t->hdr.tag == ATAG_VIDEOTEXT) {
- video_num_rows = t->u.videotext.video_lines;
- video_num_cols = t->u.videotext.video_cols;
- video_x = t->u.videotext.x;
- video_y = t->u.videotext.y;
- } else if (t->hdr.tag == ATAG_VIDEOLFB) {
- bytes_per_char_h = t->u.videolfb.lfb_depth;
- bytes_per_char_v = 8;
- } else if (t->hdr.tag == ATAG_MEM) {
- page_size = PAGE_SIZE;
- nr_pages += (t->u.mem.size / PAGE_SIZE);
- }
- }
- } else {
- nr_pages = params->nr_pages;
- page_size = params->page_size;
- video_num_rows = params->video_num_rows;
- video_num_cols = params->video_num_cols;
- video_x = params->video_x;
- video_y = params->video_y;
- bytes_per_char_h = params->bytes_per_char_h;
- bytes_per_char_v = params->bytes_per_char_v;
- }
-
- video_size_row = video_num_cols * bytes_per_char_h;
-
- if (bytes_per_char_h == 4)
- for (i = 0; i < 256; i++)
- con_charconvtable[i] =
- (i & 128 ? 1 << 0 : 0) |
- (i & 64 ? 1 << 4 : 0) |
- (i & 32 ? 1 << 8 : 0) |
- (i & 16 ? 1 << 12 : 0) |
- (i & 8 ? 1 << 16 : 0) |
- (i & 4 ? 1 << 20 : 0) |
- (i & 2 ? 1 << 24 : 0) |
- (i & 1 ? 1 << 28 : 0);
- else
- for (i = 0; i < 16; i++)
- con_charconvtable[i] =
- (i & 8 ? 1 << 0 : 0) |
- (i & 4 ? 1 << 8 : 0) |
- (i & 2 ? 1 << 16 : 0) |
- (i & 1 ? 1 << 24 : 0);
-
-
- palette_setpixel(0);
- if (bytes_per_char_h == 1) {
- palette_write (0);
- palette_write (0x00ffffff);
- for (i = 2; i < 256; i++)
- palette_write (0);
- white = 1;
- } else {
- for (i = 0; i < 256; i++)
- palette_write (i < 16 ? palette_4[i] : 0);
- white = 7;
- }
-
- if (nr_pages * page_size < 4096*1024) error("<4M of mem\n");
-}
-#endif
diff --git a/arch/arm/mach-rpc/io-acorn.S b/arch/arm/mach-rpc/io-acorn.S
deleted file mode 100644
index aa9bf0d771c0..000000000000
--- a/arch/arm/mach-rpc/io-acorn.S
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * linux/arch/arm/lib/io-acorn.S
- *
- * Copyright (C) 1995, 1996 Russell King
- *
- * 27/03/03 Ian Molton Clean up CONFIG_CPU
- */
-#include <linux/linkage.h>
-#include <linux/kern_levels.h>
-#include <asm/assembler.h>
-
- .text
- .align
-
-.Liosl_warning:
- .ascii KERN_WARNING "insl/outsl not implemented, called from %08lX\0"
- .align
-
-/*
- * These make no sense on Acorn machines.
- * Print a warning message.
- */
-ENTRY(insl)
-ENTRY(outsl)
- adr r0, .Liosl_warning
- mov r1, lr
- b _printk
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
deleted file mode 100644
index dc29384b6ef8..000000000000
--- a/arch/arm/mach-rpc/irq.c
+++ /dev/null
@@ -1,226 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/io.h>
-
-#include <asm/mach/irq.h>
-#include <asm/hardware/iomd.h>
-#include <asm/irq.h>
-#include <asm/fiq.h>
-
-// These are offsets from the stat register for each IRQ bank
-#define STAT 0x00
-#define REQ 0x04
-#define CLR 0x04
-#define MASK 0x08
-
-static const u8 irq_prio_h[256] = {
- 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10,
- 12, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10,
- 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
- 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
- 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10,
- 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10,
- 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
- 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
- 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10,
- 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10,
- 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
- 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
- 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10,
- 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10,
- 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
- 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
-};
-
-static const u8 irq_prio_d[256] = {
- 0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
- 20,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
- 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
- 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
- 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
- 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
- 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
- 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
- 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
- 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
- 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
- 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
- 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
- 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
- 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
- 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
-};
-
-static const u8 irq_prio_l[256] = {
- 0, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,
- 4, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,
- 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
- 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
- 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3,
- 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3,
- 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
- 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-};
-
-static int iomd_get_irq_nr(void)
-{
- int irq;
- u8 reg;
-
- /* get highest priority first */
- reg = readb(IOC_BASE + IOMD_IRQREQB);
- irq = irq_prio_h[reg];
- if (irq)
- return irq;
-
- /* get DMA */
- reg = readb(IOC_BASE + IOMD_DMAREQ);
- irq = irq_prio_d[reg];
- if (irq)
- return irq;
-
- /* get low priority */
- reg = readb(IOC_BASE + IOMD_IRQREQA);
- irq = irq_prio_l[reg];
- if (irq)
- return irq;
- return 0;
-}
-
-static void iomd_handle_irq(struct pt_regs *regs)
-{
- int irq;
-
- do {
- irq = iomd_get_irq_nr();
- if (irq)
- generic_handle_irq(irq);
- } while (irq);
-}
-
-static void __iomem *iomd_get_base(struct irq_data *d)
-{
- void *cd = irq_data_get_irq_chip_data(d);
-
- return (void __iomem *)(unsigned long)cd;
-}
-
-static void iomd_set_base_mask(unsigned int irq, void __iomem *base, u32 mask)
-{
- struct irq_data *d = irq_get_irq_data(irq);
-
- d->mask = mask;
- irq_set_chip_data(irq, (void *)(unsigned long)base);
-}
-
-static void iomd_irq_mask_ack(struct irq_data *d)
-{
- void __iomem *base = iomd_get_base(d);
- unsigned int val, mask = d->mask;
-
- val = readb(base + MASK);
- writeb(val & ~mask, base + MASK);
- writeb(mask, base + CLR);
-}
-
-static void iomd_irq_mask(struct irq_data *d)
-{
- void __iomem *base = iomd_get_base(d);
- unsigned int val, mask = d->mask;
-
- val = readb(base + MASK);
- writeb(val & ~mask, base + MASK);
-}
-
-static void iomd_irq_unmask(struct irq_data *d)
-{
- void __iomem *base = iomd_get_base(d);
- unsigned int val, mask = d->mask;
-
- val = readb(base + MASK);
- writeb(val | mask, base + MASK);
-}
-
-static struct irq_chip iomd_chip_clr = {
- .irq_mask_ack = iomd_irq_mask_ack,
- .irq_mask = iomd_irq_mask,
- .irq_unmask = iomd_irq_unmask,
-};
-
-static struct irq_chip iomd_chip_noclr = {
- .irq_mask = iomd_irq_mask,
- .irq_unmask = iomd_irq_unmask,
-};
-
-extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end;
-
-void __init rpc_init_irq(void)
-{
- unsigned int irq, clr, set;
-
- iomd_writeb(0, IOMD_IRQMASKA);
- iomd_writeb(0, IOMD_IRQMASKB);
- iomd_writeb(0, IOMD_FIQMASK);
- iomd_writeb(0, IOMD_DMAMASK);
-
- set_fiq_handler(&rpc_default_fiq_start,
- &rpc_default_fiq_end - &rpc_default_fiq_start);
-
- set_handle_irq(iomd_handle_irq);
-
- for (irq = 0; irq < NR_IRQS; irq++) {
- clr = IRQ_NOREQUEST;
- set = 0;
-
- if (irq <= 6 || (irq >= 9 && irq <= 15))
- clr |= IRQ_NOPROBE;
-
- if (irq == 21 || (irq >= 16 && irq <= 19) ||
- irq == IRQ_KEYBOARDTX)
- set |= IRQ_NOAUTOEN;
-
- switch (irq) {
- case 0 ... 7:
- irq_set_chip_and_handler(irq, &iomd_chip_clr,
- handle_level_irq);
- irq_modify_status(irq, clr, set);
- iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATA,
- BIT(irq));
- break;
-
- case 8 ... 15:
- irq_set_chip_and_handler(irq, &iomd_chip_noclr,
- handle_level_irq);
- irq_modify_status(irq, clr, set);
- iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATB,
- BIT(irq - 8));
- break;
-
- case 16 ... 21:
- irq_set_chip_and_handler(irq, &iomd_chip_noclr,
- handle_level_irq);
- irq_modify_status(irq, clr, set);
- iomd_set_base_mask(irq, IOMD_BASE + IOMD_DMASTAT,
- BIT(irq - 16));
- break;
-
- case 64 ... 71:
- irq_set_chip(irq, &iomd_chip_noclr);
- irq_modify_status(irq, clr, set);
- iomd_set_base_mask(irq, IOMD_BASE + IOMD_FIQSTAT,
- BIT(irq - 64));
- break;
- }
- }
-
- init_FIQ(FIQ_START);
-}
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
deleted file mode 100644
index f70fb9c4b0cb..000000000000
--- a/arch/arm/mach-rpc/riscpc.c
+++ /dev/null
@@ -1,225 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-rpc/riscpc.c
- *
- * Copyright (C) 1998-2001 Russell King
- *
- * Architecture specific fixups.
- */
-#include <linux/kernel.h>
-#include <linux/tty.h>
-#include <linux/delay.h>
-#include <linux/pm.h>
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/device.h>
-#include <linux/serial_8250.h>
-#include <linux/ata_platform.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/reboot.h>
-
-#include <asm/elf.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <asm/hardware/iomd.h>
-#include <asm/page.h>
-#include <asm/domain.h>
-#include <asm/setup.h>
-#include <asm/system_misc.h>
-
-#include <asm/mach/map.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-extern void rpc_init_irq(void);
-
-unsigned int vram_size;
-unsigned int memc_ctrl_reg;
-unsigned int number_mfm_drives;
-
-static int __init parse_tag_acorn(const struct tag *tag)
-{
- memc_ctrl_reg = tag->u.acorn.memc_control_reg;
- number_mfm_drives = tag->u.acorn.adfsdrives;
-
- switch (tag->u.acorn.vram_pages) {
- case 512:
- vram_size += PAGE_SIZE * 256;
- fallthrough; /* ??? */
- case 256:
- vram_size += PAGE_SIZE * 256;
- break;
- default:
- break;
- }
-#if 0
- if (vram_size) {
- desc->video_start = 0x02000000;
- desc->video_end = 0x02000000 + vram_size;
- }
-#endif
- return 0;
-}
-
-__tagtable(ATAG_ACORN, parse_tag_acorn);
-
-static struct map_desc rpc_io_desc[] __initdata = {
- { /* VRAM */
- .virtual = SCREEN_BASE,
- .pfn = __phys_to_pfn(SCREEN_START),
- .length = 2*1048576,
- .type = MT_DEVICE
- }, { /* IO space */
- .virtual = (u32)IO_BASE,
- .pfn = __phys_to_pfn(IO_START),
- .length = IO_SIZE ,
- .type = MT_DEVICE
- }, { /* EASI space */
- .virtual = (unsigned long)EASI_BASE,
- .pfn = __phys_to_pfn(EASI_START),
- .length = EASI_SIZE,
- .type = MT_DEVICE
- }
-};
-
-static void __init rpc_map_io(void)
-{
- iotable_init(rpc_io_desc, ARRAY_SIZE(rpc_io_desc));
-
- /*
- * Turn off floppy.
- */
- writeb(0xc, PCIO_BASE + (0x3f2 << 2));
-
- /*
- * RiscPC can't handle half-word loads and stores
- */
- elf_hwcap &= ~HWCAP_HALF;
-}
-
-static struct resource acornfb_resources[] = {
- /* VIDC */
- DEFINE_RES_MEM(0x03400000, 0x00200000),
- DEFINE_RES_IRQ(IRQ_VSYNCPULSE),
-};
-
-static struct platform_device acornfb_device = {
- .name = "acornfb",
- .id = -1,
- .dev = {
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(acornfb_resources),
- .resource = acornfb_resources,
-};
-
-static struct resource iomd_resources[] = {
- DEFINE_RES_MEM(0x03200000, 0x10000),
-};
-
-static struct platform_device iomd_device = {
- .name = "iomd",
- .id = -1,
- .num_resources = ARRAY_SIZE(iomd_resources),
- .resource = iomd_resources,
-};
-
-static struct resource iomd_kart_resources[] = {
- DEFINE_RES_IRQ(IRQ_KEYBOARDRX),
- DEFINE_RES_IRQ(IRQ_KEYBOARDTX),
-};
-
-static struct platform_device kbd_device = {
- .name = "kart",
- .id = -1,
- .dev = {
- .parent = &iomd_device.dev,
- },
- .num_resources = ARRAY_SIZE(iomd_kart_resources),
- .resource = iomd_kart_resources,
-};
-
-static struct plat_serial8250_port serial_platform_data[] = {
- {
- .mapbase = 0x03010fe0,
- .irq = IRQ_SERIALPORT,
- .uartclk = 1843200,
- .regshift = 2,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
- },
- { },
-};
-
-static struct platform_device serial_device = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = serial_platform_data,
- },
-};
-
-static struct pata_platform_info pata_platform_data = {
- .ioport_shift = 2,
-};
-
-static struct resource pata_resources[] = {
- DEFINE_RES_MEM(0x030107c0, 0x20),
- DEFINE_RES_MEM(0x03010fd8, 0x04),
- DEFINE_RES_IRQ(IRQ_HARDDISK),
-};
-
-static struct platform_device pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(pata_resources),
- .resource = pata_resources,
- .dev = {
- .platform_data = &pata_platform_data,
- .coherent_dma_mask = ~0, /* grumble */
- },
-};
-
-static struct platform_device *devs[] __initdata = {
- &iomd_device,
- &kbd_device,
- &serial_device,
- &acornfb_device,
- &pata_device,
-};
-
-static struct i2c_board_info i2c_rtc = {
- I2C_BOARD_INFO("pcf8583", 0x50)
-};
-
-static int __init rpc_init(void)
-{
- i2c_register_board_info(0, &i2c_rtc, 1);
- return platform_add_devices(devs, ARRAY_SIZE(devs));
-}
-
-arch_initcall(rpc_init);
-
-static void rpc_restart(enum reboot_mode mode, const char *cmd)
-{
- iomd_writeb(0, IOMD_ROMCR0);
-
- /*
- * Jump into the ROM
- */
- soft_restart(0);
-}
-
-void ioc_timer_init(void);
-
-MACHINE_START(RISCPC, "Acorn-RiscPC")
- /* Maintainer: Russell King */
- .atag_offset = 0x100,
- .reserve_lp0 = 1,
- .reserve_lp1 = 1,
- .map_io = rpc_map_io,
- .init_irq = rpc_init_irq,
- .init_time = ioc_timer_init,
- .restart = rpc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-rpc/time.c b/arch/arm/mach-rpc/time.c
deleted file mode 100644
index 9f8edcfe9357..000000000000
--- a/arch/arm/mach-rpc/time.c
+++ /dev/null
@@ -1,97 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/common/time-acorn.c
- *
- * Copyright (c) 1996-2000 Russell King.
- *
- * Changelog:
- * 24-Sep-1996 RMK Created
- * 10-Oct-1996 RMK Brought up to date with arch-sa110eval
- * 04-Dec-1997 RMK Updated for new arch/arm/time.c
- * 13=Jun-2004 DS Moved to arch/arm/common b/c shared w/CLPS7500
- */
-#include <linux/clocksource.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/hardware/ioc.h>
-
-#include <asm/mach/time.h>
-
-#define RPC_CLOCK_FREQ 2000000
-#define RPC_LATCH DIV_ROUND_CLOSEST(RPC_CLOCK_FREQ, HZ)
-
-static u32 ioc_time;
-
-static u64 ioc_timer_read(struct clocksource *cs)
-{
- unsigned int count1, count2, status;
- unsigned long flags;
- u32 ticks;
-
- local_irq_save(flags);
- ioc_writeb (0, IOC_T0LATCH);
- barrier ();
- count1 = ioc_readb(IOC_T0CNTL) | (ioc_readb(IOC_T0CNTH) << 8);
- barrier ();
- status = ioc_readb(IOC_IRQREQA);
- barrier ();
- ioc_writeb (0, IOC_T0LATCH);
- barrier ();
- count2 = ioc_readb(IOC_T0CNTL) | (ioc_readb(IOC_T0CNTH) << 8);
- ticks = ioc_time + RPC_LATCH - count2;
- local_irq_restore(flags);
-
- if (count2 < count1) {
- /*
- * The timer has not reloaded between reading count1 and
- * count2, check whether an interrupt was actually pending.
- */
- if (status & (1 << 5))
- ticks += RPC_LATCH;
- } else if (count2 > count1) {
- /*
- * The timer has reloaded, so count2 indicates the new
- * count since the wrap. The interrupt would not have
- * been processed, so add the missed ticks.
- */
- ticks += RPC_LATCH;
- }
-
- return ticks;
-}
-
-static struct clocksource ioctime_clocksource = {
- .read = ioc_timer_read,
- .mask = CLOCKSOURCE_MASK(32),
- .rating = 100,
-};
-
-void __init ioctime_init(void)
-{
- ioc_writeb(RPC_LATCH & 255, IOC_T0LTCHL);
- ioc_writeb(RPC_LATCH >> 8, IOC_T0LTCHH);
- ioc_writeb(0, IOC_T0GO);
-}
-
-static irqreturn_t
-ioc_timer_interrupt(int irq, void *dev_id)
-{
- ioc_time += RPC_LATCH;
- legacy_timer_tick(1);
- return IRQ_HANDLED;
-}
-
-/*
- * Set up timer interrupt.
- */
-void __init ioc_timer_init(void)
-{
- WARN_ON(clocksource_register_hz(&ioctime_clocksource, RPC_CLOCK_FREQ));
- ioctime_init();
- if (request_irq(IRQ_TIMER0, ioc_timer_interrupt, 0, "timer", NULL))
- pr_err("Failed to request irq %d (timer)\n", IRQ_TIMER0);
-}
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 350f6dcc24cc..07c2fda4d422 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -1112,7 +1112,7 @@ static void __init fill_pmd_gaps(void)
#define fill_pmd_gaps() do { } while (0)
#endif
-#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
+#if defined(CONFIG_PCI)
static void __init pci_reserve_io(void)
{
struct static_vm *svm;
diff --git a/block/partitions/Kconfig b/block/partitions/Kconfig
index ce17e41451af..94e7df547e7a 100644
--- a/block/partitions/Kconfig
+++ b/block/partitions/Kconfig
@@ -19,13 +19,11 @@ config PARTITION_ADVANCED
config ACORN_PARTITION
bool "Acorn partition support" if PARTITION_ADVANCED
- default y if ARCH_ACORN
help
Support hard disks partitioned under Acorn operating systems.
config ACORN_PARTITION_CUMANA
bool "Cumana partition support" if PARTITION_ADVANCED
- default y if ARCH_ACORN
depends on ACORN_PARTITION
help
Say Y here if you would like to use hard disks under Linux which
@@ -33,12 +31,10 @@ config ACORN_PARTITION_CUMANA
config ACORN_PARTITION_EESOX
bool "EESOX partition support" if PARTITION_ADVANCED
- default y if ARCH_ACORN
depends on ACORN_PARTITION
config ACORN_PARTITION_ICS
bool "ICS partition support" if PARTITION_ADVANCED
- default y if ARCH_ACORN
depends on ACORN_PARTITION
help
Say Y here if you would like to use hard disks under Linux which
@@ -46,7 +42,6 @@ config ACORN_PARTITION_ICS
config ACORN_PARTITION_ADFS
bool "Native filecore partition support" if PARTITION_ADVANCED
- default y if ARCH_ACORN
depends on ACORN_PARTITION
help
The Acorn Disc Filing System is the standard file system of the
@@ -56,7 +51,6 @@ config ACORN_PARTITION_ADFS
config ACORN_PARTITION_POWERTEC
bool "PowerTec partition support" if PARTITION_ADVANCED
- default y if ARCH_ACORN
depends on ACORN_PARTITION
help
Support reading partition tables created on Acorn machines using
@@ -64,7 +58,6 @@ config ACORN_PARTITION_POWERTEC
config ACORN_PARTITION_RISCIX
bool "RISCiX partition support" if PARTITION_ADVANCED
- default y if ARCH_ACORN
depends on ACORN_PARTITION
help
Once upon a time, there was a native Unix port for the Acorn series
diff --git a/drivers/tty/vt/keyboard.c b/drivers/tty/vt/keyboard.c
index c41d850b29c6..9770c83aea74 100644
--- a/drivers/tty/vt/keyboard.c
+++ b/drivers/tty/vt/keyboard.c
@@ -1308,7 +1308,7 @@ static void kbd_bh(struct tasklet_struct *unused)
#if defined(CONFIG_X86) || defined(CONFIG_ALPHA) ||\
defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_SPARC) ||\
defined(CONFIG_PARISC) || defined(CONFIG_SUPERH) ||\
- (defined(CONFIG_ARM) && defined(CONFIG_KEYBOARD_ATKBD) && !defined(CONFIG_ARCH_RPC))
+ (defined(CONFIG_ARM) && defined(CONFIG_KEYBOARD_ATKBD))
static inline bool kbd_is_hw_raw(const struct input_dev *dev)
{
diff --git a/lib/fonts/font_acorn_8x8.c b/lib/fonts/font_acorn_8x8.c
index 4ff52c79f8c4..ec2b1e463ab9 100644
--- a/lib/fonts/font_acorn_8x8.c
+++ b/lib/fonts/font_acorn_8x8.c
@@ -277,9 +277,5 @@ const struct font_desc font_acorn_8x8 = {
.height = 8,
.charcount = 256,
.data = acorndata_8x8.data,
-#ifdef CONFIG_ARCH_ACORN
- .pref = 20,
-#else
.pref = 0,
-#endif
};
--
2.53.0
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 03/13] ARM: remove riscpc
2026-09-08 15:27 ` [PATCH 03/13] ARM: remove riscpc Arnd Bergmann
@ 2026-09-09 8:04 ` Thomas Zimmermann
2026-09-09 16:42 ` Bart Van Assche
1 sibling, 0 replies; 70+ messages in thread
From: Thomas Zimmermann @ 2026-09-09 8:04 UTC (permalink / raw)
To: Arnd Bergmann, Krzysztof Kozlowski, Alexandre Belloni,
Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Ian Molton, Jens Axboe,
Helge Deller, Paul E. McKenney, linux-block, linux-serial,
linux-fbdev
Hi
Am 08.09.26 um 17:27 schrieb Arnd Bergmann:
[...]
> lib/fonts/font_acorn_8x8.c | 4 -
Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> # lib/fonts
> 41 files changed, 12 insertions(+), 3688 deletions(-)
> delete mode 100644 arch/arm/boot/compressed/font.c
> delete mode 100644 arch/arm/boot/compressed/ll_char_wr.S
> delete mode 100644 arch/arm/configs/rpc_defconfig
> delete mode 100644 arch/arm/include/asm/ecard.h
> delete mode 100644 arch/arm/include/asm/hardware/ioc.h
> delete mode 100644 arch/arm/include/asm/hardware/iomd.h
> delete mode 100644 arch/arm/include/asm/hardware/memc.h
> delete mode 100644 arch/arm/mach-rpc/Kconfig
> delete mode 100644 arch/arm/mach-rpc/Makefile
> delete mode 100644 arch/arm/mach-rpc/dma.c
> delete mode 100644 arch/arm/mach-rpc/ecard-loader.S
> delete mode 100644 arch/arm/mach-rpc/ecard.c
> delete mode 100644 arch/arm/mach-rpc/ecard.h
> delete mode 100644 arch/arm/mach-rpc/fiq.S
> delete mode 100644 arch/arm/mach-rpc/floppydma.S
> delete mode 100644 arch/arm/mach-rpc/include/mach/acornfb.h
> delete mode 100644 arch/arm/mach-rpc/include/mach/hardware.h
> delete mode 100644 arch/arm/mach-rpc/include/mach/io.h
> delete mode 100644 arch/arm/mach-rpc/include/mach/irqs.h
> delete mode 100644 arch/arm/mach-rpc/include/mach/isa-dma.h
> delete mode 100644 arch/arm/mach-rpc/include/mach/memory.h
> delete mode 100644 arch/arm/mach-rpc/include/mach/uncompress.h
> delete mode 100644 arch/arm/mach-rpc/io-acorn.S
> delete mode 100644 arch/arm/mach-rpc/irq.c
> delete mode 100644 arch/arm/mach-rpc/riscpc.c
> delete mode 100644 arch/arm/mach-rpc/time.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4380d5660402..6e8fe7640064 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2350,12 +2350,6 @@ F: Documentation/devicetree/bindings/display/arm,malidp.yaml
> F: Documentation/gpu/afbc.rst
> F: drivers/gpu/drm/arm/
>
> -ARM MFM AND FLOPPY DRIVERS
> -M: Ian Molton <spyro@f2s.com>
> -S: Maintained
> -F: arch/arm/include/asm/floppy.h
> -F: arch/arm/mach-rpc/floppydma.S
> -
> ARM PMU PROFILING AND DEBUGGING
> M: Will Deacon <will@kernel.org>
> M: Mark Rutland <mark.rutland@arm.com>
> @@ -3494,20 +3488,6 @@ F: include/linux/soc/renesas/
> N: rcar
> K: \brenesas,
>
> -ARM/RISCPC ARCHITECTURE
> -M: Russell King <linux@armlinux.org.uk>
> -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> -S: Maintained
> -W: http://www.armlinux.org.uk/
> -F: arch/arm/include/asm/hardware/ioc.h
> -F: arch/arm/include/asm/hardware/iomd.h
> -F: arch/arm/include/asm/hardware/memc.h
> -F: arch/arm/mach-rpc/
> -F: drivers/net/ethernet/8390/etherh.c
> -F: drivers/net/ethernet/i825xx/ether1*
> -F: drivers/net/ethernet/seeq/ether3*
> -F: drivers/scsi/arm/
> -
> ARM/Rockchip SoC support
> M: Heiko Stuebner <heiko@sntech.de>
> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index c3d6b8abc815..5770deca136d 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -55,7 +55,7 @@ config ARM
> select ARCH_WANT_LD_ORPHAN_WARN
> select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
> select BUILDTIME_TABLE_SORT if MMU
> - select COMMON_CLK if !ARCH_RPC
> + select COMMON_CLK
> select CLONE_BACKWARDS
> select CPU_PM if SUSPEND || CPU_IDLE
> select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
> @@ -155,13 +155,13 @@ config ARM
> select PCI_SYSCALL if PCI
> select PERF_USE_VMALLOC
> select RTC_LIB
> - select SPARSE_IRQ if !ARCH_RPC
> + select SPARSE_IRQ
> select SYS_SUPPORTS_APM_EMULATION
> select THREAD_INFO_IN_TASK
> select TIMER_OF if OF
> select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
> select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
> - select USE_OF if !ARCH_RPC
> + select USE_OF
> # Above selects are sorted alphabetically; please add new ones
> # according to that. Thanks.
> help
> @@ -277,25 +277,11 @@ config ARM_PATCH_PHYS_VIRT
> this feature (eg, building a kernel for a single machine) and
> you need to shrink the kernel to the minimal size.
>
> -config NEED_MACH_IO_H
> - bool
> - help
> - Select this when mach/io.h is required to provide special
> - definitions for this platform. The need for mach/io.h should
> - be avoided when possible.
> -
> -config NEED_MACH_MEMORY_H
> - bool
> - help
> - Select this when mach/memory.h is required to provide special
> - definitions for this platform. The need for mach/memory.h should
> - be avoided when possible.
> -
> config PHYS_OFFSET
> hex "Physical address of main memory" if MMU
> depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR
> default DRAM_BASE if !MMU
> - default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
> + default 0x10000000 if ARCH_OMAP1
> default 0xa0000000 if ARCH_PXA
> default 0xc0000000 if ARCH_EP93XX
> default 0
> @@ -337,7 +323,7 @@ config ARCH_MMAP_RND_BITS_MAX
>
> config ARCH_MULTIPLATFORM
> bool "Require kernel to be portable to multiple machines" if EXPERT
> - depends on MMU && !ARCH_RPC
> + depends on MMU
> default y
> help
> In general, all Arm machines can be supported in a single
> @@ -429,8 +415,6 @@ source "arch/arm/mach-qcom/Kconfig"
>
> source "arch/arm/mach-realtek/Kconfig"
>
> -source "arch/arm/mach-rpc/Kconfig"
> -
> source "arch/arm/mach-rockchip/Kconfig"
>
> source "arch/arm/mach-s3c/Kconfig"
> @@ -490,9 +474,6 @@ config ARCH_MPS2
> This platform is scheduled for removal in early 2027
>
> # Definitions to make life easier
> -config ARCH_ACORN
> - bool
> -
> config PLAT_ORION
> bool
> select CLKSRC_MMIO
> @@ -1191,7 +1172,7 @@ config ARCH_SELECT_MEMORY_MODEL
> def_bool y
>
> config ARCH_FLATMEM_ENABLE
> - def_bool !ARCH_RPC
> + def_bool y
>
> config ARCH_SPARSEMEM_ENABLE
> def_bool y
> @@ -1594,7 +1575,7 @@ config ARCH_DEFAULT_CRASH_DUMP
>
> config AUTO_ZRELADDR
> bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM
> - default !ARCH_RPC
> + default y
> help
> ZRELADDR is the physical address where the decompressed kernel
> image will be placed. If AUTO_ZRELADDR is selected, the address
> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index f2a80955b7a0..56c090840c5a 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -1446,7 +1446,7 @@ config DEBUG_STM32_UART
> config DEBUG_UART_FLOW_CONTROL
> bool "Enable flow control (CTS) for the debug UART"
> depends on DEBUG_LL
> - default y if DEBUG_GEMINI || ARCH_RPC
> + default y if DEBUG_GEMINI
> help
> Some UART ports are connected to terminals that will use modem
> control signals to indicate whether they are ready to receive text.
> @@ -1516,7 +1516,7 @@ config DEBUG_UART_PL01X
>
> # Compatibility options for 8250
> config DEBUG_UART_8250
> - def_bool ARCH_IXP4XX || ARCH_RPC
> + def_bool ARCH_IXP4XX
>
> config DEBUG_UART_PHYS
> hex "Physical base address of debug UART"
> @@ -1527,7 +1527,6 @@ config DEBUG_UART_PHYS
> default 0x01f02800 if DEBUG_SUNXI_R_UART
> default 0x02530c00 if DEBUG_KEYSTONE_UART0
> default 0x02531000 if DEBUG_KEYSTONE_UART1
> - default 0x03010fe0 if ARCH_RPC
> default 0x07000000 if DEBUG_SUN9I_UART0
> default 0x09530000 if DEBUG_STIH418_SBC_ASC0
> default 0x10009000 if DEBUG_REALVIEW_STD_PORT || \
> @@ -1654,7 +1653,6 @@ config DEBUG_UART_VIRT
> default 0xc881f000 if DEBUG_RV1108_UART2
> default 0xc8821000 if DEBUG_RV1108_UART1
> default 0xc8912000 if DEBUG_RV1108_UART0
> - default 0xe0010fe0 if ARCH_RPC
> default 0xe0824200 if DEBUG_AT91_SAMA7G5_FLEXCOM3
> default 0xf0010000 if DEBUG_ASM9260_UART
> default 0xf0100000 if DEBUG_DIGICOLOR_UA0
> @@ -1779,7 +1777,6 @@ config DEBUG_UART_8250_PALMCHIP
> config DEBUG_UNCOMPRESS
> bool "Enable decompressor debugging via DEBUG_LL output"
> depends on !ARCH_MULTIPLATFORM
> - depends on !ARCH_RPC
> depends on DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
> (!DEBUG_TEGRA_UART || !ZBOOT_ROM) && \
> !DEBUG_BRCMSTB_UART && !DEBUG_SEMIHOSTING
> @@ -1789,7 +1786,6 @@ config DEBUG_UNCOMPRESS
>
> config UNCOMPRESS_INCLUDE
> string
> - default "mach/uncompress.h" if ARCH_RPC
> default "debug/uncompress.h"
>
> config EARLY_PRINTK
> diff --git a/arch/arm/boot/bootp/Makefile b/arch/arm/boot/bootp/Makefile
> index 12c61684b97f..1e47bf10069d 100644
> --- a/arch/arm/boot/bootp/Makefile
> +++ b/arch/arm/boot/bootp/Makefile
> @@ -19,8 +19,6 @@ add_hex = $(shell printf 0x%x $$(( $(1) + $(2) )) )
> PARAMS_PHYS := $(call add_hex, $(PHYS_OFFSET), 0x100)
>
> # guess an initrd location if possible
> -initrd_offset-$(CONFIG_ARCH_RPC) += 0x08000000
> -INITRD_OFFSET := $(initrd_offset-y)
> ifdef INITRD_OFFSET
> INITRD_PHYS := $(call add_hex, $(PHYS_OFFSET), $(INITRD_OFFSET))
> endif
> diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
> index d8d81ba741a2..32def10f5e03 100644
> --- a/arch/arm/boot/compressed/Makefile
> +++ b/arch/arm/boot/compressed/Makefile
> @@ -25,10 +25,6 @@ endif
> #
> # Architecture dependencies
> #
> -ifeq ($(CONFIG_ARCH_ACORN),y)
> -OBJS += ll_char_wr.o font.o
> -endif
> -
> ifeq ($(CONFIG_CPU_XSCALE),y)
> OBJS += head-xscale.o
> endif
> diff --git a/arch/arm/boot/compressed/font.c b/arch/arm/boot/compressed/font.c
> deleted file mode 100644
> index 46a677649db4..000000000000
> --- a/arch/arm/boot/compressed/font.c
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -#include "../../../../lib/fonts/font_acorn_8x8.c"
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index 845abffbc2d6..af579905b630 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -668,14 +668,6 @@ LC1: .word .L_user_stack_end - LC1 @ sp
> .Linflated_image_size_offset:
> .long (input_data_end - 4) - .
>
> -#ifdef CONFIG_ARCH_RPC
> - .globl params
> -params: ldr r0, =0x10000100 @ params_phys for RPC
> - mov pc, lr
> - .ltorg
> - .align
> -#endif
> -
> /*
> * dcache_line_size - get the minimum D-cache line size from the CTR register
> * on ARMv7.
> diff --git a/arch/arm/boot/compressed/ll_char_wr.S b/arch/arm/boot/compressed/ll_char_wr.S
> deleted file mode 100644
> index 1ec8cb2898b1..000000000000
> --- a/arch/arm/boot/compressed/ll_char_wr.S
> +++ /dev/null
> @@ -1,131 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * linux/arch/arm/lib/ll_char_wr.S
> - *
> - * Copyright (C) 1995, 1996 Russell King.
> - *
> - * Speedups & 1bpp code (C) 1996 Philip Blundell & Russell King.
> - *
> - * 10-04-96 RMK Various cleanups & reduced register usage.
> - * 08-04-98 RMK Shifts re-ordered
> - */
> -
> -@ Regs: [] = corruptible
> -@ {} = used
> -@ () = do not use
> -
> -#include <linux/linkage.h>
> -#include <asm/assembler.h>
> - .text
> -
> -LC0: .word LC0
> - .word bytes_per_char_h
> - .word video_size_row
> - .word acorndata_8x8
> - .word con_charconvtable
> -
> -/*
> - * r0 = ptr
> - * r1 = char
> - * r2 = white
> - */
> -ENTRY(ll_write_char)
> - stmfd sp!, {r4 - r7, lr}
> -@
> -@ Smashable regs: {r0 - r3}, [r4 - r7], (r8 - fp), [ip], (sp), [lr], (pc)
> -@
> - /*
> - * calculate offset into character table
> - */
> - mov r1, r1, lsl #3
> - /*
> - * calculate offset required for each row.
> - */
> - adr ip, LC0
> - ldmia ip, {r3, r4, r5, r6, lr}
> - sub ip, ip, r3
> - add r6, r6, ip
> - add lr, lr, ip
> - ldr r4, [r4, ip]
> - ldr r5, [r5, ip]
> - /*
> - * Go to resolution-dependent routine...
> - */
> - cmp r4, #4
> - blt Lrow1bpp
> - add r0, r0, r5, lsl #3 @ Move to bottom of character
> - orr r1, r1, #7
> - ldrb r7, [r6, r1]
> - teq r4, #8
> - beq Lrow8bpplp
> -@
> -@ Smashable regs: {r0 - r3}, [r4], {r5 - r7}, (r8 - fp), [ip], (sp), {lr}, (pc)
> -@
> -Lrow4bpplp:
> - ldr r7, [lr, r7, lsl #2]
> - mul r7, r2, r7
> - sub r1, r1, #1 @ avoid using r7 directly after
> - str r7, [r0, -r5]!
> - ldrb r7, [r6, r1]
> - ldr r7, [lr, r7, lsl #2]
> - mul r7, r2, r7
> - tst r1, #7 @ avoid using r7 directly after
> - str r7, [r0, -r5]!
> - subne r1, r1, #1
> - ldrbne r7, [r6, r1]
> - bne Lrow4bpplp
> - ldmfd sp!, {r4 - r7, pc}
> -
> -@
> -@ Smashable regs: {r0 - r3}, [r4], {r5 - r7}, (r8 - fp), [ip], (sp), {lr}, (pc)
> -@
> -Lrow8bpplp:
> - mov ip, r7, lsr #4
> - ldr ip, [lr, ip, lsl #2]
> - mul r4, r2, ip
> - and ip, r7, #15 @ avoid r4
> - ldr ip, [lr, ip, lsl #2] @ avoid r4
> - mul ip, r2, ip @ avoid r4
> - sub r1, r1, #1 @ avoid ip
> - sub r0, r0, r5 @ avoid ip
> - stmia r0, {r4, ip}
> - ldrb r7, [r6, r1]
> - mov ip, r7, lsr #4
> - ldr ip, [lr, ip, lsl #2]
> - mul r4, r2, ip
> - and ip, r7, #15 @ avoid r4
> - ldr ip, [lr, ip, lsl #2] @ avoid r4
> - mul ip, r2, ip @ avoid r4
> - tst r1, #7 @ avoid ip
> - sub r0, r0, r5 @ avoid ip
> - stmia r0, {r4, ip}
> - subne r1, r1, #1
> - ldrbne r7, [r6, r1]
> - bne Lrow8bpplp
> - ldmfd sp!, {r4 - r7, pc}
> -
> -@
> -@ Smashable regs: {r0 - r3}, [r4], {r5, r6}, [r7], (r8 - fp), [ip], (sp), [lr], (pc)
> -@
> -Lrow1bpp:
> - add r6, r6, r1
> - ldmia r6, {r4, r7}
> - strb r4, [r0], r5
> - mov r4, r4, lsr #8
> - strb r4, [r0], r5
> - mov r4, r4, lsr #8
> - strb r4, [r0], r5
> - mov r4, r4, lsr #8
> - strb r4, [r0], r5
> - strb r7, [r0], r5
> - mov r7, r7, lsr #8
> - strb r7, [r0], r5
> - mov r7, r7, lsr #8
> - strb r7, [r0], r5
> - mov r7, r7, lsr #8
> - strb r7, [r0], r5
> - ldmfd sp!, {r4 - r7, pc}
> -
> - .bss
> -ENTRY(con_charconvtable)
> - .space 1024
> diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig
> deleted file mode 100644
> index edb52d56f679..000000000000
> --- a/arch/arm/configs/rpc_defconfig
> +++ /dev/null
> @@ -1,127 +0,0 @@
> -# CONFIG_LOCALVERSION_AUTO is not set
> -CONFIG_SYSVIPC=y
> -CONFIG_LOG_BUF_SHIFT=14
> -CONFIG_BLK_DEV_INITRD=y
> -CONFIG_EXPERT=y
> -CONFIG_ARCH_MULTI_V4=y
> -# CONFIG_ARCH_MULTI_V7 is not set
> -CONFIG_ARCH_RPC=y
> -CONFIG_CPU_SA110=y
> -CONFIG_FPE_NWFPE=y
> -# CONFIG_AEABI is not set
> -CONFIG_ATAGS=y
> -CONFIG_MODULES=y
> -CONFIG_MODULE_UNLOAD=y
> -CONFIG_PARTITION_ADVANCED=y
> -CONFIG_BSD_DISKLABEL=y
> -CONFIG_NET=y
> -CONFIG_PACKET=y
> -CONFIG_UNIX=y
> -CONFIG_INET=y
> -CONFIG_IP_MULTICAST=y
> -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> -# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> -# CONFIG_INET_XFRM_MODE_BEET is not set
> -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
> -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
> -# CONFIG_INET6_XFRM_MODE_BEET is not set
> -CONFIG_PARPORT=y
> -CONFIG_PARPORT_PC=y
> -CONFIG_PARPORT_PC_FIFO=y
> -CONFIG_BLK_DEV_FD=y
> -CONFIG_BLK_DEV_LOOP=m
> -CONFIG_BLK_DEV_RAM=y
> -CONFIG_BLK_DEV_SD=y
> -CONFIG_CHR_DEV_ST=m
> -CONFIG_BLK_DEV_SR=y
> -CONFIG_CHR_DEV_SG=y
> -# CONFIG_BLK_DEV_BSG is not set
> -CONFIG_SCSI_CONSTANTS=y
> -CONFIG_SCSI_LOGGING=y
> -CONFIG_SCSI_ARXESCSI=m
> -CONFIG_SCSI_CUMANA_2=m
> -CONFIG_SCSI_EESOXSCSI=m
> -CONFIG_SCSI_POWERTECSCSI=y
> -CONFIG_SCSI_CUMANA_1=m
> -CONFIG_SCSI_OAK1=m
> -CONFIG_ATA=y
> -CONFIG_PATA_ICSIDE=y
> -CONFIG_PATA_PLATFORM=y
> -CONFIG_NETDEVICES=y
> -CONFIG_ARM_ETHER1=y
> -CONFIG_ARM_ETHER3=y
> -CONFIG_ARM_ETHERH=y
> -CONFIG_PPP=m
> -CONFIG_PPPOE=m
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_MOUSE_PS2 is not set
> -CONFIG_MOUSE_RISCPC=y
> -# CONFIG_SERIO_SERPORT is not set
> -CONFIG_LEGACY_PTY_COUNT=64
> -CONFIG_SERIAL_8250=y
> -CONFIG_SERIAL_8250_CONSOLE=y
> -CONFIG_SERIAL_8250_NR_UARTS=16
> -CONFIG_SERIAL_8250_RUNTIME_UARTS=8
> -CONFIG_SERIAL_8250_ACORN=y
> -CONFIG_PRINTER=m
> -# CONFIG_HW_RANDOM is not set
> -CONFIG_I2C=y
> -CONFIG_I2C_CHARDEV=y
> -# CONFIG_HWMON is not set
> -CONFIG_FB=y
> -CONFIG_FB_ACORN=y
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -CONFIG_LOGO=y
> -CONFIG_SOUND=m
> -CONFIG_SOUND_PRIME=m
> -CONFIG_SOUND_OSS=m
> -CONFIG_SOUND_VIDC=m
> -# CONFIG_USB_SUPPORT is not set
> -CONFIG_RTC_CLASS=y
> -CONFIG_RTC_DRV_PCF8583=y
> -CONFIG_EXT2_FS=y
> -CONFIG_EXT4_FS=y
> -CONFIG_AUTOFS_FS=m
> -CONFIG_ISO9660_FS=y
> -CONFIG_JOLIET=y
> -CONFIG_MSDOS_FS=m
> -CONFIG_VFAT_FS=m
> -CONFIG_ADFS_FS=y
> -CONFIG_NFS_FS=y
> -# CONFIG_ACORN_PARTITION_CUMANA is not set
> -# CONFIG_ACORN_PARTITION_EESOX is not set
> -CONFIG_NLS_CODEPAGE_437=m
> -CONFIG_NLS_CODEPAGE_737=m
> -CONFIG_NLS_CODEPAGE_775=m
> -CONFIG_NLS_CODEPAGE_850=m
> -CONFIG_NLS_CODEPAGE_852=m
> -CONFIG_NLS_CODEPAGE_855=m
> -CONFIG_NLS_CODEPAGE_857=m
> -CONFIG_NLS_CODEPAGE_860=m
> -CONFIG_NLS_CODEPAGE_861=m
> -CONFIG_NLS_CODEPAGE_862=m
> -CONFIG_NLS_CODEPAGE_863=m
> -CONFIG_NLS_CODEPAGE_864=m
> -CONFIG_NLS_CODEPAGE_865=m
> -CONFIG_NLS_CODEPAGE_866=m
> -CONFIG_NLS_CODEPAGE_869=m
> -CONFIG_NLS_CODEPAGE_874=m
> -CONFIG_NLS_ISO8859_8=m
> -CONFIG_NLS_ASCII=y
> -CONFIG_NLS_ISO8859_1=m
> -CONFIG_NLS_ISO8859_2=m
> -CONFIG_NLS_ISO8859_3=m
> -CONFIG_NLS_ISO8859_4=m
> -CONFIG_NLS_ISO8859_5=m
> -CONFIG_NLS_ISO8859_6=m
> -CONFIG_NLS_ISO8859_7=m
> -CONFIG_NLS_ISO8859_9=m
> -CONFIG_NLS_KOI8_R=m
> -CONFIG_FONTS=y
> -CONFIG_FONT_8x16=y
> -CONFIG_FONT_ACORN_8x8=y
> -CONFIG_DEBUG_KERNEL=y
> -CONFIG_MAGIC_SYSRQ=y
> -CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_LL=y
> -CONFIG_DEBUG_LL_UART_8250=y
> diff --git a/arch/arm/include/asm/ecard.h b/arch/arm/include/asm/ecard.h
> deleted file mode 100644
> index 7cbe001bf9cc..000000000000
> --- a/arch/arm/include/asm/ecard.h
> +++ /dev/null
> @@ -1,219 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * arch/arm/include/asm/ecard.h
> - *
> - * definitions for expansion cards
> - *
> - * This is a new system as from Linux 1.2.3
> - *
> - * Changelog:
> - * 11-12-1996 RMK Further minor improvements
> - * 12-09-1997 RMK Added interrupt enable/disable for card level
> - *
> - * Reference: Acorns Risc OS 3 Programmers Reference Manuals.
> - */
> -
> -#ifndef __ASM_ECARD_H
> -#define __ASM_ECARD_H
> -
> -/*
> - * Currently understood cards (but not necessarily
> - * supported):
> - * Manufacturer Product ID
> - */
> -#define MANU_ACORN 0x0000
> -#define PROD_ACORN_SCSI 0x0002
> -#define PROD_ACORN_ETHER1 0x0003
> -#define PROD_ACORN_MFM 0x000b
> -
> -#define MANU_ANT2 0x0011
> -#define PROD_ANT_ETHER3 0x00a4
> -
> -#define MANU_ATOMWIDE 0x0017
> -#define PROD_ATOMWIDE_3PSERIAL 0x0090
> -
> -#define MANU_IRLAM_INSTRUMENTS 0x001f
> -#define MANU_IRLAM_INSTRUMENTS_ETHERN 0x5678
> -
> -#define MANU_OAK 0x0021
> -#define PROD_OAK_SCSI 0x0058
> -
> -#define MANU_MORLEY 0x002b
> -#define PROD_MORLEY_SCSI_UNCACHED 0x0067
> -
> -#define MANU_CUMANA 0x003a
> -#define PROD_CUMANA_SCSI_2 0x003a
> -#define PROD_CUMANA_SCSI_1 0x00a0
> -
> -#define MANU_ICS 0x003c
> -#define PROD_ICS_IDE 0x00ae
> -
> -#define MANU_ICS2 0x003d
> -#define PROD_ICS2_IDE 0x00ae
> -
> -#define MANU_SERPORT 0x003f
> -#define PROD_SERPORT_DSPORT 0x00b9
> -
> -#define MANU_ARXE 0x0041
> -#define PROD_ARXE_SCSI 0x00be
> -
> -#define MANU_I3 0x0046
> -#define PROD_I3_ETHERLAN500 0x00d4
> -#define PROD_I3_ETHERLAN600 0x00ec
> -#define PROD_I3_ETHERLAN600A 0x011e
> -
> -#define MANU_ANT 0x0053
> -#define PROD_ANT_ETHERM 0x00d8
> -#define PROD_ANT_ETHERB 0x00e4
> -
> -#define MANU_ALSYSTEMS 0x005b
> -#define PROD_ALSYS_SCSIATAPI 0x0107
> -
> -#define MANU_MCS 0x0063
> -#define PROD_MCS_CONNECT32 0x0125
> -
> -#define MANU_EESOX 0x0064
> -#define PROD_EESOX_SCSI2 0x008c
> -
> -#define MANU_YELLOWSTONE 0x0096
> -#define PROD_YELLOWSTONE_RAPIDE32 0x0120
> -
> -#ifdef ECARD_C
> -#define CONST
> -#else
> -#define CONST const
> -#endif
> -
> -#define MAX_ECARDS 9
> -
> -struct ecard_id { /* Card ID structure */
> - unsigned short manufacturer;
> - unsigned short product;
> - void *data;
> -};
> -
> -struct in_ecid { /* Packed card ID information */
> - unsigned short product; /* Product code */
> - unsigned short manufacturer; /* Manufacturer code */
> - unsigned char id:4; /* Simple ID */
> - unsigned char cd:1; /* Chunk dir present */
> - unsigned char is:1; /* Interrupt status pointers */
> - unsigned char w:2; /* Width */
> - unsigned char country; /* Country */
> - unsigned char irqmask; /* IRQ mask */
> - unsigned char fiqmask; /* FIQ mask */
> - unsigned long irqoff; /* IRQ offset */
> - unsigned long fiqoff; /* FIQ offset */
> -};
> -
> -typedef struct expansion_card ecard_t;
> -typedef unsigned long *loader_t;
> -
> -typedef struct expansion_card_ops { /* Card handler routines */
> - void (*irqenable)(ecard_t *ec, int irqnr);
> - void (*irqdisable)(ecard_t *ec, int irqnr);
> - int (*irqpending)(ecard_t *ec);
> - void (*fiqenable)(ecard_t *ec, int fiqnr);
> - void (*fiqdisable)(ecard_t *ec, int fiqnr);
> - int (*fiqpending)(ecard_t *ec);
> -} expansioncard_ops_t;
> -
> -#define ECARD_NUM_RESOURCES (6)
> -
> -#define ECARD_RES_IOCSLOW (0)
> -#define ECARD_RES_IOCMEDIUM (1)
> -#define ECARD_RES_IOCFAST (2)
> -#define ECARD_RES_IOCSYNC (3)
> -#define ECARD_RES_MEMC (4)
> -#define ECARD_RES_EASI (5)
> -
> -#define ecard_resource_start(ec,nr) ((ec)->resource[nr].start)
> -#define ecard_resource_end(ec,nr) ((ec)->resource[nr].end)
> -#define ecard_resource_len(ec,nr) ((ec)->resource[nr].end - \
> - (ec)->resource[nr].start + 1)
> -#define ecard_resource_flags(ec,nr) ((ec)->resource[nr].flags)
> -
> -/*
> - * This contains all the info needed on an expansion card
> - */
> -struct expansion_card {
> - struct expansion_card *next;
> -
> - struct device dev;
> - struct resource resource[ECARD_NUM_RESOURCES];
> -
> - /* Public data */
> - void __iomem *irqaddr; /* address of IRQ register */
> - void __iomem *fiqaddr; /* address of FIQ register */
> - unsigned char irqmask; /* IRQ mask */
> - unsigned char fiqmask; /* FIQ mask */
> - unsigned char claimed; /* Card claimed? */
> - unsigned char easi; /* EASI card */
> -
> - void *irq_data; /* Data for use for IRQ by card */
> - void *fiq_data; /* Data for use for FIQ by card */
> - const expansioncard_ops_t *ops; /* Enable/Disable Ops for card */
> -
> - CONST unsigned int slot_no; /* Slot number */
> - CONST unsigned int dma; /* DMA number (for request_dma) */
> - CONST unsigned int irq; /* IRQ number (for request_irq) */
> - CONST unsigned int fiq; /* FIQ number (for request_irq) */
> - CONST struct in_ecid cid; /* Card Identification */
> -
> - /* Private internal data */
> - const char *card_desc; /* Card description */
> - CONST loader_t loader; /* loader program */
> - u64 dma_mask;
> -};
> -
> -void ecard_setirq(struct expansion_card *ec, const struct expansion_card_ops *ops, void *irq_data);
> -
> -struct in_chunk_dir {
> - unsigned int start_offset;
> - union {
> - unsigned char string[256];
> - unsigned char data[1];
> - } d;
> -};
> -
> -/*
> - * Read a chunk from an expansion card
> - * cd : where to put read data
> - * ec : expansion card info struct
> - * id : id number to find
> - * num: (n+1)'th id to find.
> - */
> -extern int ecard_readchunk (struct in_chunk_dir *cd, struct expansion_card *ec, int id, int num);
> -
> -/*
> - * Request and release ecard resources
> - */
> -extern int ecard_request_resources(struct expansion_card *ec);
> -extern void ecard_release_resources(struct expansion_card *ec);
> -
> -void __iomem *ecardm_iomap(struct expansion_card *ec, unsigned int res,
> - unsigned long offset, unsigned long maxsize);
> -#define ecardm_iounmap(__ec, __addr) devm_iounmap(&(__ec)->dev, __addr)
> -
> -extern const struct bus_type ecard_bus_type;
> -
> -#define ECARD_DEV(_d) container_of((_d), struct expansion_card, dev)
> -
> -struct ecard_driver {
> - int (*probe)(struct expansion_card *, const struct ecard_id *id);
> - void (*remove)(struct expansion_card *);
> - void (*shutdown)(struct expansion_card *);
> - const struct ecard_id *id_table;
> - unsigned int id;
> - struct device_driver drv;
> -};
> -
> -#define ECARD_DRV(_d) container_of((_d), struct ecard_driver, drv)
> -
> -#define ecard_set_drvdata(ec,data) dev_set_drvdata(&(ec)->dev, (data))
> -#define ecard_get_drvdata(ec) dev_get_drvdata(&(ec)->dev)
> -
> -int ecard_register_driver(struct ecard_driver *);
> -void ecard_remove_driver(struct ecard_driver *);
> -
> -#endif
> diff --git a/arch/arm/include/asm/hardware/ioc.h b/arch/arm/include/asm/hardware/ioc.h
> deleted file mode 100644
> index 6edd27fcd048..000000000000
> --- a/arch/arm/include/asm/hardware/ioc.h
> +++ /dev/null
> @@ -1,69 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * arch/arm/include/asm/hardware/ioc.h
> - *
> - * Copyright (C) Russell King
> - *
> - * Use these macros to read/write the IOC. All it does is perform the actual
> - * read/write.
> - */
> -#ifndef __ASMARM_HARDWARE_IOC_H
> -#define __ASMARM_HARDWARE_IOC_H
> -
> -#ifndef __ASSEMBLY__
> -
> -/*
> - * We use __raw_base variants here so that we give the compiler the
> - * chance to keep IOC_BASE in a register.
> - */
> -#define ioc_readb(off) __raw_readb(IOC_BASE + (off))
> -#define ioc_writeb(val,off) __raw_writeb(val, IOC_BASE + (off))
> -
> -#endif
> -
> -#define IOC_CONTROL (0x00)
> -#define IOC_KARTTX (0x04)
> -#define IOC_KARTRX (0x04)
> -
> -#define IOC_IRQSTATA (0x10)
> -#define IOC_IRQREQA (0x14)
> -#define IOC_IRQCLRA (0x14)
> -#define IOC_IRQMASKA (0x18)
> -
> -#define IOC_IRQSTATB (0x20)
> -#define IOC_IRQREQB (0x24)
> -#define IOC_IRQMASKB (0x28)
> -
> -#define IOC_FIQSTAT (0x30)
> -#define IOC_FIQREQ (0x34)
> -#define IOC_FIQMASK (0x38)
> -
> -#define IOC_T0CNTL (0x40)
> -#define IOC_T0LTCHL (0x40)
> -#define IOC_T0CNTH (0x44)
> -#define IOC_T0LTCHH (0x44)
> -#define IOC_T0GO (0x48)
> -#define IOC_T0LATCH (0x4c)
> -
> -#define IOC_T1CNTL (0x50)
> -#define IOC_T1LTCHL (0x50)
> -#define IOC_T1CNTH (0x54)
> -#define IOC_T1LTCHH (0x54)
> -#define IOC_T1GO (0x58)
> -#define IOC_T1LATCH (0x5c)
> -
> -#define IOC_T2CNTL (0x60)
> -#define IOC_T2LTCHL (0x60)
> -#define IOC_T2CNTH (0x64)
> -#define IOC_T2LTCHH (0x64)
> -#define IOC_T2GO (0x68)
> -#define IOC_T2LATCH (0x6c)
> -
> -#define IOC_T3CNTL (0x70)
> -#define IOC_T3LTCHL (0x70)
> -#define IOC_T3CNTH (0x74)
> -#define IOC_T3LTCHH (0x74)
> -#define IOC_T3GO (0x78)
> -#define IOC_T3LATCH (0x7c)
> -
> -#endif
> diff --git a/arch/arm/include/asm/hardware/iomd.h b/arch/arm/include/asm/hardware/iomd.h
> deleted file mode 100644
> index 53006ba5350f..000000000000
> --- a/arch/arm/include/asm/hardware/iomd.h
> +++ /dev/null
> @@ -1,182 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * arch/arm/include/asm/hardware/iomd.h
> - *
> - * Copyright (C) 1999 Russell King
> - *
> - * This file contains information out the IOMD ASIC used in the
> - * Acorn RiscPC and subsequently integrated into the CLPS7500 chips.
> - */
> -#ifndef __ASMARM_HARDWARE_IOMD_H
> -#define __ASMARM_HARDWARE_IOMD_H
> -
> -
> -#ifndef __ASSEMBLY__
> -
> -/*
> - * We use __raw_base variants here so that we give the compiler the
> - * chance to keep IOC_BASE in a register.
> - */
> -#define iomd_readb(off) __raw_readb(IOMD_BASE + (off))
> -#define iomd_readl(off) __raw_readl(IOMD_BASE + (off))
> -#define iomd_writeb(val,off) __raw_writeb(val, IOMD_BASE + (off))
> -#define iomd_writel(val,off) __raw_writel(val, IOMD_BASE + (off))
> -
> -#endif
> -
> -#define IOMD_CONTROL (0x000)
> -#define IOMD_KARTTX (0x004)
> -#define IOMD_KARTRX (0x004)
> -#define IOMD_KCTRL (0x008)
> -
> -#define IOMD_IRQSTATA (0x010)
> -#define IOMD_IRQREQA (0x014)
> -#define IOMD_IRQCLRA (0x014)
> -#define IOMD_IRQMASKA (0x018)
> -
> -#define IOMD_IRQSTATB (0x020)
> -#define IOMD_IRQREQB (0x024)
> -#define IOMD_IRQMASKB (0x028)
> -
> -#define IOMD_FIQSTAT (0x030)
> -#define IOMD_FIQREQ (0x034)
> -#define IOMD_FIQMASK (0x038)
> -
> -#define IOMD_T0CNTL (0x040)
> -#define IOMD_T0LTCHL (0x040)
> -#define IOMD_T0CNTH (0x044)
> -#define IOMD_T0LTCHH (0x044)
> -#define IOMD_T0GO (0x048)
> -#define IOMD_T0LATCH (0x04c)
> -
> -#define IOMD_T1CNTL (0x050)
> -#define IOMD_T1LTCHL (0x050)
> -#define IOMD_T1CNTH (0x054)
> -#define IOMD_T1LTCHH (0x054)
> -#define IOMD_T1GO (0x058)
> -#define IOMD_T1LATCH (0x05c)
> -
> -#define IOMD_ROMCR0 (0x080)
> -#define IOMD_ROMCR1 (0x084)
> -#ifdef CONFIG_ARCH_RPC
> -#define IOMD_DRAMCR (0x088)
> -#endif
> -#define IOMD_REFCR (0x08C)
> -
> -#define IOMD_FSIZE (0x090)
> -#define IOMD_ID0 (0x094)
> -#define IOMD_ID1 (0x098)
> -#define IOMD_VERSION (0x09C)
> -
> -#ifdef CONFIG_ARCH_RPC
> -#define IOMD_MOUSEX (0x0A0)
> -#define IOMD_MOUSEY (0x0A4)
> -#endif
> -
> -#ifdef CONFIG_ARCH_RPC
> -#define IOMD_DMATCR (0x0C0)
> -#endif
> -#define IOMD_IOTCR (0x0C4)
> -#define IOMD_ECTCR (0x0C8)
> -#ifdef CONFIG_ARCH_RPC
> -#define IOMD_DMAEXT (0x0CC)
> -#endif
> -
> -#ifdef CONFIG_ARCH_RPC
> -#define DMA_EXT_IO0 1
> -#define DMA_EXT_IO1 2
> -#define DMA_EXT_IO2 4
> -#define DMA_EXT_IO3 8
> -
> -#define IOMD_IO0CURA (0x100)
> -#define IOMD_IO0ENDA (0x104)
> -#define IOMD_IO0CURB (0x108)
> -#define IOMD_IO0ENDB (0x10C)
> -#define IOMD_IO0CR (0x110)
> -#define IOMD_IO0ST (0x114)
> -
> -#define IOMD_IO1CURA (0x120)
> -#define IOMD_IO1ENDA (0x124)
> -#define IOMD_IO1CURB (0x128)
> -#define IOMD_IO1ENDB (0x12C)
> -#define IOMD_IO1CR (0x130)
> -#define IOMD_IO1ST (0x134)
> -
> -#define IOMD_IO2CURA (0x140)
> -#define IOMD_IO2ENDA (0x144)
> -#define IOMD_IO2CURB (0x148)
> -#define IOMD_IO2ENDB (0x14C)
> -#define IOMD_IO2CR (0x150)
> -#define IOMD_IO2ST (0x154)
> -
> -#define IOMD_IO3CURA (0x160)
> -#define IOMD_IO3ENDA (0x164)
> -#define IOMD_IO3CURB (0x168)
> -#define IOMD_IO3ENDB (0x16C)
> -#define IOMD_IO3CR (0x170)
> -#define IOMD_IO3ST (0x174)
> -#endif
> -
> -#define IOMD_SD0CURA (0x180)
> -#define IOMD_SD0ENDA (0x184)
> -#define IOMD_SD0CURB (0x188)
> -#define IOMD_SD0ENDB (0x18C)
> -#define IOMD_SD0CR (0x190)
> -#define IOMD_SD0ST (0x194)
> -
> -#ifdef CONFIG_ARCH_RPC
> -#define IOMD_SD1CURA (0x1A0)
> -#define IOMD_SD1ENDA (0x1A4)
> -#define IOMD_SD1CURB (0x1A8)
> -#define IOMD_SD1ENDB (0x1AC)
> -#define IOMD_SD1CR (0x1B0)
> -#define IOMD_SD1ST (0x1B4)
> -#endif
> -
> -#define IOMD_CURSCUR (0x1C0)
> -#define IOMD_CURSINIT (0x1C4)
> -
> -#define IOMD_VIDCUR (0x1D0)
> -#define IOMD_VIDEND (0x1D4)
> -#define IOMD_VIDSTART (0x1D8)
> -#define IOMD_VIDINIT (0x1DC)
> -#define IOMD_VIDCR (0x1E0)
> -
> -#define IOMD_DMASTAT (0x1F0)
> -#define IOMD_DMAREQ (0x1F4)
> -#define IOMD_DMAMASK (0x1F8)
> -
> -#define DMA_END_S (1 << 31)
> -#define DMA_END_L (1 << 30)
> -
> -#define DMA_CR_C 0x80
> -#define DMA_CR_D 0x40
> -#define DMA_CR_E 0x20
> -
> -#define DMA_ST_OFL 4
> -#define DMA_ST_INT 2
> -#define DMA_ST_AB 1
> -
> -/*
> - * DMA (MEMC) compatibility
> - */
> -#define HALF_SAM vram_half_sam
> -#define VDMA_ALIGNMENT (HALF_SAM * 2)
> -#define VDMA_XFERSIZE (HALF_SAM)
> -#define VDMA_INIT IOMD_VIDINIT
> -#define VDMA_START IOMD_VIDSTART
> -#define VDMA_END IOMD_VIDEND
> -
> -#ifndef __ASSEMBLY__
> -extern unsigned int vram_half_sam;
> -#define video_set_dma(start,end,offset) \
> -do { \
> - outl (SCREEN_START + start, VDMA_START); \
> - outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END); \
> - if (offset >= end - VDMA_XFERSIZE) \
> - offset |= 0x40000000; \
> - outl (SCREEN_START + offset, VDMA_INIT); \
> -} while (0)
> -#endif
> -
> -#endif
> diff --git a/arch/arm/include/asm/hardware/memc.h b/arch/arm/include/asm/hardware/memc.h
> deleted file mode 100644
> index 1d4ebe0a9678..000000000000
> --- a/arch/arm/include/asm/hardware/memc.h
> +++ /dev/null
> @@ -1,23 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * arch/arm/include/asm/hardware/memc.h
> - *
> - * Copyright (C) Russell King.
> - */
> -#define VDMA_ALIGNMENT PAGE_SIZE
> -#define VDMA_XFERSIZE 16
> -#define VDMA_INIT 0
> -#define VDMA_START 1
> -#define VDMA_END 2
> -
> -#ifndef __ASSEMBLY__
> -extern void memc_write(unsigned int reg, unsigned long val);
> -
> -#define video_set_dma(start,end,offset) \
> -do { \
> - memc_write (VDMA_START, (start >> 2)); \
> - memc_write (VDMA_END, (end - VDMA_XFERSIZE) >> 2); \
> - memc_write (VDMA_INIT, (offset >> 2)); \
> -} while (0)
> -
> -#endif
> diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
> index e6bd9e79737c..c3661af2ca2a 100644
> --- a/arch/arm/include/asm/io.h
> +++ b/arch/arm/include/asm/io.h
> @@ -207,16 +207,13 @@ void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size);
> /*
> * Now, pick up the machine-defined IO definitions
> */
> -#ifdef CONFIG_NEED_MACH_IO_H
> -#include <mach/io.h>
> -#else
> #if IS_ENABLED(CONFIG_PCMCIA) || defined(CONFIG_PCI)
> #define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
> #else
> #define IO_SPACE_LIMIT ((resource_size_t)0)
> #endif
> +
> #define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
> -#endif
>
> /*
> * IO port access primitives
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index 7c2fa7dcec6d..e10363ebdd1f 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -20,9 +20,6 @@
> #include <linux/types.h>
> #include <linux/sizes.h>
>
> -#ifdef CONFIG_NEED_MACH_MEMORY_H
> -#include <mach/memory.h>
> -#endif
> #include <asm/kasan_def.h>
>
> /*
> diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
> index 42cae73fcc19..3cbbcdb63f7d 100644
> --- a/arch/arm/kernel/head-common.S
> +++ b/arch/arm/kernel/head-common.S
> @@ -221,19 +221,6 @@ str_p2: .asciz ").\n"
> ENDPROC(__error_p)
>
> __error:
> -#ifdef CONFIG_ARCH_RPC
> -/*
> - * Turn the screen red on a error - RiscPC only.
> - */
> - mov r0, #0x02000000
> - mov r3, #0x11
> - orr r3, r3, r3, lsl #8
> - orr r3, r3, r3, lsl #16
> - str r3, [r0], #4
> - str r3, [r0], #4
> - str r3, [r0], #4
> - str r3, [r0], #4
> -#endif
> 1: mov r0, r0
> b 1b
> ENDPROC(__error)
> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> index b12fe41e579b..2ffaea2c4c9b 100644
> --- a/arch/arm/kernel/head.S
> +++ b/arch/arm/kernel/head.S
> @@ -347,18 +347,6 @@ __create_page_tables:
> /* we don't need any serial debugging mappings */
> ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
> #endif
> -#ifdef CONFIG_ARCH_RPC
> - /*
> - * Map in screen at 0x02000000 & SCREEN2_BASE
> - * Similar reasons here - for debug. This is
> - * only for Acorn RiscPC architectures.
> - */
> - add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
> - orr r3, r7, #0x02000000
> - str r3, [r0]
> - add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
> - str r3, [r0]
> -#endif
> #endif
> #ifdef CONFIG_ARM_LPAE
> sub r4, r4, #0x1000 @ point to the PGD table
> diff --git a/arch/arm/lib/delay-loop.S b/arch/arm/lib/delay-loop.S
> index 33b08ca1c242..56f9eea56268 100644
> --- a/arch/arm/lib/delay-loop.S
> +++ b/arch/arm/lib/delay-loop.S
> @@ -9,10 +9,6 @@
> #include <asm/assembler.h>
> #include <asm/delay.h>
>
> -#ifdef CONFIG_ARCH_RPC
> - .arch armv4
> -#endif
> -
> .text
>
> .LC0: .word loops_per_jiffy
> diff --git a/arch/arm/mach-rpc/Kconfig b/arch/arm/mach-rpc/Kconfig
> deleted file mode 100644
> index 60b3823b690c..000000000000
> --- a/arch/arm/mach-rpc/Kconfig
> +++ /dev/null
> @@ -1,24 +0,0 @@
> -config ARCH_RPC
> - bool "RiscPC (DEPRECATED)"
> - depends on ARCH_MULTI_V4 && !(ARCH_MULTI_V4T || ARCH_MULTI_V5)
> - depends on !(ARCH_FOOTBRIDGE || ARCH_SA1100 || ARCH_MOXART || ARCH_GEMINI)
> - depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000
> - depends on CPU_LITTLE_ENDIAN
> - depends on ATAGS
> - depends on MMU
> - select ARCH_ACORN
> - select ARCH_MAY_HAVE_PC_FDC
> - select CPU_SA110
> - select FIQ
> - select HAVE_PATA_PLATFORM
> - select ISA_DMA_API
> - select LEGACY_TIMER_TICK
> - select NEED_MACH_IO_H
> - select NEED_MACH_MEMORY_H
> - select NO_IOPORT_MAP
> - help
> - On the Acorn Risc-PC, Linux can support the internal IDE disk and
> - CD-ROM interface, serial and parallel port, and the floppy drive.
> -
> - Support for these machines will go away in 2027,
> - unless there are any remaining users that speak up.
> diff --git a/arch/arm/mach-rpc/Makefile b/arch/arm/mach-rpc/Makefile
> deleted file mode 100644
> index 90a645a18444..000000000000
> --- a/arch/arm/mach-rpc/Makefile
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0-only
> -#
> -# Makefile for the linux kernel.
> -#
> -
> -# Object file lists.
> -
> -obj-y :=dma.o ecard.o ecard-loader.o fiq.o floppydma.o io-acorn.o irq.o \
> - riscpc.o time.o
> diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c
> deleted file mode 100644
> index 50e0f97afd75..000000000000
> --- a/arch/arm/mach-rpc/dma.c
> +++ /dev/null
> @@ -1,393 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * linux/arch/arm/mach-rpc/dma.c
> - *
> - * Copyright (C) 1998 Russell King
> - *
> - * DMA functions specific to RiscPC architecture
> - */
> -#include <linux/mman.h>
> -#include <linux/init.h>
> -#include <linux/interrupt.h>
> -#include <linux/dma-mapping.h>
> -#include <linux/io.h>
> -
> -#include <asm/page.h>
> -#include <asm/dma.h>
> -#include <asm/fiq.h>
> -#include <asm/irq.h>
> -#include <mach/hardware.h>
> -#include <linux/uaccess.h>
> -
> -#include <asm/mach/dma.h>
> -#include <asm/hardware/iomd.h>
> -
> -struct iomd_dma {
> - struct dma_struct dma;
> - void __iomem *base; /* Controller base address */
> - int irq; /* Controller IRQ */
> - unsigned int state;
> - dma_addr_t cur_addr;
> - unsigned int cur_len;
> - dma_addr_t dma_addr;
> - unsigned int dma_len;
> -};
> -
> -#if 0
> -typedef enum {
> - dma_size_8 = 1,
> - dma_size_16 = 2,
> - dma_size_32 = 4,
> - dma_size_128 = 16
> -} dma_size_t;
> -#endif
> -
> -#define TRANSFER_SIZE 2
> -
> -#define CURA (0)
> -#define ENDA (IOMD_IO0ENDA - IOMD_IO0CURA)
> -#define CURB (IOMD_IO0CURB - IOMD_IO0CURA)
> -#define ENDB (IOMD_IO0ENDB - IOMD_IO0CURA)
> -#define CR (IOMD_IO0CR - IOMD_IO0CURA)
> -#define ST (IOMD_IO0ST - IOMD_IO0CURA)
> -
> -static void iomd_get_next_sg(struct iomd_dma *idma)
> -{
> - unsigned long end, offset, flags = 0;
> -
> - if (idma->dma.sg) {
> - idma->cur_addr = idma->dma_addr;
> - offset = idma->cur_addr & ~PAGE_MASK;
> -
> - end = offset + idma->dma_len;
> -
> - if (end > PAGE_SIZE)
> - end = PAGE_SIZE;
> -
> - if (offset + TRANSFER_SIZE >= end)
> - flags |= DMA_END_L;
> -
> - idma->cur_len = end - TRANSFER_SIZE;
> -
> - idma->dma_len -= end - offset;
> - idma->dma_addr += end - offset;
> -
> - if (idma->dma_len == 0) {
> - if (idma->dma.sgcount > 1) {
> - idma->dma.sg = sg_next(idma->dma.sg);
> - idma->dma_addr = idma->dma.sg->dma_address;
> - idma->dma_len = idma->dma.sg->length;
> - idma->dma.sgcount--;
> - } else {
> - idma->dma.sg = NULL;
> - flags |= DMA_END_S;
> - }
> - }
> - } else {
> - flags = DMA_END_S | DMA_END_L;
> - idma->cur_addr = 0;
> - idma->cur_len = 0;
> - }
> -
> - idma->cur_len |= flags;
> -}
> -
> -static irqreturn_t iomd_dma_handle(int irq, void *dev_id)
> -{
> - struct iomd_dma *idma = dev_id;
> - void __iomem *base = idma->base;
> - unsigned int state = idma->state;
> - unsigned int status, cur, end;
> -
> - do {
> - status = readb(base + ST);
> - if (!(status & DMA_ST_INT))
> - goto out;
> -
> - if ((state ^ status) & DMA_ST_AB)
> - iomd_get_next_sg(idma);
> -
> - // This efficiently implements state = OFL != AB ? AB : 0
> - state = ((status >> 2) ^ status) & DMA_ST_AB;
> - if (state) {
> - cur = CURA;
> - end = ENDA;
> - } else {
> - cur = CURB;
> - end = ENDB;
> - }
> - writel(idma->cur_addr, base + cur);
> - writel(idma->cur_len, base + end);
> -
> - if (status & DMA_ST_OFL &&
> - idma->cur_len == (DMA_END_S|DMA_END_L))
> - break;
> - } while (1);
> -
> - state = ~DMA_ST_AB;
> - disable_irq_nosync(irq);
> -out:
> - idma->state = state;
> - return IRQ_HANDLED;
> -}
> -
> -static int iomd_request_dma(unsigned int chan, dma_t *dma)
> -{
> - struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
> -
> - return request_irq(idma->irq, iomd_dma_handle,
> - 0, idma->dma.device_id, idma);
> -}
> -
> -static void iomd_free_dma(unsigned int chan, dma_t *dma)
> -{
> - struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
> -
> - free_irq(idma->irq, idma);
> -}
> -
> -static struct device isa_dma_dev = {
> - .init_name = "fallback device",
> - .coherent_dma_mask = ~(dma_addr_t)0,
> - .dma_mask = &isa_dma_dev.coherent_dma_mask,
> -};
> -
> -static void iomd_enable_dma(unsigned int chan, dma_t *dma)
> -{
> - struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
> - void __iomem *base = idma->base;
> - unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E;
> -
> - if (idma->dma.invalid) {
> - idma->dma.invalid = 0;
> -
> - /*
> - * Cope with ISA-style drivers which expect cache
> - * coherence.
> - */
> - if (!idma->dma.sg) {
> - idma->dma.sg = &idma->dma.buf;
> - idma->dma.sgcount = 1;
> - idma->dma.buf.length = idma->dma.count;
> - idma->dma.buf.dma_address = dma_map_single(&isa_dma_dev,
> - idma->dma.addr, idma->dma.count,
> - idma->dma.dma_mode == DMA_MODE_READ ?
> - DMA_FROM_DEVICE : DMA_TO_DEVICE);
> - }
> -
> - idma->dma_addr = idma->dma.sg->dma_address;
> - idma->dma_len = idma->dma.sg->length;
> -
> - writeb(DMA_CR_C, base + CR);
> - idma->state = DMA_ST_AB;
> - }
> -
> - if (idma->dma.dma_mode == DMA_MODE_READ)
> - ctrl |= DMA_CR_D;
> -
> - writeb(ctrl, base + CR);
> - enable_irq(idma->irq);
> -}
> -
> -static void iomd_disable_dma(unsigned int chan, dma_t *dma)
> -{
> - struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
> - void __iomem *base = idma->base;
> - unsigned long flags;
> -
> - local_irq_save(flags);
> - if (idma->state != ~DMA_ST_AB)
> - disable_irq(idma->irq);
> - writeb(0, base + CR);
> - local_irq_restore(flags);
> -}
> -
> -static int iomd_set_dma_speed(unsigned int chan, dma_t *dma, int cycle)
> -{
> - int tcr, speed;
> -
> - if (cycle < 188)
> - speed = 3;
> - else if (cycle <= 250)
> - speed = 2;
> - else if (cycle < 438)
> - speed = 1;
> - else
> - speed = 0;
> -
> - tcr = iomd_readb(IOMD_DMATCR);
> - speed &= 3;
> -
> - switch (chan) {
> - case DMA_0:
> - tcr = (tcr & ~0x03) | speed;
> - break;
> -
> - case DMA_1:
> - tcr = (tcr & ~0x0c) | (speed << 2);
> - break;
> -
> - case DMA_2:
> - tcr = (tcr & ~0x30) | (speed << 4);
> - break;
> -
> - case DMA_3:
> - tcr = (tcr & ~0xc0) | (speed << 6);
> - break;
> -
> - default:
> - break;
> - }
> -
> - iomd_writeb(tcr, IOMD_DMATCR);
> -
> - return speed;
> -}
> -
> -static struct dma_ops iomd_dma_ops = {
> - .type = "IOMD",
> - .request = iomd_request_dma,
> - .free = iomd_free_dma,
> - .enable = iomd_enable_dma,
> - .disable = iomd_disable_dma,
> - .setspeed = iomd_set_dma_speed,
> -};
> -
> -static struct fiq_handler fh = {
> - .name = "floppydma"
> -};
> -
> -struct floppy_dma {
> - struct dma_struct dma;
> - unsigned int fiq;
> -};
> -
> -static void floppy_enable_dma(unsigned int chan, dma_t *dma)
> -{
> - struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma);
> - void *fiqhandler_start;
> - unsigned int fiqhandler_length;
> - struct pt_regs regs;
> -
> - if (fdma->dma.sg)
> - BUG();
> -
> - if (fdma->dma.dma_mode == DMA_MODE_READ) {
> - extern unsigned char floppy_fiqin_start, floppy_fiqin_end;
> - fiqhandler_start = &floppy_fiqin_start;
> - fiqhandler_length = &floppy_fiqin_end - &floppy_fiqin_start;
> - } else {
> - extern unsigned char floppy_fiqout_start, floppy_fiqout_end;
> - fiqhandler_start = &floppy_fiqout_start;
> - fiqhandler_length = &floppy_fiqout_end - &floppy_fiqout_start;
> - }
> -
> - regs.ARM_r9 = fdma->dma.count;
> - regs.ARM_r10 = (unsigned long)fdma->dma.addr;
> - regs.ARM_fp = (unsigned long)FLOPPYDMA_BASE;
> -
> - if (claim_fiq(&fh)) {
> - printk("floppydma: couldn't claim FIQ.\n");
> - return;
> - }
> -
> - set_fiq_handler(fiqhandler_start, fiqhandler_length);
> - set_fiq_regs(®s);
> - enable_fiq(fdma->fiq);
> -}
> -
> -static void floppy_disable_dma(unsigned int chan, dma_t *dma)
> -{
> - struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma);
> - disable_fiq(fdma->fiq);
> - release_fiq(&fh);
> -}
> -
> -static int floppy_get_residue(unsigned int chan, dma_t *dma)
> -{
> - struct pt_regs regs;
> - get_fiq_regs(®s);
> - return regs.ARM_r9;
> -}
> -
> -static struct dma_ops floppy_dma_ops = {
> - .type = "FIQDMA",
> - .enable = floppy_enable_dma,
> - .disable = floppy_disable_dma,
> - .residue = floppy_get_residue,
> -};
> -
> -/*
> - * This is virtual DMA - we don't need anything here.
> - */
> -static void sound_enable_disable_dma(unsigned int chan, dma_t *dma)
> -{
> -}
> -
> -static struct dma_ops sound_dma_ops = {
> - .type = "VIRTUAL",
> - .enable = sound_enable_disable_dma,
> - .disable = sound_enable_disable_dma,
> -};
> -
> -static struct iomd_dma iomd_dma[6];
> -
> -static struct floppy_dma floppy_dma = {
> - .dma = {
> - .d_ops = &floppy_dma_ops,
> - },
> - .fiq = FIQ_FLOPPYDATA,
> -};
> -
> -static dma_t sound_dma = {
> - .d_ops = &sound_dma_ops,
> -};
> -
> -static int __init rpc_dma_init(void)
> -{
> - unsigned int i;
> - int ret;
> -
> - iomd_writeb(0, IOMD_IO0CR);
> - iomd_writeb(0, IOMD_IO1CR);
> - iomd_writeb(0, IOMD_IO2CR);
> - iomd_writeb(0, IOMD_IO3CR);
> -
> - iomd_writeb(0xa0, IOMD_DMATCR);
> -
> - /*
> - * Setup DMA channels 2,3 to be for podules
> - * and channels 0,1 for internal devices
> - */
> - iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT);
> -
> - iomd_dma[DMA_0].base = IOMD_BASE + IOMD_IO0CURA;
> - iomd_dma[DMA_0].irq = IRQ_DMA0;
> - iomd_dma[DMA_1].base = IOMD_BASE + IOMD_IO1CURA;
> - iomd_dma[DMA_1].irq = IRQ_DMA1;
> - iomd_dma[DMA_2].base = IOMD_BASE + IOMD_IO2CURA;
> - iomd_dma[DMA_2].irq = IRQ_DMA2;
> - iomd_dma[DMA_3].base = IOMD_BASE + IOMD_IO3CURA;
> - iomd_dma[DMA_3].irq = IRQ_DMA3;
> - iomd_dma[DMA_S0].base = IOMD_BASE + IOMD_SD0CURA;
> - iomd_dma[DMA_S0].irq = IRQ_DMAS0;
> - iomd_dma[DMA_S1].base = IOMD_BASE + IOMD_SD1CURA;
> - iomd_dma[DMA_S1].irq = IRQ_DMAS1;
> -
> - for (i = DMA_0; i <= DMA_S1; i++) {
> - iomd_dma[i].dma.d_ops = &iomd_dma_ops;
> -
> - ret = isa_dma_add(i, &iomd_dma[i].dma);
> - if (ret)
> - printk("IOMDDMA%u: unable to register: %d\n", i, ret);
> - }
> -
> - ret = isa_dma_add(DMA_VIRTUAL_FLOPPY, &floppy_dma.dma);
> - if (ret)
> - printk("IOMDFLOPPY: unable to register: %d\n", ret);
> - ret = isa_dma_add(DMA_VIRTUAL_SOUND, &sound_dma);
> - if (ret)
> - printk("IOMDSOUND: unable to register: %d\n", ret);
> - return 0;
> -}
> -core_initcall(rpc_dma_init);
> diff --git a/arch/arm/mach-rpc/ecard-loader.S b/arch/arm/mach-rpc/ecard-loader.S
> deleted file mode 100644
> index eb8ac0412da6..000000000000
> --- a/arch/arm/mach-rpc/ecard-loader.S
> +++ /dev/null
> @@ -1,40 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * linux/arch/arm/lib/ecard.S
> - *
> - * Copyright (C) 1995, 1996 Russell King
> - *
> - * 27/03/03 Ian Molton Clean up CONFIG_CPU
> - */
> -#include <linux/linkage.h>
> -#include <asm/assembler.h>
> -
> -#define CPSR2SPSR(rt) \
> - mrs rt, cpsr; \
> - msr spsr_cxsf, rt
> -
> -@ Purpose: call an expansion card loader to read bytes.
> -@ Proto : char read_loader(int offset, char *card_base, char *loader);
> -@ Returns: byte read
> -
> -ENTRY(ecard_loader_read)
> - stmfd sp!, {r4 - r12, lr}
> - mov r11, r1
> - mov r1, r0
> - CPSR2SPSR(r0)
> - mov lr, pc
> - mov pc, r2
> - ldmfd sp!, {r4 - r12, pc}
> -
> -@ Purpose: call an expansion card loader to reset the card
> -@ Proto : void read_loader(int card_base, char *loader);
> -@ Returns: byte read
> -
> -ENTRY(ecard_loader_reset)
> - stmfd sp!, {r4 - r12, lr}
> - mov r11, r0
> - CPSR2SPSR(r0)
> - mov lr, pc
> - add pc, r1, #8
> - ldmfd sp!, {r4 - r12, pc}
> -
> diff --git a/arch/arm/mach-rpc/ecard.c b/arch/arm/mach-rpc/ecard.c
> deleted file mode 100644
> index 972465840548..000000000000
> --- a/arch/arm/mach-rpc/ecard.c
> +++ /dev/null
> @@ -1,1146 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * linux/arch/arm/kernel/ecard.c
> - *
> - * Copyright 1995-2001 Russell King
> - *
> - * Find all installed expansion cards, and handle interrupts from them.
> - *
> - * Created from information from Acorns RiscOS3 PRMs
> - *
> - * 08-Dec-1996 RMK Added code for the 9'th expansion card - the ether
> - * podule slot.
> - * 06-May-1997 RMK Added blacklist for cards whose loader doesn't work.
> - * 12-Sep-1997 RMK Created new handling of interrupt enables/disables
> - * - cards can now register their own routine to control
> - * interrupts (recommended).
> - * 29-Sep-1997 RMK Expansion card interrupt hardware not being re-enabled
> - * on reset from Linux. (Caused cards not to respond
> - * under RiscOS without hard reset).
> - * 15-Feb-1998 RMK Added DMA support
> - * 12-Sep-1998 RMK Added EASI support
> - * 10-Jan-1999 RMK Run loaders in a simulated RISC OS environment.
> - * 17-Apr-1999 RMK Support for EASI Type C cycles.
> - */
> -#define ECARD_C
> -
> -#include <linux/module.h>
> -#include <linux/kernel.h>
> -#include <linux/types.h>
> -#include <linux/sched.h>
> -#include <linux/sched/mm.h>
> -#include <linux/interrupt.h>
> -#include <linux/completion.h>
> -#include <linux/reboot.h>
> -#include <linux/mm.h>
> -#include <linux/slab.h>
> -#include <linux/proc_fs.h>
> -#include <linux/seq_file.h>
> -#include <linux/device.h>
> -#include <linux/init.h>
> -#include <linux/mutex.h>
> -#include <linux/kthread.h>
> -#include <linux/irq.h>
> -#include <linux/io.h>
> -
> -#include <asm/dma.h>
> -#include <asm/ecard.h>
> -#include <mach/hardware.h>
> -#include <asm/irq.h>
> -#include <asm/mmu_context.h>
> -#include <asm/mach/irq.h>
> -#include <asm/tlbflush.h>
> -
> -#include "ecard.h"
> -
> -struct ecard_request {
> - void (*fn)(struct ecard_request *);
> - ecard_t *ec;
> - unsigned int address;
> - unsigned int length;
> - unsigned int use_loader;
> - void *buffer;
> - struct completion *complete;
> -};
> -
> -struct expcard_quirklist {
> - unsigned short manufacturer;
> - unsigned short product;
> - const char *type;
> - void (*init)(ecard_t *ec);
> -};
> -
> -static ecard_t *cards;
> -static ecard_t *slot_to_expcard[MAX_ECARDS];
> -static unsigned int ectcr;
> -
> -static void atomwide_3p_quirk(ecard_t *ec);
> -
> -/* List of descriptions of cards which don't have an extended
> - * identification, or chunk directories containing a description.
> - */
> -static struct expcard_quirklist quirklist[] __initdata = {
> - { MANU_ACORN, PROD_ACORN_ETHER1, "Acorn Ether1" },
> - { MANU_ATOMWIDE, PROD_ATOMWIDE_3PSERIAL, NULL, atomwide_3p_quirk },
> -};
> -
> -asmlinkage extern int
> -ecard_loader_reset(unsigned long base, loader_t loader);
> -asmlinkage extern int
> -ecard_loader_read(int off, unsigned long base, loader_t loader);
> -
> -static inline unsigned short ecard_getu16(unsigned char *v)
> -{
> - return v[0] | v[1] << 8;
> -}
> -
> -static inline signed long ecard_gets24(unsigned char *v)
> -{
> - return v[0] | v[1] << 8 | v[2] << 16 | ((v[2] & 0x80) ? 0xff000000 : 0);
> -}
> -
> -static inline ecard_t *slot_to_ecard(unsigned int slot)
> -{
> - return slot < MAX_ECARDS ? slot_to_expcard[slot] : NULL;
> -}
> -
> -/* ===================== Expansion card daemon ======================== */
> -/*
> - * Since the loader programs on the expansion cards need to be run
> - * in a specific environment, create a separate task with this
> - * environment up, and pass requests to this task as and when we
> - * need to.
> - *
> - * This should allow 99% of loaders to be called from Linux.
> - *
> - * From a security standpoint, we trust the card vendors. This
> - * may be a misplaced trust.
> - */
> -static void ecard_task_reset(struct ecard_request *req)
> -{
> - struct expansion_card *ec = req->ec;
> - struct resource *res;
> -
> - res = ec->slot_no == 8
> - ? &ec->resource[ECARD_RES_MEMC]
> - : ec->easi
> - ? &ec->resource[ECARD_RES_EASI]
> - : &ec->resource[ECARD_RES_IOCSYNC];
> -
> - ecard_loader_reset(res->start, ec->loader);
> -}
> -
> -static void ecard_task_readbytes(struct ecard_request *req)
> -{
> - struct expansion_card *ec = req->ec;
> - unsigned char *buf = req->buffer;
> - unsigned int len = req->length;
> - unsigned int off = req->address;
> -
> - if (ec->slot_no == 8) {
> - void __iomem *base = (void __iomem *)
> - ec->resource[ECARD_RES_MEMC].start;
> -
> - /*
> - * The card maintains an index which increments the address
> - * into a 4096-byte page on each access. We need to keep
> - * track of the counter.
> - */
> - static unsigned int index;
> - unsigned int page;
> -
> - page = (off >> 12) * 4;
> - if (page > 256 * 4)
> - return;
> -
> - off &= 4095;
> -
> - /*
> - * If we are reading offset 0, or our current index is
> - * greater than the offset, reset the hardware index counter.
> - */
> - if (off == 0 || index > off) {
> - writeb(0, base);
> - index = 0;
> - }
> -
> - /*
> - * Increment the hardware index counter until we get to the
> - * required offset. The read bytes are discarded.
> - */
> - while (index < off) {
> - readb(base + page);
> - index += 1;
> - }
> -
> - while (len--) {
> - *buf++ = readb(base + page);
> - index += 1;
> - }
> - } else {
> - unsigned long base = (ec->easi
> - ? &ec->resource[ECARD_RES_EASI]
> - : &ec->resource[ECARD_RES_IOCSYNC])->start;
> - void __iomem *pbase = (void __iomem *)base;
> -
> - if (!req->use_loader || !ec->loader) {
> - off *= 4;
> - while (len--) {
> - *buf++ = readb(pbase + off);
> - off += 4;
> - }
> - } else {
> - while(len--) {
> - /*
> - * The following is required by some
> - * expansion card loader programs.
> - */
> - *(unsigned long *)0x108 = 0;
> - *buf++ = ecard_loader_read(off++, base,
> - ec->loader);
> - }
> - }
> - }
> -
> -}
> -
> -static DECLARE_WAIT_QUEUE_HEAD(ecard_wait);
> -static struct ecard_request *ecard_req;
> -static DEFINE_MUTEX(ecard_mutex);
> -
> -/*
> - * Set up the expansion card daemon's page tables.
> - */
> -static void ecard_init_pgtables(struct mm_struct *mm)
> -{
> - struct vm_area_struct vma = TLB_FLUSH_VMA(mm, VM_EXEC);
> -
> - /* We want to set up the page tables for the following mapping:
> - * Virtual Physical
> - * 0x03000000 0x03000000
> - * 0x03010000 unmapped
> - * 0x03210000 0x03210000
> - * 0x03400000 unmapped
> - * 0x08000000 0x08000000
> - * 0x10000000 unmapped
> - *
> - * FIXME: we don't follow this 100% yet.
> - */
> - pgd_t *src_pgd, *dst_pgd;
> -
> - src_pgd = pgd_offset(mm, (unsigned long)IO_BASE);
> - dst_pgd = pgd_offset(mm, IO_START);
> -
> - memcpy(dst_pgd, src_pgd, sizeof(pgd_t) * (IO_SIZE / PGDIR_SIZE));
> -
> - src_pgd = pgd_offset(mm, (unsigned long)EASI_BASE);
> - dst_pgd = pgd_offset(mm, EASI_START);
> -
> - memcpy(dst_pgd, src_pgd, sizeof(pgd_t) * (EASI_SIZE / PGDIR_SIZE));
> -
> - flush_tlb_range(&vma, IO_START, IO_START + IO_SIZE);
> - flush_tlb_range(&vma, EASI_START, EASI_START + EASI_SIZE);
> -}
> -
> -static int ecard_init_mm(void)
> -{
> - struct mm_struct * mm = mm_alloc();
> - struct mm_struct *active_mm = current->active_mm;
> -
> - if (!mm)
> - return -ENOMEM;
> -
> - current->mm = mm;
> - current->active_mm = mm;
> - activate_mm(active_mm, mm);
> - mmdrop_lazy_tlb(active_mm);
> - ecard_init_pgtables(mm);
> - return 0;
> -}
> -
> -static int
> -ecard_task(void * unused)
> -{
> - /*
> - * Allocate a mm. We're not a lazy-TLB kernel task since we need
> - * to set page table entries where the user space would be. Note
> - * that this also creates the page tables. Failure is not an
> - * option here.
> - */
> - if (ecard_init_mm())
> - panic("kecardd: unable to alloc mm\n");
> -
> - while (1) {
> - struct ecard_request *req;
> -
> - wait_event_interruptible(ecard_wait, ecard_req != NULL);
> -
> - req = xchg(&ecard_req, NULL);
> - if (req != NULL) {
> - req->fn(req);
> - complete(req->complete);
> - }
> - }
> -}
> -
> -/*
> - * Wake the expansion card daemon to action our request.
> - *
> - * FIXME: The test here is not sufficient to detect if the
> - * kcardd is running.
> - */
> -static void ecard_call(struct ecard_request *req)
> -{
> - DECLARE_COMPLETION_ONSTACK(completion);
> -
> - req->complete = &completion;
> -
> - mutex_lock(&ecard_mutex);
> - ecard_req = req;
> - wake_up(&ecard_wait);
> -
> - /*
> - * Now wait for kecardd to run.
> - */
> - wait_for_completion(&completion);
> - mutex_unlock(&ecard_mutex);
> -}
> -
> -/* ======================= Mid-level card control ===================== */
> -
> -static void
> -ecard_readbytes(void *addr, ecard_t *ec, int off, int len, int useld)
> -{
> - struct ecard_request req;
> -
> - req.fn = ecard_task_readbytes;
> - req.ec = ec;
> - req.address = off;
> - req.length = len;
> - req.use_loader = useld;
> - req.buffer = addr;
> -
> - ecard_call(&req);
> -}
> -
> -int ecard_readchunk(struct in_chunk_dir *cd, ecard_t *ec, int id, int num)
> -{
> - struct ex_chunk_dir excd;
> - int index = 16;
> - int useld = 0;
> -
> - if (!ec->cid.cd)
> - return 0;
> -
> - while(1) {
> - ecard_readbytes(&excd, ec, index, 8, useld);
> - index += 8;
> - if (c_id(&excd) == 0) {
> - if (!useld && ec->loader) {
> - useld = 1;
> - index = 0;
> - continue;
> - }
> - return 0;
> - }
> - if (c_id(&excd) == 0xf0) { /* link */
> - index = c_start(&excd);
> - continue;
> - }
> - if (c_id(&excd) == 0x80) { /* loader */
> - if (!ec->loader) {
> - ec->loader = kmalloc(c_len(&excd),
> - GFP_KERNEL);
> - if (ec->loader)
> - ecard_readbytes(ec->loader, ec,
> - (int)c_start(&excd),
> - c_len(&excd), useld);
> - else
> - return 0;
> - }
> - continue;
> - }
> - if (c_id(&excd) == id && num-- == 0)
> - break;
> - }
> -
> - if (c_id(&excd) & 0x80) {
> - switch (c_id(&excd) & 0x70) {
> - case 0x70:
> - ecard_readbytes((unsigned char *)excd.d.string, ec,
> - (int)c_start(&excd), c_len(&excd),
> - useld);
> - break;
> - case 0x00:
> - break;
> - }
> - }
> - cd->start_offset = c_start(&excd);
> - memcpy(cd->d.string, excd.d.string, 256);
> - return 1;
> -}
> -
> -/* ======================= Interrupt control ============================ */
> -
> -static void ecard_def_irq_enable(ecard_t *ec, int irqnr)
> -{
> -}
> -
> -static void ecard_def_irq_disable(ecard_t *ec, int irqnr)
> -{
> -}
> -
> -static int ecard_def_irq_pending(ecard_t *ec)
> -{
> - return !ec->irqmask || readb(ec->irqaddr) & ec->irqmask;
> -}
> -
> -static void ecard_def_fiq_enable(ecard_t *ec, int fiqnr)
> -{
> - panic("ecard_def_fiq_enable called - impossible");
> -}
> -
> -static void ecard_def_fiq_disable(ecard_t *ec, int fiqnr)
> -{
> - panic("ecard_def_fiq_disable called - impossible");
> -}
> -
> -static int ecard_def_fiq_pending(ecard_t *ec)
> -{
> - return !ec->fiqmask || readb(ec->fiqaddr) & ec->fiqmask;
> -}
> -
> -static expansioncard_ops_t ecard_default_ops = {
> - ecard_def_irq_enable,
> - ecard_def_irq_disable,
> - ecard_def_irq_pending,
> - ecard_def_fiq_enable,
> - ecard_def_fiq_disable,
> - ecard_def_fiq_pending
> -};
> -
> -/*
> - * Enable and disable interrupts from expansion cards.
> - * (interrupts are disabled for these functions).
> - *
> - * They are not meant to be called directly, but via enable/disable_irq.
> - */
> -static void ecard_irq_unmask(struct irq_data *d)
> -{
> - ecard_t *ec = irq_data_get_irq_chip_data(d);
> -
> - if (ec) {
> - if (!ec->ops)
> - ec->ops = &ecard_default_ops;
> -
> - if (ec->claimed && ec->ops->irqenable)
> - ec->ops->irqenable(ec, d->irq);
> - else
> - printk(KERN_ERR "ecard: rejecting request to "
> - "enable IRQs for %d\n", d->irq);
> - }
> -}
> -
> -static void ecard_irq_mask(struct irq_data *d)
> -{
> - ecard_t *ec = irq_data_get_irq_chip_data(d);
> -
> - if (ec) {
> - if (!ec->ops)
> - ec->ops = &ecard_default_ops;
> -
> - if (ec->ops && ec->ops->irqdisable)
> - ec->ops->irqdisable(ec, d->irq);
> - }
> -}
> -
> -static struct irq_chip ecard_chip = {
> - .name = "ECARD",
> - .irq_ack = ecard_irq_mask,
> - .irq_mask = ecard_irq_mask,
> - .irq_unmask = ecard_irq_unmask,
> -};
> -
> -void ecard_enablefiq(unsigned int fiqnr)
> -{
> - ecard_t *ec = slot_to_ecard(fiqnr);
> -
> - if (ec) {
> - if (!ec->ops)
> - ec->ops = &ecard_default_ops;
> -
> - if (ec->claimed && ec->ops->fiqenable)
> - ec->ops->fiqenable(ec, fiqnr);
> - else
> - printk(KERN_ERR "ecard: rejecting request to "
> - "enable FIQs for %d\n", fiqnr);
> - }
> -}
> -
> -void ecard_disablefiq(unsigned int fiqnr)
> -{
> - ecard_t *ec = slot_to_ecard(fiqnr);
> -
> - if (ec) {
> - if (!ec->ops)
> - ec->ops = &ecard_default_ops;
> -
> - if (ec->ops->fiqdisable)
> - ec->ops->fiqdisable(ec, fiqnr);
> - }
> -}
> -
> -static void ecard_dump_irq_state(void)
> -{
> - ecard_t *ec;
> -
> - printk("Expansion card IRQ state:\n");
> -
> - for (ec = cards; ec; ec = ec->next) {
> - const char *claimed;
> -
> - if (ec->slot_no == 8)
> - continue;
> -
> - claimed = ec->claimed ? "" : "not ";
> -
> - if (ec->ops && ec->ops->irqpending &&
> - ec->ops != &ecard_default_ops)
> - printk(" %d: %sclaimed irq %spending\n",
> - ec->slot_no, claimed,
> - ec->ops->irqpending(ec) ? "" : "not ");
> - else
> - printk(" %d: %sclaimed irqaddr %p, mask = %02X, status = %02X\n",
> - ec->slot_no, claimed,
> - ec->irqaddr, ec->irqmask, readb(ec->irqaddr));
> - }
> -}
> -
> -static void ecard_check_lockup(struct irq_desc *desc)
> -{
> - static unsigned long last;
> - static int lockup;
> -
> - /*
> - * If the timer interrupt has not run since the last million
> - * unrecognised expansion card interrupts, then there is
> - * something seriously wrong. Disable the expansion card
> - * interrupts so at least we can continue.
> - *
> - * Maybe we ought to start a timer to re-enable them some time
> - * later?
> - */
> - if (last == jiffies) {
> - lockup += 1;
> - if (lockup > 1000000) {
> - printk(KERN_ERR "\nInterrupt lockup detected - "
> - "disabling all expansion card interrupts\n");
> -
> - desc->irq_data.chip->irq_mask(&desc->irq_data);
> - ecard_dump_irq_state();
> - }
> - } else
> - lockup = 0;
> -
> - /*
> - * If we did not recognise the source of this interrupt,
> - * warn the user, but don't flood the user with these messages.
> - */
> - if (!last || time_after(jiffies, last + 5*HZ)) {
> - last = jiffies;
> - printk(KERN_WARNING "Unrecognised interrupt from backplane\n");
> - ecard_dump_irq_state();
> - }
> -}
> -
> -static void ecard_irq_handler(struct irq_desc *desc)
> -{
> - ecard_t *ec;
> - int called = 0;
> -
> - desc->irq_data.chip->irq_mask(&desc->irq_data);
> - for (ec = cards; ec; ec = ec->next) {
> - int pending;
> -
> - if (!ec->claimed || !ec->irq || ec->slot_no == 8)
> - continue;
> -
> - if (ec->ops && ec->ops->irqpending)
> - pending = ec->ops->irqpending(ec);
> - else
> - pending = ecard_default_ops.irqpending(ec);
> -
> - if (pending) {
> - generic_handle_irq(ec->irq);
> - called ++;
> - }
> - }
> - desc->irq_data.chip->irq_unmask(&desc->irq_data);
> -
> - if (called == 0)
> - ecard_check_lockup(desc);
> -}
> -
> -static void __iomem *__ecard_address(ecard_t *ec, card_type_t type, card_speed_t speed)
> -{
> - void __iomem *address = NULL;
> - int slot = ec->slot_no;
> -
> - if (ec->slot_no == 8)
> - return ECARD_MEMC8_BASE;
> -
> - ectcr &= ~(1 << slot);
> -
> - switch (type) {
> - case ECARD_MEMC:
> - if (slot < 4)
> - address = ECARD_MEMC_BASE + (slot << 14);
> - break;
> -
> - case ECARD_IOC:
> - if (slot < 4)
> - address = ECARD_IOC_BASE + (slot << 14);
> - else
> - address = ECARD_IOC4_BASE + ((slot - 4) << 14);
> - if (address)
> - address += speed << 19;
> - break;
> -
> - case ECARD_EASI:
> - address = ECARD_EASI_BASE + (slot << 24);
> - if (speed == ECARD_FAST)
> - ectcr |= 1 << slot;
> - break;
> -
> - default:
> - break;
> - }
> -
> -#ifdef IOMD_ECTCR
> - iomd_writeb(ectcr, IOMD_ECTCR);
> -#endif
> - return address;
> -}
> -
> -static int ecard_prints(struct seq_file *m, ecard_t *ec)
> -{
> - seq_printf(m, " %d: %s ", ec->slot_no, ec->easi ? "EASI" : " ");
> -
> - if (ec->cid.id == 0) {
> - struct in_chunk_dir incd;
> -
> - seq_printf(m, "[%04X:%04X] ",
> - ec->cid.manufacturer, ec->cid.product);
> -
> - if (!ec->card_desc && ec->cid.cd &&
> - ecard_readchunk(&incd, ec, 0xf5, 0)) {
> - ec->card_desc = kmalloc(strlen(incd.d.string)+1, GFP_KERNEL);
> -
> - if (ec->card_desc)
> - strcpy((char *)ec->card_desc, incd.d.string);
> - }
> -
> - seq_printf(m, "%s\n", ec->card_desc ? ec->card_desc : "*unknown*");
> - } else
> - seq_printf(m, "Simple card %d\n", ec->cid.id);
> -
> - return 0;
> -}
> -
> -static int ecard_devices_proc_show(struct seq_file *m, void *v)
> -{
> - ecard_t *ec = cards;
> -
> - while (ec) {
> - ecard_prints(m, ec);
> - ec = ec->next;
> - }
> - return 0;
> -}
> -
> -static struct proc_dir_entry *proc_bus_ecard_dir = NULL;
> -
> -static void ecard_proc_init(void)
> -{
> - proc_bus_ecard_dir = proc_mkdir("bus/ecard", NULL);
> - proc_create_single("devices", 0, proc_bus_ecard_dir,
> - ecard_devices_proc_show);
> -}
> -
> -#define ec_set_resource(ec,nr,st,sz) \
> - do { \
> - (ec)->resource[nr].name = dev_name(&ec->dev); \
> - (ec)->resource[nr].start = st; \
> - (ec)->resource[nr].end = (st) + (sz) - 1; \
> - (ec)->resource[nr].flags = IORESOURCE_MEM; \
> - } while (0)
> -
> -static void __init ecard_free_card(struct expansion_card *ec)
> -{
> - int i;
> -
> - for (i = 0; i < ECARD_NUM_RESOURCES; i++)
> - if (ec->resource[i].flags)
> - release_resource(&ec->resource[i]);
> -
> - kfree(ec);
> -}
> -
> -static struct expansion_card *__init ecard_alloc_card(int type, int slot)
> -{
> - struct expansion_card *ec;
> - unsigned long base;
> - int i;
> -
> - ec = kzalloc_obj(ecard_t);
> - if (!ec) {
> - ec = ERR_PTR(-ENOMEM);
> - goto nomem;
> - }
> -
> - ec->slot_no = slot;
> - ec->easi = type == ECARD_EASI;
> - ec->irq = 0;
> - ec->fiq = 0;
> - ec->dma = NO_DMA;
> - ec->ops = &ecard_default_ops;
> -
> - dev_set_name(&ec->dev, "ecard%d", slot);
> - ec->dev.parent = NULL;
> - ec->dev.bus = &ecard_bus_type;
> - ec->dev.dma_mask = &ec->dma_mask;
> - ec->dma_mask = (u64)0xffffffff;
> - ec->dev.coherent_dma_mask = ec->dma_mask;
> -
> - if (slot < 4) {
> - ec_set_resource(ec, ECARD_RES_MEMC,
> - PODSLOT_MEMC_BASE + (slot << 14),
> - PODSLOT_MEMC_SIZE);
> - base = PODSLOT_IOC0_BASE + (slot << 14);
> - } else
> - base = PODSLOT_IOC4_BASE + ((slot - 4) << 14);
> -
> -#ifdef CONFIG_ARCH_RPC
> - if (slot < 8) {
> - ec_set_resource(ec, ECARD_RES_EASI,
> - PODSLOT_EASI_BASE + (slot << 24),
> - PODSLOT_EASI_SIZE);
> - }
> -
> - if (slot == 8) {
> - ec_set_resource(ec, ECARD_RES_MEMC, NETSLOT_BASE, NETSLOT_SIZE);
> - } else
> -#endif
> -
> - for (i = 0; i <= ECARD_RES_IOCSYNC - ECARD_RES_IOCSLOW; i++)
> - ec_set_resource(ec, i + ECARD_RES_IOCSLOW,
> - base + (i << 19), PODSLOT_IOC_SIZE);
> -
> - for (i = 0; i < ECARD_NUM_RESOURCES; i++) {
> - if (ec->resource[i].flags &&
> - request_resource(&iomem_resource, &ec->resource[i])) {
> - dev_err(&ec->dev, "resource(s) not available\n");
> - ec->resource[i].end -= ec->resource[i].start;
> - ec->resource[i].start = 0;
> - ec->resource[i].flags = 0;
> - }
> - }
> -
> - nomem:
> - return ec;
> -}
> -
> -static ssize_t irq_show(struct device *dev, struct device_attribute *attr, char *buf)
> -{
> - struct expansion_card *ec = ECARD_DEV(dev);
> - return sprintf(buf, "%u\n", ec->irq);
> -}
> -static DEVICE_ATTR_RO(irq);
> -
> -static ssize_t dma_show(struct device *dev, struct device_attribute *attr, char *buf)
> -{
> - struct expansion_card *ec = ECARD_DEV(dev);
> - return sprintf(buf, "%u\n", ec->dma);
> -}
> -static DEVICE_ATTR_RO(dma);
> -
> -static ssize_t resource_show(struct device *dev, struct device_attribute *attr, char *buf)
> -{
> - struct expansion_card *ec = ECARD_DEV(dev);
> - char *str = buf;
> - int i;
> -
> - for (i = 0; i < ECARD_NUM_RESOURCES; i++)
> - str += sprintf(str, "%08x %08x %08lx\n",
> - ec->resource[i].start,
> - ec->resource[i].end,
> - ec->resource[i].flags);
> -
> - return str - buf;
> -}
> -static DEVICE_ATTR_RO(resource);
> -
> -static ssize_t vendor_show(struct device *dev, struct device_attribute *attr, char *buf)
> -{
> - struct expansion_card *ec = ECARD_DEV(dev);
> - return sprintf(buf, "%u\n", ec->cid.manufacturer);
> -}
> -static DEVICE_ATTR_RO(vendor);
> -
> -static ssize_t device_show(struct device *dev, struct device_attribute *attr, char *buf)
> -{
> - struct expansion_card *ec = ECARD_DEV(dev);
> - return sprintf(buf, "%u\n", ec->cid.product);
> -}
> -static DEVICE_ATTR_RO(device);
> -
> -static ssize_t type_show(struct device *dev, struct device_attribute *attr, char *buf)
> -{
> - struct expansion_card *ec = ECARD_DEV(dev);
> - return sprintf(buf, "%s\n", ec->easi ? "EASI" : "IOC");
> -}
> -static DEVICE_ATTR_RO(type);
> -
> -static struct attribute *ecard_dev_attrs[] = {
> - &dev_attr_device.attr,
> - &dev_attr_dma.attr,
> - &dev_attr_irq.attr,
> - &dev_attr_resource.attr,
> - &dev_attr_type.attr,
> - &dev_attr_vendor.attr,
> - NULL,
> -};
> -ATTRIBUTE_GROUPS(ecard_dev);
> -
> -int ecard_request_resources(struct expansion_card *ec)
> -{
> - int i, err = 0;
> -
> - for (i = 0; i < ECARD_NUM_RESOURCES; i++) {
> - if (ecard_resource_end(ec, i) &&
> - !request_mem_region(ecard_resource_start(ec, i),
> - ecard_resource_len(ec, i),
> - ec->dev.driver->name)) {
> - err = -EBUSY;
> - break;
> - }
> - }
> -
> - if (err) {
> - while (i--)
> - if (ecard_resource_end(ec, i))
> - release_mem_region(ecard_resource_start(ec, i),
> - ecard_resource_len(ec, i));
> - }
> - return err;
> -}
> -EXPORT_SYMBOL(ecard_request_resources);
> -
> -void ecard_release_resources(struct expansion_card *ec)
> -{
> - int i;
> -
> - for (i = 0; i < ECARD_NUM_RESOURCES; i++)
> - if (ecard_resource_end(ec, i))
> - release_mem_region(ecard_resource_start(ec, i),
> - ecard_resource_len(ec, i));
> -}
> -EXPORT_SYMBOL(ecard_release_resources);
> -
> -void ecard_setirq(struct expansion_card *ec, const struct expansion_card_ops *ops, void *irq_data)
> -{
> - ec->irq_data = irq_data;
> - barrier();
> - ec->ops = ops;
> -}
> -EXPORT_SYMBOL(ecard_setirq);
> -
> -void __iomem *ecardm_iomap(struct expansion_card *ec, unsigned int res,
> - unsigned long offset, unsigned long maxsize)
> -{
> - unsigned long start = ecard_resource_start(ec, res);
> - unsigned long end = ecard_resource_end(ec, res);
> -
> - if (offset > (end - start))
> - return NULL;
> -
> - start += offset;
> - if (maxsize && end - start > maxsize)
> - end = start + maxsize;
> -
> - return devm_ioremap(&ec->dev, start, end - start);
> -}
> -EXPORT_SYMBOL(ecardm_iomap);
> -
> -static void atomwide_3p_quirk(ecard_t *ec)
> -{
> - void __iomem *addr = __ecard_address(ec, ECARD_IOC, ECARD_SYNC);
> - unsigned int i;
> -
> - /* Disable interrupts on each port */
> - for (i = 0x2000; i <= 0x2800; i += 0x0400)
> - writeb(0, addr + i + 4);
> -}
> -
> -/*
> - * Probe for an expansion card.
> - *
> - * If bit 1 of the first byte of the card is set, then the
> - * card does not exist.
> - */
> -static int __init ecard_probe(int slot, unsigned irq, card_type_t type)
> -{
> - ecard_t **ecp;
> - ecard_t *ec;
> - struct ex_ecid cid;
> - void __iomem *addr;
> - int i, rc;
> -
> - ec = ecard_alloc_card(type, slot);
> - if (IS_ERR(ec)) {
> - rc = PTR_ERR(ec);
> - goto nomem;
> - }
> -
> - rc = -ENODEV;
> - if ((addr = __ecard_address(ec, type, ECARD_SYNC)) == NULL)
> - goto nodev;
> -
> - cid.r_zero = 1;
> - ecard_readbytes(&cid, ec, 0, 16, 0);
> - if (cid.r_zero)
> - goto nodev;
> -
> - ec->cid.id = cid.r_id;
> - ec->cid.cd = cid.r_cd;
> - ec->cid.is = cid.r_is;
> - ec->cid.w = cid.r_w;
> - ec->cid.manufacturer = ecard_getu16(cid.r_manu);
> - ec->cid.product = ecard_getu16(cid.r_prod);
> - ec->cid.country = cid.r_country;
> - ec->cid.irqmask = cid.r_irqmask;
> - ec->cid.irqoff = ecard_gets24(cid.r_irqoff);
> - ec->cid.fiqmask = cid.r_fiqmask;
> - ec->cid.fiqoff = ecard_gets24(cid.r_fiqoff);
> - ec->fiqaddr =
> - ec->irqaddr = addr;
> -
> - if (ec->cid.is) {
> - ec->irqmask = ec->cid.irqmask;
> - ec->irqaddr += ec->cid.irqoff;
> - ec->fiqmask = ec->cid.fiqmask;
> - ec->fiqaddr += ec->cid.fiqoff;
> - } else {
> - ec->irqmask = 1;
> - ec->fiqmask = 4;
> - }
> -
> - for (i = 0; i < ARRAY_SIZE(quirklist); i++)
> - if (quirklist[i].manufacturer == ec->cid.manufacturer &&
> - quirklist[i].product == ec->cid.product) {
> - if (quirklist[i].type)
> - ec->card_desc = quirklist[i].type;
> - if (quirklist[i].init)
> - quirklist[i].init(ec);
> - break;
> - }
> -
> - ec->irq = irq;
> -
> - /*
> - * hook the interrupt handlers
> - */
> - if (slot < 8) {
> - irq_set_chip_and_handler(ec->irq, &ecard_chip,
> - handle_level_irq);
> - irq_set_chip_data(ec->irq, ec);
> - irq_clear_status_flags(ec->irq, IRQ_NOREQUEST);
> - }
> -
> -#ifdef CONFIG_ARCH_RPC
> - /* On RiscPC, only first two slots have DMA capability */
> - if (slot < 2)
> - ec->dma = 2 + slot;
> -#endif
> -
> - for (ecp = &cards; *ecp; ecp = &(*ecp)->next);
> -
> - *ecp = ec;
> - slot_to_expcard[slot] = ec;
> -
> - rc = device_register(&ec->dev);
> - if (rc)
> - goto nodev;
> -
> - return 0;
> -
> - nodev:
> - ecard_free_card(ec);
> - nomem:
> - return rc;
> -}
> -
> -/*
> - * Initialise the expansion card system.
> - * Locate all hardware - interrupt management and
> - * actual cards.
> - */
> -static int __init ecard_init(void)
> -{
> - struct task_struct *task;
> - int slot, irqbase;
> -
> - irqbase = irq_alloc_descs(-1, 0, 8, -1);
> - if (irqbase < 0)
> - return irqbase;
> -
> - task = kthread_run(ecard_task, NULL, "kecardd");
> - if (IS_ERR(task)) {
> - printk(KERN_ERR "Ecard: unable to create kernel thread: %ld\n",
> - PTR_ERR(task));
> - irq_free_descs(irqbase, 8);
> - return PTR_ERR(task);
> - }
> -
> - printk("Probing expansion cards\n");
> -
> - for (slot = 0; slot < 8; slot ++) {
> - if (ecard_probe(slot, irqbase + slot, ECARD_EASI) == -ENODEV)
> - ecard_probe(slot, irqbase + slot, ECARD_IOC);
> - }
> -
> - ecard_probe(8, 11, ECARD_IOC);
> -
> - irq_set_chained_handler(IRQ_EXPANSIONCARD, ecard_irq_handler);
> -
> - ecard_proc_init();
> -
> - return 0;
> -}
> -
> -subsys_initcall(ecard_init);
> -
> -/*
> - * ECARD "bus"
> - */
> -static const struct ecard_id *
> -ecard_match_device(const struct ecard_id *ids, struct expansion_card *ec)
> -{
> - int i;
> -
> - for (i = 0; ids[i].manufacturer != 65535; i++)
> - if (ec->cid.manufacturer == ids[i].manufacturer &&
> - ec->cid.product == ids[i].product)
> - return ids + i;
> -
> - return NULL;
> -}
> -
> -static int ecard_drv_probe(struct device *dev)
> -{
> - struct expansion_card *ec = ECARD_DEV(dev);
> - struct ecard_driver *drv = ECARD_DRV(dev->driver);
> - const struct ecard_id *id;
> - int ret;
> -
> - id = ecard_match_device(drv->id_table, ec);
> -
> - ec->claimed = 1;
> - ret = drv->probe(ec, id);
> - if (ret)
> - ec->claimed = 0;
> - return ret;
> -}
> -
> -static void ecard_drv_remove(struct device *dev)
> -{
> - struct expansion_card *ec = ECARD_DEV(dev);
> - struct ecard_driver *drv = ECARD_DRV(dev->driver);
> -
> - drv->remove(ec);
> - ec->claimed = 0;
> -
> - /*
> - * Restore the default operations. We ensure that the
> - * ops are set before we change the data.
> - */
> - ec->ops = &ecard_default_ops;
> - barrier();
> - ec->irq_data = NULL;
> -}
> -
> -/*
> - * Before rebooting, we must make sure that the expansion card is in a
> - * sensible state, so it can be re-detected. This means that the first
> - * page of the ROM must be visible. We call the expansion cards reset
> - * handler, if any.
> - */
> -static void ecard_drv_shutdown(struct device *dev)
> -{
> - struct expansion_card *ec = ECARD_DEV(dev);
> - struct ecard_driver *drv = ECARD_DRV(dev->driver);
> - struct ecard_request req;
> -
> - if (dev->driver) {
> - if (drv->shutdown)
> - drv->shutdown(ec);
> - ec->claimed = 0;
> - }
> -
> - /*
> - * If this card has a loader, call the reset handler.
> - */
> - if (ec->loader) {
> - req.fn = ecard_task_reset;
> - req.ec = ec;
> - ecard_call(&req);
> - }
> -}
> -
> -int ecard_register_driver(struct ecard_driver *drv)
> -{
> - drv->drv.bus = &ecard_bus_type;
> -
> - return driver_register(&drv->drv);
> -}
> -
> -void ecard_remove_driver(struct ecard_driver *drv)
> -{
> - driver_unregister(&drv->drv);
> -}
> -
> -static int ecard_match(struct device *_dev, const struct device_driver *_drv)
> -{
> - struct expansion_card *ec = ECARD_DEV(_dev);
> - struct ecard_driver *drv = ECARD_DRV(_drv);
> - int ret;
> -
> - if (drv->id_table) {
> - ret = ecard_match_device(drv->id_table, ec) != NULL;
> - } else {
> - ret = ec->cid.id == drv->id;
> - }
> -
> - return ret;
> -}
> -
> -const struct bus_type ecard_bus_type = {
> - .name = "ecard",
> - .dev_groups = ecard_dev_groups,
> - .match = ecard_match,
> - .probe = ecard_drv_probe,
> - .remove = ecard_drv_remove,
> - .shutdown = ecard_drv_shutdown,
> -};
> -
> -static int ecard_bus_init(void)
> -{
> - return bus_register(&ecard_bus_type);
> -}
> -
> -postcore_initcall(ecard_bus_init);
> -
> -EXPORT_SYMBOL(ecard_readchunk);
> -EXPORT_SYMBOL(ecard_register_driver);
> -EXPORT_SYMBOL(ecard_remove_driver);
> -EXPORT_SYMBOL(ecard_bus_type);
> diff --git a/arch/arm/mach-rpc/ecard.h b/arch/arm/mach-rpc/ecard.h
> deleted file mode 100644
> index 873dd3d9f274..000000000000
> --- a/arch/arm/mach-rpc/ecard.h
> +++ /dev/null
> @@ -1,66 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * ecard.h
> - *
> - * Copyright 2007 Russell King
> - */
> -
> -/* Definitions internal to ecard.c - for it's use only!!
> - *
> - * External expansion card header as read from the card
> - */
> -struct ex_ecid {
> - unsigned char r_irq:1;
> - unsigned char r_zero:1;
> - unsigned char r_fiq:1;
> - unsigned char r_id:4;
> - unsigned char r_a:1;
> -
> - unsigned char r_cd:1;
> - unsigned char r_is:1;
> - unsigned char r_w:2;
> - unsigned char r_r1:4;
> -
> - unsigned char r_r2:8;
> -
> - unsigned char r_prod[2];
> -
> - unsigned char r_manu[2];
> -
> - unsigned char r_country;
> -
> - unsigned char r_fiqmask;
> - unsigned char r_fiqoff[3];
> -
> - unsigned char r_irqmask;
> - unsigned char r_irqoff[3];
> -};
> -
> -/*
> - * Chunk directory entry as read from the card
> - */
> -struct ex_chunk_dir {
> - unsigned char r_id;
> - unsigned char r_len[3];
> - unsigned long r_start;
> - union {
> - char string[256];
> - char data[1];
> - } d;
> -#define c_id(x) ((x)->r_id)
> -#define c_len(x) ((x)->r_len[0]|((x)->r_len[1]<<8)|((x)->r_len[2]<<16))
> -#define c_start(x) ((x)->r_start)
> -};
> -
> -typedef enum ecard_type { /* Cards address space */
> - ECARD_IOC,
> - ECARD_MEMC,
> - ECARD_EASI
> -} card_type_t;
> -
> -typedef enum { /* Speed for ECARD_IOC space */
> - ECARD_SLOW = 0,
> - ECARD_MEDIUM = 1,
> - ECARD_FAST = 2,
> - ECARD_SYNC = 3
> -} card_speed_t;
> diff --git a/arch/arm/mach-rpc/fiq.S b/arch/arm/mach-rpc/fiq.S
> deleted file mode 100644
> index 087bdf4bc093..000000000000
> --- a/arch/arm/mach-rpc/fiq.S
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -#include <linux/linkage.h>
> -#include <asm/assembler.h>
> -#include <mach/hardware.h>
> -
> - .equ ioc_base_high, IOC_BASE & 0xff000000
> - .equ ioc_base_low, IOC_BASE & 0x00ff0000
> -
> - .text
> - .global rpc_default_fiq_end
> -ENTRY(rpc_default_fiq_start)
> - mov r12, #ioc_base_high
> - .if ioc_base_low
> - orr r12, r12, #ioc_base_low
> - .endif
> - strb r12, [r12, #0x38] @ Disable FIQ register
> - subs pc, lr, #4
> -rpc_default_fiq_end:
> diff --git a/arch/arm/mach-rpc/floppydma.S b/arch/arm/mach-rpc/floppydma.S
> deleted file mode 100644
> index 6698b83050dc..000000000000
> --- a/arch/arm/mach-rpc/floppydma.S
> +++ /dev/null
> @@ -1,29 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * linux/arch/arm/lib/floppydma.S
> - *
> - * Copyright (C) 1995, 1996 Russell King
> - */
> -#include <linux/linkage.h>
> -#include <asm/assembler.h>
> - .text
> -
> - .global floppy_fiqin_end
> -ENTRY(floppy_fiqin_start)
> - subs r9, r9, #1
> - ldrbgt r12, [r11, #-4]
> - ldrble r12, [r11], #0
> - strb r12, [r10], #1
> - subs pc, lr, #4
> -floppy_fiqin_end:
> -
> - .global floppy_fiqout_end
> -ENTRY(floppy_fiqout_start)
> - subs r9, r9, #1
> - ldrbge r12, [r10], #1
> - movlt r12, #0
> - strble r12, [r11], #0
> - subsle pc, lr, #4
> - strb r12, [r11, #-4]
> - subs pc, lr, #4
> -floppy_fiqout_end:
> diff --git a/arch/arm/mach-rpc/include/mach/acornfb.h b/arch/arm/mach-rpc/include/mach/acornfb.h
> deleted file mode 100644
> index 2bf18ab3d699..000000000000
> --- a/arch/arm/mach-rpc/include/mach/acornfb.h
> +++ /dev/null
> @@ -1,137 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * arch/arm/mach-rpc/include/mach/acornfb.h
> - *
> - * Copyright (C) 1999 Russell King
> - *
> - * AcornFB architecture specific code
> - */
> -
> -#define acornfb_bandwidth(var) ((var)->pixclock * 8 / (var)->bits_per_pixel)
> -
> -static inline int
> -acornfb_valid_pixrate(struct fb_var_screeninfo *var)
> -{
> - u_long limit;
> -
> - if (!var->pixclock)
> - return 0;
> -
> - /*
> - * Limits below are taken from RISC OS bandwidthlimit file
> - */
> - if (current_par.using_vram) {
> - if (current_par.vram_half_sam == 2048)
> - limit = 6578;
> - else
> - limit = 13157;
> - } else {
> - limit = 26315;
> - }
> -
> - return acornfb_bandwidth(var) >= limit;
> -}
> -
> -/*
> - * Try to find the best PLL parameters for the pixel clock.
> - * This algorithm seems to give best predictable results,
> - * and produces the same values as detailed in the VIDC20
> - * data sheet.
> - */
> -static inline u_int
> -acornfb_vidc20_find_pll(u_int pixclk)
> -{
> - u_int r, best_r = 2, best_v = 2;
> - int best_d = 0x7fffffff;
> -
> - for (r = 2; r <= 32; r++) {
> - u_int rr, v, p;
> - int d;
> -
> - rr = 41667 * r;
> -
> - v = (rr + pixclk / 2) / pixclk;
> -
> - if (v > 32 || v < 2)
> - continue;
> -
> - p = (rr + v / 2) / v;
> -
> - d = pixclk - p;
> -
> - if (d < 0)
> - d = -d;
> -
> - if (d < best_d) {
> - best_d = d;
> - best_v = v - 1;
> - best_r = r - 1;
> - }
> -
> - if (d == 0)
> - break;
> - }
> -
> - return best_v << 8 | best_r;
> -}
> -
> -static inline void
> -acornfb_vidc20_find_rates(struct vidc_timing *vidc,
> - struct fb_var_screeninfo *var)
> -{
> - u_int div;
> -
> - /* Select pixel-clock divisor to keep PLL in range */
> - div = var->pixclock / 9090; /*9921*/
> -
> - /* Limit divisor */
> - if (div == 0)
> - div = 1;
> - if (div > 8)
> - div = 8;
> -
> - /* Encode divisor to VIDC20 setting */
> - switch (div) {
> - case 1: vidc->control |= VIDC20_CTRL_PIX_CK; break;
> - case 2: vidc->control |= VIDC20_CTRL_PIX_CK2; break;
> - case 3: vidc->control |= VIDC20_CTRL_PIX_CK3; break;
> - case 4: vidc->control |= VIDC20_CTRL_PIX_CK4; break;
> - case 5: vidc->control |= VIDC20_CTRL_PIX_CK5; break;
> - case 6: vidc->control |= VIDC20_CTRL_PIX_CK6; break;
> - case 7: vidc->control |= VIDC20_CTRL_PIX_CK7; break;
> - case 8: vidc->control |= VIDC20_CTRL_PIX_CK8; break;
> - }
> -
> - /*
> - * With VRAM, the FIFO can be set to the highest possible setting
> - * because there are no latency considerations for other memory
> - * accesses. However, in 64 bit bus mode the FIFO preload value
> - * must not be set to VIDC20_CTRL_FIFO_28 because this will let
> - * the FIFO overflow. See VIDC20 manual page 33 (6.0 Setting the
> - * FIFO preload value).
> - */
> - if (current_par.using_vram) {
> - if (current_par.vram_half_sam == 2048)
> - vidc->control |= VIDC20_CTRL_FIFO_24;
> - else
> - vidc->control |= VIDC20_CTRL_FIFO_28;
> - } else {
> - unsigned long bandwidth = acornfb_bandwidth(var);
> -
> - /* Encode bandwidth as VIDC20 setting */
> - if (bandwidth > 33334) /* < 30.0MB/s */
> - vidc->control |= VIDC20_CTRL_FIFO_16;
> - else if (bandwidth > 26666) /* < 37.5MB/s */
> - vidc->control |= VIDC20_CTRL_FIFO_20;
> - else if (bandwidth > 22222) /* < 45.0MB/s */
> - vidc->control |= VIDC20_CTRL_FIFO_24;
> - else /* > 45.0MB/s */
> - vidc->control |= VIDC20_CTRL_FIFO_28;
> - }
> -
> - /* Find the PLL values */
> - vidc->pll_ctl = acornfb_vidc20_find_pll(var->pixclock / div);
> -}
> -
> -#define acornfb_default_control() (VIDC20_CTRL_PIX_VCLK)
> -#define acornfb_default_econtrol() (VIDC20_ECTL_DAC | VIDC20_ECTL_REG(3))
> diff --git a/arch/arm/mach-rpc/include/mach/hardware.h b/arch/arm/mach-rpc/include/mach/hardware.h
> deleted file mode 100644
> index 6f197706f979..000000000000
> --- a/arch/arm/mach-rpc/include/mach/hardware.h
> +++ /dev/null
> @@ -1,73 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * arch/arm/mach-rpc/include/mach/hardware.h
> - *
> - * Copyright (C) 1996-1999 Russell King.
> - *
> - * This file contains the hardware definitions of the RiscPC series machines.
> - */
> -#ifndef __ASM_ARCH_HARDWARE_H
> -#define __ASM_ARCH_HARDWARE_H
> -
> -#include <mach/memory.h>
> -
> -/*
> - * What hardware must be present
> - */
> -#define HAS_IOMD
> -#define HAS_VIDC20
> -
> -/* Hardware addresses of major areas.
> - * *_START is the physical address
> - * *_SIZE is the size of the region
> - * *_BASE is the virtual address
> - */
> -#define RPC_RAM_SIZE 0x10000000
> -#define RPC_RAM_START 0x10000000
> -
> -#define EASI_SIZE 0x08000000 /* EASI I/O */
> -#define EASI_START 0x08000000
> -#define EASI_BASE IOMEM(0xe5000000)
> -
> -#define IO_START 0x03000000 /* I/O */
> -#define IO_SIZE 0x01000000
> -#define IO_BASE IOMEM(0xe0000000)
> -
> -#define SCREEN_START 0x02000000 /* VRAM */
> -#define SCREEN_END 0xdfc00000
> -#define SCREEN_BASE 0xdf800000
> -
> -#define UNCACHEABLE_ADDR (FLUSH_BASE + 0x10000)
> -
> -/*
> - * IO Addresses
> - */
> -#define ECARD_EASI_BASE (EASI_BASE)
> -#define VIDC_BASE (IO_BASE + 0x00400000)
> -#define EXPMASK_BASE (IO_BASE + 0x00360000)
> -#define ECARD_IOC4_BASE (IO_BASE + 0x00270000)
> -#define ECARD_IOC_BASE (IO_BASE + 0x00240000)
> -#define IOMD_BASE (IO_BASE + 0x00200000)
> -#define IOC_BASE (IO_BASE + 0x00200000)
> -#define ECARD_MEMC8_BASE (IO_BASE + 0x0002b000)
> -#define FLOPPYDMA_BASE (IO_BASE + 0x0002a000)
> -#define PCIO_BASE (IO_BASE + 0x00010000)
> -#define ECARD_MEMC_BASE (IO_BASE + 0x00000000)
> -
> -#define vidc_writel(val) __raw_writel(val, VIDC_BASE)
> -
> -#define NETSLOT_BASE 0x0302b000
> -#define NETSLOT_SIZE 0x00001000
> -
> -#define PODSLOT_IOC0_BASE 0x03240000
> -#define PODSLOT_IOC4_BASE 0x03270000
> -#define PODSLOT_IOC_SIZE (1 << 14)
> -#define PODSLOT_MEMC_BASE 0x03000000
> -#define PODSLOT_MEMC_SIZE (1 << 14)
> -#define PODSLOT_EASI_BASE 0x08000000
> -#define PODSLOT_EASI_SIZE (1 << 24)
> -
> -#define EXPMASK_STATUS (EXPMASK_BASE + 0x00)
> -#define EXPMASK_ENABLE (EXPMASK_BASE + 0x04)
> -
> -#endif
> diff --git a/arch/arm/mach-rpc/include/mach/io.h b/arch/arm/mach-rpc/include/mach/io.h
> deleted file mode 100644
> index 8a8f28406691..000000000000
> --- a/arch/arm/mach-rpc/include/mach/io.h
> +++ /dev/null
> @@ -1,28 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * arch/arm/mach-rpc/include/mach/io.h
> - *
> - * Copyright (C) 1997 Russell King
> - *
> - * Modifications:
> - * 06-Dec-1997 RMK Created.
> - */
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#include <mach/hardware.h>
> -
> -#define IO_SPACE_LIMIT 0xffff
> -
> -/*
> - * We need PC style IO addressing for:
> - * - floppy (at 0x3f2,0x3f4,0x3f5,0x3f7)
> - * - parport (at 0x278-0x27a, 0x27b-0x27f, 0x778-0x77a)
> - * - 8250 serial (only for compile)
> - *
> - * These peripherals are found in an area of MMIO which looks very much
> - * like an ISA bus, but with registers at the low byte of each word.
> - */
> -#define __io(a) (PCIO_BASE + ((a) << 2))
> -
> -#endif
> diff --git a/arch/arm/mach-rpc/include/mach/irqs.h b/arch/arm/mach-rpc/include/mach/irqs.h
> deleted file mode 100644
> index 0c3428fd9729..000000000000
> --- a/arch/arm/mach-rpc/include/mach/irqs.h
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * arch/arm/mach-rpc/include/mach/irqs.h
> - *
> - * Copyright (C) 1996 Russell King
> - */
> -
> -#define IRQ_PRINTER 0
> -#define IRQ_BATLOW 1
> -#define IRQ_FLOPPYINDEX 2
> -#define IRQ_VSYNCPULSE 3
> -#define IRQ_POWERON 4
> -#define IRQ_TIMER0 5
> -#define IRQ_TIMER1 6
> -#define IRQ_IMMEDIATE 7
> -#define IRQ_EXPCARDFIQ 8
> -#define IRQ_HARDDISK 9
> -#define IRQ_SERIALPORT 10
> -#define IRQ_FLOPPYDISK 12
> -#define IRQ_EXPANSIONCARD 13
> -#define IRQ_KEYBOARDTX 14
> -#define IRQ_KEYBOARDRX 15
> -
> -#define IRQ_DMA0 16
> -#define IRQ_DMA1 17
> -#define IRQ_DMA2 18
> -#define IRQ_DMA3 19
> -#define IRQ_DMAS0 20
> -#define IRQ_DMAS1 21
> -
> -#define FIQ_FLOPPYDATA 0
> -#define FIQ_ECONET 2
> -#define FIQ_SERIALPORT 4
> -#define FIQ_EXPANSIONCARD 6
> -#define FIQ_FORCE 7
> -
> -/*
> - * This is the offset of the FIQ "IRQ" numbers
> - */
> -#define FIQ_START 64
> -
> -#define NR_IRQS 128
> diff --git a/arch/arm/mach-rpc/include/mach/isa-dma.h b/arch/arm/mach-rpc/include/mach/isa-dma.h
> deleted file mode 100644
> index d9c3af1ef718..000000000000
> --- a/arch/arm/mach-rpc/include/mach/isa-dma.h
> +++ /dev/null
> @@ -1,26 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * arch/arm/mach-rpc/include/mach/isa-dma.h
> - *
> - * Copyright (C) 1997 Russell King
> - */
> -#ifndef __ASM_ARCH_DMA_H
> -#define __ASM_ARCH_DMA_H
> -
> -#define MAX_DMA_CHANNELS 8
> -
> -#define DMA_0 0
> -#define DMA_1 1
> -#define DMA_2 2
> -#define DMA_3 3
> -#define DMA_S0 4
> -#define DMA_S1 5
> -#define DMA_VIRTUAL_FLOPPY 6
> -#define DMA_VIRTUAL_SOUND 7
> -
> -#define DMA_FLOPPY DMA_VIRTUAL_FLOPPY
> -
> -#define IOMD_DMA_BOUNDARY (PAGE_SIZE - 1)
> -
> -#endif /* _ASM_ARCH_DMA_H */
> -
> diff --git a/arch/arm/mach-rpc/include/mach/memory.h b/arch/arm/mach-rpc/include/mach/memory.h
> deleted file mode 100644
> index a586eb31b18d..000000000000
> --- a/arch/arm/mach-rpc/include/mach/memory.h
> +++ /dev/null
> @@ -1,32 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * arch/arm/mach-rpc/include/mach/memory.h
> - *
> - * Copyright (C) 1996,1997,1998 Russell King.
> - *
> - * Changelog:
> - * 20-Oct-1996 RMK Created
> - * 31-Dec-1997 RMK Fixed definitions to reduce warnings
> - * 11-Jan-1998 RMK Uninlined to reduce hits on cache
> - * 08-Feb-1998 RMK Added __virt_to_bus and __bus_to_virt
> - * 21-Mar-1999 RMK Renamed to memory.h
> - * RMK Added TASK_SIZE and PAGE_OFFSET
> - */
> -#ifndef __ASM_ARCH_MEMORY_H
> -#define __ASM_ARCH_MEMORY_H
> -
> -/*
> - * Cache flushing area - ROM
> - */
> -#define FLUSH_BASE_PHYS 0x00000000
> -#define FLUSH_BASE 0xdf000000
> -
> -/*
> - * Sparsemem support. Each section is a maximum of 64MB. The sections
> - * are offset by 128MB and can cover 128MB, so that gives us a maximum
> - * of 29 physmem bits.
> - */
> -#define MAX_PHYSMEM_BITS 29
> -#define SECTION_SIZE_BITS 26
> -
> -#endif
> diff --git a/arch/arm/mach-rpc/include/mach/uncompress.h b/arch/arm/mach-rpc/include/mach/uncompress.h
> deleted file mode 100644
> index 1fbe7eb956fd..000000000000
> --- a/arch/arm/mach-rpc/include/mach/uncompress.h
> +++ /dev/null
> @@ -1,181 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * arch/arm/mach-rpc/include/mach/uncompress.h
> - *
> - * Copyright (C) 1996 Russell King
> - */
> -#define VIDMEM ((char *)SCREEN_START)
> -
> -#include <linux/io.h>
> -#include <mach/hardware.h>
> -#include <asm/setup.h>
> -#include <asm/page.h>
> -
> -int video_size_row;
> -unsigned char bytes_per_char_h;
> -extern unsigned long con_charconvtable[256];
> -
> -struct param_struct {
> - unsigned long page_size;
> - unsigned long nr_pages;
> - unsigned long ramdisk_size;
> - unsigned long mountrootrdonly;
> - unsigned long rootdev;
> - unsigned long video_num_cols;
> - unsigned long video_num_rows;
> - unsigned long video_x;
> - unsigned long video_y;
> - unsigned long memc_control_reg;
> - unsigned char sounddefault;
> - unsigned char adfsdrives;
> - unsigned char bytes_per_char_h;
> - unsigned char bytes_per_char_v;
> - unsigned long unused[256/4-11];
> -};
> -
> -static const unsigned long palette_4[16] = {
> - 0x00000000,
> - 0x000000cc,
> - 0x0000cc00, /* Green */
> - 0x0000cccc, /* Yellow */
> - 0x00cc0000, /* Blue */
> - 0x00cc00cc, /* Magenta */
> - 0x00cccc00, /* Cyan */
> - 0x00cccccc, /* White */
> - 0x00000000,
> - 0x000000ff,
> - 0x0000ff00,
> - 0x0000ffff,
> - 0x00ff0000,
> - 0x00ff00ff,
> - 0x00ffff00,
> - 0x00ffffff
> -};
> -
> -#define palette_setpixel(p) *(unsigned long *)(IO_START+0x00400000) = 0x10000000|((p) & 255)
> -#define palette_write(v) *(unsigned long *)(IO_START+0x00400000) = 0x00000000|((v) & 0x00ffffff)
> -
> -/*
> - * params_phys is a linker defined symbol - see
> - * arch/arm/boot/compressed/Makefile
> - */
> -extern __attribute__((pure)) struct param_struct *params(void);
> -#define params (params())
> -
> -#ifndef STANDALONE_DEBUG
> -unsigned long video_num_cols;
> -unsigned long video_num_rows;
> -unsigned long video_x;
> -unsigned long video_y;
> -unsigned char bytes_per_char_v;
> -int white;
> -
> -/*
> - * This does not append a newline
> - */
> -static inline void putc(int c)
> -{
> - extern void ll_write_char(char *, char c, char white);
> - int x,y;
> - char *ptr;
> -
> - x = video_x;
> - y = video_y;
> -
> - if (c == '\n') {
> - if (++y >= video_num_rows)
> - y--;
> - } else if (c == '\r') {
> - x = 0;
> - } else {
> - ptr = VIDMEM + ((y*video_num_cols*bytes_per_char_v+x)*bytes_per_char_h);
> - ll_write_char(ptr, c, white);
> - if (++x >= video_num_cols) {
> - x = 0;
> - if ( ++y >= video_num_rows ) {
> - y--;
> - }
> - }
> - }
> -
> - video_x = x;
> - video_y = y;
> -}
> -
> -static inline void flush(void)
> -{
> -}
> -
> -/*
> - * Setup for decompression
> - */
> -static void arch_decomp_setup(void)
> -{
> - int i;
> - struct tag *t = (struct tag *)params;
> - unsigned int nr_pages = 0, page_size = PAGE_SIZE;
> -
> - if (t->hdr.tag == ATAG_CORE) {
> - for (; t->hdr.size; t = tag_next(t)) {
> - if (t->hdr.tag == ATAG_VIDEOTEXT) {
> - video_num_rows = t->u.videotext.video_lines;
> - video_num_cols = t->u.videotext.video_cols;
> - video_x = t->u.videotext.x;
> - video_y = t->u.videotext.y;
> - } else if (t->hdr.tag == ATAG_VIDEOLFB) {
> - bytes_per_char_h = t->u.videolfb.lfb_depth;
> - bytes_per_char_v = 8;
> - } else if (t->hdr.tag == ATAG_MEM) {
> - page_size = PAGE_SIZE;
> - nr_pages += (t->u.mem.size / PAGE_SIZE);
> - }
> - }
> - } else {
> - nr_pages = params->nr_pages;
> - page_size = params->page_size;
> - video_num_rows = params->video_num_rows;
> - video_num_cols = params->video_num_cols;
> - video_x = params->video_x;
> - video_y = params->video_y;
> - bytes_per_char_h = params->bytes_per_char_h;
> - bytes_per_char_v = params->bytes_per_char_v;
> - }
> -
> - video_size_row = video_num_cols * bytes_per_char_h;
> -
> - if (bytes_per_char_h == 4)
> - for (i = 0; i < 256; i++)
> - con_charconvtable[i] =
> - (i & 128 ? 1 << 0 : 0) |
> - (i & 64 ? 1 << 4 : 0) |
> - (i & 32 ? 1 << 8 : 0) |
> - (i & 16 ? 1 << 12 : 0) |
> - (i & 8 ? 1 << 16 : 0) |
> - (i & 4 ? 1 << 20 : 0) |
> - (i & 2 ? 1 << 24 : 0) |
> - (i & 1 ? 1 << 28 : 0);
> - else
> - for (i = 0; i < 16; i++)
> - con_charconvtable[i] =
> - (i & 8 ? 1 << 0 : 0) |
> - (i & 4 ? 1 << 8 : 0) |
> - (i & 2 ? 1 << 16 : 0) |
> - (i & 1 ? 1 << 24 : 0);
> -
> -
> - palette_setpixel(0);
> - if (bytes_per_char_h == 1) {
> - palette_write (0);
> - palette_write (0x00ffffff);
> - for (i = 2; i < 256; i++)
> - palette_write (0);
> - white = 1;
> - } else {
> - for (i = 0; i < 256; i++)
> - palette_write (i < 16 ? palette_4[i] : 0);
> - white = 7;
> - }
> -
> - if (nr_pages * page_size < 4096*1024) error("<4M of mem\n");
> -}
> -#endif
> diff --git a/arch/arm/mach-rpc/io-acorn.S b/arch/arm/mach-rpc/io-acorn.S
> deleted file mode 100644
> index aa9bf0d771c0..000000000000
> --- a/arch/arm/mach-rpc/io-acorn.S
> +++ /dev/null
> @@ -1,28 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * linux/arch/arm/lib/io-acorn.S
> - *
> - * Copyright (C) 1995, 1996 Russell King
> - *
> - * 27/03/03 Ian Molton Clean up CONFIG_CPU
> - */
> -#include <linux/linkage.h>
> -#include <linux/kern_levels.h>
> -#include <asm/assembler.h>
> -
> - .text
> - .align
> -
> -.Liosl_warning:
> - .ascii KERN_WARNING "insl/outsl not implemented, called from %08lX\0"
> - .align
> -
> -/*
> - * These make no sense on Acorn machines.
> - * Print a warning message.
> - */
> -ENTRY(insl)
> -ENTRY(outsl)
> - adr r0, .Liosl_warning
> - mov r1, lr
> - b _printk
> diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
> deleted file mode 100644
> index dc29384b6ef8..000000000000
> --- a/arch/arm/mach-rpc/irq.c
> +++ /dev/null
> @@ -1,226 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -#include <linux/init.h>
> -#include <linux/list.h>
> -#include <linux/io.h>
> -
> -#include <asm/mach/irq.h>
> -#include <asm/hardware/iomd.h>
> -#include <asm/irq.h>
> -#include <asm/fiq.h>
> -
> -// These are offsets from the stat register for each IRQ bank
> -#define STAT 0x00
> -#define REQ 0x04
> -#define CLR 0x04
> -#define MASK 0x08
> -
> -static const u8 irq_prio_h[256] = {
> - 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10,
> - 12, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10,
> - 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
> - 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
> - 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10,
> - 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10,
> - 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
> - 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
> - 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10,
> - 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10,
> - 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
> - 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
> - 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10,
> - 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10,
> - 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
> - 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
> -};
> -
> -static const u8 irq_prio_d[256] = {
> - 0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
> - 20,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
> - 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
> - 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
> - 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
> - 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
> - 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
> - 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
> - 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
> - 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
> - 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
> - 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
> - 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
> - 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
> - 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
> - 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
> -};
> -
> -static const u8 irq_prio_l[256] = {
> - 0, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,
> - 4, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,
> - 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
> - 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
> - 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3,
> - 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3,
> - 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
> - 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
> - 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
> - 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
> - 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
> - 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
> - 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
> - 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
> - 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
> - 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
> -};
> -
> -static int iomd_get_irq_nr(void)
> -{
> - int irq;
> - u8 reg;
> -
> - /* get highest priority first */
> - reg = readb(IOC_BASE + IOMD_IRQREQB);
> - irq = irq_prio_h[reg];
> - if (irq)
> - return irq;
> -
> - /* get DMA */
> - reg = readb(IOC_BASE + IOMD_DMAREQ);
> - irq = irq_prio_d[reg];
> - if (irq)
> - return irq;
> -
> - /* get low priority */
> - reg = readb(IOC_BASE + IOMD_IRQREQA);
> - irq = irq_prio_l[reg];
> - if (irq)
> - return irq;
> - return 0;
> -}
> -
> -static void iomd_handle_irq(struct pt_regs *regs)
> -{
> - int irq;
> -
> - do {
> - irq = iomd_get_irq_nr();
> - if (irq)
> - generic_handle_irq(irq);
> - } while (irq);
> -}
> -
> -static void __iomem *iomd_get_base(struct irq_data *d)
> -{
> - void *cd = irq_data_get_irq_chip_data(d);
> -
> - return (void __iomem *)(unsigned long)cd;
> -}
> -
> -static void iomd_set_base_mask(unsigned int irq, void __iomem *base, u32 mask)
> -{
> - struct irq_data *d = irq_get_irq_data(irq);
> -
> - d->mask = mask;
> - irq_set_chip_data(irq, (void *)(unsigned long)base);
> -}
> -
> -static void iomd_irq_mask_ack(struct irq_data *d)
> -{
> - void __iomem *base = iomd_get_base(d);
> - unsigned int val, mask = d->mask;
> -
> - val = readb(base + MASK);
> - writeb(val & ~mask, base + MASK);
> - writeb(mask, base + CLR);
> -}
> -
> -static void iomd_irq_mask(struct irq_data *d)
> -{
> - void __iomem *base = iomd_get_base(d);
> - unsigned int val, mask = d->mask;
> -
> - val = readb(base + MASK);
> - writeb(val & ~mask, base + MASK);
> -}
> -
> -static void iomd_irq_unmask(struct irq_data *d)
> -{
> - void __iomem *base = iomd_get_base(d);
> - unsigned int val, mask = d->mask;
> -
> - val = readb(base + MASK);
> - writeb(val | mask, base + MASK);
> -}
> -
> -static struct irq_chip iomd_chip_clr = {
> - .irq_mask_ack = iomd_irq_mask_ack,
> - .irq_mask = iomd_irq_mask,
> - .irq_unmask = iomd_irq_unmask,
> -};
> -
> -static struct irq_chip iomd_chip_noclr = {
> - .irq_mask = iomd_irq_mask,
> - .irq_unmask = iomd_irq_unmask,
> -};
> -
> -extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end;
> -
> -void __init rpc_init_irq(void)
> -{
> - unsigned int irq, clr, set;
> -
> - iomd_writeb(0, IOMD_IRQMASKA);
> - iomd_writeb(0, IOMD_IRQMASKB);
> - iomd_writeb(0, IOMD_FIQMASK);
> - iomd_writeb(0, IOMD_DMAMASK);
> -
> - set_fiq_handler(&rpc_default_fiq_start,
> - &rpc_default_fiq_end - &rpc_default_fiq_start);
> -
> - set_handle_irq(iomd_handle_irq);
> -
> - for (irq = 0; irq < NR_IRQS; irq++) {
> - clr = IRQ_NOREQUEST;
> - set = 0;
> -
> - if (irq <= 6 || (irq >= 9 && irq <= 15))
> - clr |= IRQ_NOPROBE;
> -
> - if (irq == 21 || (irq >= 16 && irq <= 19) ||
> - irq == IRQ_KEYBOARDTX)
> - set |= IRQ_NOAUTOEN;
> -
> - switch (irq) {
> - case 0 ... 7:
> - irq_set_chip_and_handler(irq, &iomd_chip_clr,
> - handle_level_irq);
> - irq_modify_status(irq, clr, set);
> - iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATA,
> - BIT(irq));
> - break;
> -
> - case 8 ... 15:
> - irq_set_chip_and_handler(irq, &iomd_chip_noclr,
> - handle_level_irq);
> - irq_modify_status(irq, clr, set);
> - iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATB,
> - BIT(irq - 8));
> - break;
> -
> - case 16 ... 21:
> - irq_set_chip_and_handler(irq, &iomd_chip_noclr,
> - handle_level_irq);
> - irq_modify_status(irq, clr, set);
> - iomd_set_base_mask(irq, IOMD_BASE + IOMD_DMASTAT,
> - BIT(irq - 16));
> - break;
> -
> - case 64 ... 71:
> - irq_set_chip(irq, &iomd_chip_noclr);
> - irq_modify_status(irq, clr, set);
> - iomd_set_base_mask(irq, IOMD_BASE + IOMD_FIQSTAT,
> - BIT(irq - 64));
> - break;
> - }
> - }
> -
> - init_FIQ(FIQ_START);
> -}
> diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
> deleted file mode 100644
> index f70fb9c4b0cb..000000000000
> --- a/arch/arm/mach-rpc/riscpc.c
> +++ /dev/null
> @@ -1,225 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * linux/arch/arm/mach-rpc/riscpc.c
> - *
> - * Copyright (C) 1998-2001 Russell King
> - *
> - * Architecture specific fixups.
> - */
> -#include <linux/kernel.h>
> -#include <linux/tty.h>
> -#include <linux/delay.h>
> -#include <linux/pm.h>
> -#include <linux/init.h>
> -#include <linux/sched.h>
> -#include <linux/device.h>
> -#include <linux/serial_8250.h>
> -#include <linux/ata_platform.h>
> -#include <linux/io.h>
> -#include <linux/i2c.h>
> -#include <linux/reboot.h>
> -
> -#include <asm/elf.h>
> -#include <asm/mach-types.h>
> -#include <mach/hardware.h>
> -#include <asm/hardware/iomd.h>
> -#include <asm/page.h>
> -#include <asm/domain.h>
> -#include <asm/setup.h>
> -#include <asm/system_misc.h>
> -
> -#include <asm/mach/map.h>
> -#include <asm/mach/arch.h>
> -#include <asm/mach/time.h>
> -
> -extern void rpc_init_irq(void);
> -
> -unsigned int vram_size;
> -unsigned int memc_ctrl_reg;
> -unsigned int number_mfm_drives;
> -
> -static int __init parse_tag_acorn(const struct tag *tag)
> -{
> - memc_ctrl_reg = tag->u.acorn.memc_control_reg;
> - number_mfm_drives = tag->u.acorn.adfsdrives;
> -
> - switch (tag->u.acorn.vram_pages) {
> - case 512:
> - vram_size += PAGE_SIZE * 256;
> - fallthrough; /* ??? */
> - case 256:
> - vram_size += PAGE_SIZE * 256;
> - break;
> - default:
> - break;
> - }
> -#if 0
> - if (vram_size) {
> - desc->video_start = 0x02000000;
> - desc->video_end = 0x02000000 + vram_size;
> - }
> -#endif
> - return 0;
> -}
> -
> -__tagtable(ATAG_ACORN, parse_tag_acorn);
> -
> -static struct map_desc rpc_io_desc[] __initdata = {
> - { /* VRAM */
> - .virtual = SCREEN_BASE,
> - .pfn = __phys_to_pfn(SCREEN_START),
> - .length = 2*1048576,
> - .type = MT_DEVICE
> - }, { /* IO space */
> - .virtual = (u32)IO_BASE,
> - .pfn = __phys_to_pfn(IO_START),
> - .length = IO_SIZE ,
> - .type = MT_DEVICE
> - }, { /* EASI space */
> - .virtual = (unsigned long)EASI_BASE,
> - .pfn = __phys_to_pfn(EASI_START),
> - .length = EASI_SIZE,
> - .type = MT_DEVICE
> - }
> -};
> -
> -static void __init rpc_map_io(void)
> -{
> - iotable_init(rpc_io_desc, ARRAY_SIZE(rpc_io_desc));
> -
> - /*
> - * Turn off floppy.
> - */
> - writeb(0xc, PCIO_BASE + (0x3f2 << 2));
> -
> - /*
> - * RiscPC can't handle half-word loads and stores
> - */
> - elf_hwcap &= ~HWCAP_HALF;
> -}
> -
> -static struct resource acornfb_resources[] = {
> - /* VIDC */
> - DEFINE_RES_MEM(0x03400000, 0x00200000),
> - DEFINE_RES_IRQ(IRQ_VSYNCPULSE),
> -};
> -
> -static struct platform_device acornfb_device = {
> - .name = "acornfb",
> - .id = -1,
> - .dev = {
> - .coherent_dma_mask = 0xffffffff,
> - },
> - .num_resources = ARRAY_SIZE(acornfb_resources),
> - .resource = acornfb_resources,
> -};
> -
> -static struct resource iomd_resources[] = {
> - DEFINE_RES_MEM(0x03200000, 0x10000),
> -};
> -
> -static struct platform_device iomd_device = {
> - .name = "iomd",
> - .id = -1,
> - .num_resources = ARRAY_SIZE(iomd_resources),
> - .resource = iomd_resources,
> -};
> -
> -static struct resource iomd_kart_resources[] = {
> - DEFINE_RES_IRQ(IRQ_KEYBOARDRX),
> - DEFINE_RES_IRQ(IRQ_KEYBOARDTX),
> -};
> -
> -static struct platform_device kbd_device = {
> - .name = "kart",
> - .id = -1,
> - .dev = {
> - .parent = &iomd_device.dev,
> - },
> - .num_resources = ARRAY_SIZE(iomd_kart_resources),
> - .resource = iomd_kart_resources,
> -};
> -
> -static struct plat_serial8250_port serial_platform_data[] = {
> - {
> - .mapbase = 0x03010fe0,
> - .irq = IRQ_SERIALPORT,
> - .uartclk = 1843200,
> - .regshift = 2,
> - .iotype = UPIO_MEM,
> - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
> - },
> - { },
> -};
> -
> -static struct platform_device serial_device = {
> - .name = "serial8250",
> - .id = PLAT8250_DEV_PLATFORM,
> - .dev = {
> - .platform_data = serial_platform_data,
> - },
> -};
> -
> -static struct pata_platform_info pata_platform_data = {
> - .ioport_shift = 2,
> -};
> -
> -static struct resource pata_resources[] = {
> - DEFINE_RES_MEM(0x030107c0, 0x20),
> - DEFINE_RES_MEM(0x03010fd8, 0x04),
> - DEFINE_RES_IRQ(IRQ_HARDDISK),
> -};
> -
> -static struct platform_device pata_device = {
> - .name = "pata_platform",
> - .id = -1,
> - .num_resources = ARRAY_SIZE(pata_resources),
> - .resource = pata_resources,
> - .dev = {
> - .platform_data = &pata_platform_data,
> - .coherent_dma_mask = ~0, /* grumble */
> - },
> -};
> -
> -static struct platform_device *devs[] __initdata = {
> - &iomd_device,
> - &kbd_device,
> - &serial_device,
> - &acornfb_device,
> - &pata_device,
> -};
> -
> -static struct i2c_board_info i2c_rtc = {
> - I2C_BOARD_INFO("pcf8583", 0x50)
> -};
> -
> -static int __init rpc_init(void)
> -{
> - i2c_register_board_info(0, &i2c_rtc, 1);
> - return platform_add_devices(devs, ARRAY_SIZE(devs));
> -}
> -
> -arch_initcall(rpc_init);
> -
> -static void rpc_restart(enum reboot_mode mode, const char *cmd)
> -{
> - iomd_writeb(0, IOMD_ROMCR0);
> -
> - /*
> - * Jump into the ROM
> - */
> - soft_restart(0);
> -}
> -
> -void ioc_timer_init(void);
> -
> -MACHINE_START(RISCPC, "Acorn-RiscPC")
> - /* Maintainer: Russell King */
> - .atag_offset = 0x100,
> - .reserve_lp0 = 1,
> - .reserve_lp1 = 1,
> - .map_io = rpc_map_io,
> - .init_irq = rpc_init_irq,
> - .init_time = ioc_timer_init,
> - .restart = rpc_restart,
> -MACHINE_END
> diff --git a/arch/arm/mach-rpc/time.c b/arch/arm/mach-rpc/time.c
> deleted file mode 100644
> index 9f8edcfe9357..000000000000
> --- a/arch/arm/mach-rpc/time.c
> +++ /dev/null
> @@ -1,97 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * linux/arch/arm/common/time-acorn.c
> - *
> - * Copyright (c) 1996-2000 Russell King.
> - *
> - * Changelog:
> - * 24-Sep-1996 RMK Created
> - * 10-Oct-1996 RMK Brought up to date with arch-sa110eval
> - * 04-Dec-1997 RMK Updated for new arch/arm/time.c
> - * 13=Jun-2004 DS Moved to arch/arm/common b/c shared w/CLPS7500
> - */
> -#include <linux/clocksource.h>
> -#include <linux/init.h>
> -#include <linux/interrupt.h>
> -#include <linux/irq.h>
> -#include <linux/io.h>
> -
> -#include <mach/hardware.h>
> -#include <asm/hardware/ioc.h>
> -
> -#include <asm/mach/time.h>
> -
> -#define RPC_CLOCK_FREQ 2000000
> -#define RPC_LATCH DIV_ROUND_CLOSEST(RPC_CLOCK_FREQ, HZ)
> -
> -static u32 ioc_time;
> -
> -static u64 ioc_timer_read(struct clocksource *cs)
> -{
> - unsigned int count1, count2, status;
> - unsigned long flags;
> - u32 ticks;
> -
> - local_irq_save(flags);
> - ioc_writeb (0, IOC_T0LATCH);
> - barrier ();
> - count1 = ioc_readb(IOC_T0CNTL) | (ioc_readb(IOC_T0CNTH) << 8);
> - barrier ();
> - status = ioc_readb(IOC_IRQREQA);
> - barrier ();
> - ioc_writeb (0, IOC_T0LATCH);
> - barrier ();
> - count2 = ioc_readb(IOC_T0CNTL) | (ioc_readb(IOC_T0CNTH) << 8);
> - ticks = ioc_time + RPC_LATCH - count2;
> - local_irq_restore(flags);
> -
> - if (count2 < count1) {
> - /*
> - * The timer has not reloaded between reading count1 and
> - * count2, check whether an interrupt was actually pending.
> - */
> - if (status & (1 << 5))
> - ticks += RPC_LATCH;
> - } else if (count2 > count1) {
> - /*
> - * The timer has reloaded, so count2 indicates the new
> - * count since the wrap. The interrupt would not have
> - * been processed, so add the missed ticks.
> - */
> - ticks += RPC_LATCH;
> - }
> -
> - return ticks;
> -}
> -
> -static struct clocksource ioctime_clocksource = {
> - .read = ioc_timer_read,
> - .mask = CLOCKSOURCE_MASK(32),
> - .rating = 100,
> -};
> -
> -void __init ioctime_init(void)
> -{
> - ioc_writeb(RPC_LATCH & 255, IOC_T0LTCHL);
> - ioc_writeb(RPC_LATCH >> 8, IOC_T0LTCHH);
> - ioc_writeb(0, IOC_T0GO);
> -}
> -
> -static irqreturn_t
> -ioc_timer_interrupt(int irq, void *dev_id)
> -{
> - ioc_time += RPC_LATCH;
> - legacy_timer_tick(1);
> - return IRQ_HANDLED;
> -}
> -
> -/*
> - * Set up timer interrupt.
> - */
> -void __init ioc_timer_init(void)
> -{
> - WARN_ON(clocksource_register_hz(&ioctime_clocksource, RPC_CLOCK_FREQ));
> - ioctime_init();
> - if (request_irq(IRQ_TIMER0, ioc_timer_interrupt, 0, "timer", NULL))
> - pr_err("Failed to request irq %d (timer)\n", IRQ_TIMER0);
> -}
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index 350f6dcc24cc..07c2fda4d422 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -1112,7 +1112,7 @@ static void __init fill_pmd_gaps(void)
> #define fill_pmd_gaps() do { } while (0)
> #endif
>
> -#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
> +#if defined(CONFIG_PCI)
> static void __init pci_reserve_io(void)
> {
> struct static_vm *svm;
> diff --git a/block/partitions/Kconfig b/block/partitions/Kconfig
> index ce17e41451af..94e7df547e7a 100644
> --- a/block/partitions/Kconfig
> +++ b/block/partitions/Kconfig
> @@ -19,13 +19,11 @@ config PARTITION_ADVANCED
>
> config ACORN_PARTITION
> bool "Acorn partition support" if PARTITION_ADVANCED
> - default y if ARCH_ACORN
> help
> Support hard disks partitioned under Acorn operating systems.
>
> config ACORN_PARTITION_CUMANA
> bool "Cumana partition support" if PARTITION_ADVANCED
> - default y if ARCH_ACORN
> depends on ACORN_PARTITION
> help
> Say Y here if you would like to use hard disks under Linux which
> @@ -33,12 +31,10 @@ config ACORN_PARTITION_CUMANA
>
> config ACORN_PARTITION_EESOX
> bool "EESOX partition support" if PARTITION_ADVANCED
> - default y if ARCH_ACORN
> depends on ACORN_PARTITION
>
> config ACORN_PARTITION_ICS
> bool "ICS partition support" if PARTITION_ADVANCED
> - default y if ARCH_ACORN
> depends on ACORN_PARTITION
> help
> Say Y here if you would like to use hard disks under Linux which
> @@ -46,7 +42,6 @@ config ACORN_PARTITION_ICS
>
> config ACORN_PARTITION_ADFS
> bool "Native filecore partition support" if PARTITION_ADVANCED
> - default y if ARCH_ACORN
> depends on ACORN_PARTITION
> help
> The Acorn Disc Filing System is the standard file system of the
> @@ -56,7 +51,6 @@ config ACORN_PARTITION_ADFS
>
> config ACORN_PARTITION_POWERTEC
> bool "PowerTec partition support" if PARTITION_ADVANCED
> - default y if ARCH_ACORN
> depends on ACORN_PARTITION
> help
> Support reading partition tables created on Acorn machines using
> @@ -64,7 +58,6 @@ config ACORN_PARTITION_POWERTEC
>
> config ACORN_PARTITION_RISCIX
> bool "RISCiX partition support" if PARTITION_ADVANCED
> - default y if ARCH_ACORN
> depends on ACORN_PARTITION
> help
> Once upon a time, there was a native Unix port for the Acorn series
> diff --git a/drivers/tty/vt/keyboard.c b/drivers/tty/vt/keyboard.c
> index c41d850b29c6..9770c83aea74 100644
> --- a/drivers/tty/vt/keyboard.c
> +++ b/drivers/tty/vt/keyboard.c
> @@ -1308,7 +1308,7 @@ static void kbd_bh(struct tasklet_struct *unused)
> #if defined(CONFIG_X86) || defined(CONFIG_ALPHA) ||\
> defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_SPARC) ||\
> defined(CONFIG_PARISC) || defined(CONFIG_SUPERH) ||\
> - (defined(CONFIG_ARM) && defined(CONFIG_KEYBOARD_ATKBD) && !defined(CONFIG_ARCH_RPC))
> + (defined(CONFIG_ARM) && defined(CONFIG_KEYBOARD_ATKBD))
>
> static inline bool kbd_is_hw_raw(const struct input_dev *dev)
> {
> diff --git a/lib/fonts/font_acorn_8x8.c b/lib/fonts/font_acorn_8x8.c
> index 4ff52c79f8c4..ec2b1e463ab9 100644
> --- a/lib/fonts/font_acorn_8x8.c
> +++ b/lib/fonts/font_acorn_8x8.c
> @@ -277,9 +277,5 @@ const struct font_desc font_acorn_8x8 = {
> .height = 8,
> .charcount = 256,
> .data = acorndata_8x8.data,
> -#ifdef CONFIG_ARCH_ACORN
> - .pref = 20,
> -#else
> .pref = 0,
> -#endif
> };
--
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstr. 146, 90461 Nürnberg, Germany, www.suse.com
GF: Jochen Jaser, Andrew McDonald, (HRB 36809, AG Nürnberg)
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 03/13] ARM: remove riscpc
2026-09-08 15:27 ` [PATCH 03/13] ARM: remove riscpc Arnd Bergmann
2026-09-09 8:04 ` Thomas Zimmermann
@ 2026-09-09 16:42 ` Bart Van Assche
2026-09-09 20:09 ` Arnd Bergmann
1 sibling, 1 reply; 70+ messages in thread
From: Bart Van Assche @ 2026-09-09 16:42 UTC (permalink / raw)
To: Arnd Bergmann, Krzysztof Kozlowski, Alexandre Belloni,
Linus Walleij, Russell King
Cc: linux-doc, linux-kernel, linux-arm-kernel, devicetree, imx,
linux-stm32, linux-omap, linux-block, linux-serial, linux-fbdev
On 9/8/26 8:27 AM, Arnd Bergmann wrote:
> The Acorn Risc PC is the oldest still support Arm machine in the kernel,
> originally shipped with an ARMv3 ARM610 support in 1994, it later allowed
> faster StrongARM CPUs.
>
> The main limitation here is the CPU bus that does not allow 16-bit
> wide data transfers and hence requires the kernel to be built with the
> -march=armv3 compiler option that was discontinued in gcc-9.
>
> As gcc-8 is barely supported for compiling the kernel, this one
> will not see another LTS kernel release, so remove it now.
If this patch has to be reposted, here is the feedback of my AI coding
assistant (based on an LLM and hence may be wrong):
----------------------------------------------------------------------
Overview
--------
This patch removes the Acorn RiscPC platform (ARCH_RPC), the oldest
32-bit ARM machine supported in mainline Linux (originally ARMv3 ARM610,
later StrongARM SA-110). Because RiscPC hardware requires -march=armv3
(discontinued in GCC 9) due to bus limitations, deprecating and removing
it paves the way to clean out legacy ARMv3 support from the kernel.
Removing RiscPC also represents a major architectural milestone for
arch/arm: with SA-1100 (patch 1), Footbridge (patch 2), and RiscPC
(patch 3) removed, COMMON_CLK, SPARSE_IRQ, and USE_OF (Device Tree)
become unconditionally selected for all 32-bit ARM targets, and legacy
headers mach/io.h and mach/memory.h are eliminated.
Overall, this is a very welcome cleanup, but there are a few missed
references, orphaned symbols, and stale comments that should be addressed.
Issues & Observations
---------------------
1. Missed arch/arm/Makefile cleanup
Patch 03 deletes the entire directory arch/arm/mach-rpc/, but does not
touch arch/arm/Makefile. As a result, two orphaned entries remain:
makefile
machine-$(CONFIG_ARCH_RPC) += rpc
machdirs-$(CONFIG_ARCH_RPC) += arch/arm/mach-rpc
Furthermore, machdirs-$(CONFIG_ARCH_RPC) was the very last user of
machdirs- in arch/arm/Makefile (after Footbridge and SA-1100 are removed
in patches 1 & 2):
makefile
# legacy platforms provide their own mach/*.h headers globally,
# these three are mutually exclusive
machdirs-$(CONFIG_ARCH_FOOTBRIDGE) += arch/arm/mach-footbridge
machdirs-$(CONFIG_ARCH_RPC) += arch/arm/mach-rpc
machdirs-$(CONFIG_ARCH_SA1100) += arch/arm/mach-sa1100
KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%/include,$(machdirs-y))
Once RiscPC is gone, the entire machdirs- inclusion block can and should
be removed from arch/arm/Makefile.
2. Missed ARCH_ACORN reference in lib/fonts/Kconfig
The patch deletes config ARCH_ACORN from arch/arm/Kconfig and removes
#ifdef CONFIG_ARCH_ACORN from
lib/fonts/font_acorn_8x8.c
, but missed
lib/fonts/Kconfig:74
:
kconfig
config FONT_ACORN_8x8
bool "Acorn console 8x8 font" if FONTS
depends on FRAMEBUFFER_CONSOLE || DRM_PANIC
default y if !SPARC && !FONTS && ARM && ARCH_ACORN
Because ARCH_ACORN is removed, this default can never trigger and the
reference should be cleaned up.
3. Orphaned ARCH_RPC reference in arch/arm/mm/Kconfig
In
arch/arm/mm/Kconfig:281-282
:
kconfig
config CPU_SA110
bool
select CPU_32v3 if ARCH_RPC
select CPU_32v4 if !ARCH_RPC
Since ARCH_RPC is removed, select CPU_32v3 if ARCH_RPC references a
non-existent symbol. If CPU_SA110 remains temporarily (before the
architectural cleanup in 7.5), this should be simplified to select CPU_32v4.
4. Dead code in arch/arm/kernel/atags_compat.c
With CONFIG_ARCH_ACORN removed from arch/arm/Kconfig, two blocks in
arch/arm/kernel/atags_compat.c
are now dead code:
Lines 150–157: #ifdef CONFIG_ARCH_ACORN / if (machine_is_riscpc())
memory bank tagging.
Lines 186–194: #ifdef CONFIG_ARCH_ACORN ATAG_ACORN translation.
These blocks should be removed as part of this patch.
5. Stale comments
arch/arm/include/asm/io.h:207-209
:
c
/*
* Now, pick up the machine-defined IO definitions
*/
#if IS_ENABLED(CONFIG_PCMCIA) || defined(CONFIG_PCI)
CONFIG_NEED_MACH_IO_H and #include <mach/io.h> were removed, leaving
this comment describing generic PCI/PCMCIA I/O limits.
arch/arm/boot/bootp/Makefile:21
: # guess an initrd location if possible is left dangling right before
ifdef INITRD_OFFSET after all initrd_offset-$(CONFIG_...) logic has been
stripped out.
6. Floppy driver & arch/arm/include/asm/floppy.h status
The patch removes the ARM MFM AND FLOPPY DRIVERS entry from MAINTAINERS:
diff
-ARM MFM AND FLOPPY DRIVERS
-M: Ian Molton <spyro@f2s.com>
-S: Maintained
-F: arch/arm/include/asm/floppy.h
-F: arch/arm/mach-rpc/floppydma.S
While
floppydma.S
was deleted,
arch/arm/include/asm/floppy.h
was left in the tree.
On ARM, floppy support requires ARCH_MAY_HAVE_PC_FDC, which was selected
only by Footbridge and RiscPC.
With both gone, no ARM board selects ARCH_MAY_HAVE_PC_FDC.
Furthermore, asm/floppy.h references IRQ_FLOPPYDISK and DMA_FLOPPY,
which no longer exist on ARM.
Either
arch/arm/include/asm/floppy.h
and config ARCH_MAY_HAVE_PC_FDC in arch/arm/Kconfig should be deleted
in this patch, or noted if intentionally deferred to the 7.5 driver cleanup.
7. Good changes & verification
block/partitions/Kconfig: Dropping default y if ARCH_ACORN while keeping
ACORN_PARTITION available under PARTITION_ADVANCED is correct; users can
still inspect/mount Acorn media on modern architectures.
drivers/tty/vt/keyboard.c: Clean removal of !defined(CONFIG_ARCH_RPC)
from the raw keyboard scan handler.
Elimination of NEED_MACH_IO_H and NEED_MACH_MEMORY_H: Very clean removal
across arch/arm/Kconfig, arch/arm/include/asm/io.h,
arch/arm/include/asm/memory.h, and arch/arm/mm/mmu.c.
Minor Typo in Commit Message
text
The Acorn Risc PC is the oldest still support Arm machine in the kernel,
originally shipped with an ARMv3 ARM610 support in 1994, it later allowed
faster StrongARM CPUs.
"oldest still support Arm machine" -> "oldest still supported Arm machine"
"with an ARMv3 ARM610 support" -> "with ARMv3 ARM610 support" or "with
an ARMv3 ARM610 CPU"
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 03/13] ARM: remove riscpc
2026-09-09 16:42 ` Bart Van Assche
@ 2026-09-09 20:09 ` Arnd Bergmann
0 siblings, 0 replies; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-09 20:09 UTC (permalink / raw)
To: Bart Van Assche, Krzysztof Kozlowski, Alexandre Belloni,
Linus Walleij, Russell King
Cc: linux-doc, linux-kernel, linux-arm-kernel, devicetree, imx,
linux-stm32, Linux-OMAP, linux-block, linux-serial, linux-fbdev
On Wed, Sep 9, 2026, at 18:42, Bart Van Assche wrote:
> On 9/8/26 8:27 AM, Arnd Bergmann wrote:
>> The Acorn Risc PC is the oldest still support Arm machine in the kernel,
>> originally shipped with an ARMv3 ARM610 support in 1994, it later allowed
>> faster StrongARM CPUs.
>>
>> The main limitation here is the CPU bus that does not allow 16-bit
>> wide data transfers and hence requires the kernel to be built with the
>> -march=armv3 compiler option that was discontinued in gcc-9.
>>
>> As gcc-8 is barely supported for compiling the kernel, this one
>> will not see another LTS kernel release, so remove it now.
>
> If this patch has to be reposted, here is the feedback of my AI coding
> assistant (based on an LLM and hence may be wrong):
Most of this was already discussed, but there are two additional
changes that I made based on it.
> Issues & Observations
> ---------------------
> 1. Missed arch/arm/Makefile cleanup
> Patch 03 deletes the entire directory arch/arm/mach-rpc/, but does not
> touch arch/arm/Makefile. As a result, two orphaned entries remain:
>
> machine-$(CONFIG_ARCH_RPC) += rpc
> machdirs-$(CONFIG_ARCH_RPC) += arch/arm/mach-rpc
> Furthermore, machdirs-$(CONFIG_ARCH_RPC) was the very last user of
> machdirs- in arch/arm/Makefile (after Footbridge and SA-1100 are removed
> in patches 1 & 2):
Fixed already after sashiko-bot found the same thing.
> kconfig
>
>
> config FONT_ACORN_8x8
> bool "Acorn console 8x8 font" if FONTS
> depends on FRAMEBUFFER_CONSOLE || DRM_PANIC
> default y if !SPARC && !FONTS && ARM && ARCH_ACORN
> Because ARCH_ACORN is removed, this default can never trigger and the
> reference should be cleaned up.
I have this in the patch that removes acornfb. It could go into
either one, but I felt it fits better there
> kconfig
>
>
> config CPU_SA110
> bool
> select CPU_32v3 if ARCH_RPC
> select CPU_32v4 if !ARCH_RPC
> Since ARCH_RPC is removed, select CPU_32v3 if ARCH_RPC references a
> non-existent symbol. If CPU_SA110 remains temporarily (before the
> architectural cleanup in 7.5), this should be simplified to select CPU_32v4.
Also explained already that I preferred removing CPU_32v3 along
with CPU_SA110 in a later patch, not together with ARCH_RPC.
> 4. Dead code in arch/arm/kernel/atags_compat.c
> With CONFIG_ARCH_ACORN removed from arch/arm/Kconfig, two blocks in
> arch/arm/kernel/atags_compat.c
> are now dead code:
>
> Lines 150–157: #ifdef CONFIG_ARCH_ACORN / if (machine_is_riscpc())
> memory bank tagging.
> Lines 186–194: #ifdef CONFIG_ARCH_ACORN ATAG_ACORN translation.
> These blocks should be removed as part of this patch.
I have a patch to remove that file.
>
> /*
> * Now, pick up the machine-defined IO definitions
> */
> #if IS_ENABLED(CONFIG_PCMCIA) || defined(CONFIG_PCI)
> CONFIG_NEED_MACH_IO_H and #include <mach/io.h> were removed, leaving
> this comment describing generic PCI/PCMCIA I/O limits.
Fixed now.
> arch/arm/boot/bootp/Makefile:21
> : # guess an initrd location if possible is left dangling right before
> ifdef INITRD_OFFSET after all initrd_offset-$(CONFIG_...) logic has been
> stripped out.
Removed that entire block now:
--- a/arch/arm/boot/bootp/Makefile
+++ b/arch/arm/boot/bootp/Makefile
@@ -17,12 +17,6 @@ add_hex = $(shell printf 0x%x $$(( $(1) + $(2) )) )
# INITRD_PHYS must be in RAM
PARAMS_PHYS := $(call add_hex, $(PHYS_OFFSET), 0x100)
-
-# guess an initrd location if possible
-ifdef INITRD_OFFSET
-INITRD_PHYS := $(call add_hex, $(PHYS_OFFSET), $(INITRD_OFFSET))
-endif
-
endif
PHONY += initrd
@@ -30,7 +24,7 @@ initrd:
@test "$(PARAMS_PHYS)" != "" || \
(echo bootpImage: You must specify PHYS_OFFSET of PARAMS_PHYS ; exit -1)
@test "$(INITRD_PHYS)" != "" || \
- (echo bootpImage: You must specify INITRD_OFFSET or INITRD_PHYS ; exit -1)
+ (echo bootpImage: You must specify INITRD_PHYS ; exit -1)
@test "$(INITRD)" != "" || \
(echo bootpImage: You must specify INITRD; exit -1)
> 6. Floppy driver & arch/arm/include/asm/floppy.h status
> The patch removes the ARM MFM AND FLOPPY DRIVERS entry from MAINTAINERS:
commented already that this is removed along with CONFIG_ISA in a later
patch.
Arnd
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH 04/13] ARM: remove legacy pxa board files
2026-09-08 15:27 [PATCH 00/13] ARM: deprecated platform removal Arnd Bergmann
` (2 preceding siblings ...)
2026-09-08 15:27 ` [PATCH 03/13] ARM: remove riscpc Arnd Bergmann
@ 2026-09-08 15:27 ` Arnd Bergmann
2026-09-08 17:30 ` Linus Walleij
2026-09-08 18:32 ` Daniel Mack
2026-09-08 15:27 ` [PATCH 05/13] ARM: orion/dove/mv78xx0: remove all " Arnd Bergmann
` (9 subsequent siblings)
13 siblings, 2 replies; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 15:27 UTC (permalink / raw)
To: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Daniel Mack,
Haojian Zhuang, Bartosz Golaszewski
From: Arnd Bergmann <arnd@arndb.de>
The PXA platform supports devicetree based booting, but still has a
few traditional board files, which were left as a starting point for a
possible conversion to devicetree during the last mass purge of board
files in 2022.
None of these boards were actually converted, so drop support for these
now, along with the 'scoop' support chip that was used on some PDAs that
are no longer usable now.
The only remaining board support is for the "Raumfeld" speaker system
based on PXA300 SoC, though basic support for PXA250 and PXA270 is still
there and may work with external dts files.
Cc: Daniel Mack <daniel@zonque.org>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Linus Walleij <linusw@kernel.org>
Cc: Bartosz Golaszewski <brgl@kernel.org>
Cc: Ethan Nelson-Moore <enelsonmoore@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/boot/compressed/Makefile | 4 -
arch/arm/boot/compressed/head-sharpsl.S | 151 ---
arch/arm/common/Kconfig | 6 -
arch/arm/common/Makefile | 2 -
arch/arm/common/scoop.c | 269 -----
arch/arm/common/sharpsl_param.c | 63 --
arch/arm/configs/am200epdkit_defconfig | 91 --
arch/arm/configs/spitz_defconfig | 237 -----
arch/arm/include/asm/hardware/scoop.h | 67 --
arch/arm/include/asm/mach/sharpsl_param.h | 33 -
arch/arm/mach-pxa/Kconfig | 89 --
arch/arm/mach-pxa/Makefile | 8 -
arch/arm/mach-pxa/am200epd.c | 395 -------
arch/arm/mach-pxa/am300epd.c | 296 ------
arch/arm/mach-pxa/devices.c | 705 -------------
arch/arm/mach-pxa/devices.h | 68 --
arch/arm/mach-pxa/generic.h | 5 -
arch/arm/mach-pxa/gumstix.c | 237 -----
arch/arm/mach-pxa/gumstix.h | 89 --
arch/arm/mach-pxa/pxa25x.c | 59 --
arch/arm/mach-pxa/pxa27x.c | 77 --
arch/arm/mach-pxa/pxa300.c | 1 -
arch/arm/mach-pxa/pxa320.c | 1 -
arch/arm/mach-pxa/pxa3xx.c | 6 -
arch/arm/mach-pxa/sharpsl_pm.c | 941 -----------------
arch/arm/mach-pxa/sharpsl_pm.h | 108 --
arch/arm/mach-pxa/spitz.c | 1174 ---------------------
arch/arm/mach-pxa/spitz.h | 185 ----
arch/arm/mach-pxa/spitz_pm.c | 257 -----
29 files changed, 5624 deletions(-)
delete mode 100644 arch/arm/boot/compressed/head-sharpsl.S
delete mode 100644 arch/arm/common/scoop.c
delete mode 100644 arch/arm/common/sharpsl_param.c
delete mode 100644 arch/arm/configs/am200epdkit_defconfig
delete mode 100644 arch/arm/configs/spitz_defconfig
delete mode 100644 arch/arm/include/asm/hardware/scoop.h
delete mode 100644 arch/arm/include/asm/mach/sharpsl_param.h
delete mode 100644 arch/arm/mach-pxa/am200epd.c
delete mode 100644 arch/arm/mach-pxa/am300epd.c
delete mode 100644 arch/arm/mach-pxa/devices.h
delete mode 100644 arch/arm/mach-pxa/gumstix.c
delete mode 100644 arch/arm/mach-pxa/gumstix.h
delete mode 100644 arch/arm/mach-pxa/sharpsl_pm.c
delete mode 100644 arch/arm/mach-pxa/sharpsl_pm.h
delete mode 100644 arch/arm/mach-pxa/spitz.c
delete mode 100644 arch/arm/mach-pxa/spitz.h
delete mode 100644 arch/arm/mach-pxa/spitz_pm.c
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 32def10f5e03..232b646bfd26 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -29,10 +29,6 @@ ifeq ($(CONFIG_CPU_XSCALE),y)
OBJS += head-xscale.o
endif
-ifeq ($(CONFIG_PXA_SHARPSL_DETECT_MACH_ID),y)
-OBJS += head-sharpsl.o
-endif
-
ifeq ($(CONFIG_CPU_ENDIAN_BE32),y)
ifeq ($(CONFIG_CPU_CP15),y)
OBJS += big-endian.o
diff --git a/arch/arm/boot/compressed/head-sharpsl.S b/arch/arm/boot/compressed/head-sharpsl.S
deleted file mode 100644
index 992e784500fa..000000000000
--- a/arch/arm/boot/compressed/head-sharpsl.S
+++ /dev/null
@@ -1,151 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/arm/boot/compressed/head-sharpsl.S
- *
- * Copyright (C) 2004-2005 Richard Purdie <rpurdie@rpsys.net>
- *
- * Sharp's bootloader doesn't pass any kind of machine ID
- * so we have to figure out the machine for ourselves...
- *
- * Support for Poodle, Corgi (SL-C700), Shepherd (SL-C750)
- * Husky (SL-C760), Tosa (SL-C6000), Spitz (SL-C3000),
- * Akita (SL-C1000) and Borzoi (SL-C3100).
- *
- */
-
-#include <linux/linkage.h>
-#include <asm/mach-types.h>
-
-#ifndef CONFIG_PXA_SHARPSL
-#error What am I doing here...
-#endif
-
- .section ".start", "ax"
-
-__SharpSL_start:
-
-/* Check for TC6393 - if found we have a Tosa */
- ldr r7, .TOSAID
- mov r1, #0x10000000 @ Base address of TC6393 chip
- mov r6, #0x03
- ldrh r3, [r1, #8] @ Load TC6393XB Revison: This is 0x0003
- cmp r6, r3
- beq .SHARPEND @ Success -> tosa
-
-/* Check for pxa270 - if found, branch */
- mrc p15, 0, r4, c0, c0 @ Get Processor ID
- and r4, r4, #0xffffff00
- ldr r3, .PXA270ID
- cmp r4, r3
- beq .PXA270
-
-/* Check for w100 - if not found we have a Poodle */
- ldr r1, .W100ADDR @ Base address of w100 chip + regs offset
-
- mov r6, #0x31 @ Load Magic Init value
- str r6, [r1, #0x280] @ to SCRATCH_UMSK
- mov r5, #0x3000
-.W100LOOP:
- subs r5, r5, #1
- bne .W100LOOP
- mov r6, #0x30 @ Load 2nd Magic Init value
- str r6, [r1, #0x280] @ to SCRATCH_UMSK
-
- ldr r6, [r1, #0] @ Load Chip ID
- ldr r3, .W100ID
- ldr r7, .POODLEID
- cmp r6, r3
- bne .SHARPEND @ We have no w100 - Poodle
-
-/* Check for pxa250 - if found we have a Corgi */
- ldr r7, .CORGIID
- ldr r3, .PXA255ID
- cmp r4, r3
- blo .SHARPEND @ We have a PXA250 - Corgi
-
-/* Check for 64MiB flash - if found we have a Shepherd */
- bl get_flash_ids
- ldr r7, .SHEPHERDID
- cmp r3, #0x76 @ 64MiB flash
- beq .SHARPEND @ We have Shepherd
-
-/* Must be a Husky */
- ldr r7, .HUSKYID @ Must be Husky
- b .SHARPEND
-
-.PXA270:
-/* Check for 16MiB flash - if found we have Spitz */
- bl get_flash_ids
- ldr r7, .SPITZID
- cmp r3, #0x73 @ 16MiB flash
- beq .SHARPEND @ We have Spitz
-
-/* Check for a second SCOOP chip - if found we have Borzoi */
- ldr r1, .SCOOP2ADDR
- ldr r7, .BORZOIID
- mov r6, #0x0140
- strh r6, [r1]
- ldrh r6, [r1]
- cmp r6, #0x0140
- beq .SHARPEND @ We have Borzoi
-
-/* Must be Akita */
- ldr r7, .AKITAID
- b .SHARPEND @ We have Borzoi
-
-.PXA255ID:
- .word 0x69052d00 @ PXA255 Processor ID
-.PXA270ID:
- .word 0x69054100 @ PXA270 Processor ID
-.W100ID:
- .word 0x57411002 @ w100 Chip ID
-.W100ADDR:
- .word 0x08010000 @ w100 Chip ID Reg Address
-.SCOOP2ADDR:
- .word 0x08800040
-.POODLEID:
- .word MACH_TYPE_POODLE
-.CORGIID:
- .word MACH_TYPE_CORGI
-.SHEPHERDID:
- .word MACH_TYPE_SHEPHERD
-.HUSKYID:
- .word MACH_TYPE_HUSKY
-.TOSAID:
- .word MACH_TYPE_TOSA
-.SPITZID:
- .word MACH_TYPE_SPITZ
-.AKITAID:
- .word MACH_TYPE_AKITA
-.BORZOIID:
- .word MACH_TYPE_BORZOI
-
-/*
- * Return: r2 - NAND Manufacturer ID
- * r3 - NAND Chip ID
- * Corrupts: r1
- */
-get_flash_ids:
- mov r1, #0x0c000000 @ Base address of NAND chip
- ldrb r3, [r1, #24] @ Load FLASHCTL
- bic r3, r3, #0x11 @ SET NCE
- orr r3, r3, #0x0a @ SET CLR + FLWP
- strb r3, [r1, #24] @ Save to FLASHCTL
- mov r2, #0x90 @ Command "readid"
- strb r2, [r1, #20] @ Save to FLASHIO
- bic r3, r3, #2 @ CLR CLE
- orr r3, r3, #4 @ SET ALE
- strb r3, [r1, #24] @ Save to FLASHCTL
- mov r2, #0 @ Address 0x00
- strb r2, [r1, #20] @ Save to FLASHIO
- bic r3, r3, #4 @ CLR ALE
- strb r3, [r1, #24] @ Save to FLASHCTL
-.fids1:
- ldrb r3, [r1, #24] @ Load FLASHCTL
- tst r3, #32 @ Is chip ready?
- beq .fids1
- ldrb r2, [r1, #20] @ NAND Manufacturer ID
- ldrb r3, [r1, #20] @ NAND Chip ID
- mov pc, lr
-
-.SHARPEND:
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index d72dccf6f3c2..cf75be68d05c 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -1,9 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
config KRAIT_L2_ACCESSORS
bool
-
-config SHARP_PARAM
- bool
-
-config SHARP_SCOOP
- bool
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index e1bcc250874f..1935b23700b0 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -6,8 +6,6 @@
obj-y += firmware.o
obj-$(CONFIG_KRAIT_L2_ACCESSORS) += krait-l2-accessors.o
-obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
-obj-$(CONFIG_SHARP_SCOOP) += scoop.o
obj-$(CONFIG_CPU_V7) += secure_cntvoff.o
obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
CFLAGS_REMOVE_mcpm_entry.o = -pg
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c
deleted file mode 100644
index 90474994757c..000000000000
--- a/arch/arm/common/scoop.c
+++ /dev/null
@@ -1,269 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Support code for the SCOOP interface found on various Sharp PDAs
- *
- * Copyright (c) 2004 Richard Purdie
- *
- * Based on code written by Sharp/Lineo for 2.4 kernels
- */
-
-#include <linux/device.h>
-#include <linux/gpio/driver.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-#include <linux/export.h>
-#include <linux/io.h>
-#include <asm/hardware/scoop.h>
-
-/* PCMCIA to Scoop linkage
-
- There is no easy way to link multiple scoop devices into one
- single entity for the pxa2xx_pcmcia device so this structure
- is used which is setup by the platform code.
-
- This file is never modular so this symbol is always
- accessile to the board support files.
-*/
-struct scoop_pcmcia_config *platform_scoop_config;
-EXPORT_SYMBOL(platform_scoop_config);
-
-struct scoop_dev {
- void __iomem *base;
- struct gpio_chip gpio;
- spinlock_t scoop_lock;
- unsigned short suspend_clr;
- unsigned short suspend_set;
- u32 scoop_gpwr;
-};
-
-void reset_scoop(struct device *dev)
-{
- struct scoop_dev *sdev = dev_get_drvdata(dev);
-
- iowrite16(0x0100, sdev->base + SCOOP_MCR); /* 00 */
- iowrite16(0x0000, sdev->base + SCOOP_CDR); /* 04 */
- iowrite16(0x0000, sdev->base + SCOOP_CCR); /* 10 */
- iowrite16(0x0000, sdev->base + SCOOP_IMR); /* 18 */
- iowrite16(0x00FF, sdev->base + SCOOP_IRM); /* 14 */
- iowrite16(0x0000, sdev->base + SCOOP_ISR); /* 1C */
- iowrite16(0x0000, sdev->base + SCOOP_IRM);
-}
-
-static void __scoop_gpio_set(struct scoop_dev *sdev,
- unsigned offset, int value)
-{
- unsigned short gpwr;
-
- gpwr = ioread16(sdev->base + SCOOP_GPWR);
- if (value)
- gpwr |= 1 << (offset + 1);
- else
- gpwr &= ~(1 << (offset + 1));
- iowrite16(gpwr, sdev->base + SCOOP_GPWR);
-}
-
-static int scoop_gpio_set(struct gpio_chip *chip, unsigned int offset,
- int value)
-{
- struct scoop_dev *sdev = gpiochip_get_data(chip);
- unsigned long flags;
-
- spin_lock_irqsave(&sdev->scoop_lock, flags);
-
- __scoop_gpio_set(sdev, offset, value);
-
- spin_unlock_irqrestore(&sdev->scoop_lock, flags);
-
- return 0;
-}
-
-static int scoop_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
- struct scoop_dev *sdev = gpiochip_get_data(chip);
-
- /* XXX: I'm unsure, but it seems so */
- return !!(ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1)));
-}
-
-static int scoop_gpio_direction_input(struct gpio_chip *chip,
- unsigned offset)
-{
- struct scoop_dev *sdev = gpiochip_get_data(chip);
- unsigned long flags;
- unsigned short gpcr;
-
- spin_lock_irqsave(&sdev->scoop_lock, flags);
-
- gpcr = ioread16(sdev->base + SCOOP_GPCR);
- gpcr &= ~(1 << (offset + 1));
- iowrite16(gpcr, sdev->base + SCOOP_GPCR);
-
- spin_unlock_irqrestore(&sdev->scoop_lock, flags);
-
- return 0;
-}
-
-static int scoop_gpio_direction_output(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- struct scoop_dev *sdev = gpiochip_get_data(chip);
- unsigned long flags;
- unsigned short gpcr;
-
- spin_lock_irqsave(&sdev->scoop_lock, flags);
-
- __scoop_gpio_set(sdev, offset, value);
-
- gpcr = ioread16(sdev->base + SCOOP_GPCR);
- gpcr |= 1 << (offset + 1);
- iowrite16(gpcr, sdev->base + SCOOP_GPCR);
-
- spin_unlock_irqrestore(&sdev->scoop_lock, flags);
-
- return 0;
-}
-
-unsigned short read_scoop_reg(struct device *dev, unsigned short reg)
-{
- struct scoop_dev *sdev = dev_get_drvdata(dev);
- return ioread16(sdev->base + reg);
-}
-
-void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data)
-{
- struct scoop_dev *sdev = dev_get_drvdata(dev);
- iowrite16(data, sdev->base + reg);
-}
-
-EXPORT_SYMBOL(reset_scoop);
-EXPORT_SYMBOL(read_scoop_reg);
-EXPORT_SYMBOL(write_scoop_reg);
-
-#ifdef CONFIG_PM
-static void check_scoop_reg(struct scoop_dev *sdev)
-{
- unsigned short mcr;
-
- mcr = ioread16(sdev->base + SCOOP_MCR);
- if ((mcr & 0x100) == 0)
- iowrite16(0x0101, sdev->base + SCOOP_MCR);
-}
-
-static int scoop_suspend(struct platform_device *dev, pm_message_t state)
-{
- struct scoop_dev *sdev = platform_get_drvdata(dev);
-
- check_scoop_reg(sdev);
- sdev->scoop_gpwr = ioread16(sdev->base + SCOOP_GPWR);
- iowrite16((sdev->scoop_gpwr & ~sdev->suspend_clr) | sdev->suspend_set, sdev->base + SCOOP_GPWR);
-
- return 0;
-}
-
-static int scoop_resume(struct platform_device *dev)
-{
- struct scoop_dev *sdev = platform_get_drvdata(dev);
-
- check_scoop_reg(sdev);
- iowrite16(sdev->scoop_gpwr, sdev->base + SCOOP_GPWR);
-
- return 0;
-}
-#else
-#define scoop_suspend NULL
-#define scoop_resume NULL
-#endif
-
-static int scoop_probe(struct platform_device *pdev)
-{
- struct scoop_dev *devptr;
- struct scoop_config *inf;
- struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- int ret;
-
- if (!mem)
- return -EINVAL;
-
- devptr = kzalloc_obj(struct scoop_dev);
- if (!devptr)
- return -ENOMEM;
-
- spin_lock_init(&devptr->scoop_lock);
-
- inf = pdev->dev.platform_data;
- devptr->base = ioremap(mem->start, resource_size(mem));
-
- if (!devptr->base) {
- ret = -ENOMEM;
- goto err_ioremap;
- }
-
- platform_set_drvdata(pdev, devptr);
-
- printk("Sharp Scoop Device found at 0x%08x -> 0x%8p\n",(unsigned int)mem->start, devptr->base);
-
- iowrite16(0x0140, devptr->base + SCOOP_MCR);
- reset_scoop(&pdev->dev);
- iowrite16(0x0000, devptr->base + SCOOP_CPR);
- iowrite16(inf->io_dir & 0xffff, devptr->base + SCOOP_GPCR);
- iowrite16(inf->io_out & 0xffff, devptr->base + SCOOP_GPWR);
-
- devptr->suspend_clr = inf->suspend_clr;
- devptr->suspend_set = inf->suspend_set;
-
- devptr->gpio.base = -1;
-
- if (inf->gpio_base != 0) {
- devptr->gpio.label = dev_name(&pdev->dev);
- devptr->gpio.base = inf->gpio_base;
- devptr->gpio.ngpio = 12; /* PA11 = 0, PA12 = 1, etc. up to PA22 = 11 */
- devptr->gpio.set = scoop_gpio_set;
- devptr->gpio.get = scoop_gpio_get;
- devptr->gpio.direction_input = scoop_gpio_direction_input;
- devptr->gpio.direction_output = scoop_gpio_direction_output;
-
- ret = gpiochip_add_data(&devptr->gpio, devptr);
- if (ret)
- goto err_gpio;
- }
-
- return 0;
-
-err_gpio:
- platform_set_drvdata(pdev, NULL);
-err_ioremap:
- iounmap(devptr->base);
- kfree(devptr);
-
- return ret;
-}
-
-static void scoop_remove(struct platform_device *pdev)
-{
- struct scoop_dev *sdev = platform_get_drvdata(pdev);
-
- if (sdev->gpio.base != -1)
- gpiochip_remove(&sdev->gpio);
-
- platform_set_drvdata(pdev, NULL);
- iounmap(sdev->base);
- kfree(sdev);
-}
-
-static struct platform_driver scoop_driver = {
- .probe = scoop_probe,
- .remove = scoop_remove,
- .suspend = scoop_suspend,
- .resume = scoop_resume,
- .driver = {
- .name = "sharp-scoop",
- },
-};
-
-static int __init scoop_init(void)
-{
- return platform_driver_register(&scoop_driver);
-}
-
-subsys_initcall(scoop_init);
diff --git a/arch/arm/common/sharpsl_param.c b/arch/arm/common/sharpsl_param.c
deleted file mode 100644
index 1ca26c063f80..000000000000
--- a/arch/arm/common/sharpsl_param.c
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Hardware parameter area specific to Sharp SL series devices
- *
- * Copyright (c) 2005 Richard Purdie
- *
- * Based on Sharp's 2.4 kernel patches
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <asm/mach/sharpsl_param.h>
-#include <asm/page.h>
-
-/*
- * Certain hardware parameters determined at the time of device manufacture,
- * typically including LCD parameters are loaded by the bootloader at the
- * address PARAM_BASE. As the kernel will overwrite them, we need to store
- * them early in the boot process, then pass them to the appropriate drivers.
- * Not all devices use all parameters but the format is common to all.
- */
-#ifdef CONFIG_ARCH_SA1100
-#define PARAM_BASE 0xe8ffc000
-#define param_start(x) (void *)(x)
-#else
-#define PARAM_BASE 0xa0000a00
-#define param_start(x) __va(x)
-#endif
-#define MAGIC_CHG(a,b,c,d) ( ( d << 24 ) | ( c << 16 ) | ( b << 8 ) | a )
-
-#define COMADJ_MAGIC MAGIC_CHG('C','M','A','D')
-#define UUID_MAGIC MAGIC_CHG('U','U','I','D')
-#define TOUCH_MAGIC MAGIC_CHG('T','U','C','H')
-#define AD_MAGIC MAGIC_CHG('B','V','A','D')
-#define PHAD_MAGIC MAGIC_CHG('P','H','A','D')
-
-struct sharpsl_param_info sharpsl_param;
-EXPORT_SYMBOL(sharpsl_param);
-
-void sharpsl_save_param(void)
-{
- struct sharpsl_param_info *params = param_start(PARAM_BASE);
-
- memcpy(&sharpsl_param, params, sizeof(*params));
-
- if (sharpsl_param.comadj_keyword != COMADJ_MAGIC)
- sharpsl_param.comadj=-1;
-
- if (sharpsl_param.phad_keyword != PHAD_MAGIC)
- sharpsl_param.phadadj=-1;
-
- if (sharpsl_param.uuid_keyword != UUID_MAGIC)
- sharpsl_param.uuid[0]=-1;
-
- if (sharpsl_param.touch_keyword != TOUCH_MAGIC)
- sharpsl_param.touch_xp=-1;
-
- if (sharpsl_param.adadj_keyword != AD_MAGIC)
- sharpsl_param.adadj=-1;
-}
-
-
diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig
deleted file mode 100644
index 61beac88e863..000000000000
--- a/arch/arm/configs/am200epdkit_defconfig
+++ /dev/null
@@ -1,91 +0,0 @@
-CONFIG_LOCALVERSION="gum"
-CONFIG_SYSVIPC=y
-CONFIG_PREEMPT=y
-CONFIG_EXPERT=y
-# CONFIG_EPOLL is not set
-# CONFIG_SHMEM is not set
-# CONFIG_ARCH_MULTI_V7 is not set
-CONFIG_ARCH_PXA=y
-CONFIG_ARCH_GUMSTIX=y
-CONFIG_ATAGS=y
-CONFIG_CMDLINE="console=ttyS0,115200n8 root=1f01 rootfstype=jffs2"
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_SWAP is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_NET=y
-CONFIG_PACKET=m
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_BT=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_H4=y
-CONFIG_PCCARD=y
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PXA2XX=y
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_SD=m
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ATA=m
-CONFIG_PATA_PCMCIA=m
-CONFIG_NETDEVICES=y
-CONFIG_SMC91X=m
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_SA1100_WATCHDOG=m
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_TILEBLITTING=y
-CONFIG_FB_PXA=y
-CONFIG_FB_PXA_PARAMETERS=y
-CONFIG_FB_MBX=m
-CONFIG_FB_VIRTUAL=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-# CONFIG_SND_VERBOSE_PROCFS is not set
-CONFIG_SND_PXA2XX_AC97=m
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_MMC=y
-CONFIG_MMC_PXA=y
-# CONFIG_DNOTIFY is not set
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_RUBIN=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DETECT_SOFTLOCKUP is not set
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_ARC4=m
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_PREEMPT is not set
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
deleted file mode 100644
index c7cf089001bf..000000000000
--- a/arch/arm/configs/spitz_defconfig
+++ /dev/null
@@ -1,237 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_PREEMPT=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-CONFIG_PROFILING=y
-# CONFIG_ARCH_MULTI_V7 is not set
-CONFIG_ARCH_PXA=y
-CONFIG_PXA_SHARPSL=y
-CONFIG_MACH_AKITA=y
-CONFIG_MACH_BORZOI=y
-CONFIG_ATAGS=y
-CONFIG_CMDLINE="console=ttyS0,115200n8 console=tty1 noinitrd root=/dev/mtdblock2 rootfstype=jffs2 debug"
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_BINFMT_MISC=m
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_SYN_COOKIES=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_NETFILTER=y
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_BT=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIBTUART=m
-CONFIG_BT_HCIVHCI=m
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_PXA2XX=y
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_NAND_SHARPSL=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-CONFIG_CHR_DEV_OSST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ATA=y
-CONFIG_PATA_PCMCIA=y
-CONFIG_NETDEVICES=y
-CONFIG_PCMCIA_PCNET=m
-CONFIG_PPP=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=m
-# CONFIG_USB_NET_CDC_SUBSET is not set
-CONFIG_NET_PCMCIA=y
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=m
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_8250=m
-CONFIG_SERIAL_8250_CS=m
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_SPI_PXA2XX=y
-CONFIG_FB=y
-CONFIG_FB_PXA=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_CORGI=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_HID_A4TECH=m
-CONFIG_HID_APPLE=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-CONFIG_HID_CYPRESS=m
-CONFIG_HID_EZKEY=m
-CONFIG_HID_GYRATION=m
-CONFIG_HID_LOGITECH=m
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MONTEREY=m
-CONFIG_HID_PANTHERLORD=m
-CONFIG_HID_PETALYNX=m
-CONFIG_HID_SAMSUNG=m
-CONFIG_HID_SONY=m
-CONFIG_HID_SUNPLUS=m
-CONFIG_USB_KBD=m
-CONFIG_USB_MOUSE=m
-CONFIG_USB=m
-CONFIG_USB_MON=m
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_SL811_HCD=m
-CONFIG_USB_SL811_CS=m
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_STORAGE=m
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_GARMIN=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_TI=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_IDMOUSE=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_GADGET_DUMMY_HCD=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_MMC=y
-CONFIG_MMC_PXA=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_RUBIN=y
-CONFIG_CRAMFS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
-CONFIG_NFS_V4=m
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_BENCHMARK=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
diff --git a/arch/arm/include/asm/hardware/scoop.h b/arch/arm/include/asm/hardware/scoop.h
deleted file mode 100644
index 505453315287..000000000000
--- a/arch/arm/include/asm/hardware/scoop.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Definitions for the SCOOP interface found on various Sharp PDAs
- *
- * Copyright (c) 2004 Richard Purdie
- */
-
-#define SCOOP_MCR 0x00
-#define SCOOP_CDR 0x04
-#define SCOOP_CSR 0x08
-#define SCOOP_CPR 0x0C
-#define SCOOP_CCR 0x10
-#define SCOOP_IRR 0x14
-#define SCOOP_IRM 0x14
-#define SCOOP_IMR 0x18
-#define SCOOP_ISR 0x1C
-#define SCOOP_GPCR 0x20
-#define SCOOP_GPWR 0x24
-#define SCOOP_GPRR 0x28
-
-#define SCOOP_CPR_OUT (1 << 7)
-#define SCOOP_CPR_SD_3V (1 << 2)
-#define SCOOP_CPR_CF_XV (1 << 1)
-#define SCOOP_CPR_CF_3V (1 << 0)
-
-#define SCOOP_GPCR_PA22 (1 << 12)
-#define SCOOP_GPCR_PA21 (1 << 11)
-#define SCOOP_GPCR_PA20 (1 << 10)
-#define SCOOP_GPCR_PA19 (1 << 9)
-#define SCOOP_GPCR_PA18 (1 << 8)
-#define SCOOP_GPCR_PA17 (1 << 7)
-#define SCOOP_GPCR_PA16 (1 << 6)
-#define SCOOP_GPCR_PA15 (1 << 5)
-#define SCOOP_GPCR_PA14 (1 << 4)
-#define SCOOP_GPCR_PA13 (1 << 3)
-#define SCOOP_GPCR_PA12 (1 << 2)
-#define SCOOP_GPCR_PA11 (1 << 1)
-
-struct scoop_config {
- unsigned short io_out;
- unsigned short io_dir;
- unsigned short suspend_clr;
- unsigned short suspend_set;
- int gpio_base;
-};
-
-/* Structure for linking scoop devices to PCMCIA sockets */
-struct scoop_pcmcia_dev {
- struct device *dev; /* Pointer to this socket's scoop device */
- int irq; /* irq for socket */
- int cd_irq;
- const char *cd_irq_str;
- unsigned char keep_vs;
- unsigned char keep_rd;
-};
-
-struct scoop_pcmcia_config {
- struct scoop_pcmcia_dev *devs;
- int num_devs;
- void (*power_ctrl)(struct device *scoop, unsigned short cpr, int nr);
-};
-
-extern struct scoop_pcmcia_config *platform_scoop_config;
-
-void reset_scoop(struct device *dev);
-unsigned short read_scoop_reg(struct device *dev, unsigned short reg);
-void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data);
diff --git a/arch/arm/include/asm/mach/sharpsl_param.h b/arch/arm/include/asm/mach/sharpsl_param.h
deleted file mode 100644
index 700a377c20bf..000000000000
--- a/arch/arm/include/asm/mach/sharpsl_param.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Hardware parameter area specific to Sharp SL series devices
- *
- * Copyright (c) 2005 Richard Purdie
- *
- * Based on Sharp's 2.4 kernel patches
- */
-
-struct sharpsl_param_info {
- unsigned int comadj_keyword;
- unsigned int comadj;
-
- unsigned int uuid_keyword;
- unsigned char uuid[16];
-
- unsigned int touch_keyword;
- unsigned int touch_xp;
- unsigned int touch_yp;
- unsigned int touch_xd;
- unsigned int touch_yd;
-
- unsigned int adadj_keyword;
- unsigned int adadj;
-
- unsigned int phad_keyword;
- unsigned int phadadj;
-} __attribute__((packed));
-
-
-extern struct sharpsl_param_info sharpsl_param;
-extern void sharpsl_save_param(void);
-
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 2fb29b9ef744..354e3dc17776 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -50,77 +50,6 @@ config MACH_PXA3XX_DT
the device tree. Needn't select any other machine while
MACH_PXA3XX_DT is enabled.
-if ATAGS
-
-comment "Legacy board files"
-
-config ARCH_GUMSTIX
- bool "Gumstix XScale 255 boards (DEPRECATED)"
- select PXA25x
- help
- Say Y here if you intend to run this kernel on
- Basix, Connex, ws-200ax, ws-400ax systems
-
- Support for this machine will go away in early 2027,
- unless it gets converted to device tree.
-
-choice
- prompt "Gumstix Carrier/Expansion Board"
- depends on ARCH_GUMSTIX
-
-config GUMSTIX_AM200EPD
- bool "Enable AM200EPD board support"
-
-config GUMSTIX_AM300EPD
- bool "Enable AM300EPD board support"
-
-endchoice
-
-config PXA_SHARPSL
- bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models (DEPRECATED)"
- select SHARP_PARAM
- select SHARP_SCOOP
- help
- Say Y here if you intend to run this kernel on a
- Sharp Zaurus SL-5600 (Poodle), SL-C700 (Corgi),
- SL-C750 (Shepherd), SL-C760 (Husky), SL-C1000 (Akita),
- SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa)
- handheld computer.
-
- Support for these machines will go away in early 2027,
- unless they get converted to device tree.
-
-config PXA_SHARPSL_DETECT_MACH_ID
- bool "Detect machine ID at run-time in the decompressor"
- depends on PXA_SHARPSL
- help
- Say Y here if you want the zImage decompressor to detect
- the Zaurus machine ID at run-time. For latest kexec-based
- boot loader, this is not necessary.
-
-config MACH_AKITA
- bool "Enable Sharp SL-1000 (Akita) Support"
- depends on PXA_SHARPSL
- select I2C
- select I2C_PXA
- select MACH_SPITZ
- select PXA27x
- select PXA_SHARP_Cxx00
-
-config MACH_SPITZ
- bool "Enable Sharp Zaurus SL-3000 (Spitz) Support"
- depends on PXA_SHARPSL
- select PXA27x
- select PXA_SHARP_Cxx00
-
-config MACH_BORZOI
- bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support"
- depends on PXA_SHARPSL
- select PXA27x
- select PXA_SHARP_Cxx00
-
-endif # ATAGS
-
config PXA25x
bool
select CPU_XSCALE
@@ -157,22 +86,4 @@ config CPU_PXA320
help
PXA320 (codename Monahans-P)
-config PXA_SHARP_Cxx00
- bool
- select SHARPSL_PM
- help
- Enable common support for Sharp Cxx00 models
-
-config SHARPSL_PM
- bool
- select APM_EMULATION
- select SHARPSL_PM_MAX1111
-
-config SHARPSL_PM_MAX1111
- bool
- select HWMON
- select SENSORS_MAX1111
- select SPI
- select SPI_MASTER
-
endif
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index faccdd356482..3bc3b2e56afe 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -22,11 +22,3 @@ obj-$(CONFIG_CPU_PXA320) += pxa320.o
obj-$(CONFIG_MACH_PXA25X_DT) += pxa-dt.o
obj-$(CONFIG_MACH_PXA27X_DT) += pxa-dt.o
obj-$(CONFIG_MACH_PXA3XX_DT) += pxa-dt.o
-
-# 3rd Party Dev Platforms
-obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o
-obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o
-obj-$(CONFIG_GUMSTIX_AM300EPD) += am300epd.o
-
-# End-user Products
-obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o
diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c
deleted file mode 100644
index 4814f3cfe775..000000000000
--- a/arch/arm/mach-pxa/am200epd.c
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * am200epd.c -- Platform device for AM200 EPD kit
- *
- * Copyright (C) 2008, Jaya Kumar
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive for
- * more details.
- *
- * Layout is based on skeletonfb.c by James Simmons and Geert Uytterhoeven.
- *
- * This work was made possible by help and equipment support from E-Ink
- * Corporation. http://support.eink.com/community
- *
- * This driver is written to be used with the Metronome display controller.
- * on the AM200 EPD prototype kit/development kit with an E-Ink 800x600
- * Vizplex EPD on a Gumstix board using the Lyre interface board.
- *
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/fb.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/gpio/legacy.h>
-
-#include "pxa25x.h"
-#include "gumstix.h"
-#include <linux/platform_data/video-pxafb.h>
-
-#include "generic.h"
-
-#include <video/metronomefb.h>
-
-static unsigned int panel_type = 6;
-static struct platform_device *am200_device;
-static struct metronome_board am200_board;
-
-static struct pxafb_mode_info am200_fb_mode_9inch7 = {
- .pixclock = 40000,
- .xres = 1200,
- .yres = 842,
- .bpp = 16,
- .hsync_len = 2,
- .left_margin = 2,
- .right_margin = 2,
- .vsync_len = 1,
- .upper_margin = 2,
- .lower_margin = 25,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-};
-
-static struct pxafb_mode_info am200_fb_mode_8inch = {
- .pixclock = 40000,
- .xres = 1088,
- .yres = 791,
- .bpp = 16,
- .hsync_len = 28,
- .left_margin = 8,
- .right_margin = 30,
- .vsync_len = 8,
- .upper_margin = 10,
- .lower_margin = 8,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-};
-
-static struct pxafb_mode_info am200_fb_mode_6inch = {
- .pixclock = 40189,
- .xres = 832,
- .yres = 622,
- .bpp = 16,
- .hsync_len = 28,
- .left_margin = 34,
- .right_margin = 34,
- .vsync_len = 25,
- .upper_margin = 0,
- .lower_margin = 2,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-};
-
-static struct pxafb_mach_info am200_fb_info = {
- .modes = &am200_fb_mode_6inch,
- .num_modes = 1,
- .lcd_conn = LCD_TYPE_COLOR_TFT | LCD_PCLK_EDGE_FALL |
- LCD_AC_BIAS_FREQ(24),
-};
-
-/* register offsets for gpio control */
-#define LED_GPIO_PIN 51
-#define STDBY_GPIO_PIN 48
-#define RST_GPIO_PIN 49
-#define RDY_GPIO_PIN 32
-#define ERR_GPIO_PIN 17
-#define PCBPWR_GPIO_PIN 16
-static int gpios[] = { LED_GPIO_PIN , STDBY_GPIO_PIN , RST_GPIO_PIN,
- RDY_GPIO_PIN, ERR_GPIO_PIN, PCBPWR_GPIO_PIN };
-static char *gpio_names[] = { "LED" , "STDBY" , "RST", "RDY", "ERR", "PCBPWR" };
-
-static int am200_init_gpio_regs(struct metronomefb_par *par)
-{
- int i;
- int err;
-
- for (i = 0; i < ARRAY_SIZE(gpios); i++) {
- err = gpio_request(gpios[i], gpio_names[i]);
- if (err) {
- dev_err(&am200_device->dev, "failed requesting "
- "gpio %s, err=%d\n", gpio_names[i], err);
- goto err_req_gpio;
- }
- }
-
- gpio_direction_output(LED_GPIO_PIN, 0);
- gpio_direction_output(STDBY_GPIO_PIN, 0);
- gpio_direction_output(RST_GPIO_PIN, 0);
-
- gpio_direction_input(RDY_GPIO_PIN);
- gpio_direction_input(ERR_GPIO_PIN);
-
- gpio_direction_output(PCBPWR_GPIO_PIN, 0);
-
- return 0;
-
-err_req_gpio:
- while (--i >= 0)
- gpio_free(gpios[i]);
-
- return err;
-}
-
-static void am200_cleanup(struct metronomefb_par *par)
-{
- int i;
-
- free_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), par);
-
- for (i = 0; i < ARRAY_SIZE(gpios); i++)
- gpio_free(gpios[i]);
-}
-
-static int am200_share_video_mem(struct fb_info *info)
-{
- /* rough check if this is our desired fb and not something else */
- if ((info->var.xres != am200_fb_info.modes->xres)
- || (info->var.yres != am200_fb_info.modes->yres))
- return 0;
-
- /* we've now been notified that we have our new fb */
- am200_board.metromem = info->screen_base;
- am200_board.host_fbinfo = info;
-
- /* try to refcount host drv since we are the consumer after this */
- if (!try_module_get(info->fbops->owner))
- return -ENODEV;
-
- return 0;
-}
-
-static int am200_unshare_video_mem(struct fb_info *info)
-{
- dev_dbg(&am200_device->dev, "ENTER %s\n", __func__);
-
- if (info != am200_board.host_fbinfo)
- return 0;
-
- module_put(am200_board.host_fbinfo->fbops->owner);
- return 0;
-}
-
-static int am200_fb_notifier_callback(struct notifier_block *self,
- unsigned long event, void *data)
-{
- struct fb_event *evdata = data;
- struct fb_info *info = evdata->info;
-
- dev_dbg(&am200_device->dev, "ENTER %s\n", __func__);
-
- if (event == FB_EVENT_FB_REGISTERED)
- return am200_share_video_mem(info);
- else if (event == FB_EVENT_FB_UNREGISTERED)
- return am200_unshare_video_mem(info);
-
- return 0;
-}
-
-static struct notifier_block am200_fb_notif = {
- .notifier_call = am200_fb_notifier_callback,
-};
-
-/* this gets called as part of our init. these steps must be done now so
- * that we can use pxa_set_fb_info */
-static void __init am200_presetup_fb(void)
-{
- int fw;
- int fh;
- int padding_size;
- int totalsize;
-
- switch (panel_type) {
- case 6:
- am200_fb_info.modes = &am200_fb_mode_6inch;
- break;
- case 8:
- am200_fb_info.modes = &am200_fb_mode_8inch;
- break;
- case 97:
- am200_fb_info.modes = &am200_fb_mode_9inch7;
- break;
- default:
- dev_err(&am200_device->dev, "invalid panel_type selection,"
- " setting to 6\n");
- am200_fb_info.modes = &am200_fb_mode_6inch;
- break;
- }
-
- /* the frame buffer is divided as follows:
- command | CRC | padding
- 16kb waveform data | CRC | padding
- image data | CRC
- */
-
- fw = am200_fb_info.modes->xres;
- fh = am200_fb_info.modes->yres;
-
- /* waveform must be 16k + 2 for checksum */
- am200_board.wfm_size = roundup(16*1024 + 2, fw);
-
- padding_size = PAGE_SIZE + (4 * fw);
-
- /* total is 1 cmd , 1 wfm, padding and image */
- totalsize = fw + am200_board.wfm_size + padding_size + (fw*fh);
-
- /* save this off because we're manipulating fw after this and
- * we'll need it when we're ready to setup the framebuffer */
- am200_board.fw = fw;
- am200_board.fh = fh;
-
- /* the reason we do this adjustment is because we want to acquire
- * more framebuffer memory without imposing custom awareness on the
- * underlying pxafb driver */
- am200_fb_info.modes->yres = DIV_ROUND_UP(totalsize, fw);
-
- /* we divide since we told the LCD controller we're 16bpp */
- am200_fb_info.modes->xres /= 2;
-
- pxa_set_fb_info(NULL, &am200_fb_info);
-
-}
-
-/* this gets called by metronomefb as part of its init, in our case, we
- * have already completed initial framebuffer init in presetup_fb so we
- * can just setup the fb access pointers */
-static int am200_setup_fb(struct metronomefb_par *par)
-{
- int fw;
- int fh;
-
- fw = am200_board.fw;
- fh = am200_board.fh;
-
- /* metromem was set up by the notifier in share_video_mem so now
- * we can use its value to calculate the other entries */
- par->metromem_cmd = (struct metromem_cmd *) am200_board.metromem;
- par->metromem_wfm = am200_board.metromem + fw;
- par->metromem_img = par->metromem_wfm + am200_board.wfm_size;
- par->metromem_img_csum = (u16 *) (par->metromem_img + (fw * fh));
- par->metromem_dma = am200_board.host_fbinfo->fix.smem_start;
-
- return 0;
-}
-
-static int am200_get_panel_type(void)
-{
- return panel_type;
-}
-
-static irqreturn_t am200_handle_irq(int irq, void *dev_id)
-{
- struct metronomefb_par *par = dev_id;
-
- wake_up_interruptible(&par->waitq);
- return IRQ_HANDLED;
-}
-
-static int am200_setup_irq(struct fb_info *info)
-{
- int ret;
-
- ret = request_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), am200_handle_irq,
- IRQF_TRIGGER_FALLING, "AM200", info->par);
- if (ret)
- dev_err(&am200_device->dev, "request_irq failed: %d\n", ret);
-
- return ret;
-}
-
-static void am200_set_rst(struct metronomefb_par *par, int state)
-{
- gpio_set_value(RST_GPIO_PIN, state);
-}
-
-static void am200_set_stdby(struct metronomefb_par *par, int state)
-{
- gpio_set_value(STDBY_GPIO_PIN, state);
-}
-
-static int am200_wait_event(struct metronomefb_par *par)
-{
- return wait_event_timeout(par->waitq, gpio_get_value(RDY_GPIO_PIN), HZ);
-}
-
-static int am200_wait_event_intr(struct metronomefb_par *par)
-{
- return wait_event_interruptible_timeout(par->waitq,
- gpio_get_value(RDY_GPIO_PIN), HZ);
-}
-
-static struct metronome_board am200_board = {
- .owner = THIS_MODULE,
- .setup_irq = am200_setup_irq,
- .setup_io = am200_init_gpio_regs,
- .setup_fb = am200_setup_fb,
- .set_rst = am200_set_rst,
- .set_stdby = am200_set_stdby,
- .met_wait_event = am200_wait_event,
- .met_wait_event_intr = am200_wait_event_intr,
- .get_panel_type = am200_get_panel_type,
- .cleanup = am200_cleanup,
-};
-
-static unsigned long am200_pin_config[] __initdata = {
- GPIO51_GPIO,
- GPIO49_GPIO,
- GPIO48_GPIO,
- GPIO32_GPIO,
- GPIO17_GPIO,
- GPIO16_GPIO,
-};
-
-int __init am200_init(void)
-{
- int ret;
-
- /*
- * Before anything else, we request notification for any fb
- * creation events.
- *
- * FIXME: This is terrible and needs to be nuked. The notifier is used
- * to get at the fb base address from the boot splash fb driver, which
- * is then passed to metronomefb. Instaed of metronomfb or this board
- * support file here figuring this out on their own.
- *
- * See also the #ifdef in fbmem.c.
- */
- fb_register_client(&am200_fb_notif);
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(am200_pin_config));
-
- /* request our platform independent driver */
- request_module("metronomefb");
-
- am200_device = platform_device_alloc("metronomefb", -1);
- if (!am200_device)
- return -ENOMEM;
-
- /* the am200_board that will be seen by metronomefb is a copy */
- platform_device_add_data(am200_device, &am200_board,
- sizeof(am200_board));
-
- /* this _add binds metronomefb to am200. metronomefb refcounts am200 */
- ret = platform_device_add(am200_device);
-
- if (ret) {
- platform_device_put(am200_device);
- fb_unregister_client(&am200_fb_notif);
- return ret;
- }
-
- am200_presetup_fb();
-
- return 0;
-}
-
-module_param(panel_type, uint, 0);
-MODULE_PARM_DESC(panel_type, "Select the panel type: 6, 8, 97");
-
-MODULE_DESCRIPTION("board driver for am200 metronome epd kit");
-MODULE_AUTHOR("Jaya Kumar");
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c
deleted file mode 100644
index 435fb72da7de..000000000000
--- a/arch/arm/mach-pxa/am300epd.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * am300epd.c -- Platform device for AM300 EPD kit
- *
- * Copyright (C) 2008, Jaya Kumar
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive for
- * more details.
- *
- * This work was made possible by help and equipment support from E-Ink
- * Corporation. http://support.eink.com/community
- *
- * This driver is written to be used with the Broadsheet display controller.
- * on the AM300 EPD prototype kit/development kit with an E-Ink 800x600
- * Vizplex EPD on a Gumstix board using the Broadsheet interface board.
- *
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/fb.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/gpio/legacy.h>
-
-#include "gumstix.h"
-#include "mfp-pxa25x.h"
-#include "irqs.h"
-#include <linux/platform_data/video-pxafb.h>
-
-#include "generic.h"
-
-#include <video/broadsheetfb.h>
-
-static unsigned int panel_type = 6;
-static struct platform_device *am300_device;
-static struct broadsheet_board am300_board;
-
-static unsigned long am300_pin_config[] __initdata = {
- GPIO16_GPIO,
- GPIO17_GPIO,
- GPIO32_GPIO,
- GPIO48_GPIO,
- GPIO49_GPIO,
- GPIO51_GPIO,
- GPIO74_GPIO,
- GPIO75_GPIO,
- GPIO76_GPIO,
- GPIO77_GPIO,
-
- /* this is the 16-bit hdb bus 58-73 */
- GPIO58_GPIO,
- GPIO59_GPIO,
- GPIO60_GPIO,
- GPIO61_GPIO,
-
- GPIO62_GPIO,
- GPIO63_GPIO,
- GPIO64_GPIO,
- GPIO65_GPIO,
-
- GPIO66_GPIO,
- GPIO67_GPIO,
- GPIO68_GPIO,
- GPIO69_GPIO,
-
- GPIO70_GPIO,
- GPIO71_GPIO,
- GPIO72_GPIO,
- GPIO73_GPIO,
-};
-
-/* register offsets for gpio control */
-#define PWR_GPIO_PIN 16
-#define CFG_GPIO_PIN 17
-#define RDY_GPIO_PIN 32
-#define DC_GPIO_PIN 48
-#define RST_GPIO_PIN 49
-#define LED_GPIO_PIN 51
-#define RD_GPIO_PIN 74
-#define WR_GPIO_PIN 75
-#define CS_GPIO_PIN 76
-#define IRQ_GPIO_PIN 77
-
-/* hdb bus */
-#define DB0_GPIO_PIN 58
-#define DB15_GPIO_PIN 73
-
-static int gpios[] = { PWR_GPIO_PIN, CFG_GPIO_PIN, RDY_GPIO_PIN, DC_GPIO_PIN,
- RST_GPIO_PIN, RD_GPIO_PIN, WR_GPIO_PIN, CS_GPIO_PIN,
- IRQ_GPIO_PIN, LED_GPIO_PIN };
-static char *gpio_names[] = { "PWR", "CFG", "RDY", "DC", "RST", "RD", "WR",
- "CS", "IRQ", "LED" };
-
-static int am300_wait_event(struct broadsheetfb_par *par)
-{
- /* todo: improve err recovery */
- wait_event(par->waitq, gpio_get_value(RDY_GPIO_PIN));
- return 0;
-}
-
-static int am300_init_gpio_regs(struct broadsheetfb_par *par)
-{
- int i;
- int err;
- char dbname[8];
-
- for (i = 0; i < ARRAY_SIZE(gpios); i++) {
- err = gpio_request(gpios[i], gpio_names[i]);
- if (err) {
- dev_err(&am300_device->dev, "failed requesting "
- "gpio %s, err=%d\n", gpio_names[i], err);
- goto err_req_gpio;
- }
- }
-
- /* we also need to take care of the hdb bus */
- for (i = DB0_GPIO_PIN; i <= DB15_GPIO_PIN; i++) {
- sprintf(dbname, "DB%d", i);
- err = gpio_request(i, dbname);
- if (err) {
- dev_err(&am300_device->dev, "failed requesting "
- "gpio %d, err=%d\n", i, err);
- goto err_req_gpio2;
- }
- }
-
- /* setup the outputs and init values */
- gpio_direction_output(PWR_GPIO_PIN, 0);
- gpio_direction_output(CFG_GPIO_PIN, 1);
- gpio_direction_output(DC_GPIO_PIN, 0);
- gpio_direction_output(RD_GPIO_PIN, 1);
- gpio_direction_output(WR_GPIO_PIN, 1);
- gpio_direction_output(CS_GPIO_PIN, 1);
- gpio_direction_output(RST_GPIO_PIN, 0);
-
- /* setup the inputs */
- gpio_direction_input(RDY_GPIO_PIN);
- gpio_direction_input(IRQ_GPIO_PIN);
-
- /* start the hdb bus as an input */
- for (i = DB0_GPIO_PIN; i <= DB15_GPIO_PIN; i++)
- gpio_direction_output(i, 0);
-
- /* go into command mode */
- gpio_set_value(CFG_GPIO_PIN, 1);
- gpio_set_value(RST_GPIO_PIN, 0);
- msleep(10);
- gpio_set_value(RST_GPIO_PIN, 1);
- msleep(10);
- am300_wait_event(par);
-
- return 0;
-
-err_req_gpio2:
- while (--i >= DB0_GPIO_PIN)
- gpio_free(i);
- i = ARRAY_SIZE(gpios);
-err_req_gpio:
- while (--i >= 0)
- gpio_free(gpios[i]);
-
- return err;
-}
-
-static int am300_init_board(struct broadsheetfb_par *par)
-{
- return am300_init_gpio_regs(par);
-}
-
-static void am300_cleanup(struct broadsheetfb_par *par)
-{
- int i;
-
- free_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), par);
-
- for (i = 0; i < ARRAY_SIZE(gpios); i++)
- gpio_free(gpios[i]);
-
- for (i = DB0_GPIO_PIN; i <= DB15_GPIO_PIN; i++)
- gpio_free(i);
-
-}
-
-static u16 am300_get_hdb(struct broadsheetfb_par *par)
-{
- u16 res = 0;
- int i;
-
- for (i = 0; i <= (DB15_GPIO_PIN - DB0_GPIO_PIN) ; i++)
- res |= (gpio_get_value(DB0_GPIO_PIN + i)) ? (1 << i) : 0;
-
- return res;
-}
-
-static void am300_set_hdb(struct broadsheetfb_par *par, u16 data)
-{
- int i;
-
- for (i = 0; i <= (DB15_GPIO_PIN - DB0_GPIO_PIN) ; i++)
- gpio_set_value(DB0_GPIO_PIN + i, (data >> i) & 0x01);
-}
-
-
-static void am300_set_ctl(struct broadsheetfb_par *par, unsigned char bit,
- u8 state)
-{
- switch (bit) {
- case BS_CS:
- gpio_set_value(CS_GPIO_PIN, state);
- break;
- case BS_DC:
- gpio_set_value(DC_GPIO_PIN, state);
- break;
- case BS_WR:
- gpio_set_value(WR_GPIO_PIN, state);
- break;
- }
-}
-
-static int am300_get_panel_type(void)
-{
- return panel_type;
-}
-
-static irqreturn_t am300_handle_irq(int irq, void *dev_id)
-{
- struct broadsheetfb_par *par = dev_id;
-
- wake_up(&par->waitq);
- return IRQ_HANDLED;
-}
-
-static int am300_setup_irq(struct fb_info *info)
-{
- int ret;
- struct broadsheetfb_par *par = info->par;
-
- ret = request_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), am300_handle_irq,
- IRQF_TRIGGER_RISING, "AM300", par);
- if (ret)
- dev_err(&am300_device->dev, "request_irq failed: %d\n", ret);
-
- return ret;
-}
-
-static struct broadsheet_board am300_board = {
- .owner = THIS_MODULE,
- .init = am300_init_board,
- .cleanup = am300_cleanup,
- .set_hdb = am300_set_hdb,
- .get_hdb = am300_get_hdb,
- .set_ctl = am300_set_ctl,
- .wait_for_rdy = am300_wait_event,
- .get_panel_type = am300_get_panel_type,
- .setup_irq = am300_setup_irq,
-};
-
-int __init am300_init(void)
-{
- int ret;
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(am300_pin_config));
-
- /* request our platform independent driver */
- request_module("broadsheetfb");
-
- am300_device = platform_device_alloc("broadsheetfb", -1);
- if (!am300_device)
- return -ENOMEM;
-
- /* the am300_board that will be seen by broadsheetfb is a copy */
- platform_device_add_data(am300_device, &am300_board,
- sizeof(am300_board));
-
- ret = platform_device_add(am300_device);
-
- if (ret) {
- platform_device_put(am300_device);
- return ret;
- }
-
- return 0;
-}
-
-module_param(panel_type, uint, 0);
-MODULE_PARM_DESC(panel_type, "Select the panel type: 37, 6, 97");
-
-MODULE_DESCRIPTION("board driver for am300 epd kit");
-MODULE_AUTHOR("Jaya Kumar");
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index edad956a1483..c2a2469a003a 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -1,715 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/dma-mapping.h>
-#include <linux/dmaengine.h>
-#include <linux/gpio-pxa.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/soc/pxa/cpu.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/mmc-pxamci.h>
#include "irqs.h"
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <linux/platform_data/mmp_dma.h>
-
-#include "mfp-pxa2xx.h"
#include "regs-ost.h"
#include "reset.h"
-#include "devices.h"
-#include "generic.h"
-
-void __init pxa_register_device(struct platform_device *dev, void *data)
-{
- int ret;
-
- dev->dev.platform_data = data;
-
- ret = platform_device_register(dev);
- if (ret)
- dev_err(&dev->dev, "unable to register device: %d\n", ret);
-}
-
-static struct resource pxa_resource_pmu = {
- .start = IRQ_PMU,
- .end = IRQ_PMU,
- .flags = IORESOURCE_IRQ,
-};
-
-struct platform_device pxa_device_pmu = {
- .name = "xscale-pmu",
- .id = -1,
- .resource = &pxa_resource_pmu,
- .num_resources = 1,
-};
-
-static const struct resource pxamci_resources[] = {
- [0] = {
- .start = 0x41100000,
- .end = 0x41100fff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_MMC,
- .end = IRQ_MMC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-void __init pxa_set_mci_info(const struct pxamci_platform_data *info,
- const struct property_entry *props)
-{
- const struct platform_device_info mci_info = {
- .name = "pxa2xx-mci",
- .id = 0,
- .res = pxamci_resources,
- .num_res = ARRAY_SIZE(pxamci_resources),
- .data = info,
- .size_data = sizeof(*info),
- .dma_mask = 0xffffffffUL,
- .properties = props,
- };
- struct platform_device *mci_dev;
- int err;
-
- mci_dev = platform_device_register_full(&mci_info);
- err = PTR_ERR_OR_ZERO(mci_dev);
- if (err)
- pr_err("Unable to create mci device: %d\n", err);
-}
-
-static struct resource pxa2xx_udc_resources[] = {
- [0] = {
- .start = 0x40600000,
- .end = 0x4060ffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_USB,
- .end = IRQ_USB,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 udc_dma_mask = ~(u32)0;
-
-struct platform_device pxa25x_device_udc = {
- .name = "pxa25x-udc",
- .id = -1,
- .resource = pxa2xx_udc_resources,
- .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
- .dev = {
- .dma_mask = &udc_dma_mask,
- }
-};
-
-struct platform_device pxa27x_device_udc = {
- .name = "pxa27x-udc",
- .id = -1,
- .resource = pxa2xx_udc_resources,
- .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
- .dev = {
- .dma_mask = &udc_dma_mask,
- }
-};
-
-static struct resource pxafb_resources[] = {
- [0] = {
- .start = 0x44000000,
- .end = 0x4400ffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_LCD,
- .end = IRQ_LCD,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 fb_dma_mask = ~(u64)0;
-
-struct platform_device pxa_device_fb = {
- .name = "pxa2xx-fb",
- .id = -1,
- .dev = {
- .dma_mask = &fb_dma_mask,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(pxafb_resources),
- .resource = pxafb_resources,
-};
-
-void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
-{
- pxa_device_fb.dev.parent = parent;
- pxa_register_device(&pxa_device_fb, info);
-}
-
-static struct resource pxa_resource_ffuart[] = {
- {
- .start = 0x40100000,
- .end = 0x40100023,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_FFUART,
- .end = IRQ_FFUART,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-struct platform_device pxa_device_ffuart = {
- .name = "pxa2xx-uart",
- .id = 0,
- .resource = pxa_resource_ffuart,
- .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
-};
-
-void __init pxa_set_ffuart_info(void *info)
-{
- pxa_register_device(&pxa_device_ffuart, info);
-}
-
-static struct resource pxa_resource_btuart[] = {
- {
- .start = 0x40200000,
- .end = 0x40200023,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_BTUART,
- .end = IRQ_BTUART,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-struct platform_device pxa_device_btuart = {
- .name = "pxa2xx-uart",
- .id = 1,
- .resource = pxa_resource_btuart,
- .num_resources = ARRAY_SIZE(pxa_resource_btuart),
-};
-
-void __init pxa_set_btuart_info(void *info)
-{
- pxa_register_device(&pxa_device_btuart, info);
-}
-
-static struct resource pxa_resource_stuart[] = {
- {
- .start = 0x40700000,
- .end = 0x40700023,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_STUART,
- .end = IRQ_STUART,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-struct platform_device pxa_device_stuart = {
- .name = "pxa2xx-uart",
- .id = 2,
- .resource = pxa_resource_stuart,
- .num_resources = ARRAY_SIZE(pxa_resource_stuart),
-};
-
-void __init pxa_set_stuart_info(void *info)
-{
- pxa_register_device(&pxa_device_stuart, info);
-}
-
-static struct resource pxa_resource_hwuart[] = {
- {
- .start = 0x41600000,
- .end = 0x4160002F,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_HWUART,
- .end = IRQ_HWUART,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-struct platform_device pxa_device_hwuart = {
- .name = "pxa2xx-uart",
- .id = 3,
- .resource = pxa_resource_hwuart,
- .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
-};
-
-void __init pxa_set_hwuart_info(void *info)
-{
- if (cpu_is_pxa255())
- pxa_register_device(&pxa_device_hwuart, info);
- else
- pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
-}
-
-static struct resource pxai2c_resources[] = {
- {
- .start = 0x40301680,
- .end = 0x403016a3,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_I2C,
- .end = IRQ_I2C,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa_device_i2c = {
- .name = "pxa2xx-i2c",
- .id = 0,
- .resource = pxai2c_resources,
- .num_resources = ARRAY_SIZE(pxai2c_resources),
-};
-
-void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
-{
- pxa_register_device(&pxa_device_i2c, info);
-}
-
-#ifdef CONFIG_PXA27x
-static struct resource pxa27x_resources_i2c_power[] = {
- {
- .start = 0x40f00180,
- .end = 0x40f001a3,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PWRI2C,
- .end = IRQ_PWRI2C,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa27x_device_i2c_power = {
- .name = "pxa2xx-i2c",
- .id = 1,
- .resource = pxa27x_resources_i2c_power,
- .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
-};
-#endif
-
-static struct resource pxai2s_resources[] = {
- {
- .start = 0x40400000,
- .end = 0x40400083,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_I2S,
- .end = IRQ_I2S,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa_device_i2s = {
- .name = "pxa2xx-i2s",
- .id = -1,
- .resource = pxai2s_resources,
- .num_resources = ARRAY_SIZE(pxai2s_resources),
-};
-
-struct platform_device pxa_device_asoc_ssp1 = {
- .name = "pxa-ssp-dai",
- .id = 0,
-};
-
-struct platform_device pxa_device_asoc_ssp2= {
- .name = "pxa-ssp-dai",
- .id = 1,
-};
-
-struct platform_device pxa_device_asoc_ssp3 = {
- .name = "pxa-ssp-dai",
- .id = 2,
-};
-
-struct platform_device pxa_device_asoc_ssp4 = {
- .name = "pxa-ssp-dai",
- .id = 3,
-};
-
-struct platform_device pxa_device_asoc_platform = {
- .name = "pxa-pcm-audio",
- .id = -1,
-};
-
-static struct resource pxa_rtc_resources[] = {
- [0] = {
- .start = 0x40900000,
- .end = 0x40900000 + 0x3b,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_RTC1Hz,
- .end = IRQ_RTC1Hz,
- .name = "rtc 1Hz",
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .start = IRQ_RTCAlrm,
- .end = IRQ_RTCAlrm,
- .name = "rtc alarm",
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa_device_rtc = {
- .name = "pxa-rtc",
- .id = -1,
- .num_resources = ARRAY_SIZE(pxa_rtc_resources),
- .resource = pxa_rtc_resources,
-};
-
-struct platform_device sa1100_device_rtc = {
- .name = "sa1100-rtc",
- .id = -1,
- .num_resources = ARRAY_SIZE(pxa_rtc_resources),
- .resource = pxa_rtc_resources,
-};
-
-#ifdef CONFIG_PXA25x
-
-static struct resource pxa25x_resource_pwm0[] = {
- [0] = {
- .start = 0x40b00000,
- .end = 0x40b0000f,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device pxa25x_device_pwm0 = {
- .name = "pxa25x-pwm",
- .id = 0,
- .resource = pxa25x_resource_pwm0,
- .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
-};
-
-static struct resource pxa25x_resource_pwm1[] = {
- [0] = {
- .start = 0x40c00000,
- .end = 0x40c0000f,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device pxa25x_device_pwm1 = {
- .name = "pxa25x-pwm",
- .id = 1,
- .resource = pxa25x_resource_pwm1,
- .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
-};
-
-static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource pxa25x_resource_ssp[] = {
- [0] = {
- .start = 0x41000000,
- .end = 0x4100001f,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SSP,
- .end = IRQ_SSP,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa25x_device_ssp = {
- .name = "pxa25x-ssp",
- .id = 0,
- .dev = {
- .dma_mask = &pxa25x_ssp_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = pxa25x_resource_ssp,
- .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
-};
-
-static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource pxa25x_resource_nssp[] = {
- [0] = {
- .start = 0x41400000,
- .end = 0x4140002f,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_NSSP,
- .end = IRQ_NSSP,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa25x_device_nssp = {
- .name = "pxa25x-nssp",
- .id = 1,
- .dev = {
- .dma_mask = &pxa25x_nssp_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = pxa25x_resource_nssp,
- .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
-};
-
-static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource pxa25x_resource_assp[] = {
- [0] = {
- .start = 0x41500000,
- .end = 0x4150002f,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_ASSP,
- .end = IRQ_ASSP,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa25x_device_assp = {
- /* ASSP is basically equivalent to NSSP */
- .name = "pxa25x-nssp",
- .id = 2,
- .dev = {
- .dma_mask = &pxa25x_assp_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = pxa25x_resource_assp,
- .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
-};
-#endif /* CONFIG_PXA25x */
-
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource pxa27x_resource_ohci[] = {
- [0] = {
- .start = 0x4C000000,
- .end = 0x4C00ff6f,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_USBH1,
- .end = IRQ_USBH1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa27x_device_ohci = {
- .name = "pxa27x-ohci",
- .id = -1,
- .dev = {
- .dma_mask = &pxa27x_ohci_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
- .resource = pxa27x_resource_ohci,
-};
-
-void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
-{
- pxa_register_device(&pxa27x_device_ohci, info);
-}
-#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
-
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource pxa27x_resource_ssp1[] = {
- [0] = {
- .start = 0x41000000,
- .end = 0x4100003f,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SSP,
- .end = IRQ_SSP,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa27x_device_ssp1 = {
- .name = "pxa27x-ssp",
- .id = 0,
- .dev = {
- .dma_mask = &pxa27x_ssp1_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = pxa27x_resource_ssp1,
- .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
-};
-
-static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource pxa27x_resource_ssp2[] = {
- [0] = {
- .start = 0x41700000,
- .end = 0x4170003f,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SSP2,
- .end = IRQ_SSP2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa27x_device_ssp2 = {
- .name = "pxa27x-ssp",
- .id = 1,
- .dev = {
- .dma_mask = &pxa27x_ssp2_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = pxa27x_resource_ssp2,
- .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
-};
-
-static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource pxa27x_resource_ssp3[] = {
- [0] = {
- .start = 0x41900000,
- .end = 0x4190003f,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SSP3,
- .end = IRQ_SSP3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa27x_device_ssp3 = {
- .name = "pxa27x-ssp",
- .id = 2,
- .dev = {
- .dma_mask = &pxa27x_ssp3_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = pxa27x_resource_ssp3,
- .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
-};
-
-static struct resource pxa27x_resource_pwm0[] = {
- [0] = {
- .start = 0x40b00000,
- .end = 0x40b0001f,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device pxa27x_device_pwm0 = {
- .name = "pxa27x-pwm",
- .id = 0,
- .resource = pxa27x_resource_pwm0,
- .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
-};
-
-static struct resource pxa27x_resource_pwm1[] = {
- [0] = {
- .start = 0x40c00000,
- .end = 0x40c0001f,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device pxa27x_device_pwm1 = {
- .name = "pxa27x-pwm",
- .id = 1,
- .resource = pxa27x_resource_pwm1,
- .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
-};
-#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
-
-#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
-const struct software_node pxa2xx_gpiochip_node = {
- .name = "gpio-pxa",
-};
-
-struct resource pxa_resource_gpio[] = {
- {
- .start = 0x40e00000,
- .end = 0x40e0ffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_GPIO0,
- .end = IRQ_GPIO0,
- .name = "gpio0",
- .flags = IORESOURCE_IRQ,
- }, {
- .start = IRQ_GPIO1,
- .end = IRQ_GPIO1,
- .name = "gpio1",
- .flags = IORESOURCE_IRQ,
- }, {
- .start = IRQ_GPIO_2_x,
- .end = IRQ_GPIO_2_x,
- .name = "gpio_mux",
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct pxa_gpio_platform_data pxa2xx_gpio_info = {
- .irq_base = PXA_GPIO_TO_IRQ(0),
- .gpio_set_wake = gpio_set_wake,
-};
-
-struct platform_device pxa25x_device_gpio = {
- .name = "pxa25x-gpio",
- .id = -1,
- .num_resources = ARRAY_SIZE(pxa_resource_gpio),
- .resource = pxa_resource_gpio,
- .dev = {
- .platform_data = &pxa2xx_gpio_info,
- },
-};
-
-struct platform_device pxa27x_device_gpio = {
- .name = "pxa27x-gpio",
- .id = -1,
- .num_resources = ARRAY_SIZE(pxa_resource_gpio),
- .resource = pxa_resource_gpio,
- .dev = {
- .platform_data = &pxa2xx_gpio_info,
- },
-};
-#endif /* CONFIG_PXA25x || CONFIG_PXA27x */
-
-static struct resource pxa_dma_resource[] = {
- [0] = {
- .start = 0x40000000,
- .end = 0x4000ffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_DMA,
- .end = IRQ_DMA,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 pxadma_dmamask = 0xffffffffUL;
-
-static struct platform_device pxa2xx_pxa_dma = {
- .name = "pxa-dma",
- .id = 0,
- .dev = {
- .dma_mask = &pxadma_dmamask,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(pxa_dma_resource),
- .resource = pxa_dma_resource,
-};
-
-void __init pxa2xx_set_dmac_info(struct mmp_dma_platdata *dma_pdata)
-{
- pxa_register_device(&pxa2xx_pxa_dma, dma_pdata);
-}
void __init pxa_register_wdt(unsigned int reset_status)
{
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
deleted file mode 100644
index 72c556ff67db..000000000000
--- a/arch/arm/mach-pxa/devices.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#define PDMA_FILTER_PARAM(_prio, _requestor) (&(struct pxad_param) { \
- .prio = PXAD_PRIO_##_prio, .drcmr = _requestor })
-struct mmp_dma_platdata;
-
-extern struct platform_device pxa_device_pmu;
-extern struct platform_device pxa3xx_device_mci2;
-extern struct platform_device pxa3xx_device_mci3;
-extern struct platform_device pxa25x_device_udc;
-extern struct platform_device pxa27x_device_udc;
-extern struct platform_device pxa_device_fb;
-extern struct platform_device pxa_device_ffuart;
-extern struct platform_device pxa_device_btuart;
-extern struct platform_device pxa_device_stuart;
-extern struct platform_device pxa_device_hwuart;
-extern struct platform_device pxa_device_i2c;
-extern struct platform_device pxa_device_i2s;
-extern struct platform_device sa1100_device_rtc;
-extern struct platform_device pxa_device_rtc;
-extern struct platform_device pxa_device_ac97;
-
-extern struct platform_device pxa27x_device_i2c_power;
-extern struct platform_device pxa27x_device_ohci;
-extern struct platform_device pxa27x_device_keypad;
-
-extern struct platform_device pxa25x_device_ssp;
-extern struct platform_device pxa25x_device_nssp;
-extern struct platform_device pxa25x_device_assp;
-extern struct platform_device pxa27x_device_ssp1;
-extern struct platform_device pxa27x_device_ssp2;
-extern struct platform_device pxa27x_device_ssp3;
-extern struct platform_device pxa3xx_device_ssp1;
-extern struct platform_device pxa3xx_device_ssp2;
-extern struct platform_device pxa3xx_device_ssp3;
-extern struct platform_device pxa3xx_device_ssp4;
-
-extern struct platform_device pxa25x_device_pwm0;
-extern struct platform_device pxa25x_device_pwm1;
-extern struct platform_device pxa27x_device_pwm0;
-extern struct platform_device pxa27x_device_pwm1;
-
-extern struct platform_device pxa3xx_device_nand;
-extern struct platform_device pxa3xx_device_i2c_power;
-
-extern struct platform_device pxa3xx_device_gcu;
-
-extern struct platform_device pxa_device_asoc_platform;
-extern struct platform_device pxa_device_asoc_ssp1;
-extern struct platform_device pxa_device_asoc_ssp2;
-extern struct platform_device pxa_device_asoc_ssp3;
-extern struct platform_device pxa_device_asoc_ssp4;
-
-extern struct platform_device pxa25x_device_gpio;
-extern struct platform_device pxa27x_device_gpio;
-
-extern const struct software_node pxa2xx_gpiochip_node;
-
-void __init pxa_register_device(struct platform_device *dev, void *data);
-void __init pxa2xx_set_dmac_info(struct mmp_dma_platdata *dma_pdata);
-
-struct i2c_pxa_platform_data;
-extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
-#ifdef CONFIG_PXA27x
-extern void pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info);
-#endif
-#ifdef CONFIG_PXA3xx
-extern void pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info);
-#endif
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index caad4fca8de3..239d1b4119cc 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -38,11 +38,6 @@ extern struct syscore pxa_irq_syscore;
extern struct syscore pxa2xx_mfp_syscore;
extern struct syscore pxa3xx_mfp_syscore;
-void __init pxa_set_ffuart_info(void *info);
-void __init pxa_set_btuart_info(void *info);
-void __init pxa_set_stuart_info(void *info);
-void __init pxa_set_hwuart_info(void *info);
-
void pxa_restart(enum reboot_mode, const char *);
#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
deleted file mode 100644
index 7ab0cb015d1b..000000000000
--- a/arch/arm/mach-pxa/gumstix.c
+++ /dev/null
@@ -1,237 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/gumstix.c
- *
- * Support for the Gumstix motherboards.
- *
- * Original Author: Craig Hughes
- * Created: Feb 14, 2008
- * Copyright: Craig Hughes
- *
- * Implemented based on lubbock.c by Nicolas Pitre and code from Craig
- * Hughes
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio/property.h>
-#include <linux/gpio/legacy.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <linux/sizes.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/flash.h>
-
-#include "pxa25x.h"
-#include <linux/platform_data/mmc-pxamci.h>
-#include "gumstix.h"
-#include "devices.h"
-
-#include "generic.h"
-
-static struct resource flash_resource = {
- .start = 0x00000000,
- .end = SZ_64M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct mtd_partition gumstix_partitions[] = {
- {
- .name = "Bootloader",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_WRITEABLE /* force read-only */
- } , {
- .name = "rootfs",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND
- }
-};
-
-static struct flash_platform_data gumstix_flash_data = {
- .map_name = "cfi_probe",
- .parts = gumstix_partitions,
- .nr_parts = ARRAY_SIZE(gumstix_partitions),
- .width = 2,
-};
-
-static struct platform_device gumstix_flash_device = {
- .name = "pxa2xx-flash",
- .id = 0,
- .dev = {
- .platform_data = &gumstix_flash_data,
- },
- .resource = &flash_resource,
- .num_resources = 1,
-};
-
-static struct platform_device *devices[] __initdata = {
- &gumstix_flash_device,
-};
-
-#ifdef CONFIG_MMC_PXA
-static struct pxamci_platform_data gumstix_mci_platform_data = {
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
-};
-
-static void __init gumstix_mmc_init(void)
-{
- pxa_set_mci_info(&gumstix_mci_platform_data, NULL);
-}
-#else
-static void __init gumstix_mmc_init(void)
-{
- pr_debug("Gumstix mmc disabled\n");
-}
-#endif
-
-#if IS_ENABLED(CONFIG_USB_PXA25X)
-static const struct property_entry gumstix_vbus_props[] __initconst = {
- PROPERTY_ENTRY_GPIO("vbus-gpios", &pxa2xx_gpiochip_node,
- GPIO_GUMSTIX_USB_GPIOn, GPIO_ACTIVE_HIGH),
- PROPERTY_ENTRY_GPIO("pullup-gpios", &pxa2xx_gpiochip_node,
- GPIO_GUMSTIX_USB_GPIOx, GPIO_ACTIVE_HIGH),
- { }
-};
-
-static const struct platform_device_info gumstix_gpio_vbus_info __initconst = {
- .name = "gpio-vbus",
- .id = PLATFORM_DEVID_NONE,
- .properties = gumstix_vbus_props,
-};
-
-static void __init gumstix_udc_init(void)
-{
- platform_device_register_full(&gumstix_gpio_vbus_info);
-}
-#else
-static void gumstix_udc_init(void)
-{
- pr_debug("Gumstix udc is disabled\n");
-}
-#endif
-
-#ifdef CONFIG_BT
-/* Normally, the bootloader would have enabled this 32kHz clock but many
-** boards still have u-boot 1.1.4 so we check if it has been turned on and
-** if not, we turn it on with a warning message. */
-static void gumstix_setup_bt_clock(void)
-{
- int timeout = 500;
-
- if (!(readl(OSCC) & OSCC_OOK))
- pr_warn("32kHz clock was not on. Bootloader may need to be updated\n");
- else
- return;
-
- writel(readl(OSCC) | OSCC_OON, OSCC);
- do {
- if (readl(OSCC) & OSCC_OOK)
- break;
- udelay(1);
- } while (--timeout);
- if (!timeout)
- pr_err("Failed to start 32kHz clock\n");
-}
-
-static void __init gumstix_bluetooth_init(void)
-{
- int err;
-
- gumstix_setup_bt_clock();
-
- err = gpio_request(GPIO_GUMSTIX_BTRESET, "BTRST");
- if (err) {
- pr_err("gumstix: failed request gpio for bluetooth reset\n");
- return;
- }
-
- err = gpio_direction_output(GPIO_GUMSTIX_BTRESET, 1);
- if (err) {
- pr_err("gumstix: can't reset bluetooth\n");
- return;
- }
- gpio_set_value(GPIO_GUMSTIX_BTRESET, 0);
- udelay(100);
- gpio_set_value(GPIO_GUMSTIX_BTRESET, 1);
-}
-#else
-static void gumstix_bluetooth_init(void)
-{
- pr_debug("Gumstix Bluetooth is disabled\n");
-}
-#endif
-
-static unsigned long gumstix_pin_config[] __initdata = {
- GPIO12_32KHz,
- /* BTUART */
- GPIO42_HWUART_RXD,
- GPIO43_HWUART_TXD,
- GPIO44_HWUART_CTS,
- GPIO45_HWUART_RTS,
- /* MMC */
- GPIO6_MMC_CLK,
- GPIO53_MMC_CLK,
- GPIO8_MMC_CS0,
-};
-
-int __attribute__((weak)) am200_init(void)
-{
- return 0;
-}
-
-int __attribute__((weak)) am300_init(void)
-{
- return 0;
-}
-
-static void __init carrier_board_init(void)
-{
- /*
- * put carrier/expansion board init here if
- * they cannot be detected programatically
- */
- am200_init();
- am300_init();
-}
-
-static void __init gumstix_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(gumstix_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
- pxa_set_hwuart_info(NULL);
-
- gumstix_bluetooth_init();
- gumstix_udc_init();
- gumstix_mmc_init();
- (void) platform_add_devices(devices, ARRAY_SIZE(devices));
- carrier_board_init();
-}
-
-MACHINE_START(GUMSTIX, "Gumstix")
- .atag_offset = 0x100, /* match u-boot bi_boot_params */
- .map_io = pxa25x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .init_time = pxa_timer_init,
- .init_machine = gumstix_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/gumstix.h b/arch/arm/mach-pxa/gumstix.h
deleted file mode 100644
index 9005b3c0aabd..000000000000
--- a/arch/arm/mach-pxa/gumstix.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-pxa/include/mach/gumstix.h
- */
-
-#include "irqs.h" /* PXA_GPIO_TO_IRQ */
-
-/* BTRESET - Reset line to Bluetooth module, active low signal. */
-#define GPIO_GUMSTIX_BTRESET 7
-#define GPIO_GUMSTIX_BTRESET_MD (GPIO_GUMSTIX_BTRESET | GPIO_OUT)
-
-
-/*
-GPIOn - Input from MAX823 (or equiv), normalizing USB +5V into a clean
-interrupt signal for determining cable presence. On the gumstix F,
-this moves to GPIO17 and GPIO37. */
-
-/* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn
-has detected a cable insertion; driven low otherwise. */
-
-#define GPIO_GUMSTIX_USB_GPIOn 35
-#define GPIO_GUMSTIX_USB_GPIOx 41
-
-/* usb state change */
-#define GUMSTIX_USB_INTR_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_USB_GPIOn)
-
-#define GPIO_GUMSTIX_USB_GPIOn_MD (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN)
-#define GPIO_GUMSTIX_USB_GPIOx_CON_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT)
-#define GPIO_GUMSTIX_USB_GPIOx_DIS_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_IN)
-
-/*
- * SD/MMC definitions
- */
-#define GUMSTIX_GPIO_nSD_WP 22 /* SD Write Protect */
-#define GUMSTIX_GPIO_nSD_DETECT 11 /* MMC/SD Card Detect */
-#define GUMSTIX_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(GUMSTIX_GPIO_nSD_DETECT)
-
-/*
- * SMC Ethernet definitions
- * ETH_RST provides a hardware reset line to the ethernet chip
- * ETH is the IRQ line in from the ethernet chip to the PXA
- */
-#define GPIO_GUMSTIX_ETH0_RST 80
-#define GPIO_GUMSTIX_ETH0_RST_MD (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT)
-#define GPIO_GUMSTIX_ETH1_RST 52
-#define GPIO_GUMSTIX_ETH1_RST_MD (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT)
-
-#define GPIO_GUMSTIX_ETH0 36
-#define GPIO_GUMSTIX_ETH0_MD (GPIO_GUMSTIX_ETH0 | GPIO_IN)
-#define GUMSTIX_ETH0_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0)
-#define GPIO_GUMSTIX_ETH1 27
-#define GPIO_GUMSTIX_ETH1_MD (GPIO_GUMSTIX_ETH1 | GPIO_IN)
-#define GUMSTIX_ETH1_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH1)
-
-
-/* CF reset line */
-#define GPIO8_RESET 8
-
-/* CF slot 0 */
-#define GPIO4_nBVD1 4
-#define GPIO4_nSTSCHG GPIO4_nBVD1
-#define GPIO11_nCD 11
-#define GPIO26_PRDY_nBSY 26
-#define GUMSTIX_S0_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO4_nSTSCHG)
-#define GUMSTIX_S0_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO11_nCD)
-#define GUMSTIX_S0_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO26_PRDY_nBSY)
-
-/* CF slot 1 */
-#define GPIO18_nBVD1 18
-#define GPIO18_nSTSCHG GPIO18_nBVD1
-#define GPIO36_nCD 36
-#define GPIO27_PRDY_nBSY 27
-#define GUMSTIX_S1_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO18_nSTSCHG)
-#define GUMSTIX_S1_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO36_nCD)
-#define GUMSTIX_S1_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO27_PRDY_nBSY)
-
-/* CF GPIO line modes */
-#define GPIO4_nSTSCHG_MD (GPIO4_nSTSCHG | GPIO_IN)
-#define GPIO8_RESET_MD (GPIO8_RESET | GPIO_OUT)
-#define GPIO11_nCD_MD (GPIO11_nCD | GPIO_IN)
-#define GPIO18_nSTSCHG_MD (GPIO18_nSTSCHG | GPIO_IN)
-#define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN)
-#define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN)
-#define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN)
-
-/* for expansion boards that can't be programatically detected */
-extern int am200_init(void);
-extern int am300_init(void);
-
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index a273f0af095e..de6a306cf0e2 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -25,7 +25,6 @@
#include <linux/syscore_ops.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
-#include <linux/platform_data/mmp_dma.h>
#include <linux/soc/pxa/cpu.h>
#include <linux/soc/pxa/smemc.h>
@@ -39,7 +38,6 @@
#include "smemc.h"
#include "generic.h"
-#include "devices.h"
/*
* Various clock factors driven by the CCCR register.
@@ -178,53 +176,6 @@ void __init pxa25x_map_io(void)
pxa25x_get_clk_frequency_khz(1);
}
-static struct platform_device *pxa25x_devices[] __initdata = {
- &pxa25x_device_gpio,
- &pxa25x_device_udc,
- &pxa_device_pmu,
- &pxa_device_i2s,
- &sa1100_device_rtc,
- &pxa25x_device_ssp,
- &pxa25x_device_nssp,
- &pxa25x_device_assp,
- &pxa25x_device_pwm0,
- &pxa25x_device_pwm1,
- &pxa_device_asoc_platform,
-};
-
-static const struct dma_slave_map pxa25x_slave_map[] = {
- /* PXA25x, PXA27x and PXA3xx common entries */
- { "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) },
- { "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) },
- { "pxa2xx-ac97", "pcm_pcm_aux_mono_out",
- PDMA_FILTER_PARAM(LOWEST, 10) },
- { "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) },
- { "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) },
- { "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
- { "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
- { "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
- { "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
- { "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) },
- { "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) },
- { "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) },
- { "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) },
-
- /* PXA25x specific map */
- { "pxa25x-ssp.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
- { "pxa25x-ssp.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
- { "pxa25x-nssp.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
- { "pxa25x-nssp.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
- { "pxa25x-nssp.2", "rx", PDMA_FILTER_PARAM(LOWEST, 23) },
- { "pxa25x-nssp.2", "tx", PDMA_FILTER_PARAM(LOWEST, 24) },
-};
-
-static struct mmp_dma_platdata pxa25x_dma_pdata = {
- .dma_channels = 16,
- .nb_requestors = 40,
- .slave_map = pxa25x_slave_map,
- .slave_map_cnt = ARRAY_SIZE(pxa25x_slave_map),
-};
-
static int __init pxa25x_init(void)
{
int ret = 0;
@@ -237,16 +188,6 @@ static int __init pxa25x_init(void)
register_syscore(&pxa_irq_syscore);
register_syscore(&pxa2xx_mfp_syscore);
-
- if (!of_have_populated_dt()) {
- software_node_register(&pxa2xx_gpiochip_node);
- pxa25x_device_gpio.dev.fwnode = software_node_fwnode(
- &pxa2xx_gpiochip_node);
-
- pxa2xx_set_dmac_info(&pxa25x_dma_pdata);
- ret = platform_add_devices(pxa25x_devices,
- ARRAY_SIZE(pxa25x_devices));
- }
}
return ret;
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 814e0a12f38a..617af225628b 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -21,8 +21,6 @@
#include <linux/syscore_ops.h>
#include <linux/io.h>
#include <linux/irq.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/platform_data/mmp_dma.h>
#include <linux/soc/pxa/cpu.h>
#include <linux/soc/pxa/smemc.h>
@@ -33,14 +31,12 @@
#include "pxa27x.h"
#include "reset.h"
#include <linux/platform_data/pxa2xx_udc.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
#include <linux/platform_data/asoc-pxa.h>
#include "pm.h"
#include "addr-map.h"
#include "smemc.h"
#include "generic.h"
-#include "devices.h"
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
@@ -272,90 +268,17 @@ void __init pxa27x_map_io(void)
pxa27x_get_clk_frequency_khz(1);
}
-/*
- * device registration specific to PXA27x.
- */
-void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
-{
- local_irq_disable();
- PCFR |= PCFR_PI2CEN;
- local_irq_enable();
- pxa_register_device(&pxa27x_device_i2c_power, info);
-}
-
-static struct platform_device *devices[] __initdata = {
- &pxa27x_device_gpio,
- &pxa27x_device_udc,
- &pxa_device_pmu,
- &pxa_device_i2s,
- &pxa_device_asoc_ssp1,
- &pxa_device_asoc_ssp2,
- &pxa_device_asoc_ssp3,
- &pxa_device_asoc_platform,
- &pxa_device_rtc,
- &pxa27x_device_ssp1,
- &pxa27x_device_ssp2,
- &pxa27x_device_ssp3,
- &pxa27x_device_pwm0,
- &pxa27x_device_pwm1,
-};
-
-static const struct dma_slave_map pxa27x_slave_map[] = {
- /* PXA25x, PXA27x and PXA3xx common entries */
- { "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) },
- { "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) },
- { "pxa2xx-ac97", "pcm_pcm_aux_mono_out",
- PDMA_FILTER_PARAM(LOWEST, 10) },
- { "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) },
- { "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) },
- { "pxa-ssp-dai.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
- { "pxa-ssp-dai.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
- { "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
- { "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
- { "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) },
- { "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) },
- { "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) },
- { "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) },
- { "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 66) },
- { "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 67) },
-
- /* PXA27x specific map */
- { "pxa2xx-i2s", "rx", PDMA_FILTER_PARAM(LOWEST, 2) },
- { "pxa2xx-i2s", "tx", PDMA_FILTER_PARAM(LOWEST, 3) },
- { "pxa27x-camera.0", "CI_Y", PDMA_FILTER_PARAM(HIGHEST, 68) },
- { "pxa27x-camera.0", "CI_U", PDMA_FILTER_PARAM(HIGHEST, 69) },
- { "pxa27x-camera.0", "CI_V", PDMA_FILTER_PARAM(HIGHEST, 70) },
-};
-
-static struct mmp_dma_platdata pxa27x_dma_pdata = {
- .dma_channels = 32,
- .nb_requestors = 75,
- .slave_map = pxa27x_slave_map,
- .slave_map_cnt = ARRAY_SIZE(pxa27x_slave_map),
-};
-
static int __init pxa27x_init(void)
{
int ret = 0;
if (cpu_is_pxa27x()) {
-
pxa_register_wdt(RCSR);
pxa27x_init_pm();
register_syscore(&pxa_irq_syscore);
register_syscore(&pxa2xx_mfp_syscore);
-
- if (!of_have_populated_dt()) {
- software_node_register(&pxa2xx_gpiochip_node);
- pxa27x_device_gpio.dev.fwnode = software_node_fwnode(
- &pxa2xx_gpiochip_node);
-
- pxa2xx_set_dmac_info(&pxa27x_dma_pdata);
- ret = platform_add_devices(devices,
- ARRAY_SIZE(devices));
- }
}
return ret;
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
index f77ec118d5b9..0022bf235114 100644
--- a/arch/arm/mach-pxa/pxa300.c
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -19,7 +19,6 @@
#include "pxa300.h"
#include "generic.h"
-#include "devices.h"
static struct mfp_addr_map pxa300_mfp_addr_map[] __initdata = {
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
index e372e6c118de..2e84afd94467 100644
--- a/arch/arm/mach-pxa/pxa320.c
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -19,7 +19,6 @@
#include "pxa320.h"
#include "generic.h"
-#include "devices.h"
static struct mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 06c578ea658e..46f4efdfb514 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -10,11 +10,9 @@
* initial version
*/
#include <linux/dmaengine.h>
-#include <linux/dma/pxa-dma.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
-#include <linux/gpio-pxa.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
@@ -22,8 +20,6 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/syscore_ops.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/platform_data/mmp_dma.h>
#include <linux/soc/pxa/cpu.h>
#include <linux/clk/pxa.h>
@@ -31,14 +27,12 @@
#include <asm/suspend.h>
#include "pxa3xx-regs.h"
#include "reset.h"
-#include <linux/platform_data/usb-ohci-pxa27x.h>
#include "pm.h"
#include "addr-map.h"
#include "smemc.h"
#include "irqs.h"
#include "generic.h"
-#include "devices.h"
#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
deleted file mode 100644
index a611eea70e5a..000000000000
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ /dev/null
@@ -1,941 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Battery and Power Management code for the Sharp SL-C7xx and SL-Cxx00
- * series of PDAs
- *
- * Copyright (c) 2004-2005 Richard Purdie
- *
- * Based on code written by Sharp for 2.4 kernels
- */
-
-#undef DEBUG
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/apm-emulation.h>
-#include <linux/timer.h>
-#include <linux/delay.h>
-#include <linux/leds.h>
-#include <linux/suspend.h>
-#include <linux/gpio/legacy.h>
-#include <linux/io.h>
-
-#include <asm/mach-types.h>
-#include "pm.h"
-#include "pxa2xx-regs.h"
-#include "regs-rtc.h"
-#include "sharpsl_pm.h"
-
-/*
- * Constants
- */
-#define SHARPSL_CHARGE_ON_TIME_INTERVAL (secs_to_jiffies(60))
-#define SHARPSL_CHARGE_FINISH_TIME (secs_to_jiffies(10*60))
-#define SHARPSL_BATCHK_TIME (secs_to_jiffies(15))
-#define SHARPSL_BATCHK_TIME_SUSPEND (60*10) /* 10 min */
-
-#define SHARPSL_WAIT_CO_TIME 15 /* 15 sec */
-#define SHARPSL_WAIT_DISCHARGE_ON 100 /* 100 msec */
-#define SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP 10 /* 10 msec */
-#define SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT 10 /* 10 msec */
-#define SHARPSL_CHECK_BATTERY_WAIT_TIME_ACIN 10 /* 10 msec */
-#define SHARPSL_CHARGE_WAIT_TIME 15 /* 15 msec */
-#define SHARPSL_CHARGE_CO_CHECK_TIME 5 /* 5 msec */
-#define SHARPSL_CHARGE_RETRY_CNT 1 /* eqv. 10 min */
-
-/*
- * Prototypes
- */
-#ifdef CONFIG_PM
-static int sharpsl_off_charge_battery(void);
-static int sharpsl_check_battery_voltage(void);
-#endif
-static int sharpsl_check_battery_temp(void);
-static int sharpsl_ac_check(void);
-static int sharpsl_average_value(int ad);
-static void sharpsl_average_clear(void);
-static void sharpsl_charge_toggle(struct work_struct *private_);
-static void sharpsl_battery_thread(struct work_struct *private_);
-
-
-/*
- * Variables
- */
-struct sharpsl_pm_status sharpsl_pm;
-static DECLARE_DELAYED_WORK(toggle_charger, sharpsl_charge_toggle);
-static DECLARE_DELAYED_WORK(sharpsl_bat, sharpsl_battery_thread);
-DEFINE_LED_TRIGGER(sharpsl_charge_led_trigger);
-
-
-
-struct battery_thresh sharpsl_battery_levels_acin[] = {
- { 213, 100},
- { 212, 98},
- { 211, 95},
- { 210, 93},
- { 209, 90},
- { 208, 88},
- { 207, 85},
- { 206, 83},
- { 205, 80},
- { 204, 78},
- { 203, 75},
- { 202, 73},
- { 201, 70},
- { 200, 68},
- { 199, 65},
- { 198, 63},
- { 197, 60},
- { 196, 58},
- { 195, 55},
- { 194, 53},
- { 193, 50},
- { 192, 48},
- { 192, 45},
- { 191, 43},
- { 191, 40},
- { 190, 38},
- { 190, 35},
- { 189, 33},
- { 188, 30},
- { 187, 28},
- { 186, 25},
- { 185, 23},
- { 184, 20},
- { 183, 18},
- { 182, 15},
- { 181, 13},
- { 180, 10},
- { 179, 8},
- { 178, 5},
- { 0, 0},
-};
-
-struct battery_thresh sharpsl_battery_levels_noac[] = {
- { 213, 100},
- { 212, 98},
- { 211, 95},
- { 210, 93},
- { 209, 90},
- { 208, 88},
- { 207, 85},
- { 206, 83},
- { 205, 80},
- { 204, 78},
- { 203, 75},
- { 202, 73},
- { 201, 70},
- { 200, 68},
- { 199, 65},
- { 198, 63},
- { 197, 60},
- { 196, 58},
- { 195, 55},
- { 194, 53},
- { 193, 50},
- { 192, 48},
- { 191, 45},
- { 190, 43},
- { 189, 40},
- { 188, 38},
- { 187, 35},
- { 186, 33},
- { 185, 30},
- { 184, 28},
- { 183, 25},
- { 182, 23},
- { 181, 20},
- { 180, 18},
- { 179, 15},
- { 178, 13},
- { 177, 10},
- { 176, 8},
- { 175, 5},
- { 0, 0},
-};
-
-/* MAX1111 Commands */
-#define MAXCTRL_PD0 (1u << 0)
-#define MAXCTRL_PD1 (1u << 1)
-#define MAXCTRL_SGL (1u << 2)
-#define MAXCTRL_UNI (1u << 3)
-#define MAXCTRL_SEL_SH 4
-#define MAXCTRL_STR (1u << 7)
-
-extern int max1111_read_channel(int);
-/*
- * Read MAX1111 ADC
- */
-int sharpsl_pm_pxa_read_max1111(int channel)
-{
- /* max1111 accepts channels from 0-3, however,
- * it is encoded from 0-7 here in the code.
- */
- return max1111_read_channel(channel >> 1);
-}
-
-static int get_percentage(int voltage)
-{
- int i = sharpsl_pm.machinfo->bat_levels - 1;
- int bl_status = sharpsl_pm.machinfo->backlight_get_status ? sharpsl_pm.machinfo->backlight_get_status() : 0;
- struct battery_thresh *thresh;
-
- if (sharpsl_pm.charge_mode == CHRG_ON)
- thresh = bl_status ? sharpsl_pm.machinfo->bat_levels_acin_bl : sharpsl_pm.machinfo->bat_levels_acin;
- else
- thresh = bl_status ? sharpsl_pm.machinfo->bat_levels_noac_bl : sharpsl_pm.machinfo->bat_levels_noac;
-
- while (i > 0 && (voltage > thresh[i].voltage))
- i--;
-
- return thresh[i].percentage;
-}
-
-static int get_apm_status(int voltage)
-{
- int low_thresh, high_thresh;
-
- if (sharpsl_pm.charge_mode == CHRG_ON) {
- high_thresh = sharpsl_pm.machinfo->status_high_acin;
- low_thresh = sharpsl_pm.machinfo->status_low_acin;
- } else {
- high_thresh = sharpsl_pm.machinfo->status_high_noac;
- low_thresh = sharpsl_pm.machinfo->status_low_noac;
- }
-
- if (voltage >= high_thresh)
- return APM_BATTERY_STATUS_HIGH;
- if (voltage >= low_thresh)
- return APM_BATTERY_STATUS_LOW;
- return APM_BATTERY_STATUS_CRITICAL;
-}
-
-void sharpsl_battery_kick(void)
-{
- schedule_delayed_work(&sharpsl_bat, msecs_to_jiffies(125));
-}
-
-static void sharpsl_battery_thread(struct work_struct *private_)
-{
- int voltage, percent, apm_status, i;
-
- if (!sharpsl_pm.machinfo)
- return;
-
- sharpsl_pm.battstat.ac_status = (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN) ? APM_AC_ONLINE : APM_AC_OFFLINE);
-
- /* Corgi cannot confirm when battery fully charged so periodically kick! */
- if (!sharpsl_pm.machinfo->batfull_irq && (sharpsl_pm.charge_mode == CHRG_ON)
- && time_after(jiffies, sharpsl_pm.charge_start_time + SHARPSL_CHARGE_ON_TIME_INTERVAL))
- schedule_delayed_work(&toggle_charger, 0);
-
- for (i = 0; i < 5; i++) {
- voltage = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT);
- if (voltage > 0)
- break;
- }
- if (voltage <= 0) {
- voltage = sharpsl_pm.machinfo->bat_levels_noac[0].voltage;
- dev_warn(sharpsl_pm.dev, "Warning: Cannot read main battery!\n");
- }
-
- voltage = sharpsl_average_value(voltage);
- apm_status = get_apm_status(voltage);
- percent = get_percentage(voltage);
-
- /* At low battery voltages, the voltage has a tendency to start
- creeping back up so we try to avoid this here */
- if ((sharpsl_pm.battstat.ac_status == APM_AC_ONLINE)
- || (apm_status == APM_BATTERY_STATUS_HIGH)
- || percent <= sharpsl_pm.battstat.mainbat_percent) {
- sharpsl_pm.battstat.mainbat_voltage = voltage;
- sharpsl_pm.battstat.mainbat_status = apm_status;
- sharpsl_pm.battstat.mainbat_percent = percent;
- }
-
- dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage,
- sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies);
-
- /* Suspend if critical battery level */
- if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
- && (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL)
- && !(sharpsl_pm.flags & SHARPSL_APM_QUEUED)) {
- sharpsl_pm.flags |= SHARPSL_APM_QUEUED;
- dev_err(sharpsl_pm.dev, "Fatal Off\n");
- apm_queue_event(APM_CRITICAL_SUSPEND);
- }
-
- schedule_delayed_work(&sharpsl_bat, SHARPSL_BATCHK_TIME);
-}
-
-void sharpsl_pm_led(int val)
-{
- if (val == SHARPSL_LED_ERROR) {
- dev_err(sharpsl_pm.dev, "Charging Error!\n");
- } else if (val == SHARPSL_LED_ON) {
- dev_dbg(sharpsl_pm.dev, "Charge LED On\n");
- led_trigger_event(sharpsl_charge_led_trigger, LED_FULL);
- } else {
- dev_dbg(sharpsl_pm.dev, "Charge LED Off\n");
- led_trigger_event(sharpsl_charge_led_trigger, LED_OFF);
- }
-}
-
-static void sharpsl_charge_on(void)
-{
- dev_dbg(sharpsl_pm.dev, "Turning Charger On\n");
-
- sharpsl_pm.full_count = 0;
- sharpsl_pm.charge_mode = CHRG_ON;
- schedule_delayed_work(&toggle_charger, msecs_to_jiffies(250));
- schedule_delayed_work(&sharpsl_bat, msecs_to_jiffies(500));
-}
-
-static void sharpsl_charge_off(void)
-{
- dev_dbg(sharpsl_pm.dev, "Turning Charger Off\n");
-
- sharpsl_pm.machinfo->charge(0);
- sharpsl_pm_led(SHARPSL_LED_OFF);
- sharpsl_pm.charge_mode = CHRG_OFF;
-
- schedule_delayed_work(&sharpsl_bat, 0);
-}
-
-static void sharpsl_charge_error(void)
-{
- sharpsl_pm_led(SHARPSL_LED_ERROR);
- sharpsl_pm.machinfo->charge(0);
- sharpsl_pm.charge_mode = CHRG_ERROR;
-}
-
-static void sharpsl_charge_toggle(struct work_struct *private_)
-{
- dev_dbg(sharpsl_pm.dev, "Toggling Charger at time: %lx\n", jiffies);
-
- if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN)) {
- sharpsl_charge_off();
- return;
- } else if ((sharpsl_check_battery_temp() < 0) || (sharpsl_ac_check() < 0)) {
- sharpsl_charge_error();
- return;
- }
-
- sharpsl_pm_led(SHARPSL_LED_ON);
- sharpsl_pm.machinfo->charge(0);
- mdelay(SHARPSL_CHARGE_WAIT_TIME);
- sharpsl_pm.machinfo->charge(1);
-
- sharpsl_pm.charge_start_time = jiffies;
-}
-
-static void sharpsl_ac_timer(struct timer_list *unused)
-{
- int acin = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN);
-
- dev_dbg(sharpsl_pm.dev, "AC Status: %d\n", acin);
-
- sharpsl_average_clear();
- if (acin && (sharpsl_pm.charge_mode != CHRG_ON))
- sharpsl_charge_on();
- else if (sharpsl_pm.charge_mode == CHRG_ON)
- sharpsl_charge_off();
-
- schedule_delayed_work(&sharpsl_bat, 0);
-}
-
-
-static irqreturn_t sharpsl_ac_isr(int irq, void *dev_id)
-{
- /* Delay the event slightly to debounce */
- /* Must be a smaller delay than the chrg_full_isr below */
- mod_timer(&sharpsl_pm.ac_timer, jiffies + msecs_to_jiffies(250));
-
- return IRQ_HANDLED;
-}
-
-static void sharpsl_chrg_full_timer(struct timer_list *unused)
-{
- dev_dbg(sharpsl_pm.dev, "Charge Full at time: %lx\n", jiffies);
-
- sharpsl_pm.full_count++;
-
- if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN)) {
- dev_dbg(sharpsl_pm.dev, "Charge Full: AC removed - stop charging!\n");
- if (sharpsl_pm.charge_mode == CHRG_ON)
- sharpsl_charge_off();
- } else if (sharpsl_pm.full_count < 2) {
- dev_dbg(sharpsl_pm.dev, "Charge Full: Count too low\n");
- schedule_delayed_work(&toggle_charger, 0);
- } else if (time_after(jiffies, sharpsl_pm.charge_start_time + SHARPSL_CHARGE_FINISH_TIME)) {
- dev_dbg(sharpsl_pm.dev, "Charge Full: Interrupt generated too slowly - retry.\n");
- schedule_delayed_work(&toggle_charger, 0);
- } else {
- sharpsl_charge_off();
- sharpsl_pm.charge_mode = CHRG_DONE;
- dev_dbg(sharpsl_pm.dev, "Charge Full: Charging Finished\n");
- }
-}
-
-/* Charging Finished Interrupt (Not present on Corgi) */
-/* Can trigger at the same time as an AC status change so
- delay until after that has been processed */
-static irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id)
-{
- if (sharpsl_pm.flags & SHARPSL_SUSPENDED)
- return IRQ_HANDLED;
-
- /* delay until after any ac interrupt */
- mod_timer(&sharpsl_pm.chrg_full_timer, jiffies + msecs_to_jiffies(500));
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t sharpsl_fatal_isr(int irq, void *dev_id)
-{
- int is_fatal = 0;
-
- if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_LOCK)) {
- dev_err(sharpsl_pm.dev, "Battery now Unlocked! Suspending.\n");
- is_fatal = 1;
- }
-
- if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_FATAL)) {
- dev_err(sharpsl_pm.dev, "Fatal Batt Error! Suspending.\n");
- is_fatal = 1;
- }
-
- if (!(sharpsl_pm.flags & SHARPSL_APM_QUEUED) && is_fatal) {
- sharpsl_pm.flags |= SHARPSL_APM_QUEUED;
- apm_queue_event(APM_CRITICAL_SUSPEND);
- }
-
- return IRQ_HANDLED;
-}
-
-/*
- * Maintain an average of the last 10 readings
- */
-#define SHARPSL_CNV_VALUE_NUM 10
-static int sharpsl_ad_index;
-
-static void sharpsl_average_clear(void)
-{
- sharpsl_ad_index = 0;
-}
-
-static int sharpsl_average_value(int ad)
-{
- int i, ad_val = 0;
- static int sharpsl_ad[SHARPSL_CNV_VALUE_NUM+1];
-
- if (sharpsl_pm.battstat.mainbat_status != APM_BATTERY_STATUS_HIGH) {
- sharpsl_ad_index = 0;
- return ad;
- }
-
- sharpsl_ad[sharpsl_ad_index] = ad;
- sharpsl_ad_index++;
- if (sharpsl_ad_index >= SHARPSL_CNV_VALUE_NUM) {
- for (i = 0; i < (SHARPSL_CNV_VALUE_NUM-1); i++)
- sharpsl_ad[i] = sharpsl_ad[i+1];
- sharpsl_ad_index = SHARPSL_CNV_VALUE_NUM - 1;
- }
- for (i = 0; i < sharpsl_ad_index; i++)
- ad_val += sharpsl_ad[i];
-
- return ad_val / sharpsl_ad_index;
-}
-
-/*
- * Take an array of 5 integers, remove the maximum and minimum values
- * and return the average.
- */
-static int get_select_val(int *val)
-{
- int i, j, k, temp, sum = 0;
-
- /* Find MAX val */
- temp = val[0];
- j = 0;
- for (i = 1; i < 5; i++) {
- if (temp < val[i]) {
- temp = val[i];
- j = i;
- }
- }
-
- /* Find MIN val */
- temp = val[4];
- k = 4;
- for (i = 3; i >= 0; i--) {
- if (temp > val[i]) {
- temp = val[i];
- k = i;
- }
- }
-
- for (i = 0; i < 5; i++)
- if (i != j && i != k)
- sum += val[i];
-
- dev_dbg(sharpsl_pm.dev, "Average: %d from values: %d, %d, %d, %d, %d\n", sum/3, val[0], val[1], val[2], val[3], val[4]);
-
- return sum/3;
-}
-
-static int sharpsl_check_battery_temp(void)
-{
- int val, i, buff[5];
-
- /* Check battery temperature */
- for (i = 0; i < 5; i++) {
- mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP);
- sharpsl_pm.machinfo->measure_temp(1);
- mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP);
- buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_TEMP);
- sharpsl_pm.machinfo->measure_temp(0);
- }
-
- val = get_select_val(buff);
-
- dev_dbg(sharpsl_pm.dev, "Temperature: %d\n", val);
- if (val > sharpsl_pm.machinfo->charge_on_temp) {
- printk(KERN_WARNING "Not charging: temperature out of limits.\n");
- return -1;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int sharpsl_check_battery_voltage(void)
-{
- int val, i, buff[5];
-
- /* disable charge, enable discharge */
- sharpsl_pm.machinfo->charge(0);
- sharpsl_pm.machinfo->discharge(1);
- mdelay(SHARPSL_WAIT_DISCHARGE_ON);
-
- if (sharpsl_pm.machinfo->discharge1)
- sharpsl_pm.machinfo->discharge1(1);
-
- /* Check battery voltage */
- for (i = 0; i < 5; i++) {
- buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT);
- mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT);
- }
-
- if (sharpsl_pm.machinfo->discharge1)
- sharpsl_pm.machinfo->discharge1(0);
-
- sharpsl_pm.machinfo->discharge(0);
-
- val = get_select_val(buff);
- dev_dbg(sharpsl_pm.dev, "Battery Voltage: %d\n", val);
-
- if (val < sharpsl_pm.machinfo->charge_on_volt)
- return -1;
-
- return 0;
-}
-#endif
-
-static int sharpsl_ac_check(void)
-{
- int temp, i, buff[5];
-
- for (i = 0; i < 5; i++) {
- buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_ACIN_VOLT);
- mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_ACIN);
- }
-
- temp = get_select_val(buff);
- dev_dbg(sharpsl_pm.dev, "AC Voltage: %d\n", temp);
-
- if ((temp > sharpsl_pm.machinfo->charge_acin_high) || (temp < sharpsl_pm.machinfo->charge_acin_low)) {
- dev_err(sharpsl_pm.dev, "Error: AC check failed: voltage %d.\n", temp);
- return -1;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int sharpsl_pm_suspend(struct platform_device *pdev, pm_message_t state)
-{
- sharpsl_pm.flags |= SHARPSL_SUSPENDED;
- flush_delayed_work(&toggle_charger);
- flush_delayed_work(&sharpsl_bat);
-
- if (sharpsl_pm.charge_mode == CHRG_ON)
- sharpsl_pm.flags |= SHARPSL_DO_OFFLINE_CHRG;
- else
- sharpsl_pm.flags &= ~SHARPSL_DO_OFFLINE_CHRG;
-
- return 0;
-}
-
-static int sharpsl_pm_resume(struct platform_device *pdev)
-{
- /* Clear the reset source indicators as they break the bootloader upon reboot */
- RCSR = 0x0f;
- sharpsl_average_clear();
- sharpsl_pm.flags &= ~SHARPSL_APM_QUEUED;
- sharpsl_pm.flags &= ~SHARPSL_SUSPENDED;
-
- return 0;
-}
-
-static void corgi_goto_sleep(unsigned long alarm_time, unsigned int alarm_enable, suspend_state_t state)
-{
- dev_dbg(sharpsl_pm.dev, "Time is: %08x\n", RCNR);
-
- dev_dbg(sharpsl_pm.dev, "Offline Charge Activate = %d\n", sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG);
- /* not charging and AC-IN! */
-
- if ((sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG) && (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN))) {
- dev_dbg(sharpsl_pm.dev, "Activating Offline Charger...\n");
- sharpsl_pm.charge_mode = CHRG_OFF;
- sharpsl_pm.flags &= ~SHARPSL_DO_OFFLINE_CHRG;
- sharpsl_off_charge_battery();
- }
-
- sharpsl_pm.machinfo->presuspend();
-
- PEDR = 0xffffffff; /* clear it */
-
- sharpsl_pm.flags &= ~SHARPSL_ALARM_ACTIVE;
- if ((sharpsl_pm.charge_mode == CHRG_ON) && ((alarm_enable && ((alarm_time - RCNR) > (SHARPSL_BATCHK_TIME_SUSPEND + 30))) || !alarm_enable)) {
- RTSR &= RTSR_ALE;
- RTAR = RCNR + SHARPSL_BATCHK_TIME_SUSPEND;
- dev_dbg(sharpsl_pm.dev, "Charging alarm at: %08x\n", RTAR);
- sharpsl_pm.flags |= SHARPSL_ALARM_ACTIVE;
- } else if (alarm_enable) {
- RTSR &= RTSR_ALE;
- RTAR = alarm_time;
- dev_dbg(sharpsl_pm.dev, "User alarm at: %08x\n", RTAR);
- } else {
- dev_dbg(sharpsl_pm.dev, "No alarms set.\n");
- }
-
- pxa_pm_enter(state);
-
- sharpsl_pm.machinfo->postsuspend();
-
- dev_dbg(sharpsl_pm.dev, "Corgi woken up from suspend: %08x\n", PEDR);
-}
-
-static int corgi_enter_suspend(unsigned long alarm_time, unsigned int alarm_enable, suspend_state_t state)
-{
- if (!sharpsl_pm.machinfo->should_wakeup(!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE) && alarm_enable)) {
- if (!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE)) {
- dev_dbg(sharpsl_pm.dev, "No user triggered wakeup events and not charging. Strange. Suspend.\n");
- corgi_goto_sleep(alarm_time, alarm_enable, state);
- return 1;
- }
- if (sharpsl_off_charge_battery()) {
- dev_dbg(sharpsl_pm.dev, "Charging. Suspend...\n");
- corgi_goto_sleep(alarm_time, alarm_enable, state);
- return 1;
- }
- dev_dbg(sharpsl_pm.dev, "User triggered wakeup in offline charger.\n");
- }
-
- if ((!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_LOCK)) ||
- (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_FATAL))) {
- dev_err(sharpsl_pm.dev, "Fatal condition. Suspend.\n");
- corgi_goto_sleep(alarm_time, alarm_enable, state);
- return 1;
- }
-
- return 0;
-}
-
-static int corgi_pxa_pm_enter(suspend_state_t state)
-{
- unsigned long alarm_time = RTAR;
- unsigned int alarm_status = ((RTSR & RTSR_ALE) != 0);
-
- dev_dbg(sharpsl_pm.dev, "SharpSL suspending for first time.\n");
-
- corgi_goto_sleep(alarm_time, alarm_status, state);
-
- while (corgi_enter_suspend(alarm_time, alarm_status, state))
- {}
-
- if (sharpsl_pm.machinfo->earlyresume)
- sharpsl_pm.machinfo->earlyresume();
-
- dev_dbg(sharpsl_pm.dev, "SharpSL resuming...\n");
-
- return 0;
-}
-
-static int sharpsl_off_charge_error(void)
-{
- dev_err(sharpsl_pm.dev, "Offline Charger: Error occurred.\n");
- sharpsl_pm.machinfo->charge(0);
- sharpsl_pm_led(SHARPSL_LED_ERROR);
- sharpsl_pm.charge_mode = CHRG_ERROR;
- return 1;
-}
-
-/*
- * Charging Control while suspended
- * Return 1 - go straight to sleep
- * Return 0 - sleep or wakeup depending on other factors
- */
-static int sharpsl_off_charge_battery(void)
-{
- int time;
-
- dev_dbg(sharpsl_pm.dev, "Charge Mode: %d\n", sharpsl_pm.charge_mode);
-
- if (sharpsl_pm.charge_mode == CHRG_OFF) {
- dev_dbg(sharpsl_pm.dev, "Offline Charger: Step 1\n");
-
- /* AC Check */
- if ((sharpsl_ac_check() < 0) || (sharpsl_check_battery_temp() < 0))
- return sharpsl_off_charge_error();
-
- /* Start Charging */
- sharpsl_pm_led(SHARPSL_LED_ON);
- sharpsl_pm.machinfo->charge(0);
- mdelay(SHARPSL_CHARGE_WAIT_TIME);
- sharpsl_pm.machinfo->charge(1);
-
- sharpsl_pm.charge_mode = CHRG_ON;
- sharpsl_pm.full_count = 0;
-
- return 1;
- } else if (sharpsl_pm.charge_mode != CHRG_ON) {
- return 1;
- }
-
- if (sharpsl_pm.full_count == 0) {
- int time;
-
- dev_dbg(sharpsl_pm.dev, "Offline Charger: Step 2\n");
-
- if ((sharpsl_check_battery_temp() < 0) || (sharpsl_check_battery_voltage() < 0))
- return sharpsl_off_charge_error();
-
- sharpsl_pm.machinfo->charge(0);
- mdelay(SHARPSL_CHARGE_WAIT_TIME);
- sharpsl_pm.machinfo->charge(1);
- sharpsl_pm.charge_mode = CHRG_ON;
-
- mdelay(SHARPSL_CHARGE_CO_CHECK_TIME);
-
- time = RCNR;
- while (1) {
- /* Check if any wakeup event had occurred */
- if (sharpsl_pm.machinfo->charger_wakeup())
- return 0;
- /* Check for timeout */
- if ((RCNR - time) > SHARPSL_WAIT_CO_TIME)
- return 1;
- if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) {
- dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occurred. Retrying to check\n");
- sharpsl_pm.full_count++;
- sharpsl_pm.machinfo->charge(0);
- mdelay(SHARPSL_CHARGE_WAIT_TIME);
- sharpsl_pm.machinfo->charge(1);
- return 1;
- }
- }
- }
-
- dev_dbg(sharpsl_pm.dev, "Offline Charger: Step 3\n");
-
- mdelay(SHARPSL_CHARGE_CO_CHECK_TIME);
-
- time = RCNR;
- while (1) {
- /* Check if any wakeup event had occurred */
- if (sharpsl_pm.machinfo->charger_wakeup())
- return 0;
- /* Check for timeout */
- if ((RCNR-time) > SHARPSL_WAIT_CO_TIME) {
- if (sharpsl_pm.full_count > SHARPSL_CHARGE_RETRY_CNT) {
- dev_dbg(sharpsl_pm.dev, "Offline Charger: Not charged sufficiently. Retrying.\n");
- sharpsl_pm.full_count = 0;
- }
- sharpsl_pm.full_count++;
- return 1;
- }
- if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) {
- dev_dbg(sharpsl_pm.dev, "Offline Charger: Charging complete.\n");
- sharpsl_pm_led(SHARPSL_LED_OFF);
- sharpsl_pm.machinfo->charge(0);
- sharpsl_pm.charge_mode = CHRG_DONE;
- return 1;
- }
- }
-}
-#else
-#define sharpsl_pm_suspend NULL
-#define sharpsl_pm_resume NULL
-#endif
-
-static ssize_t battery_percentage_show(struct device *dev, struct device_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", sharpsl_pm.battstat.mainbat_percent);
-}
-
-static ssize_t battery_voltage_show(struct device *dev, struct device_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", sharpsl_pm.battstat.mainbat_voltage);
-}
-
-static DEVICE_ATTR_RO(battery_percentage);
-static DEVICE_ATTR_RO(battery_voltage);
-
-extern void (*apm_get_power_status)(struct apm_power_info *);
-
-static void sharpsl_apm_get_power_status(struct apm_power_info *info)
-{
- info->ac_line_status = sharpsl_pm.battstat.ac_status;
-
- if (sharpsl_pm.charge_mode == CHRG_ON)
- info->battery_status = APM_BATTERY_STATUS_CHARGING;
- else
- info->battery_status = sharpsl_pm.battstat.mainbat_status;
-
- info->battery_flag = (1 << info->battery_status);
- info->battery_life = sharpsl_pm.battstat.mainbat_percent;
-}
-
-#ifdef CONFIG_PM
-static const struct platform_suspend_ops sharpsl_pm_ops = {
- .prepare = pxa_pm_prepare,
- .finish = pxa_pm_finish,
- .enter = corgi_pxa_pm_enter,
- .valid = suspend_valid_only_mem,
-};
-#endif
-
-static int sharpsl_pm_probe(struct platform_device *pdev)
-{
- int ret, irq;
-
- if (!pdev->dev.platform_data)
- return -EINVAL;
-
- sharpsl_pm.dev = &pdev->dev;
- sharpsl_pm.machinfo = pdev->dev.platform_data;
- sharpsl_pm.charge_mode = CHRG_OFF;
- sharpsl_pm.flags = 0;
-
- timer_setup(&sharpsl_pm.ac_timer, sharpsl_ac_timer, 0);
-
- timer_setup(&sharpsl_pm.chrg_full_timer, sharpsl_chrg_full_timer, 0);
-
- led_trigger_register_simple("sharpsl-charge", &sharpsl_charge_led_trigger);
-
- sharpsl_pm.machinfo->init();
-
- gpio_request(sharpsl_pm.machinfo->gpio_acin, "AC IN");
- gpio_direction_input(sharpsl_pm.machinfo->gpio_acin);
- gpio_request(sharpsl_pm.machinfo->gpio_batfull, "Battery Full");
- gpio_direction_input(sharpsl_pm.machinfo->gpio_batfull);
- gpio_request(sharpsl_pm.machinfo->gpio_batlock, "Battery Lock");
- gpio_direction_input(sharpsl_pm.machinfo->gpio_batlock);
-
- /* Register interrupt handlers */
- irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_acin);
- if (request_irq(irq, sharpsl_ac_isr, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) {
- dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
- }
-
- irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_batlock);
- if (request_irq(irq, sharpsl_fatal_isr, IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) {
- dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
- }
-
- if (sharpsl_pm.machinfo->gpio_fatal) {
- irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_fatal);
- if (request_irq(irq, sharpsl_fatal_isr, IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) {
- dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
- }
- }
-
- if (sharpsl_pm.machinfo->batfull_irq) {
- /* Register interrupt handler. */
- irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_batfull);
- if (request_irq(irq, sharpsl_chrg_full_isr, IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) {
- dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
- }
- }
-
- ret = device_create_file(&pdev->dev, &dev_attr_battery_percentage);
- ret |= device_create_file(&pdev->dev, &dev_attr_battery_voltage);
- if (ret != 0)
- dev_warn(&pdev->dev, "Failed to register attributes (%d)\n", ret);
-
- apm_get_power_status = sharpsl_apm_get_power_status;
-
-#ifdef CONFIG_PM
- suspend_set_ops(&sharpsl_pm_ops);
-#endif
-
- mod_timer(&sharpsl_pm.ac_timer, jiffies + msecs_to_jiffies(250));
-
- return 0;
-}
-
-static void sharpsl_pm_remove(struct platform_device *pdev)
-{
- suspend_set_ops(NULL);
-
- device_remove_file(&pdev->dev, &dev_attr_battery_percentage);
- device_remove_file(&pdev->dev, &dev_attr_battery_voltage);
-
- led_trigger_unregister_simple(sharpsl_charge_led_trigger);
-
- free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr);
- free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr);
-
- if (sharpsl_pm.machinfo->gpio_fatal)
- free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr);
-
- if (sharpsl_pm.machinfo->batfull_irq)
- free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr);
-
- gpio_free(sharpsl_pm.machinfo->gpio_batlock);
- gpio_free(sharpsl_pm.machinfo->gpio_batfull);
- gpio_free(sharpsl_pm.machinfo->gpio_acin);
-
- if (sharpsl_pm.machinfo->exit)
- sharpsl_pm.machinfo->exit();
-
- timer_delete_sync(&sharpsl_pm.chrg_full_timer);
- timer_delete_sync(&sharpsl_pm.ac_timer);
-}
-
-static struct platform_driver sharpsl_pm_driver = {
- .probe = sharpsl_pm_probe,
- .remove = sharpsl_pm_remove,
- .suspend = sharpsl_pm_suspend,
- .resume = sharpsl_pm_resume,
- .driver = {
- .name = "sharpsl-pm",
- },
-};
-
-static int sharpsl_pm_init(void)
-{
- return platform_driver_register(&sharpsl_pm_driver);
-}
-
-static void sharpsl_pm_exit(void)
-{
- platform_driver_unregister(&sharpsl_pm_driver);
-}
-
-late_initcall(sharpsl_pm_init);
-module_exit(sharpsl_pm_exit);
diff --git a/arch/arm/mach-pxa/sharpsl_pm.h b/arch/arm/mach-pxa/sharpsl_pm.h
deleted file mode 100644
index 623167f30ec2..000000000000
--- a/arch/arm/mach-pxa/sharpsl_pm.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * SharpSL Battery/PM Driver
- *
- * Copyright (c) 2004-2005 Richard Purdie
- */
-#ifndef _MACH_SHARPSL_PM
-#define _MACH_SHARPSL_PM
-
-struct sharpsl_charger_machinfo {
- void (*init)(void);
- void (*exit)(void);
- int gpio_acin;
- int gpio_batfull;
- int batfull_irq;
- int gpio_batlock;
- int gpio_fatal;
- void (*discharge)(int);
- void (*discharge1)(int);
- void (*charge)(int);
- void (*measure_temp)(int);
- void (*presuspend)(void);
- void (*postsuspend)(void);
- void (*earlyresume)(void);
- unsigned long (*read_devdata)(int);
-#define SHARPSL_BATT_VOLT 1
-#define SHARPSL_BATT_TEMP 2
-#define SHARPSL_ACIN_VOLT 3
-#define SHARPSL_STATUS_ACIN 4
-#define SHARPSL_STATUS_LOCK 5
-#define SHARPSL_STATUS_CHRGFULL 6
-#define SHARPSL_STATUS_FATAL 7
- bool (*charger_wakeup)(void);
- int (*should_wakeup)(unsigned int resume_on_alarm);
- void (*backlight_limit)(int);
- int (*backlight_get_status) (void);
- int charge_on_volt;
- int charge_on_temp;
- int charge_acin_high;
- int charge_acin_low;
- int fatal_acin_volt;
- int fatal_noacin_volt;
- int bat_levels;
- struct battery_thresh *bat_levels_noac;
- struct battery_thresh *bat_levels_acin;
- struct battery_thresh *bat_levels_noac_bl;
- struct battery_thresh *bat_levels_acin_bl;
- int status_high_acin;
- int status_low_acin;
- int status_high_noac;
- int status_low_noac;
-};
-
-struct battery_thresh {
- int voltage;
- int percentage;
-};
-
-struct battery_stat {
- int ac_status; /* APM AC Present/Not Present */
- int mainbat_status; /* APM Main Battery Status */
- int mainbat_percent; /* Main Battery Percentage Charge */
- int mainbat_voltage; /* Main Battery Voltage */
-};
-
-struct sharpsl_pm_status {
- struct device *dev;
- struct timer_list ac_timer;
- struct timer_list chrg_full_timer;
-
- int charge_mode;
-#define CHRG_ERROR (-1)
-#define CHRG_OFF (0)
-#define CHRG_ON (1)
-#define CHRG_DONE (2)
-
- unsigned int flags;
-#define SHARPSL_SUSPENDED (1 << 0) /* Device is Suspended */
-#define SHARPSL_ALARM_ACTIVE (1 << 1) /* Alarm is for charging event (not user) */
-#define SHARPSL_BL_LIMIT (1 << 2) /* Backlight Intensity Limited */
-#define SHARPSL_APM_QUEUED (1 << 3) /* APM Event Queued */
-#define SHARPSL_DO_OFFLINE_CHRG (1 << 4) /* Trigger the offline charger */
-
- int full_count;
- unsigned long charge_start_time;
- struct sharpsl_charger_machinfo *machinfo;
- struct battery_stat battstat;
-};
-
-extern struct sharpsl_pm_status sharpsl_pm;
-
-extern struct battery_thresh sharpsl_battery_levels_acin[];
-extern struct battery_thresh sharpsl_battery_levels_noac[];
-
-#define SHARPSL_LED_ERROR 2
-#define SHARPSL_LED_ON 1
-#define SHARPSL_LED_OFF 0
-
-void sharpsl_battery_kick(void);
-void sharpsl_pm_led(int val);
-
-/* MAX1111 Channel Definitions */
-#define MAX1111_BATT_VOLT 4u
-#define MAX1111_BATT_TEMP 2u
-#define MAX1111_ACIN_VOLT 6u
-int sharpsl_pm_pxa_read_max1111(int channel);
-
-#endif
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
deleted file mode 100644
index 5eaf38243b9e..000000000000
--- a/arch/arm/mach-pxa/spitz.c
+++ /dev/null
@@ -1,1174 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Support for Sharp SL-Cxx00 Series of PDAs
- * Models: SL-C3000 (Spitz), SL-C1000 (Akita) and SL-C3100 (Borzoi)
- *
- * Copyright (c) 2005 Richard Purdie
- *
- * Based on Sharp's 2.4 kernel patches/lubbock.c
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio/legacy.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio/property.h>
-#include <linux/leds.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/platform_data/pca953x.h>
-#include <linux/property.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-#include <linux/spi/corgi_lcd.h>
-#include <linux/mtd/sharpsl.h>
-#include <linux/mtd/physmap.h>
-#include <linux/input-event-codes.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/regulator/machine.h>
-#include <linux/io.h>
-#include <linux/property.h>
-#include <linux/reboot.h>
-#include <linux/memblock.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/sharpsl_param.h>
-#include <asm/hardware/scoop.h>
-
-#include "pxa27x.h"
-#include "pxa27x-udc.h"
-#include "reset.h"
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <linux/platform_data/video-pxafb.h>
-#include "spitz.h"
-#include "sharpsl_pm.h"
-#include "smemc.h"
-
-#include "generic.h"
-#include "devices.h"
-
-/******************************************************************************
- * Pin configuration
- ******************************************************************************/
-static unsigned long spitz_pin_config[] __initdata = {
- /* Chip Selects */
- GPIO78_nCS_2, /* SCOOP #2 */
- GPIO79_nCS_3, /* NAND */
- GPIO80_nCS_4, /* SCOOP #1 */
-
- /* LCD - 16bpp Active TFT */
- GPIOxx_LCD_TFT_16BPP,
-
- /* PC Card */
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO85_nPCE_1,
- GPIO54_nPCE_2,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16,
- GPIO104_PSKTSEL,
-
- /* I2S */
- GPIO28_I2S_BITCLK_OUT,
- GPIO29_I2S_SDATA_IN,
- GPIO30_I2S_SDATA_OUT,
- GPIO31_I2S_SYNC,
-
- /* MMC */
- GPIO32_MMC_CLK,
- GPIO112_MMC_CMD,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
-
- /* GPIOs */
- GPIO9_GPIO, /* SPITZ_GPIO_nSD_DETECT */
- GPIO16_GPIO, /* SPITZ_GPIO_SYNC */
- GPIO81_GPIO, /* SPITZ_GPIO_nSD_WP */
- GPIO41_GPIO, /* SPITZ_GPIO_USB_CONNECT */
- GPIO37_GPIO, /* SPITZ_GPIO_USB_HOST */
- GPIO35_GPIO, /* SPITZ_GPIO_USB_DEVICE */
- GPIO22_GPIO, /* SPITZ_GPIO_HSYNC */
- GPIO94_GPIO, /* SPITZ_GPIO_CF_CD */
- GPIO105_GPIO, /* SPITZ_GPIO_CF_IRQ */
- GPIO106_GPIO, /* SPITZ_GPIO_CF2_IRQ */
-
- /* GPIO matrix keypad */
- GPIO88_GPIO, /* column 0 */
- GPIO23_GPIO, /* column 1 */
- GPIO24_GPIO, /* column 2 */
- GPIO25_GPIO, /* column 3 */
- GPIO26_GPIO, /* column 4 */
- GPIO27_GPIO, /* column 5 */
- GPIO52_GPIO, /* column 6 */
- GPIO103_GPIO, /* column 7 */
- GPIO107_GPIO, /* column 8 */
- GPIO108_GPIO, /* column 9 */
- GPIO114_GPIO, /* column 10 */
- GPIO12_GPIO, /* row 0 */
- GPIO17_GPIO, /* row 1 */
- GPIO91_GPIO, /* row 2 */
- GPIO34_GPIO, /* row 3 */
- GPIO36_GPIO, /* row 4 */
- GPIO38_GPIO, /* row 5 */
- GPIO39_GPIO, /* row 6 */
-
- /* I2C */
- GPIO117_I2C_SCL,
- GPIO118_I2C_SDA,
-
- GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, /* SPITZ_GPIO_KEY_INT */
- GPIO1_GPIO | WAKEUP_ON_EDGE_FALL, /* SPITZ_GPIO_RESET */
-};
-
-static const struct software_node spitz_scoop_1_gpiochip_node = {
- .name = "sharp-scoop.0",
-};
-
-/* Only on Spitz */
-static const struct software_node spitz_scoop_2_gpiochip_node = {
- .name = "sharp-scoop.1",
-};
-
-/* Only on Akita */
-static const struct software_node akita_max7310_gpiochip_node = {
- .name = "i2c-max7310",
-};
-
-/******************************************************************************
- * Scoop GPIO expander
- ******************************************************************************/
-#if defined(CONFIG_SHARP_SCOOP) || defined(CONFIG_SHARP_SCOOP_MODULE)
-/* SCOOP Device #1 */
-static struct resource spitz_scoop_1_resources[] = {
- [0] = {
- .start = 0x10800000,
- .end = 0x10800fff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct scoop_config spitz_scoop_1_setup = {
- .io_dir = SPITZ_SCP_IO_DIR,
- .io_out = SPITZ_SCP_IO_OUT,
- .suspend_clr = SPITZ_SCP_SUS_CLR,
- .suspend_set = SPITZ_SCP_SUS_SET,
- .gpio_base = SPITZ_SCP_GPIO_BASE,
-};
-
-static struct platform_device spitz_scoop_1_device = {
- .name = "sharp-scoop",
- .id = 0,
- .dev = {
- .platform_data = &spitz_scoop_1_setup,
- },
- .num_resources = ARRAY_SIZE(spitz_scoop_1_resources),
- .resource = spitz_scoop_1_resources,
-};
-
-/* SCOOP Device #2 */
-static struct resource spitz_scoop_2_resources[] = {
- [0] = {
- .start = 0x08800040,
- .end = 0x08800fff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct scoop_config spitz_scoop_2_setup = {
- .io_dir = SPITZ_SCP2_IO_DIR,
- .io_out = SPITZ_SCP2_IO_OUT,
- .suspend_clr = SPITZ_SCP2_SUS_CLR,
- .suspend_set = SPITZ_SCP2_SUS_SET,
- .gpio_base = SPITZ_SCP2_GPIO_BASE,
-};
-
-static struct platform_device spitz_scoop_2_device = {
- .name = "sharp-scoop",
- .id = 1,
- .dev = {
- .platform_data = &spitz_scoop_2_setup,
- },
- .num_resources = ARRAY_SIZE(spitz_scoop_2_resources),
- .resource = spitz_scoop_2_resources,
-};
-
-static void __init spitz_scoop_init(void)
-{
- spitz_scoop_1_device.dev.fwnode = software_node_fwnode(&spitz_scoop_1_gpiochip_node);
- platform_device_register(&spitz_scoop_1_device);
-
- /* Akita doesn't have the second SCOOP chip */
- if (!machine_is_akita()) {
- spitz_scoop_2_device.dev.fwnode = software_node_fwnode(
- &spitz_scoop_2_gpiochip_node);
- platform_device_register(&spitz_scoop_2_device);
- }
-}
-
-/* Power control is shared with between one of the CF slots and SD */
-static void __maybe_unused spitz_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr)
-{
- unsigned short cpr;
- unsigned long flags;
-
- if (new_cpr & 0x7) {
- gpio_set_value(SPITZ_GPIO_CF_POWER, 1);
- mdelay(5);
- }
-
- local_irq_save(flags);
-
- cpr = read_scoop_reg(&spitz_scoop_1_device.dev, SCOOP_CPR);
-
- if (enable & new_cpr)
- cpr |= new_cpr;
- else
- cpr &= ~enable;
-
- write_scoop_reg(&spitz_scoop_1_device.dev, SCOOP_CPR, cpr);
-
- local_irq_restore(flags);
-
- if (!(cpr & 0x7)) {
- mdelay(1);
- gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
- }
-}
-
-#else
-static inline void spitz_scoop_init(void) {}
-static inline void spitz_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr) {}
-#endif
-
-/******************************************************************************
- * PCMCIA
- ******************************************************************************/
-#if defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
-static void spitz_pcmcia_pwr(struct device *scoop, uint16_t cpr, int nr)
-{
- /* Only need to override behaviour for slot 0 */
- if (nr == 0)
- spitz_card_pwr_ctrl(
- cpr & (SCOOP_CPR_CF_3V | SCOOP_CPR_CF_XV), cpr);
- else
- write_scoop_reg(scoop, SCOOP_CPR, cpr);
-}
-
-static struct scoop_pcmcia_dev spitz_pcmcia_scoop[] = {
- {
- .dev = &spitz_scoop_1_device.dev,
- .irq = SPITZ_IRQ_GPIO_CF_IRQ,
- .cd_irq = SPITZ_IRQ_GPIO_CF_CD,
- .cd_irq_str = "PCMCIA0 CD",
- }, {
- .dev = &spitz_scoop_2_device.dev,
- .irq = SPITZ_IRQ_GPIO_CF2_IRQ,
- .cd_irq = -1,
- },
-};
-
-static struct scoop_pcmcia_config spitz_pcmcia_config = {
- .devs = &spitz_pcmcia_scoop[0],
- .num_devs = 2,
- .power_ctrl = spitz_pcmcia_pwr,
-};
-
-static void __init spitz_pcmcia_init(void)
-{
- /* Akita has only one PCMCIA slot used */
- if (machine_is_akita())
- spitz_pcmcia_config.num_devs = 1;
-
- platform_scoop_config = &spitz_pcmcia_config;
-}
-#else
-static inline void spitz_pcmcia_init(void) {}
-#endif
-
-/******************************************************************************
- * GPIO keyboard
- ******************************************************************************/
-#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
-
-#define SPITZ_KEY_CALENDAR KEY_F1
-#define SPITZ_KEY_ADDRESS KEY_F2
-#define SPITZ_KEY_FN KEY_F3
-#define SPITZ_KEY_CANCEL KEY_F4
-#define SPITZ_KEY_EXOK KEY_F5
-#define SPITZ_KEY_EXCANCEL KEY_F6
-#define SPITZ_KEY_EXJOGDOWN KEY_F7
-#define SPITZ_KEY_EXJOGUP KEY_F8
-#define SPITZ_KEY_JAP1 KEY_LEFTALT
-#define SPITZ_KEY_JAP2 KEY_RIGHTCTRL
-#define SPITZ_KEY_SYNC KEY_F9
-#define SPITZ_KEY_MAIL KEY_F10
-#define SPITZ_KEY_OK KEY_F11
-#define SPITZ_KEY_MENU KEY_F12
-
-static const uint32_t spitz_keymap[] = {
- KEY(0, 0, KEY_LEFTCTRL),
- KEY(0, 1, KEY_1),
- KEY(0, 2, KEY_3),
- KEY(0, 3, KEY_5),
- KEY(0, 4, KEY_6),
- KEY(0, 5, KEY_7),
- KEY(0, 6, KEY_9),
- KEY(0, 7, KEY_0),
- KEY(0, 8, KEY_BACKSPACE),
- KEY(0, 9, SPITZ_KEY_EXOK), /* EXOK */
- KEY(0, 10, SPITZ_KEY_EXCANCEL), /* EXCANCEL */
- KEY(1, 1, KEY_2),
- KEY(1, 2, KEY_4),
- KEY(1, 3, KEY_R),
- KEY(1, 4, KEY_Y),
- KEY(1, 5, KEY_8),
- KEY(1, 6, KEY_I),
- KEY(1, 7, KEY_O),
- KEY(1, 8, KEY_P),
- KEY(1, 9, SPITZ_KEY_EXJOGDOWN), /* EXJOGDOWN */
- KEY(1, 10, SPITZ_KEY_EXJOGUP), /* EXJOGUP */
- KEY(2, 0, KEY_TAB),
- KEY(2, 1, KEY_Q),
- KEY(2, 2, KEY_E),
- KEY(2, 3, KEY_T),
- KEY(2, 4, KEY_G),
- KEY(2, 5, KEY_U),
- KEY(2, 6, KEY_J),
- KEY(2, 7, KEY_K),
- KEY(3, 0, SPITZ_KEY_ADDRESS), /* ADDRESS */
- KEY(3, 1, KEY_W),
- KEY(3, 2, KEY_S),
- KEY(3, 3, KEY_F),
- KEY(3, 4, KEY_V),
- KEY(3, 5, KEY_H),
- KEY(3, 6, KEY_M),
- KEY(3, 7, KEY_L),
- KEY(3, 9, KEY_RIGHTSHIFT),
- KEY(4, 0, SPITZ_KEY_CALENDAR), /* CALENDAR */
- KEY(4, 1, KEY_A),
- KEY(4, 2, KEY_D),
- KEY(4, 3, KEY_C),
- KEY(4, 4, KEY_B),
- KEY(4, 5, KEY_N),
- KEY(4, 6, KEY_DOT),
- KEY(4, 8, KEY_ENTER),
- KEY(4, 9, KEY_LEFTSHIFT),
- KEY(5, 0, SPITZ_KEY_MAIL), /* MAIL */
- KEY(5, 1, KEY_Z),
- KEY(5, 2, KEY_X),
- KEY(5, 3, KEY_MINUS),
- KEY(5, 4, KEY_SPACE),
- KEY(5, 5, KEY_COMMA),
- KEY(5, 7, KEY_UP),
- KEY(5, 10, SPITZ_KEY_FN), /* FN */
- KEY(6, 0, KEY_SYSRQ),
- KEY(6, 1, SPITZ_KEY_JAP1), /* JAP1 */
- KEY(6, 2, SPITZ_KEY_JAP2), /* JAP2 */
- KEY(6, 3, SPITZ_KEY_CANCEL), /* CANCEL */
- KEY(6, 4, SPITZ_KEY_OK), /* OK */
- KEY(6, 5, SPITZ_KEY_MENU), /* MENU */
- KEY(6, 6, KEY_LEFT),
- KEY(6, 7, KEY_DOWN),
- KEY(6, 8, KEY_RIGHT),
-};
-
-static const struct software_node_ref_args spitz_mkp_row_gpios[] = {
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 12, GPIO_ACTIVE_HIGH),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 17, GPIO_ACTIVE_HIGH),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 91, GPIO_ACTIVE_HIGH),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 34, GPIO_ACTIVE_HIGH),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 36, GPIO_ACTIVE_HIGH),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 38, GPIO_ACTIVE_HIGH),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 39, GPIO_ACTIVE_HIGH),
-};
-
-static const struct software_node_ref_args spitz_mkp_col_gpios[] = {
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 88, GPIO_ACTIVE_HIGH),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 23, GPIO_ACTIVE_HIGH),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 24, GPIO_ACTIVE_HIGH),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 25, GPIO_ACTIVE_HIGH),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 26, GPIO_ACTIVE_HIGH),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 27, GPIO_ACTIVE_HIGH),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 52, GPIO_ACTIVE_HIGH),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 103, GPIO_ACTIVE_HIGH),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 107, GPIO_ACTIVE_HIGH),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 108, GPIO_ACTIVE_HIGH),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 114, GPIO_ACTIVE_HIGH),
-};
-
-static const struct property_entry spitz_mkp_properties[] = {
- PROPERTY_ENTRY_U32_ARRAY("linux,keymap", spitz_keymap),
- PROPERTY_ENTRY_REF_ARRAY("row-gpios", spitz_mkp_row_gpios),
- PROPERTY_ENTRY_REF_ARRAY("col-gpios", spitz_mkp_col_gpios),
- PROPERTY_ENTRY_U32("col-scan-delay-us", 10),
- PROPERTY_ENTRY_U32("debounce-delay-ms", 10),
- PROPERTY_ENTRY_BOOL("wakeup-source"),
- { }
-};
-
-static const struct platform_device_info spitz_mkp_info __initconst = {
- .name = "matrix-keypad",
- .id = PLATFORM_DEVID_NONE,
- .properties = spitz_mkp_properties,
-};
-
-
-static void __init spitz_mkp_init(void)
-{
- struct platform_device *pd;
- int err;
-
- pd = platform_device_register_full(&spitz_mkp_info);
- err = PTR_ERR_OR_ZERO(pd);
- if (err)
- pr_err("failed to create keypad device: %d\n", err);
-}
-#else
-static inline void spitz_mkp_init(void) {}
-#endif
-
-/******************************************************************************
- * GPIO keys
- ******************************************************************************/
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static const struct software_node spitz_gpio_keys_node = {
- .name = "spitz-gpio-keys",
-};
-
-static const struct property_entry spitz_suspend_key_props[] = {
- PROPERTY_ENTRY_U32("linux,input-type", EV_PWR),
- PROPERTY_ENTRY_U32("linux,code", KEY_SUSPEND),
- PROPERTY_ENTRY_GPIO("gpios", &pxa2xx_gpiochip_node,
- SPITZ_GPIO_ON_KEY, GPIO_ACTIVE_HIGH),
- PROPERTY_ENTRY_STRING("label", "On Off"),
- PROPERTY_ENTRY_BOOL("wakeup-source"),
- { }
-};
-
-static const struct software_node spitz_suspend_key_node = {
- .parent = &spitz_gpio_keys_node,
- .properties = spitz_suspend_key_props,
-};
-
-static const struct property_entry spitz_sw1_props[] = {
- PROPERTY_ENTRY_U32("linux,input-type", EV_SW),
- PROPERTY_ENTRY_U32("linux,code", 0),
- PROPERTY_ENTRY_GPIO("gpios", &pxa2xx_gpiochip_node,
- SPITZ_GPIO_SWA, GPIO_ACTIVE_HIGH),
- PROPERTY_ENTRY_STRING("label", "Display Down"),
- { }
-};
-
-static const struct software_node spitz_sw1_node = {
- .parent = &spitz_gpio_keys_node,
- .properties = spitz_sw1_props,
-};
-
-static const struct property_entry spitz_sw2_props[] = {
- PROPERTY_ENTRY_U32("linux,input-type", EV_SW),
- PROPERTY_ENTRY_U32("linux,code", 1),
- PROPERTY_ENTRY_GPIO("gpios", &pxa2xx_gpiochip_node,
- SPITZ_GPIO_SWB, GPIO_ACTIVE_HIGH),
- PROPERTY_ENTRY_STRING("label", "Lid Closed"),
- { }
-};
-
-static const struct software_node spitz_sw2_node = {
- .parent = &spitz_gpio_keys_node,
- .properties = spitz_sw2_props,
-};
-
-static const struct software_node *spitz_gpio_keys_swnodes[] = {
- &spitz_gpio_keys_node,
- &spitz_suspend_key_node,
- &spitz_sw1_node,
- &spitz_sw2_node,
- NULL
-};
-
-static void __init spitz_keys_init(void)
-{
- struct platform_device_info keys_info = {
- .name = "gpio-keys",
- .id = PLATFORM_DEVID_NONE,
- };
- struct platform_device *pd;
- int err;
-
- err = software_node_register_node_group(spitz_gpio_keys_swnodes);
- if (err) {
- pr_err("failed to register gpio-keys software nodes: %d\n", err);
- return;
- }
-
- keys_info.fwnode = software_node_fwnode(&spitz_gpio_keys_node);
-
- pd = platform_device_register_full(&keys_info);
- err = PTR_ERR_OR_ZERO(pd);
- if (err)
- pr_err("failed to create gpio-keys device: %d\n", err);
-}
-#else
-static inline void spitz_keys_init(void) {}
-#endif
-
-/******************************************************************************
- * LEDs
- ******************************************************************************/
-#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-static const struct software_node spitz_gpio_leds_node = {
- .name = "spitz-leds",
-};
-
-static const struct property_entry spitz_orange_led_props[] = {
- PROPERTY_ENTRY_STRING("linux,default-trigger", "sharpsl-charge"),
- PROPERTY_ENTRY_GPIO("gpios",
- &spitz_scoop_1_gpiochip_node, 6, GPIO_ACTIVE_HIGH),
- { }
-};
-
-static const struct software_node spitz_orange_led_node = {
- .name = "spitz:amber:charge",
- .parent = &spitz_gpio_leds_node,
- .properties = spitz_orange_led_props,
-};
-
-static const struct property_entry spitz_green_led_props[] = {
- PROPERTY_ENTRY_STRING("linux,default-trigger", "disk-activity"),
- PROPERTY_ENTRY_GPIO("gpios",
- &spitz_scoop_1_gpiochip_node, 0, GPIO_ACTIVE_HIGH),
- { }
-};
-
-static const struct software_node spitz_green_led_node = {
- .name = "spitz:green:hddactivity",
- .parent = &spitz_gpio_leds_node,
- .properties = spitz_green_led_props,
-};
-
-static const struct software_node *spitz_gpio_leds_swnodes[] = {
- &spitz_gpio_leds_node,
- &spitz_orange_led_node,
- &spitz_green_led_node,
- NULL
-};
-
-static void __init spitz_leds_init(void)
-{
- struct platform_device_info led_info = {
- .name = "leds-gpio",
- .id = PLATFORM_DEVID_NONE,
- };
- struct platform_device *led_dev;
- int err;
-
- err = software_node_register_node_group(spitz_gpio_leds_swnodes);
- if (err) {
- pr_err("failed to register LED software nodes: %d\n", err);
- return;
- }
-
- led_info.fwnode = software_node_fwnode(&spitz_gpio_leds_node);
-
- led_dev = platform_device_register_full(&led_info);
- err = PTR_ERR_OR_ZERO(led_dev);
- if (err)
- pr_err("failed to create LED device: %d\n", err);
-}
-#else
-static inline void spitz_leds_init(void) {}
-#endif
-
-/******************************************************************************
- * SSP Devices
- ******************************************************************************/
-#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
-
-static const struct property_entry spitz_ads7846_props[] = {
- PROPERTY_ENTRY_STRING("compatible", "ti,ads7846"),
- PROPERTY_ENTRY_U32("touchscreen-max-pressure", 1024),
- PROPERTY_ENTRY_U16("ti,x-plate-ohms", 419),
- PROPERTY_ENTRY_U16("ti,y-plate-ohms", 486),
- PROPERTY_ENTRY_U16("ti,vref-delay-usecs", 100),
- PROPERTY_ENTRY_GPIO("pendown-gpios", &pxa2xx_gpiochip_node,
- SPITZ_GPIO_TP_INT, GPIO_ACTIVE_LOW),
- PROPERTY_ENTRY_GPIO("ti,hsync-gpios", &pxa2xx_gpiochip_node,
- SPITZ_GPIO_HSYNC, GPIO_ACTIVE_LOW),
- { }
-};
-
-static const struct software_node spitz_ads7846_swnode = {
- .name = "ads7846",
- .properties = spitz_ads7846_props,
-};
-
-static const struct property_entry spitz_lcdcon_props[] = {
- PROPERTY_ENTRY_GPIO("BL_CONT-gpios",
- &spitz_scoop_2_gpiochip_node, 6, GPIO_ACTIVE_LOW),
- PROPERTY_ENTRY_GPIO("BL_ON-gpios",
- &spitz_scoop_2_gpiochip_node, 7, GPIO_ACTIVE_HIGH),
- { }
-};
-
-static const struct property_entry akita_lcdcon_props[] = {
- PROPERTY_ENTRY_GPIO("BL_ON-gpios",
- &akita_max7310_gpiochip_node, 3, GPIO_ACTIVE_HIGH),
- PROPERTY_ENTRY_GPIO("BL_CONT-gpios",
- &akita_max7310_gpiochip_node, 4, GPIO_ACTIVE_LOW),
- { }
-};
-
-static struct software_node spitz_lcdcon_node = {
- .name = "spitz-lcdcon",
-};
-
-static struct corgi_lcd_platform_data spitz_lcdcon_info = {
- .init_mode = CORGI_LCD_MODE_VGA,
- .max_intensity = 0x2f,
- .default_intensity = 0x1f,
- .limit_mask = 0x0b,
- .kick_battery = sharpsl_battery_kick,
-};
-
-static struct spi_board_info spitz_spi_devices[] = {
- {
- .modalias = "ads7846",
- .max_speed_hz = 1200000,
- .bus_num = 2,
- .chip_select = 0,
- .swnode = &spitz_ads7846_swnode,
- .irq = PXA_GPIO_TO_IRQ(SPITZ_GPIO_TP_INT),
- }, {
- .modalias = "corgi-lcd",
- .max_speed_hz = 50000,
- .bus_num = 2,
- .chip_select = 1,
- .platform_data = &spitz_lcdcon_info,
- .swnode = &spitz_lcdcon_node,
- }, {
- .modalias = "max1111",
- .max_speed_hz = 450000,
- .bus_num = 2,
- .chip_select = 2,
- },
-};
-
-static const struct software_node_ref_args spitz_spi_gpio_refs[] = {
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, SPITZ_GPIO_ADS7846_CS,
- GPIO_ACTIVE_LOW),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, SPITZ_GPIO_LCDCON_CS,
- GPIO_ACTIVE_LOW),
- SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, SPITZ_GPIO_MAX1111_CS,
- GPIO_ACTIVE_LOW),
-};
-
-static const struct property_entry spitz_spi_properties[] = {
- PROPERTY_ENTRY_REF_ARRAY("gpios", spitz_spi_gpio_refs),
- { }
-};
-
-static const struct platform_device_info spitz_spi_device_info = {
- .name = "pxa2xx-spi",
- /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1 */
- .id = 2,
- .properties = spitz_spi_properties,
-};
-
-static void __init spitz_spi_init(void)
-{
- struct platform_device *pd;
- int err;
-
- pd = platform_device_register_full(&spitz_spi_device_info);
- err = PTR_ERR_OR_ZERO(pd);
- if (err)
- pr_err("pxa2xx-spi: failed to instantiate SPI controller: %d\n",
- err);
-
- spitz_lcdcon_node.properties = machine_is_akita() ?
- akita_lcdcon_props : spitz_lcdcon_props;
- spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices));
-}
-#else
-static inline void spitz_spi_init(void) {}
-#endif
-
-/******************************************************************************
- * SD/MMC card controller
- ******************************************************************************/
-#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
-/*
- * NOTE: The card detect interrupt isn't debounced so we delay it by 250ms to
- * give the card a chance to fully insert/eject.
- */
-static int spitz_mci_setpower(struct device *dev, unsigned int vdd)
-{
- struct pxamci_platform_data* p_d = dev->platform_data;
-
- if ((1 << vdd) & p_d->ocr_mask)
- spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, SCOOP_CPR_SD_3V);
- else
- spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0);
-
- return 0;
-}
-
-static struct pxamci_platform_data spitz_mci_platform_data = {
- .detect_delay_ms = 250,
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
- .setpower = spitz_mci_setpower,
-};
-
-static const struct property_entry spitz_mci_props[] __initconst = {
- PROPERTY_ENTRY_GPIO("cd-gpios", &pxa2xx_gpiochip_node,
- SPITZ_GPIO_nSD_DETECT, GPIO_ACTIVE_LOW),
- PROPERTY_ENTRY_GPIO("wp-gpios", &pxa2xx_gpiochip_node,
- SPITZ_GPIO_nSD_WP, GPIO_ACTIVE_LOW),
- { }
-};
-
-static void __init spitz_mmc_init(void)
-{
- pxa_set_mci_info(&spitz_mci_platform_data, spitz_mci_props);
-}
-#else
-static inline void spitz_mmc_init(void) {}
-#endif
-
-/******************************************************************************
- * USB Host
- ******************************************************************************/
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static int spitz_ohci_init(struct device *dev)
-{
- int err;
-
- err = gpio_request(SPITZ_GPIO_USB_HOST, "USB_HOST");
- if (err)
- return err;
-
- /* Only Port 2 is connected, setup USB Port 2 Output Control Register */
- UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
-
- return gpio_direction_output(SPITZ_GPIO_USB_HOST, 1);
-}
-
-static void spitz_ohci_exit(struct device *dev)
-{
- gpio_free(SPITZ_GPIO_USB_HOST);
-}
-
-static struct pxaohci_platform_data spitz_ohci_platform_data = {
- .port_mode = PMM_NPS_MODE,
- .init = spitz_ohci_init,
- .exit = spitz_ohci_exit,
- .flags = ENABLE_PORT_ALL | NO_OC_PROTECTION,
- .power_budget = 150,
-};
-
-static void __init spitz_uhc_init(void)
-{
- pxa_set_ohci_info(&spitz_ohci_platform_data);
-}
-#else
-static inline void spitz_uhc_init(void) {}
-#endif
-
-/******************************************************************************
- * Framebuffer
- ******************************************************************************/
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static struct pxafb_mode_info spitz_pxafb_modes[] = {
- {
- .pixclock = 19231,
- .xres = 480,
- .yres = 640,
- .bpp = 16,
- .hsync_len = 40,
- .left_margin = 46,
- .right_margin = 125,
- .vsync_len = 3,
- .upper_margin = 1,
- .lower_margin = 0,
- .sync = 0,
- }, {
- .pixclock = 134617,
- .xres = 240,
- .yres = 320,
- .bpp = 16,
- .hsync_len = 20,
- .left_margin = 20,
- .right_margin = 46,
- .vsync_len = 2,
- .upper_margin = 1,
- .lower_margin = 0,
- .sync = 0,
- },
-};
-
-static struct pxafb_mach_info spitz_pxafb_info = {
- .modes = spitz_pxafb_modes,
- .num_modes = ARRAY_SIZE(spitz_pxafb_modes),
- .fixed_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_ALTERNATE_MAPPING,
-};
-
-static void __init spitz_lcd_init(void)
-{
- pxa_set_fb_info(NULL, &spitz_pxafb_info);
-}
-#else
-static inline void spitz_lcd_init(void) {}
-#endif
-
-/******************************************************************************
- * NAND Flash
- ******************************************************************************/
-#if defined(CONFIG_MTD_NAND_SHARPSL) || defined(CONFIG_MTD_NAND_SHARPSL_MODULE)
-static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
-
-static struct nand_bbt_descr spitz_nand_bbt = {
- .options = 0,
- .offs = 4,
- .len = 2,
- .pattern = scan_ff_pattern
-};
-
-static int akita_ooblayout_ecc(struct mtd_info *mtd, int section,
- struct mtd_oob_region *oobregion)
-{
- if (section > 12)
- return -ERANGE;
-
- switch (section % 3) {
- case 0:
- oobregion->offset = 5;
- oobregion->length = 1;
- break;
-
- case 1:
- oobregion->offset = 1;
- oobregion->length = 3;
- break;
-
- case 2:
- oobregion->offset = 6;
- oobregion->length = 2;
- break;
- }
-
- oobregion->offset += (section / 3) * 0x10;
-
- return 0;
-}
-
-static int akita_ooblayout_free(struct mtd_info *mtd, int section,
- struct mtd_oob_region *oobregion)
-{
- if (section)
- return -ERANGE;
-
- oobregion->offset = 8;
- oobregion->length = 9;
-
- return 0;
-}
-
-static const struct mtd_ooblayout_ops akita_ooblayout_ops = {
- .ecc = akita_ooblayout_ecc,
- .free = akita_ooblayout_free,
-};
-
-static const char * const probes[] = {
- "cmdlinepart",
- "ofpart",
- "sharpslpart",
- NULL,
-};
-
-static struct sharpsl_nand_platform_data spitz_nand_pdata = {
- .badblock_pattern = &spitz_nand_bbt,
- .part_parsers = probes,
-};
-
-static struct resource spitz_nand_resources[] = {
- {
- .start = PXA_CS3_PHYS,
- .end = PXA_CS3_PHYS + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device spitz_nand_device = {
- .name = "sharpsl-nand",
- .id = -1,
- .resource = spitz_nand_resources,
- .num_resources = ARRAY_SIZE(spitz_nand_resources),
- .dev = {
- .platform_data = &spitz_nand_pdata,
- }
-};
-
-static void __init spitz_nand_init(void)
-{
- if (machine_is_akita() || machine_is_borzoi()) {
- spitz_nand_bbt.len = 1;
- spitz_nand_pdata.ecc_layout = &akita_ooblayout_ops;
- }
-
- platform_device_register(&spitz_nand_device);
-}
-#else
-static inline void spitz_nand_init(void) {}
-#endif
-
-/******************************************************************************
- * NOR Flash
- ******************************************************************************/
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
-static struct mtd_partition spitz_rom_parts[] = {
- {
- .name ="Boot PROM Filesystem",
- .offset = 0x00140000,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct physmap_flash_data spitz_rom_data = {
- .width = 2,
- .nr_parts = ARRAY_SIZE(spitz_rom_parts),
- .parts = spitz_rom_parts,
-};
-
-static struct resource spitz_rom_resources[] = {
- {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_8M - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device spitz_rom_device = {
- .name = "physmap-flash",
- .id = -1,
- .resource = spitz_rom_resources,
- .num_resources = ARRAY_SIZE(spitz_rom_resources),
- .dev = {
- .platform_data = &spitz_rom_data,
- },
-};
-
-static void __init spitz_nor_init(void)
-{
- platform_device_register(&spitz_rom_device);
-}
-#else
-static inline void spitz_nor_init(void) {}
-#endif
-
-/******************************************************************************
- * I2C devices
- ******************************************************************************/
-#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
-static struct pca953x_platform_data akita_pca953x_pdata = {
- .gpio_base = AKITA_IOEXP_GPIO_BASE,
-};
-
-static struct i2c_board_info spitz_i2c_devs[] = {
- {
- .type = "wm8750",
- .addr = 0x1b,
- }, {
- .type = "max7310",
- .addr = 0x18,
- .platform_data = &akita_pca953x_pdata,
- .swnode = &akita_max7310_gpiochip_node,
- },
-};
-
-static struct regulator_consumer_supply isl6271a_consumers[] = {
- REGULATOR_SUPPLY("vcc_core", NULL),
-};
-
-static struct regulator_init_data isl6271a_info[] = {
- {
- .constraints = {
- .name = "vcc_core range",
- .min_uV = 850000,
- .max_uV = 1600000,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
- },
- .consumer_supplies = isl6271a_consumers,
- .num_consumer_supplies = ARRAY_SIZE(isl6271a_consumers),
- }
-};
-
-static struct i2c_board_info spitz_pi2c_devs[] = {
- {
- .type = "isl6271a",
- .addr = 0x0c,
- .platform_data = &isl6271a_info,
- },
-};
-
-static void __init spitz_i2c_init(void)
-{
- int size = ARRAY_SIZE(spitz_i2c_devs);
-
- /* Only Akita has the max7310 chip */
- if (!machine_is_akita())
- size--;
-
- pxa_set_i2c_info(NULL);
- pxa27x_set_i2c_power_info(NULL);
- i2c_register_board_info(0, spitz_i2c_devs, size);
- i2c_register_board_info(1, ARRAY_AND_SIZE(spitz_pi2c_devs));
-}
-#else
-static inline void spitz_i2c_init(void) {}
-#endif
-
-static const struct property_entry spitz_audio_props[] = {
- PROPERTY_ENTRY_GPIO("mute-l-gpios", &spitz_scoop_1_gpiochip_node, 3,
- GPIO_ACTIVE_HIGH),
- PROPERTY_ENTRY_GPIO("mute-r-gpios", &spitz_scoop_1_gpiochip_node, 4,
- GPIO_ACTIVE_HIGH),
- PROPERTY_ENTRY_GPIO("mic-gpios", &spitz_scoop_2_gpiochip_node, 8,
- GPIO_ACTIVE_HIGH),
- { }
-};
-
-static const struct property_entry akita_audio_props[] = {
- PROPERTY_ENTRY_GPIO("mute-l-gpios", &spitz_scoop_1_gpiochip_node, 3,
- GPIO_ACTIVE_HIGH),
- PROPERTY_ENTRY_GPIO("mute-r-gpios", &spitz_scoop_1_gpiochip_node, 4,
- GPIO_ACTIVE_HIGH),
- PROPERTY_ENTRY_GPIO("mic-gpios", &akita_max7310_gpiochip_node, 2,
- GPIO_ACTIVE_HIGH),
- { }
-};
-
-/******************************************************************************
- * Audio devices
- ******************************************************************************/
-static inline void spitz_audio_init(void)
-{
- struct platform_device_info audio_info = {
- .name = "spitz-audio",
- .id = PLATFORM_DEVID_NONE,
- .properties = machine_is_akita() ?
- akita_audio_props : spitz_audio_props,
- };
-
- platform_device_register_full(&audio_info);
-}
-
-/******************************************************************************
- * Machine init
- ******************************************************************************/
-static void spitz_poweroff(void)
-{
- pxa_restart(REBOOT_GPIO, NULL);
-}
-
-static void spitz_restart(enum reboot_mode mode, const char *cmd)
-{
- uint32_t msc0 = __raw_readl(MSC0);
- /* Bootloader magic for a reboot */
- if ((msc0 & 0xffff0000) == 0x7ff00000)
- __raw_writel((msc0 & 0xffff) | 0x7ee00000, MSC0);
-
- spitz_poweroff();
-}
-
-static void __init spitz_init(void)
-{
- software_node_register(&spitz_scoop_1_gpiochip_node);
- if (machine_is_akita())
- software_node_register(&akita_max7310_gpiochip_node);
- else
- software_node_register(&spitz_scoop_2_gpiochip_node);
-
- init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
- register_platform_power_off(spitz_poweroff);
-
- PMCR = 0x00;
-
- /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
- PCFR |= PCFR_OPDE;
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(spitz_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- spitz_spi_init();
- spitz_scoop_init();
- spitz_mkp_init();
- spitz_keys_init();
- spitz_leds_init();
- spitz_mmc_init();
- spitz_pcmcia_init();
- spitz_uhc_init();
- spitz_lcd_init();
- spitz_nor_init();
- spitz_nand_init();
- spitz_i2c_init();
- spitz_audio_init();
-
- regulator_has_full_constraints();
-}
-
-static void __init spitz_fixup(struct tag *tags, char **cmdline)
-{
- sharpsl_save_param();
- memblock_add(0xa0000000, SZ_64M);
-}
-
-#ifdef CONFIG_MACH_SPITZ
-MACHINE_START(SPITZ, "SHARP Spitz")
- .fixup = spitz_fixup,
- .map_io = pxa27x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .init_machine = spitz_init,
- .init_time = pxa_timer_init,
- .restart = spitz_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_BORZOI
-MACHINE_START(BORZOI, "SHARP Borzoi")
- .fixup = spitz_fixup,
- .map_io = pxa27x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .init_machine = spitz_init,
- .init_time = pxa_timer_init,
- .restart = spitz_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_AKITA
-MACHINE_START(AKITA, "SHARP Akita")
- .fixup = spitz_fixup,
- .map_io = pxa27x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .init_machine = spitz_init,
- .init_time = pxa_timer_init,
- .restart = spitz_restart,
-MACHINE_END
-#endif
diff --git a/arch/arm/mach-pxa/spitz.h b/arch/arm/mach-pxa/spitz.h
deleted file mode 100644
index 04828d8918aa..000000000000
--- a/arch/arm/mach-pxa/spitz.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Hardware specific definitions for SL-Cx000 series of PDAs
- *
- * Copyright (c) 2005 Alexander Wykes
- * Copyright (c) 2005 Richard Purdie
- *
- * Based on Sharp's 2.4 kernel patches
- */
-#ifndef __ASM_ARCH_SPITZ_H
-#define __ASM_ARCH_SPITZ_H 1
-#endif
-
-#include "irqs.h" /* PXA_NR_BUILTIN_GPIO, PXA_GPIO_TO_IRQ */
-#include <linux/fb.h>
-
-/* Spitz/Akita GPIOs */
-
-#define SPITZ_GPIO_KEY_INT (0) /* Key Interrupt */
-#define SPITZ_GPIO_RESET (1)
-#define SPITZ_GPIO_nSD_DETECT (9)
-#define SPITZ_GPIO_TP_INT (11) /* Touch Panel interrupt */
-#define SPITZ_GPIO_AK_INT (13) /* Remote Control */
-#define SPITZ_GPIO_ADS7846_CS (14)
-#define SPITZ_GPIO_SYNC (16)
-#define SPITZ_GPIO_MAX1111_CS (20)
-#define SPITZ_GPIO_FATAL_BAT (21)
-#define SPITZ_GPIO_HSYNC (22)
-#define SPITZ_GPIO_nSD_CLK (32)
-#define SPITZ_GPIO_USB_DEVICE (35)
-#define SPITZ_GPIO_USB_HOST (37)
-#define SPITZ_GPIO_USB_CONNECT (41)
-#define SPITZ_GPIO_LCDCON_CS (53)
-#define SPITZ_GPIO_nPCE (54)
-#define SPITZ_GPIO_nSD_WP (81)
-#define SPITZ_GPIO_ON_RESET (89)
-#define SPITZ_GPIO_BAT_COVER (90)
-#define SPITZ_GPIO_CF_CD (94)
-#define SPITZ_GPIO_ON_KEY (95)
-#define SPITZ_GPIO_SWA (97)
-#define SPITZ_GPIO_SWB (96)
-#define SPITZ_GPIO_CHRG_FULL (101)
-#define SPITZ_GPIO_CO (101)
-#define SPITZ_GPIO_CF_IRQ (105)
-#define SPITZ_GPIO_AC_IN (115)
-#define SPITZ_GPIO_HP_IN (116)
-
-/* Spitz Only GPIOs */
-
-#define SPITZ_GPIO_CF2_IRQ (106) /* CF slot1 Ready */
-#define SPITZ_GPIO_CF2_CD (93)
-
-
-/* Spitz/Akita Keyboard Definitions */
-
-#define SPITZ_KEY_STROBE_NUM (11)
-#define SPITZ_KEY_SENSE_NUM (7)
-#define SPITZ_GPIO_G0_STROBE_BIT 0x0f800000
-#define SPITZ_GPIO_G1_STROBE_BIT 0x00100000
-#define SPITZ_GPIO_G2_STROBE_BIT 0x01000000
-#define SPITZ_GPIO_G3_STROBE_BIT 0x00041880
-#define SPITZ_GPIO_G0_SENSE_BIT 0x00021000
-#define SPITZ_GPIO_G1_SENSE_BIT 0x000000d4
-#define SPITZ_GPIO_G2_SENSE_BIT 0x08000000
-#define SPITZ_GPIO_G3_SENSE_BIT 0x00000000
-
-#define SPITZ_GPIO_KEY_STROBE0 88
-#define SPITZ_GPIO_KEY_STROBE1 23
-#define SPITZ_GPIO_KEY_STROBE2 24
-#define SPITZ_GPIO_KEY_STROBE3 25
-#define SPITZ_GPIO_KEY_STROBE4 26
-#define SPITZ_GPIO_KEY_STROBE5 27
-#define SPITZ_GPIO_KEY_STROBE6 52
-#define SPITZ_GPIO_KEY_STROBE7 103
-#define SPITZ_GPIO_KEY_STROBE8 107
-#define SPITZ_GPIO_KEY_STROBE9 108
-#define SPITZ_GPIO_KEY_STROBE10 114
-
-#define SPITZ_GPIO_KEY_SENSE0 12
-#define SPITZ_GPIO_KEY_SENSE1 17
-#define SPITZ_GPIO_KEY_SENSE2 91
-#define SPITZ_GPIO_KEY_SENSE3 34
-#define SPITZ_GPIO_KEY_SENSE4 36
-#define SPITZ_GPIO_KEY_SENSE5 38
-#define SPITZ_GPIO_KEY_SENSE6 39
-
-
-/* Spitz Scoop Device (No. 1) GPIOs */
-/* Suspend States in comments */
-#define SPITZ_SCP_LED_GREEN SCOOP_GPCR_PA11 /* Keep */
-#define SPITZ_SCP_JK_B SCOOP_GPCR_PA12 /* Keep */
-#define SPITZ_SCP_CHRG_ON SCOOP_GPCR_PA13 /* Keep */
-#define SPITZ_SCP_MUTE_L SCOOP_GPCR_PA14 /* Low */
-#define SPITZ_SCP_MUTE_R SCOOP_GPCR_PA15 /* Low */
-#define SPITZ_SCP_CF_POWER SCOOP_GPCR_PA16 /* Keep */
-#define SPITZ_SCP_LED_ORANGE SCOOP_GPCR_PA17 /* Keep */
-#define SPITZ_SCP_JK_A SCOOP_GPCR_PA18 /* Low */
-#define SPITZ_SCP_ADC_TEMP_ON SCOOP_GPCR_PA19 /* Low */
-
-#define SPITZ_SCP_IO_DIR (SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \
- SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | \
- SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
-#define SPITZ_SCP_IO_OUT (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R)
-#define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
-#define SPITZ_SCP_SUS_SET 0
-
-#define SPITZ_SCP_GPIO_BASE (PXA_NR_BUILTIN_GPIO)
-#define SPITZ_GPIO_LED_GREEN (SPITZ_SCP_GPIO_BASE + 0)
-#define SPITZ_GPIO_JK_B (SPITZ_SCP_GPIO_BASE + 1)
-#define SPITZ_GPIO_CHRG_ON (SPITZ_SCP_GPIO_BASE + 2)
-#define SPITZ_GPIO_MUTE_L (SPITZ_SCP_GPIO_BASE + 3)
-#define SPITZ_GPIO_MUTE_R (SPITZ_SCP_GPIO_BASE + 4)
-#define SPITZ_GPIO_CF_POWER (SPITZ_SCP_GPIO_BASE + 5)
-#define SPITZ_GPIO_LED_ORANGE (SPITZ_SCP_GPIO_BASE + 6)
-#define SPITZ_GPIO_JK_A (SPITZ_SCP_GPIO_BASE + 7)
-#define SPITZ_GPIO_ADC_TEMP_ON (SPITZ_SCP_GPIO_BASE + 8)
-
-/* Spitz Scoop Device (No. 2) GPIOs */
-/* Suspend States in comments */
-#define SPITZ_SCP2_IR_ON SCOOP_GPCR_PA11 /* High */
-#define SPITZ_SCP2_AKIN_PULLUP SCOOP_GPCR_PA12 /* Keep */
-#define SPITZ_SCP2_RESERVED_1 SCOOP_GPCR_PA13 /* High */
-#define SPITZ_SCP2_RESERVED_2 SCOOP_GPCR_PA14 /* Low */
-#define SPITZ_SCP2_RESERVED_3 SCOOP_GPCR_PA15 /* Low */
-#define SPITZ_SCP2_RESERVED_4 SCOOP_GPCR_PA16 /* Low */
-#define SPITZ_SCP2_BACKLIGHT_CONT SCOOP_GPCR_PA17 /* Low */
-#define SPITZ_SCP2_BACKLIGHT_ON SCOOP_GPCR_PA18 /* Low */
-#define SPITZ_SCP2_MIC_BIAS SCOOP_GPCR_PA19 /* Low */
-
-#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \
- SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
- SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
-
-#define SPITZ_SCP2_IO_OUT (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1)
-#define SPITZ_SCP2_SUS_CLR (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
- SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
-#define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1)
-
-#define SPITZ_SCP2_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12)
-#define SPITZ_GPIO_IR_ON (SPITZ_SCP2_GPIO_BASE + 0)
-#define SPITZ_GPIO_AKIN_PULLUP (SPITZ_SCP2_GPIO_BASE + 1)
-#define SPITZ_GPIO_RESERVED_1 (SPITZ_SCP2_GPIO_BASE + 2)
-#define SPITZ_GPIO_RESERVED_2 (SPITZ_SCP2_GPIO_BASE + 3)
-#define SPITZ_GPIO_RESERVED_3 (SPITZ_SCP2_GPIO_BASE + 4)
-#define SPITZ_GPIO_RESERVED_4 (SPITZ_SCP2_GPIO_BASE + 5)
-#define SPITZ_GPIO_BACKLIGHT_CONT (SPITZ_SCP2_GPIO_BASE + 6)
-#define SPITZ_GPIO_BACKLIGHT_ON (SPITZ_SCP2_GPIO_BASE + 7)
-#define SPITZ_GPIO_MIC_BIAS (SPITZ_SCP2_GPIO_BASE + 8)
-
-/* Akita IO Expander GPIOs */
-#define AKITA_IOEXP_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12)
-#define AKITA_GPIO_RESERVED_0 (AKITA_IOEXP_GPIO_BASE + 0)
-#define AKITA_GPIO_RESERVED_1 (AKITA_IOEXP_GPIO_BASE + 1)
-#define AKITA_GPIO_MIC_BIAS (AKITA_IOEXP_GPIO_BASE + 2)
-#define AKITA_GPIO_BACKLIGHT_ON (AKITA_IOEXP_GPIO_BASE + 3)
-#define AKITA_GPIO_BACKLIGHT_CONT (AKITA_IOEXP_GPIO_BASE + 4)
-#define AKITA_GPIO_AKIN_PULLUP (AKITA_IOEXP_GPIO_BASE + 5)
-#define AKITA_GPIO_IR_ON (AKITA_IOEXP_GPIO_BASE + 6)
-#define AKITA_GPIO_RESERVED_7 (AKITA_IOEXP_GPIO_BASE + 7)
-
-/* Spitz IRQ Definitions */
-
-#define SPITZ_IRQ_GPIO_KEY_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_KEY_INT)
-#define SPITZ_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(SPITZ_GPIO_AC_IN)
-#define SPITZ_IRQ_GPIO_AK_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_AK_INT)
-#define SPITZ_IRQ_GPIO_HP_IN PXA_GPIO_TO_IRQ(SPITZ_GPIO_HP_IN)
-#define SPITZ_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_TP_INT)
-#define SPITZ_IRQ_GPIO_SYNC PXA_GPIO_TO_IRQ(SPITZ_GPIO_SYNC)
-#define SPITZ_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(SPITZ_GPIO_ON_KEY)
-#define SPITZ_IRQ_GPIO_SWA PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWA)
-#define SPITZ_IRQ_GPIO_SWB PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWB)
-#define SPITZ_IRQ_GPIO_BAT_COVER PXA_GPIO_TO_IRQ(SPITZ_GPIO_BAT_COVER)
-#define SPITZ_IRQ_GPIO_FATAL_BAT PXA_GPIO_TO_IRQ(SPITZ_GPIO_FATAL_BAT)
-#define SPITZ_IRQ_GPIO_CO PXA_GPIO_TO_IRQ(SPITZ_GPIO_CO)
-#define SPITZ_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_IRQ)
-#define SPITZ_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_CD)
-#define SPITZ_IRQ_GPIO_CF2_IRQ PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF2_IRQ)
-#define SPITZ_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_INT)
-#define SPITZ_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_DETECT)
-
-/*
- * Shared data structures
- */
-extern struct platform_device spitzssp_device;
-extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
deleted file mode 100644
index 806847c36549..000000000000
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ /dev/null
@@ -1,257 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Battery and Power Management code for the Sharp SL-Cxx00
- *
- * Copyright (c) 2005 Richard Purdie
- */
-
-#include <linux/module.h>
-#include <linux/stat.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/gpio/legacy.h>
-#include <linux/gpio-pxa.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/apm-emulation.h>
-#include <linux/spi/corgi_lcd.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include "spitz.h"
-#include "pxa27x.h"
-#include "sharpsl_pm.h"
-
-#include "generic.h"
-
-#define SHARPSL_CHARGE_ON_VOLT 0x99 /* 2.9V */
-#define SHARPSL_CHARGE_ON_TEMP 0xe0 /* 2.9V */
-#define SHARPSL_CHARGE_ON_ACIN_HIGH 0x9b /* 6V */
-#define SHARPSL_CHARGE_ON_ACIN_LOW 0x34 /* 2V */
-#define SHARPSL_FATAL_ACIN_VOLT 182 /* 3.45V */
-#define SHARPSL_FATAL_NOACIN_VOLT 170 /* 3.40V */
-
-static int spitz_last_ac_status;
-
-static void spitz_charger_init(void)
-{
- gpio_request(SPITZ_GPIO_KEY_INT, "Keyboard Interrupt");
- gpio_direction_input(SPITZ_GPIO_KEY_INT);
- gpio_request(SPITZ_GPIO_SYNC, "Sync");
- gpio_direction_input(SPITZ_GPIO_SYNC);
- gpio_request(SPITZ_GPIO_AC_IN, "Charger Detection");
- gpio_direction_input(SPITZ_GPIO_AC_IN);
- gpio_request(SPITZ_GPIO_ADC_TEMP_ON, "ADC Temp On");
- gpio_direction_output(SPITZ_GPIO_ADC_TEMP_ON, 0);
- gpio_request(SPITZ_GPIO_JK_B, "JK B");
- gpio_direction_output(SPITZ_GPIO_JK_B, 0);
- gpio_request(SPITZ_GPIO_CHRG_ON, "Charger On");
- gpio_direction_output(SPITZ_GPIO_CHRG_ON, 0);
-}
-
-static void spitz_measure_temp(int on)
-{
- gpio_set_value(SPITZ_GPIO_ADC_TEMP_ON, on);
-}
-
-static void spitz_charge(int on)
-{
- if (on) {
- if (sharpsl_pm.flags & SHARPSL_SUSPENDED) {
- gpio_set_value(SPITZ_GPIO_JK_B, 1);
- gpio_set_value(SPITZ_GPIO_CHRG_ON, 0);
- } else {
- gpio_set_value(SPITZ_GPIO_JK_B, 0);
- gpio_set_value(SPITZ_GPIO_CHRG_ON, 0);
- }
- } else {
- gpio_set_value(SPITZ_GPIO_JK_B, 0);
- gpio_set_value(SPITZ_GPIO_CHRG_ON, 1);
- }
-}
-
-static void spitz_discharge(int on)
-{
- gpio_set_value(SPITZ_GPIO_JK_A, on);
-}
-
-/* HACK - For unknown reasons, accurate voltage readings are only made with a load
- on the power bus which the green led on spitz provides */
-static void spitz_discharge1(int on)
-{
- gpio_set_value(SPITZ_GPIO_LED_GREEN, on);
-}
-
-static unsigned long gpio18_config = GPIO18_GPIO;
-
-static void spitz_presuspend(void)
-{
- spitz_last_ac_status = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN);
-
- /* GPIO Sleep Register */
- PGSR0 = 0x00144018;
- PGSR1 = 0x00EF0000;
- if (machine_is_akita()) {
- PGSR2 = 0x2121C000;
- PGSR3 = 0x00600400;
- } else {
- PGSR2 = 0x0121C000;
- PGSR3 = 0x00600000;
- }
-
- PGSR0 &= ~SPITZ_GPIO_G0_STROBE_BIT;
- PGSR1 &= ~SPITZ_GPIO_G1_STROBE_BIT;
- PGSR2 &= ~SPITZ_GPIO_G2_STROBE_BIT;
- PGSR3 &= ~SPITZ_GPIO_G3_STROBE_BIT;
- PGSR2 |= GPIO_bit(SPITZ_GPIO_KEY_STROBE0);
-
- pxa2xx_mfp_config(&gpio18_config, 1);
- gpio_request_one(18, GPIOF_OUT_INIT_HIGH, "Unknown");
- gpio_free(18);
-
- PRER = GPIO_bit(SPITZ_GPIO_KEY_INT);
- PFER = GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET);
- PWER = GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET) | PWER_RTC;
- PKWR = GPIO_bit(SPITZ_GPIO_SYNC) | GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET);
- PKSR = 0xffffffff; /* clear */
-
- /* nRESET_OUT Disable */
- PSLR |= PSLR_SL_ROD;
-
- /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
- PCFR = PCFR_GPR_EN | PCFR_OPDE;
-}
-
-static void spitz_postsuspend(void)
-{
-}
-
-static int spitz_should_wakeup(unsigned int resume_on_alarm)
-{
- int is_resume = 0;
- int acin = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN);
-
- if (spitz_last_ac_status != acin) {
- if (acin) {
- /* charge on */
- sharpsl_pm.flags |= SHARPSL_DO_OFFLINE_CHRG;
- dev_dbg(sharpsl_pm.dev, "AC Inserted\n");
- } else {
- /* charge off */
- dev_dbg(sharpsl_pm.dev, "AC Removed\n");
- sharpsl_pm_led(SHARPSL_LED_OFF);
- sharpsl_pm.machinfo->charge(0);
- sharpsl_pm.charge_mode = CHRG_OFF;
- }
- spitz_last_ac_status = acin;
- /* Return to suspend as this must be what we were woken for */
- return 0;
- }
-
- if (PEDR & GPIO_bit(SPITZ_GPIO_KEY_INT))
- is_resume |= GPIO_bit(SPITZ_GPIO_KEY_INT);
-
- if (PKSR & GPIO_bit(SPITZ_GPIO_SYNC))
- is_resume |= GPIO_bit(SPITZ_GPIO_SYNC);
-
- if (resume_on_alarm && (PEDR & PWER_RTC))
- is_resume |= PWER_RTC;
-
- dev_dbg(sharpsl_pm.dev, "is_resume: %x\n", is_resume);
- return is_resume;
-}
-
-static bool spitz_charger_wakeup(void)
-{
- return !gpio_get_value(SPITZ_GPIO_KEY_INT) ||
- gpio_get_value(SPITZ_GPIO_SYNC);
-}
-
-static unsigned long spitzpm_read_devdata(int type)
-{
- switch (type) {
- case SHARPSL_STATUS_ACIN:
- return !gpio_get_value(SPITZ_GPIO_AC_IN);
- case SHARPSL_STATUS_LOCK:
- return gpio_get_value(sharpsl_pm.machinfo->gpio_batlock);
- case SHARPSL_STATUS_CHRGFULL:
- return gpio_get_value(sharpsl_pm.machinfo->gpio_batfull);
- case SHARPSL_STATUS_FATAL:
- return gpio_get_value(sharpsl_pm.machinfo->gpio_fatal);
- case SHARPSL_ACIN_VOLT:
- return sharpsl_pm_pxa_read_max1111(MAX1111_ACIN_VOLT);
- case SHARPSL_BATT_TEMP:
- return sharpsl_pm_pxa_read_max1111(MAX1111_BATT_TEMP);
- case SHARPSL_BATT_VOLT:
- default:
- return sharpsl_pm_pxa_read_max1111(MAX1111_BATT_VOLT);
- }
-}
-
-struct sharpsl_charger_machinfo spitz_pm_machinfo = {
- .init = spitz_charger_init,
- .exit = NULL,
- .gpio_batlock = SPITZ_GPIO_BAT_COVER,
- .gpio_acin = SPITZ_GPIO_AC_IN,
- .gpio_batfull = SPITZ_GPIO_CHRG_FULL,
- .batfull_irq = 1,
- .gpio_fatal = SPITZ_GPIO_FATAL_BAT,
- .discharge = spitz_discharge,
- .discharge1 = spitz_discharge1,
- .charge = spitz_charge,
- .measure_temp = spitz_measure_temp,
- .presuspend = spitz_presuspend,
- .postsuspend = spitz_postsuspend,
- .read_devdata = spitzpm_read_devdata,
- .charger_wakeup = spitz_charger_wakeup,
- .should_wakeup = spitz_should_wakeup,
-#if defined(CONFIG_LCD_CORGI)
- .backlight_limit = corgi_lcd_limit_intensity,
-#endif
- .charge_on_volt = SHARPSL_CHARGE_ON_VOLT,
- .charge_on_temp = SHARPSL_CHARGE_ON_TEMP,
- .charge_acin_high = SHARPSL_CHARGE_ON_ACIN_HIGH,
- .charge_acin_low = SHARPSL_CHARGE_ON_ACIN_LOW,
- .fatal_acin_volt = SHARPSL_FATAL_ACIN_VOLT,
- .fatal_noacin_volt= SHARPSL_FATAL_NOACIN_VOLT,
- .bat_levels = 40,
- .bat_levels_noac = sharpsl_battery_levels_noac,
- .bat_levels_acin = sharpsl_battery_levels_acin,
- .status_high_acin = 188,
- .status_low_acin = 178,
- .status_high_noac = 185,
- .status_low_noac = 175,
-};
-
-static struct platform_device *spitzpm_device;
-
-static int spitzpm_init(void)
-{
- int ret;
-
- if (!machine_is_spitz() && !machine_is_akita()
- && !machine_is_borzoi())
- return -ENODEV;
-
- spitzpm_device = platform_device_alloc("sharpsl-pm", -1);
- if (!spitzpm_device)
- return -ENOMEM;
-
- spitzpm_device->dev.platform_data = &spitz_pm_machinfo;
- ret = platform_device_add(spitzpm_device);
-
- if (ret)
- platform_device_put(spitzpm_device);
-
- return ret;
-}
-
-static void spitzpm_exit(void)
-{
- platform_device_unregister(spitzpm_device);
-}
-
-module_init(spitzpm_init);
-module_exit(spitzpm_exit);
--
2.53.0
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 04/13] ARM: remove legacy pxa board files
2026-09-08 15:27 ` [PATCH 04/13] ARM: remove legacy pxa board files Arnd Bergmann
@ 2026-09-08 17:30 ` Linus Walleij
2026-09-08 18:32 ` Daniel Mack
1 sibling, 0 replies; 70+ messages in thread
From: Linus Walleij @ 2026-09-08 17:30 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Russell King,
Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Daniel Mack,
Haojian Zhuang, Bartosz Golaszewski
On Tue, Sep 8, 2026 at 5:29 PM Arnd Bergmann <arnd@kernel.org> wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The PXA platform supports devicetree based booting, but still has a
> few traditional board files, which were left as a starting point for a
> possible conversion to devicetree during the last mass purge of board
> files in 2022.
>
> None of these boards were actually converted, so drop support for these
> now, along with the 'scoop' support chip that was used on some PDAs that
> are no longer usable now.
>
> The only remaining board support is for the "Raumfeld" speaker system
> based on PXA300 SoC, though basic support for PXA250 and PXA270 is still
> there and may work with external dts files.
>
> Cc: Daniel Mack <daniel@zonque.org>
> Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
> Cc: Robert Jarzmik <robert.jarzmik@free.fr>
> Cc: Linus Walleij <linusw@kernel.org>
> Cc: Bartosz Golaszewski <brgl@kernel.org>
> Cc: Ethan Nelson-Moore <enelsonmoore@gmail.com>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linusw@kernel.org>
I ACK this based on the number of refactorings I did on this
to remove the static GPIO assignments, I'm really tired of
doing them if no-one benefits.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 04/13] ARM: remove legacy pxa board files
2026-09-08 15:27 ` [PATCH 04/13] ARM: remove legacy pxa board files Arnd Bergmann
2026-09-08 17:30 ` Linus Walleij
@ 2026-09-08 18:32 ` Daniel Mack
1 sibling, 0 replies; 70+ messages in thread
From: Daniel Mack @ 2026-09-08 18:32 UTC (permalink / raw)
To: Arnd Bergmann, Krzysztof Kozlowski, Alexandre Belloni,
Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Daniel Mack,
Haojian Zhuang, Bartosz Golaszewski
On 9/8/26 17:27, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The PXA platform supports devicetree based booting, but still has a
> few traditional board files, which were left as a starting point for a
> possible conversion to devicetree during the last mass purge of board
> files in 2022.
>
> None of these boards were actually converted, so drop support for these
> now, along with the 'scoop' support chip that was used on some PDAs that
> are no longer usable now.
>
> The only remaining board support is for the "Raumfeld" speaker system
> based on PXA300 SoC, though basic support for PXA250 and PXA270 is still
> there and may work with external dts files.
>
> Cc: Daniel Mack <daniel@zonque.org>
> Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
> Cc: Robert Jarzmik <robert.jarzmik@free.fr>
> Cc: Linus Walleij <linusw@kernel.org>
> Cc: Bartosz Golaszewski <brgl@kernel.org>
> Cc: Ethan Nelson-Moore <enelsonmoore@gmail.com>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Daniel Mack <daniel@zonque.org>
> ---
> arch/arm/boot/compressed/Makefile | 4 -
> arch/arm/boot/compressed/head-sharpsl.S | 151 ---
> arch/arm/common/Kconfig | 6 -
> arch/arm/common/Makefile | 2 -
> arch/arm/common/scoop.c | 269 -----
> arch/arm/common/sharpsl_param.c | 63 --
> arch/arm/configs/am200epdkit_defconfig | 91 --
> arch/arm/configs/spitz_defconfig | 237 -----
> arch/arm/include/asm/hardware/scoop.h | 67 --
> arch/arm/include/asm/mach/sharpsl_param.h | 33 -
> arch/arm/mach-pxa/Kconfig | 89 --
> arch/arm/mach-pxa/Makefile | 8 -
> arch/arm/mach-pxa/am200epd.c | 395 -------
> arch/arm/mach-pxa/am300epd.c | 296 ------
> arch/arm/mach-pxa/devices.c | 705 -------------
> arch/arm/mach-pxa/devices.h | 68 --
> arch/arm/mach-pxa/generic.h | 5 -
> arch/arm/mach-pxa/gumstix.c | 237 -----
> arch/arm/mach-pxa/gumstix.h | 89 --
> arch/arm/mach-pxa/pxa25x.c | 59 --
> arch/arm/mach-pxa/pxa27x.c | 77 --
> arch/arm/mach-pxa/pxa300.c | 1 -
> arch/arm/mach-pxa/pxa320.c | 1 -
> arch/arm/mach-pxa/pxa3xx.c | 6 -
> arch/arm/mach-pxa/sharpsl_pm.c | 941 -----------------
> arch/arm/mach-pxa/sharpsl_pm.h | 108 --
> arch/arm/mach-pxa/spitz.c | 1174 ---------------------
> arch/arm/mach-pxa/spitz.h | 185 ----
> arch/arm/mach-pxa/spitz_pm.c | 257 -----
> 29 files changed, 5624 deletions(-)
> delete mode 100644 arch/arm/boot/compressed/head-sharpsl.S
> delete mode 100644 arch/arm/common/scoop.c
> delete mode 100644 arch/arm/common/sharpsl_param.c
> delete mode 100644 arch/arm/configs/am200epdkit_defconfig
> delete mode 100644 arch/arm/configs/spitz_defconfig
> delete mode 100644 arch/arm/include/asm/hardware/scoop.h
> delete mode 100644 arch/arm/include/asm/mach/sharpsl_param.h
> delete mode 100644 arch/arm/mach-pxa/am200epd.c
> delete mode 100644 arch/arm/mach-pxa/am300epd.c
> delete mode 100644 arch/arm/mach-pxa/devices.h
> delete mode 100644 arch/arm/mach-pxa/gumstix.c
> delete mode 100644 arch/arm/mach-pxa/gumstix.h
> delete mode 100644 arch/arm/mach-pxa/sharpsl_pm.c
> delete mode 100644 arch/arm/mach-pxa/sharpsl_pm.h
> delete mode 100644 arch/arm/mach-pxa/spitz.c
> delete mode 100644 arch/arm/mach-pxa/spitz.h
> delete mode 100644 arch/arm/mach-pxa/spitz_pm.c
>
> diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
> index 32def10f5e03..232b646bfd26 100644
> --- a/arch/arm/boot/compressed/Makefile
> +++ b/arch/arm/boot/compressed/Makefile
> @@ -29,10 +29,6 @@ ifeq ($(CONFIG_CPU_XSCALE),y)
> OBJS += head-xscale.o
> endif
>
> -ifeq ($(CONFIG_PXA_SHARPSL_DETECT_MACH_ID),y)
> -OBJS += head-sharpsl.o
> -endif
> -
> ifeq ($(CONFIG_CPU_ENDIAN_BE32),y)
> ifeq ($(CONFIG_CPU_CP15),y)
> OBJS += big-endian.o
> diff --git a/arch/arm/boot/compressed/head-sharpsl.S b/arch/arm/boot/compressed/head-sharpsl.S
> deleted file mode 100644
> index 992e784500fa..000000000000
> --- a/arch/arm/boot/compressed/head-sharpsl.S
> +++ /dev/null
> @@ -1,151 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * linux/arch/arm/boot/compressed/head-sharpsl.S
> - *
> - * Copyright (C) 2004-2005 Richard Purdie <rpurdie@rpsys.net>
> - *
> - * Sharp's bootloader doesn't pass any kind of machine ID
> - * so we have to figure out the machine for ourselves...
> - *
> - * Support for Poodle, Corgi (SL-C700), Shepherd (SL-C750)
> - * Husky (SL-C760), Tosa (SL-C6000), Spitz (SL-C3000),
> - * Akita (SL-C1000) and Borzoi (SL-C3100).
> - *
> - */
> -
> -#include <linux/linkage.h>
> -#include <asm/mach-types.h>
> -
> -#ifndef CONFIG_PXA_SHARPSL
> -#error What am I doing here...
> -#endif
> -
> - .section ".start", "ax"
> -
> -__SharpSL_start:
> -
> -/* Check for TC6393 - if found we have a Tosa */
> - ldr r7, .TOSAID
> - mov r1, #0x10000000 @ Base address of TC6393 chip
> - mov r6, #0x03
> - ldrh r3, [r1, #8] @ Load TC6393XB Revison: This is 0x0003
> - cmp r6, r3
> - beq .SHARPEND @ Success -> tosa
> -
> -/* Check for pxa270 - if found, branch */
> - mrc p15, 0, r4, c0, c0 @ Get Processor ID
> - and r4, r4, #0xffffff00
> - ldr r3, .PXA270ID
> - cmp r4, r3
> - beq .PXA270
> -
> -/* Check for w100 - if not found we have a Poodle */
> - ldr r1, .W100ADDR @ Base address of w100 chip + regs offset
> -
> - mov r6, #0x31 @ Load Magic Init value
> - str r6, [r1, #0x280] @ to SCRATCH_UMSK
> - mov r5, #0x3000
> -.W100LOOP:
> - subs r5, r5, #1
> - bne .W100LOOP
> - mov r6, #0x30 @ Load 2nd Magic Init value
> - str r6, [r1, #0x280] @ to SCRATCH_UMSK
> -
> - ldr r6, [r1, #0] @ Load Chip ID
> - ldr r3, .W100ID
> - ldr r7, .POODLEID
> - cmp r6, r3
> - bne .SHARPEND @ We have no w100 - Poodle
> -
> -/* Check for pxa250 - if found we have a Corgi */
> - ldr r7, .CORGIID
> - ldr r3, .PXA255ID
> - cmp r4, r3
> - blo .SHARPEND @ We have a PXA250 - Corgi
> -
> -/* Check for 64MiB flash - if found we have a Shepherd */
> - bl get_flash_ids
> - ldr r7, .SHEPHERDID
> - cmp r3, #0x76 @ 64MiB flash
> - beq .SHARPEND @ We have Shepherd
> -
> -/* Must be a Husky */
> - ldr r7, .HUSKYID @ Must be Husky
> - b .SHARPEND
> -
> -.PXA270:
> -/* Check for 16MiB flash - if found we have Spitz */
> - bl get_flash_ids
> - ldr r7, .SPITZID
> - cmp r3, #0x73 @ 16MiB flash
> - beq .SHARPEND @ We have Spitz
> -
> -/* Check for a second SCOOP chip - if found we have Borzoi */
> - ldr r1, .SCOOP2ADDR
> - ldr r7, .BORZOIID
> - mov r6, #0x0140
> - strh r6, [r1]
> - ldrh r6, [r1]
> - cmp r6, #0x0140
> - beq .SHARPEND @ We have Borzoi
> -
> -/* Must be Akita */
> - ldr r7, .AKITAID
> - b .SHARPEND @ We have Borzoi
> -
> -.PXA255ID:
> - .word 0x69052d00 @ PXA255 Processor ID
> -.PXA270ID:
> - .word 0x69054100 @ PXA270 Processor ID
> -.W100ID:
> - .word 0x57411002 @ w100 Chip ID
> -.W100ADDR:
> - .word 0x08010000 @ w100 Chip ID Reg Address
> -.SCOOP2ADDR:
> - .word 0x08800040
> -.POODLEID:
> - .word MACH_TYPE_POODLE
> -.CORGIID:
> - .word MACH_TYPE_CORGI
> -.SHEPHERDID:
> - .word MACH_TYPE_SHEPHERD
> -.HUSKYID:
> - .word MACH_TYPE_HUSKY
> -.TOSAID:
> - .word MACH_TYPE_TOSA
> -.SPITZID:
> - .word MACH_TYPE_SPITZ
> -.AKITAID:
> - .word MACH_TYPE_AKITA
> -.BORZOIID:
> - .word MACH_TYPE_BORZOI
> -
> -/*
> - * Return: r2 - NAND Manufacturer ID
> - * r3 - NAND Chip ID
> - * Corrupts: r1
> - */
> -get_flash_ids:
> - mov r1, #0x0c000000 @ Base address of NAND chip
> - ldrb r3, [r1, #24] @ Load FLASHCTL
> - bic r3, r3, #0x11 @ SET NCE
> - orr r3, r3, #0x0a @ SET CLR + FLWP
> - strb r3, [r1, #24] @ Save to FLASHCTL
> - mov r2, #0x90 @ Command "readid"
> - strb r2, [r1, #20] @ Save to FLASHIO
> - bic r3, r3, #2 @ CLR CLE
> - orr r3, r3, #4 @ SET ALE
> - strb r3, [r1, #24] @ Save to FLASHCTL
> - mov r2, #0 @ Address 0x00
> - strb r2, [r1, #20] @ Save to FLASHIO
> - bic r3, r3, #4 @ CLR ALE
> - strb r3, [r1, #24] @ Save to FLASHCTL
> -.fids1:
> - ldrb r3, [r1, #24] @ Load FLASHCTL
> - tst r3, #32 @ Is chip ready?
> - beq .fids1
> - ldrb r2, [r1, #20] @ NAND Manufacturer ID
> - ldrb r3, [r1, #20] @ NAND Chip ID
> - mov pc, lr
> -
> -.SHARPEND:
> diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
> index d72dccf6f3c2..cf75be68d05c 100644
> --- a/arch/arm/common/Kconfig
> +++ b/arch/arm/common/Kconfig
> @@ -1,9 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> config KRAIT_L2_ACCESSORS
> bool
> -
> -config SHARP_PARAM
> - bool
> -
> -config SHARP_SCOOP
> - bool
> diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
> index e1bcc250874f..1935b23700b0 100644
> --- a/arch/arm/common/Makefile
> +++ b/arch/arm/common/Makefile
> @@ -6,8 +6,6 @@
> obj-y += firmware.o
>
> obj-$(CONFIG_KRAIT_L2_ACCESSORS) += krait-l2-accessors.o
> -obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
> -obj-$(CONFIG_SHARP_SCOOP) += scoop.o
> obj-$(CONFIG_CPU_V7) += secure_cntvoff.o
> obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
> CFLAGS_REMOVE_mcpm_entry.o = -pg
> diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c
> deleted file mode 100644
> index 90474994757c..000000000000
> --- a/arch/arm/common/scoop.c
> +++ /dev/null
> @@ -1,269 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Support code for the SCOOP interface found on various Sharp PDAs
> - *
> - * Copyright (c) 2004 Richard Purdie
> - *
> - * Based on code written by Sharp/Lineo for 2.4 kernels
> - */
> -
> -#include <linux/device.h>
> -#include <linux/gpio/driver.h>
> -#include <linux/string.h>
> -#include <linux/slab.h>
> -#include <linux/platform_device.h>
> -#include <linux/export.h>
> -#include <linux/io.h>
> -#include <asm/hardware/scoop.h>
> -
> -/* PCMCIA to Scoop linkage
> -
> - There is no easy way to link multiple scoop devices into one
> - single entity for the pxa2xx_pcmcia device so this structure
> - is used which is setup by the platform code.
> -
> - This file is never modular so this symbol is always
> - accessile to the board support files.
> -*/
> -struct scoop_pcmcia_config *platform_scoop_config;
> -EXPORT_SYMBOL(platform_scoop_config);
> -
> -struct scoop_dev {
> - void __iomem *base;
> - struct gpio_chip gpio;
> - spinlock_t scoop_lock;
> - unsigned short suspend_clr;
> - unsigned short suspend_set;
> - u32 scoop_gpwr;
> -};
> -
> -void reset_scoop(struct device *dev)
> -{
> - struct scoop_dev *sdev = dev_get_drvdata(dev);
> -
> - iowrite16(0x0100, sdev->base + SCOOP_MCR); /* 00 */
> - iowrite16(0x0000, sdev->base + SCOOP_CDR); /* 04 */
> - iowrite16(0x0000, sdev->base + SCOOP_CCR); /* 10 */
> - iowrite16(0x0000, sdev->base + SCOOP_IMR); /* 18 */
> - iowrite16(0x00FF, sdev->base + SCOOP_IRM); /* 14 */
> - iowrite16(0x0000, sdev->base + SCOOP_ISR); /* 1C */
> - iowrite16(0x0000, sdev->base + SCOOP_IRM);
> -}
> -
> -static void __scoop_gpio_set(struct scoop_dev *sdev,
> - unsigned offset, int value)
> -{
> - unsigned short gpwr;
> -
> - gpwr = ioread16(sdev->base + SCOOP_GPWR);
> - if (value)
> - gpwr |= 1 << (offset + 1);
> - else
> - gpwr &= ~(1 << (offset + 1));
> - iowrite16(gpwr, sdev->base + SCOOP_GPWR);
> -}
> -
> -static int scoop_gpio_set(struct gpio_chip *chip, unsigned int offset,
> - int value)
> -{
> - struct scoop_dev *sdev = gpiochip_get_data(chip);
> - unsigned long flags;
> -
> - spin_lock_irqsave(&sdev->scoop_lock, flags);
> -
> - __scoop_gpio_set(sdev, offset, value);
> -
> - spin_unlock_irqrestore(&sdev->scoop_lock, flags);
> -
> - return 0;
> -}
> -
> -static int scoop_gpio_get(struct gpio_chip *chip, unsigned offset)
> -{
> - struct scoop_dev *sdev = gpiochip_get_data(chip);
> -
> - /* XXX: I'm unsure, but it seems so */
> - return !!(ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1)));
> -}
> -
> -static int scoop_gpio_direction_input(struct gpio_chip *chip,
> - unsigned offset)
> -{
> - struct scoop_dev *sdev = gpiochip_get_data(chip);
> - unsigned long flags;
> - unsigned short gpcr;
> -
> - spin_lock_irqsave(&sdev->scoop_lock, flags);
> -
> - gpcr = ioread16(sdev->base + SCOOP_GPCR);
> - gpcr &= ~(1 << (offset + 1));
> - iowrite16(gpcr, sdev->base + SCOOP_GPCR);
> -
> - spin_unlock_irqrestore(&sdev->scoop_lock, flags);
> -
> - return 0;
> -}
> -
> -static int scoop_gpio_direction_output(struct gpio_chip *chip,
> - unsigned offset, int value)
> -{
> - struct scoop_dev *sdev = gpiochip_get_data(chip);
> - unsigned long flags;
> - unsigned short gpcr;
> -
> - spin_lock_irqsave(&sdev->scoop_lock, flags);
> -
> - __scoop_gpio_set(sdev, offset, value);
> -
> - gpcr = ioread16(sdev->base + SCOOP_GPCR);
> - gpcr |= 1 << (offset + 1);
> - iowrite16(gpcr, sdev->base + SCOOP_GPCR);
> -
> - spin_unlock_irqrestore(&sdev->scoop_lock, flags);
> -
> - return 0;
> -}
> -
> -unsigned short read_scoop_reg(struct device *dev, unsigned short reg)
> -{
> - struct scoop_dev *sdev = dev_get_drvdata(dev);
> - return ioread16(sdev->base + reg);
> -}
> -
> -void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data)
> -{
> - struct scoop_dev *sdev = dev_get_drvdata(dev);
> - iowrite16(data, sdev->base + reg);
> -}
> -
> -EXPORT_SYMBOL(reset_scoop);
> -EXPORT_SYMBOL(read_scoop_reg);
> -EXPORT_SYMBOL(write_scoop_reg);
> -
> -#ifdef CONFIG_PM
> -static void check_scoop_reg(struct scoop_dev *sdev)
> -{
> - unsigned short mcr;
> -
> - mcr = ioread16(sdev->base + SCOOP_MCR);
> - if ((mcr & 0x100) == 0)
> - iowrite16(0x0101, sdev->base + SCOOP_MCR);
> -}
> -
> -static int scoop_suspend(struct platform_device *dev, pm_message_t state)
> -{
> - struct scoop_dev *sdev = platform_get_drvdata(dev);
> -
> - check_scoop_reg(sdev);
> - sdev->scoop_gpwr = ioread16(sdev->base + SCOOP_GPWR);
> - iowrite16((sdev->scoop_gpwr & ~sdev->suspend_clr) | sdev->suspend_set, sdev->base + SCOOP_GPWR);
> -
> - return 0;
> -}
> -
> -static int scoop_resume(struct platform_device *dev)
> -{
> - struct scoop_dev *sdev = platform_get_drvdata(dev);
> -
> - check_scoop_reg(sdev);
> - iowrite16(sdev->scoop_gpwr, sdev->base + SCOOP_GPWR);
> -
> - return 0;
> -}
> -#else
> -#define scoop_suspend NULL
> -#define scoop_resume NULL
> -#endif
> -
> -static int scoop_probe(struct platform_device *pdev)
> -{
> - struct scoop_dev *devptr;
> - struct scoop_config *inf;
> - struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> - int ret;
> -
> - if (!mem)
> - return -EINVAL;
> -
> - devptr = kzalloc_obj(struct scoop_dev);
> - if (!devptr)
> - return -ENOMEM;
> -
> - spin_lock_init(&devptr->scoop_lock);
> -
> - inf = pdev->dev.platform_data;
> - devptr->base = ioremap(mem->start, resource_size(mem));
> -
> - if (!devptr->base) {
> - ret = -ENOMEM;
> - goto err_ioremap;
> - }
> -
> - platform_set_drvdata(pdev, devptr);
> -
> - printk("Sharp Scoop Device found at 0x%08x -> 0x%8p\n",(unsigned int)mem->start, devptr->base);
> -
> - iowrite16(0x0140, devptr->base + SCOOP_MCR);
> - reset_scoop(&pdev->dev);
> - iowrite16(0x0000, devptr->base + SCOOP_CPR);
> - iowrite16(inf->io_dir & 0xffff, devptr->base + SCOOP_GPCR);
> - iowrite16(inf->io_out & 0xffff, devptr->base + SCOOP_GPWR);
> -
> - devptr->suspend_clr = inf->suspend_clr;
> - devptr->suspend_set = inf->suspend_set;
> -
> - devptr->gpio.base = -1;
> -
> - if (inf->gpio_base != 0) {
> - devptr->gpio.label = dev_name(&pdev->dev);
> - devptr->gpio.base = inf->gpio_base;
> - devptr->gpio.ngpio = 12; /* PA11 = 0, PA12 = 1, etc. up to PA22 = 11 */
> - devptr->gpio.set = scoop_gpio_set;
> - devptr->gpio.get = scoop_gpio_get;
> - devptr->gpio.direction_input = scoop_gpio_direction_input;
> - devptr->gpio.direction_output = scoop_gpio_direction_output;
> -
> - ret = gpiochip_add_data(&devptr->gpio, devptr);
> - if (ret)
> - goto err_gpio;
> - }
> -
> - return 0;
> -
> -err_gpio:
> - platform_set_drvdata(pdev, NULL);
> -err_ioremap:
> - iounmap(devptr->base);
> - kfree(devptr);
> -
> - return ret;
> -}
> -
> -static void scoop_remove(struct platform_device *pdev)
> -{
> - struct scoop_dev *sdev = platform_get_drvdata(pdev);
> -
> - if (sdev->gpio.base != -1)
> - gpiochip_remove(&sdev->gpio);
> -
> - platform_set_drvdata(pdev, NULL);
> - iounmap(sdev->base);
> - kfree(sdev);
> -}
> -
> -static struct platform_driver scoop_driver = {
> - .probe = scoop_probe,
> - .remove = scoop_remove,
> - .suspend = scoop_suspend,
> - .resume = scoop_resume,
> - .driver = {
> - .name = "sharp-scoop",
> - },
> -};
> -
> -static int __init scoop_init(void)
> -{
> - return platform_driver_register(&scoop_driver);
> -}
> -
> -subsys_initcall(scoop_init);
> diff --git a/arch/arm/common/sharpsl_param.c b/arch/arm/common/sharpsl_param.c
> deleted file mode 100644
> index 1ca26c063f80..000000000000
> --- a/arch/arm/common/sharpsl_param.c
> +++ /dev/null
> @@ -1,63 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Hardware parameter area specific to Sharp SL series devices
> - *
> - * Copyright (c) 2005 Richard Purdie
> - *
> - * Based on Sharp's 2.4 kernel patches
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/module.h>
> -#include <linux/string.h>
> -#include <asm/mach/sharpsl_param.h>
> -#include <asm/page.h>
> -
> -/*
> - * Certain hardware parameters determined at the time of device manufacture,
> - * typically including LCD parameters are loaded by the bootloader at the
> - * address PARAM_BASE. As the kernel will overwrite them, we need to store
> - * them early in the boot process, then pass them to the appropriate drivers.
> - * Not all devices use all parameters but the format is common to all.
> - */
> -#ifdef CONFIG_ARCH_SA1100
> -#define PARAM_BASE 0xe8ffc000
> -#define param_start(x) (void *)(x)
> -#else
> -#define PARAM_BASE 0xa0000a00
> -#define param_start(x) __va(x)
> -#endif
> -#define MAGIC_CHG(a,b,c,d) ( ( d << 24 ) | ( c << 16 ) | ( b << 8 ) | a )
> -
> -#define COMADJ_MAGIC MAGIC_CHG('C','M','A','D')
> -#define UUID_MAGIC MAGIC_CHG('U','U','I','D')
> -#define TOUCH_MAGIC MAGIC_CHG('T','U','C','H')
> -#define AD_MAGIC MAGIC_CHG('B','V','A','D')
> -#define PHAD_MAGIC MAGIC_CHG('P','H','A','D')
> -
> -struct sharpsl_param_info sharpsl_param;
> -EXPORT_SYMBOL(sharpsl_param);
> -
> -void sharpsl_save_param(void)
> -{
> - struct sharpsl_param_info *params = param_start(PARAM_BASE);
> -
> - memcpy(&sharpsl_param, params, sizeof(*params));
> -
> - if (sharpsl_param.comadj_keyword != COMADJ_MAGIC)
> - sharpsl_param.comadj=-1;
> -
> - if (sharpsl_param.phad_keyword != PHAD_MAGIC)
> - sharpsl_param.phadadj=-1;
> -
> - if (sharpsl_param.uuid_keyword != UUID_MAGIC)
> - sharpsl_param.uuid[0]=-1;
> -
> - if (sharpsl_param.touch_keyword != TOUCH_MAGIC)
> - sharpsl_param.touch_xp=-1;
> -
> - if (sharpsl_param.adadj_keyword != AD_MAGIC)
> - sharpsl_param.adadj=-1;
> -}
> -
> -
> diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig
> deleted file mode 100644
> index 61beac88e863..000000000000
> --- a/arch/arm/configs/am200epdkit_defconfig
> +++ /dev/null
> @@ -1,91 +0,0 @@
> -CONFIG_LOCALVERSION="gum"
> -CONFIG_SYSVIPC=y
> -CONFIG_PREEMPT=y
> -CONFIG_EXPERT=y
> -# CONFIG_EPOLL is not set
> -# CONFIG_SHMEM is not set
> -# CONFIG_ARCH_MULTI_V7 is not set
> -CONFIG_ARCH_PXA=y
> -CONFIG_ARCH_GUMSTIX=y
> -CONFIG_ATAGS=y
> -CONFIG_CMDLINE="console=ttyS0,115200n8 root=1f01 rootfstype=jffs2"
> -CONFIG_MODULES=y
> -CONFIG_MODULE_UNLOAD=y
> -CONFIG_PARTITION_ADVANCED=y
> -# CONFIG_SWAP is not set
> -# CONFIG_VM_EVENT_COUNTERS is not set
> -CONFIG_NET=y
> -CONFIG_PACKET=m
> -CONFIG_UNIX=y
> -CONFIG_INET=y
> -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> -# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> -# CONFIG_INET_XFRM_MODE_BEET is not set
> -# CONFIG_INET_DIAG is not set
> -# CONFIG_IPV6 is not set
> -CONFIG_BT=m
> -CONFIG_BT_RFCOMM=m
> -CONFIG_BT_RFCOMM_TTY=y
> -CONFIG_BT_BNEP=m
> -CONFIG_BT_HCIUART=m
> -CONFIG_BT_HCIUART_H4=y
> -CONFIG_PCCARD=y
> -CONFIG_MTD=y
> -CONFIG_MTD_BLOCK=y
> -CONFIG_MTD_CFI=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_GEOMETRY=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
> -# CONFIG_MTD_CFI_I2 is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -CONFIG_MTD_COMPLEX_MAPPINGS=y
> -CONFIG_MTD_PXA2XX=y
> -CONFIG_BLK_DEV_LOOP=m
> -CONFIG_BLK_DEV_SD=m
> -# CONFIG_BLK_DEV_BSG is not set
> -CONFIG_ATA=m
> -CONFIG_PATA_PCMCIA=m
> -CONFIG_NETDEVICES=y
> -CONFIG_SMC91X=m
> -# CONFIG_LEGACY_PTYS is not set
> -CONFIG_SERIAL_PXA=y
> -CONFIG_SERIAL_PXA_CONSOLE=y
> -# CONFIG_HW_RANDOM is not set
> -# CONFIG_HWMON is not set
> -CONFIG_WATCHDOG=y
> -CONFIG_SA1100_WATCHDOG=m
> -CONFIG_FB=y
> -CONFIG_FB_MODE_HELPERS=y
> -CONFIG_FB_TILEBLITTING=y
> -CONFIG_FB_PXA=y
> -CONFIG_FB_PXA_PARAMETERS=y
> -CONFIG_FB_MBX=m
> -CONFIG_FB_VIRTUAL=m
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_SOUND=m
> -CONFIG_SND=m
> -CONFIG_SND_MIXER_OSS=m
> -CONFIG_SND_PCM_OSS=m
> -# CONFIG_SND_VERBOSE_PROCFS is not set
> -CONFIG_SND_PXA2XX_AC97=m
> -CONFIG_USB_GADGET=y
> -CONFIG_USB_ETH=m
> -CONFIG_MMC=y
> -CONFIG_MMC_PXA=y
> -# CONFIG_DNOTIFY is not set
> -CONFIG_VFAT_FS=y
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_COMPRESSION_OPTIONS=y
> -CONFIG_JFFS2_RUBIN=y
> -CONFIG_NLS_CODEPAGE_437=y
> -CONFIG_NLS_ISO8859_1=y
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_DETECT_SOFTLOCKUP is not set
> -CONFIG_CRYPTO=y
> -CONFIG_CRYPTO_CBC=m
> -CONFIG_CRYPTO_ECB=m
> -CONFIG_CRYPTO_ARC4=m
> -# CONFIG_DEBUG_BUGVERBOSE is not set
> -# CONFIG_DEBUG_PREEMPT is not set
> -CONFIG_DEBUG_USER=y
> diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
> deleted file mode 100644
> index c7cf089001bf..000000000000
> --- a/arch/arm/configs/spitz_defconfig
> +++ /dev/null
> @@ -1,237 +0,0 @@
> -CONFIG_SYSVIPC=y
> -CONFIG_PREEMPT=y
> -CONFIG_BSD_PROCESS_ACCT=y
> -CONFIG_LOG_BUF_SHIFT=14
> -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
> -CONFIG_EXPERT=y
> -CONFIG_PROFILING=y
> -# CONFIG_ARCH_MULTI_V7 is not set
> -CONFIG_ARCH_PXA=y
> -CONFIG_PXA_SHARPSL=y
> -CONFIG_MACH_AKITA=y
> -CONFIG_MACH_BORZOI=y
> -CONFIG_ATAGS=y
> -CONFIG_CMDLINE="console=ttyS0,115200n8 console=tty1 noinitrd root=/dev/mtdblock2 rootfstype=jffs2 debug"
> -CONFIG_MODULES=y
> -CONFIG_MODULE_UNLOAD=y
> -CONFIG_MODULE_FORCE_UNLOAD=y
> -CONFIG_PARTITION_ADVANCED=y
> -CONFIG_BINFMT_MISC=m
> -CONFIG_PM=y
> -CONFIG_NET=y
> -CONFIG_PACKET=y
> -CONFIG_UNIX=y
> -CONFIG_INET=y
> -CONFIG_SYN_COOKIES=y
> -CONFIG_INET6_AH=m
> -CONFIG_INET6_ESP=m
> -CONFIG_INET6_IPCOMP=m
> -CONFIG_IPV6_TUNNEL=m
> -CONFIG_NETFILTER=y
> -CONFIG_IP_NF_IPTABLES=m
> -CONFIG_IP_NF_MATCH_ADDRTYPE=m
> -CONFIG_IP_NF_MATCH_ECN=m
> -CONFIG_IP_NF_MATCH_TTL=m
> -CONFIG_IP_NF_FILTER=m
> -CONFIG_IP_NF_TARGET_LOG=m
> -CONFIG_IP_NF_MANGLE=m
> -CONFIG_IP_NF_RAW=m
> -CONFIG_IP_NF_ARPTABLES=m
> -CONFIG_IP_NF_ARPFILTER=m
> -CONFIG_IP_NF_ARP_MANGLE=m
> -CONFIG_IP6_NF_IPTABLES=m
> -CONFIG_IP6_NF_MATCH_EUI64=m
> -CONFIG_IP6_NF_MATCH_FRAG=m
> -CONFIG_IP6_NF_MATCH_OPTS=m
> -CONFIG_IP6_NF_MATCH_HL=m
> -CONFIG_IP6_NF_MATCH_IPV6HEADER=m
> -CONFIG_IP6_NF_MATCH_RT=m
> -CONFIG_IP6_NF_FILTER=m
> -CONFIG_IP6_NF_MANGLE=m
> -CONFIG_IP6_NF_RAW=m
> -CONFIG_BT=m
> -CONFIG_BT_RFCOMM=m
> -CONFIG_BT_RFCOMM_TTY=y
> -CONFIG_BT_BNEP=m
> -CONFIG_BT_BNEP_MC_FILTER=y
> -CONFIG_BT_BNEP_PROTO_FILTER=y
> -CONFIG_BT_HIDP=m
> -CONFIG_BT_HCIUART=m
> -CONFIG_BT_HCIUART_H4=y
> -CONFIG_BT_HCIUART_BCSP=y
> -CONFIG_BT_HCIBCM203X=m
> -CONFIG_BT_HCIBPA10X=m
> -CONFIG_BT_HCIBFUSB=m
> -CONFIG_BT_HCIBTUART=m
> -CONFIG_BT_HCIVHCI=m
> -CONFIG_PCCARD=y
> -CONFIG_PCMCIA_PXA2XX=y
> -CONFIG_MTD=y
> -CONFIG_MTD_CMDLINE_PARTS=y
> -CONFIG_MTD_BLOCK=y
> -CONFIG_MTD_ROM=y
> -CONFIG_MTD_COMPLEX_MAPPINGS=y
> -CONFIG_MTD_RAW_NAND=y
> -CONFIG_MTD_NAND_SHARPSL=y
> -CONFIG_BLK_DEV_LOOP=y
> -CONFIG_BLK_DEV_SD=y
> -CONFIG_CHR_DEV_ST=m
> -CONFIG_CHR_DEV_OSST=m
> -CONFIG_BLK_DEV_SR=m
> -CONFIG_CHR_DEV_SG=m
> -# CONFIG_BLK_DEV_BSG is not set
> -CONFIG_ATA=y
> -CONFIG_PATA_PCMCIA=y
> -CONFIG_NETDEVICES=y
> -CONFIG_PCMCIA_PCNET=m
> -CONFIG_PPP=m
> -CONFIG_PPP_BSDCOMP=m
> -CONFIG_PPP_ASYNC=m
> -CONFIG_USB_CATC=m
> -CONFIG_USB_KAWETH=m
> -CONFIG_USB_PEGASUS=m
> -CONFIG_USB_RTL8150=m
> -CONFIG_USB_USBNET=m
> -# CONFIG_USB_NET_CDC_SUBSET is not set
> -CONFIG_NET_PCMCIA=y
> -CONFIG_INPUT_FF_MEMLESS=m
> -# CONFIG_INPUT_MOUSEDEV is not set
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_KEYBOARD_ATKBD is not set
> -# CONFIG_INPUT_MOUSE is not set
> -CONFIG_INPUT_TOUCHSCREEN=y
> -CONFIG_TOUCHSCREEN_ADS7846=y
> -CONFIG_INPUT_MISC=y
> -CONFIG_INPUT_UINPUT=m
> -# CONFIG_SERIO is not set
> -# CONFIG_LEGACY_PTYS is not set
> -CONFIG_SERIAL_8250=m
> -CONFIG_SERIAL_8250_CS=m
> -CONFIG_SERIAL_PXA=y
> -CONFIG_SERIAL_PXA_CONSOLE=y
> -CONFIG_SPI=y
> -CONFIG_SPI_PXA2XX=y
> -CONFIG_FB=y
> -CONFIG_FB_PXA=y
> -CONFIG_LCD_CLASS_DEVICE=y
> -CONFIG_LCD_CORGI=y
> -CONFIG_BACKLIGHT_CLASS_DEVICE=y
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
> -CONFIG_HID_A4TECH=m
> -CONFIG_HID_APPLE=m
> -CONFIG_HID_BELKIN=m
> -CONFIG_HID_CHERRY=m
> -CONFIG_HID_CHICONY=m
> -CONFIG_HID_CYPRESS=m
> -CONFIG_HID_EZKEY=m
> -CONFIG_HID_GYRATION=m
> -CONFIG_HID_LOGITECH=m
> -CONFIG_HID_MICROSOFT=m
> -CONFIG_HID_MONTEREY=m
> -CONFIG_HID_PANTHERLORD=m
> -CONFIG_HID_PETALYNX=m
> -CONFIG_HID_SAMSUNG=m
> -CONFIG_HID_SONY=m
> -CONFIG_HID_SUNPLUS=m
> -CONFIG_USB_KBD=m
> -CONFIG_USB_MOUSE=m
> -CONFIG_USB=m
> -CONFIG_USB_MON=m
> -CONFIG_USB_OHCI_HCD=m
> -CONFIG_USB_SL811_HCD=m
> -CONFIG_USB_SL811_CS=m
> -CONFIG_USB_ACM=m
> -CONFIG_USB_PRINTER=m
> -CONFIG_USB_STORAGE=m
> -CONFIG_USB_MDC800=m
> -CONFIG_USB_MICROTEK=m
> -CONFIG_USB_SERIAL=m
> -CONFIG_USB_SERIAL_GENERIC=y
> -CONFIG_USB_SERIAL_BELKIN=m
> -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
> -CONFIG_USB_SERIAL_CYPRESS_M8=m
> -CONFIG_USB_SERIAL_EMPEG=m
> -CONFIG_USB_SERIAL_FTDI_SIO=m
> -CONFIG_USB_SERIAL_VISOR=m
> -CONFIG_USB_SERIAL_IPAQ=m
> -CONFIG_USB_SERIAL_IR=m
> -CONFIG_USB_SERIAL_EDGEPORT=m
> -CONFIG_USB_SERIAL_EDGEPORT_TI=m
> -CONFIG_USB_SERIAL_GARMIN=m
> -CONFIG_USB_SERIAL_IPW=m
> -CONFIG_USB_SERIAL_KEYSPAN_PDA=m
> -CONFIG_USB_SERIAL_KEYSPAN=m
> -CONFIG_USB_SERIAL_KLSI=m
> -CONFIG_USB_SERIAL_KOBIL_SCT=m
> -CONFIG_USB_SERIAL_MCT_U232=m
> -CONFIG_USB_SERIAL_PL2303=m
> -CONFIG_USB_SERIAL_SAFE=m
> -CONFIG_USB_SERIAL_TI=m
> -CONFIG_USB_SERIAL_CYBERJACK=m
> -CONFIG_USB_SERIAL_OMNINET=m
> -CONFIG_USB_EMI62=m
> -CONFIG_USB_EMI26=m
> -CONFIG_USB_LEGOTOWER=m
> -CONFIG_USB_LCD=m
> -CONFIG_USB_CYTHERM=m
> -CONFIG_USB_IDMOUSE=m
> -CONFIG_USB_GADGET=m
> -CONFIG_USB_GADGET_DUMMY_HCD=y
> -CONFIG_USB_ZERO=m
> -CONFIG_USB_ETH=m
> -CONFIG_USB_GADGETFS=m
> -CONFIG_USB_MASS_STORAGE=m
> -CONFIG_USB_G_SERIAL=m
> -CONFIG_MMC=y
> -CONFIG_MMC_PXA=y
> -CONFIG_EXT2_FS=y
> -CONFIG_EXT2_FS_XATTR=y
> -CONFIG_EXT2_FS_POSIX_ACL=y
> -CONFIG_EXT2_FS_SECURITY=y
> -CONFIG_EXT4_FS=y
> -# CONFIG_EXT4_FS_XATTR is not set
> -CONFIG_MSDOS_FS=y
> -CONFIG_VFAT_FS=y
> -CONFIG_TMPFS=y
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_SUMMARY=y
> -CONFIG_JFFS2_COMPRESSION_OPTIONS=y
> -CONFIG_JFFS2_RUBIN=y
> -CONFIG_CRAMFS=m
> -CONFIG_NFS_FS=m
> -CONFIG_NFS_V3=y
> -CONFIG_NFS_V4=y
> -CONFIG_SMB_FS=m
> -CONFIG_SMB_NLS_DEFAULT=y
> -CONFIG_NFS_V4=m
> -CONFIG_NLS_DEFAULT="cp437"
> -CONFIG_NLS_CODEPAGE_437=y
> -CONFIG_NLS_ISO8859_1=y
> -CONFIG_NLS_UTF8=y
> -CONFIG_DEBUG_KERNEL=y
> -CONFIG_CRYPTO_NULL=m
> -CONFIG_CRYPTO_BENCHMARK=m
> -CONFIG_CRYPTO_ECB=m
> -CONFIG_CRYPTO_SHA256=m
> -CONFIG_CRYPTO_AES=m
> -CONFIG_CRYPTO_ANUBIS=m
> -CONFIG_CRYPTO_ARC4=m
> -CONFIG_CRYPTO_BLOWFISH=m
> -CONFIG_CRYPTO_CAST5=m
> -CONFIG_CRYPTO_CAST6=m
> -CONFIG_CRYPTO_KHAZAD=m
> -CONFIG_CRYPTO_SERPENT=m
> -CONFIG_CRYPTO_TEA=m
> -CONFIG_CRYPTO_TWOFISH=m
> -CONFIG_CRYPTO_HMAC=y
> -CONFIG_CRYPTO_MD4=m
> -CONFIG_CRYPTO_SHA512=m
> -CONFIG_CRYPTO_WP512=m
> -CONFIG_FONTS=y
> -CONFIG_FONT_8x8=y
> -CONFIG_FONT_8x16=y
> -CONFIG_MAGIC_SYSRQ=y
> -# CONFIG_DEBUG_PREEMPT is not set
> -# CONFIG_FTRACE is not set
> diff --git a/arch/arm/include/asm/hardware/scoop.h b/arch/arm/include/asm/hardware/scoop.h
> deleted file mode 100644
> index 505453315287..000000000000
> --- a/arch/arm/include/asm/hardware/scoop.h
> +++ /dev/null
> @@ -1,67 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * Definitions for the SCOOP interface found on various Sharp PDAs
> - *
> - * Copyright (c) 2004 Richard Purdie
> - */
> -
> -#define SCOOP_MCR 0x00
> -#define SCOOP_CDR 0x04
> -#define SCOOP_CSR 0x08
> -#define SCOOP_CPR 0x0C
> -#define SCOOP_CCR 0x10
> -#define SCOOP_IRR 0x14
> -#define SCOOP_IRM 0x14
> -#define SCOOP_IMR 0x18
> -#define SCOOP_ISR 0x1C
> -#define SCOOP_GPCR 0x20
> -#define SCOOP_GPWR 0x24
> -#define SCOOP_GPRR 0x28
> -
> -#define SCOOP_CPR_OUT (1 << 7)
> -#define SCOOP_CPR_SD_3V (1 << 2)
> -#define SCOOP_CPR_CF_XV (1 << 1)
> -#define SCOOP_CPR_CF_3V (1 << 0)
> -
> -#define SCOOP_GPCR_PA22 (1 << 12)
> -#define SCOOP_GPCR_PA21 (1 << 11)
> -#define SCOOP_GPCR_PA20 (1 << 10)
> -#define SCOOP_GPCR_PA19 (1 << 9)
> -#define SCOOP_GPCR_PA18 (1 << 8)
> -#define SCOOP_GPCR_PA17 (1 << 7)
> -#define SCOOP_GPCR_PA16 (1 << 6)
> -#define SCOOP_GPCR_PA15 (1 << 5)
> -#define SCOOP_GPCR_PA14 (1 << 4)
> -#define SCOOP_GPCR_PA13 (1 << 3)
> -#define SCOOP_GPCR_PA12 (1 << 2)
> -#define SCOOP_GPCR_PA11 (1 << 1)
> -
> -struct scoop_config {
> - unsigned short io_out;
> - unsigned short io_dir;
> - unsigned short suspend_clr;
> - unsigned short suspend_set;
> - int gpio_base;
> -};
> -
> -/* Structure for linking scoop devices to PCMCIA sockets */
> -struct scoop_pcmcia_dev {
> - struct device *dev; /* Pointer to this socket's scoop device */
> - int irq; /* irq for socket */
> - int cd_irq;
> - const char *cd_irq_str;
> - unsigned char keep_vs;
> - unsigned char keep_rd;
> -};
> -
> -struct scoop_pcmcia_config {
> - struct scoop_pcmcia_dev *devs;
> - int num_devs;
> - void (*power_ctrl)(struct device *scoop, unsigned short cpr, int nr);
> -};
> -
> -extern struct scoop_pcmcia_config *platform_scoop_config;
> -
> -void reset_scoop(struct device *dev);
> -unsigned short read_scoop_reg(struct device *dev, unsigned short reg);
> -void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data);
> diff --git a/arch/arm/include/asm/mach/sharpsl_param.h b/arch/arm/include/asm/mach/sharpsl_param.h
> deleted file mode 100644
> index 700a377c20bf..000000000000
> --- a/arch/arm/include/asm/mach/sharpsl_param.h
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * Hardware parameter area specific to Sharp SL series devices
> - *
> - * Copyright (c) 2005 Richard Purdie
> - *
> - * Based on Sharp's 2.4 kernel patches
> - */
> -
> -struct sharpsl_param_info {
> - unsigned int comadj_keyword;
> - unsigned int comadj;
> -
> - unsigned int uuid_keyword;
> - unsigned char uuid[16];
> -
> - unsigned int touch_keyword;
> - unsigned int touch_xp;
> - unsigned int touch_yp;
> - unsigned int touch_xd;
> - unsigned int touch_yd;
> -
> - unsigned int adadj_keyword;
> - unsigned int adadj;
> -
> - unsigned int phad_keyword;
> - unsigned int phadadj;
> -} __attribute__((packed));
> -
> -
> -extern struct sharpsl_param_info sharpsl_param;
> -extern void sharpsl_save_param(void);
> -
> diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
> index 2fb29b9ef744..354e3dc17776 100644
> --- a/arch/arm/mach-pxa/Kconfig
> +++ b/arch/arm/mach-pxa/Kconfig
> @@ -50,77 +50,6 @@ config MACH_PXA3XX_DT
> the device tree. Needn't select any other machine while
> MACH_PXA3XX_DT is enabled.
>
> -if ATAGS
> -
> -comment "Legacy board files"
> -
> -config ARCH_GUMSTIX
> - bool "Gumstix XScale 255 boards (DEPRECATED)"
> - select PXA25x
> - help
> - Say Y here if you intend to run this kernel on
> - Basix, Connex, ws-200ax, ws-400ax systems
> -
> - Support for this machine will go away in early 2027,
> - unless it gets converted to device tree.
> -
> -choice
> - prompt "Gumstix Carrier/Expansion Board"
> - depends on ARCH_GUMSTIX
> -
> -config GUMSTIX_AM200EPD
> - bool "Enable AM200EPD board support"
> -
> -config GUMSTIX_AM300EPD
> - bool "Enable AM300EPD board support"
> -
> -endchoice
> -
> -config PXA_SHARPSL
> - bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models (DEPRECATED)"
> - select SHARP_PARAM
> - select SHARP_SCOOP
> - help
> - Say Y here if you intend to run this kernel on a
> - Sharp Zaurus SL-5600 (Poodle), SL-C700 (Corgi),
> - SL-C750 (Shepherd), SL-C760 (Husky), SL-C1000 (Akita),
> - SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa)
> - handheld computer.
> -
> - Support for these machines will go away in early 2027,
> - unless they get converted to device tree.
> -
> -config PXA_SHARPSL_DETECT_MACH_ID
> - bool "Detect machine ID at run-time in the decompressor"
> - depends on PXA_SHARPSL
> - help
> - Say Y here if you want the zImage decompressor to detect
> - the Zaurus machine ID at run-time. For latest kexec-based
> - boot loader, this is not necessary.
> -
> -config MACH_AKITA
> - bool "Enable Sharp SL-1000 (Akita) Support"
> - depends on PXA_SHARPSL
> - select I2C
> - select I2C_PXA
> - select MACH_SPITZ
> - select PXA27x
> - select PXA_SHARP_Cxx00
> -
> -config MACH_SPITZ
> - bool "Enable Sharp Zaurus SL-3000 (Spitz) Support"
> - depends on PXA_SHARPSL
> - select PXA27x
> - select PXA_SHARP_Cxx00
> -
> -config MACH_BORZOI
> - bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support"
> - depends on PXA_SHARPSL
> - select PXA27x
> - select PXA_SHARP_Cxx00
> -
> -endif # ATAGS
> -
> config PXA25x
> bool
> select CPU_XSCALE
> @@ -157,22 +86,4 @@ config CPU_PXA320
> help
> PXA320 (codename Monahans-P)
>
> -config PXA_SHARP_Cxx00
> - bool
> - select SHARPSL_PM
> - help
> - Enable common support for Sharp Cxx00 models
> -
> -config SHARPSL_PM
> - bool
> - select APM_EMULATION
> - select SHARPSL_PM_MAX1111
> -
> -config SHARPSL_PM_MAX1111
> - bool
> - select HWMON
> - select SENSORS_MAX1111
> - select SPI
> - select SPI_MASTER
> -
> endif
> diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
> index faccdd356482..3bc3b2e56afe 100644
> --- a/arch/arm/mach-pxa/Makefile
> +++ b/arch/arm/mach-pxa/Makefile
> @@ -22,11 +22,3 @@ obj-$(CONFIG_CPU_PXA320) += pxa320.o
> obj-$(CONFIG_MACH_PXA25X_DT) += pxa-dt.o
> obj-$(CONFIG_MACH_PXA27X_DT) += pxa-dt.o
> obj-$(CONFIG_MACH_PXA3XX_DT) += pxa-dt.o
> -
> -# 3rd Party Dev Platforms
> -obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o
> -obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o
> -obj-$(CONFIG_GUMSTIX_AM300EPD) += am300epd.o
> -
> -# End-user Products
> -obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o
> diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c
> deleted file mode 100644
> index 4814f3cfe775..000000000000
> --- a/arch/arm/mach-pxa/am200epd.c
> +++ /dev/null
> @@ -1,395 +0,0 @@
> -/*
> - * am200epd.c -- Platform device for AM200 EPD kit
> - *
> - * Copyright (C) 2008, Jaya Kumar
> - *
> - * This file is subject to the terms and conditions of the GNU General Public
> - * License. See the file COPYING in the main directory of this archive for
> - * more details.
> - *
> - * Layout is based on skeletonfb.c by James Simmons and Geert Uytterhoeven.
> - *
> - * This work was made possible by help and equipment support from E-Ink
> - * Corporation. http://support.eink.com/community
> - *
> - * This driver is written to be used with the Metronome display controller.
> - * on the AM200 EPD prototype kit/development kit with an E-Ink 800x600
> - * Vizplex EPD on a Gumstix board using the Lyre interface board.
> - *
> - */
> -
> -#include <linux/module.h>
> -#include <linux/kernel.h>
> -#include <linux/errno.h>
> -#include <linux/string.h>
> -#include <linux/delay.h>
> -#include <linux/interrupt.h>
> -#include <linux/fb.h>
> -#include <linux/init.h>
> -#include <linux/platform_device.h>
> -#include <linux/irq.h>
> -#include <linux/gpio/legacy.h>
> -
> -#include "pxa25x.h"
> -#include "gumstix.h"
> -#include <linux/platform_data/video-pxafb.h>
> -
> -#include "generic.h"
> -
> -#include <video/metronomefb.h>
> -
> -static unsigned int panel_type = 6;
> -static struct platform_device *am200_device;
> -static struct metronome_board am200_board;
> -
> -static struct pxafb_mode_info am200_fb_mode_9inch7 = {
> - .pixclock = 40000,
> - .xres = 1200,
> - .yres = 842,
> - .bpp = 16,
> - .hsync_len = 2,
> - .left_margin = 2,
> - .right_margin = 2,
> - .vsync_len = 1,
> - .upper_margin = 2,
> - .lower_margin = 25,
> - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
> -};
> -
> -static struct pxafb_mode_info am200_fb_mode_8inch = {
> - .pixclock = 40000,
> - .xres = 1088,
> - .yres = 791,
> - .bpp = 16,
> - .hsync_len = 28,
> - .left_margin = 8,
> - .right_margin = 30,
> - .vsync_len = 8,
> - .upper_margin = 10,
> - .lower_margin = 8,
> - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
> -};
> -
> -static struct pxafb_mode_info am200_fb_mode_6inch = {
> - .pixclock = 40189,
> - .xres = 832,
> - .yres = 622,
> - .bpp = 16,
> - .hsync_len = 28,
> - .left_margin = 34,
> - .right_margin = 34,
> - .vsync_len = 25,
> - .upper_margin = 0,
> - .lower_margin = 2,
> - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
> -};
> -
> -static struct pxafb_mach_info am200_fb_info = {
> - .modes = &am200_fb_mode_6inch,
> - .num_modes = 1,
> - .lcd_conn = LCD_TYPE_COLOR_TFT | LCD_PCLK_EDGE_FALL |
> - LCD_AC_BIAS_FREQ(24),
> -};
> -
> -/* register offsets for gpio control */
> -#define LED_GPIO_PIN 51
> -#define STDBY_GPIO_PIN 48
> -#define RST_GPIO_PIN 49
> -#define RDY_GPIO_PIN 32
> -#define ERR_GPIO_PIN 17
> -#define PCBPWR_GPIO_PIN 16
> -static int gpios[] = { LED_GPIO_PIN , STDBY_GPIO_PIN , RST_GPIO_PIN,
> - RDY_GPIO_PIN, ERR_GPIO_PIN, PCBPWR_GPIO_PIN };
> -static char *gpio_names[] = { "LED" , "STDBY" , "RST", "RDY", "ERR", "PCBPWR" };
> -
> -static int am200_init_gpio_regs(struct metronomefb_par *par)
> -{
> - int i;
> - int err;
> -
> - for (i = 0; i < ARRAY_SIZE(gpios); i++) {
> - err = gpio_request(gpios[i], gpio_names[i]);
> - if (err) {
> - dev_err(&am200_device->dev, "failed requesting "
> - "gpio %s, err=%d\n", gpio_names[i], err);
> - goto err_req_gpio;
> - }
> - }
> -
> - gpio_direction_output(LED_GPIO_PIN, 0);
> - gpio_direction_output(STDBY_GPIO_PIN, 0);
> - gpio_direction_output(RST_GPIO_PIN, 0);
> -
> - gpio_direction_input(RDY_GPIO_PIN);
> - gpio_direction_input(ERR_GPIO_PIN);
> -
> - gpio_direction_output(PCBPWR_GPIO_PIN, 0);
> -
> - return 0;
> -
> -err_req_gpio:
> - while (--i >= 0)
> - gpio_free(gpios[i]);
> -
> - return err;
> -}
> -
> -static void am200_cleanup(struct metronomefb_par *par)
> -{
> - int i;
> -
> - free_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), par);
> -
> - for (i = 0; i < ARRAY_SIZE(gpios); i++)
> - gpio_free(gpios[i]);
> -}
> -
> -static int am200_share_video_mem(struct fb_info *info)
> -{
> - /* rough check if this is our desired fb and not something else */
> - if ((info->var.xres != am200_fb_info.modes->xres)
> - || (info->var.yres != am200_fb_info.modes->yres))
> - return 0;
> -
> - /* we've now been notified that we have our new fb */
> - am200_board.metromem = info->screen_base;
> - am200_board.host_fbinfo = info;
> -
> - /* try to refcount host drv since we are the consumer after this */
> - if (!try_module_get(info->fbops->owner))
> - return -ENODEV;
> -
> - return 0;
> -}
> -
> -static int am200_unshare_video_mem(struct fb_info *info)
> -{
> - dev_dbg(&am200_device->dev, "ENTER %s\n", __func__);
> -
> - if (info != am200_board.host_fbinfo)
> - return 0;
> -
> - module_put(am200_board.host_fbinfo->fbops->owner);
> - return 0;
> -}
> -
> -static int am200_fb_notifier_callback(struct notifier_block *self,
> - unsigned long event, void *data)
> -{
> - struct fb_event *evdata = data;
> - struct fb_info *info = evdata->info;
> -
> - dev_dbg(&am200_device->dev, "ENTER %s\n", __func__);
> -
> - if (event == FB_EVENT_FB_REGISTERED)
> - return am200_share_video_mem(info);
> - else if (event == FB_EVENT_FB_UNREGISTERED)
> - return am200_unshare_video_mem(info);
> -
> - return 0;
> -}
> -
> -static struct notifier_block am200_fb_notif = {
> - .notifier_call = am200_fb_notifier_callback,
> -};
> -
> -/* this gets called as part of our init. these steps must be done now so
> - * that we can use pxa_set_fb_info */
> -static void __init am200_presetup_fb(void)
> -{
> - int fw;
> - int fh;
> - int padding_size;
> - int totalsize;
> -
> - switch (panel_type) {
> - case 6:
> - am200_fb_info.modes = &am200_fb_mode_6inch;
> - break;
> - case 8:
> - am200_fb_info.modes = &am200_fb_mode_8inch;
> - break;
> - case 97:
> - am200_fb_info.modes = &am200_fb_mode_9inch7;
> - break;
> - default:
> - dev_err(&am200_device->dev, "invalid panel_type selection,"
> - " setting to 6\n");
> - am200_fb_info.modes = &am200_fb_mode_6inch;
> - break;
> - }
> -
> - /* the frame buffer is divided as follows:
> - command | CRC | padding
> - 16kb waveform data | CRC | padding
> - image data | CRC
> - */
> -
> - fw = am200_fb_info.modes->xres;
> - fh = am200_fb_info.modes->yres;
> -
> - /* waveform must be 16k + 2 for checksum */
> - am200_board.wfm_size = roundup(16*1024 + 2, fw);
> -
> - padding_size = PAGE_SIZE + (4 * fw);
> -
> - /* total is 1 cmd , 1 wfm, padding and image */
> - totalsize = fw + am200_board.wfm_size + padding_size + (fw*fh);
> -
> - /* save this off because we're manipulating fw after this and
> - * we'll need it when we're ready to setup the framebuffer */
> - am200_board.fw = fw;
> - am200_board.fh = fh;
> -
> - /* the reason we do this adjustment is because we want to acquire
> - * more framebuffer memory without imposing custom awareness on the
> - * underlying pxafb driver */
> - am200_fb_info.modes->yres = DIV_ROUND_UP(totalsize, fw);
> -
> - /* we divide since we told the LCD controller we're 16bpp */
> - am200_fb_info.modes->xres /= 2;
> -
> - pxa_set_fb_info(NULL, &am200_fb_info);
> -
> -}
> -
> -/* this gets called by metronomefb as part of its init, in our case, we
> - * have already completed initial framebuffer init in presetup_fb so we
> - * can just setup the fb access pointers */
> -static int am200_setup_fb(struct metronomefb_par *par)
> -{
> - int fw;
> - int fh;
> -
> - fw = am200_board.fw;
> - fh = am200_board.fh;
> -
> - /* metromem was set up by the notifier in share_video_mem so now
> - * we can use its value to calculate the other entries */
> - par->metromem_cmd = (struct metromem_cmd *) am200_board.metromem;
> - par->metromem_wfm = am200_board.metromem + fw;
> - par->metromem_img = par->metromem_wfm + am200_board.wfm_size;
> - par->metromem_img_csum = (u16 *) (par->metromem_img + (fw * fh));
> - par->metromem_dma = am200_board.host_fbinfo->fix.smem_start;
> -
> - return 0;
> -}
> -
> -static int am200_get_panel_type(void)
> -{
> - return panel_type;
> -}
> -
> -static irqreturn_t am200_handle_irq(int irq, void *dev_id)
> -{
> - struct metronomefb_par *par = dev_id;
> -
> - wake_up_interruptible(&par->waitq);
> - return IRQ_HANDLED;
> -}
> -
> -static int am200_setup_irq(struct fb_info *info)
> -{
> - int ret;
> -
> - ret = request_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), am200_handle_irq,
> - IRQF_TRIGGER_FALLING, "AM200", info->par);
> - if (ret)
> - dev_err(&am200_device->dev, "request_irq failed: %d\n", ret);
> -
> - return ret;
> -}
> -
> -static void am200_set_rst(struct metronomefb_par *par, int state)
> -{
> - gpio_set_value(RST_GPIO_PIN, state);
> -}
> -
> -static void am200_set_stdby(struct metronomefb_par *par, int state)
> -{
> - gpio_set_value(STDBY_GPIO_PIN, state);
> -}
> -
> -static int am200_wait_event(struct metronomefb_par *par)
> -{
> - return wait_event_timeout(par->waitq, gpio_get_value(RDY_GPIO_PIN), HZ);
> -}
> -
> -static int am200_wait_event_intr(struct metronomefb_par *par)
> -{
> - return wait_event_interruptible_timeout(par->waitq,
> - gpio_get_value(RDY_GPIO_PIN), HZ);
> -}
> -
> -static struct metronome_board am200_board = {
> - .owner = THIS_MODULE,
> - .setup_irq = am200_setup_irq,
> - .setup_io = am200_init_gpio_regs,
> - .setup_fb = am200_setup_fb,
> - .set_rst = am200_set_rst,
> - .set_stdby = am200_set_stdby,
> - .met_wait_event = am200_wait_event,
> - .met_wait_event_intr = am200_wait_event_intr,
> - .get_panel_type = am200_get_panel_type,
> - .cleanup = am200_cleanup,
> -};
> -
> -static unsigned long am200_pin_config[] __initdata = {
> - GPIO51_GPIO,
> - GPIO49_GPIO,
> - GPIO48_GPIO,
> - GPIO32_GPIO,
> - GPIO17_GPIO,
> - GPIO16_GPIO,
> -};
> -
> -int __init am200_init(void)
> -{
> - int ret;
> -
> - /*
> - * Before anything else, we request notification for any fb
> - * creation events.
> - *
> - * FIXME: This is terrible and needs to be nuked. The notifier is used
> - * to get at the fb base address from the boot splash fb driver, which
> - * is then passed to metronomefb. Instaed of metronomfb or this board
> - * support file here figuring this out on their own.
> - *
> - * See also the #ifdef in fbmem.c.
> - */
> - fb_register_client(&am200_fb_notif);
> -
> - pxa2xx_mfp_config(ARRAY_AND_SIZE(am200_pin_config));
> -
> - /* request our platform independent driver */
> - request_module("metronomefb");
> -
> - am200_device = platform_device_alloc("metronomefb", -1);
> - if (!am200_device)
> - return -ENOMEM;
> -
> - /* the am200_board that will be seen by metronomefb is a copy */
> - platform_device_add_data(am200_device, &am200_board,
> - sizeof(am200_board));
> -
> - /* this _add binds metronomefb to am200. metronomefb refcounts am200 */
> - ret = platform_device_add(am200_device);
> -
> - if (ret) {
> - platform_device_put(am200_device);
> - fb_unregister_client(&am200_fb_notif);
> - return ret;
> - }
> -
> - am200_presetup_fb();
> -
> - return 0;
> -}
> -
> -module_param(panel_type, uint, 0);
> -MODULE_PARM_DESC(panel_type, "Select the panel type: 6, 8, 97");
> -
> -MODULE_DESCRIPTION("board driver for am200 metronome epd kit");
> -MODULE_AUTHOR("Jaya Kumar");
> -MODULE_LICENSE("GPL");
> diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c
> deleted file mode 100644
> index 435fb72da7de..000000000000
> --- a/arch/arm/mach-pxa/am300epd.c
> +++ /dev/null
> @@ -1,296 +0,0 @@
> -/*
> - * am300epd.c -- Platform device for AM300 EPD kit
> - *
> - * Copyright (C) 2008, Jaya Kumar
> - *
> - * This file is subject to the terms and conditions of the GNU General Public
> - * License. See the file COPYING in the main directory of this archive for
> - * more details.
> - *
> - * This work was made possible by help and equipment support from E-Ink
> - * Corporation. http://support.eink.com/community
> - *
> - * This driver is written to be used with the Broadsheet display controller.
> - * on the AM300 EPD prototype kit/development kit with an E-Ink 800x600
> - * Vizplex EPD on a Gumstix board using the Broadsheet interface board.
> - *
> - */
> -
> -#include <linux/module.h>
> -#include <linux/kernel.h>
> -#include <linux/errno.h>
> -#include <linux/string.h>
> -#include <linux/delay.h>
> -#include <linux/interrupt.h>
> -#include <linux/fb.h>
> -#include <linux/init.h>
> -#include <linux/platform_device.h>
> -#include <linux/irq.h>
> -#include <linux/gpio/legacy.h>
> -
> -#include "gumstix.h"
> -#include "mfp-pxa25x.h"
> -#include "irqs.h"
> -#include <linux/platform_data/video-pxafb.h>
> -
> -#include "generic.h"
> -
> -#include <video/broadsheetfb.h>
> -
> -static unsigned int panel_type = 6;
> -static struct platform_device *am300_device;
> -static struct broadsheet_board am300_board;
> -
> -static unsigned long am300_pin_config[] __initdata = {
> - GPIO16_GPIO,
> - GPIO17_GPIO,
> - GPIO32_GPIO,
> - GPIO48_GPIO,
> - GPIO49_GPIO,
> - GPIO51_GPIO,
> - GPIO74_GPIO,
> - GPIO75_GPIO,
> - GPIO76_GPIO,
> - GPIO77_GPIO,
> -
> - /* this is the 16-bit hdb bus 58-73 */
> - GPIO58_GPIO,
> - GPIO59_GPIO,
> - GPIO60_GPIO,
> - GPIO61_GPIO,
> -
> - GPIO62_GPIO,
> - GPIO63_GPIO,
> - GPIO64_GPIO,
> - GPIO65_GPIO,
> -
> - GPIO66_GPIO,
> - GPIO67_GPIO,
> - GPIO68_GPIO,
> - GPIO69_GPIO,
> -
> - GPIO70_GPIO,
> - GPIO71_GPIO,
> - GPIO72_GPIO,
> - GPIO73_GPIO,
> -};
> -
> -/* register offsets for gpio control */
> -#define PWR_GPIO_PIN 16
> -#define CFG_GPIO_PIN 17
> -#define RDY_GPIO_PIN 32
> -#define DC_GPIO_PIN 48
> -#define RST_GPIO_PIN 49
> -#define LED_GPIO_PIN 51
> -#define RD_GPIO_PIN 74
> -#define WR_GPIO_PIN 75
> -#define CS_GPIO_PIN 76
> -#define IRQ_GPIO_PIN 77
> -
> -/* hdb bus */
> -#define DB0_GPIO_PIN 58
> -#define DB15_GPIO_PIN 73
> -
> -static int gpios[] = { PWR_GPIO_PIN, CFG_GPIO_PIN, RDY_GPIO_PIN, DC_GPIO_PIN,
> - RST_GPIO_PIN, RD_GPIO_PIN, WR_GPIO_PIN, CS_GPIO_PIN,
> - IRQ_GPIO_PIN, LED_GPIO_PIN };
> -static char *gpio_names[] = { "PWR", "CFG", "RDY", "DC", "RST", "RD", "WR",
> - "CS", "IRQ", "LED" };
> -
> -static int am300_wait_event(struct broadsheetfb_par *par)
> -{
> - /* todo: improve err recovery */
> - wait_event(par->waitq, gpio_get_value(RDY_GPIO_PIN));
> - return 0;
> -}
> -
> -static int am300_init_gpio_regs(struct broadsheetfb_par *par)
> -{
> - int i;
> - int err;
> - char dbname[8];
> -
> - for (i = 0; i < ARRAY_SIZE(gpios); i++) {
> - err = gpio_request(gpios[i], gpio_names[i]);
> - if (err) {
> - dev_err(&am300_device->dev, "failed requesting "
> - "gpio %s, err=%d\n", gpio_names[i], err);
> - goto err_req_gpio;
> - }
> - }
> -
> - /* we also need to take care of the hdb bus */
> - for (i = DB0_GPIO_PIN; i <= DB15_GPIO_PIN; i++) {
> - sprintf(dbname, "DB%d", i);
> - err = gpio_request(i, dbname);
> - if (err) {
> - dev_err(&am300_device->dev, "failed requesting "
> - "gpio %d, err=%d\n", i, err);
> - goto err_req_gpio2;
> - }
> - }
> -
> - /* setup the outputs and init values */
> - gpio_direction_output(PWR_GPIO_PIN, 0);
> - gpio_direction_output(CFG_GPIO_PIN, 1);
> - gpio_direction_output(DC_GPIO_PIN, 0);
> - gpio_direction_output(RD_GPIO_PIN, 1);
> - gpio_direction_output(WR_GPIO_PIN, 1);
> - gpio_direction_output(CS_GPIO_PIN, 1);
> - gpio_direction_output(RST_GPIO_PIN, 0);
> -
> - /* setup the inputs */
> - gpio_direction_input(RDY_GPIO_PIN);
> - gpio_direction_input(IRQ_GPIO_PIN);
> -
> - /* start the hdb bus as an input */
> - for (i = DB0_GPIO_PIN; i <= DB15_GPIO_PIN; i++)
> - gpio_direction_output(i, 0);
> -
> - /* go into command mode */
> - gpio_set_value(CFG_GPIO_PIN, 1);
> - gpio_set_value(RST_GPIO_PIN, 0);
> - msleep(10);
> - gpio_set_value(RST_GPIO_PIN, 1);
> - msleep(10);
> - am300_wait_event(par);
> -
> - return 0;
> -
> -err_req_gpio2:
> - while (--i >= DB0_GPIO_PIN)
> - gpio_free(i);
> - i = ARRAY_SIZE(gpios);
> -err_req_gpio:
> - while (--i >= 0)
> - gpio_free(gpios[i]);
> -
> - return err;
> -}
> -
> -static int am300_init_board(struct broadsheetfb_par *par)
> -{
> - return am300_init_gpio_regs(par);
> -}
> -
> -static void am300_cleanup(struct broadsheetfb_par *par)
> -{
> - int i;
> -
> - free_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), par);
> -
> - for (i = 0; i < ARRAY_SIZE(gpios); i++)
> - gpio_free(gpios[i]);
> -
> - for (i = DB0_GPIO_PIN; i <= DB15_GPIO_PIN; i++)
> - gpio_free(i);
> -
> -}
> -
> -static u16 am300_get_hdb(struct broadsheetfb_par *par)
> -{
> - u16 res = 0;
> - int i;
> -
> - for (i = 0; i <= (DB15_GPIO_PIN - DB0_GPIO_PIN) ; i++)
> - res |= (gpio_get_value(DB0_GPIO_PIN + i)) ? (1 << i) : 0;
> -
> - return res;
> -}
> -
> -static void am300_set_hdb(struct broadsheetfb_par *par, u16 data)
> -{
> - int i;
> -
> - for (i = 0; i <= (DB15_GPIO_PIN - DB0_GPIO_PIN) ; i++)
> - gpio_set_value(DB0_GPIO_PIN + i, (data >> i) & 0x01);
> -}
> -
> -
> -static void am300_set_ctl(struct broadsheetfb_par *par, unsigned char bit,
> - u8 state)
> -{
> - switch (bit) {
> - case BS_CS:
> - gpio_set_value(CS_GPIO_PIN, state);
> - break;
> - case BS_DC:
> - gpio_set_value(DC_GPIO_PIN, state);
> - break;
> - case BS_WR:
> - gpio_set_value(WR_GPIO_PIN, state);
> - break;
> - }
> -}
> -
> -static int am300_get_panel_type(void)
> -{
> - return panel_type;
> -}
> -
> -static irqreturn_t am300_handle_irq(int irq, void *dev_id)
> -{
> - struct broadsheetfb_par *par = dev_id;
> -
> - wake_up(&par->waitq);
> - return IRQ_HANDLED;
> -}
> -
> -static int am300_setup_irq(struct fb_info *info)
> -{
> - int ret;
> - struct broadsheetfb_par *par = info->par;
> -
> - ret = request_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), am300_handle_irq,
> - IRQF_TRIGGER_RISING, "AM300", par);
> - if (ret)
> - dev_err(&am300_device->dev, "request_irq failed: %d\n", ret);
> -
> - return ret;
> -}
> -
> -static struct broadsheet_board am300_board = {
> - .owner = THIS_MODULE,
> - .init = am300_init_board,
> - .cleanup = am300_cleanup,
> - .set_hdb = am300_set_hdb,
> - .get_hdb = am300_get_hdb,
> - .set_ctl = am300_set_ctl,
> - .wait_for_rdy = am300_wait_event,
> - .get_panel_type = am300_get_panel_type,
> - .setup_irq = am300_setup_irq,
> -};
> -
> -int __init am300_init(void)
> -{
> - int ret;
> -
> - pxa2xx_mfp_config(ARRAY_AND_SIZE(am300_pin_config));
> -
> - /* request our platform independent driver */
> - request_module("broadsheetfb");
> -
> - am300_device = platform_device_alloc("broadsheetfb", -1);
> - if (!am300_device)
> - return -ENOMEM;
> -
> - /* the am300_board that will be seen by broadsheetfb is a copy */
> - platform_device_add_data(am300_device, &am300_board,
> - sizeof(am300_board));
> -
> - ret = platform_device_add(am300_device);
> -
> - if (ret) {
> - platform_device_put(am300_device);
> - return ret;
> - }
> -
> - return 0;
> -}
> -
> -module_param(panel_type, uint, 0);
> -MODULE_PARM_DESC(panel_type, "Select the panel type: 37, 6, 97");
> -
> -MODULE_DESCRIPTION("board driver for am300 epd kit");
> -MODULE_AUTHOR("Jaya Kumar");
> -MODULE_LICENSE("GPL");
> diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
> index edad956a1483..c2a2469a003a 100644
> --- a/arch/arm/mach-pxa/devices.c
> +++ b/arch/arm/mach-pxa/devices.c
> @@ -1,715 +1,10 @@
> // SPDX-License-Identifier: GPL-2.0
> -#include <linux/module.h>
> -#include <linux/kernel.h>
> #include <linux/init.h>
> #include <linux/platform_device.h>
> -#include <linux/clkdev.h>
> -#include <linux/clk-provider.h>
> -#include <linux/dma-mapping.h>
> -#include <linux/dmaengine.h>
> -#include <linux/gpio-pxa.h>
> -#include <linux/platform_data/i2c-pxa.h>
> -#include <linux/soc/pxa/cpu.h>
>
> -#include <linux/platform_data/video-pxafb.h>
> -#include <linux/platform_data/mmc-pxamci.h>
> #include "irqs.h"
> -#include <linux/platform_data/usb-ohci-pxa27x.h>
> -#include <linux/platform_data/mmp_dma.h>
> -
> -#include "mfp-pxa2xx.h"
> #include "regs-ost.h"
> #include "reset.h"
> -#include "devices.h"
> -#include "generic.h"
> -
> -void __init pxa_register_device(struct platform_device *dev, void *data)
> -{
> - int ret;
> -
> - dev->dev.platform_data = data;
> -
> - ret = platform_device_register(dev);
> - if (ret)
> - dev_err(&dev->dev, "unable to register device: %d\n", ret);
> -}
> -
> -static struct resource pxa_resource_pmu = {
> - .start = IRQ_PMU,
> - .end = IRQ_PMU,
> - .flags = IORESOURCE_IRQ,
> -};
> -
> -struct platform_device pxa_device_pmu = {
> - .name = "xscale-pmu",
> - .id = -1,
> - .resource = &pxa_resource_pmu,
> - .num_resources = 1,
> -};
> -
> -static const struct resource pxamci_resources[] = {
> - [0] = {
> - .start = 0x41100000,
> - .end = 0x41100fff,
> - .flags = IORESOURCE_MEM,
> - },
> - [1] = {
> - .start = IRQ_MMC,
> - .end = IRQ_MMC,
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -void __init pxa_set_mci_info(const struct pxamci_platform_data *info,
> - const struct property_entry *props)
> -{
> - const struct platform_device_info mci_info = {
> - .name = "pxa2xx-mci",
> - .id = 0,
> - .res = pxamci_resources,
> - .num_res = ARRAY_SIZE(pxamci_resources),
> - .data = info,
> - .size_data = sizeof(*info),
> - .dma_mask = 0xffffffffUL,
> - .properties = props,
> - };
> - struct platform_device *mci_dev;
> - int err;
> -
> - mci_dev = platform_device_register_full(&mci_info);
> - err = PTR_ERR_OR_ZERO(mci_dev);
> - if (err)
> - pr_err("Unable to create mci device: %d\n", err);
> -}
> -
> -static struct resource pxa2xx_udc_resources[] = {
> - [0] = {
> - .start = 0x40600000,
> - .end = 0x4060ffff,
> - .flags = IORESOURCE_MEM,
> - },
> - [1] = {
> - .start = IRQ_USB,
> - .end = IRQ_USB,
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -static u64 udc_dma_mask = ~(u32)0;
> -
> -struct platform_device pxa25x_device_udc = {
> - .name = "pxa25x-udc",
> - .id = -1,
> - .resource = pxa2xx_udc_resources,
> - .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
> - .dev = {
> - .dma_mask = &udc_dma_mask,
> - }
> -};
> -
> -struct platform_device pxa27x_device_udc = {
> - .name = "pxa27x-udc",
> - .id = -1,
> - .resource = pxa2xx_udc_resources,
> - .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
> - .dev = {
> - .dma_mask = &udc_dma_mask,
> - }
> -};
> -
> -static struct resource pxafb_resources[] = {
> - [0] = {
> - .start = 0x44000000,
> - .end = 0x4400ffff,
> - .flags = IORESOURCE_MEM,
> - },
> - [1] = {
> - .start = IRQ_LCD,
> - .end = IRQ_LCD,
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -static u64 fb_dma_mask = ~(u64)0;
> -
> -struct platform_device pxa_device_fb = {
> - .name = "pxa2xx-fb",
> - .id = -1,
> - .dev = {
> - .dma_mask = &fb_dma_mask,
> - .coherent_dma_mask = 0xffffffff,
> - },
> - .num_resources = ARRAY_SIZE(pxafb_resources),
> - .resource = pxafb_resources,
> -};
> -
> -void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
> -{
> - pxa_device_fb.dev.parent = parent;
> - pxa_register_device(&pxa_device_fb, info);
> -}
> -
> -static struct resource pxa_resource_ffuart[] = {
> - {
> - .start = 0x40100000,
> - .end = 0x40100023,
> - .flags = IORESOURCE_MEM,
> - }, {
> - .start = IRQ_FFUART,
> - .end = IRQ_FFUART,
> - .flags = IORESOURCE_IRQ,
> - }
> -};
> -
> -struct platform_device pxa_device_ffuart = {
> - .name = "pxa2xx-uart",
> - .id = 0,
> - .resource = pxa_resource_ffuart,
> - .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
> -};
> -
> -void __init pxa_set_ffuart_info(void *info)
> -{
> - pxa_register_device(&pxa_device_ffuart, info);
> -}
> -
> -static struct resource pxa_resource_btuart[] = {
> - {
> - .start = 0x40200000,
> - .end = 0x40200023,
> - .flags = IORESOURCE_MEM,
> - }, {
> - .start = IRQ_BTUART,
> - .end = IRQ_BTUART,
> - .flags = IORESOURCE_IRQ,
> - }
> -};
> -
> -struct platform_device pxa_device_btuart = {
> - .name = "pxa2xx-uart",
> - .id = 1,
> - .resource = pxa_resource_btuart,
> - .num_resources = ARRAY_SIZE(pxa_resource_btuart),
> -};
> -
> -void __init pxa_set_btuart_info(void *info)
> -{
> - pxa_register_device(&pxa_device_btuart, info);
> -}
> -
> -static struct resource pxa_resource_stuart[] = {
> - {
> - .start = 0x40700000,
> - .end = 0x40700023,
> - .flags = IORESOURCE_MEM,
> - }, {
> - .start = IRQ_STUART,
> - .end = IRQ_STUART,
> - .flags = IORESOURCE_IRQ,
> - }
> -};
> -
> -struct platform_device pxa_device_stuart = {
> - .name = "pxa2xx-uart",
> - .id = 2,
> - .resource = pxa_resource_stuart,
> - .num_resources = ARRAY_SIZE(pxa_resource_stuart),
> -};
> -
> -void __init pxa_set_stuart_info(void *info)
> -{
> - pxa_register_device(&pxa_device_stuart, info);
> -}
> -
> -static struct resource pxa_resource_hwuart[] = {
> - {
> - .start = 0x41600000,
> - .end = 0x4160002F,
> - .flags = IORESOURCE_MEM,
> - }, {
> - .start = IRQ_HWUART,
> - .end = IRQ_HWUART,
> - .flags = IORESOURCE_IRQ,
> - }
> -};
> -
> -struct platform_device pxa_device_hwuart = {
> - .name = "pxa2xx-uart",
> - .id = 3,
> - .resource = pxa_resource_hwuart,
> - .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
> -};
> -
> -void __init pxa_set_hwuart_info(void *info)
> -{
> - if (cpu_is_pxa255())
> - pxa_register_device(&pxa_device_hwuart, info);
> - else
> - pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
> -}
> -
> -static struct resource pxai2c_resources[] = {
> - {
> - .start = 0x40301680,
> - .end = 0x403016a3,
> - .flags = IORESOURCE_MEM,
> - }, {
> - .start = IRQ_I2C,
> - .end = IRQ_I2C,
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -struct platform_device pxa_device_i2c = {
> - .name = "pxa2xx-i2c",
> - .id = 0,
> - .resource = pxai2c_resources,
> - .num_resources = ARRAY_SIZE(pxai2c_resources),
> -};
> -
> -void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
> -{
> - pxa_register_device(&pxa_device_i2c, info);
> -}
> -
> -#ifdef CONFIG_PXA27x
> -static struct resource pxa27x_resources_i2c_power[] = {
> - {
> - .start = 0x40f00180,
> - .end = 0x40f001a3,
> - .flags = IORESOURCE_MEM,
> - }, {
> - .start = IRQ_PWRI2C,
> - .end = IRQ_PWRI2C,
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -struct platform_device pxa27x_device_i2c_power = {
> - .name = "pxa2xx-i2c",
> - .id = 1,
> - .resource = pxa27x_resources_i2c_power,
> - .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
> -};
> -#endif
> -
> -static struct resource pxai2s_resources[] = {
> - {
> - .start = 0x40400000,
> - .end = 0x40400083,
> - .flags = IORESOURCE_MEM,
> - }, {
> - .start = IRQ_I2S,
> - .end = IRQ_I2S,
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -struct platform_device pxa_device_i2s = {
> - .name = "pxa2xx-i2s",
> - .id = -1,
> - .resource = pxai2s_resources,
> - .num_resources = ARRAY_SIZE(pxai2s_resources),
> -};
> -
> -struct platform_device pxa_device_asoc_ssp1 = {
> - .name = "pxa-ssp-dai",
> - .id = 0,
> -};
> -
> -struct platform_device pxa_device_asoc_ssp2= {
> - .name = "pxa-ssp-dai",
> - .id = 1,
> -};
> -
> -struct platform_device pxa_device_asoc_ssp3 = {
> - .name = "pxa-ssp-dai",
> - .id = 2,
> -};
> -
> -struct platform_device pxa_device_asoc_ssp4 = {
> - .name = "pxa-ssp-dai",
> - .id = 3,
> -};
> -
> -struct platform_device pxa_device_asoc_platform = {
> - .name = "pxa-pcm-audio",
> - .id = -1,
> -};
> -
> -static struct resource pxa_rtc_resources[] = {
> - [0] = {
> - .start = 0x40900000,
> - .end = 0x40900000 + 0x3b,
> - .flags = IORESOURCE_MEM,
> - },
> - [1] = {
> - .start = IRQ_RTC1Hz,
> - .end = IRQ_RTC1Hz,
> - .name = "rtc 1Hz",
> - .flags = IORESOURCE_IRQ,
> - },
> - [2] = {
> - .start = IRQ_RTCAlrm,
> - .end = IRQ_RTCAlrm,
> - .name = "rtc alarm",
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -struct platform_device pxa_device_rtc = {
> - .name = "pxa-rtc",
> - .id = -1,
> - .num_resources = ARRAY_SIZE(pxa_rtc_resources),
> - .resource = pxa_rtc_resources,
> -};
> -
> -struct platform_device sa1100_device_rtc = {
> - .name = "sa1100-rtc",
> - .id = -1,
> - .num_resources = ARRAY_SIZE(pxa_rtc_resources),
> - .resource = pxa_rtc_resources,
> -};
> -
> -#ifdef CONFIG_PXA25x
> -
> -static struct resource pxa25x_resource_pwm0[] = {
> - [0] = {
> - .start = 0x40b00000,
> - .end = 0x40b0000f,
> - .flags = IORESOURCE_MEM,
> - },
> -};
> -
> -struct platform_device pxa25x_device_pwm0 = {
> - .name = "pxa25x-pwm",
> - .id = 0,
> - .resource = pxa25x_resource_pwm0,
> - .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
> -};
> -
> -static struct resource pxa25x_resource_pwm1[] = {
> - [0] = {
> - .start = 0x40c00000,
> - .end = 0x40c0000f,
> - .flags = IORESOURCE_MEM,
> - },
> -};
> -
> -struct platform_device pxa25x_device_pwm1 = {
> - .name = "pxa25x-pwm",
> - .id = 1,
> - .resource = pxa25x_resource_pwm1,
> - .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
> -};
> -
> -static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
> -
> -static struct resource pxa25x_resource_ssp[] = {
> - [0] = {
> - .start = 0x41000000,
> - .end = 0x4100001f,
> - .flags = IORESOURCE_MEM,
> - },
> - [1] = {
> - .start = IRQ_SSP,
> - .end = IRQ_SSP,
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -struct platform_device pxa25x_device_ssp = {
> - .name = "pxa25x-ssp",
> - .id = 0,
> - .dev = {
> - .dma_mask = &pxa25x_ssp_dma_mask,
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - },
> - .resource = pxa25x_resource_ssp,
> - .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
> -};
> -
> -static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
> -
> -static struct resource pxa25x_resource_nssp[] = {
> - [0] = {
> - .start = 0x41400000,
> - .end = 0x4140002f,
> - .flags = IORESOURCE_MEM,
> - },
> - [1] = {
> - .start = IRQ_NSSP,
> - .end = IRQ_NSSP,
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -struct platform_device pxa25x_device_nssp = {
> - .name = "pxa25x-nssp",
> - .id = 1,
> - .dev = {
> - .dma_mask = &pxa25x_nssp_dma_mask,
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - },
> - .resource = pxa25x_resource_nssp,
> - .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
> -};
> -
> -static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
> -
> -static struct resource pxa25x_resource_assp[] = {
> - [0] = {
> - .start = 0x41500000,
> - .end = 0x4150002f,
> - .flags = IORESOURCE_MEM,
> - },
> - [1] = {
> - .start = IRQ_ASSP,
> - .end = IRQ_ASSP,
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -struct platform_device pxa25x_device_assp = {
> - /* ASSP is basically equivalent to NSSP */
> - .name = "pxa25x-nssp",
> - .id = 2,
> - .dev = {
> - .dma_mask = &pxa25x_assp_dma_mask,
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - },
> - .resource = pxa25x_resource_assp,
> - .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
> -};
> -#endif /* CONFIG_PXA25x */
> -
> -#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
> -static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
> -
> -static struct resource pxa27x_resource_ohci[] = {
> - [0] = {
> - .start = 0x4C000000,
> - .end = 0x4C00ff6f,
> - .flags = IORESOURCE_MEM,
> - },
> - [1] = {
> - .start = IRQ_USBH1,
> - .end = IRQ_USBH1,
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -struct platform_device pxa27x_device_ohci = {
> - .name = "pxa27x-ohci",
> - .id = -1,
> - .dev = {
> - .dma_mask = &pxa27x_ohci_dma_mask,
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - },
> - .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
> - .resource = pxa27x_resource_ohci,
> -};
> -
> -void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
> -{
> - pxa_register_device(&pxa27x_device_ohci, info);
> -}
> -#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
> -
> -#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
> -static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
> -
> -static struct resource pxa27x_resource_ssp1[] = {
> - [0] = {
> - .start = 0x41000000,
> - .end = 0x4100003f,
> - .flags = IORESOURCE_MEM,
> - },
> - [1] = {
> - .start = IRQ_SSP,
> - .end = IRQ_SSP,
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -struct platform_device pxa27x_device_ssp1 = {
> - .name = "pxa27x-ssp",
> - .id = 0,
> - .dev = {
> - .dma_mask = &pxa27x_ssp1_dma_mask,
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - },
> - .resource = pxa27x_resource_ssp1,
> - .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
> -};
> -
> -static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
> -
> -static struct resource pxa27x_resource_ssp2[] = {
> - [0] = {
> - .start = 0x41700000,
> - .end = 0x4170003f,
> - .flags = IORESOURCE_MEM,
> - },
> - [1] = {
> - .start = IRQ_SSP2,
> - .end = IRQ_SSP2,
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -struct platform_device pxa27x_device_ssp2 = {
> - .name = "pxa27x-ssp",
> - .id = 1,
> - .dev = {
> - .dma_mask = &pxa27x_ssp2_dma_mask,
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - },
> - .resource = pxa27x_resource_ssp2,
> - .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
> -};
> -
> -static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
> -
> -static struct resource pxa27x_resource_ssp3[] = {
> - [0] = {
> - .start = 0x41900000,
> - .end = 0x4190003f,
> - .flags = IORESOURCE_MEM,
> - },
> - [1] = {
> - .start = IRQ_SSP3,
> - .end = IRQ_SSP3,
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -struct platform_device pxa27x_device_ssp3 = {
> - .name = "pxa27x-ssp",
> - .id = 2,
> - .dev = {
> - .dma_mask = &pxa27x_ssp3_dma_mask,
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - },
> - .resource = pxa27x_resource_ssp3,
> - .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
> -};
> -
> -static struct resource pxa27x_resource_pwm0[] = {
> - [0] = {
> - .start = 0x40b00000,
> - .end = 0x40b0001f,
> - .flags = IORESOURCE_MEM,
> - },
> -};
> -
> -struct platform_device pxa27x_device_pwm0 = {
> - .name = "pxa27x-pwm",
> - .id = 0,
> - .resource = pxa27x_resource_pwm0,
> - .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
> -};
> -
> -static struct resource pxa27x_resource_pwm1[] = {
> - [0] = {
> - .start = 0x40c00000,
> - .end = 0x40c0001f,
> - .flags = IORESOURCE_MEM,
> - },
> -};
> -
> -struct platform_device pxa27x_device_pwm1 = {
> - .name = "pxa27x-pwm",
> - .id = 1,
> - .resource = pxa27x_resource_pwm1,
> - .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
> -};
> -#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
> -
> -#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
> -const struct software_node pxa2xx_gpiochip_node = {
> - .name = "gpio-pxa",
> -};
> -
> -struct resource pxa_resource_gpio[] = {
> - {
> - .start = 0x40e00000,
> - .end = 0x40e0ffff,
> - .flags = IORESOURCE_MEM,
> - }, {
> - .start = IRQ_GPIO0,
> - .end = IRQ_GPIO0,
> - .name = "gpio0",
> - .flags = IORESOURCE_IRQ,
> - }, {
> - .start = IRQ_GPIO1,
> - .end = IRQ_GPIO1,
> - .name = "gpio1",
> - .flags = IORESOURCE_IRQ,
> - }, {
> - .start = IRQ_GPIO_2_x,
> - .end = IRQ_GPIO_2_x,
> - .name = "gpio_mux",
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -static struct pxa_gpio_platform_data pxa2xx_gpio_info = {
> - .irq_base = PXA_GPIO_TO_IRQ(0),
> - .gpio_set_wake = gpio_set_wake,
> -};
> -
> -struct platform_device pxa25x_device_gpio = {
> - .name = "pxa25x-gpio",
> - .id = -1,
> - .num_resources = ARRAY_SIZE(pxa_resource_gpio),
> - .resource = pxa_resource_gpio,
> - .dev = {
> - .platform_data = &pxa2xx_gpio_info,
> - },
> -};
> -
> -struct platform_device pxa27x_device_gpio = {
> - .name = "pxa27x-gpio",
> - .id = -1,
> - .num_resources = ARRAY_SIZE(pxa_resource_gpio),
> - .resource = pxa_resource_gpio,
> - .dev = {
> - .platform_data = &pxa2xx_gpio_info,
> - },
> -};
> -#endif /* CONFIG_PXA25x || CONFIG_PXA27x */
> -
> -static struct resource pxa_dma_resource[] = {
> - [0] = {
> - .start = 0x40000000,
> - .end = 0x4000ffff,
> - .flags = IORESOURCE_MEM,
> - },
> - [1] = {
> - .start = IRQ_DMA,
> - .end = IRQ_DMA,
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -static u64 pxadma_dmamask = 0xffffffffUL;
> -
> -static struct platform_device pxa2xx_pxa_dma = {
> - .name = "pxa-dma",
> - .id = 0,
> - .dev = {
> - .dma_mask = &pxadma_dmamask,
> - .coherent_dma_mask = 0xffffffff,
> - },
> - .num_resources = ARRAY_SIZE(pxa_dma_resource),
> - .resource = pxa_dma_resource,
> -};
> -
> -void __init pxa2xx_set_dmac_info(struct mmp_dma_platdata *dma_pdata)
> -{
> - pxa_register_device(&pxa2xx_pxa_dma, dma_pdata);
> -}
>
> void __init pxa_register_wdt(unsigned int reset_status)
> {
> diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
> deleted file mode 100644
> index 72c556ff67db..000000000000
> --- a/arch/arm/mach-pxa/devices.h
> +++ /dev/null
> @@ -1,68 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -#define PDMA_FILTER_PARAM(_prio, _requestor) (&(struct pxad_param) { \
> - .prio = PXAD_PRIO_##_prio, .drcmr = _requestor })
> -struct mmp_dma_platdata;
> -
> -extern struct platform_device pxa_device_pmu;
> -extern struct platform_device pxa3xx_device_mci2;
> -extern struct platform_device pxa3xx_device_mci3;
> -extern struct platform_device pxa25x_device_udc;
> -extern struct platform_device pxa27x_device_udc;
> -extern struct platform_device pxa_device_fb;
> -extern struct platform_device pxa_device_ffuart;
> -extern struct platform_device pxa_device_btuart;
> -extern struct platform_device pxa_device_stuart;
> -extern struct platform_device pxa_device_hwuart;
> -extern struct platform_device pxa_device_i2c;
> -extern struct platform_device pxa_device_i2s;
> -extern struct platform_device sa1100_device_rtc;
> -extern struct platform_device pxa_device_rtc;
> -extern struct platform_device pxa_device_ac97;
> -
> -extern struct platform_device pxa27x_device_i2c_power;
> -extern struct platform_device pxa27x_device_ohci;
> -extern struct platform_device pxa27x_device_keypad;
> -
> -extern struct platform_device pxa25x_device_ssp;
> -extern struct platform_device pxa25x_device_nssp;
> -extern struct platform_device pxa25x_device_assp;
> -extern struct platform_device pxa27x_device_ssp1;
> -extern struct platform_device pxa27x_device_ssp2;
> -extern struct platform_device pxa27x_device_ssp3;
> -extern struct platform_device pxa3xx_device_ssp1;
> -extern struct platform_device pxa3xx_device_ssp2;
> -extern struct platform_device pxa3xx_device_ssp3;
> -extern struct platform_device pxa3xx_device_ssp4;
> -
> -extern struct platform_device pxa25x_device_pwm0;
> -extern struct platform_device pxa25x_device_pwm1;
> -extern struct platform_device pxa27x_device_pwm0;
> -extern struct platform_device pxa27x_device_pwm1;
> -
> -extern struct platform_device pxa3xx_device_nand;
> -extern struct platform_device pxa3xx_device_i2c_power;
> -
> -extern struct platform_device pxa3xx_device_gcu;
> -
> -extern struct platform_device pxa_device_asoc_platform;
> -extern struct platform_device pxa_device_asoc_ssp1;
> -extern struct platform_device pxa_device_asoc_ssp2;
> -extern struct platform_device pxa_device_asoc_ssp3;
> -extern struct platform_device pxa_device_asoc_ssp4;
> -
> -extern struct platform_device pxa25x_device_gpio;
> -extern struct platform_device pxa27x_device_gpio;
> -
> -extern const struct software_node pxa2xx_gpiochip_node;
> -
> -void __init pxa_register_device(struct platform_device *dev, void *data);
> -void __init pxa2xx_set_dmac_info(struct mmp_dma_platdata *dma_pdata);
> -
> -struct i2c_pxa_platform_data;
> -extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
> -#ifdef CONFIG_PXA27x
> -extern void pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info);
> -#endif
> -#ifdef CONFIG_PXA3xx
> -extern void pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info);
> -#endif
> diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
> index caad4fca8de3..239d1b4119cc 100644
> --- a/arch/arm/mach-pxa/generic.h
> +++ b/arch/arm/mach-pxa/generic.h
> @@ -38,11 +38,6 @@ extern struct syscore pxa_irq_syscore;
> extern struct syscore pxa2xx_mfp_syscore;
> extern struct syscore pxa3xx_mfp_syscore;
>
> -void __init pxa_set_ffuart_info(void *info);
> -void __init pxa_set_btuart_info(void *info);
> -void __init pxa_set_stuart_info(void *info);
> -void __init pxa_set_hwuart_info(void *info);
> -
> void pxa_restart(enum reboot_mode, const char *);
>
> #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
> diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
> deleted file mode 100644
> index 7ab0cb015d1b..000000000000
> --- a/arch/arm/mach-pxa/gumstix.c
> +++ /dev/null
> @@ -1,237 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * linux/arch/arm/mach-pxa/gumstix.c
> - *
> - * Support for the Gumstix motherboards.
> - *
> - * Original Author: Craig Hughes
> - * Created: Feb 14, 2008
> - * Copyright: Craig Hughes
> - *
> - * Implemented based on lubbock.c by Nicolas Pitre and code from Craig
> - * Hughes
> - */
> -
> -#include <linux/module.h>
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/platform_device.h>
> -#include <linux/interrupt.h>
> -#include <linux/delay.h>
> -#include <linux/mtd/mtd.h>
> -#include <linux/mtd/partitions.h>
> -#include <linux/gpio/machine.h>
> -#include <linux/gpio/property.h>
> -#include <linux/gpio/legacy.h>
> -#include <linux/err.h>
> -#include <linux/clk.h>
> -
> -#include <asm/setup.h>
> -#include <asm/page.h>
> -#include <asm/mach-types.h>
> -#include <asm/irq.h>
> -#include <linux/sizes.h>
> -
> -#include <asm/mach/arch.h>
> -#include <asm/mach/map.h>
> -#include <asm/mach/irq.h>
> -#include <asm/mach/flash.h>
> -
> -#include "pxa25x.h"
> -#include <linux/platform_data/mmc-pxamci.h>
> -#include "gumstix.h"
> -#include "devices.h"
> -
> -#include "generic.h"
> -
> -static struct resource flash_resource = {
> - .start = 0x00000000,
> - .end = SZ_64M - 1,
> - .flags = IORESOURCE_MEM,
> -};
> -
> -static struct mtd_partition gumstix_partitions[] = {
> - {
> - .name = "Bootloader",
> - .size = 0x00040000,
> - .offset = 0,
> - .mask_flags = MTD_WRITEABLE /* force read-only */
> - } , {
> - .name = "rootfs",
> - .size = MTDPART_SIZ_FULL,
> - .offset = MTDPART_OFS_APPEND
> - }
> -};
> -
> -static struct flash_platform_data gumstix_flash_data = {
> - .map_name = "cfi_probe",
> - .parts = gumstix_partitions,
> - .nr_parts = ARRAY_SIZE(gumstix_partitions),
> - .width = 2,
> -};
> -
> -static struct platform_device gumstix_flash_device = {
> - .name = "pxa2xx-flash",
> - .id = 0,
> - .dev = {
> - .platform_data = &gumstix_flash_data,
> - },
> - .resource = &flash_resource,
> - .num_resources = 1,
> -};
> -
> -static struct platform_device *devices[] __initdata = {
> - &gumstix_flash_device,
> -};
> -
> -#ifdef CONFIG_MMC_PXA
> -static struct pxamci_platform_data gumstix_mci_platform_data = {
> - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
> -};
> -
> -static void __init gumstix_mmc_init(void)
> -{
> - pxa_set_mci_info(&gumstix_mci_platform_data, NULL);
> -}
> -#else
> -static void __init gumstix_mmc_init(void)
> -{
> - pr_debug("Gumstix mmc disabled\n");
> -}
> -#endif
> -
> -#if IS_ENABLED(CONFIG_USB_PXA25X)
> -static const struct property_entry gumstix_vbus_props[] __initconst = {
> - PROPERTY_ENTRY_GPIO("vbus-gpios", &pxa2xx_gpiochip_node,
> - GPIO_GUMSTIX_USB_GPIOn, GPIO_ACTIVE_HIGH),
> - PROPERTY_ENTRY_GPIO("pullup-gpios", &pxa2xx_gpiochip_node,
> - GPIO_GUMSTIX_USB_GPIOx, GPIO_ACTIVE_HIGH),
> - { }
> -};
> -
> -static const struct platform_device_info gumstix_gpio_vbus_info __initconst = {
> - .name = "gpio-vbus",
> - .id = PLATFORM_DEVID_NONE,
> - .properties = gumstix_vbus_props,
> -};
> -
> -static void __init gumstix_udc_init(void)
> -{
> - platform_device_register_full(&gumstix_gpio_vbus_info);
> -}
> -#else
> -static void gumstix_udc_init(void)
> -{
> - pr_debug("Gumstix udc is disabled\n");
> -}
> -#endif
> -
> -#ifdef CONFIG_BT
> -/* Normally, the bootloader would have enabled this 32kHz clock but many
> -** boards still have u-boot 1.1.4 so we check if it has been turned on and
> -** if not, we turn it on with a warning message. */
> -static void gumstix_setup_bt_clock(void)
> -{
> - int timeout = 500;
> -
> - if (!(readl(OSCC) & OSCC_OOK))
> - pr_warn("32kHz clock was not on. Bootloader may need to be updated\n");
> - else
> - return;
> -
> - writel(readl(OSCC) | OSCC_OON, OSCC);
> - do {
> - if (readl(OSCC) & OSCC_OOK)
> - break;
> - udelay(1);
> - } while (--timeout);
> - if (!timeout)
> - pr_err("Failed to start 32kHz clock\n");
> -}
> -
> -static void __init gumstix_bluetooth_init(void)
> -{
> - int err;
> -
> - gumstix_setup_bt_clock();
> -
> - err = gpio_request(GPIO_GUMSTIX_BTRESET, "BTRST");
> - if (err) {
> - pr_err("gumstix: failed request gpio for bluetooth reset\n");
> - return;
> - }
> -
> - err = gpio_direction_output(GPIO_GUMSTIX_BTRESET, 1);
> - if (err) {
> - pr_err("gumstix: can't reset bluetooth\n");
> - return;
> - }
> - gpio_set_value(GPIO_GUMSTIX_BTRESET, 0);
> - udelay(100);
> - gpio_set_value(GPIO_GUMSTIX_BTRESET, 1);
> -}
> -#else
> -static void gumstix_bluetooth_init(void)
> -{
> - pr_debug("Gumstix Bluetooth is disabled\n");
> -}
> -#endif
> -
> -static unsigned long gumstix_pin_config[] __initdata = {
> - GPIO12_32KHz,
> - /* BTUART */
> - GPIO42_HWUART_RXD,
> - GPIO43_HWUART_TXD,
> - GPIO44_HWUART_CTS,
> - GPIO45_HWUART_RTS,
> - /* MMC */
> - GPIO6_MMC_CLK,
> - GPIO53_MMC_CLK,
> - GPIO8_MMC_CS0,
> -};
> -
> -int __attribute__((weak)) am200_init(void)
> -{
> - return 0;
> -}
> -
> -int __attribute__((weak)) am300_init(void)
> -{
> - return 0;
> -}
> -
> -static void __init carrier_board_init(void)
> -{
> - /*
> - * put carrier/expansion board init here if
> - * they cannot be detected programatically
> - */
> - am200_init();
> - am300_init();
> -}
> -
> -static void __init gumstix_init(void)
> -{
> - pxa2xx_mfp_config(ARRAY_AND_SIZE(gumstix_pin_config));
> -
> - pxa_set_ffuart_info(NULL);
> - pxa_set_btuart_info(NULL);
> - pxa_set_stuart_info(NULL);
> - pxa_set_hwuart_info(NULL);
> -
> - gumstix_bluetooth_init();
> - gumstix_udc_init();
> - gumstix_mmc_init();
> - (void) platform_add_devices(devices, ARRAY_SIZE(devices));
> - carrier_board_init();
> -}
> -
> -MACHINE_START(GUMSTIX, "Gumstix")
> - .atag_offset = 0x100, /* match u-boot bi_boot_params */
> - .map_io = pxa25x_map_io,
> - .nr_irqs = PXA_NR_IRQS,
> - .init_irq = pxa25x_init_irq,
> - .init_time = pxa_timer_init,
> - .init_machine = gumstix_init,
> - .restart = pxa_restart,
> -MACHINE_END
> diff --git a/arch/arm/mach-pxa/gumstix.h b/arch/arm/mach-pxa/gumstix.h
> deleted file mode 100644
> index 9005b3c0aabd..000000000000
> --- a/arch/arm/mach-pxa/gumstix.h
> +++ /dev/null
> @@ -1,89 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * arch/arm/mach-pxa/include/mach/gumstix.h
> - */
> -
> -#include "irqs.h" /* PXA_GPIO_TO_IRQ */
> -
> -/* BTRESET - Reset line to Bluetooth module, active low signal. */
> -#define GPIO_GUMSTIX_BTRESET 7
> -#define GPIO_GUMSTIX_BTRESET_MD (GPIO_GUMSTIX_BTRESET | GPIO_OUT)
> -
> -
> -/*
> -GPIOn - Input from MAX823 (or equiv), normalizing USB +5V into a clean
> -interrupt signal for determining cable presence. On the gumstix F,
> -this moves to GPIO17 and GPIO37. */
> -
> -/* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn
> -has detected a cable insertion; driven low otherwise. */
> -
> -#define GPIO_GUMSTIX_USB_GPIOn 35
> -#define GPIO_GUMSTIX_USB_GPIOx 41
> -
> -/* usb state change */
> -#define GUMSTIX_USB_INTR_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_USB_GPIOn)
> -
> -#define GPIO_GUMSTIX_USB_GPIOn_MD (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN)
> -#define GPIO_GUMSTIX_USB_GPIOx_CON_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT)
> -#define GPIO_GUMSTIX_USB_GPIOx_DIS_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_IN)
> -
> -/*
> - * SD/MMC definitions
> - */
> -#define GUMSTIX_GPIO_nSD_WP 22 /* SD Write Protect */
> -#define GUMSTIX_GPIO_nSD_DETECT 11 /* MMC/SD Card Detect */
> -#define GUMSTIX_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(GUMSTIX_GPIO_nSD_DETECT)
> -
> -/*
> - * SMC Ethernet definitions
> - * ETH_RST provides a hardware reset line to the ethernet chip
> - * ETH is the IRQ line in from the ethernet chip to the PXA
> - */
> -#define GPIO_GUMSTIX_ETH0_RST 80
> -#define GPIO_GUMSTIX_ETH0_RST_MD (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT)
> -#define GPIO_GUMSTIX_ETH1_RST 52
> -#define GPIO_GUMSTIX_ETH1_RST_MD (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT)
> -
> -#define GPIO_GUMSTIX_ETH0 36
> -#define GPIO_GUMSTIX_ETH0_MD (GPIO_GUMSTIX_ETH0 | GPIO_IN)
> -#define GUMSTIX_ETH0_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0)
> -#define GPIO_GUMSTIX_ETH1 27
> -#define GPIO_GUMSTIX_ETH1_MD (GPIO_GUMSTIX_ETH1 | GPIO_IN)
> -#define GUMSTIX_ETH1_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH1)
> -
> -
> -/* CF reset line */
> -#define GPIO8_RESET 8
> -
> -/* CF slot 0 */
> -#define GPIO4_nBVD1 4
> -#define GPIO4_nSTSCHG GPIO4_nBVD1
> -#define GPIO11_nCD 11
> -#define GPIO26_PRDY_nBSY 26
> -#define GUMSTIX_S0_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO4_nSTSCHG)
> -#define GUMSTIX_S0_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO11_nCD)
> -#define GUMSTIX_S0_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO26_PRDY_nBSY)
> -
> -/* CF slot 1 */
> -#define GPIO18_nBVD1 18
> -#define GPIO18_nSTSCHG GPIO18_nBVD1
> -#define GPIO36_nCD 36
> -#define GPIO27_PRDY_nBSY 27
> -#define GUMSTIX_S1_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO18_nSTSCHG)
> -#define GUMSTIX_S1_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO36_nCD)
> -#define GUMSTIX_S1_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO27_PRDY_nBSY)
> -
> -/* CF GPIO line modes */
> -#define GPIO4_nSTSCHG_MD (GPIO4_nSTSCHG | GPIO_IN)
> -#define GPIO8_RESET_MD (GPIO8_RESET | GPIO_OUT)
> -#define GPIO11_nCD_MD (GPIO11_nCD | GPIO_IN)
> -#define GPIO18_nSTSCHG_MD (GPIO18_nSTSCHG | GPIO_IN)
> -#define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN)
> -#define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN)
> -#define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN)
> -
> -/* for expansion boards that can't be programatically detected */
> -extern int am200_init(void);
> -extern int am300_init(void);
> -
> diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
> index a273f0af095e..de6a306cf0e2 100644
> --- a/arch/arm/mach-pxa/pxa25x.c
> +++ b/arch/arm/mach-pxa/pxa25x.c
> @@ -25,7 +25,6 @@
> #include <linux/syscore_ops.h>
> #include <linux/irq.h>
> #include <linux/irqchip.h>
> -#include <linux/platform_data/mmp_dma.h>
> #include <linux/soc/pxa/cpu.h>
> #include <linux/soc/pxa/smemc.h>
>
> @@ -39,7 +38,6 @@
> #include "smemc.h"
>
> #include "generic.h"
> -#include "devices.h"
>
> /*
> * Various clock factors driven by the CCCR register.
> @@ -178,53 +176,6 @@ void __init pxa25x_map_io(void)
> pxa25x_get_clk_frequency_khz(1);
> }
>
> -static struct platform_device *pxa25x_devices[] __initdata = {
> - &pxa25x_device_gpio,
> - &pxa25x_device_udc,
> - &pxa_device_pmu,
> - &pxa_device_i2s,
> - &sa1100_device_rtc,
> - &pxa25x_device_ssp,
> - &pxa25x_device_nssp,
> - &pxa25x_device_assp,
> - &pxa25x_device_pwm0,
> - &pxa25x_device_pwm1,
> - &pxa_device_asoc_platform,
> -};
> -
> -static const struct dma_slave_map pxa25x_slave_map[] = {
> - /* PXA25x, PXA27x and PXA3xx common entries */
> - { "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) },
> - { "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) },
> - { "pxa2xx-ac97", "pcm_pcm_aux_mono_out",
> - PDMA_FILTER_PARAM(LOWEST, 10) },
> - { "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) },
> - { "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) },
> - { "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
> - { "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
> - { "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
> - { "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
> - { "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) },
> - { "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) },
> - { "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) },
> - { "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) },
> -
> - /* PXA25x specific map */
> - { "pxa25x-ssp.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
> - { "pxa25x-ssp.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
> - { "pxa25x-nssp.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
> - { "pxa25x-nssp.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
> - { "pxa25x-nssp.2", "rx", PDMA_FILTER_PARAM(LOWEST, 23) },
> - { "pxa25x-nssp.2", "tx", PDMA_FILTER_PARAM(LOWEST, 24) },
> -};
> -
> -static struct mmp_dma_platdata pxa25x_dma_pdata = {
> - .dma_channels = 16,
> - .nb_requestors = 40,
> - .slave_map = pxa25x_slave_map,
> - .slave_map_cnt = ARRAY_SIZE(pxa25x_slave_map),
> -};
> -
> static int __init pxa25x_init(void)
> {
> int ret = 0;
> @@ -237,16 +188,6 @@ static int __init pxa25x_init(void)
>
> register_syscore(&pxa_irq_syscore);
> register_syscore(&pxa2xx_mfp_syscore);
> -
> - if (!of_have_populated_dt()) {
> - software_node_register(&pxa2xx_gpiochip_node);
> - pxa25x_device_gpio.dev.fwnode = software_node_fwnode(
> - &pxa2xx_gpiochip_node);
> -
> - pxa2xx_set_dmac_info(&pxa25x_dma_pdata);
> - ret = platform_add_devices(pxa25x_devices,
> - ARRAY_SIZE(pxa25x_devices));
> - }
> }
>
> return ret;
> diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
> index 814e0a12f38a..617af225628b 100644
> --- a/arch/arm/mach-pxa/pxa27x.c
> +++ b/arch/arm/mach-pxa/pxa27x.c
> @@ -21,8 +21,6 @@
> #include <linux/syscore_ops.h>
> #include <linux/io.h>
> #include <linux/irq.h>
> -#include <linux/platform_data/i2c-pxa.h>
> -#include <linux/platform_data/mmp_dma.h>
> #include <linux/soc/pxa/cpu.h>
> #include <linux/soc/pxa/smemc.h>
>
> @@ -33,14 +31,12 @@
> #include "pxa27x.h"
> #include "reset.h"
> #include <linux/platform_data/pxa2xx_udc.h>
> -#include <linux/platform_data/usb-ohci-pxa27x.h>
> #include <linux/platform_data/asoc-pxa.h>
> #include "pm.h"
> #include "addr-map.h"
> #include "smemc.h"
>
> #include "generic.h"
> -#include "devices.h"
> #include <linux/clk-provider.h>
> #include <linux/clkdev.h>
>
> @@ -272,90 +268,17 @@ void __init pxa27x_map_io(void)
> pxa27x_get_clk_frequency_khz(1);
> }
>
> -/*
> - * device registration specific to PXA27x.
> - */
> -void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
> -{
> - local_irq_disable();
> - PCFR |= PCFR_PI2CEN;
> - local_irq_enable();
> - pxa_register_device(&pxa27x_device_i2c_power, info);
> -}
> -
> -static struct platform_device *devices[] __initdata = {
> - &pxa27x_device_gpio,
> - &pxa27x_device_udc,
> - &pxa_device_pmu,
> - &pxa_device_i2s,
> - &pxa_device_asoc_ssp1,
> - &pxa_device_asoc_ssp2,
> - &pxa_device_asoc_ssp3,
> - &pxa_device_asoc_platform,
> - &pxa_device_rtc,
> - &pxa27x_device_ssp1,
> - &pxa27x_device_ssp2,
> - &pxa27x_device_ssp3,
> - &pxa27x_device_pwm0,
> - &pxa27x_device_pwm1,
> -};
> -
> -static const struct dma_slave_map pxa27x_slave_map[] = {
> - /* PXA25x, PXA27x and PXA3xx common entries */
> - { "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) },
> - { "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) },
> - { "pxa2xx-ac97", "pcm_pcm_aux_mono_out",
> - PDMA_FILTER_PARAM(LOWEST, 10) },
> - { "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) },
> - { "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) },
> - { "pxa-ssp-dai.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
> - { "pxa-ssp-dai.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
> - { "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
> - { "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
> - { "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) },
> - { "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) },
> - { "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) },
> - { "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) },
> - { "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 66) },
> - { "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 67) },
> -
> - /* PXA27x specific map */
> - { "pxa2xx-i2s", "rx", PDMA_FILTER_PARAM(LOWEST, 2) },
> - { "pxa2xx-i2s", "tx", PDMA_FILTER_PARAM(LOWEST, 3) },
> - { "pxa27x-camera.0", "CI_Y", PDMA_FILTER_PARAM(HIGHEST, 68) },
> - { "pxa27x-camera.0", "CI_U", PDMA_FILTER_PARAM(HIGHEST, 69) },
> - { "pxa27x-camera.0", "CI_V", PDMA_FILTER_PARAM(HIGHEST, 70) },
> -};
> -
> -static struct mmp_dma_platdata pxa27x_dma_pdata = {
> - .dma_channels = 32,
> - .nb_requestors = 75,
> - .slave_map = pxa27x_slave_map,
> - .slave_map_cnt = ARRAY_SIZE(pxa27x_slave_map),
> -};
> -
> static int __init pxa27x_init(void)
> {
> int ret = 0;
>
> if (cpu_is_pxa27x()) {
> -
> pxa_register_wdt(RCSR);
>
> pxa27x_init_pm();
>
> register_syscore(&pxa_irq_syscore);
> register_syscore(&pxa2xx_mfp_syscore);
> -
> - if (!of_have_populated_dt()) {
> - software_node_register(&pxa2xx_gpiochip_node);
> - pxa27x_device_gpio.dev.fwnode = software_node_fwnode(
> - &pxa2xx_gpiochip_node);
> -
> - pxa2xx_set_dmac_info(&pxa27x_dma_pdata);
> - ret = platform_add_devices(devices,
> - ARRAY_SIZE(devices));
> - }
> }
>
> return ret;
> diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
> index f77ec118d5b9..0022bf235114 100644
> --- a/arch/arm/mach-pxa/pxa300.c
> +++ b/arch/arm/mach-pxa/pxa300.c
> @@ -19,7 +19,6 @@
> #include "pxa300.h"
>
> #include "generic.h"
> -#include "devices.h"
>
> static struct mfp_addr_map pxa300_mfp_addr_map[] __initdata = {
>
> diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
> index e372e6c118de..2e84afd94467 100644
> --- a/arch/arm/mach-pxa/pxa320.c
> +++ b/arch/arm/mach-pxa/pxa320.c
> @@ -19,7 +19,6 @@
> #include "pxa320.h"
>
> #include "generic.h"
> -#include "devices.h"
>
> static struct mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
>
> diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
> index 06c578ea658e..46f4efdfb514 100644
> --- a/arch/arm/mach-pxa/pxa3xx.c
> +++ b/arch/arm/mach-pxa/pxa3xx.c
> @@ -10,11 +10,9 @@
> * initial version
> */
> #include <linux/dmaengine.h>
> -#include <linux/dma/pxa-dma.h>
> #include <linux/module.h>
> #include <linux/kernel.h>
> #include <linux/init.h>
> -#include <linux/gpio-pxa.h>
> #include <linux/pm.h>
> #include <linux/platform_device.h>
> #include <linux/irq.h>
> @@ -22,8 +20,6 @@
> #include <linux/io.h>
> #include <linux/of.h>
> #include <linux/syscore_ops.h>
> -#include <linux/platform_data/i2c-pxa.h>
> -#include <linux/platform_data/mmp_dma.h>
> #include <linux/soc/pxa/cpu.h>
> #include <linux/clk/pxa.h>
>
> @@ -31,14 +27,12 @@
> #include <asm/suspend.h>
> #include "pxa3xx-regs.h"
> #include "reset.h"
> -#include <linux/platform_data/usb-ohci-pxa27x.h>
> #include "pm.h"
> #include "addr-map.h"
> #include "smemc.h"
> #include "irqs.h"
>
> #include "generic.h"
> -#include "devices.h"
>
> #define PECR_IE(n) ((1 << ((n) * 2)) << 28)
> #define PECR_IS(n) ((1 << ((n) * 2)) << 29)
> diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
> deleted file mode 100644
> index a611eea70e5a..000000000000
> --- a/arch/arm/mach-pxa/sharpsl_pm.c
> +++ /dev/null
> @@ -1,941 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Battery and Power Management code for the Sharp SL-C7xx and SL-Cxx00
> - * series of PDAs
> - *
> - * Copyright (c) 2004-2005 Richard Purdie
> - *
> - * Based on code written by Sharp for 2.4 kernels
> - */
> -
> -#undef DEBUG
> -
> -#include <linux/module.h>
> -#include <linux/kernel.h>
> -#include <linux/interrupt.h>
> -#include <linux/platform_device.h>
> -#include <linux/apm-emulation.h>
> -#include <linux/timer.h>
> -#include <linux/delay.h>
> -#include <linux/leds.h>
> -#include <linux/suspend.h>
> -#include <linux/gpio/legacy.h>
> -#include <linux/io.h>
> -
> -#include <asm/mach-types.h>
> -#include "pm.h"
> -#include "pxa2xx-regs.h"
> -#include "regs-rtc.h"
> -#include "sharpsl_pm.h"
> -
> -/*
> - * Constants
> - */
> -#define SHARPSL_CHARGE_ON_TIME_INTERVAL (secs_to_jiffies(60))
> -#define SHARPSL_CHARGE_FINISH_TIME (secs_to_jiffies(10*60))
> -#define SHARPSL_BATCHK_TIME (secs_to_jiffies(15))
> -#define SHARPSL_BATCHK_TIME_SUSPEND (60*10) /* 10 min */
> -
> -#define SHARPSL_WAIT_CO_TIME 15 /* 15 sec */
> -#define SHARPSL_WAIT_DISCHARGE_ON 100 /* 100 msec */
> -#define SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP 10 /* 10 msec */
> -#define SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT 10 /* 10 msec */
> -#define SHARPSL_CHECK_BATTERY_WAIT_TIME_ACIN 10 /* 10 msec */
> -#define SHARPSL_CHARGE_WAIT_TIME 15 /* 15 msec */
> -#define SHARPSL_CHARGE_CO_CHECK_TIME 5 /* 5 msec */
> -#define SHARPSL_CHARGE_RETRY_CNT 1 /* eqv. 10 min */
> -
> -/*
> - * Prototypes
> - */
> -#ifdef CONFIG_PM
> -static int sharpsl_off_charge_battery(void);
> -static int sharpsl_check_battery_voltage(void);
> -#endif
> -static int sharpsl_check_battery_temp(void);
> -static int sharpsl_ac_check(void);
> -static int sharpsl_average_value(int ad);
> -static void sharpsl_average_clear(void);
> -static void sharpsl_charge_toggle(struct work_struct *private_);
> -static void sharpsl_battery_thread(struct work_struct *private_);
> -
> -
> -/*
> - * Variables
> - */
> -struct sharpsl_pm_status sharpsl_pm;
> -static DECLARE_DELAYED_WORK(toggle_charger, sharpsl_charge_toggle);
> -static DECLARE_DELAYED_WORK(sharpsl_bat, sharpsl_battery_thread);
> -DEFINE_LED_TRIGGER(sharpsl_charge_led_trigger);
> -
> -
> -
> -struct battery_thresh sharpsl_battery_levels_acin[] = {
> - { 213, 100},
> - { 212, 98},
> - { 211, 95},
> - { 210, 93},
> - { 209, 90},
> - { 208, 88},
> - { 207, 85},
> - { 206, 83},
> - { 205, 80},
> - { 204, 78},
> - { 203, 75},
> - { 202, 73},
> - { 201, 70},
> - { 200, 68},
> - { 199, 65},
> - { 198, 63},
> - { 197, 60},
> - { 196, 58},
> - { 195, 55},
> - { 194, 53},
> - { 193, 50},
> - { 192, 48},
> - { 192, 45},
> - { 191, 43},
> - { 191, 40},
> - { 190, 38},
> - { 190, 35},
> - { 189, 33},
> - { 188, 30},
> - { 187, 28},
> - { 186, 25},
> - { 185, 23},
> - { 184, 20},
> - { 183, 18},
> - { 182, 15},
> - { 181, 13},
> - { 180, 10},
> - { 179, 8},
> - { 178, 5},
> - { 0, 0},
> -};
> -
> -struct battery_thresh sharpsl_battery_levels_noac[] = {
> - { 213, 100},
> - { 212, 98},
> - { 211, 95},
> - { 210, 93},
> - { 209, 90},
> - { 208, 88},
> - { 207, 85},
> - { 206, 83},
> - { 205, 80},
> - { 204, 78},
> - { 203, 75},
> - { 202, 73},
> - { 201, 70},
> - { 200, 68},
> - { 199, 65},
> - { 198, 63},
> - { 197, 60},
> - { 196, 58},
> - { 195, 55},
> - { 194, 53},
> - { 193, 50},
> - { 192, 48},
> - { 191, 45},
> - { 190, 43},
> - { 189, 40},
> - { 188, 38},
> - { 187, 35},
> - { 186, 33},
> - { 185, 30},
> - { 184, 28},
> - { 183, 25},
> - { 182, 23},
> - { 181, 20},
> - { 180, 18},
> - { 179, 15},
> - { 178, 13},
> - { 177, 10},
> - { 176, 8},
> - { 175, 5},
> - { 0, 0},
> -};
> -
> -/* MAX1111 Commands */
> -#define MAXCTRL_PD0 (1u << 0)
> -#define MAXCTRL_PD1 (1u << 1)
> -#define MAXCTRL_SGL (1u << 2)
> -#define MAXCTRL_UNI (1u << 3)
> -#define MAXCTRL_SEL_SH 4
> -#define MAXCTRL_STR (1u << 7)
> -
> -extern int max1111_read_channel(int);
> -/*
> - * Read MAX1111 ADC
> - */
> -int sharpsl_pm_pxa_read_max1111(int channel)
> -{
> - /* max1111 accepts channels from 0-3, however,
> - * it is encoded from 0-7 here in the code.
> - */
> - return max1111_read_channel(channel >> 1);
> -}
> -
> -static int get_percentage(int voltage)
> -{
> - int i = sharpsl_pm.machinfo->bat_levels - 1;
> - int bl_status = sharpsl_pm.machinfo->backlight_get_status ? sharpsl_pm.machinfo->backlight_get_status() : 0;
> - struct battery_thresh *thresh;
> -
> - if (sharpsl_pm.charge_mode == CHRG_ON)
> - thresh = bl_status ? sharpsl_pm.machinfo->bat_levels_acin_bl : sharpsl_pm.machinfo->bat_levels_acin;
> - else
> - thresh = bl_status ? sharpsl_pm.machinfo->bat_levels_noac_bl : sharpsl_pm.machinfo->bat_levels_noac;
> -
> - while (i > 0 && (voltage > thresh[i].voltage))
> - i--;
> -
> - return thresh[i].percentage;
> -}
> -
> -static int get_apm_status(int voltage)
> -{
> - int low_thresh, high_thresh;
> -
> - if (sharpsl_pm.charge_mode == CHRG_ON) {
> - high_thresh = sharpsl_pm.machinfo->status_high_acin;
> - low_thresh = sharpsl_pm.machinfo->status_low_acin;
> - } else {
> - high_thresh = sharpsl_pm.machinfo->status_high_noac;
> - low_thresh = sharpsl_pm.machinfo->status_low_noac;
> - }
> -
> - if (voltage >= high_thresh)
> - return APM_BATTERY_STATUS_HIGH;
> - if (voltage >= low_thresh)
> - return APM_BATTERY_STATUS_LOW;
> - return APM_BATTERY_STATUS_CRITICAL;
> -}
> -
> -void sharpsl_battery_kick(void)
> -{
> - schedule_delayed_work(&sharpsl_bat, msecs_to_jiffies(125));
> -}
> -
> -static void sharpsl_battery_thread(struct work_struct *private_)
> -{
> - int voltage, percent, apm_status, i;
> -
> - if (!sharpsl_pm.machinfo)
> - return;
> -
> - sharpsl_pm.battstat.ac_status = (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN) ? APM_AC_ONLINE : APM_AC_OFFLINE);
> -
> - /* Corgi cannot confirm when battery fully charged so periodically kick! */
> - if (!sharpsl_pm.machinfo->batfull_irq && (sharpsl_pm.charge_mode == CHRG_ON)
> - && time_after(jiffies, sharpsl_pm.charge_start_time + SHARPSL_CHARGE_ON_TIME_INTERVAL))
> - schedule_delayed_work(&toggle_charger, 0);
> -
> - for (i = 0; i < 5; i++) {
> - voltage = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT);
> - if (voltage > 0)
> - break;
> - }
> - if (voltage <= 0) {
> - voltage = sharpsl_pm.machinfo->bat_levels_noac[0].voltage;
> - dev_warn(sharpsl_pm.dev, "Warning: Cannot read main battery!\n");
> - }
> -
> - voltage = sharpsl_average_value(voltage);
> - apm_status = get_apm_status(voltage);
> - percent = get_percentage(voltage);
> -
> - /* At low battery voltages, the voltage has a tendency to start
> - creeping back up so we try to avoid this here */
> - if ((sharpsl_pm.battstat.ac_status == APM_AC_ONLINE)
> - || (apm_status == APM_BATTERY_STATUS_HIGH)
> - || percent <= sharpsl_pm.battstat.mainbat_percent) {
> - sharpsl_pm.battstat.mainbat_voltage = voltage;
> - sharpsl_pm.battstat.mainbat_status = apm_status;
> - sharpsl_pm.battstat.mainbat_percent = percent;
> - }
> -
> - dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage,
> - sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies);
> -
> - /* Suspend if critical battery level */
> - if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
> - && (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL)
> - && !(sharpsl_pm.flags & SHARPSL_APM_QUEUED)) {
> - sharpsl_pm.flags |= SHARPSL_APM_QUEUED;
> - dev_err(sharpsl_pm.dev, "Fatal Off\n");
> - apm_queue_event(APM_CRITICAL_SUSPEND);
> - }
> -
> - schedule_delayed_work(&sharpsl_bat, SHARPSL_BATCHK_TIME);
> -}
> -
> -void sharpsl_pm_led(int val)
> -{
> - if (val == SHARPSL_LED_ERROR) {
> - dev_err(sharpsl_pm.dev, "Charging Error!\n");
> - } else if (val == SHARPSL_LED_ON) {
> - dev_dbg(sharpsl_pm.dev, "Charge LED On\n");
> - led_trigger_event(sharpsl_charge_led_trigger, LED_FULL);
> - } else {
> - dev_dbg(sharpsl_pm.dev, "Charge LED Off\n");
> - led_trigger_event(sharpsl_charge_led_trigger, LED_OFF);
> - }
> -}
> -
> -static void sharpsl_charge_on(void)
> -{
> - dev_dbg(sharpsl_pm.dev, "Turning Charger On\n");
> -
> - sharpsl_pm.full_count = 0;
> - sharpsl_pm.charge_mode = CHRG_ON;
> - schedule_delayed_work(&toggle_charger, msecs_to_jiffies(250));
> - schedule_delayed_work(&sharpsl_bat, msecs_to_jiffies(500));
> -}
> -
> -static void sharpsl_charge_off(void)
> -{
> - dev_dbg(sharpsl_pm.dev, "Turning Charger Off\n");
> -
> - sharpsl_pm.machinfo->charge(0);
> - sharpsl_pm_led(SHARPSL_LED_OFF);
> - sharpsl_pm.charge_mode = CHRG_OFF;
> -
> - schedule_delayed_work(&sharpsl_bat, 0);
> -}
> -
> -static void sharpsl_charge_error(void)
> -{
> - sharpsl_pm_led(SHARPSL_LED_ERROR);
> - sharpsl_pm.machinfo->charge(0);
> - sharpsl_pm.charge_mode = CHRG_ERROR;
> -}
> -
> -static void sharpsl_charge_toggle(struct work_struct *private_)
> -{
> - dev_dbg(sharpsl_pm.dev, "Toggling Charger at time: %lx\n", jiffies);
> -
> - if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN)) {
> - sharpsl_charge_off();
> - return;
> - } else if ((sharpsl_check_battery_temp() < 0) || (sharpsl_ac_check() < 0)) {
> - sharpsl_charge_error();
> - return;
> - }
> -
> - sharpsl_pm_led(SHARPSL_LED_ON);
> - sharpsl_pm.machinfo->charge(0);
> - mdelay(SHARPSL_CHARGE_WAIT_TIME);
> - sharpsl_pm.machinfo->charge(1);
> -
> - sharpsl_pm.charge_start_time = jiffies;
> -}
> -
> -static void sharpsl_ac_timer(struct timer_list *unused)
> -{
> - int acin = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN);
> -
> - dev_dbg(sharpsl_pm.dev, "AC Status: %d\n", acin);
> -
> - sharpsl_average_clear();
> - if (acin && (sharpsl_pm.charge_mode != CHRG_ON))
> - sharpsl_charge_on();
> - else if (sharpsl_pm.charge_mode == CHRG_ON)
> - sharpsl_charge_off();
> -
> - schedule_delayed_work(&sharpsl_bat, 0);
> -}
> -
> -
> -static irqreturn_t sharpsl_ac_isr(int irq, void *dev_id)
> -{
> - /* Delay the event slightly to debounce */
> - /* Must be a smaller delay than the chrg_full_isr below */
> - mod_timer(&sharpsl_pm.ac_timer, jiffies + msecs_to_jiffies(250));
> -
> - return IRQ_HANDLED;
> -}
> -
> -static void sharpsl_chrg_full_timer(struct timer_list *unused)
> -{
> - dev_dbg(sharpsl_pm.dev, "Charge Full at time: %lx\n", jiffies);
> -
> - sharpsl_pm.full_count++;
> -
> - if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN)) {
> - dev_dbg(sharpsl_pm.dev, "Charge Full: AC removed - stop charging!\n");
> - if (sharpsl_pm.charge_mode == CHRG_ON)
> - sharpsl_charge_off();
> - } else if (sharpsl_pm.full_count < 2) {
> - dev_dbg(sharpsl_pm.dev, "Charge Full: Count too low\n");
> - schedule_delayed_work(&toggle_charger, 0);
> - } else if (time_after(jiffies, sharpsl_pm.charge_start_time + SHARPSL_CHARGE_FINISH_TIME)) {
> - dev_dbg(sharpsl_pm.dev, "Charge Full: Interrupt generated too slowly - retry.\n");
> - schedule_delayed_work(&toggle_charger, 0);
> - } else {
> - sharpsl_charge_off();
> - sharpsl_pm.charge_mode = CHRG_DONE;
> - dev_dbg(sharpsl_pm.dev, "Charge Full: Charging Finished\n");
> - }
> -}
> -
> -/* Charging Finished Interrupt (Not present on Corgi) */
> -/* Can trigger at the same time as an AC status change so
> - delay until after that has been processed */
> -static irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id)
> -{
> - if (sharpsl_pm.flags & SHARPSL_SUSPENDED)
> - return IRQ_HANDLED;
> -
> - /* delay until after any ac interrupt */
> - mod_timer(&sharpsl_pm.chrg_full_timer, jiffies + msecs_to_jiffies(500));
> -
> - return IRQ_HANDLED;
> -}
> -
> -static irqreturn_t sharpsl_fatal_isr(int irq, void *dev_id)
> -{
> - int is_fatal = 0;
> -
> - if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_LOCK)) {
> - dev_err(sharpsl_pm.dev, "Battery now Unlocked! Suspending.\n");
> - is_fatal = 1;
> - }
> -
> - if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_FATAL)) {
> - dev_err(sharpsl_pm.dev, "Fatal Batt Error! Suspending.\n");
> - is_fatal = 1;
> - }
> -
> - if (!(sharpsl_pm.flags & SHARPSL_APM_QUEUED) && is_fatal) {
> - sharpsl_pm.flags |= SHARPSL_APM_QUEUED;
> - apm_queue_event(APM_CRITICAL_SUSPEND);
> - }
> -
> - return IRQ_HANDLED;
> -}
> -
> -/*
> - * Maintain an average of the last 10 readings
> - */
> -#define SHARPSL_CNV_VALUE_NUM 10
> -static int sharpsl_ad_index;
> -
> -static void sharpsl_average_clear(void)
> -{
> - sharpsl_ad_index = 0;
> -}
> -
> -static int sharpsl_average_value(int ad)
> -{
> - int i, ad_val = 0;
> - static int sharpsl_ad[SHARPSL_CNV_VALUE_NUM+1];
> -
> - if (sharpsl_pm.battstat.mainbat_status != APM_BATTERY_STATUS_HIGH) {
> - sharpsl_ad_index = 0;
> - return ad;
> - }
> -
> - sharpsl_ad[sharpsl_ad_index] = ad;
> - sharpsl_ad_index++;
> - if (sharpsl_ad_index >= SHARPSL_CNV_VALUE_NUM) {
> - for (i = 0; i < (SHARPSL_CNV_VALUE_NUM-1); i++)
> - sharpsl_ad[i] = sharpsl_ad[i+1];
> - sharpsl_ad_index = SHARPSL_CNV_VALUE_NUM - 1;
> - }
> - for (i = 0; i < sharpsl_ad_index; i++)
> - ad_val += sharpsl_ad[i];
> -
> - return ad_val / sharpsl_ad_index;
> -}
> -
> -/*
> - * Take an array of 5 integers, remove the maximum and minimum values
> - * and return the average.
> - */
> -static int get_select_val(int *val)
> -{
> - int i, j, k, temp, sum = 0;
> -
> - /* Find MAX val */
> - temp = val[0];
> - j = 0;
> - for (i = 1; i < 5; i++) {
> - if (temp < val[i]) {
> - temp = val[i];
> - j = i;
> - }
> - }
> -
> - /* Find MIN val */
> - temp = val[4];
> - k = 4;
> - for (i = 3; i >= 0; i--) {
> - if (temp > val[i]) {
> - temp = val[i];
> - k = i;
> - }
> - }
> -
> - for (i = 0; i < 5; i++)
> - if (i != j && i != k)
> - sum += val[i];
> -
> - dev_dbg(sharpsl_pm.dev, "Average: %d from values: %d, %d, %d, %d, %d\n", sum/3, val[0], val[1], val[2], val[3], val[4]);
> -
> - return sum/3;
> -}
> -
> -static int sharpsl_check_battery_temp(void)
> -{
> - int val, i, buff[5];
> -
> - /* Check battery temperature */
> - for (i = 0; i < 5; i++) {
> - mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP);
> - sharpsl_pm.machinfo->measure_temp(1);
> - mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP);
> - buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_TEMP);
> - sharpsl_pm.machinfo->measure_temp(0);
> - }
> -
> - val = get_select_val(buff);
> -
> - dev_dbg(sharpsl_pm.dev, "Temperature: %d\n", val);
> - if (val > sharpsl_pm.machinfo->charge_on_temp) {
> - printk(KERN_WARNING "Not charging: temperature out of limits.\n");
> - return -1;
> - }
> -
> - return 0;
> -}
> -
> -#ifdef CONFIG_PM
> -static int sharpsl_check_battery_voltage(void)
> -{
> - int val, i, buff[5];
> -
> - /* disable charge, enable discharge */
> - sharpsl_pm.machinfo->charge(0);
> - sharpsl_pm.machinfo->discharge(1);
> - mdelay(SHARPSL_WAIT_DISCHARGE_ON);
> -
> - if (sharpsl_pm.machinfo->discharge1)
> - sharpsl_pm.machinfo->discharge1(1);
> -
> - /* Check battery voltage */
> - for (i = 0; i < 5; i++) {
> - buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT);
> - mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT);
> - }
> -
> - if (sharpsl_pm.machinfo->discharge1)
> - sharpsl_pm.machinfo->discharge1(0);
> -
> - sharpsl_pm.machinfo->discharge(0);
> -
> - val = get_select_val(buff);
> - dev_dbg(sharpsl_pm.dev, "Battery Voltage: %d\n", val);
> -
> - if (val < sharpsl_pm.machinfo->charge_on_volt)
> - return -1;
> -
> - return 0;
> -}
> -#endif
> -
> -static int sharpsl_ac_check(void)
> -{
> - int temp, i, buff[5];
> -
> - for (i = 0; i < 5; i++) {
> - buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_ACIN_VOLT);
> - mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_ACIN);
> - }
> -
> - temp = get_select_val(buff);
> - dev_dbg(sharpsl_pm.dev, "AC Voltage: %d\n", temp);
> -
> - if ((temp > sharpsl_pm.machinfo->charge_acin_high) || (temp < sharpsl_pm.machinfo->charge_acin_low)) {
> - dev_err(sharpsl_pm.dev, "Error: AC check failed: voltage %d.\n", temp);
> - return -1;
> - }
> -
> - return 0;
> -}
> -
> -#ifdef CONFIG_PM
> -static int sharpsl_pm_suspend(struct platform_device *pdev, pm_message_t state)
> -{
> - sharpsl_pm.flags |= SHARPSL_SUSPENDED;
> - flush_delayed_work(&toggle_charger);
> - flush_delayed_work(&sharpsl_bat);
> -
> - if (sharpsl_pm.charge_mode == CHRG_ON)
> - sharpsl_pm.flags |= SHARPSL_DO_OFFLINE_CHRG;
> - else
> - sharpsl_pm.flags &= ~SHARPSL_DO_OFFLINE_CHRG;
> -
> - return 0;
> -}
> -
> -static int sharpsl_pm_resume(struct platform_device *pdev)
> -{
> - /* Clear the reset source indicators as they break the bootloader upon reboot */
> - RCSR = 0x0f;
> - sharpsl_average_clear();
> - sharpsl_pm.flags &= ~SHARPSL_APM_QUEUED;
> - sharpsl_pm.flags &= ~SHARPSL_SUSPENDED;
> -
> - return 0;
> -}
> -
> -static void corgi_goto_sleep(unsigned long alarm_time, unsigned int alarm_enable, suspend_state_t state)
> -{
> - dev_dbg(sharpsl_pm.dev, "Time is: %08x\n", RCNR);
> -
> - dev_dbg(sharpsl_pm.dev, "Offline Charge Activate = %d\n", sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG);
> - /* not charging and AC-IN! */
> -
> - if ((sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG) && (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN))) {
> - dev_dbg(sharpsl_pm.dev, "Activating Offline Charger...\n");
> - sharpsl_pm.charge_mode = CHRG_OFF;
> - sharpsl_pm.flags &= ~SHARPSL_DO_OFFLINE_CHRG;
> - sharpsl_off_charge_battery();
> - }
> -
> - sharpsl_pm.machinfo->presuspend();
> -
> - PEDR = 0xffffffff; /* clear it */
> -
> - sharpsl_pm.flags &= ~SHARPSL_ALARM_ACTIVE;
> - if ((sharpsl_pm.charge_mode == CHRG_ON) && ((alarm_enable && ((alarm_time - RCNR) > (SHARPSL_BATCHK_TIME_SUSPEND + 30))) || !alarm_enable)) {
> - RTSR &= RTSR_ALE;
> - RTAR = RCNR + SHARPSL_BATCHK_TIME_SUSPEND;
> - dev_dbg(sharpsl_pm.dev, "Charging alarm at: %08x\n", RTAR);
> - sharpsl_pm.flags |= SHARPSL_ALARM_ACTIVE;
> - } else if (alarm_enable) {
> - RTSR &= RTSR_ALE;
> - RTAR = alarm_time;
> - dev_dbg(sharpsl_pm.dev, "User alarm at: %08x\n", RTAR);
> - } else {
> - dev_dbg(sharpsl_pm.dev, "No alarms set.\n");
> - }
> -
> - pxa_pm_enter(state);
> -
> - sharpsl_pm.machinfo->postsuspend();
> -
> - dev_dbg(sharpsl_pm.dev, "Corgi woken up from suspend: %08x\n", PEDR);
> -}
> -
> -static int corgi_enter_suspend(unsigned long alarm_time, unsigned int alarm_enable, suspend_state_t state)
> -{
> - if (!sharpsl_pm.machinfo->should_wakeup(!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE) && alarm_enable)) {
> - if (!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE)) {
> - dev_dbg(sharpsl_pm.dev, "No user triggered wakeup events and not charging. Strange. Suspend.\n");
> - corgi_goto_sleep(alarm_time, alarm_enable, state);
> - return 1;
> - }
> - if (sharpsl_off_charge_battery()) {
> - dev_dbg(sharpsl_pm.dev, "Charging. Suspend...\n");
> - corgi_goto_sleep(alarm_time, alarm_enable, state);
> - return 1;
> - }
> - dev_dbg(sharpsl_pm.dev, "User triggered wakeup in offline charger.\n");
> - }
> -
> - if ((!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_LOCK)) ||
> - (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_FATAL))) {
> - dev_err(sharpsl_pm.dev, "Fatal condition. Suspend.\n");
> - corgi_goto_sleep(alarm_time, alarm_enable, state);
> - return 1;
> - }
> -
> - return 0;
> -}
> -
> -static int corgi_pxa_pm_enter(suspend_state_t state)
> -{
> - unsigned long alarm_time = RTAR;
> - unsigned int alarm_status = ((RTSR & RTSR_ALE) != 0);
> -
> - dev_dbg(sharpsl_pm.dev, "SharpSL suspending for first time.\n");
> -
> - corgi_goto_sleep(alarm_time, alarm_status, state);
> -
> - while (corgi_enter_suspend(alarm_time, alarm_status, state))
> - {}
> -
> - if (sharpsl_pm.machinfo->earlyresume)
> - sharpsl_pm.machinfo->earlyresume();
> -
> - dev_dbg(sharpsl_pm.dev, "SharpSL resuming...\n");
> -
> - return 0;
> -}
> -
> -static int sharpsl_off_charge_error(void)
> -{
> - dev_err(sharpsl_pm.dev, "Offline Charger: Error occurred.\n");
> - sharpsl_pm.machinfo->charge(0);
> - sharpsl_pm_led(SHARPSL_LED_ERROR);
> - sharpsl_pm.charge_mode = CHRG_ERROR;
> - return 1;
> -}
> -
> -/*
> - * Charging Control while suspended
> - * Return 1 - go straight to sleep
> - * Return 0 - sleep or wakeup depending on other factors
> - */
> -static int sharpsl_off_charge_battery(void)
> -{
> - int time;
> -
> - dev_dbg(sharpsl_pm.dev, "Charge Mode: %d\n", sharpsl_pm.charge_mode);
> -
> - if (sharpsl_pm.charge_mode == CHRG_OFF) {
> - dev_dbg(sharpsl_pm.dev, "Offline Charger: Step 1\n");
> -
> - /* AC Check */
> - if ((sharpsl_ac_check() < 0) || (sharpsl_check_battery_temp() < 0))
> - return sharpsl_off_charge_error();
> -
> - /* Start Charging */
> - sharpsl_pm_led(SHARPSL_LED_ON);
> - sharpsl_pm.machinfo->charge(0);
> - mdelay(SHARPSL_CHARGE_WAIT_TIME);
> - sharpsl_pm.machinfo->charge(1);
> -
> - sharpsl_pm.charge_mode = CHRG_ON;
> - sharpsl_pm.full_count = 0;
> -
> - return 1;
> - } else if (sharpsl_pm.charge_mode != CHRG_ON) {
> - return 1;
> - }
> -
> - if (sharpsl_pm.full_count == 0) {
> - int time;
> -
> - dev_dbg(sharpsl_pm.dev, "Offline Charger: Step 2\n");
> -
> - if ((sharpsl_check_battery_temp() < 0) || (sharpsl_check_battery_voltage() < 0))
> - return sharpsl_off_charge_error();
> -
> - sharpsl_pm.machinfo->charge(0);
> - mdelay(SHARPSL_CHARGE_WAIT_TIME);
> - sharpsl_pm.machinfo->charge(1);
> - sharpsl_pm.charge_mode = CHRG_ON;
> -
> - mdelay(SHARPSL_CHARGE_CO_CHECK_TIME);
> -
> - time = RCNR;
> - while (1) {
> - /* Check if any wakeup event had occurred */
> - if (sharpsl_pm.machinfo->charger_wakeup())
> - return 0;
> - /* Check for timeout */
> - if ((RCNR - time) > SHARPSL_WAIT_CO_TIME)
> - return 1;
> - if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) {
> - dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occurred. Retrying to check\n");
> - sharpsl_pm.full_count++;
> - sharpsl_pm.machinfo->charge(0);
> - mdelay(SHARPSL_CHARGE_WAIT_TIME);
> - sharpsl_pm.machinfo->charge(1);
> - return 1;
> - }
> - }
> - }
> -
> - dev_dbg(sharpsl_pm.dev, "Offline Charger: Step 3\n");
> -
> - mdelay(SHARPSL_CHARGE_CO_CHECK_TIME);
> -
> - time = RCNR;
> - while (1) {
> - /* Check if any wakeup event had occurred */
> - if (sharpsl_pm.machinfo->charger_wakeup())
> - return 0;
> - /* Check for timeout */
> - if ((RCNR-time) > SHARPSL_WAIT_CO_TIME) {
> - if (sharpsl_pm.full_count > SHARPSL_CHARGE_RETRY_CNT) {
> - dev_dbg(sharpsl_pm.dev, "Offline Charger: Not charged sufficiently. Retrying.\n");
> - sharpsl_pm.full_count = 0;
> - }
> - sharpsl_pm.full_count++;
> - return 1;
> - }
> - if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) {
> - dev_dbg(sharpsl_pm.dev, "Offline Charger: Charging complete.\n");
> - sharpsl_pm_led(SHARPSL_LED_OFF);
> - sharpsl_pm.machinfo->charge(0);
> - sharpsl_pm.charge_mode = CHRG_DONE;
> - return 1;
> - }
> - }
> -}
> -#else
> -#define sharpsl_pm_suspend NULL
> -#define sharpsl_pm_resume NULL
> -#endif
> -
> -static ssize_t battery_percentage_show(struct device *dev, struct device_attribute *attr, char *buf)
> -{
> - return sprintf(buf, "%d\n", sharpsl_pm.battstat.mainbat_percent);
> -}
> -
> -static ssize_t battery_voltage_show(struct device *dev, struct device_attribute *attr, char *buf)
> -{
> - return sprintf(buf, "%d\n", sharpsl_pm.battstat.mainbat_voltage);
> -}
> -
> -static DEVICE_ATTR_RO(battery_percentage);
> -static DEVICE_ATTR_RO(battery_voltage);
> -
> -extern void (*apm_get_power_status)(struct apm_power_info *);
> -
> -static void sharpsl_apm_get_power_status(struct apm_power_info *info)
> -{
> - info->ac_line_status = sharpsl_pm.battstat.ac_status;
> -
> - if (sharpsl_pm.charge_mode == CHRG_ON)
> - info->battery_status = APM_BATTERY_STATUS_CHARGING;
> - else
> - info->battery_status = sharpsl_pm.battstat.mainbat_status;
> -
> - info->battery_flag = (1 << info->battery_status);
> - info->battery_life = sharpsl_pm.battstat.mainbat_percent;
> -}
> -
> -#ifdef CONFIG_PM
> -static const struct platform_suspend_ops sharpsl_pm_ops = {
> - .prepare = pxa_pm_prepare,
> - .finish = pxa_pm_finish,
> - .enter = corgi_pxa_pm_enter,
> - .valid = suspend_valid_only_mem,
> -};
> -#endif
> -
> -static int sharpsl_pm_probe(struct platform_device *pdev)
> -{
> - int ret, irq;
> -
> - if (!pdev->dev.platform_data)
> - return -EINVAL;
> -
> - sharpsl_pm.dev = &pdev->dev;
> - sharpsl_pm.machinfo = pdev->dev.platform_data;
> - sharpsl_pm.charge_mode = CHRG_OFF;
> - sharpsl_pm.flags = 0;
> -
> - timer_setup(&sharpsl_pm.ac_timer, sharpsl_ac_timer, 0);
> -
> - timer_setup(&sharpsl_pm.chrg_full_timer, sharpsl_chrg_full_timer, 0);
> -
> - led_trigger_register_simple("sharpsl-charge", &sharpsl_charge_led_trigger);
> -
> - sharpsl_pm.machinfo->init();
> -
> - gpio_request(sharpsl_pm.machinfo->gpio_acin, "AC IN");
> - gpio_direction_input(sharpsl_pm.machinfo->gpio_acin);
> - gpio_request(sharpsl_pm.machinfo->gpio_batfull, "Battery Full");
> - gpio_direction_input(sharpsl_pm.machinfo->gpio_batfull);
> - gpio_request(sharpsl_pm.machinfo->gpio_batlock, "Battery Lock");
> - gpio_direction_input(sharpsl_pm.machinfo->gpio_batlock);
> -
> - /* Register interrupt handlers */
> - irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_acin);
> - if (request_irq(irq, sharpsl_ac_isr, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) {
> - dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
> - }
> -
> - irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_batlock);
> - if (request_irq(irq, sharpsl_fatal_isr, IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) {
> - dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
> - }
> -
> - if (sharpsl_pm.machinfo->gpio_fatal) {
> - irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_fatal);
> - if (request_irq(irq, sharpsl_fatal_isr, IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) {
> - dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
> - }
> - }
> -
> - if (sharpsl_pm.machinfo->batfull_irq) {
> - /* Register interrupt handler. */
> - irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_batfull);
> - if (request_irq(irq, sharpsl_chrg_full_isr, IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) {
> - dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
> - }
> - }
> -
> - ret = device_create_file(&pdev->dev, &dev_attr_battery_percentage);
> - ret |= device_create_file(&pdev->dev, &dev_attr_battery_voltage);
> - if (ret != 0)
> - dev_warn(&pdev->dev, "Failed to register attributes (%d)\n", ret);
> -
> - apm_get_power_status = sharpsl_apm_get_power_status;
> -
> -#ifdef CONFIG_PM
> - suspend_set_ops(&sharpsl_pm_ops);
> -#endif
> -
> - mod_timer(&sharpsl_pm.ac_timer, jiffies + msecs_to_jiffies(250));
> -
> - return 0;
> -}
> -
> -static void sharpsl_pm_remove(struct platform_device *pdev)
> -{
> - suspend_set_ops(NULL);
> -
> - device_remove_file(&pdev->dev, &dev_attr_battery_percentage);
> - device_remove_file(&pdev->dev, &dev_attr_battery_voltage);
> -
> - led_trigger_unregister_simple(sharpsl_charge_led_trigger);
> -
> - free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr);
> - free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr);
> -
> - if (sharpsl_pm.machinfo->gpio_fatal)
> - free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr);
> -
> - if (sharpsl_pm.machinfo->batfull_irq)
> - free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr);
> -
> - gpio_free(sharpsl_pm.machinfo->gpio_batlock);
> - gpio_free(sharpsl_pm.machinfo->gpio_batfull);
> - gpio_free(sharpsl_pm.machinfo->gpio_acin);
> -
> - if (sharpsl_pm.machinfo->exit)
> - sharpsl_pm.machinfo->exit();
> -
> - timer_delete_sync(&sharpsl_pm.chrg_full_timer);
> - timer_delete_sync(&sharpsl_pm.ac_timer);
> -}
> -
> -static struct platform_driver sharpsl_pm_driver = {
> - .probe = sharpsl_pm_probe,
> - .remove = sharpsl_pm_remove,
> - .suspend = sharpsl_pm_suspend,
> - .resume = sharpsl_pm_resume,
> - .driver = {
> - .name = "sharpsl-pm",
> - },
> -};
> -
> -static int sharpsl_pm_init(void)
> -{
> - return platform_driver_register(&sharpsl_pm_driver);
> -}
> -
> -static void sharpsl_pm_exit(void)
> -{
> - platform_driver_unregister(&sharpsl_pm_driver);
> -}
> -
> -late_initcall(sharpsl_pm_init);
> -module_exit(sharpsl_pm_exit);
> diff --git a/arch/arm/mach-pxa/sharpsl_pm.h b/arch/arm/mach-pxa/sharpsl_pm.h
> deleted file mode 100644
> index 623167f30ec2..000000000000
> --- a/arch/arm/mach-pxa/sharpsl_pm.h
> +++ /dev/null
> @@ -1,108 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * SharpSL Battery/PM Driver
> - *
> - * Copyright (c) 2004-2005 Richard Purdie
> - */
> -#ifndef _MACH_SHARPSL_PM
> -#define _MACH_SHARPSL_PM
> -
> -struct sharpsl_charger_machinfo {
> - void (*init)(void);
> - void (*exit)(void);
> - int gpio_acin;
> - int gpio_batfull;
> - int batfull_irq;
> - int gpio_batlock;
> - int gpio_fatal;
> - void (*discharge)(int);
> - void (*discharge1)(int);
> - void (*charge)(int);
> - void (*measure_temp)(int);
> - void (*presuspend)(void);
> - void (*postsuspend)(void);
> - void (*earlyresume)(void);
> - unsigned long (*read_devdata)(int);
> -#define SHARPSL_BATT_VOLT 1
> -#define SHARPSL_BATT_TEMP 2
> -#define SHARPSL_ACIN_VOLT 3
> -#define SHARPSL_STATUS_ACIN 4
> -#define SHARPSL_STATUS_LOCK 5
> -#define SHARPSL_STATUS_CHRGFULL 6
> -#define SHARPSL_STATUS_FATAL 7
> - bool (*charger_wakeup)(void);
> - int (*should_wakeup)(unsigned int resume_on_alarm);
> - void (*backlight_limit)(int);
> - int (*backlight_get_status) (void);
> - int charge_on_volt;
> - int charge_on_temp;
> - int charge_acin_high;
> - int charge_acin_low;
> - int fatal_acin_volt;
> - int fatal_noacin_volt;
> - int bat_levels;
> - struct battery_thresh *bat_levels_noac;
> - struct battery_thresh *bat_levels_acin;
> - struct battery_thresh *bat_levels_noac_bl;
> - struct battery_thresh *bat_levels_acin_bl;
> - int status_high_acin;
> - int status_low_acin;
> - int status_high_noac;
> - int status_low_noac;
> -};
> -
> -struct battery_thresh {
> - int voltage;
> - int percentage;
> -};
> -
> -struct battery_stat {
> - int ac_status; /* APM AC Present/Not Present */
> - int mainbat_status; /* APM Main Battery Status */
> - int mainbat_percent; /* Main Battery Percentage Charge */
> - int mainbat_voltage; /* Main Battery Voltage */
> -};
> -
> -struct sharpsl_pm_status {
> - struct device *dev;
> - struct timer_list ac_timer;
> - struct timer_list chrg_full_timer;
> -
> - int charge_mode;
> -#define CHRG_ERROR (-1)
> -#define CHRG_OFF (0)
> -#define CHRG_ON (1)
> -#define CHRG_DONE (2)
> -
> - unsigned int flags;
> -#define SHARPSL_SUSPENDED (1 << 0) /* Device is Suspended */
> -#define SHARPSL_ALARM_ACTIVE (1 << 1) /* Alarm is for charging event (not user) */
> -#define SHARPSL_BL_LIMIT (1 << 2) /* Backlight Intensity Limited */
> -#define SHARPSL_APM_QUEUED (1 << 3) /* APM Event Queued */
> -#define SHARPSL_DO_OFFLINE_CHRG (1 << 4) /* Trigger the offline charger */
> -
> - int full_count;
> - unsigned long charge_start_time;
> - struct sharpsl_charger_machinfo *machinfo;
> - struct battery_stat battstat;
> -};
> -
> -extern struct sharpsl_pm_status sharpsl_pm;
> -
> -extern struct battery_thresh sharpsl_battery_levels_acin[];
> -extern struct battery_thresh sharpsl_battery_levels_noac[];
> -
> -#define SHARPSL_LED_ERROR 2
> -#define SHARPSL_LED_ON 1
> -#define SHARPSL_LED_OFF 0
> -
> -void sharpsl_battery_kick(void);
> -void sharpsl_pm_led(int val);
> -
> -/* MAX1111 Channel Definitions */
> -#define MAX1111_BATT_VOLT 4u
> -#define MAX1111_BATT_TEMP 2u
> -#define MAX1111_ACIN_VOLT 6u
> -int sharpsl_pm_pxa_read_max1111(int channel);
> -
> -#endif
> diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
> deleted file mode 100644
> index 5eaf38243b9e..000000000000
> --- a/arch/arm/mach-pxa/spitz.c
> +++ /dev/null
> @@ -1,1174 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Support for Sharp SL-Cxx00 Series of PDAs
> - * Models: SL-C3000 (Spitz), SL-C1000 (Akita) and SL-C3100 (Borzoi)
> - *
> - * Copyright (c) 2005 Richard Purdie
> - *
> - * Based on Sharp's 2.4 kernel patches/lubbock.c
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/platform_device.h>
> -#include <linux/delay.h>
> -#include <linux/gpio_keys.h>
> -#include <linux/gpio/legacy.h>
> -#include <linux/gpio/machine.h>
> -#include <linux/gpio/property.h>
> -#include <linux/leds.h>
> -#include <linux/i2c.h>
> -#include <linux/platform_data/i2c-pxa.h>
> -#include <linux/platform_data/pca953x.h>
> -#include <linux/property.h>
> -#include <linux/spi/spi.h>
> -#include <linux/spi/ads7846.h>
> -#include <linux/spi/corgi_lcd.h>
> -#include <linux/mtd/sharpsl.h>
> -#include <linux/mtd/physmap.h>
> -#include <linux/input-event-codes.h>
> -#include <linux/input/matrix_keypad.h>
> -#include <linux/regulator/machine.h>
> -#include <linux/io.h>
> -#include <linux/property.h>
> -#include <linux/reboot.h>
> -#include <linux/memblock.h>
> -
> -#include <asm/setup.h>
> -#include <asm/mach-types.h>
> -#include <asm/mach/arch.h>
> -#include <asm/mach/sharpsl_param.h>
> -#include <asm/hardware/scoop.h>
> -
> -#include "pxa27x.h"
> -#include "pxa27x-udc.h"
> -#include "reset.h"
> -#include <linux/platform_data/mmc-pxamci.h>
> -#include <linux/platform_data/usb-ohci-pxa27x.h>
> -#include <linux/platform_data/video-pxafb.h>
> -#include "spitz.h"
> -#include "sharpsl_pm.h"
> -#include "smemc.h"
> -
> -#include "generic.h"
> -#include "devices.h"
> -
> -/******************************************************************************
> - * Pin configuration
> - ******************************************************************************/
> -static unsigned long spitz_pin_config[] __initdata = {
> - /* Chip Selects */
> - GPIO78_nCS_2, /* SCOOP #2 */
> - GPIO79_nCS_3, /* NAND */
> - GPIO80_nCS_4, /* SCOOP #1 */
> -
> - /* LCD - 16bpp Active TFT */
> - GPIOxx_LCD_TFT_16BPP,
> -
> - /* PC Card */
> - GPIO48_nPOE,
> - GPIO49_nPWE,
> - GPIO50_nPIOR,
> - GPIO51_nPIOW,
> - GPIO85_nPCE_1,
> - GPIO54_nPCE_2,
> - GPIO55_nPREG,
> - GPIO56_nPWAIT,
> - GPIO57_nIOIS16,
> - GPIO104_PSKTSEL,
> -
> - /* I2S */
> - GPIO28_I2S_BITCLK_OUT,
> - GPIO29_I2S_SDATA_IN,
> - GPIO30_I2S_SDATA_OUT,
> - GPIO31_I2S_SYNC,
> -
> - /* MMC */
> - GPIO32_MMC_CLK,
> - GPIO112_MMC_CMD,
> - GPIO92_MMC_DAT_0,
> - GPIO109_MMC_DAT_1,
> - GPIO110_MMC_DAT_2,
> - GPIO111_MMC_DAT_3,
> -
> - /* GPIOs */
> - GPIO9_GPIO, /* SPITZ_GPIO_nSD_DETECT */
> - GPIO16_GPIO, /* SPITZ_GPIO_SYNC */
> - GPIO81_GPIO, /* SPITZ_GPIO_nSD_WP */
> - GPIO41_GPIO, /* SPITZ_GPIO_USB_CONNECT */
> - GPIO37_GPIO, /* SPITZ_GPIO_USB_HOST */
> - GPIO35_GPIO, /* SPITZ_GPIO_USB_DEVICE */
> - GPIO22_GPIO, /* SPITZ_GPIO_HSYNC */
> - GPIO94_GPIO, /* SPITZ_GPIO_CF_CD */
> - GPIO105_GPIO, /* SPITZ_GPIO_CF_IRQ */
> - GPIO106_GPIO, /* SPITZ_GPIO_CF2_IRQ */
> -
> - /* GPIO matrix keypad */
> - GPIO88_GPIO, /* column 0 */
> - GPIO23_GPIO, /* column 1 */
> - GPIO24_GPIO, /* column 2 */
> - GPIO25_GPIO, /* column 3 */
> - GPIO26_GPIO, /* column 4 */
> - GPIO27_GPIO, /* column 5 */
> - GPIO52_GPIO, /* column 6 */
> - GPIO103_GPIO, /* column 7 */
> - GPIO107_GPIO, /* column 8 */
> - GPIO108_GPIO, /* column 9 */
> - GPIO114_GPIO, /* column 10 */
> - GPIO12_GPIO, /* row 0 */
> - GPIO17_GPIO, /* row 1 */
> - GPIO91_GPIO, /* row 2 */
> - GPIO34_GPIO, /* row 3 */
> - GPIO36_GPIO, /* row 4 */
> - GPIO38_GPIO, /* row 5 */
> - GPIO39_GPIO, /* row 6 */
> -
> - /* I2C */
> - GPIO117_I2C_SCL,
> - GPIO118_I2C_SDA,
> -
> - GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, /* SPITZ_GPIO_KEY_INT */
> - GPIO1_GPIO | WAKEUP_ON_EDGE_FALL, /* SPITZ_GPIO_RESET */
> -};
> -
> -static const struct software_node spitz_scoop_1_gpiochip_node = {
> - .name = "sharp-scoop.0",
> -};
> -
> -/* Only on Spitz */
> -static const struct software_node spitz_scoop_2_gpiochip_node = {
> - .name = "sharp-scoop.1",
> -};
> -
> -/* Only on Akita */
> -static const struct software_node akita_max7310_gpiochip_node = {
> - .name = "i2c-max7310",
> -};
> -
> -/******************************************************************************
> - * Scoop GPIO expander
> - ******************************************************************************/
> -#if defined(CONFIG_SHARP_SCOOP) || defined(CONFIG_SHARP_SCOOP_MODULE)
> -/* SCOOP Device #1 */
> -static struct resource spitz_scoop_1_resources[] = {
> - [0] = {
> - .start = 0x10800000,
> - .end = 0x10800fff,
> - .flags = IORESOURCE_MEM,
> - },
> -};
> -
> -static struct scoop_config spitz_scoop_1_setup = {
> - .io_dir = SPITZ_SCP_IO_DIR,
> - .io_out = SPITZ_SCP_IO_OUT,
> - .suspend_clr = SPITZ_SCP_SUS_CLR,
> - .suspend_set = SPITZ_SCP_SUS_SET,
> - .gpio_base = SPITZ_SCP_GPIO_BASE,
> -};
> -
> -static struct platform_device spitz_scoop_1_device = {
> - .name = "sharp-scoop",
> - .id = 0,
> - .dev = {
> - .platform_data = &spitz_scoop_1_setup,
> - },
> - .num_resources = ARRAY_SIZE(spitz_scoop_1_resources),
> - .resource = spitz_scoop_1_resources,
> -};
> -
> -/* SCOOP Device #2 */
> -static struct resource spitz_scoop_2_resources[] = {
> - [0] = {
> - .start = 0x08800040,
> - .end = 0x08800fff,
> - .flags = IORESOURCE_MEM,
> - },
> -};
> -
> -static struct scoop_config spitz_scoop_2_setup = {
> - .io_dir = SPITZ_SCP2_IO_DIR,
> - .io_out = SPITZ_SCP2_IO_OUT,
> - .suspend_clr = SPITZ_SCP2_SUS_CLR,
> - .suspend_set = SPITZ_SCP2_SUS_SET,
> - .gpio_base = SPITZ_SCP2_GPIO_BASE,
> -};
> -
> -static struct platform_device spitz_scoop_2_device = {
> - .name = "sharp-scoop",
> - .id = 1,
> - .dev = {
> - .platform_data = &spitz_scoop_2_setup,
> - },
> - .num_resources = ARRAY_SIZE(spitz_scoop_2_resources),
> - .resource = spitz_scoop_2_resources,
> -};
> -
> -static void __init spitz_scoop_init(void)
> -{
> - spitz_scoop_1_device.dev.fwnode = software_node_fwnode(&spitz_scoop_1_gpiochip_node);
> - platform_device_register(&spitz_scoop_1_device);
> -
> - /* Akita doesn't have the second SCOOP chip */
> - if (!machine_is_akita()) {
> - spitz_scoop_2_device.dev.fwnode = software_node_fwnode(
> - &spitz_scoop_2_gpiochip_node);
> - platform_device_register(&spitz_scoop_2_device);
> - }
> -}
> -
> -/* Power control is shared with between one of the CF slots and SD */
> -static void __maybe_unused spitz_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr)
> -{
> - unsigned short cpr;
> - unsigned long flags;
> -
> - if (new_cpr & 0x7) {
> - gpio_set_value(SPITZ_GPIO_CF_POWER, 1);
> - mdelay(5);
> - }
> -
> - local_irq_save(flags);
> -
> - cpr = read_scoop_reg(&spitz_scoop_1_device.dev, SCOOP_CPR);
> -
> - if (enable & new_cpr)
> - cpr |= new_cpr;
> - else
> - cpr &= ~enable;
> -
> - write_scoop_reg(&spitz_scoop_1_device.dev, SCOOP_CPR, cpr);
> -
> - local_irq_restore(flags);
> -
> - if (!(cpr & 0x7)) {
> - mdelay(1);
> - gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
> - }
> -}
> -
> -#else
> -static inline void spitz_scoop_init(void) {}
> -static inline void spitz_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr) {}
> -#endif
> -
> -/******************************************************************************
> - * PCMCIA
> - ******************************************************************************/
> -#if defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
> -static void spitz_pcmcia_pwr(struct device *scoop, uint16_t cpr, int nr)
> -{
> - /* Only need to override behaviour for slot 0 */
> - if (nr == 0)
> - spitz_card_pwr_ctrl(
> - cpr & (SCOOP_CPR_CF_3V | SCOOP_CPR_CF_XV), cpr);
> - else
> - write_scoop_reg(scoop, SCOOP_CPR, cpr);
> -}
> -
> -static struct scoop_pcmcia_dev spitz_pcmcia_scoop[] = {
> - {
> - .dev = &spitz_scoop_1_device.dev,
> - .irq = SPITZ_IRQ_GPIO_CF_IRQ,
> - .cd_irq = SPITZ_IRQ_GPIO_CF_CD,
> - .cd_irq_str = "PCMCIA0 CD",
> - }, {
> - .dev = &spitz_scoop_2_device.dev,
> - .irq = SPITZ_IRQ_GPIO_CF2_IRQ,
> - .cd_irq = -1,
> - },
> -};
> -
> -static struct scoop_pcmcia_config spitz_pcmcia_config = {
> - .devs = &spitz_pcmcia_scoop[0],
> - .num_devs = 2,
> - .power_ctrl = spitz_pcmcia_pwr,
> -};
> -
> -static void __init spitz_pcmcia_init(void)
> -{
> - /* Akita has only one PCMCIA slot used */
> - if (machine_is_akita())
> - spitz_pcmcia_config.num_devs = 1;
> -
> - platform_scoop_config = &spitz_pcmcia_config;
> -}
> -#else
> -static inline void spitz_pcmcia_init(void) {}
> -#endif
> -
> -/******************************************************************************
> - * GPIO keyboard
> - ******************************************************************************/
> -#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
> -
> -#define SPITZ_KEY_CALENDAR KEY_F1
> -#define SPITZ_KEY_ADDRESS KEY_F2
> -#define SPITZ_KEY_FN KEY_F3
> -#define SPITZ_KEY_CANCEL KEY_F4
> -#define SPITZ_KEY_EXOK KEY_F5
> -#define SPITZ_KEY_EXCANCEL KEY_F6
> -#define SPITZ_KEY_EXJOGDOWN KEY_F7
> -#define SPITZ_KEY_EXJOGUP KEY_F8
> -#define SPITZ_KEY_JAP1 KEY_LEFTALT
> -#define SPITZ_KEY_JAP2 KEY_RIGHTCTRL
> -#define SPITZ_KEY_SYNC KEY_F9
> -#define SPITZ_KEY_MAIL KEY_F10
> -#define SPITZ_KEY_OK KEY_F11
> -#define SPITZ_KEY_MENU KEY_F12
> -
> -static const uint32_t spitz_keymap[] = {
> - KEY(0, 0, KEY_LEFTCTRL),
> - KEY(0, 1, KEY_1),
> - KEY(0, 2, KEY_3),
> - KEY(0, 3, KEY_5),
> - KEY(0, 4, KEY_6),
> - KEY(0, 5, KEY_7),
> - KEY(0, 6, KEY_9),
> - KEY(0, 7, KEY_0),
> - KEY(0, 8, KEY_BACKSPACE),
> - KEY(0, 9, SPITZ_KEY_EXOK), /* EXOK */
> - KEY(0, 10, SPITZ_KEY_EXCANCEL), /* EXCANCEL */
> - KEY(1, 1, KEY_2),
> - KEY(1, 2, KEY_4),
> - KEY(1, 3, KEY_R),
> - KEY(1, 4, KEY_Y),
> - KEY(1, 5, KEY_8),
> - KEY(1, 6, KEY_I),
> - KEY(1, 7, KEY_O),
> - KEY(1, 8, KEY_P),
> - KEY(1, 9, SPITZ_KEY_EXJOGDOWN), /* EXJOGDOWN */
> - KEY(1, 10, SPITZ_KEY_EXJOGUP), /* EXJOGUP */
> - KEY(2, 0, KEY_TAB),
> - KEY(2, 1, KEY_Q),
> - KEY(2, 2, KEY_E),
> - KEY(2, 3, KEY_T),
> - KEY(2, 4, KEY_G),
> - KEY(2, 5, KEY_U),
> - KEY(2, 6, KEY_J),
> - KEY(2, 7, KEY_K),
> - KEY(3, 0, SPITZ_KEY_ADDRESS), /* ADDRESS */
> - KEY(3, 1, KEY_W),
> - KEY(3, 2, KEY_S),
> - KEY(3, 3, KEY_F),
> - KEY(3, 4, KEY_V),
> - KEY(3, 5, KEY_H),
> - KEY(3, 6, KEY_M),
> - KEY(3, 7, KEY_L),
> - KEY(3, 9, KEY_RIGHTSHIFT),
> - KEY(4, 0, SPITZ_KEY_CALENDAR), /* CALENDAR */
> - KEY(4, 1, KEY_A),
> - KEY(4, 2, KEY_D),
> - KEY(4, 3, KEY_C),
> - KEY(4, 4, KEY_B),
> - KEY(4, 5, KEY_N),
> - KEY(4, 6, KEY_DOT),
> - KEY(4, 8, KEY_ENTER),
> - KEY(4, 9, KEY_LEFTSHIFT),
> - KEY(5, 0, SPITZ_KEY_MAIL), /* MAIL */
> - KEY(5, 1, KEY_Z),
> - KEY(5, 2, KEY_X),
> - KEY(5, 3, KEY_MINUS),
> - KEY(5, 4, KEY_SPACE),
> - KEY(5, 5, KEY_COMMA),
> - KEY(5, 7, KEY_UP),
> - KEY(5, 10, SPITZ_KEY_FN), /* FN */
> - KEY(6, 0, KEY_SYSRQ),
> - KEY(6, 1, SPITZ_KEY_JAP1), /* JAP1 */
> - KEY(6, 2, SPITZ_KEY_JAP2), /* JAP2 */
> - KEY(6, 3, SPITZ_KEY_CANCEL), /* CANCEL */
> - KEY(6, 4, SPITZ_KEY_OK), /* OK */
> - KEY(6, 5, SPITZ_KEY_MENU), /* MENU */
> - KEY(6, 6, KEY_LEFT),
> - KEY(6, 7, KEY_DOWN),
> - KEY(6, 8, KEY_RIGHT),
> -};
> -
> -static const struct software_node_ref_args spitz_mkp_row_gpios[] = {
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 12, GPIO_ACTIVE_HIGH),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 17, GPIO_ACTIVE_HIGH),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 91, GPIO_ACTIVE_HIGH),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 34, GPIO_ACTIVE_HIGH),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 36, GPIO_ACTIVE_HIGH),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 38, GPIO_ACTIVE_HIGH),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 39, GPIO_ACTIVE_HIGH),
> -};
> -
> -static const struct software_node_ref_args spitz_mkp_col_gpios[] = {
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 88, GPIO_ACTIVE_HIGH),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 23, GPIO_ACTIVE_HIGH),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 24, GPIO_ACTIVE_HIGH),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 25, GPIO_ACTIVE_HIGH),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 26, GPIO_ACTIVE_HIGH),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 27, GPIO_ACTIVE_HIGH),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 52, GPIO_ACTIVE_HIGH),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 103, GPIO_ACTIVE_HIGH),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 107, GPIO_ACTIVE_HIGH),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 108, GPIO_ACTIVE_HIGH),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, 114, GPIO_ACTIVE_HIGH),
> -};
> -
> -static const struct property_entry spitz_mkp_properties[] = {
> - PROPERTY_ENTRY_U32_ARRAY("linux,keymap", spitz_keymap),
> - PROPERTY_ENTRY_REF_ARRAY("row-gpios", spitz_mkp_row_gpios),
> - PROPERTY_ENTRY_REF_ARRAY("col-gpios", spitz_mkp_col_gpios),
> - PROPERTY_ENTRY_U32("col-scan-delay-us", 10),
> - PROPERTY_ENTRY_U32("debounce-delay-ms", 10),
> - PROPERTY_ENTRY_BOOL("wakeup-source"),
> - { }
> -};
> -
> -static const struct platform_device_info spitz_mkp_info __initconst = {
> - .name = "matrix-keypad",
> - .id = PLATFORM_DEVID_NONE,
> - .properties = spitz_mkp_properties,
> -};
> -
> -
> -static void __init spitz_mkp_init(void)
> -{
> - struct platform_device *pd;
> - int err;
> -
> - pd = platform_device_register_full(&spitz_mkp_info);
> - err = PTR_ERR_OR_ZERO(pd);
> - if (err)
> - pr_err("failed to create keypad device: %d\n", err);
> -}
> -#else
> -static inline void spitz_mkp_init(void) {}
> -#endif
> -
> -/******************************************************************************
> - * GPIO keys
> - ******************************************************************************/
> -#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
> -static const struct software_node spitz_gpio_keys_node = {
> - .name = "spitz-gpio-keys",
> -};
> -
> -static const struct property_entry spitz_suspend_key_props[] = {
> - PROPERTY_ENTRY_U32("linux,input-type", EV_PWR),
> - PROPERTY_ENTRY_U32("linux,code", KEY_SUSPEND),
> - PROPERTY_ENTRY_GPIO("gpios", &pxa2xx_gpiochip_node,
> - SPITZ_GPIO_ON_KEY, GPIO_ACTIVE_HIGH),
> - PROPERTY_ENTRY_STRING("label", "On Off"),
> - PROPERTY_ENTRY_BOOL("wakeup-source"),
> - { }
> -};
> -
> -static const struct software_node spitz_suspend_key_node = {
> - .parent = &spitz_gpio_keys_node,
> - .properties = spitz_suspend_key_props,
> -};
> -
> -static const struct property_entry spitz_sw1_props[] = {
> - PROPERTY_ENTRY_U32("linux,input-type", EV_SW),
> - PROPERTY_ENTRY_U32("linux,code", 0),
> - PROPERTY_ENTRY_GPIO("gpios", &pxa2xx_gpiochip_node,
> - SPITZ_GPIO_SWA, GPIO_ACTIVE_HIGH),
> - PROPERTY_ENTRY_STRING("label", "Display Down"),
> - { }
> -};
> -
> -static const struct software_node spitz_sw1_node = {
> - .parent = &spitz_gpio_keys_node,
> - .properties = spitz_sw1_props,
> -};
> -
> -static const struct property_entry spitz_sw2_props[] = {
> - PROPERTY_ENTRY_U32("linux,input-type", EV_SW),
> - PROPERTY_ENTRY_U32("linux,code", 1),
> - PROPERTY_ENTRY_GPIO("gpios", &pxa2xx_gpiochip_node,
> - SPITZ_GPIO_SWB, GPIO_ACTIVE_HIGH),
> - PROPERTY_ENTRY_STRING("label", "Lid Closed"),
> - { }
> -};
> -
> -static const struct software_node spitz_sw2_node = {
> - .parent = &spitz_gpio_keys_node,
> - .properties = spitz_sw2_props,
> -};
> -
> -static const struct software_node *spitz_gpio_keys_swnodes[] = {
> - &spitz_gpio_keys_node,
> - &spitz_suspend_key_node,
> - &spitz_sw1_node,
> - &spitz_sw2_node,
> - NULL
> -};
> -
> -static void __init spitz_keys_init(void)
> -{
> - struct platform_device_info keys_info = {
> - .name = "gpio-keys",
> - .id = PLATFORM_DEVID_NONE,
> - };
> - struct platform_device *pd;
> - int err;
> -
> - err = software_node_register_node_group(spitz_gpio_keys_swnodes);
> - if (err) {
> - pr_err("failed to register gpio-keys software nodes: %d\n", err);
> - return;
> - }
> -
> - keys_info.fwnode = software_node_fwnode(&spitz_gpio_keys_node);
> -
> - pd = platform_device_register_full(&keys_info);
> - err = PTR_ERR_OR_ZERO(pd);
> - if (err)
> - pr_err("failed to create gpio-keys device: %d\n", err);
> -}
> -#else
> -static inline void spitz_keys_init(void) {}
> -#endif
> -
> -/******************************************************************************
> - * LEDs
> - ******************************************************************************/
> -#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
> -static const struct software_node spitz_gpio_leds_node = {
> - .name = "spitz-leds",
> -};
> -
> -static const struct property_entry spitz_orange_led_props[] = {
> - PROPERTY_ENTRY_STRING("linux,default-trigger", "sharpsl-charge"),
> - PROPERTY_ENTRY_GPIO("gpios",
> - &spitz_scoop_1_gpiochip_node, 6, GPIO_ACTIVE_HIGH),
> - { }
> -};
> -
> -static const struct software_node spitz_orange_led_node = {
> - .name = "spitz:amber:charge",
> - .parent = &spitz_gpio_leds_node,
> - .properties = spitz_orange_led_props,
> -};
> -
> -static const struct property_entry spitz_green_led_props[] = {
> - PROPERTY_ENTRY_STRING("linux,default-trigger", "disk-activity"),
> - PROPERTY_ENTRY_GPIO("gpios",
> - &spitz_scoop_1_gpiochip_node, 0, GPIO_ACTIVE_HIGH),
> - { }
> -};
> -
> -static const struct software_node spitz_green_led_node = {
> - .name = "spitz:green:hddactivity",
> - .parent = &spitz_gpio_leds_node,
> - .properties = spitz_green_led_props,
> -};
> -
> -static const struct software_node *spitz_gpio_leds_swnodes[] = {
> - &spitz_gpio_leds_node,
> - &spitz_orange_led_node,
> - &spitz_green_led_node,
> - NULL
> -};
> -
> -static void __init spitz_leds_init(void)
> -{
> - struct platform_device_info led_info = {
> - .name = "leds-gpio",
> - .id = PLATFORM_DEVID_NONE,
> - };
> - struct platform_device *led_dev;
> - int err;
> -
> - err = software_node_register_node_group(spitz_gpio_leds_swnodes);
> - if (err) {
> - pr_err("failed to register LED software nodes: %d\n", err);
> - return;
> - }
> -
> - led_info.fwnode = software_node_fwnode(&spitz_gpio_leds_node);
> -
> - led_dev = platform_device_register_full(&led_info);
> - err = PTR_ERR_OR_ZERO(led_dev);
> - if (err)
> - pr_err("failed to create LED device: %d\n", err);
> -}
> -#else
> -static inline void spitz_leds_init(void) {}
> -#endif
> -
> -/******************************************************************************
> - * SSP Devices
> - ******************************************************************************/
> -#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
> -
> -static const struct property_entry spitz_ads7846_props[] = {
> - PROPERTY_ENTRY_STRING("compatible", "ti,ads7846"),
> - PROPERTY_ENTRY_U32("touchscreen-max-pressure", 1024),
> - PROPERTY_ENTRY_U16("ti,x-plate-ohms", 419),
> - PROPERTY_ENTRY_U16("ti,y-plate-ohms", 486),
> - PROPERTY_ENTRY_U16("ti,vref-delay-usecs", 100),
> - PROPERTY_ENTRY_GPIO("pendown-gpios", &pxa2xx_gpiochip_node,
> - SPITZ_GPIO_TP_INT, GPIO_ACTIVE_LOW),
> - PROPERTY_ENTRY_GPIO("ti,hsync-gpios", &pxa2xx_gpiochip_node,
> - SPITZ_GPIO_HSYNC, GPIO_ACTIVE_LOW),
> - { }
> -};
> -
> -static const struct software_node spitz_ads7846_swnode = {
> - .name = "ads7846",
> - .properties = spitz_ads7846_props,
> -};
> -
> -static const struct property_entry spitz_lcdcon_props[] = {
> - PROPERTY_ENTRY_GPIO("BL_CONT-gpios",
> - &spitz_scoop_2_gpiochip_node, 6, GPIO_ACTIVE_LOW),
> - PROPERTY_ENTRY_GPIO("BL_ON-gpios",
> - &spitz_scoop_2_gpiochip_node, 7, GPIO_ACTIVE_HIGH),
> - { }
> -};
> -
> -static const struct property_entry akita_lcdcon_props[] = {
> - PROPERTY_ENTRY_GPIO("BL_ON-gpios",
> - &akita_max7310_gpiochip_node, 3, GPIO_ACTIVE_HIGH),
> - PROPERTY_ENTRY_GPIO("BL_CONT-gpios",
> - &akita_max7310_gpiochip_node, 4, GPIO_ACTIVE_LOW),
> - { }
> -};
> -
> -static struct software_node spitz_lcdcon_node = {
> - .name = "spitz-lcdcon",
> -};
> -
> -static struct corgi_lcd_platform_data spitz_lcdcon_info = {
> - .init_mode = CORGI_LCD_MODE_VGA,
> - .max_intensity = 0x2f,
> - .default_intensity = 0x1f,
> - .limit_mask = 0x0b,
> - .kick_battery = sharpsl_battery_kick,
> -};
> -
> -static struct spi_board_info spitz_spi_devices[] = {
> - {
> - .modalias = "ads7846",
> - .max_speed_hz = 1200000,
> - .bus_num = 2,
> - .chip_select = 0,
> - .swnode = &spitz_ads7846_swnode,
> - .irq = PXA_GPIO_TO_IRQ(SPITZ_GPIO_TP_INT),
> - }, {
> - .modalias = "corgi-lcd",
> - .max_speed_hz = 50000,
> - .bus_num = 2,
> - .chip_select = 1,
> - .platform_data = &spitz_lcdcon_info,
> - .swnode = &spitz_lcdcon_node,
> - }, {
> - .modalias = "max1111",
> - .max_speed_hz = 450000,
> - .bus_num = 2,
> - .chip_select = 2,
> - },
> -};
> -
> -static const struct software_node_ref_args spitz_spi_gpio_refs[] = {
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, SPITZ_GPIO_ADS7846_CS,
> - GPIO_ACTIVE_LOW),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, SPITZ_GPIO_LCDCON_CS,
> - GPIO_ACTIVE_LOW),
> - SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, SPITZ_GPIO_MAX1111_CS,
> - GPIO_ACTIVE_LOW),
> -};
> -
> -static const struct property_entry spitz_spi_properties[] = {
> - PROPERTY_ENTRY_REF_ARRAY("gpios", spitz_spi_gpio_refs),
> - { }
> -};
> -
> -static const struct platform_device_info spitz_spi_device_info = {
> - .name = "pxa2xx-spi",
> - /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1 */
> - .id = 2,
> - .properties = spitz_spi_properties,
> -};
> -
> -static void __init spitz_spi_init(void)
> -{
> - struct platform_device *pd;
> - int err;
> -
> - pd = platform_device_register_full(&spitz_spi_device_info);
> - err = PTR_ERR_OR_ZERO(pd);
> - if (err)
> - pr_err("pxa2xx-spi: failed to instantiate SPI controller: %d\n",
> - err);
> -
> - spitz_lcdcon_node.properties = machine_is_akita() ?
> - akita_lcdcon_props : spitz_lcdcon_props;
> - spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices));
> -}
> -#else
> -static inline void spitz_spi_init(void) {}
> -#endif
> -
> -/******************************************************************************
> - * SD/MMC card controller
> - ******************************************************************************/
> -#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
> -/*
> - * NOTE: The card detect interrupt isn't debounced so we delay it by 250ms to
> - * give the card a chance to fully insert/eject.
> - */
> -static int spitz_mci_setpower(struct device *dev, unsigned int vdd)
> -{
> - struct pxamci_platform_data* p_d = dev->platform_data;
> -
> - if ((1 << vdd) & p_d->ocr_mask)
> - spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, SCOOP_CPR_SD_3V);
> - else
> - spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0);
> -
> - return 0;
> -}
> -
> -static struct pxamci_platform_data spitz_mci_platform_data = {
> - .detect_delay_ms = 250,
> - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
> - .setpower = spitz_mci_setpower,
> -};
> -
> -static const struct property_entry spitz_mci_props[] __initconst = {
> - PROPERTY_ENTRY_GPIO("cd-gpios", &pxa2xx_gpiochip_node,
> - SPITZ_GPIO_nSD_DETECT, GPIO_ACTIVE_LOW),
> - PROPERTY_ENTRY_GPIO("wp-gpios", &pxa2xx_gpiochip_node,
> - SPITZ_GPIO_nSD_WP, GPIO_ACTIVE_LOW),
> - { }
> -};
> -
> -static void __init spitz_mmc_init(void)
> -{
> - pxa_set_mci_info(&spitz_mci_platform_data, spitz_mci_props);
> -}
> -#else
> -static inline void spitz_mmc_init(void) {}
> -#endif
> -
> -/******************************************************************************
> - * USB Host
> - ******************************************************************************/
> -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
> -static int spitz_ohci_init(struct device *dev)
> -{
> - int err;
> -
> - err = gpio_request(SPITZ_GPIO_USB_HOST, "USB_HOST");
> - if (err)
> - return err;
> -
> - /* Only Port 2 is connected, setup USB Port 2 Output Control Register */
> - UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
> -
> - return gpio_direction_output(SPITZ_GPIO_USB_HOST, 1);
> -}
> -
> -static void spitz_ohci_exit(struct device *dev)
> -{
> - gpio_free(SPITZ_GPIO_USB_HOST);
> -}
> -
> -static struct pxaohci_platform_data spitz_ohci_platform_data = {
> - .port_mode = PMM_NPS_MODE,
> - .init = spitz_ohci_init,
> - .exit = spitz_ohci_exit,
> - .flags = ENABLE_PORT_ALL | NO_OC_PROTECTION,
> - .power_budget = 150,
> -};
> -
> -static void __init spitz_uhc_init(void)
> -{
> - pxa_set_ohci_info(&spitz_ohci_platform_data);
> -}
> -#else
> -static inline void spitz_uhc_init(void) {}
> -#endif
> -
> -/******************************************************************************
> - * Framebuffer
> - ******************************************************************************/
> -#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
> -static struct pxafb_mode_info spitz_pxafb_modes[] = {
> - {
> - .pixclock = 19231,
> - .xres = 480,
> - .yres = 640,
> - .bpp = 16,
> - .hsync_len = 40,
> - .left_margin = 46,
> - .right_margin = 125,
> - .vsync_len = 3,
> - .upper_margin = 1,
> - .lower_margin = 0,
> - .sync = 0,
> - }, {
> - .pixclock = 134617,
> - .xres = 240,
> - .yres = 320,
> - .bpp = 16,
> - .hsync_len = 20,
> - .left_margin = 20,
> - .right_margin = 46,
> - .vsync_len = 2,
> - .upper_margin = 1,
> - .lower_margin = 0,
> - .sync = 0,
> - },
> -};
> -
> -static struct pxafb_mach_info spitz_pxafb_info = {
> - .modes = spitz_pxafb_modes,
> - .num_modes = ARRAY_SIZE(spitz_pxafb_modes),
> - .fixed_modes = 1,
> - .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_ALTERNATE_MAPPING,
> -};
> -
> -static void __init spitz_lcd_init(void)
> -{
> - pxa_set_fb_info(NULL, &spitz_pxafb_info);
> -}
> -#else
> -static inline void spitz_lcd_init(void) {}
> -#endif
> -
> -/******************************************************************************
> - * NAND Flash
> - ******************************************************************************/
> -#if defined(CONFIG_MTD_NAND_SHARPSL) || defined(CONFIG_MTD_NAND_SHARPSL_MODULE)
> -static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
> -
> -static struct nand_bbt_descr spitz_nand_bbt = {
> - .options = 0,
> - .offs = 4,
> - .len = 2,
> - .pattern = scan_ff_pattern
> -};
> -
> -static int akita_ooblayout_ecc(struct mtd_info *mtd, int section,
> - struct mtd_oob_region *oobregion)
> -{
> - if (section > 12)
> - return -ERANGE;
> -
> - switch (section % 3) {
> - case 0:
> - oobregion->offset = 5;
> - oobregion->length = 1;
> - break;
> -
> - case 1:
> - oobregion->offset = 1;
> - oobregion->length = 3;
> - break;
> -
> - case 2:
> - oobregion->offset = 6;
> - oobregion->length = 2;
> - break;
> - }
> -
> - oobregion->offset += (section / 3) * 0x10;
> -
> - return 0;
> -}
> -
> -static int akita_ooblayout_free(struct mtd_info *mtd, int section,
> - struct mtd_oob_region *oobregion)
> -{
> - if (section)
> - return -ERANGE;
> -
> - oobregion->offset = 8;
> - oobregion->length = 9;
> -
> - return 0;
> -}
> -
> -static const struct mtd_ooblayout_ops akita_ooblayout_ops = {
> - .ecc = akita_ooblayout_ecc,
> - .free = akita_ooblayout_free,
> -};
> -
> -static const char * const probes[] = {
> - "cmdlinepart",
> - "ofpart",
> - "sharpslpart",
> - NULL,
> -};
> -
> -static struct sharpsl_nand_platform_data spitz_nand_pdata = {
> - .badblock_pattern = &spitz_nand_bbt,
> - .part_parsers = probes,
> -};
> -
> -static struct resource spitz_nand_resources[] = {
> - {
> - .start = PXA_CS3_PHYS,
> - .end = PXA_CS3_PHYS + SZ_4K - 1,
> - .flags = IORESOURCE_MEM,
> - },
> -};
> -
> -static struct platform_device spitz_nand_device = {
> - .name = "sharpsl-nand",
> - .id = -1,
> - .resource = spitz_nand_resources,
> - .num_resources = ARRAY_SIZE(spitz_nand_resources),
> - .dev = {
> - .platform_data = &spitz_nand_pdata,
> - }
> -};
> -
> -static void __init spitz_nand_init(void)
> -{
> - if (machine_is_akita() || machine_is_borzoi()) {
> - spitz_nand_bbt.len = 1;
> - spitz_nand_pdata.ecc_layout = &akita_ooblayout_ops;
> - }
> -
> - platform_device_register(&spitz_nand_device);
> -}
> -#else
> -static inline void spitz_nand_init(void) {}
> -#endif
> -
> -/******************************************************************************
> - * NOR Flash
> - ******************************************************************************/
> -#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
> -static struct mtd_partition spitz_rom_parts[] = {
> - {
> - .name ="Boot PROM Filesystem",
> - .offset = 0x00140000,
> - .size = MTDPART_SIZ_FULL,
> - },
> -};
> -
> -static struct physmap_flash_data spitz_rom_data = {
> - .width = 2,
> - .nr_parts = ARRAY_SIZE(spitz_rom_parts),
> - .parts = spitz_rom_parts,
> -};
> -
> -static struct resource spitz_rom_resources[] = {
> - {
> - .start = PXA_CS0_PHYS,
> - .end = PXA_CS0_PHYS + SZ_8M - 1,
> - .flags = IORESOURCE_MEM,
> - },
> -};
> -
> -static struct platform_device spitz_rom_device = {
> - .name = "physmap-flash",
> - .id = -1,
> - .resource = spitz_rom_resources,
> - .num_resources = ARRAY_SIZE(spitz_rom_resources),
> - .dev = {
> - .platform_data = &spitz_rom_data,
> - },
> -};
> -
> -static void __init spitz_nor_init(void)
> -{
> - platform_device_register(&spitz_rom_device);
> -}
> -#else
> -static inline void spitz_nor_init(void) {}
> -#endif
> -
> -/******************************************************************************
> - * I2C devices
> - ******************************************************************************/
> -#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
> -static struct pca953x_platform_data akita_pca953x_pdata = {
> - .gpio_base = AKITA_IOEXP_GPIO_BASE,
> -};
> -
> -static struct i2c_board_info spitz_i2c_devs[] = {
> - {
> - .type = "wm8750",
> - .addr = 0x1b,
> - }, {
> - .type = "max7310",
> - .addr = 0x18,
> - .platform_data = &akita_pca953x_pdata,
> - .swnode = &akita_max7310_gpiochip_node,
> - },
> -};
> -
> -static struct regulator_consumer_supply isl6271a_consumers[] = {
> - REGULATOR_SUPPLY("vcc_core", NULL),
> -};
> -
> -static struct regulator_init_data isl6271a_info[] = {
> - {
> - .constraints = {
> - .name = "vcc_core range",
> - .min_uV = 850000,
> - .max_uV = 1600000,
> - .always_on = 1,
> - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> - },
> - .consumer_supplies = isl6271a_consumers,
> - .num_consumer_supplies = ARRAY_SIZE(isl6271a_consumers),
> - }
> -};
> -
> -static struct i2c_board_info spitz_pi2c_devs[] = {
> - {
> - .type = "isl6271a",
> - .addr = 0x0c,
> - .platform_data = &isl6271a_info,
> - },
> -};
> -
> -static void __init spitz_i2c_init(void)
> -{
> - int size = ARRAY_SIZE(spitz_i2c_devs);
> -
> - /* Only Akita has the max7310 chip */
> - if (!machine_is_akita())
> - size--;
> -
> - pxa_set_i2c_info(NULL);
> - pxa27x_set_i2c_power_info(NULL);
> - i2c_register_board_info(0, spitz_i2c_devs, size);
> - i2c_register_board_info(1, ARRAY_AND_SIZE(spitz_pi2c_devs));
> -}
> -#else
> -static inline void spitz_i2c_init(void) {}
> -#endif
> -
> -static const struct property_entry spitz_audio_props[] = {
> - PROPERTY_ENTRY_GPIO("mute-l-gpios", &spitz_scoop_1_gpiochip_node, 3,
> - GPIO_ACTIVE_HIGH),
> - PROPERTY_ENTRY_GPIO("mute-r-gpios", &spitz_scoop_1_gpiochip_node, 4,
> - GPIO_ACTIVE_HIGH),
> - PROPERTY_ENTRY_GPIO("mic-gpios", &spitz_scoop_2_gpiochip_node, 8,
> - GPIO_ACTIVE_HIGH),
> - { }
> -};
> -
> -static const struct property_entry akita_audio_props[] = {
> - PROPERTY_ENTRY_GPIO("mute-l-gpios", &spitz_scoop_1_gpiochip_node, 3,
> - GPIO_ACTIVE_HIGH),
> - PROPERTY_ENTRY_GPIO("mute-r-gpios", &spitz_scoop_1_gpiochip_node, 4,
> - GPIO_ACTIVE_HIGH),
> - PROPERTY_ENTRY_GPIO("mic-gpios", &akita_max7310_gpiochip_node, 2,
> - GPIO_ACTIVE_HIGH),
> - { }
> -};
> -
> -/******************************************************************************
> - * Audio devices
> - ******************************************************************************/
> -static inline void spitz_audio_init(void)
> -{
> - struct platform_device_info audio_info = {
> - .name = "spitz-audio",
> - .id = PLATFORM_DEVID_NONE,
> - .properties = machine_is_akita() ?
> - akita_audio_props : spitz_audio_props,
> - };
> -
> - platform_device_register_full(&audio_info);
> -}
> -
> -/******************************************************************************
> - * Machine init
> - ******************************************************************************/
> -static void spitz_poweroff(void)
> -{
> - pxa_restart(REBOOT_GPIO, NULL);
> -}
> -
> -static void spitz_restart(enum reboot_mode mode, const char *cmd)
> -{
> - uint32_t msc0 = __raw_readl(MSC0);
> - /* Bootloader magic for a reboot */
> - if ((msc0 & 0xffff0000) == 0x7ff00000)
> - __raw_writel((msc0 & 0xffff) | 0x7ee00000, MSC0);
> -
> - spitz_poweroff();
> -}
> -
> -static void __init spitz_init(void)
> -{
> - software_node_register(&spitz_scoop_1_gpiochip_node);
> - if (machine_is_akita())
> - software_node_register(&akita_max7310_gpiochip_node);
> - else
> - software_node_register(&spitz_scoop_2_gpiochip_node);
> -
> - init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
> - register_platform_power_off(spitz_poweroff);
> -
> - PMCR = 0x00;
> -
> - /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
> - PCFR |= PCFR_OPDE;
> -
> - pxa2xx_mfp_config(ARRAY_AND_SIZE(spitz_pin_config));
> -
> - pxa_set_ffuart_info(NULL);
> - pxa_set_btuart_info(NULL);
> - pxa_set_stuart_info(NULL);
> -
> - spitz_spi_init();
> - spitz_scoop_init();
> - spitz_mkp_init();
> - spitz_keys_init();
> - spitz_leds_init();
> - spitz_mmc_init();
> - spitz_pcmcia_init();
> - spitz_uhc_init();
> - spitz_lcd_init();
> - spitz_nor_init();
> - spitz_nand_init();
> - spitz_i2c_init();
> - spitz_audio_init();
> -
> - regulator_has_full_constraints();
> -}
> -
> -static void __init spitz_fixup(struct tag *tags, char **cmdline)
> -{
> - sharpsl_save_param();
> - memblock_add(0xa0000000, SZ_64M);
> -}
> -
> -#ifdef CONFIG_MACH_SPITZ
> -MACHINE_START(SPITZ, "SHARP Spitz")
> - .fixup = spitz_fixup,
> - .map_io = pxa27x_map_io,
> - .nr_irqs = PXA_NR_IRQS,
> - .init_irq = pxa27x_init_irq,
> - .init_machine = spitz_init,
> - .init_time = pxa_timer_init,
> - .restart = spitz_restart,
> -MACHINE_END
> -#endif
> -
> -#ifdef CONFIG_MACH_BORZOI
> -MACHINE_START(BORZOI, "SHARP Borzoi")
> - .fixup = spitz_fixup,
> - .map_io = pxa27x_map_io,
> - .nr_irqs = PXA_NR_IRQS,
> - .init_irq = pxa27x_init_irq,
> - .init_machine = spitz_init,
> - .init_time = pxa_timer_init,
> - .restart = spitz_restart,
> -MACHINE_END
> -#endif
> -
> -#ifdef CONFIG_MACH_AKITA
> -MACHINE_START(AKITA, "SHARP Akita")
> - .fixup = spitz_fixup,
> - .map_io = pxa27x_map_io,
> - .nr_irqs = PXA_NR_IRQS,
> - .init_irq = pxa27x_init_irq,
> - .init_machine = spitz_init,
> - .init_time = pxa_timer_init,
> - .restart = spitz_restart,
> -MACHINE_END
> -#endif
> diff --git a/arch/arm/mach-pxa/spitz.h b/arch/arm/mach-pxa/spitz.h
> deleted file mode 100644
> index 04828d8918aa..000000000000
> --- a/arch/arm/mach-pxa/spitz.h
> +++ /dev/null
> @@ -1,185 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * Hardware specific definitions for SL-Cx000 series of PDAs
> - *
> - * Copyright (c) 2005 Alexander Wykes
> - * Copyright (c) 2005 Richard Purdie
> - *
> - * Based on Sharp's 2.4 kernel patches
> - */
> -#ifndef __ASM_ARCH_SPITZ_H
> -#define __ASM_ARCH_SPITZ_H 1
> -#endif
> -
> -#include "irqs.h" /* PXA_NR_BUILTIN_GPIO, PXA_GPIO_TO_IRQ */
> -#include <linux/fb.h>
> -
> -/* Spitz/Akita GPIOs */
> -
> -#define SPITZ_GPIO_KEY_INT (0) /* Key Interrupt */
> -#define SPITZ_GPIO_RESET (1)
> -#define SPITZ_GPIO_nSD_DETECT (9)
> -#define SPITZ_GPIO_TP_INT (11) /* Touch Panel interrupt */
> -#define SPITZ_GPIO_AK_INT (13) /* Remote Control */
> -#define SPITZ_GPIO_ADS7846_CS (14)
> -#define SPITZ_GPIO_SYNC (16)
> -#define SPITZ_GPIO_MAX1111_CS (20)
> -#define SPITZ_GPIO_FATAL_BAT (21)
> -#define SPITZ_GPIO_HSYNC (22)
> -#define SPITZ_GPIO_nSD_CLK (32)
> -#define SPITZ_GPIO_USB_DEVICE (35)
> -#define SPITZ_GPIO_USB_HOST (37)
> -#define SPITZ_GPIO_USB_CONNECT (41)
> -#define SPITZ_GPIO_LCDCON_CS (53)
> -#define SPITZ_GPIO_nPCE (54)
> -#define SPITZ_GPIO_nSD_WP (81)
> -#define SPITZ_GPIO_ON_RESET (89)
> -#define SPITZ_GPIO_BAT_COVER (90)
> -#define SPITZ_GPIO_CF_CD (94)
> -#define SPITZ_GPIO_ON_KEY (95)
> -#define SPITZ_GPIO_SWA (97)
> -#define SPITZ_GPIO_SWB (96)
> -#define SPITZ_GPIO_CHRG_FULL (101)
> -#define SPITZ_GPIO_CO (101)
> -#define SPITZ_GPIO_CF_IRQ (105)
> -#define SPITZ_GPIO_AC_IN (115)
> -#define SPITZ_GPIO_HP_IN (116)
> -
> -/* Spitz Only GPIOs */
> -
> -#define SPITZ_GPIO_CF2_IRQ (106) /* CF slot1 Ready */
> -#define SPITZ_GPIO_CF2_CD (93)
> -
> -
> -/* Spitz/Akita Keyboard Definitions */
> -
> -#define SPITZ_KEY_STROBE_NUM (11)
> -#define SPITZ_KEY_SENSE_NUM (7)
> -#define SPITZ_GPIO_G0_STROBE_BIT 0x0f800000
> -#define SPITZ_GPIO_G1_STROBE_BIT 0x00100000
> -#define SPITZ_GPIO_G2_STROBE_BIT 0x01000000
> -#define SPITZ_GPIO_G3_STROBE_BIT 0x00041880
> -#define SPITZ_GPIO_G0_SENSE_BIT 0x00021000
> -#define SPITZ_GPIO_G1_SENSE_BIT 0x000000d4
> -#define SPITZ_GPIO_G2_SENSE_BIT 0x08000000
> -#define SPITZ_GPIO_G3_SENSE_BIT 0x00000000
> -
> -#define SPITZ_GPIO_KEY_STROBE0 88
> -#define SPITZ_GPIO_KEY_STROBE1 23
> -#define SPITZ_GPIO_KEY_STROBE2 24
> -#define SPITZ_GPIO_KEY_STROBE3 25
> -#define SPITZ_GPIO_KEY_STROBE4 26
> -#define SPITZ_GPIO_KEY_STROBE5 27
> -#define SPITZ_GPIO_KEY_STROBE6 52
> -#define SPITZ_GPIO_KEY_STROBE7 103
> -#define SPITZ_GPIO_KEY_STROBE8 107
> -#define SPITZ_GPIO_KEY_STROBE9 108
> -#define SPITZ_GPIO_KEY_STROBE10 114
> -
> -#define SPITZ_GPIO_KEY_SENSE0 12
> -#define SPITZ_GPIO_KEY_SENSE1 17
> -#define SPITZ_GPIO_KEY_SENSE2 91
> -#define SPITZ_GPIO_KEY_SENSE3 34
> -#define SPITZ_GPIO_KEY_SENSE4 36
> -#define SPITZ_GPIO_KEY_SENSE5 38
> -#define SPITZ_GPIO_KEY_SENSE6 39
> -
> -
> -/* Spitz Scoop Device (No. 1) GPIOs */
> -/* Suspend States in comments */
> -#define SPITZ_SCP_LED_GREEN SCOOP_GPCR_PA11 /* Keep */
> -#define SPITZ_SCP_JK_B SCOOP_GPCR_PA12 /* Keep */
> -#define SPITZ_SCP_CHRG_ON SCOOP_GPCR_PA13 /* Keep */
> -#define SPITZ_SCP_MUTE_L SCOOP_GPCR_PA14 /* Low */
> -#define SPITZ_SCP_MUTE_R SCOOP_GPCR_PA15 /* Low */
> -#define SPITZ_SCP_CF_POWER SCOOP_GPCR_PA16 /* Keep */
> -#define SPITZ_SCP_LED_ORANGE SCOOP_GPCR_PA17 /* Keep */
> -#define SPITZ_SCP_JK_A SCOOP_GPCR_PA18 /* Low */
> -#define SPITZ_SCP_ADC_TEMP_ON SCOOP_GPCR_PA19 /* Low */
> -
> -#define SPITZ_SCP_IO_DIR (SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \
> - SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | \
> - SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
> -#define SPITZ_SCP_IO_OUT (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R)
> -#define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
> -#define SPITZ_SCP_SUS_SET 0
> -
> -#define SPITZ_SCP_GPIO_BASE (PXA_NR_BUILTIN_GPIO)
> -#define SPITZ_GPIO_LED_GREEN (SPITZ_SCP_GPIO_BASE + 0)
> -#define SPITZ_GPIO_JK_B (SPITZ_SCP_GPIO_BASE + 1)
> -#define SPITZ_GPIO_CHRG_ON (SPITZ_SCP_GPIO_BASE + 2)
> -#define SPITZ_GPIO_MUTE_L (SPITZ_SCP_GPIO_BASE + 3)
> -#define SPITZ_GPIO_MUTE_R (SPITZ_SCP_GPIO_BASE + 4)
> -#define SPITZ_GPIO_CF_POWER (SPITZ_SCP_GPIO_BASE + 5)
> -#define SPITZ_GPIO_LED_ORANGE (SPITZ_SCP_GPIO_BASE + 6)
> -#define SPITZ_GPIO_JK_A (SPITZ_SCP_GPIO_BASE + 7)
> -#define SPITZ_GPIO_ADC_TEMP_ON (SPITZ_SCP_GPIO_BASE + 8)
> -
> -/* Spitz Scoop Device (No. 2) GPIOs */
> -/* Suspend States in comments */
> -#define SPITZ_SCP2_IR_ON SCOOP_GPCR_PA11 /* High */
> -#define SPITZ_SCP2_AKIN_PULLUP SCOOP_GPCR_PA12 /* Keep */
> -#define SPITZ_SCP2_RESERVED_1 SCOOP_GPCR_PA13 /* High */
> -#define SPITZ_SCP2_RESERVED_2 SCOOP_GPCR_PA14 /* Low */
> -#define SPITZ_SCP2_RESERVED_3 SCOOP_GPCR_PA15 /* Low */
> -#define SPITZ_SCP2_RESERVED_4 SCOOP_GPCR_PA16 /* Low */
> -#define SPITZ_SCP2_BACKLIGHT_CONT SCOOP_GPCR_PA17 /* Low */
> -#define SPITZ_SCP2_BACKLIGHT_ON SCOOP_GPCR_PA18 /* Low */
> -#define SPITZ_SCP2_MIC_BIAS SCOOP_GPCR_PA19 /* Low */
> -
> -#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \
> - SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
> - SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
> -
> -#define SPITZ_SCP2_IO_OUT (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1)
> -#define SPITZ_SCP2_SUS_CLR (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
> - SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
> -#define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1)
> -
> -#define SPITZ_SCP2_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12)
> -#define SPITZ_GPIO_IR_ON (SPITZ_SCP2_GPIO_BASE + 0)
> -#define SPITZ_GPIO_AKIN_PULLUP (SPITZ_SCP2_GPIO_BASE + 1)
> -#define SPITZ_GPIO_RESERVED_1 (SPITZ_SCP2_GPIO_BASE + 2)
> -#define SPITZ_GPIO_RESERVED_2 (SPITZ_SCP2_GPIO_BASE + 3)
> -#define SPITZ_GPIO_RESERVED_3 (SPITZ_SCP2_GPIO_BASE + 4)
> -#define SPITZ_GPIO_RESERVED_4 (SPITZ_SCP2_GPIO_BASE + 5)
> -#define SPITZ_GPIO_BACKLIGHT_CONT (SPITZ_SCP2_GPIO_BASE + 6)
> -#define SPITZ_GPIO_BACKLIGHT_ON (SPITZ_SCP2_GPIO_BASE + 7)
> -#define SPITZ_GPIO_MIC_BIAS (SPITZ_SCP2_GPIO_BASE + 8)
> -
> -/* Akita IO Expander GPIOs */
> -#define AKITA_IOEXP_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12)
> -#define AKITA_GPIO_RESERVED_0 (AKITA_IOEXP_GPIO_BASE + 0)
> -#define AKITA_GPIO_RESERVED_1 (AKITA_IOEXP_GPIO_BASE + 1)
> -#define AKITA_GPIO_MIC_BIAS (AKITA_IOEXP_GPIO_BASE + 2)
> -#define AKITA_GPIO_BACKLIGHT_ON (AKITA_IOEXP_GPIO_BASE + 3)
> -#define AKITA_GPIO_BACKLIGHT_CONT (AKITA_IOEXP_GPIO_BASE + 4)
> -#define AKITA_GPIO_AKIN_PULLUP (AKITA_IOEXP_GPIO_BASE + 5)
> -#define AKITA_GPIO_IR_ON (AKITA_IOEXP_GPIO_BASE + 6)
> -#define AKITA_GPIO_RESERVED_7 (AKITA_IOEXP_GPIO_BASE + 7)
> -
> -/* Spitz IRQ Definitions */
> -
> -#define SPITZ_IRQ_GPIO_KEY_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_KEY_INT)
> -#define SPITZ_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(SPITZ_GPIO_AC_IN)
> -#define SPITZ_IRQ_GPIO_AK_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_AK_INT)
> -#define SPITZ_IRQ_GPIO_HP_IN PXA_GPIO_TO_IRQ(SPITZ_GPIO_HP_IN)
> -#define SPITZ_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_TP_INT)
> -#define SPITZ_IRQ_GPIO_SYNC PXA_GPIO_TO_IRQ(SPITZ_GPIO_SYNC)
> -#define SPITZ_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(SPITZ_GPIO_ON_KEY)
> -#define SPITZ_IRQ_GPIO_SWA PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWA)
> -#define SPITZ_IRQ_GPIO_SWB PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWB)
> -#define SPITZ_IRQ_GPIO_BAT_COVER PXA_GPIO_TO_IRQ(SPITZ_GPIO_BAT_COVER)
> -#define SPITZ_IRQ_GPIO_FATAL_BAT PXA_GPIO_TO_IRQ(SPITZ_GPIO_FATAL_BAT)
> -#define SPITZ_IRQ_GPIO_CO PXA_GPIO_TO_IRQ(SPITZ_GPIO_CO)
> -#define SPITZ_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_IRQ)
> -#define SPITZ_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_CD)
> -#define SPITZ_IRQ_GPIO_CF2_IRQ PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF2_IRQ)
> -#define SPITZ_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_INT)
> -#define SPITZ_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_DETECT)
> -
> -/*
> - * Shared data structures
> - */
> -extern struct platform_device spitzssp_device;
> -extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
> diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
> deleted file mode 100644
> index 806847c36549..000000000000
> --- a/arch/arm/mach-pxa/spitz_pm.c
> +++ /dev/null
> @@ -1,257 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Battery and Power Management code for the Sharp SL-Cxx00
> - *
> - * Copyright (c) 2005 Richard Purdie
> - */
> -
> -#include <linux/module.h>
> -#include <linux/stat.h>
> -#include <linux/init.h>
> -#include <linux/kernel.h>
> -#include <linux/delay.h>
> -#include <linux/gpio/legacy.h>
> -#include <linux/gpio-pxa.h>
> -#include <linux/interrupt.h>
> -#include <linux/platform_device.h>
> -#include <linux/apm-emulation.h>
> -#include <linux/spi/corgi_lcd.h>
> -
> -#include <asm/irq.h>
> -#include <asm/mach-types.h>
> -
> -#include "spitz.h"
> -#include "pxa27x.h"
> -#include "sharpsl_pm.h"
> -
> -#include "generic.h"
> -
> -#define SHARPSL_CHARGE_ON_VOLT 0x99 /* 2.9V */
> -#define SHARPSL_CHARGE_ON_TEMP 0xe0 /* 2.9V */
> -#define SHARPSL_CHARGE_ON_ACIN_HIGH 0x9b /* 6V */
> -#define SHARPSL_CHARGE_ON_ACIN_LOW 0x34 /* 2V */
> -#define SHARPSL_FATAL_ACIN_VOLT 182 /* 3.45V */
> -#define SHARPSL_FATAL_NOACIN_VOLT 170 /* 3.40V */
> -
> -static int spitz_last_ac_status;
> -
> -static void spitz_charger_init(void)
> -{
> - gpio_request(SPITZ_GPIO_KEY_INT, "Keyboard Interrupt");
> - gpio_direction_input(SPITZ_GPIO_KEY_INT);
> - gpio_request(SPITZ_GPIO_SYNC, "Sync");
> - gpio_direction_input(SPITZ_GPIO_SYNC);
> - gpio_request(SPITZ_GPIO_AC_IN, "Charger Detection");
> - gpio_direction_input(SPITZ_GPIO_AC_IN);
> - gpio_request(SPITZ_GPIO_ADC_TEMP_ON, "ADC Temp On");
> - gpio_direction_output(SPITZ_GPIO_ADC_TEMP_ON, 0);
> - gpio_request(SPITZ_GPIO_JK_B, "JK B");
> - gpio_direction_output(SPITZ_GPIO_JK_B, 0);
> - gpio_request(SPITZ_GPIO_CHRG_ON, "Charger On");
> - gpio_direction_output(SPITZ_GPIO_CHRG_ON, 0);
> -}
> -
> -static void spitz_measure_temp(int on)
> -{
> - gpio_set_value(SPITZ_GPIO_ADC_TEMP_ON, on);
> -}
> -
> -static void spitz_charge(int on)
> -{
> - if (on) {
> - if (sharpsl_pm.flags & SHARPSL_SUSPENDED) {
> - gpio_set_value(SPITZ_GPIO_JK_B, 1);
> - gpio_set_value(SPITZ_GPIO_CHRG_ON, 0);
> - } else {
> - gpio_set_value(SPITZ_GPIO_JK_B, 0);
> - gpio_set_value(SPITZ_GPIO_CHRG_ON, 0);
> - }
> - } else {
> - gpio_set_value(SPITZ_GPIO_JK_B, 0);
> - gpio_set_value(SPITZ_GPIO_CHRG_ON, 1);
> - }
> -}
> -
> -static void spitz_discharge(int on)
> -{
> - gpio_set_value(SPITZ_GPIO_JK_A, on);
> -}
> -
> -/* HACK - For unknown reasons, accurate voltage readings are only made with a load
> - on the power bus which the green led on spitz provides */
> -static void spitz_discharge1(int on)
> -{
> - gpio_set_value(SPITZ_GPIO_LED_GREEN, on);
> -}
> -
> -static unsigned long gpio18_config = GPIO18_GPIO;
> -
> -static void spitz_presuspend(void)
> -{
> - spitz_last_ac_status = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN);
> -
> - /* GPIO Sleep Register */
> - PGSR0 = 0x00144018;
> - PGSR1 = 0x00EF0000;
> - if (machine_is_akita()) {
> - PGSR2 = 0x2121C000;
> - PGSR3 = 0x00600400;
> - } else {
> - PGSR2 = 0x0121C000;
> - PGSR3 = 0x00600000;
> - }
> -
> - PGSR0 &= ~SPITZ_GPIO_G0_STROBE_BIT;
> - PGSR1 &= ~SPITZ_GPIO_G1_STROBE_BIT;
> - PGSR2 &= ~SPITZ_GPIO_G2_STROBE_BIT;
> - PGSR3 &= ~SPITZ_GPIO_G3_STROBE_BIT;
> - PGSR2 |= GPIO_bit(SPITZ_GPIO_KEY_STROBE0);
> -
> - pxa2xx_mfp_config(&gpio18_config, 1);
> - gpio_request_one(18, GPIOF_OUT_INIT_HIGH, "Unknown");
> - gpio_free(18);
> -
> - PRER = GPIO_bit(SPITZ_GPIO_KEY_INT);
> - PFER = GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET);
> - PWER = GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET) | PWER_RTC;
> - PKWR = GPIO_bit(SPITZ_GPIO_SYNC) | GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET);
> - PKSR = 0xffffffff; /* clear */
> -
> - /* nRESET_OUT Disable */
> - PSLR |= PSLR_SL_ROD;
> -
> - /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
> - PCFR = PCFR_GPR_EN | PCFR_OPDE;
> -}
> -
> -static void spitz_postsuspend(void)
> -{
> -}
> -
> -static int spitz_should_wakeup(unsigned int resume_on_alarm)
> -{
> - int is_resume = 0;
> - int acin = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN);
> -
> - if (spitz_last_ac_status != acin) {
> - if (acin) {
> - /* charge on */
> - sharpsl_pm.flags |= SHARPSL_DO_OFFLINE_CHRG;
> - dev_dbg(sharpsl_pm.dev, "AC Inserted\n");
> - } else {
> - /* charge off */
> - dev_dbg(sharpsl_pm.dev, "AC Removed\n");
> - sharpsl_pm_led(SHARPSL_LED_OFF);
> - sharpsl_pm.machinfo->charge(0);
> - sharpsl_pm.charge_mode = CHRG_OFF;
> - }
> - spitz_last_ac_status = acin;
> - /* Return to suspend as this must be what we were woken for */
> - return 0;
> - }
> -
> - if (PEDR & GPIO_bit(SPITZ_GPIO_KEY_INT))
> - is_resume |= GPIO_bit(SPITZ_GPIO_KEY_INT);
> -
> - if (PKSR & GPIO_bit(SPITZ_GPIO_SYNC))
> - is_resume |= GPIO_bit(SPITZ_GPIO_SYNC);
> -
> - if (resume_on_alarm && (PEDR & PWER_RTC))
> - is_resume |= PWER_RTC;
> -
> - dev_dbg(sharpsl_pm.dev, "is_resume: %x\n", is_resume);
> - return is_resume;
> -}
> -
> -static bool spitz_charger_wakeup(void)
> -{
> - return !gpio_get_value(SPITZ_GPIO_KEY_INT) ||
> - gpio_get_value(SPITZ_GPIO_SYNC);
> -}
> -
> -static unsigned long spitzpm_read_devdata(int type)
> -{
> - switch (type) {
> - case SHARPSL_STATUS_ACIN:
> - return !gpio_get_value(SPITZ_GPIO_AC_IN);
> - case SHARPSL_STATUS_LOCK:
> - return gpio_get_value(sharpsl_pm.machinfo->gpio_batlock);
> - case SHARPSL_STATUS_CHRGFULL:
> - return gpio_get_value(sharpsl_pm.machinfo->gpio_batfull);
> - case SHARPSL_STATUS_FATAL:
> - return gpio_get_value(sharpsl_pm.machinfo->gpio_fatal);
> - case SHARPSL_ACIN_VOLT:
> - return sharpsl_pm_pxa_read_max1111(MAX1111_ACIN_VOLT);
> - case SHARPSL_BATT_TEMP:
> - return sharpsl_pm_pxa_read_max1111(MAX1111_BATT_TEMP);
> - case SHARPSL_BATT_VOLT:
> - default:
> - return sharpsl_pm_pxa_read_max1111(MAX1111_BATT_VOLT);
> - }
> -}
> -
> -struct sharpsl_charger_machinfo spitz_pm_machinfo = {
> - .init = spitz_charger_init,
> - .exit = NULL,
> - .gpio_batlock = SPITZ_GPIO_BAT_COVER,
> - .gpio_acin = SPITZ_GPIO_AC_IN,
> - .gpio_batfull = SPITZ_GPIO_CHRG_FULL,
> - .batfull_irq = 1,
> - .gpio_fatal = SPITZ_GPIO_FATAL_BAT,
> - .discharge = spitz_discharge,
> - .discharge1 = spitz_discharge1,
> - .charge = spitz_charge,
> - .measure_temp = spitz_measure_temp,
> - .presuspend = spitz_presuspend,
> - .postsuspend = spitz_postsuspend,
> - .read_devdata = spitzpm_read_devdata,
> - .charger_wakeup = spitz_charger_wakeup,
> - .should_wakeup = spitz_should_wakeup,
> -#if defined(CONFIG_LCD_CORGI)
> - .backlight_limit = corgi_lcd_limit_intensity,
> -#endif
> - .charge_on_volt = SHARPSL_CHARGE_ON_VOLT,
> - .charge_on_temp = SHARPSL_CHARGE_ON_TEMP,
> - .charge_acin_high = SHARPSL_CHARGE_ON_ACIN_HIGH,
> - .charge_acin_low = SHARPSL_CHARGE_ON_ACIN_LOW,
> - .fatal_acin_volt = SHARPSL_FATAL_ACIN_VOLT,
> - .fatal_noacin_volt= SHARPSL_FATAL_NOACIN_VOLT,
> - .bat_levels = 40,
> - .bat_levels_noac = sharpsl_battery_levels_noac,
> - .bat_levels_acin = sharpsl_battery_levels_acin,
> - .status_high_acin = 188,
> - .status_low_acin = 178,
> - .status_high_noac = 185,
> - .status_low_noac = 175,
> -};
> -
> -static struct platform_device *spitzpm_device;
> -
> -static int spitzpm_init(void)
> -{
> - int ret;
> -
> - if (!machine_is_spitz() && !machine_is_akita()
> - && !machine_is_borzoi())
> - return -ENODEV;
> -
> - spitzpm_device = platform_device_alloc("sharpsl-pm", -1);
> - if (!spitzpm_device)
> - return -ENOMEM;
> -
> - spitzpm_device->dev.platform_data = &spitz_pm_machinfo;
> - ret = platform_device_add(spitzpm_device);
> -
> - if (ret)
> - platform_device_put(spitzpm_device);
> -
> - return ret;
> -}
> -
> -static void spitzpm_exit(void)
> -{
> - platform_device_unregister(spitzpm_device);
> -}
> -
> -module_init(spitzpm_init);
> -module_exit(spitzpm_exit);
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH 05/13] ARM: orion/dove/mv78xx0: remove all board files
2026-09-08 15:27 [PATCH 00/13] ARM: deprecated platform removal Arnd Bergmann
` (3 preceding siblings ...)
2026-09-08 15:27 ` [PATCH 04/13] ARM: remove legacy pxa board files Arnd Bergmann
@ 2026-09-08 15:27 ` Arnd Bergmann
2026-09-08 15:34 ` Mark Brown
` (5 more replies)
2026-09-08 15:27 ` [PATCH 06/13] ARM: omap2: remove omap24xx support Arnd Bergmann
` (8 subsequent siblings)
13 siblings, 6 replies; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 15:27 UTC (permalink / raw)
To: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Alexander Clouter,
Jeremy J. Peper, Damien Le Moal, Niklas Cassel, Ulf Hansson,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
Vinod Koul, Rafael J. Wysocki, Daniel Lezcano, Guenter Roeck,
Mark Brown, Bartosz Golaszewski, Thomas Weissschuh, linux-ide,
linux-mmc, linux-pci, linux-phy, linux-rtc, linux-pm,
linux-watchdog, linux-sound, linux-gpio
From: Arnd Bergmann <arnd@arndb.de>
The 'orion' platform is the predecessor to what linux now calls the
'mvebu' line of Marvell SoCs, and originally covered orion5x,
mv78xx0, kirkwood, dove and a few others that do not have any
upstream support at the moment.
Only a few board files remain here, these are the ones left
in 2022 board file purge because they had some level of support
in Debian or OpenWRT, mostly for commercial NAS or router boxes.
This distro support is now gone, and nobody has converted the
board files to devicetree, though the orion5x and dove platforms
also come with devicetree support for some other machines.
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Gregory Clement <gregory.clement@bootlin.com>
Cc: Alexander Clouter <alex@digriz.org.uk>
Cc: Jeremy J. Peper <jeremy@jeremypeper.com>
Cc: Damien Le Moal <dlemoal@kernel.org>
Cc: Niklas Cassel <cassel@kernel.org>
Cc: Ulf Hansson <ulfh@kernel.org>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: Daniel Lezcano <daniel.lezcano@kernel.org>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Mark Brown <broonie@kernel.org>
Cc: Linus Walleij <linusw@kernel.org>
Cc: Bartosz Golaszewski <brgl@kernel.org>
Cc: Thomas Weissschuh <thomas.weissschuh@linutronix.de>
Cc: linux-ide@vger.kernel.org
Cc: linux-mmc@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-phy@lists.infradead.org
Cc: linux-rtc@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: linux-watchdog@vger.kernel.org
Cc: linux-sound@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
MAINTAINERS | 2 -
arch/arm/Kconfig | 2 -
arch/arm/Kconfig.debug | 2 +-
arch/arm/Makefile | 2 -
arch/arm/configs/dove_defconfig | 134 ---
arch/arm/configs/mv78xx0_defconfig | 120 ---
arch/arm/mach-dove/Kconfig | 32 -
arch/arm/mach-dove/Makefile | 7 -
arch/arm/mach-dove/bridge-regs.h | 50 --
arch/arm/mach-dove/cm-a510.c | 94 --
arch/arm/mach-dove/common.c | 449 ----------
arch/arm/mach-dove/common.h | 46 -
arch/arm/mach-dove/dove.h | 185 ----
arch/arm/mach-dove/irq.c | 81 --
arch/arm/mach-dove/irqs.h | 89 --
arch/arm/mach-dove/mpp.c | 159 ----
arch/arm/mach-dove/mpp.h | 197 -----
arch/arm/mach-dove/pcie.c | 226 -----
arch/arm/mach-dove/pm.h | 58 --
arch/arm/mach-mv78xx0/Kconfig | 27 -
arch/arm/mach-mv78xx0/Makefile | 5 -
arch/arm/mach-mv78xx0/bridge-regs.h | 31 -
arch/arm/mach-mv78xx0/buffalo-wxl-setup.c | 183 ----
arch/arm/mach-mv78xx0/common.c | 444 ----------
arch/arm/mach-mv78xx0/common.h | 54 --
arch/arm/mach-mv78xx0/irq.c | 69 --
arch/arm/mach-mv78xx0/irqs.h | 87 --
arch/arm/mach-mv78xx0/mpp.c | 34 -
arch/arm/mach-mv78xx0/mpp.h | 337 -------
arch/arm/mach-mv78xx0/mv78xx0.h | 134 ---
arch/arm/mach-mv78xx0/pcie.c | 280 ------
arch/arm/mach-orion5x/Kconfig | 95 --
arch/arm/mach-orion5x/Makefile | 9 -
arch/arm/mach-orion5x/board-dt.c | 3 +-
arch/arm/mach-orion5x/common.c | 238 +----
arch/arm/mach-orion5x/common.h | 15 -
arch/arm/mach-orion5x/dns323-setup.c | 757 ----------------
arch/arm/mach-orion5x/kurobox_pro-setup.c | 407 ---------
arch/arm/mach-orion5x/mv2120-setup.c | 256 ------
arch/arm/mach-orion5x/net2big-setup.c | 444 ----------
arch/arm/mach-orion5x/pci.c | 1 -
.../arm/mach-orion5x/terastation_pro2-setup.c | 366 --------
arch/arm/mach-orion5x/ts209-setup.c | 331 -------
arch/arm/mach-orion5x/ts409-setup.c | 329 -------
arch/arm/mach-orion5x/ts78xx-fpga.h | 42 -
arch/arm/mach-orion5x/ts78xx-setup.c | 574 ------------
arch/arm/mach-orion5x/tsx09-common.c | 129 ---
arch/arm/mach-orion5x/tsx09-common.h | 21 -
arch/arm/mm/Kconfig | 2 +-
arch/arm/plat-orion/Makefile | 2 +-
arch/arm/plat-orion/common.c | 826 ------------------
arch/arm/plat-orion/include/plat/addr-map.h | 54 --
arch/arm/plat-orion/include/plat/common.h | 104 ---
arch/arm/plat-orion/include/plat/time.h | 20 -
arch/arm/plat-orion/pcie.c | 1 -
arch/arm/plat-orion/time.c | 238 -----
drivers/ata/Kconfig | 3 +-
drivers/mmc/host/Kconfig | 2 +-
drivers/pci/controller/Kconfig | 2 +-
drivers/phy/marvell/Kconfig | 2 +-
drivers/rtc/Kconfig | 2 +-
drivers/soc/Makefile | 1 -
drivers/thermal/Kconfig | 2 +-
drivers/watchdog/Kconfig | 2 +-
sound/soc/kirkwood/Kconfig | 2 +-
65 files changed, 14 insertions(+), 8888 deletions(-)
delete mode 100644 arch/arm/configs/dove_defconfig
delete mode 100644 arch/arm/configs/mv78xx0_defconfig
delete mode 100644 arch/arm/mach-dove/Kconfig
delete mode 100644 arch/arm/mach-dove/Makefile
delete mode 100644 arch/arm/mach-dove/bridge-regs.h
delete mode 100644 arch/arm/mach-dove/cm-a510.c
delete mode 100644 arch/arm/mach-dove/common.c
delete mode 100644 arch/arm/mach-dove/common.h
delete mode 100644 arch/arm/mach-dove/dove.h
delete mode 100644 arch/arm/mach-dove/irq.c
delete mode 100644 arch/arm/mach-dove/irqs.h
delete mode 100644 arch/arm/mach-dove/mpp.c
delete mode 100644 arch/arm/mach-dove/mpp.h
delete mode 100644 arch/arm/mach-dove/pcie.c
delete mode 100644 arch/arm/mach-dove/pm.h
delete mode 100644 arch/arm/mach-mv78xx0/Kconfig
delete mode 100644 arch/arm/mach-mv78xx0/Makefile
delete mode 100644 arch/arm/mach-mv78xx0/bridge-regs.h
delete mode 100644 arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
delete mode 100644 arch/arm/mach-mv78xx0/common.c
delete mode 100644 arch/arm/mach-mv78xx0/common.h
delete mode 100644 arch/arm/mach-mv78xx0/irq.c
delete mode 100644 arch/arm/mach-mv78xx0/irqs.h
delete mode 100644 arch/arm/mach-mv78xx0/mpp.c
delete mode 100644 arch/arm/mach-mv78xx0/mpp.h
delete mode 100644 arch/arm/mach-mv78xx0/mv78xx0.h
delete mode 100644 arch/arm/mach-mv78xx0/pcie.c
delete mode 100644 arch/arm/mach-orion5x/dns323-setup.c
delete mode 100644 arch/arm/mach-orion5x/kurobox_pro-setup.c
delete mode 100644 arch/arm/mach-orion5x/mv2120-setup.c
delete mode 100644 arch/arm/mach-orion5x/net2big-setup.c
delete mode 100644 arch/arm/mach-orion5x/terastation_pro2-setup.c
delete mode 100644 arch/arm/mach-orion5x/ts209-setup.c
delete mode 100644 arch/arm/mach-orion5x/ts409-setup.c
delete mode 100644 arch/arm/mach-orion5x/ts78xx-fpga.h
delete mode 100644 arch/arm/mach-orion5x/ts78xx-setup.c
delete mode 100644 arch/arm/mach-orion5x/tsx09-common.c
delete mode 100644 arch/arm/mach-orion5x/tsx09-common.h
delete mode 100644 arch/arm/plat-orion/common.c
delete mode 100644 arch/arm/plat-orion/include/plat/addr-map.h
delete mode 100644 arch/arm/plat-orion/include/plat/common.h
delete mode 100644 arch/arm/plat-orion/include/plat/time.h
delete mode 100644 arch/arm/plat-orion/time.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 6e8fe7640064..028db7ad15ad 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3080,8 +3080,6 @@ F: Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.yaml
F: Documentation/devicetree/bindings/soc/dove/
F: arch/arm/boot/dts/marvell/dove*
F: arch/arm/boot/dts/marvell/orion5x*
-F: arch/arm/mach-dove/
-F: arch/arm/mach-mv78xx0/
F: arch/arm/mach-orion5x/
F: arch/arm/plat-orion/
F: drivers/bus/mvebu-mbus.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5770deca136d..da29afce309f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -393,8 +393,6 @@ source "arch/arm/mach-mmp/Kconfig"
source "arch/arm/mach-mstar/Kconfig"
-source "arch/arm/mach-mv78xx0/Kconfig"
-
source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/mach-mxs/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 56c090840c5a..e2fc89055463 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -583,7 +583,7 @@ choice
config DEBUG_MVEBU_UART0_ALTERNATE
bool "Kernel low-level debugging messages via MVEBU UART0 (new bootloaders)"
- depends on ARCH_MVEBU || ARCH_DOVE || ARCH_MV78XX0 || ARCH_ORION5X
+ depends on ARCH_MVEBU || ARCH_ORION5X
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index f5bc9ad7f6f5..5421a3ec3825 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -179,7 +179,6 @@ machine-$(CONFIG_ARCH_BERLIN) += berlin
machine-$(CONFIG_ARCH_CLPS711X) += clps711x
machine-$(CONFIG_ARCH_DAVINCI) += davinci
machine-$(CONFIG_ARCH_DIGICOLOR) += digicolor
-machine-$(CONFIG_ARCH_DOVE) += dove
machine-$(CONFIG_ARCH_EXYNOS) += exynos
machine-$(CONFIG_ARCH_GEMINI) += gemini
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
@@ -190,7 +189,6 @@ machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MMP) += mmp
-machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_MXC) += imx
machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
deleted file mode 100644
index 917a864fec74..000000000000
--- a/arch/arm/configs/dove_defconfig
+++ /dev/null
@@ -1,134 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EXPERT=y
-# CONFIG_ARCH_MULTI_V6 is not set
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_DOVE=y
-CONFIG_MACH_CM_A510=y
-CONFIG_HIGHMEM=y
-CONFIG_ATAGS=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_VFP=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_PCI=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MVEBU=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=1
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_ATA=y
-CONFIG_SATA_MV=y
-CONFIG_NETDEVICES=y
-CONFIG_MV643XX_ETH=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_MOUSE_PS2 is not set
-# CONFIG_SERIO is not set
-CONFIG_LEGACY_PTY_COUNT=16
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MV64XXX=y
-CONFIG_SPI=y
-CONFIG_SPI_ORION=y
-# CONFIG_HWMON is not set
-CONFIG_THERMAL=y
-CONFIG_DOVE_THERMAL=y
-CONFIG_WATCHDOG=y
-CONFIG_ORION_WATCHDOG=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_DOVE=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_MV=y
-CONFIG_DMADEVICES=y
-CONFIG_MV_XOR=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=y
-CONFIG_NLS_UTF8=y
-CONFIG_TIMER_STATS=y
-CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_BLOWFISH=y
-CONFIG_CRYPTO_TEA=y
-CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_DEV_MARVELL_CESA=y
-CONFIG_PRINTK_TIME=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig
deleted file mode 100644
index e3cc8de7c1c2..000000000000
--- a/arch/arm/configs/mv78xx0_defconfig
+++ /dev/null
@@ -1,120 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_PROFILING=y
-CONFIG_ARCH_MULTI_V5=y
-# CONFIG_ARCH_MULTI_V6 is not set
-# CONFIG_ARCH_MULTI_V7 is not set
-CONFIG_ARCH_MV78XX0=y
-CONFIG_MACH_TERASTATION_WXL=y
-CONFIG_HIGHMEM=y
-CONFIG_ATAGS=y
-CONFIG_VFP=y
-CONFIG_KPROBES=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_NET_PKTGEN=m
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_NAND_ORION=y
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ATA=y
-CONFIG_SATA_MV=y
-CONFIG_NETDEVICES=y
-CONFIG_MII=y
-CONFIG_NET_PCI=y
-CONFIG_MV643XX_ETH=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_MARVELL_PHY=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_LEGACY_PTY_COUNT=16
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_SERIAL_8250_PCI is not set
-CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MV64XXX=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
-CONFIG_USB_PRINTER=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DATAFAB=y
-CONFIG_USB_STORAGE_FREECOM=y
-CONFIG_USB_STORAGE_SDDR09=y
-CONFIG_USB_STORAGE_SDDR55=y
-CONFIG_USB_STORAGE_JUMPSHOT=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_RTC_DRV_RS5C372=y
-CONFIG_RTC_DRV_M41T80=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=y
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_ECB=m
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_SCHEDSTATS=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
deleted file mode 100644
index f547120e223e..000000000000
--- a/arch/arm/mach-dove/Kconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menuconfig ARCH_DOVE
- bool "Marvell Dove (DEPRECATED)" if ARCH_MULTI_V7
- depends on ATAGS
- select CPU_PJ4
- select GPIOLIB
- select MVEBU_MBUS
- select PINCTRL
- select PINCTRL_DOVE
- select PLAT_ORION_LEGACY
- select PM_GENERIC_DOMAINS if PM
- select PCI_QUIRKS if PCI
- help
- Support for the Marvell Dove SoC 88AP510 using board files.
-
- Support for this machine will be removed in early 2027, unless
- there is a strong reason to keep it. Users should migrate to
- the devicetree-enabled version (CONFIG_MACH_DOVE) instead.
-
-if ARCH_DOVE
-
-config DOVE_LEGACY
- bool
-
-config MACH_CM_A510
- bool "CompuLab CM-A510 Board"
- select DOVE_LEGACY
- help
- Say 'Y' here if you want your kernel to support the
- CompuLab CM-A510 Board.
-
-endif
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
deleted file mode 100644
index 0d31390be069..000000000000
--- a/arch/arm/mach-dove/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-ccflags-y := -I$(srctree)/arch/arm/plat-orion/include
-
-obj-y += common.o
-obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o
-obj-$(CONFIG_PCI) += pcie.o
-obj-$(CONFIG_MACH_CM_A510) += cm-a510.o
diff --git a/arch/arm/mach-dove/bridge-regs.h b/arch/arm/mach-dove/bridge-regs.h
deleted file mode 100644
index 6fbc152d0950..000000000000
--- a/arch/arm/mach-dove/bridge-regs.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* Mbus-L to Mbus Bridge Registers */
-
-#ifndef __ASM_ARCH_BRIDGE_REGS_H
-#define __ASM_ARCH_BRIDGE_REGS_H
-
-#include "dove.h"
-
-#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000)
-
-#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
-#define CPU_CTRL_PCIE0_LINK 0x00000001
-#define CPU_RESET 0x00000002
-#define CPU_CTRL_PCIE1_LINK 0x00000008
-
-#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
-#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
-#define SOFT_RESET_OUT_EN 0x00000004
-
-#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
-#define SOFT_RESET 0x00000001
-
-#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
-#define BRIDGE_INT_TIMER1_CLR (~0x0004)
-
-#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
-#define IRQ_CAUSE_LOW_OFF 0x0000
-#define IRQ_MASK_LOW_OFF 0x0004
-#define FIQ_MASK_LOW_OFF 0x0008
-#define ENDPOINT_MASK_LOW_OFF 0x000c
-#define IRQ_CAUSE_HIGH_OFF 0x0010
-#define IRQ_MASK_HIGH_OFF 0x0014
-#define FIQ_MASK_HIGH_OFF 0x0018
-#define ENDPOINT_MASK_HIGH_OFF 0x001c
-#define PCIE_INTERRUPT_MASK_OFF 0x0020
-
-#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)
-#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)
-#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)
-#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)
-#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)
-#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
-#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
-
-#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c)
-
-#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
-#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
-
-#endif
diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
deleted file mode 100644
index beb532537c22..000000000000
--- a/arch/arm/mach-dove/cm-a510.c
+++ /dev/null
@@ -1,94 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-dove/cm-a510.c
- *
- * Copyright (C) 2010 CompuLab, Ltd.
- * Konstantin Sinyuk <kostyas@compulab.co.il>
- *
- * Based on Marvell DB-MV88AP510-BP Development Board Setup
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "dove.h"
-#include "common.h"
-
-static struct mv643xx_eth_platform_data cm_a510_ge00_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
-};
-
-static struct mv_sata_platform_data cm_a510_sata_data = {
- .n_ports = 1,
-};
-
-/*
- * SPI Devices:
- * SPI0: 1M Flash Winbond w25q32bv
- */
-static const struct flash_platform_data cm_a510_spi_flash_data = {
- .type = "w25q32bv",
-};
-
-static struct spi_board_info __initdata cm_a510_spi_flash_info[] = {
- {
- .modalias = "m25p80",
- .platform_data = &cm_a510_spi_flash_data,
- .irq = -1,
- .max_speed_hz = 20000000,
- .bus_num = 0,
- .chip_select = 0,
- },
-};
-
-static int __init cm_a510_pci_init(void)
-{
- if (machine_is_cm_a510())
- dove_pcie_init(1, 1);
-
- return 0;
-}
-
-subsys_initcall(cm_a510_pci_init);
-
-/* Board Init */
-static void __init cm_a510_init(void)
-{
- /*
- * Basic Dove setup. Needs to be called early.
- */
- dove_init();
-
- dove_ge00_init(&cm_a510_ge00_data);
- dove_ehci0_init();
- dove_ehci1_init();
- dove_sata_init(&cm_a510_sata_data);
- dove_sdio0_init();
- dove_sdio1_init();
- dove_spi0_init();
- dove_spi1_init();
- dove_uart0_init();
- dove_uart1_init();
- dove_i2c_init();
- spi_register_board_info(cm_a510_spi_flash_info,
- ARRAY_SIZE(cm_a510_spi_flash_info));
-}
-
-MACHINE_START(CM_A510, "Compulab CM-A510 Board")
- .atag_offset = 0x100,
- .nr_irqs = DOVE_NR_IRQS,
- .init_machine = cm_a510_init,
- .map_io = dove_map_io,
- .init_early = dove_init_early,
- .init_irq = dove_init_irq,
- .init_time = dove_timer_init,
- .restart = dove_restart,
-MACHINE_END
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
deleted file mode 100644
index 35e978514591..000000000000
--- a/arch/arm/mach-dove/common.c
+++ /dev/null
@@ -1,449 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-dove/common.c
- *
- * Core functions for Marvell Dove 88AP510 System On Chip
- */
-
-#include <linux/clk-provider.h>
-#include <linux/dma-mapping.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/platform_data/dma-mv_xor.h>
-#include <linux/platform_data/usb-ehci-orion.h>
-#include <linux/platform_device.h>
-#include <linux/soc/dove/pmu.h>
-#include <asm/hardware/cache-tauros2.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-#include <plat/common.h>
-#include <plat/irq.h>
-#include <plat/time.h>
-#include "bridge-regs.h"
-#include "pm.h"
-#include "common.h"
-
-/* These can go away once Dove uses the mvebu-mbus DT binding */
-#define DOVE_MBUS_PCIE0_MEM_TARGET 0x4
-#define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8
-#define DOVE_MBUS_PCIE0_IO_TARGET 0x4
-#define DOVE_MBUS_PCIE0_IO_ATTR 0xe0
-#define DOVE_MBUS_PCIE1_MEM_TARGET 0x8
-#define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8
-#define DOVE_MBUS_PCIE1_IO_TARGET 0x8
-#define DOVE_MBUS_PCIE1_IO_ATTR 0xe0
-#define DOVE_MBUS_CESA_TARGET 0x3
-#define DOVE_MBUS_CESA_ATTR 0x1
-#define DOVE_MBUS_BOOTROM_TARGET 0x1
-#define DOVE_MBUS_BOOTROM_ATTR 0xfd
-#define DOVE_MBUS_SCRATCHPAD_TARGET 0xd
-#define DOVE_MBUS_SCRATCHPAD_ATTR 0x0
-
-/*****************************************************************************
- * I/O Address Mapping
- ****************************************************************************/
-static struct map_desc __maybe_unused dove_io_desc[] __initdata = {
- {
- .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
- .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
- .length = DOVE_SB_REGS_SIZE,
- .type = MT_DEVICE,
- }, {
- .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
- .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
- .length = DOVE_NB_REGS_SIZE,
- .type = MT_DEVICE,
- },
-};
-
-void __init dove_map_io(void)
-{
- iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
-}
-
-/*****************************************************************************
- * CLK tree
- ****************************************************************************/
-static int dove_tclk;
-
-static DEFINE_SPINLOCK(gating_lock);
-static struct clk *tclk;
-
-static struct clk __init *dove_register_gate(const char *name,
- const char *parent, u8 bit_idx)
-{
- return clk_register_gate(NULL, name, parent, 0,
- (void __iomem *)CLOCK_GATING_CONTROL,
- bit_idx, 0, &gating_lock);
-}
-
-static void __init dove_clk_init(void)
-{
- struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
- struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
- struct clk *xor0, *xor1, *ge;
-
- tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, dove_tclk);
-
- usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
- usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
- sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
- pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
- pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
- sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
- sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
- nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
- camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
- i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
- i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
- crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
- ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
- pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
- xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
- xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
- dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
- ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
-
- orion_clkdev_add(NULL, "orion_spi.0", tclk);
- orion_clkdev_add(NULL, "orion_spi.1", tclk);
- orion_clkdev_add(NULL, "orion_wdt", tclk);
- orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
-
- orion_clkdev_add(NULL, "orion-ehci.0", usb0);
- orion_clkdev_add(NULL, "orion-ehci.1", usb1);
- orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
- orion_clkdev_add(NULL, "sata_mv.0", sata);
- orion_clkdev_add("0", "pcie", pex0);
- orion_clkdev_add("1", "pcie", pex1);
- orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
- orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
- orion_clkdev_add(NULL, "orion_nand", nand);
- orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
- orion_clkdev_add(NULL, "mvebu-audio.0", i2s0);
- orion_clkdev_add(NULL, "mvebu-audio.1", i2s1);
- orion_clkdev_add(NULL, "mv_crypto", crypto);
- orion_clkdev_add(NULL, "dove-ac97", ac97);
- orion_clkdev_add(NULL, "dove-pdma", pdma);
- orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
- orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
-}
-
-/*****************************************************************************
- * EHCI0
- ****************************************************************************/
-void __init dove_ehci0_init(void)
-{
- orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
-}
-
-/*****************************************************************************
- * EHCI1
- ****************************************************************************/
-void __init dove_ehci1_init(void)
-{
- orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
-}
-
-/*****************************************************************************
- * GE00
- ****************************************************************************/
-void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
-{
- orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
- IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
- 1600);
-}
-
-/*****************************************************************************
- * SoC RTC
- ****************************************************************************/
-static void __init dove_rtc_init(void)
-{
- orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
-}
-
-/*****************************************************************************
- * SATA
- ****************************************************************************/
-void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
-{
- orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
-
-}
-
-/*****************************************************************************
- * UART0
- ****************************************************************************/
-void __init dove_uart0_init(void)
-{
- orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
- IRQ_DOVE_UART_0, tclk);
-}
-
-/*****************************************************************************
- * UART1
- ****************************************************************************/
-void __init dove_uart1_init(void)
-{
- orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
- IRQ_DOVE_UART_1, tclk);
-}
-
-/*****************************************************************************
- * UART2
- ****************************************************************************/
-void __init dove_uart2_init(void)
-{
- orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
- IRQ_DOVE_UART_2, tclk);
-}
-
-/*****************************************************************************
- * UART3
- ****************************************************************************/
-void __init dove_uart3_init(void)
-{
- orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
- IRQ_DOVE_UART_3, tclk);
-}
-
-/*****************************************************************************
- * SPI
- ****************************************************************************/
-void __init dove_spi0_init(void)
-{
- orion_spi_init(DOVE_SPI0_PHYS_BASE);
-}
-
-void __init dove_spi1_init(void)
-{
- orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
-}
-
-/*****************************************************************************
- * I2C
- ****************************************************************************/
-void __init dove_i2c_init(void)
-{
- orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
-}
-
-/*****************************************************************************
- * Time handling
- ****************************************************************************/
-void __init dove_init_early(void)
-{
- orion_time_set_base(TIMER_VIRT_BASE);
- mvebu_mbus_init("marvell,dove-mbus",
- BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
- DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
-}
-
-static int __init dove_find_tclk(void)
-{
- return 166666667;
-}
-
-void __init dove_timer_init(void)
-{
- dove_tclk = dove_find_tclk();
- orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
- IRQ_DOVE_BRIDGE, dove_tclk);
-}
-
-/*****************************************************************************
- * XOR 0
- ****************************************************************************/
-static void __init dove_xor0_init(void)
-{
- orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
- IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
-}
-
-/*****************************************************************************
- * XOR 1
- ****************************************************************************/
-static void __init dove_xor1_init(void)
-{
- orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
- IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
-}
-
-/*****************************************************************************
- * SDIO
- ****************************************************************************/
-static u64 sdio_dmamask = DMA_BIT_MASK(32);
-
-static struct resource dove_sdio0_resources[] = {
- {
- .start = DOVE_SDIO0_PHYS_BASE,
- .end = DOVE_SDIO0_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_DOVE_SDIO0,
- .end = IRQ_DOVE_SDIO0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dove_sdio0 = {
- .name = "sdhci-dove",
- .id = 0,
- .dev = {
- .dma_mask = &sdio_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = dove_sdio0_resources,
- .num_resources = ARRAY_SIZE(dove_sdio0_resources),
-};
-
-void __init dove_sdio0_init(void)
-{
- platform_device_register(&dove_sdio0);
-}
-
-static struct resource dove_sdio1_resources[] = {
- {
- .start = DOVE_SDIO1_PHYS_BASE,
- .end = DOVE_SDIO1_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_DOVE_SDIO1,
- .end = IRQ_DOVE_SDIO1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dove_sdio1 = {
- .name = "sdhci-dove",
- .id = 1,
- .dev = {
- .dma_mask = &sdio_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = dove_sdio1_resources,
- .num_resources = ARRAY_SIZE(dove_sdio1_resources),
-};
-
-void __init dove_sdio1_init(void)
-{
- platform_device_register(&dove_sdio1);
-}
-
-void __init dove_setup_cpu_wins(void)
-{
- /*
- * The PCIe windows will no longer be statically allocated
- * here once Dove is migrated to the pci-mvebu driver. The
- * non-PCIe windows will no longer be created here once Dove
- * fully moves to DT.
- */
- mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
- DOVE_MBUS_PCIE0_IO_ATTR,
- DOVE_PCIE0_IO_PHYS_BASE,
- DOVE_PCIE0_IO_SIZE,
- DOVE_PCIE0_IO_BUS_BASE);
- mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
- DOVE_MBUS_PCIE1_IO_ATTR,
- DOVE_PCIE1_IO_PHYS_BASE,
- DOVE_PCIE1_IO_SIZE,
- DOVE_PCIE1_IO_BUS_BASE);
- mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
- DOVE_MBUS_PCIE0_MEM_ATTR,
- DOVE_PCIE0_MEM_PHYS_BASE,
- DOVE_PCIE0_MEM_SIZE);
- mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
- DOVE_MBUS_PCIE1_MEM_ATTR,
- DOVE_PCIE1_MEM_PHYS_BASE,
- DOVE_PCIE1_MEM_SIZE);
- mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
- DOVE_MBUS_CESA_ATTR,
- DOVE_CESA_PHYS_BASE,
- DOVE_CESA_SIZE);
- mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
- DOVE_MBUS_BOOTROM_ATTR,
- DOVE_BOOTROM_PHYS_BASE,
- DOVE_BOOTROM_SIZE);
- mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
- DOVE_MBUS_SCRATCHPAD_ATTR,
- DOVE_SCRATCHPAD_PHYS_BASE,
- DOVE_SCRATCHPAD_SIZE);
-}
-
-static struct resource orion_wdt_resource[] = {
- DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
- DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
-};
-
-static struct platform_device orion_wdt_device = {
- .name = "orion_wdt",
- .id = -1,
- .num_resources = ARRAY_SIZE(orion_wdt_resource),
- .resource = orion_wdt_resource,
-};
-
-static void __init __maybe_unused orion_wdt_init(void)
-{
- platform_device_register(&orion_wdt_device);
-}
-
-static const struct dove_pmu_domain_initdata pmu_domains[] __initconst = {
- {
- .pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK,
- .rst_mask = PMU_SW_RST_VIDEO_MASK,
- .iso_mask = PMU_ISO_VIDEO_MASK,
- .name = "vpu-domain",
- }, {
- .pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK,
- .rst_mask = PMU_SW_RST_GPU_MASK,
- .iso_mask = PMU_ISO_GPU_MASK,
- .name = "gpu-domain",
- }, {
- /* sentinel */
- },
-};
-
-static const struct dove_pmu_initdata pmu_data __initconst = {
- .pmc_base = DOVE_PMU_VIRT_BASE,
- .pmu_base = DOVE_PMU_VIRT_BASE + 0x8000,
- .irq = IRQ_DOVE_PMU,
- .irq_domain_start = IRQ_DOVE_PMU_START,
- .domains = pmu_domains,
-};
-
-void __init dove_init(void)
-{
- pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
- (dove_tclk + 499999) / 1000000);
-
-#ifdef CONFIG_CACHE_TAUROS2
- tauros2_init(0);
-#endif
- dove_setup_cpu_wins();
-
- /* Setup root of clk tree */
- dove_clk_init();
-
- /* internal devices that every board has */
- dove_init_pmu_legacy(&pmu_data);
- dove_rtc_init();
- dove_xor0_init();
- dove_xor1_init();
-}
-
-void dove_restart(enum reboot_mode mode, const char *cmd)
-{
- /*
- * Enable soft reset to assert RSTOUTn.
- */
- writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
-
- /*
- * Assert soft reset.
- */
- writel(SOFT_RESET, SYSTEM_SOFT_RESET);
-
- while (1)
- ;
-}
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
deleted file mode 100644
index 57ebc413d68c..000000000000
--- a/arch/arm/mach-dove/common.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-dove/common.h
- *
- * Core functions for Marvell Dove 88AP510 System On Chip
- */
-
-#ifndef __ARCH_DOVE_COMMON_H
-#define __ARCH_DOVE_COMMON_H
-
-#include <linux/reboot.h>
-
-struct mv643xx_eth_platform_data;
-struct mv_sata_platform_data;
-
-extern void dove_timer_init(void);
-
-/*
- * Basic Dove init functions used early by machine-setup.
- */
-void dove_map_io(void);
-void dove_init(void);
-void dove_init_early(void);
-void dove_init_irq(void);
-void dove_setup_cpu_wins(void);
-void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
-void dove_sata_init(struct mv_sata_platform_data *sata_data);
-#ifdef CONFIG_PCI
-void dove_pcie_init(int init_port0, int init_port1);
-#else
-static inline void dove_pcie_init(int init_port0, int init_port1) { }
-#endif
-void dove_ehci0_init(void);
-void dove_ehci1_init(void);
-void dove_uart0_init(void);
-void dove_uart1_init(void);
-void dove_uart2_init(void);
-void dove_uart3_init(void);
-void dove_spi0_init(void);
-void dove_spi1_init(void);
-void dove_i2c_init(void);
-void dove_sdio0_init(void);
-void dove_sdio1_init(void);
-void dove_restart(enum reboot_mode, const char *);
-
-#endif
diff --git a/arch/arm/mach-dove/dove.h b/arch/arm/mach-dove/dove.h
deleted file mode 100644
index e5054e3b0b78..000000000000
--- a/arch/arm/mach-dove/dove.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* Generic definitions for Marvell Dove 88AP510 SoC */
-
-#ifndef __ASM_ARCH_DOVE_H
-#define __ASM_ARCH_DOVE_H
-
-#include "irqs.h"
-
-/*
- * Marvell Dove address maps.
- *
- * phys virt size
- * c8000000 fdb00000 1M Cryptographic SRAM
- * e0000000 @runtime 128M PCIe-0 Memory space
- * e8000000 @runtime 128M PCIe-1 Memory space
- * f1000000 fec00000 1M on-chip south-bridge registers
- * f1800000 fe400000 8M on-chip north-bridge registers
- * f2000000 fee00000 1M PCIe-0 I/O space
- * f2100000 fef00000 1M PCIe-1 I/O space
- */
-
-#define DOVE_CESA_PHYS_BASE 0xc8000000
-#define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
-#define DOVE_CESA_SIZE SZ_1M
-
-#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
-#define DOVE_PCIE0_MEM_SIZE SZ_128M
-
-#define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
-#define DOVE_PCIE1_MEM_SIZE SZ_128M
-
-#define DOVE_BOOTROM_PHYS_BASE 0xf8000000
-#define DOVE_BOOTROM_SIZE SZ_128M
-
-#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
-#define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
-#define DOVE_SCRATCHPAD_SIZE SZ_1M
-
-#define DOVE_SB_REGS_PHYS_BASE 0xf1000000
-#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfec00000)
-#define DOVE_SB_REGS_SIZE SZ_1M
-
-#define DOVE_NB_REGS_PHYS_BASE 0xf1800000
-#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe400000)
-#define DOVE_NB_REGS_SIZE SZ_8M
-
-#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
-#define DOVE_PCIE0_IO_BUS_BASE 0x00000000
-#define DOVE_PCIE0_IO_SIZE SZ_64K
-
-#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000
-#define DOVE_PCIE1_IO_BUS_BASE 0x00010000
-#define DOVE_PCIE1_IO_SIZE SZ_64K
-
-/*
- * Dove Core Registers Map
- */
-
-/* SPI, I2C, UART */
-#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000)
-#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000)
-#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000)
-#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100)
-#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100)
-#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200)
-#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200)
-#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300)
-#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300)
-#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600)
-#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600)
-
-/* North-South Bridge */
-#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000)
-#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000)
-#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE)
-#define BRIDGE_WINS_SZ (0x80)
-
-/* Cryptographic Engine */
-#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000)
-
-/* PCIe 0 */
-#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000)
-
-/* USB */
-#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000)
-#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000)
-
-/* XOR 0 Engine */
-#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800)
-#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800)
-#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00)
-#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00)
-
-/* XOR 1 Engine */
-#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900)
-#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900)
-#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00)
-#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00)
-
-/* Gigabit Ethernet */
-#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000)
-
-/* PCIe 1 */
-#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000)
-
-/* CAFE */
-#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000)
-#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000)
-#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000)
-#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000)
-
-/* SATA */
-#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000)
-
-/* I2S/SPDIF */
-#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000)
-#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000)
-
-/* NAND Flash Controller */
-#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000)
-
-/* MPP, GPIO, Reset Sampling */
-#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
-#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
-#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014)
-#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018)
-#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
-#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420)
-#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
-#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
-#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
-#define DOVE_NAND_GPIO_EN (1 << 0)
-#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
-#define DOVE_SPI_GPIO_SEL (1 << 5)
-#define DOVE_UART1_GPIO_SEL (1 << 4)
-#define DOVE_AU1_GPIO_SEL (1 << 3)
-#define DOVE_CAM_GPIO_SEL (1 << 2)
-#define DOVE_SD1_GPIO_SEL (1 << 1)
-#define DOVE_SD0_GPIO_SEL (1 << 0)
-
-/* Power Management */
-#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000)
-#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c)
-
-/* Real Time Clock */
-#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500)
-
-/* AC97 */
-#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000)
-#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000)
-
-/* Peripheral DMA */
-#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000)
-#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000)
-
-#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
-#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7)
-#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
-#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20)
-#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21)
-#define DOVE_TWSI_OPTION3_GPIO (1 << 22)
-#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000)
-#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
-#define DOVE_SSP_ON_AU1 (1 << 0)
-#define DOVE_SSP_CLOCK_ENABLE (1 << 1)
-#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11)
-/* Memory Controller */
-#define DOVE_MC_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x00000)
-#define DOVE_MC_WINS_BASE (DOVE_MC_PHYS_BASE + 0x100)
-#define DOVE_MC_WINS_SZ (0x8)
-#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000)
-
-/* LCD Controller */
-#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
-#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000)
-#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
-#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000)
-
-/* Graphic Engine */
-#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000)
-
-/* Video Engine */
-#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000)
-
-#endif
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
deleted file mode 100644
index 027a8f87bc2e..000000000000
--- a/arch/arm/mach-dove/irq.c
+++ /dev/null
@@ -1,81 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-dove/irq.c
- *
- * Dove IRQ handling.
- */
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <asm/exception.h>
-
-#include <plat/irq.h>
-#include <plat/orion-gpio.h>
-
-#include "pm.h"
-#include "bridge-regs.h"
-#include "common.h"
-
-static int __initdata gpio0_irqs[4] = {
- IRQ_DOVE_GPIO_0_7,
- IRQ_DOVE_GPIO_8_15,
- IRQ_DOVE_GPIO_16_23,
- IRQ_DOVE_GPIO_24_31,
-};
-
-static int __initdata gpio1_irqs[4] = {
- IRQ_DOVE_HIGH_GPIO,
- 0,
- 0,
- 0,
-};
-
-static int __initdata gpio2_irqs[4] = {
- 0,
- 0,
- 0,
- 0,
-};
-
-static void __iomem *dove_irq_base = IRQ_VIRT_BASE;
-
-static asmlinkage void
-__exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
-{
- u32 stat;
-
- stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF);
- stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF);
- if (stat) {
- unsigned int hwirq = 1 + __fls(stat);
- handle_IRQ(hwirq, regs);
- return;
- }
- stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF);
- stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF);
- if (stat) {
- unsigned int hwirq = 33 + __fls(stat);
- handle_IRQ(hwirq, regs);
- return;
- }
-}
-
-void __init dove_init_irq(void)
-{
- orion_irq_init(1, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
- orion_irq_init(33, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
-
- set_handle_irq(dove_legacy_handle_irq);
-
- /*
- * Initialize gpiolib for GPIOs 0-71.
- */
- orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
- IRQ_DOVE_GPIO_START, gpio0_irqs);
-
- orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
- IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
-
- orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
- IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
-}
diff --git a/arch/arm/mach-dove/irqs.h b/arch/arm/mach-dove/irqs.h
deleted file mode 100644
index 5467098c7042..000000000000
--- a/arch/arm/mach-dove/irqs.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* IRQ definitions for Marvell Dove 88AP510 SoC */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-/*
- * Dove Low Interrupt Controller
- */
-#define IRQ_DOVE_BRIDGE (1 + 0)
-#define IRQ_DOVE_H2C (1 + 1)
-#define IRQ_DOVE_C2H (1 + 2)
-#define IRQ_DOVE_NAND (1 + 3)
-#define IRQ_DOVE_PDMA (1 + 4)
-#define IRQ_DOVE_SPI1 (1 + 5)
-#define IRQ_DOVE_SPI0 (1 + 6)
-#define IRQ_DOVE_UART_0 (1 + 7)
-#define IRQ_DOVE_UART_1 (1 + 8)
-#define IRQ_DOVE_UART_2 (1 + 9)
-#define IRQ_DOVE_UART_3 (1 + 10)
-#define IRQ_DOVE_I2C (1 + 11)
-#define IRQ_DOVE_GPIO_0_7 (1 + 12)
-#define IRQ_DOVE_GPIO_8_15 (1 + 13)
-#define IRQ_DOVE_GPIO_16_23 (1 + 14)
-#define IRQ_DOVE_PCIE0_ERR (1 + 15)
-#define IRQ_DOVE_PCIE0 (1 + 16)
-#define IRQ_DOVE_PCIE1_ERR (1 + 17)
-#define IRQ_DOVE_PCIE1 (1 + 18)
-#define IRQ_DOVE_I2S0 (1 + 19)
-#define IRQ_DOVE_I2S0_ERR (1 + 20)
-#define IRQ_DOVE_I2S1 (1 + 21)
-#define IRQ_DOVE_I2S1_ERR (1 + 22)
-#define IRQ_DOVE_USB_ERR (1 + 23)
-#define IRQ_DOVE_USB0 (1 + 24)
-#define IRQ_DOVE_USB1 (1 + 25)
-#define IRQ_DOVE_GE00_RX (1 + 26)
-#define IRQ_DOVE_GE00_TX (1 + 27)
-#define IRQ_DOVE_GE00_MISC (1 + 28)
-#define IRQ_DOVE_GE00_SUM (1 + 29)
-#define IRQ_DOVE_GE00_ERR (1 + 30)
-#define IRQ_DOVE_CRYPTO (1 + 31)
-
-/*
- * Dove High Interrupt Controller
- */
-#define IRQ_DOVE_AC97 (1 + 32)
-#define IRQ_DOVE_PMU (1 + 33)
-#define IRQ_DOVE_CAM (1 + 34)
-#define IRQ_DOVE_SDIO0 (1 + 35)
-#define IRQ_DOVE_SDIO1 (1 + 36)
-#define IRQ_DOVE_SDIO0_WAKEUP (1 + 37)
-#define IRQ_DOVE_SDIO1_WAKEUP (1 + 38)
-#define IRQ_DOVE_XOR_00 (1 + 39)
-#define IRQ_DOVE_XOR_01 (1 + 40)
-#define IRQ_DOVE_XOR0_ERR (1 + 41)
-#define IRQ_DOVE_XOR_10 (1 + 42)
-#define IRQ_DOVE_XOR_11 (1 + 43)
-#define IRQ_DOVE_XOR1_ERR (1 + 44)
-#define IRQ_DOVE_LCD_DCON (1 + 45)
-#define IRQ_DOVE_LCD1 (1 + 46)
-#define IRQ_DOVE_LCD0 (1 + 47)
-#define IRQ_DOVE_GPU (1 + 48)
-#define IRQ_DOVE_PERFORM_MNTR (1 + 49)
-#define IRQ_DOVE_VPRO_DMA1 (1 + 51)
-#define IRQ_DOVE_SSP_TIMER (1 + 54)
-#define IRQ_DOVE_SSP (1 + 55)
-#define IRQ_DOVE_MC_L2_ERR (1 + 56)
-#define IRQ_DOVE_CRYPTO_ERR (1 + 59)
-#define IRQ_DOVE_GPIO_24_31 (1 + 60)
-#define IRQ_DOVE_HIGH_GPIO (1 + 61)
-#define IRQ_DOVE_SATA (1 + 62)
-
-/*
- * DOVE General Purpose Pins
- */
-#define IRQ_DOVE_GPIO_START 65
-#define NR_GPIO_IRQS 64
-
-/*
- * PMU interrupts
- */
-#define IRQ_DOVE_PMU_START (IRQ_DOVE_GPIO_START + NR_GPIO_IRQS)
-#define NR_PMU_IRQS 7
-#define IRQ_DOVE_RTC (IRQ_DOVE_PMU_START + 5)
-
-#define DOVE_NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
-
-
-#endif
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
deleted file mode 100644
index e41bd473abe9..000000000000
--- a/arch/arm/mach-dove/mpp.c
+++ /dev/null
@@ -1,159 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-dove/mpp.c
- *
- * MPP functions for Marvell Dove SoCs
- */
-
-#include <linux/kernel.h>
-#include <linux/gpio/consumer.h>
-#include <linux/io.h>
-#include <plat/mpp.h>
-#include <plat/orion-gpio.h>
-#include "dove.h"
-#include "mpp.h"
-
-struct dove_mpp_grp {
- int start;
- int end;
-};
-
-/* Map a group to a range of GPIO pins in that group */
-static const struct dove_mpp_grp dove_mpp_grp[] = {
- [MPP_24_39] = {
- .start = 24,
- .end = 39,
- },
- [MPP_40_45] = {
- .start = 40,
- .end = 45,
- },
- [MPP_46_51] = {
- .start = 46,
- .end = 51,
- },
- [MPP_58_61] = {
- .start = 58,
- .end = 61,
- },
- [MPP_62_63] = {
- .start = 62,
- .end = 63,
- },
-};
-
-/* Enable gpio for a range of pins. mode should be a combination of
- GPIO_OUTPUT_OK | GPIO_INPUT_OK */
-static void __init dove_mpp_gpio_mode(int start, int end, int gpio_mode)
-{
- int i;
-
- for (i = start; i <= end; i++)
- orion_gpio_set_valid(i, gpio_mode);
-}
-
-/* Dump all the extra MPP registers. The platform code will dump the
- registers for pins 0-23. */
-static void __init dove_mpp_dump_regs(void)
-{
- pr_debug("PMU_CTRL4_CTRL: %08x\n",
- readl(DOVE_MPP_CTRL4_VIRT_BASE));
-
- pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n",
- readl(DOVE_PMU_MPP_GENERAL_CTRL));
-
- pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
-}
-
-static void __init dove_mpp_cfg_nfc(int sel)
-{
- u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE);
-
- mpp_gen_cfg &= ~0x1;
- mpp_gen_cfg |= sel;
- writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE);
-
- dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK);
-}
-
-static void __init dove_mpp_cfg_au1(int sel)
-{
- u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
- u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
- u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
- u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
-
- mpp_ctrl4 &= ~(DOVE_AU1_GPIO_SEL);
- ssp_ctrl1 &= ~(DOVE_SSP_ON_AU1);
- mpp_gen_ctrl &= ~(DOVE_AU1_SPDIFO_GPIO_EN);
- global_cfg_2 &= ~(DOVE_TWSI_OPTION3_GPIO);
-
- if (!sel || sel == 0x2)
- dove_mpp_gpio_mode(52, 57, 0);
- else
- dove_mpp_gpio_mode(52, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
-
- if (sel & 0x1) {
- global_cfg_2 |= DOVE_TWSI_OPTION3_GPIO;
- dove_mpp_gpio_mode(56, 57, 0);
- }
- if (sel & 0x2) {
- mpp_gen_ctrl |= DOVE_AU1_SPDIFO_GPIO_EN;
- dove_mpp_gpio_mode(57, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
- }
- if (sel & 0x4) {
- ssp_ctrl1 |= DOVE_SSP_ON_AU1;
- dove_mpp_gpio_mode(52, 55, 0);
- }
- if (sel & 0x8)
- mpp_ctrl4 |= DOVE_AU1_GPIO_SEL;
-
- writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
- writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1);
- writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE);
- writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
-}
-
-/* Configure the group registers, enabling GPIO if sel indicates the
- pin is to be used for GPIO */
-static void __init dove_mpp_conf_grp(unsigned int *mpp_grp_list)
-{
- u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
- int gpio_mode;
-
- for ( ; *mpp_grp_list; mpp_grp_list++) {
- unsigned int num = MPP_NUM(*mpp_grp_list);
- unsigned int sel = MPP_SEL(*mpp_grp_list);
-
- if (num > MPP_GRP_MAX) {
- pr_err("dove: invalid MPP GRP number (%u)\n", num);
- continue;
- }
-
- mpp_ctrl4 &= ~(0x1 << num);
- mpp_ctrl4 |= sel << num;
-
- gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
- dove_mpp_gpio_mode(dove_mpp_grp[num].start,
- dove_mpp_grp[num].end, gpio_mode);
- }
- writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
-}
-
-/* Configure the various MPP pins on Dove */
-void __init dove_mpp_conf(unsigned int *mpp_list,
- unsigned int *mpp_grp_list,
- unsigned int grp_au1_52_57,
- unsigned int grp_nfc_64_71)
-{
- dove_mpp_dump_regs();
-
- /* Use platform code for pins 0-23 */
- orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE);
-
- dove_mpp_conf_grp(mpp_grp_list);
- dove_mpp_cfg_au1(grp_au1_52_57);
- dove_mpp_cfg_nfc(grp_nfc_64_71);
-
- dove_mpp_dump_regs();
-}
diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h
deleted file mode 100644
index 2e4b89c86ca8..000000000000
--- a/arch/arm/mach-dove/mpp.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ARCH_DOVE_MPP_CODED_H
-#define __ARCH_DOVE_MPP_CODED_H
-
-#define MPP(_num, _sel, _in, _out) ( \
- /* MPP number */ ((_num) & 0xff) | \
- /* MPP select value */ (((_sel) & 0xf) << 8) | \
- /* may be input signal */ ((!!(_in)) << 12) | \
- /* may be output signal */ ((!!(_out)) << 13))
-
-#define MPP0_GPIO0 MPP(0, 0x0, 1, 1)
-#define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0)
-#define MPP0_SDIO0_CD MPP(0, 0x3, 0, 0)
-#define MPP0_LCD0_PWM MPP(0, 0xf, 0, 0)
-
-#define MPP1_GPIO1 MPP(1, 0x0, 1, 1)
-#define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0)
-#define MPP1_SDIO0_WP MPP(1, 0x3, 0, 0)
-#define MPP1_LCD1_PWM MPP(1, 0xf, 0, 0)
-
-#define MPP2_GPIO2 MPP(2, 0x0, 1, 1)
-#define MPP2_SATA_PRESENT MPP(2, 0x1, 0, 0)
-#define MPP2_UA2_TXD MPP(2, 0x2, 0, 0)
-#define MPP2_SDIO0_BUS_POWER MPP(2, 0x3, 0, 0)
-#define MPP2_UA_RTSn1 MPP(2, 0x4, 0, 0)
-
-#define MPP3_GPIO3 MPP(3, 0x0, 1, 1)
-#define MPP3_SATA_ACT MPP(3, 0x1, 0, 0)
-#define MPP3_UA2_RXD MPP(3, 0x2, 0, 0)
-#define MPP3_SDIO0_LED_CTRL MPP(3, 0x3, 0, 0)
-#define MPP3_UA_CTSn1 MPP(3, 0x4, 0, 0)
-#define MPP3_SPI_LCD_CS1 MPP(3, 0xf, 0, 0)
-
-#define MPP4_GPIO4 MPP(4, 0x0, 1, 1)
-#define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0)
-#define MPP4_SDIO1_CD MPP(4, 0x3, 0, 0)
-#define MPP4_SPI_1_MISO MPP(4, 0x4, 0, 0)
-
-#define MPP5_GPIO5 MPP(5, 0x0, 1, 1)
-#define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0)
-#define MPP5_SDIO1_WP MPP(5, 0x3, 0, 0)
-#define MPP5_SPI_1_CS MPP(5, 0x4, 0, 0)
-
-#define MPP6_GPIO6 MPP(6, 0x0, 1, 1)
-#define MPP6_UA3_TXD MPP(6, 0x2, 0, 0)
-#define MPP6_SDIO1_BUS_POWER MPP(6, 0x3, 0, 0)
-#define MPP6_SPI_1_MOSI MPP(6, 0x4, 0, 0)
-
-#define MPP7_GPIO7 MPP(7, 0x0, 1, 1)
-#define MPP7_UA3_RXD MPP(7, 0x2, 0, 0)
-#define MPP7_SDIO1_LED_CTRL MPP(7, 0x3, 0, 0)
-#define MPP7_SPI_1_SCK MPP(7, 0x4, 0, 0)
-
-#define MPP8_GPIO8 MPP(8, 0x0, 1, 1)
-#define MPP8_WD_RST_OUT MPP(8, 0x1, 0, 0)
-
-#define MPP9_GPIO9 MPP(9, 0x0, 1, 1)
-#define MPP9_PEX1_CLKREQn MPP(9, 0x5, 0, 0)
-
-#define MPP10_GPIO10 MPP(10, 0x0, 1, 1)
-#define MPP10_SSP_SCLK MPP(10, 0x5, 0, 0)
-
-#define MPP11_GPIO11 MPP(11, 0x0, 1, 1)
-#define MPP11_SATA_PRESENT MPP(11, 0x1, 0, 0)
-#define MPP11_SATA_ACT MPP(11, 0x2, 0, 0)
-#define MPP11_SDIO0_LED_CTRL MPP(11, 0x3, 0, 0)
-#define MPP11_SDIO1_LED_CTRL MPP(11, 0x4, 0, 0)
-#define MPP11_PEX0_CLKREQn MPP(11, 0x5, 0, 0)
-
-#define MPP12_GPIO12 MPP(12, 0x0, 1, 1)
-#define MPP12_SATA_ACT MPP(12, 0x1, 0, 0)
-#define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0)
-#define MPP12_AD0_I2S_EXT_MCLK MPP(12, 0x3, 0, 0)
-#define MPP12_SDIO1_CD MPP(12, 0x4, 0, 0)
-
-#define MPP13_GPIO13 MPP(13, 0x0, 1, 1)
-#define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0)
-#define MPP13_AD1_I2S_EXT_MCLK MPP(13, 0x3, 0, 0)
-#define MPP13_SDIO1WP MPP(13, 0x4, 0, 0)
-#define MPP13_SSP_EXTCLK MPP(13, 0x5, 0, 0)
-
-#define MPP14_GPIO14 MPP(14, 0x0, 1, 1)
-#define MPP14_UA2_TXD MPP(14, 0x2, 0, 0)
-#define MPP14_SDIO1_BUS_POWER MPP(14, 0x4, 0, 0)
-#define MPP14_SSP_RXD MPP(14, 0x5, 0, 0)
-
-#define MPP15_GPIO15 MPP(15, 0x0, 1, 1)
-#define MPP15_UA2_RXD MPP(15, 0x2, 0, 0)
-#define MPP15_SDIO1_LED_CTRL MPP(15, 0x4, 0, 0)
-#define MPP15_SSP_SFRM MPP(15, 0x5, 0, 0)
-
-#define MPP16_GPIO16 MPP(16, 0x0, 1, 1)
-#define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0)
-#define MPP16_SDIO0_CD MPP(16, 0x3, 0, 0)
-#define MPP16_SPI_LCD_CS1 MPP(16, 0x4, 0, 0)
-#define MPP16_AC97_SDATA_IN1 MPP(16, 0x5, 0, 0)
-
-#define MPP17_GPIO17 MPP(17, 0x0, 1, 1)
-#define MPP17_AC97_SYSCLK_OUT MPP(17, 0x1, 0, 0)
-#define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0)
-#define MPP17_SDIO0_WP MPP(17, 0x3, 0, 0)
-#define MPP17_TW_SDA2 MPP(17, 0x4, 0, 0)
-#define MPP17_AC97_SDATA_IN2 MPP(17, 0x5, 0, 0)
-
-#define MPP18_GPIO18 MPP(18, 0x0, 1, 1)
-#define MPP18_UA3_TXD MPP(18, 0x2, 0, 0)
-#define MPP18_SDIO0_BUS_POWER MPP(18, 0x3, 0, 0)
-#define MPP18_LCD0_PWM MPP(18, 0x4, 0, 0)
-#define MPP18_AC_SDATA_IN3 MPP(18, 0x5, 0, 0)
-
-#define MPP19_GPIO19 MPP(19, 0x0, 1, 1)
-#define MPP19_UA3_RXD MPP(19, 0x2, 0, 0)
-#define MPP19_SDIO0_LED_CTRL MPP(19, 0x3, 0, 0)
-#define MPP19_TW_SCK2 MPP(19, 0x4, 0, 0)
-
-#define MPP20_GPIO20 MPP(20, 0x0, 1, 1)
-#define MPP20_AC97_SYSCLK_OUT MPP(20, 0x1, 0, 0)
-#define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0)
-#define MPP20_SDIO1_CD MPP(20, 0x3, 0, 0)
-#define MPP20_SDIO0_CD MPP(20, 0x5, 0, 0)
-#define MPP20_SPI_1_MISO MPP(20, 0x6, 0, 0)
-
-#define MPP21_GPIO21 MPP(21, 0x0, 1, 1)
-#define MPP21_UA1_RTSn MPP(21, 0x1, 0, 0)
-#define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0)
-#define MPP21_SDIO1_WP MPP(21, 0x3, 0, 0)
-#define MPP21_SSP_SFRM MPP(21, 0x4, 0, 0)
-#define MPP21_SDIO0_WP MPP(21, 0x5, 0, 0)
-#define MPP21_SPI_1_CS MPP(21, 0x6, 0, 0)
-
-#define MPP22_GPIO22 MPP(22, 0x0, 1, 1)
-#define MPP22_UA1_CTSn MPP(22, 0x1, 0, 0)
-#define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0)
-#define MPP22_SDIO1_BUS_POWER MPP(22, 0x3, 0, 0)
-#define MPP22_SSP_TXD MPP(22, 0x4, 0, 0)
-#define MPP22_SDIO0_BUS_POWER MPP(22, 0x5, 0, 0)
-#define MPP22_SPI_1_MOSI MPP(22, 0x6, 0, 0)
-
-#define MPP23_GPIO23 MPP(23, 0x0, 1, 1)
-#define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0)
-#define MPP23_SDIO1_LED_CTRL MPP(23, 0x3, 0, 0)
-#define MPP23_SSP_SCLK MPP(23, 0x4, 0, 0)
-#define MPP23_SDIO0_LED_CTRL MPP(23, 0x5, 0, 0)
-#define MPP23_SPI_1_SCK MPP(23, 0x6, 0, 0)
-
-#define MPP_MAX 23
-
-#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 0)
-
-/* for MPP groups _num is a group index */
-enum dove_mpp_grp_idx {
- MPP_24_39 = 2,
- MPP_40_45 = 0,
- MPP_46_51 = 1,
- MPP_58_61 = 5,
- MPP_62_63 = 4,
- MPP_GRP_MAX = 5,
-};
-
-#define MPP_GRP_24_39_GPIO MPP_GRP(MPP_24_39, 0x1)
-#define MPP_GRP_24_39_CAM MPP_GRP(MPP_24_39, 0x0)
-
-#define MPP_GRP_40_45_GPIO MPP_GRP(MPP_40_45, 0x1)
-#define MPP_GRP_40_45_SD0 MPP_GRP(MPP_40_45, 0x0)
-
-#define MPP_GRP_46_51_GPIO MPP_GRP(MPP_46_51, 0x1)
-#define MPP_GRP_46_51_SD1 MPP_GRP(MPP_46_51, 0x0)
-
-#define MPP_GRP_58_61_GPIO MPP_GRP(MPP_58_61, 0x1)
-#define MPP_GRP_58_61_SPI MPP_GRP(MPP_58_61, 0x0)
-
-#define MPP_GRP_62_63_GPIO MPP_GRP(MPP_62_63, 0x1)
-#define MPP_GRP_62_63_UA1 MPP_GRP(MPP_62_63, 0x0)
-
-/* The MPP[64:71] control differs from other groups */
-#define MPP_GRP_NFC_64_71_GPO 0x1
-#define MPP_GRP_NFC_64_71_NFC 0x0
-
-/*
- * The MPP[52:57] functionality is encoded by 4 bits in different
- * registers. The _num field in this case encodes those bits in
- * correspodence with Table 135 of 88AP510 Functional specification
- */
-#define MPP_GRP_AU1_52_57_AU1 0x0
-#define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2
-#define MPP_GRP_AU1_52_57_GPIO 0xa
-#define MPP_GRP_AU1_52_57_TW_GPIO 0xb
-#define MPP_GRP_AU1_52_57_AU1_SSP 0xc
-#define MPP_GRP_AU1_52_57_SSP_GPIO 0xe
-#define MPP_GRP_AU1_52_57_SSP_TW 0xf
-
-void dove_mpp_conf(unsigned int *mpp_list,
- unsigned int *mpp_grp_list,
- unsigned int grp_au1_52_57,
- unsigned int grp_nfc_64_71);
-
-#endif /* __ARCH_DOVE_MPP_CODED_H */
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
deleted file mode 100644
index 3044b7e03890..000000000000
--- a/arch/arm/mach-dove/pcie.c
+++ /dev/null
@@ -1,226 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-dove/pcie.c
- *
- * PCIe functions for Marvell Dove 88AP510 SoC
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/clk.h>
-#include <video/vga.h>
-#include <asm/mach/pci.h>
-#include <asm/mach/arch.h>
-#include <asm/setup.h>
-#include <asm/delay.h>
-#include <plat/pcie.h>
-#include <plat/addr-map.h>
-#include "irqs.h"
-#include "bridge-regs.h"
-#include "common.h"
-
-struct pcie_port {
- u8 index;
- u8 root_bus_nr;
- void __iomem *base;
- spinlock_t conf_lock;
- char mem_space_name[16];
- struct resource res;
-};
-
-static struct pcie_port pcie_port[2];
-static int num_pcie_ports;
-
-
-static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
-{
- struct pcie_port *pp;
- struct resource realio;
-
- if (nr >= num_pcie_ports)
- return 0;
-
- pp = &pcie_port[nr];
- sys->private_data = pp;
- pp->root_bus_nr = sys->busnr;
-
- /*
- * Generic PCIe unit setup.
- */
- orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
-
- orion_pcie_setup(pp->base);
-
- realio.start = sys->busnr * SZ_64K;
- realio.end = realio.start + SZ_64K - 1;
- pci_remap_iospace(&realio, pp->index == 0 ? DOVE_PCIE0_IO_PHYS_BASE :
- DOVE_PCIE1_IO_PHYS_BASE);
-
- /*
- * IORESOURCE_MEM
- */
- snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
- "PCIe %d MEM", pp->index);
- pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
- pp->res.name = pp->mem_space_name;
- if (pp->index == 0) {
- pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
- pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
- } else {
- pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
- pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
- }
- pp->res.flags = IORESOURCE_MEM;
- if (request_resource(&iomem_resource, &pp->res))
- panic("Request PCIe Memory resource failed\n");
- pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
-
- return 1;
-}
-
-static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
-{
- /*
- * Don't go out when trying to access nonexisting devices
- * on the local bus.
- */
- if (bus == pp->root_bus_nr && dev > 1)
- return 0;
-
- return 1;
-}
-
-static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
- int size, u32 *val)
-{
- struct pci_sys_data *sys = bus->sysdata;
- struct pcie_port *pp = sys->private_data;
- unsigned long flags;
- int ret;
-
- if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
- *val = 0xffffffff;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
- spin_lock_irqsave(&pp->conf_lock, flags);
- ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
- spin_unlock_irqrestore(&pp->conf_lock, flags);
-
- return ret;
-}
-
-static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
- int where, int size, u32 val)
-{
- struct pci_sys_data *sys = bus->sysdata;
- struct pcie_port *pp = sys->private_data;
- unsigned long flags;
- int ret;
-
- if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- spin_lock_irqsave(&pp->conf_lock, flags);
- ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
- spin_unlock_irqrestore(&pp->conf_lock, flags);
-
- return ret;
-}
-
-static struct pci_ops pcie_ops = {
- .read = pcie_rd_conf,
- .write = pcie_wr_conf,
-};
-
-/*
- * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
- * is operating as a root complex this needs to be switched to
- * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
- * the device. Decoding setup is handled by the orion code.
- */
-static void rc_pci_fixup(struct pci_dev *dev)
-{
- if (dev->bus->parent == NULL && dev->devfn == 0) {
- struct resource *r;
-
- dev->class &= 0xff;
- dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
- pci_dev_for_each_resource(dev, r) {
- r->start = 0;
- r->end = 0;
- r->flags = 0;
- }
- }
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
-
-static int __init
-dove_pcie_scan_bus(int nr, struct pci_host_bridge *bridge)
-{
- struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
-
- if (nr >= num_pcie_ports) {
- BUG();
- return -EINVAL;
- }
-
- list_splice_init(&sys->resources, &bridge->windows);
- bridge->dev.parent = NULL;
- bridge->sysdata = sys;
- bridge->busnr = sys->busnr;
- bridge->ops = &pcie_ops;
-
- return pci_scan_root_bus_bridge(bridge);
-}
-
-static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- struct pci_sys_data *sys = dev->sysdata;
- struct pcie_port *pp = sys->private_data;
-
- return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
-}
-
-static struct hw_pci dove_pci __initdata = {
- .nr_controllers = 2,
- .setup = dove_pcie_setup,
- .scan = dove_pcie_scan_bus,
- .map_irq = dove_pcie_map_irq,
-};
-
-static void __init add_pcie_port(int index, void __iomem *base)
-{
- printk(KERN_INFO "Dove PCIe port %d: ", index);
-
- if (orion_pcie_link_up(base)) {
- struct pcie_port *pp = &pcie_port[num_pcie_ports++];
- struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0"));
-
- if (!IS_ERR(clk))
- clk_prepare_enable(clk);
-
- printk(KERN_INFO "link up\n");
-
- pp->index = index;
- pp->root_bus_nr = -1;
- pp->base = base;
- spin_lock_init(&pp->conf_lock);
- memset(&pp->res, 0, sizeof(pp->res));
- } else {
- printk(KERN_INFO "link down, ignoring\n");
- }
-}
-
-void __init dove_pcie_init(int init_port0, int init_port1)
-{
- vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
-
- if (init_port0)
- add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
-
- if (init_port1)
- add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
-
- pci_common_init(&dove_pci);
-}
diff --git a/arch/arm/mach-dove/pm.h b/arch/arm/mach-dove/pm.h
deleted file mode 100644
index a4c3aba1e2d0..000000000000
--- a/arch/arm/mach-dove/pm.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __ASM_ARCH_PM_H
-#define __ASM_ARCH_PM_H
-
-#include <asm/errno.h>
-#include "irqs.h"
-
-#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)
-#define CLOCK_GATING_BIT_USB0 0
-#define CLOCK_GATING_BIT_USB1 1
-#define CLOCK_GATING_BIT_GBE 2
-#define CLOCK_GATING_BIT_SATA 3
-#define CLOCK_GATING_BIT_PCIE0 4
-#define CLOCK_GATING_BIT_PCIE1 5
-#define CLOCK_GATING_BIT_SDIO0 8
-#define CLOCK_GATING_BIT_SDIO1 9
-#define CLOCK_GATING_BIT_NAND 10
-#define CLOCK_GATING_BIT_CAMERA 11
-#define CLOCK_GATING_BIT_I2S0 12
-#define CLOCK_GATING_BIT_I2S1 13
-#define CLOCK_GATING_BIT_CRYPTO 15
-#define CLOCK_GATING_BIT_AC97 21
-#define CLOCK_GATING_BIT_PDMA 22
-#define CLOCK_GATING_BIT_XOR0 23
-#define CLOCK_GATING_BIT_XOR1 24
-#define CLOCK_GATING_BIT_GIGA_PHY 30
-#define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0)
-#define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1)
-#define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE)
-#define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA)
-#define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0)
-#define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1)
-#define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0)
-#define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1)
-#define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND)
-#define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA)
-#define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0)
-#define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1)
-#define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO)
-#define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97)
-#define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA)
-#define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0)
-#define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1)
-#define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY)
-
-#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)
-
-#define PMU_SW_RST_VIDEO_MASK BIT(16)
-#define PMU_SW_RST_GPU_MASK BIT(18)
-
-#define PMU_PWR_GPU_PWR_DWN_MASK BIT(2)
-#define PMU_PWR_VPU_PWR_DWN_MASK BIT(3)
-
-#define PMU_ISO_VIDEO_MASK BIT(0)
-#define PMU_ISO_GPU_MASK BIT(1)
-
-#endif
diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig
deleted file mode 100644
index 98b35f5d05ba..000000000000
--- a/arch/arm/mach-mv78xx0/Kconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-menuconfig ARCH_MV78XX0
- bool "Marvell MV78xx0 (DEPRECATED)"
- depends on ARCH_MULTI_V5
- depends on CPU_LITTLE_ENDIAN
- depends on ATAGS
- select CPU_FEROCEON
- select GPIOLIB
- select GPIOLIB_LEGACY
- select MVEBU_MBUS
- select FORCE_PCI
- select PLAT_ORION_LEGACY
- help
- Support for the following Marvell MV78xx0 series SoCs:
- MV781x0, MV782x0.
-
- This platform is scheduled for removal in early 2027.
-
-if ARCH_MV78XX0
-
-config MACH_TERASTATION_WXL
- bool "Buffalo WLX (Terastation Duo) NAS"
- help
- Say 'Y' here if you want your kernel to support the
- Buffalo WXL Nas.
-
-endif
diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile
deleted file mode 100644
index ddee6ae501bb..000000000000
--- a/arch/arm/mach-mv78xx0/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-ccflags-y := -I$(srctree)/arch/arm/plat-orion/include
-
-obj-y += common.o mpp.o irq.o pcie.o
-obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o
diff --git a/arch/arm/mach-mv78xx0/bridge-regs.h b/arch/arm/mach-mv78xx0/bridge-regs.h
deleted file mode 100644
index d57ac967c4b3..000000000000
--- a/arch/arm/mach-mv78xx0/bridge-regs.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __ASM_ARCH_BRIDGE_REGS_H
-#define __ASM_ARCH_BRIDGE_REGS_H
-
-#include "mv78xx0.h"
-
-#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
-#define L2_WRITETHROUGH 0x00020000
-
-#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
-#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
-#define SOFT_RESET_OUT_EN 0x00000004
-
-#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
-#define SOFT_RESET 0x00000001
-
-#define BRIDGE_INT_TIMER1_CLR (~0x0004)
-
-#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
-#define IRQ_CAUSE_ERR_OFF 0x0000
-#define IRQ_CAUSE_LOW_OFF 0x0004
-#define IRQ_CAUSE_HIGH_OFF 0x0008
-#define IRQ_MASK_ERR_OFF 0x000c
-#define IRQ_MASK_LOW_OFF 0x0010
-#define IRQ_MASK_HIGH_OFF 0x0014
-
-#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
-#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
-
-#endif
diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
deleted file mode 100644
index 3b2e381b7383..000000000000
--- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
+++ /dev/null
@@ -1,183 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
- *
- * Buffalo WXL (Terastation Duo) Setup routines
- *
- * sebastien requiem <sebastien@requiem.fr>
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ethtool.h>
-#include <linux/i2c.h>
-#include <linux/gpio/legacy.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "mv78xx0.h"
-#include "common.h"
-#include "mpp.h"
-
-
-#define TSWXL_AUTO_SWITCH 15
-#define TSWXL_USB_POWER1 30
-#define TSWXL_USB_POWER2 31
-
-
-/* This arch has 2 Giga Ethernet */
-
-static struct mv643xx_eth_platform_data db78x00_ge00_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(0),
-};
-
-static struct mv643xx_eth_platform_data db78x00_ge01_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
-};
-
-
-/* 2 SATA controller supporting HotPlug */
-
-static struct mv_sata_platform_data db78x00_sata_data = {
- .n_ports = 2,
-};
-
-static struct i2c_board_info __initdata db78x00_i2c_rtc = {
- I2C_BOARD_INFO("rs5c372a", 0x32),
-};
-
-
-static unsigned int wxl_mpp_config[] __initdata = {
- MPP0_GE1_TXCLK,
- MPP1_GE1_TXCTL,
- MPP2_GE1_RXCTL,
- MPP3_GE1_RXCLK,
- MPP4_GE1_TXD0,
- MPP5_GE1_TXD1,
- MPP6_GE1_TXD2,
- MPP7_GE1_TXD3,
- MPP8_GE1_RXD0,
- MPP9_GE1_RXD1,
- MPP10_GE1_RXD2,
- MPP11_GE1_RXD3,
- MPP12_GPIO,
- MPP13_GPIO,
- MPP14_GPIO,
- MPP15_GPIO,
- MPP16_GPIO,
- MPP17_GPIO,
- MPP18_GPIO,
- MPP19_GPIO,
- MPP20_GPIO,
- MPP21_GPIO,
- MPP22_GPIO,
- MPP23_GPIO,
- MPP24_UA2_TXD,
- MPP25_UA2_RXD,
- MPP26_UA2_CTSn,
- MPP27_UA2_RTSn,
- MPP28_GPIO,
- MPP29_GPIO,
- MPP30_GPIO,
- MPP31_GPIO,
- MPP32_GPIO,
- MPP33_GPIO,
- MPP34_GPIO,
- MPP35_GPIO,
- MPP36_GPIO,
- MPP37_GPIO,
- MPP38_GPIO,
- MPP39_GPIO,
- MPP40_GPIO,
- MPP41_GPIO,
- MPP42_GPIO,
- MPP43_GPIO,
- MPP44_GPIO,
- MPP45_GPIO,
- MPP46_GPIO,
- MPP47_GPIO,
- MPP48_GPIO,
- MPP49_GPIO,
- 0
-};
-
-static struct gpio_keys_button tswxl_buttons[] = {
- {
- .code = KEY_OPTION,
- .gpio = TSWXL_AUTO_SWITCH,
- .desc = "Power-auto Switch",
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_platform_data tswxl_button_data = {
- .buttons = tswxl_buttons,
- .nbuttons = ARRAY_SIZE(tswxl_buttons),
-};
-
-static struct platform_device tswxl_button_device = {
- .name = "gpio-keys",
- .id = -1,
- .num_resources = 0,
- .dev = {
- .platform_data = &tswxl_button_data,
- },
-};
-
-static void __init wxl_init(void)
-{
- /*
- * Basic MV78xx0 setup. Needs to be called early.
- */
- mv78xx0_init();
- mv78xx0_mpp_conf(wxl_mpp_config);
-
- /*
- * Partition on-chip peripherals between the two CPU cores.
- */
- mv78xx0_ehci0_init();
- mv78xx0_ehci1_init();
- mv78xx0_ge00_init(&db78x00_ge00_data);
- mv78xx0_ge01_init(&db78x00_ge01_data);
- mv78xx0_sata_init(&db78x00_sata_data);
- mv78xx0_uart0_init();
- mv78xx0_uart1_init();
- mv78xx0_uart2_init();
- mv78xx0_uart3_init();
- mv78xx0_xor_init();
- mv78xx0_crypto_init();
- mv78xx0_i2c_init();
- i2c_register_board_info(0, &db78x00_i2c_rtc, 1);
-
- //enable both usb ports
- gpio_direction_output(TSWXL_USB_POWER1, 1);
- gpio_direction_output(TSWXL_USB_POWER2, 1);
-
- //enable rear switch
- platform_device_register(&tswxl_button_device);
-}
-
-static int __init wxl_pci_init(void)
-{
- if (machine_is_terastation_wxl() && mv78xx0_core_index() == 0)
- mv78xx0_pcie_init(1, 1);
-
- return 0;
-}
-subsys_initcall(wxl_pci_init);
-
-MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL")
- /* Maintainer: Sebastien Requiem <sebastien@requiem.fr> */
- .atag_offset = 0x100,
- .nr_irqs = MV78XX0_NR_IRQS,
- .init_machine = wxl_init,
- .map_io = mv78xx0_map_io,
- .init_early = mv78xx0_init_early,
- .init_irq = mv78xx0_init_irq,
- .init_time = mv78xx0_timer_init,
- .restart = mv78xx0_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
deleted file mode 100644
index 679753fcc0ef..000000000000
--- a/arch/arm/mach-mv78xx0/common.c
+++ /dev/null
@@ -1,444 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-mv78xx0/common.c
- *
- * Core functions for Marvell MV78xx0 SoCs
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/ata_platform.h>
-#include <linux/clk-provider.h>
-#include <linux/ethtool.h>
-#include <asm/hardware/cache-feroceon-l2.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-#include <linux/platform_data/usb-ehci-orion.h>
-#include <linux/platform_data/mtd-orion_nand.h>
-#include <plat/time.h>
-#include <plat/common.h>
-#include <plat/addr-map.h>
-#include "mv78xx0.h"
-#include "bridge-regs.h"
-#include "common.h"
-
-static int get_tclk(void);
-
-/*****************************************************************************
- * Common bits
- ****************************************************************************/
-int mv78xx0_core_index(void)
-{
- u32 extra;
-
- /*
- * Read Extra Features register.
- */
- __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
-
- return !!(extra & 0x00004000);
-}
-
-static int get_hclk(void)
-{
- int hclk;
-
- /*
- * HCLK tick rate is configured by DEV_D[7:5] pins.
- */
- switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
- case 0:
- hclk = 166666667;
- break;
- case 1:
- hclk = 200000000;
- break;
- case 2:
- hclk = 266666667;
- break;
- case 3:
- hclk = 333333333;
- break;
- case 4:
- hclk = 400000000;
- break;
- default:
- panic("unknown HCLK PLL setting: %.8x\n",
- readl(SAMPLE_AT_RESET_LOW));
- }
-
- return hclk;
-}
-
-static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
-{
- u32 cfg;
-
- /*
- * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
- * PCLK/L2CLK by bits [19:14].
- */
- if (core_index == 0) {
- cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
- } else {
- cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
- }
-
- /*
- * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
- * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
- */
- *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
-
- /*
- * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
- * ratio (1, 2, 3).
- */
- *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
-}
-
-static int get_tclk(void)
-{
- int tclk_freq;
-
- /*
- * TCLK tick rate is configured by DEV_A[2:0] strap pins.
- */
- switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
- case 1:
- tclk_freq = 166666667;
- break;
- case 3:
- tclk_freq = 200000000;
- break;
- default:
- panic("unknown TCLK PLL setting: %.8x\n",
- readl(SAMPLE_AT_RESET_HIGH));
- }
-
- return tclk_freq;
-}
-
-
-/*****************************************************************************
- * I/O Address Mapping
- ****************************************************************************/
-static struct map_desc mv78xx0_io_desc[] __initdata = {
- {
- .virtual = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
- .pfn = 0,
- .length = MV78XX0_CORE_REGS_SIZE,
- .type = MT_DEVICE,
- }, {
- .virtual = (unsigned long) MV78XX0_REGS_VIRT_BASE,
- .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
- .length = MV78XX0_REGS_SIZE,
- .type = MT_DEVICE,
- },
-};
-
-void __init mv78xx0_map_io(void)
-{
- unsigned long phys;
-
- /*
- * Map the right set of per-core registers depending on
- * which core we are running on.
- */
- if (mv78xx0_core_index() == 0) {
- phys = MV78XX0_CORE0_REGS_PHYS_BASE;
- } else {
- phys = MV78XX0_CORE1_REGS_PHYS_BASE;
- }
- mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
-
- iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
-}
-
-
-/*****************************************************************************
- * CLK tree
- ****************************************************************************/
-static struct clk *tclk;
-
-static void __init clk_init(void)
-{
- tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, get_tclk());
-
- orion_clkdev_init(tclk);
-}
-
-/*****************************************************************************
- * EHCI
- ****************************************************************************/
-void __init mv78xx0_ehci0_init(void)
-{
- orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
-}
-
-
-/*****************************************************************************
- * EHCI1
- ****************************************************************************/
-void __init mv78xx0_ehci1_init(void)
-{
- orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
-}
-
-
-/*****************************************************************************
- * EHCI2
- ****************************************************************************/
-void __init mv78xx0_ehci2_init(void)
-{
- orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
-}
-
-
-/*****************************************************************************
- * GE00
- ****************************************************************************/
-void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
-{
- orion_ge00_init(eth_data,
- GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
- IRQ_MV78XX0_GE_ERR,
- MV643XX_TX_CSUM_DEFAULT_LIMIT);
-}
-
-
-/*****************************************************************************
- * GE01
- ****************************************************************************/
-void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
-{
- orion_ge01_init(eth_data,
- GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
- MV643XX_TX_CSUM_DEFAULT_LIMIT);
-}
-
-
-/*****************************************************************************
- * GE10
- ****************************************************************************/
-void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
-{
- u32 dev, rev;
-
- /*
- * On the Z0, ge10 and ge11 are internally connected back
- * to back, and not brought out.
- */
- mv78xx0_pcie_id(&dev, &rev);
- if (dev == MV78X00_Z0_DEV_ID) {
- eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
- eth_data->speed = SPEED_1000;
- eth_data->duplex = DUPLEX_FULL;
- }
-
- orion_ge10_init(eth_data, GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM);
-}
-
-
-/*****************************************************************************
- * GE11
- ****************************************************************************/
-void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
-{
- u32 dev, rev;
-
- /*
- * On the Z0, ge10 and ge11 are internally connected back
- * to back, and not brought out.
- */
- mv78xx0_pcie_id(&dev, &rev);
- if (dev == MV78X00_Z0_DEV_ID) {
- eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
- eth_data->speed = SPEED_1000;
- eth_data->duplex = DUPLEX_FULL;
- }
-
- orion_ge11_init(eth_data, GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM);
-}
-
-/*****************************************************************************
- * I2C
- ****************************************************************************/
-void __init mv78xx0_i2c_init(void)
-{
- orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
- orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
-}
-
-/*****************************************************************************
- * SATA
- ****************************************************************************/
-void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
-{
- orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
-}
-
-
-/*****************************************************************************
- * UART0
- ****************************************************************************/
-void __init mv78xx0_uart0_init(void)
-{
- orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
- IRQ_MV78XX0_UART_0, tclk);
-}
-
-
-/*****************************************************************************
- * UART1
- ****************************************************************************/
-void __init mv78xx0_uart1_init(void)
-{
- orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
- IRQ_MV78XX0_UART_1, tclk);
-}
-
-
-/*****************************************************************************
- * UART2
- ****************************************************************************/
-void __init mv78xx0_uart2_init(void)
-{
- orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
- IRQ_MV78XX0_UART_2, tclk);
-}
-
-/*****************************************************************************
- * UART3
- ****************************************************************************/
-void __init mv78xx0_uart3_init(void)
-{
- orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
- IRQ_MV78XX0_UART_3, tclk);
-}
-
-/*****************************************************************************
- * Time handling
- ****************************************************************************/
-void __init mv78xx0_init_early(void)
-{
- orion_time_set_base(TIMER_VIRT_BASE);
- if (mv78xx0_core_index() == 0)
- mvebu_mbus_init("marvell,mv78xx0-mbus",
- BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ,
- DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ);
- else
- mvebu_mbus_init("marvell,mv78xx0-mbus",
- BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ,
- DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ);
-}
-
-void __ref mv78xx0_timer_init(void)
-{
- orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
- IRQ_MV78XX0_TIMER_1, get_tclk());
-}
-
-/****************************************************************************
-* XOR engine
-****************************************************************************/
-void __init mv78xx0_xor_init(void)
-{
- orion_xor0_init(XOR_PHYS_BASE,
- XOR_PHYS_BASE + 0x200,
- IRQ_MV78XX0_XOR_0, IRQ_MV78XX0_XOR_1);
-}
-
-/****************************************************************************
- * Cryptographic Engines and Security Accelerator (CESA)
-****************************************************************************/
-void __init mv78xx0_crypto_init(void)
-{
- mvebu_mbus_add_window_by_id(MV78XX0_MBUS_SRAM_TARGET,
- MV78XX0_MBUS_SRAM_ATTR,
- MV78XX0_SRAM_PHYS_BASE,
- MV78XX0_SRAM_SIZE);
- orion_crypto_init(CRYPTO_PHYS_BASE, MV78XX0_SRAM_PHYS_BASE,
- SZ_8K, IRQ_MV78XX0_CRYPTO);
-}
-
-
-/*****************************************************************************
- * General
- ****************************************************************************/
-static char * __init mv78xx0_id(void)
-{
- u32 dev, rev;
-
- mv78xx0_pcie_id(&dev, &rev);
-
- if (dev == MV78X00_Z0_DEV_ID) {
- if (rev == MV78X00_REV_Z0)
- return "MV78X00-Z0";
- else
- return "MV78X00-Rev-Unsupported";
- } else if (dev == MV78100_DEV_ID) {
- if (rev == MV78100_REV_A0)
- return "MV78100-A0";
- else if (rev == MV78100_REV_A1)
- return "MV78100-A1";
- else
- return "MV78100-Rev-Unsupported";
- } else if (dev == MV78200_DEV_ID) {
- if (rev == MV78100_REV_A0)
- return "MV78200-A0";
- else
- return "MV78200-Rev-Unsupported";
- } else {
- return "Device-Unknown";
- }
-}
-
-static int __init is_l2_writethrough(void)
-{
- return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
-}
-
-void __init mv78xx0_init(void)
-{
- int core_index;
- int hclk;
- int pclk;
- int l2clk;
-
- core_index = mv78xx0_core_index();
- hclk = get_hclk();
- get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
-
- printk(KERN_INFO "%s ", mv78xx0_id());
- printk("core #%d, ", core_index);
- printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
- printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
- printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
- printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
-
- if (IS_ENABLED(CONFIG_CACHE_FEROCEON_L2))
- feroceon_l2_init(is_l2_writethrough());
-
- /* Setup root of clk tree */
- clk_init();
-}
-
-void mv78xx0_restart(enum reboot_mode mode, const char *cmd)
-{
- /*
- * Enable soft reset to assert RSTOUTn.
- */
- writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
-
- /*
- * Assert soft reset.
- */
- writel(SOFT_RESET, SYSTEM_SOFT_RESET);
-
- while (1)
- ;
-}
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
deleted file mode 100644
index 9f1dfd595003..000000000000
--- a/arch/arm/mach-mv78xx0/common.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-mv78xx0/common.h
- *
- * Core functions for Marvell MV78xx0 SoCs
- */
-
-#ifndef __ARCH_MV78XX0_COMMON_H
-#define __ARCH_MV78XX0_COMMON_H
-
-#include <linux/reboot.h>
-
-struct mv643xx_eth_platform_data;
-struct mv_sata_platform_data;
-
-/*
- * Basic MV78xx0 init functions used early by machine-setup.
- */
-int mv78xx0_core_index(void);
-void mv78xx0_map_io(void);
-void mv78xx0_init(void);
-void mv78xx0_init_early(void);
-void mv78xx0_init_irq(void);
-
-void mv78xx0_setup_cpu_mbus(void);
-void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
- int maj, int min);
-void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
- int maj, int min);
-
-void mv78xx0_pcie_id(u32 *dev, u32 *rev);
-
-void mv78xx0_ehci0_init(void);
-void mv78xx0_ehci1_init(void);
-void mv78xx0_ehci2_init(void);
-void mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data);
-void mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data);
-void mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data);
-void mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data);
-void mv78xx0_pcie_init(int init_port0, int init_port1);
-void mv78xx0_sata_init(struct mv_sata_platform_data *sata_data);
-void mv78xx0_uart0_init(void);
-void mv78xx0_uart1_init(void);
-void mv78xx0_uart2_init(void);
-void mv78xx0_uart3_init(void);
-void mv78xx0_xor_init(void);
-void mv78xx0_crypto_init(void);
-void mv78xx0_i2c_init(void);
-void mv78xx0_restart(enum reboot_mode, const char *);
-
-extern void mv78xx0_timer_init(void);
-
-
-#endif
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
deleted file mode 100644
index 6e42f6446637..000000000000
--- a/arch/arm/mach-mv78xx0/irq.c
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-mv78xx0/irq.c
- *
- * MV78xx0 IRQ handling.
- */
-#include <linux/gpio/consumer.h>
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <asm/exception.h>
-#include <plat/orion-gpio.h>
-#include <plat/irq.h>
-#include "bridge-regs.h"
-#include "common.h"
-
-static int __initdata gpio0_irqs[4] = {
- IRQ_MV78XX0_GPIO_0_7,
- IRQ_MV78XX0_GPIO_8_15,
- IRQ_MV78XX0_GPIO_16_23,
- IRQ_MV78XX0_GPIO_24_31,
-};
-
-static void __iomem *mv78xx0_irq_base = IRQ_VIRT_BASE;
-
-static asmlinkage void
-__exception_irq_entry mv78xx0_legacy_handle_irq(struct pt_regs *regs)
-{
- u32 stat;
-
- stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_LOW_OFF);
- stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_LOW_OFF);
- if (stat) {
- unsigned int hwirq = __fls(stat);
- handle_IRQ(hwirq, regs);
- return;
- }
- stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_HIGH_OFF);
- stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_HIGH_OFF);
- if (stat) {
- unsigned int hwirq = 32 + __fls(stat);
- handle_IRQ(hwirq, regs);
- return;
- }
- stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_ERR_OFF);
- stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_ERR_OFF);
- if (stat) {
- unsigned int hwirq = 64 + __fls(stat);
- handle_IRQ(hwirq, regs);
- return;
- }
-}
-
-void __init mv78xx0_init_irq(void)
-{
- orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
- orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
- orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
-
- set_handle_irq(mv78xx0_legacy_handle_irq);
-
- /*
- * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask
- * registers for core #1 are at an offset of 0x18 from those of
- * core #0.)
- */
- orion_gpio_init(0, 32, GPIO_VIRT_BASE, mv78xx0_core_index() ? 0x18 : 0,
- IRQ_MV78XX0_GPIO_START, gpio0_irqs);
-}
diff --git a/arch/arm/mach-mv78xx0/irqs.h b/arch/arm/mach-mv78xx0/irqs.h
deleted file mode 100644
index 12b357d383d8..000000000000
--- a/arch/arm/mach-mv78xx0/irqs.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* IRQ definitions for Marvell MV78xx0 SoCs */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-/*
- * MV78xx0 Low Interrupt Controller
- */
-#define IRQ_MV78XX0_ERR 0
-#define IRQ_MV78XX0_SPI 1
-#define IRQ_MV78XX0_I2C_0 2
-#define IRQ_MV78XX0_I2C_1 3
-#define IRQ_MV78XX0_IDMA_0 4
-#define IRQ_MV78XX0_IDMA_1 5
-#define IRQ_MV78XX0_IDMA_2 6
-#define IRQ_MV78XX0_IDMA_3 7
-#define IRQ_MV78XX0_TIMER_0 8
-#define IRQ_MV78XX0_TIMER_1 9
-#define IRQ_MV78XX0_TIMER_2 10
-#define IRQ_MV78XX0_TIMER_3 11
-#define IRQ_MV78XX0_UART_0 12
-#define IRQ_MV78XX0_UART_1 13
-#define IRQ_MV78XX0_UART_2 14
-#define IRQ_MV78XX0_UART_3 15
-#define IRQ_MV78XX0_USB_0 16
-#define IRQ_MV78XX0_USB_1 17
-#define IRQ_MV78XX0_USB_2 18
-#define IRQ_MV78XX0_CRYPTO 19
-#define IRQ_MV78XX0_SDIO_0 20
-#define IRQ_MV78XX0_SDIO_1 21
-#define IRQ_MV78XX0_XOR_0 22
-#define IRQ_MV78XX0_XOR_1 23
-#define IRQ_MV78XX0_I2S_0 24
-#define IRQ_MV78XX0_I2S_1 25
-#define IRQ_MV78XX0_SATA 26
-#define IRQ_MV78XX0_TDMI 27
-
-/*
- * MV78xx0 High Interrupt Controller
- */
-#define IRQ_MV78XX0_PCIE_00 32
-#define IRQ_MV78XX0_PCIE_01 33
-#define IRQ_MV78XX0_PCIE_02 34
-#define IRQ_MV78XX0_PCIE_03 35
-#define IRQ_MV78XX0_PCIE_10 36
-#define IRQ_MV78XX0_PCIE_11 37
-#define IRQ_MV78XX0_PCIE_12 38
-#define IRQ_MV78XX0_PCIE_13 39
-#define IRQ_MV78XX0_GE00_SUM 40
-#define IRQ_MV78XX0_GE00_RX 41
-#define IRQ_MV78XX0_GE00_TX 42
-#define IRQ_MV78XX0_GE00_MISC 43
-#define IRQ_MV78XX0_GE01_SUM 44
-#define IRQ_MV78XX0_GE01_RX 45
-#define IRQ_MV78XX0_GE01_TX 46
-#define IRQ_MV78XX0_GE01_MISC 47
-#define IRQ_MV78XX0_GE10_SUM 48
-#define IRQ_MV78XX0_GE10_RX 49
-#define IRQ_MV78XX0_GE10_TX 50
-#define IRQ_MV78XX0_GE10_MISC 51
-#define IRQ_MV78XX0_GE11_SUM 52
-#define IRQ_MV78XX0_GE11_RX 53
-#define IRQ_MV78XX0_GE11_TX 54
-#define IRQ_MV78XX0_GE11_MISC 55
-#define IRQ_MV78XX0_GPIO_0_7 56
-#define IRQ_MV78XX0_GPIO_8_15 57
-#define IRQ_MV78XX0_GPIO_16_23 58
-#define IRQ_MV78XX0_GPIO_24_31 59
-#define IRQ_MV78XX0_DB_IN 60
-#define IRQ_MV78XX0_DB_OUT 61
-
-/*
- * MV78xx0 Error Interrupt Controller
- */
-#define IRQ_MV78XX0_GE_ERR 70
-
-/*
- * MV78XX0 General Purpose Pins
- */
-#define IRQ_MV78XX0_GPIO_START 96
-#define NR_GPIO_IRQS 32
-
-#define MV78XX0_NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
-
-
-#endif
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
deleted file mode 100644
index 32bf590d79fe..000000000000
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-mv78x00/mpp.c
- *
- * MPP functions for Marvell MV78x00 SoCs
- */
-#include <linux/gpio/consumer.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <plat/mpp.h>
-#include "mv78xx0.h"
-#include "common.h"
-#include "mpp.h"
-
-static unsigned int __init mv78xx0_variant(void)
-{
- u32 dev, rev;
-
- mv78xx0_pcie_id(&dev, &rev);
-
- if (dev == MV78100_DEV_ID && rev >= MV78100_REV_A0)
- return MPP_78100_A0_MASK;
-
- printk(KERN_ERR "MPP setup: unknown mv78x00 variant "
- "(dev %#x rev %#x)\n", dev, rev);
- return 0;
-}
-
-void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
-{
- orion_mpp_conf(mpp_list, mv78xx0_variant(),
- MPP_MAX, DEV_BUS_VIRT_BASE);
-}
diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h
deleted file mode 100644
index 47db52f45546..000000000000
--- a/arch/arm/mach-mv78xx0/mpp.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * linux/arch/arm/mach-mv78xx0/mpp.h -- Multi Purpose Pins
- *
- * sebastien requiem <sebastien@requiem.fr>
- */
-
-#ifndef __MV78X00_MPP_H
-#define __MV78X00_MPP_H
-
-#define MPP(_num, _sel, _in, _out, _78100_A0) (\
- /* MPP number */ ((_num) & 0xff) | \
- /* MPP select value */ (((_sel) & 0xf) << 8) | \
- /* may be input signal */ ((!!(_in)) << 12) | \
- /* may be output signal */ ((!!(_out)) << 13) | \
- /* available on A0 */ ((!!(_78100_A0)) << 14))
-
- /* num sel i o 78100_A0 */
-
-#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1)
-
-#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1)
-#define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1)
-#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1)
-#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1)
-
-#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1)
-#define MPP1_GE0_RXERR MPP(1, 0x1, 0, 0, 1)
-#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1)
-#define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1)
-
-#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1)
-#define MPP2_GE0_CRS MPP(2, 0x1, 0, 0, 1)
-#define MPP2_GE1_RXCTL MPP(2, 0x2, 0, 0, 1)
-#define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1)
-
-#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1)
-#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 0, 1)
-#define MPP3_GE1_RXCLK MPP(3, 0x2, 0, 0, 1)
-#define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1)
-
-#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1)
-#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 0, 1)
-#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 0, 1)
-#define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1)
-
-#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1)
-#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 0, 1)
-#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 0, 1)
-#define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1)
-
-#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1)
-#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 0, 1)
-#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 0, 1)
-#define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1)
-
-#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1)
-#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 0, 1)
-#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 0, 1)
-#define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1)
-
-#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1)
-#define MPP8_GE0_RXD4 MPP(8, 0x1, 0, 0, 1)
-#define MPP8_GE1_RXD0 MPP(8, 0x2, 0, 0, 1)
-#define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1)
-
-#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1)
-#define MPP9_GE0_RXD5 MPP(9, 0x1, 0, 0, 1)
-#define MPP9_GE1_RXD1 MPP(9, 0x2, 0, 0, 1)
-#define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1)
-
-#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1)
-#define MPP10_GE0_RXD6 MPP(10, 0x1, 0, 0, 1)
-#define MPP10_GE1_RXD2 MPP(10, 0x2, 0, 0, 1)
-#define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1)
-
-#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1)
-#define MPP11_GE0_RXD7 MPP(11, 0x1, 0, 0, 1)
-#define MPP11_GE1_RXD3 MPP(11, 0x2, 0, 0, 1)
-#define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1)
-
-#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1)
-#define MPP12_M_BB MPP(12, 0x3, 0, 0, 1)
-#define MPP12_UA0_CTSn MPP(12, 0x4, 0, 0, 1)
-#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 0, 1)
-#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 0, 1)
-#define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1)
-
-#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1)
-#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 0, 1)
-#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 0, 1)
-#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 0, 1)
-#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 0, 1)
-#define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1)
-
-#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1)
-#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 0, 1)
-#define MPP14_UA1_CTSn MPP(14, 0x4, 0, 0, 1)
-#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 0, 1)
-#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 0, 1)
-#define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1)
-
-#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1)
-#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 0, 1)
-#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 0, 1)
-#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 0, 1)
-#define MPP15_TDM_SMISO MPP(15, 0x6, 0, 0, 1)
-#define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1)
-
-#define MPP16_GPIO MPP(16, 0x0, 1, 1, 1)
-#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 0, 1)
-#define MPP16_UA2_TXD MPP(16, 0x4, 0, 0, 1)
-#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 0, 1)
-#define MPP16_TDM_INTn MPP(16, 0x6, 0, 0, 1)
-#define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1)
-
-
-#define MPP17_GPIO MPP(17, 0x0, 1, 1, 1)
-#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 0, 1)
-#define MPP17_UA2_RXD MPP(17, 0x4, 0, 0, 1)
-#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 0, 1)
-#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 0, 1)
-#define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1)
-
-
-#define MPP18_GPIO MPP(18, 0x0, 1, 1, 1)
-#define MPP18_UA0_CTSn MPP(18, 0x4, 0, 0, 1)
-#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 0, 1)
-#define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1)
-
-
-
-#define MPP19_GPIO MPP(19, 0x0, 1, 1, 1)
-#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 0, 1)
-#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 0, 1)
-#define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1)
-
-
-#define MPP20_GPIO MPP(20, 0x0, 1, 1, 1)
-#define MPP20_UA1_CTSs MPP(20, 0x4, 0, 0, 1)
-#define MPP20_TDM_PCLK MPP(20, 0x6, 0, 0, 0)
-#define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1)
-
-
-
-#define MPP21_GPIO MPP(21, 0x0, 1, 1, 1)
-#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 0, 1)
-#define MPP21_TDM_FSYNC MPP(21, 0x6, 0, 0, 0)
-#define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1)
-
-
-
-#define MPP22_GPIO MPP(22, 0x0, 1, 1, 1)
-#define MPP22_UA3_TDX MPP(22, 0x4, 0, 0, 1)
-#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 0, 1)
-#define MPP22_TDM_DRX MPP(22, 0x6, 0, 0, 1)
-#define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1)
-
-
-
-#define MPP23_GPIO MPP(23, 0x0, 1, 1, 1)
-#define MPP23_UA3_RDX MPP(23, 0x4, 0, 0, 1)
-#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 0, 1)
-#define MPP23_TDM_DTX MPP(23, 0x6, 0, 0, 1)
-#define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1)
-
-
-#define MPP24_GPIO MPP(24, 0x0, 1, 1, 1)
-#define MPP24_UA2_TXD MPP(24, 0x4, 0, 0, 1)
-#define MPP24_TDM_INTn MPP(24, 0x6, 0, 0, 1)
-#define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1)
-
-
-#define MPP25_GPIO MPP(25, 0x0, 1, 1, 1)
-#define MPP25_UA2_RXD MPP(25, 0x4, 0, 0, 1)
-#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 0, 1)
-#define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1)
-
-
-#define MPP26_GPIO MPP(26, 0x0, 1, 1, 1)
-#define MPP26_UA2_CTSn MPP(26, 0x4, 0, 0, 1)
-#define MPP26_TDM_PCLK MPP(26, 0x6, 0, 0, 1)
-#define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1)
-
-
-#define MPP27_GPIO MPP(27, 0x0, 1, 1, 1)
-#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 0, 1)
-#define MPP27_TDM_FSYNC MPP(27, 0x6, 0, 0, 1)
-#define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1)
-
-
-#define MPP28_GPIO MPP(28, 0x0, 1, 1, 1)
-#define MPP28_UA3_TXD MPP(28, 0x4, 0, 0, 1)
-#define MPP28_TDM_DRX MPP(28, 0x6, 0, 0, 1)
-#define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1)
-
-#define MPP29_GPIO MPP(29, 0x0, 1, 1, 1)
-#define MPP29_UA3_RXD MPP(29, 0x4, 0, 0, 1)
-#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 0, 1)
-#define MPP29_TDM_DTX MPP(29, 0x6, 0, 0, 1)
-#define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1)
-
-#define MPP30_GPIO MPP(30, 0x0, 1, 1, 1)
-#define MPP30_UA3_CTSn MPP(30, 0x4, 0, 0, 1)
-#define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1)
-
-#define MPP31_GPIO MPP(31, 0x0, 1, 1, 1)
-#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 0, 1)
-#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 0, 1)
-#define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1)
-
-
-#define MPP32_GPIO MPP(32, 0x1, 1, 1, 1)
-#define MPP32_UA3_TDX MPP(32, 0x4, 0, 0, 1)
-#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 0, 1)
-#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 0, 1)
-#define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1)
-
-
-#define MPP33_GPIO MPP(33, 0x1, 1, 1, 1)
-#define MPP33_UA3_RDX MPP(33, 0x4, 0, 0, 1)
-#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 0, 1)
-#define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1)
-
-
-
-#define MPP34_GPIO MPP(34, 0x1, 1, 1, 1)
-#define MPP34_UA2_TDX MPP(34, 0x4, 0, 0, 1)
-#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 0, 1)
-#define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1)
-
-
-
-#define MPP35_GPIO MPP(35, 0x1, 1, 1, 1)
-#define MPP35_UA2_RDX MPP(35, 0x4, 0, 0, 1)
-#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 0, 1)
-#define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1)
-
-#define MPP36_GPIO MPP(36, 0x1, 1, 1, 1)
-#define MPP36_UA0_CTSn MPP(36, 0x2, 0, 0, 1)
-#define MPP36_UA2_TDX MPP(36, 0x4, 0, 0, 1)
-#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 0, 1)
-#define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1)
-
-
-#define MPP37_GPIO MPP(37, 0x1, 1, 1, 1)
-#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 0, 1)
-#define MPP37_UA2_RXD MPP(37, 0x4, 0, 0, 1)
-#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 0, 1)
-#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 0, 1)
-#define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1)
-
-
-
-
-#define MPP38_GPIO MPP(38, 0x1, 1, 1, 1)
-#define MPP38_UA1_CTSn MPP(38, 0x2, 0, 0, 1)
-#define MPP38_UA3_TXD MPP(38, 0x4, 0, 0, 1)
-#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 0, 1)
-#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 0, 1)
-#define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1)
-
-
-
-
-#define MPP39_GPIO MPP(39, 0x1, 1, 1, 1)
-#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 0, 1)
-#define MPP39_UA3_RXD MPP(39, 0x4, 0, 0, 1)
-#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 0, 1)
-#define MPP39_TDM_SMISO MPP(39, 0x6, 0, 0, 1)
-#define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1)
-
-
-
-#define MPP40_GPIO MPP(40, 0x1, 1, 1, 1)
-#define MPP40_TDM_INTn MPP(40, 0x6, 0, 0, 1)
-#define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1)
-
-
-
-#define MPP41_GPIO MPP(41, 0x1, 1, 1, 1)
-#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 0, 1)
-#define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1)
-
-
-
-#define MPP42_GPIO MPP(42, 0x1, 1, 1, 1)
-#define MPP42_TDM_PCLK MPP(42, 0x6, 0, 0, 1)
-#define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1)
-
-
-
-#define MPP43_GPIO MPP(43, 0x1, 1, 1, 1)
-#define MPP43_TDM_FSYNC MPP(43, 0x6, 0, 0, 1)
-#define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1)
-
-
-
-#define MPP44_GPIO MPP(44, 0x1, 1, 1, 1)
-#define MPP44_TDM_DRX MPP(44, 0x6, 0, 0, 1)
-#define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1)
-
-
-
-#define MPP45_GPIO MPP(45, 0x1, 1, 1, 1)
-#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 0, 1)
-#define MPP45_TDM_DRX MPP(45, 0x6, 0, 0, 1)
-#define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1)
-
-
-#define MPP46_GPIO MPP(46, 0x1, 1, 1, 1)
-#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 0, 1)
-#define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1)
-
-
-#define MPP47_GPIO MPP(47, 0x1, 1, 1, 1)
-#define MPP47_UNUSED MPP(47, 0x0, 0, 0, 1)
-
-
-
-#define MPP48_GPIO MPP(48, 0x1, 1, 1, 1)
-#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 0, 1)
-#define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1)
-
-
-
-#define MPP49_GPIO MPP(49, 0x1, 1, 1, 1)
-#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 0, 1)
-#define MPP49_M_BB MPP(49, 0x4, 0, 0, 1)
-#define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1)
-
-
-#define MPP_MAX 49
-
-void mv78xx0_mpp_conf(unsigned int *mpp_list);
-
-#endif
diff --git a/arch/arm/mach-mv78xx0/mv78xx0.h b/arch/arm/mach-mv78xx0/mv78xx0.h
deleted file mode 100644
index 88efb1e44142..000000000000
--- a/arch/arm/mach-mv78xx0/mv78xx0.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Generic definitions for Marvell MV78xx0 SoC flavors:
- * MV781x0 and MV782x0.
- */
-
-#ifndef __ASM_ARCH_MV78XX0_H
-#define __ASM_ARCH_MV78XX0_H
-
-#include "irqs.h"
-
-/*
- * Marvell MV78xx0 address maps.
- *
- * phys
- * c0000000 PCIe Memory space
- * f0800000 PCIe #0 I/O space
- * f0900000 PCIe #1 I/O space
- * f0a00000 PCIe #2 I/O space
- * f0b00000 PCIe #3 I/O space
- * f0c00000 PCIe #4 I/O space
- * f0d00000 PCIe #5 I/O space
- * f0e00000 PCIe #6 I/O space
- * f0f00000 PCIe #7 I/O space
- * f1000000 on-chip peripheral registers
- *
- * virt phys size
- * fe400000 f102x000 16K core-specific peripheral registers
- * fee00000 f0800000 64K PCIe #0 I/O space
- * fee10000 f0900000 64K PCIe #1 I/O space
- * fee20000 f0a00000 64K PCIe #2 I/O space
- * fee30000 f0b00000 64K PCIe #3 I/O space
- * fee40000 f0c00000 64K PCIe #4 I/O space
- * fee50000 f0d00000 64K PCIe #5 I/O space
- * fee60000 f0e00000 64K PCIe #6 I/O space
- * fee70000 f0f00000 64K PCIe #7 I/O space
- * fec00000 f1000000 1M on-chip peripheral registers
- */
-#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
-#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
-#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
-#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
-#define MV78XX0_CORE_REGS_SIZE SZ_16K
-
-#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
-#define MV78XX0_PCIE_IO_SIZE SZ_1M
-
-#define MV78XX0_REGS_PHYS_BASE 0xf1000000
-#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
-#define MV78XX0_REGS_SIZE SZ_1M
-
-#define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
-#define MV78XX0_SRAM_SIZE SZ_8K
-
-#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
-#define MV78XX0_PCIE_MEM_SIZE 0x30000000
-
-#define MV78XX0_MBUS_SRAM_TARGET 0x09
-#define MV78XX0_MBUS_SRAM_ATTR 0x00
-
-/*
- * Core-specific peripheral registers.
- */
-#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
-#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE)
-#define BRIDGE_WINS_CPU0_BASE (MV78XX0_CORE0_REGS_PHYS_BASE)
-#define BRIDGE_WINS_CPU1_BASE (MV78XX0_CORE1_REGS_PHYS_BASE)
-#define BRIDGE_WINS_SZ (0xA000)
-
-/*
- * Register Map
- */
-#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000)
-#define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000)
-#define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500)
-#define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570)
-#define DDR_WINDOW_CPU_SZ (0x20)
-
-#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000)
-#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000)
-#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030)
-#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034)
-#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
-#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
-#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100)
-#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
-#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
-#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
-#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
-#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200)
-#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200)
-#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300)
-#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300)
-
-#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000)
-#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000)
-
-#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000)
-#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000)
-#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000)
-#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000)
-
-#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000)
-#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000)
-#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000)
-
-#define XOR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x60900)
-
-#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000)
-#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000)
-
-#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000)
-#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000)
-#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000)
-#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000)
-
-#define CRYPTO_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x90000)
-
-#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000)
-
-/*
- * Supported devices and revisions.
- */
-#define MV78X00_Z0_DEV_ID 0x6381
-#define MV78X00_REV_Z0 1
-
-#define MV78100_DEV_ID 0x7810
-#define MV78100_REV_A0 1
-#define MV78100_REV_A1 2
-
-#define MV78200_DEV_ID 0x7820
-#define MV78200_REV_A0 1
-
-#endif
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
deleted file mode 100644
index 533cb7856943..000000000000
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ /dev/null
@@ -1,280 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-mv78xx0/pcie.c
- *
- * PCIe functions for Marvell MV78xx0 SoCs
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/mbus.h>
-#include <video/vga.h>
-#include <asm/irq.h>
-#include <asm/mach/pci.h>
-#include <plat/pcie.h>
-#include "mv78xx0.h"
-#include "common.h"
-
-#define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4)
-#define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane)))
-#define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4)
-#define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane)))
-
-struct pcie_port {
- u8 maj;
- u8 min;
- u8 root_bus_nr;
- void __iomem *base;
- spinlock_t conf_lock;
- char mem_space_name[20];
- struct resource res;
-};
-
-static struct pcie_port pcie_port[8];
-static int num_pcie_ports;
-static struct resource pcie_io_space;
-
-void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
-{
- *dev = orion_pcie_dev_id(PCIE00_VIRT_BASE);
- *rev = orion_pcie_rev(PCIE00_VIRT_BASE);
-}
-
-u32 pcie_port_size[8] = {
- 0,
- 0x20000000,
- 0x10000000,
- 0x10000000,
- 0x08000000,
- 0x08000000,
- 0x08000000,
- 0x04000000,
-};
-
-static void __init mv78xx0_pcie_preinit(void)
-{
- int i;
- u32 size_each;
- u32 start;
-
- pcie_io_space.name = "PCIe I/O Space";
- pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
- pcie_io_space.end =
- MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
- pcie_io_space.flags = IORESOURCE_MEM;
- if (request_resource(&iomem_resource, &pcie_io_space))
- panic("can't allocate PCIe I/O space");
-
- if (num_pcie_ports > 7)
- panic("invalid number of PCIe ports");
-
- size_each = pcie_port_size[num_pcie_ports];
-
- start = MV78XX0_PCIE_MEM_PHYS_BASE;
- for (i = 0; i < num_pcie_ports; i++) {
- struct pcie_port *pp = pcie_port + i;
-
- snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
- "PCIe %d.%d MEM", pp->maj, pp->min);
- pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
- pp->res.name = pp->mem_space_name;
- pp->res.flags = IORESOURCE_MEM;
- pp->res.start = start;
- pp->res.end = start + size_each - 1;
- start += size_each;
-
- if (request_resource(&iomem_resource, &pp->res))
- panic("can't allocate PCIe MEM sub-space");
-
- mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min),
- MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min),
- pp->res.start, resource_size(&pp->res));
- mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min),
- MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min),
- i * SZ_64K, SZ_64K, 0);
- }
-}
-
-static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
-{
- struct pcie_port *pp;
- struct resource realio;
-
- if (nr >= num_pcie_ports)
- return 0;
-
- pp = &pcie_port[nr];
- sys->private_data = pp;
- pp->root_bus_nr = sys->busnr;
-
- /*
- * Generic PCIe unit setup.
- */
- orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
- orion_pcie_setup(pp->base);
-
- realio.start = nr * SZ_64K;
- realio.end = realio.start + SZ_64K - 1;
- pci_remap_iospace(&realio, MV78XX0_PCIE_IO_PHYS_BASE(nr));
-
- pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
-
- return 1;
-}
-
-static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
-{
- /*
- * Don't go out when trying to access nonexisting devices
- * on the local bus.
- */
- if (bus == pp->root_bus_nr && dev > 1)
- return 0;
-
- return 1;
-}
-
-static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
- int size, u32 *val)
-{
- struct pci_sys_data *sys = bus->sysdata;
- struct pcie_port *pp = sys->private_data;
- unsigned long flags;
- int ret;
-
- if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
- *val = 0xffffffff;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
- spin_lock_irqsave(&pp->conf_lock, flags);
- ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
- spin_unlock_irqrestore(&pp->conf_lock, flags);
-
- return ret;
-}
-
-static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
- int where, int size, u32 val)
-{
- struct pci_sys_data *sys = bus->sysdata;
- struct pcie_port *pp = sys->private_data;
- unsigned long flags;
- int ret;
-
- if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- spin_lock_irqsave(&pp->conf_lock, flags);
- ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
- spin_unlock_irqrestore(&pp->conf_lock, flags);
-
- return ret;
-}
-
-static struct pci_ops pcie_ops = {
- .read = pcie_rd_conf,
- .write = pcie_wr_conf,
-};
-
-/*
- * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
- * is operating as a root complex this needs to be switched to
- * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
- * the device. Decoding setup is handled by the orion code.
- */
-static void rc_pci_fixup(struct pci_dev *dev)
-{
- if (dev->bus->parent == NULL && dev->devfn == 0) {
- struct resource *r;
-
- dev->class &= 0xff;
- dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
- pci_dev_for_each_resource(dev, r) {
- r->start = 0;
- r->end = 0;
- r->flags = 0;
- }
- }
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
-
-static int __init mv78xx0_pcie_scan_bus(int nr, struct pci_host_bridge *bridge)
-{
- struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
-
- if (nr >= num_pcie_ports) {
- BUG();
- return -EINVAL;
- }
-
- list_splice_init(&sys->resources, &bridge->windows);
- bridge->dev.parent = NULL;
- bridge->sysdata = sys;
- bridge->busnr = sys->busnr;
- bridge->ops = &pcie_ops;
-
- return pci_scan_root_bus_bridge(bridge);
-}
-
-static int __init mv78xx0_pcie_map_irq(const struct pci_dev *dev, u8 slot,
- u8 pin)
-{
- struct pci_sys_data *sys = dev->bus->sysdata;
- struct pcie_port *pp = sys->private_data;
-
- return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min;
-}
-
-static struct hw_pci mv78xx0_pci __initdata = {
- .nr_controllers = 8,
- .preinit = mv78xx0_pcie_preinit,
- .setup = mv78xx0_pcie_setup,
- .scan = mv78xx0_pcie_scan_bus,
- .map_irq = mv78xx0_pcie_map_irq,
-};
-
-static void __init add_pcie_port(int maj, int min, void __iomem *base)
-{
- printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
-
- if (orion_pcie_link_up(base)) {
- struct pcie_port *pp = &pcie_port[num_pcie_ports++];
-
- printk("link up\n");
-
- pp->maj = maj;
- pp->min = min;
- pp->root_bus_nr = -1;
- pp->base = base;
- spin_lock_init(&pp->conf_lock);
- memset(&pp->res, 0, sizeof(pp->res));
- } else {
- printk("link down, ignoring\n");
- }
-}
-
-void __init mv78xx0_pcie_init(int init_port0, int init_port1)
-{
- vga_base = MV78XX0_PCIE_MEM_PHYS_BASE;
-
- if (init_port0) {
- add_pcie_port(0, 0, PCIE00_VIRT_BASE);
- if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) {
- add_pcie_port(0, 1, PCIE01_VIRT_BASE);
- add_pcie_port(0, 2, PCIE02_VIRT_BASE);
- add_pcie_port(0, 3, PCIE03_VIRT_BASE);
- }
- }
-
- if (init_port1) {
- add_pcie_port(1, 0, PCIE10_VIRT_BASE);
- if (!orion_pcie_x4_mode((void __iomem *)PCIE10_VIRT_BASE)) {
- add_pcie_port(1, 1, PCIE11_VIRT_BASE);
- add_pcie_port(1, 2, PCIE12_VIRT_BASE);
- add_pcie_port(1, 3, PCIE13_VIRT_BASE);
- }
- }
-
- pci_common_init(&mv78xx0_pci);
-}
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index c61999d01c80..78b8d59d7cc1 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -37,60 +37,6 @@ config MACH_RD88F5182_DT
Say 'Y' here if you want your kernel to support the Marvell
Orion-NAS (88F5182) RD2, Flattened Device Tree.
-config MACH_KUROBOX_PRO
- bool "KuroBox Pro (DEPRECATED)"
- select I2C_BOARDINFO if I2C
- depends on ATAGS
- help
- Say 'Y' here if you want your kernel to support the
- KuroBox Pro platform.
-
- Support for this machine will go away in early 2027,
- unless it gets converted to device tree.
-
-config MACH_DNS323
- bool "D-Link DNS-323 (DEPRECATED)"
- select I2C_BOARDINFO if I2C
- depends on ATAGS
- help
- Say 'Y' here if you want your kernel to support the
- D-Link DNS-323 platform.
-
- Support for this machine will go away in early 2027,
- unless it gets converted to device tree.
-
-config MACH_TS209
- bool "QNAP TS-109/TS-209 (DEPRECATED)"
- depends on ATAGS
- help
- Say 'Y' here if you want your kernel to support the
- QNAP TS-109/TS-209 platform.
-
- Support for this machine will go away in early 2027,
- unless it gets converted to device tree.
-
-config MACH_TERASTATION_PRO2
- bool "Buffalo Terastation Pro II/Live (DEPRECATED)"
- depends on ATAGS
- help
- Say 'Y' here if you want your kernel to support the
- Buffalo Terastation Pro II/Live platform.
-
- Support for this machine will go away in early 2027,
- unless it gets converted to device tree.
-
-config MACH_LINKSTATION_PRO
- bool "Buffalo Linkstation Pro/Live (DEPRECATED)"
- depends on ATAGS
- select I2C_BOARDINFO if I2C
- help
- Say 'Y' here if you want your kernel to support the
- Buffalo Linkstation Pro/Live platform. Both v1 and
- v2 devices are supported.
-
- Support for this machine will go away in early 2027,
- unless it gets converted to device tree.
-
config MACH_LINKSTATION_MINI
bool "Buffalo Linkstation Mini (Flattened Device Tree)"
select ARCH_ORION5X_DT
@@ -98,36 +44,6 @@ config MACH_LINKSTATION_MINI
Say 'Y' here if you want your kernel to support the
Buffalo Linkstation Mini (LS-WSGL) platform.
-config MACH_TS409
- bool "QNAP TS-409 (DEPRECATED)"
- depends on ATAGS
- help
- Say 'Y' here if you want your kernel to support the
- QNAP TS-409 platform.
-
- Support for this machine will go away in early 2027,
- unless it gets converted to device tree.
-
-config MACH_TS78XX
- bool "Technologic Systems TS-78xx (DEPRECATED)"
- depends on ATAGS
- help
- Say 'Y' here if you want your kernel to support the
- Technologic Systems TS-78xx platform.
-
- Support for this machine will go away in early 2027,
- unless it gets converted to device tree.
-
-config MACH_MV2120
- bool "HP Media Vault mv2120 (DEPRECATED)"
- depends on ATAGS
- help
- Say 'Y' here if you want your kernel to support the
- HP Media Vault mv2120 or mv5100.
-
- Support for this machine will go away in early 2027,
- unless it gets converted to device tree.
-
config MACH_D2NET_DT
bool "LaCie d2 Network / Big Disk Network (Flattened Device Tree)"
select ARCH_ORION5X_DT
@@ -135,17 +51,6 @@ config MACH_D2NET_DT
Say 'Y' here if you want your kernel to support the
LaCie d2 Network NAS.
-config MACH_NET2BIG
- bool "LaCie 2Big Network (DEPRECATED)"
- depends on ATAGS
- select I2C_BOARDINFO if I2C
- help
- Say 'Y' here if you want your kernel to support the
- LaCie 2Big Network NAS.
-
- Support for this machine will go away in early 2027,
- unless it gets converted to device tree.
-
config MACH_MSS2_DT
bool "Maxtor Shared Storage II (Flattened Device Tree)"
select ARCH_ORION5X_DT
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 6f54d7fef27a..7e9634e04318 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -2,15 +2,6 @@
ccflags-y := -I$(srctree)/arch/arm/plat-orion/include
obj-y += common.o pci.o irq.o mpp.o
-obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o
-obj-$(CONFIG_MACH_TERASTATION_PRO2) += terastation_pro2-setup.o
-obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o
-obj-$(CONFIG_MACH_DNS323) += dns323-setup.o
-obj-$(CONFIG_MACH_TS209) += ts209-setup.o tsx09-common.o
-obj-$(CONFIG_MACH_TS409) += ts409-setup.o tsx09-common.o
-obj-$(CONFIG_MACH_TS78XX) += ts78xx-setup.o
-obj-$(CONFIG_MACH_MV2120) += mv2120-setup.o
-obj-$(CONFIG_MACH_NET2BIG) += net2big-setup.o
obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o
obj-$(CONFIG_MACH_D2NET_DT) += board-d2net.o
diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
index be47492c6640..2614213e2cbc 100644
--- a/arch/arm/mach-orion5x/board-dt.c
+++ b/arch/arm/mach-orion5x/board-dt.c
@@ -18,7 +18,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <plat/irq.h>
-#include <plat/time.h>
#include "orion5x.h"
#include "bridge-regs.h"
#include "common.h"
@@ -39,7 +38,7 @@ static void __init orion5x_dt_init(void)
u32 dev, rev;
orion5x_id(&dev, &rev, &dev_name);
- printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
+ printk(KERN_INFO "Orion ID: %s.\n", dev_name);
BUG_ON(mvebu_mbus_dt_init(false));
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index df056d60b675..050a95af2bbf 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -7,27 +7,16 @@
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*/
+#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/serial_8250.h>
-#include <linux/mv643xx_i2c.h>
-#include <linux/ata_platform.h>
-#include <linux/delay.h>
-#include <linux/clk-provider.h>
-#include <linux/cpu.h>
+#include <linux/mbus.h>
#include <asm/page.h>
#include <asm/setup.h>
-#include <asm/system_misc.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
-#include <linux/platform_data/mtd-orion_nand.h>
-#include <linux/platform_data/usb-ehci-orion.h>
-#include <plat/time.h>
-#include <plat/common.h>
#include "bridge-regs.h"
#include "common.h"
@@ -55,167 +44,6 @@ void __init orion5x_map_io(void)
iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
}
-
-/*****************************************************************************
- * CLK tree
- ****************************************************************************/
-static struct clk *tclk;
-
-void __init clk_init(void)
-{
- tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, orion5x_tclk);
-
- orion_clkdev_init(tclk);
-}
-
-/*****************************************************************************
- * EHCI0
- ****************************************************************************/
-void __init orion5x_ehci0_init(void)
-{
- orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
- EHCI_PHY_ORION);
-}
-
-
-/*****************************************************************************
- * EHCI1
- ****************************************************************************/
-void __init orion5x_ehci1_init(void)
-{
- orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
-}
-
-
-/*****************************************************************************
- * GE00
- ****************************************************************************/
-void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
-{
- orion_ge00_init(eth_data,
- ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
- IRQ_ORION5X_ETH_ERR,
- MV643XX_TX_CSUM_DEFAULT_LIMIT);
-}
-
-
-/*****************************************************************************
- * I2C
- ****************************************************************************/
-void __init orion5x_i2c_init(void)
-{
- orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
-
-}
-
-
-/*****************************************************************************
- * SATA
- ****************************************************************************/
-void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
-{
- orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
-}
-
-
-/*****************************************************************************
- * SPI
- ****************************************************************************/
-void __init orion5x_spi_init(void)
-{
- orion_spi_init(SPI_PHYS_BASE);
-}
-
-
-/*****************************************************************************
- * UART0
- ****************************************************************************/
-void __init orion5x_uart0_init(void)
-{
- orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
- IRQ_ORION5X_UART0, tclk);
-}
-
-/*****************************************************************************
- * UART1
- ****************************************************************************/
-void __init orion5x_uart1_init(void)
-{
- orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
- IRQ_ORION5X_UART1, tclk);
-}
-
-/*****************************************************************************
- * XOR engine
- ****************************************************************************/
-void __init orion5x_xor_init(void)
-{
- orion_xor0_init(ORION5X_XOR_PHYS_BASE,
- ORION5X_XOR_PHYS_BASE + 0x200,
- IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
-}
-
-/*****************************************************************************
- * Cryptographic Engines and Security Accelerator (CESA)
- ****************************************************************************/
-static void __init orion5x_crypto_init(void)
-{
- mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET,
- ORION_MBUS_SRAM_ATTR,
- ORION5X_SRAM_PHYS_BASE,
- ORION5X_SRAM_SIZE);
- orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
- SZ_8K, IRQ_ORION5X_CESA);
-}
-
-/*****************************************************************************
- * Watchdog
- ****************************************************************************/
-static struct resource orion_wdt_resource[] = {
- DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
- DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
-};
-
-static struct platform_device orion_wdt_device = {
- .name = "orion_wdt",
- .id = -1,
- .num_resources = ARRAY_SIZE(orion_wdt_resource),
- .resource = orion_wdt_resource,
-};
-
-static void __init orion5x_wdt_init(void)
-{
- platform_device_register(&orion_wdt_device);
-}
-
-
-/*****************************************************************************
- * Time handling
- ****************************************************************************/
-void __init orion5x_init_early(void)
-{
- u32 rev, dev;
- const char *mbus_soc_name;
-
- orion_time_set_base(TIMER_VIRT_BASE);
-
- /* Initialize the MBUS driver */
- orion5x_pcie_id(&dev, &rev);
- if (dev == MV88F5281_DEV_ID)
- mbus_soc_name = "marvell,orion5x-88f5281-mbus";
- else if (dev == MV88F5182_DEV_ID)
- mbus_soc_name = "marvell,orion5x-88f5182-mbus";
- else if (dev == MV88F5181_DEV_ID)
- mbus_soc_name = "marvell,orion5x-88f5181-mbus";
- else if (dev == MV88F6183_DEV_ID)
- mbus_soc_name = "marvell,orion5x-88f6183-mbus";
- else
- mbus_soc_name = NULL;
- mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE,
- ORION5X_BRIDGE_WINS_SZ,
- ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ);
-}
-
void orion5x_setup_wins(void)
{
/*
@@ -242,29 +70,6 @@ void orion5x_setup_wins(void)
ORION5X_PCI_MEM_SIZE);
}
-int orion5x_tclk;
-
-static int __init orion5x_find_tclk(void)
-{
- u32 dev, rev;
-
- orion5x_pcie_id(&dev, &rev);
- if (dev == MV88F6183_DEV_ID &&
- (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
- return 133333333;
-
- return 166666667;
-}
-
-void __init orion5x_timer_init(void)
-{
- orion5x_tclk = orion5x_find_tclk();
-
- orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
- IRQ_ORION5X_BRIDGE, orion5x_tclk);
-}
-
-
/*****************************************************************************
* General
****************************************************************************/
@@ -310,45 +115,6 @@ void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
}
}
-void __init orion5x_init(void)
-{
- char *dev_name;
- u32 dev, rev;
-
- orion5x_id(&dev, &rev, &dev_name);
- printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
-
- /*
- * Setup Orion address map
- */
- orion5x_setup_wins();
-
- /* Setup root of clk tree */
- clk_init();
-
- /*
- * Don't issue "Wait for Interrupt" instruction if we are
- * running on D0 5281 silicon.
- */
- if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
- printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
- cpu_idle_poll_ctrl(true);
- }
-
- /*
- * The 5082/5181l/5182/6082/6082l/6183 have crypto
- * while 5180n/5181/5281 don't have crypto.
- */
- if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
- dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
- orion5x_crypto_init();
-
- /*
- * Register watchdog driver
- */
- orion5x_wdt_init();
-}
-
void orion5x_restart(enum reboot_mode mode, const char *cmd)
{
/*
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 8df70e23aa82..4dc6c59bde99 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -4,9 +4,6 @@
#include <linux/reboot.h>
-struct mv643xx_eth_platform_data;
-struct mv_sata_platform_data;
-
#define ORION_MBUS_PCIE_MEM_TARGET 0x04
#define ORION_MBUS_PCIE_MEM_ATTR 0x59
#define ORION_MBUS_PCIE_IO_TARGET 0x04
@@ -32,21 +29,9 @@ void orion5x_init_early(void);
void orion5x_init_irq(void);
void orion5x_init(void);
void orion5x_id(u32 *dev, u32 *rev, char **dev_name);
-void clk_init(void);
-extern int orion5x_tclk;
-extern void orion5x_timer_init(void);
void orion5x_setup_wins(void);
-void orion5x_ehci0_init(void);
-void orion5x_ehci1_init(void);
-void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
-void orion5x_i2c_init(void);
-void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
-void orion5x_spi_init(void);
-void orion5x_uart0_init(void);
-void orion5x_uart1_init(void);
-void orion5x_xor_init(void);
void orion5x_restart(enum reboot_mode, const char *);
/*
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
deleted file mode 100644
index 7b81b08b0dda..000000000000
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ /dev/null
@@ -1,757 +0,0 @@
-/*
- * arch/arm/mach-orion5x/dns323-setup.c
- *
- * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
- *
- * Support for HW Rev C1:
- *
- * Copyright (C) 2010 Benjamin Herrenschmidt <benh@kernel.crashing.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- */
-#include <linux/gpio/legacy.h>
-#include <linux/gpio/machine.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/leds.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/ata_platform.h>
-#include <linux/phy.h>
-#include <linux/marvell_phy.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include <asm/system_info.h>
-#include <plat/orion-gpio.h>
-#include "orion5x.h"
-#include "common.h"
-#include "mpp.h"
-
-/* Rev A1 and B1 */
-#define DNS323_GPIO_LED_RIGHT_AMBER 1
-#define DNS323_GPIO_LED_LEFT_AMBER 2
-#define DNS323_GPIO_SYSTEM_UP 3
-#define DNS323_GPIO_LED_POWER1 4
-#define DNS323_GPIO_LED_POWER2 5
-#define DNS323_GPIO_OVERTEMP 6
-#define DNS323_GPIO_RTC 7
-#define DNS323_GPIO_POWER_OFF 8
-#define DNS323_GPIO_KEY_POWER 9
-#define DNS323_GPIO_KEY_RESET 10
-
-/* Rev C1 */
-#define DNS323C_GPIO_KEY_POWER 1
-#define DNS323C_GPIO_POWER_OFF 2
-#define DNS323C_GPIO_LED_RIGHT_AMBER 8
-#define DNS323C_GPIO_LED_LEFT_AMBER 9
-#define DNS323C_GPIO_LED_POWER 17
-#define DNS323C_GPIO_FAN_BIT1 18
-#define DNS323C_GPIO_FAN_BIT0 19
-
-/* Exposed to userspace, do not change */
-enum {
- DNS323_REV_A1, /* 0 */
- DNS323_REV_B1, /* 1 */
- DNS323_REV_C1, /* 2 */
-};
-
-
-/****************************************************************************
- * PCI setup
- */
-
-static int __init dns323_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq;
-
- /*
- * Check for devices with hard-wired IRQs.
- */
- irq = orion5x_pci_map_irq(dev, slot, pin);
- if (irq != -1)
- return irq;
-
- return -1;
-}
-
-static struct hw_pci dns323_pci __initdata = {
- .nr_controllers = 2,
- .setup = orion5x_pci_sys_setup,
- .scan = orion5x_pci_sys_scan_bus,
- .map_irq = dns323_pci_map_irq,
-};
-
-static int __init dns323_pci_init(void)
-{
- /* Rev B1 and C1 doesn't really use its PCI bus, and initialising PCI
- * gets in the way of initialising the SATA controller.
- */
- if (machine_is_dns323() && system_rev == DNS323_REV_A1)
- pci_common_init(&dns323_pci);
-
- return 0;
-}
-
-subsys_initcall(dns323_pci_init);
-
-/****************************************************************************
- * 8MiB NOR flash (Spansion S29GL064M90TFIR4)
- *
- * Layout as used by D-Link:
- * 0x00000000-0x00010000 : "MTD1"
- * 0x00010000-0x00020000 : "MTD2"
- * 0x00020000-0x001a0000 : "Linux Kernel"
- * 0x001a0000-0x007d0000 : "File System"
- * 0x007d0000-0x00800000 : "u-boot"
- */
-
-#define DNS323_NOR_BOOT_BASE 0xf4000000
-#define DNS323_NOR_BOOT_SIZE SZ_8M
-
-static struct mtd_partition dns323_partitions[] = {
- {
- .name = "MTD1",
- .size = 0x00010000,
- .offset = 0,
- }, {
- .name = "MTD2",
- .size = 0x00010000,
- .offset = 0x00010000,
- }, {
- .name = "Linux Kernel",
- .size = 0x00180000,
- .offset = 0x00020000,
- }, {
- .name = "File System",
- .size = 0x00630000,
- .offset = 0x001A0000,
- }, {
- .name = "u-boot",
- .size = 0x00030000,
- .offset = 0x007d0000,
- },
-};
-
-static struct physmap_flash_data dns323_nor_flash_data = {
- .width = 1,
- .parts = dns323_partitions,
- .nr_parts = ARRAY_SIZE(dns323_partitions)
-};
-
-static struct resource dns323_nor_flash_resource = {
- .flags = IORESOURCE_MEM,
- .start = DNS323_NOR_BOOT_BASE,
- .end = DNS323_NOR_BOOT_BASE + DNS323_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device dns323_nor_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &dns323_nor_flash_data,
- },
- .resource = &dns323_nor_flash_resource,
- .num_resources = 1,
-};
-
-/****************************************************************************
- * Ethernet
- */
-
-static struct mv643xx_eth_platform_data dns323_eth_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
-};
-
-/* dns323_parse_hex_*() taken from tsx09-common.c; should a common copy of these
- * functions be kept somewhere?
- */
-static int __init dns323_parse_hex_nibble(char n)
-{
- if (n >= '0' && n <= '9')
- return n - '0';
-
- if (n >= 'A' && n <= 'F')
- return n - 'A' + 10;
-
- if (n >= 'a' && n <= 'f')
- return n - 'a' + 10;
-
- return -1;
-}
-
-static int __init dns323_parse_hex_byte(const char *b)
-{
- int hi;
- int lo;
-
- hi = dns323_parse_hex_nibble(b[0]);
- lo = dns323_parse_hex_nibble(b[1]);
-
- if (hi < 0 || lo < 0)
- return -1;
-
- return (hi << 4) | lo;
-}
-
-static int __init dns323_read_mac_addr(void)
-{
- u_int8_t addr[6];
- int i;
- char *mac_page;
-
- /* MAC address is stored as a regular ol' string in /dev/mtdblock4
- * (0x007d0000-0x00800000) starting at offset 196480 (0x2ff80).
- */
- mac_page = ioremap(DNS323_NOR_BOOT_BASE + 0x7d0000 + 196480, 1024);
- if (!mac_page)
- return -ENOMEM;
-
- /* Sanity check the string we're looking at */
- for (i = 0; i < 5; i++) {
- if (*(mac_page + (i * 3) + 2) != ':') {
- goto error_fail;
- }
- }
-
- for (i = 0; i < 6; i++) {
- int byte;
-
- byte = dns323_parse_hex_byte(mac_page + (i * 3));
- if (byte < 0) {
- goto error_fail;
- }
-
- addr[i] = byte;
- }
-
- iounmap(mac_page);
- printk("DNS-323: Found ethernet MAC address: %pM\n", addr);
-
- memcpy(dns323_eth_data.mac_addr, addr, 6);
-
- return 0;
-
-error_fail:
- iounmap(mac_page);
- return -EINVAL;
-}
-
-/****************************************************************************
- * GPIO LEDs (simple - doesn't use hardware blinking support)
- */
-
-static struct gpio_led dns323ab_leds[] = {
- {
- .name = "power:blue",
- .default_trigger = "default-on",
- }, {
- .name = "right:amber",
- }, {
- .name = "left:amber",
- },
-};
-
-static struct gpiod_lookup_table dns323a1_leds_gpio_table = {
- .dev_id = "leds-gpio",
- .table = {
- GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_POWER2, NULL,
- 0, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_RIGHT_AMBER, NULL,
- 1, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_LEFT_AMBER, NULL,
- 2, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-/* B1 is the same but power LED is active high */
-static struct gpiod_lookup_table dns323b1_leds_gpio_table = {
- .dev_id = "leds-gpio",
- .table = {
- GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_POWER2, NULL,
- 0, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_RIGHT_AMBER, NULL,
- 1, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_LEFT_AMBER, NULL,
- 2, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct gpio_led dns323c_leds[] = {
- {
- .name = "power:blue",
- .default_trigger = "timer",
- }, {
- .name = "right:amber",
- }, {
- .name = "left:amber",
- },
-};
-
-static struct gpiod_lookup_table dns323c_leds_gpio_table = {
- .dev_id = "leds-gpio",
- .table = {
- GPIO_LOOKUP_IDX("orion_gpio0", DNS323C_GPIO_LED_POWER, NULL,
- 0, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("orion_gpio0", DNS323C_GPIO_LED_RIGHT_AMBER, NULL,
- 1, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("orion_gpio0", DNS323C_GPIO_LED_LEFT_AMBER, NULL,
- 2, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct gpio_led_platform_data dns323ab_led_data = {
- .num_leds = ARRAY_SIZE(dns323ab_leds),
- .leds = dns323ab_leds,
- .gpio_blink_set = orion_gpio_led_blink_set,
-};
-
-static struct gpio_led_platform_data dns323c_led_data = {
- .num_leds = ARRAY_SIZE(dns323c_leds),
- .leds = dns323c_leds,
- .gpio_blink_set = orion_gpio_led_blink_set,
-};
-
-static struct platform_device dns323_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &dns323ab_led_data,
- },
-};
-
-/****************************************************************************
- * GPIO Attached Keys
- */
-
-static struct gpio_keys_button dns323ab_buttons[] = {
- {
- .code = KEY_RESTART,
- .gpio = DNS323_GPIO_KEY_RESET,
- .desc = "Reset Button",
- .active_low = 1,
- }, {
- .code = KEY_POWER,
- .gpio = DNS323_GPIO_KEY_POWER,
- .desc = "Power Button",
- .active_low = 1,
- },
-};
-
-static struct gpio_keys_platform_data dns323ab_button_data = {
- .buttons = dns323ab_buttons,
- .nbuttons = ARRAY_SIZE(dns323ab_buttons),
-};
-
-static struct gpio_keys_button dns323c_buttons[] = {
- {
- .code = KEY_POWER,
- .gpio = DNS323C_GPIO_KEY_POWER,
- .desc = "Power Button",
- .active_low = 1,
- },
-};
-
-static struct gpio_keys_platform_data dns323c_button_data = {
- .buttons = dns323c_buttons,
- .nbuttons = ARRAY_SIZE(dns323c_buttons),
-};
-
-static struct platform_device dns323_button_device = {
- .name = "gpio-keys",
- .id = -1,
- .num_resources = 0,
- .dev = {
- .platform_data = &dns323ab_button_data,
- },
-};
-
-/*****************************************************************************
- * SATA
- */
-static struct mv_sata_platform_data dns323_sata_data = {
- .n_ports = 2,
-};
-
-/****************************************************************************
- * General Setup
- */
-static unsigned int dns323a_mpp_modes[] __initdata = {
- MPP0_PCIE_RST_OUTn,
- MPP1_GPIO, /* right amber LED (sata ch0) */
- MPP2_GPIO, /* left amber LED (sata ch1) */
- MPP3_UNUSED,
- MPP4_GPIO, /* power button LED */
- MPP5_GPIO, /* power button LED */
- MPP6_GPIO, /* GMT G751-2f overtemp */
- MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */
- MPP8_GPIO, /* triggers power off */
- MPP9_GPIO, /* power button switch */
- MPP10_GPIO, /* reset button switch */
- MPP11_UNUSED,
- MPP12_UNUSED,
- MPP13_UNUSED,
- MPP14_UNUSED,
- MPP15_UNUSED,
- MPP16_UNUSED,
- MPP17_UNUSED,
- MPP18_UNUSED,
- MPP19_UNUSED,
- 0,
-};
-
-static unsigned int dns323b_mpp_modes[] __initdata = {
- MPP0_UNUSED,
- MPP1_GPIO, /* right amber LED (sata ch0) */
- MPP2_GPIO, /* left amber LED (sata ch1) */
- MPP3_GPIO, /* system up flag */
- MPP4_GPIO, /* power button LED */
- MPP5_GPIO, /* power button LED */
- MPP6_GPIO, /* GMT G751-2f overtemp */
- MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */
- MPP8_GPIO, /* triggers power off */
- MPP9_GPIO, /* power button switch */
- MPP10_GPIO, /* reset button switch */
- MPP11_UNUSED,
- MPP12_SATA_LED,
- MPP13_SATA_LED,
- MPP14_SATA_LED,
- MPP15_SATA_LED,
- MPP16_UNUSED,
- MPP17_UNUSED,
- MPP18_UNUSED,
- MPP19_UNUSED,
- 0,
-};
-
-static unsigned int dns323c_mpp_modes[] __initdata = {
- MPP0_GPIO, /* ? input */
- MPP1_GPIO, /* input power switch (0 = pressed) */
- MPP2_GPIO, /* output power off */
- MPP3_UNUSED, /* ? output */
- MPP4_UNUSED, /* ? output */
- MPP5_UNUSED, /* ? output */
- MPP6_UNUSED, /* ? output */
- MPP7_UNUSED, /* ? output */
- MPP8_GPIO, /* i/o right amber LED */
- MPP9_GPIO, /* i/o left amber LED */
- MPP10_GPIO, /* input */
- MPP11_UNUSED,
- MPP12_SATA_LED,
- MPP13_SATA_LED,
- MPP14_SATA_LED,
- MPP15_SATA_LED,
- MPP16_UNUSED,
- MPP17_GPIO, /* power button LED */
- MPP18_GPIO, /* fan speed bit 0 */
- MPP19_GPIO, /* fan speed bit 1 */
- 0,
-};
-
-/* Rev C1 Fan speed notes:
- *
- * The fan is controlled by 2 GPIOs on this board. The settings
- * of the bits is as follow:
- *
- * GPIO 18 GPIO 19 Fan
- *
- * 0 0 stopped
- * 0 1 low speed
- * 1 0 high speed
- * 1 1 don't do that (*)
- *
- * (*) I think the two bits control two feed-in resistors into a fixed
- * PWN circuit, setting both bits will basically go a 'bit' faster
- * than high speed, but d-link doesn't do it and you may get out of
- * HW spec so don't do it.
- */
-
-/*
- * On the DNS-323 A1 and B1 the following devices are attached via I2C:
- *
- * i2c addr | chip | description
- * 0x3e | GMT G760Af | fan speed PWM controller
- * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
- * 0x68 | ST M41T80 | RTC w/ alarm
- */
-static struct i2c_board_info __initdata dns323ab_i2c_devices[] = {
- {
- I2C_BOARD_INFO("g760a", 0x3e),
- }, {
- I2C_BOARD_INFO("lm75", 0x48),
- }, {
- I2C_BOARD_INFO("m41t80", 0x68),
- },
-};
-
-/*
- * On the DNS-323 C1 the following devices are attached via I2C:
- *
- * i2c addr | chip | description
- * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
- * 0x68 | ST M41T80 | RTC w/ alarm
- */
-static struct i2c_board_info __initdata dns323c_i2c_devices[] = {
- {
- I2C_BOARD_INFO("lm75", 0x48),
- }, {
- I2C_BOARD_INFO("m41t80", 0x68),
- },
-};
-
-/* DNS-323 rev. A specific power off method */
-static void dns323a_power_off(void)
-{
- pr_info("DNS-323: Triggering power-off...\n");
- gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
-}
-
-/* DNS-323 rev B specific power off method */
-static void dns323b_power_off(void)
-{
- pr_info("DNS-323: Triggering power-off...\n");
- /* Pin has to be changed to 1 and back to 0 to do actual power off. */
- gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
- mdelay(100);
- gpio_set_value(DNS323_GPIO_POWER_OFF, 0);
-}
-
-/* DNS-323 rev. C specific power off method */
-static void dns323c_power_off(void)
-{
- pr_info("DNS-323: Triggering power-off...\n");
- gpio_set_value(DNS323C_GPIO_POWER_OFF, 1);
-}
-
-static int dns323c_phy_fixup(struct phy_device *phy)
-{
- phy->dev_flags |= MARVELL_PHY_M1118_DNS323_LEDS;
-
- return 0;
-}
-
-static int __init dns323_identify_rev(void)
-{
- u32 dev, rev, i, reg;
-
- pr_debug("DNS-323: Identifying board ... \n");
-
- /* Rev A1 has a 5181 */
- orion5x_pcie_id(&dev, &rev);
- if (dev == MV88F5181_DEV_ID) {
- pr_debug("DNS-323: 5181 found, board is A1\n");
- return DNS323_REV_A1;
- }
- pr_debug("DNS-323: 5182 found, board is B1 or C1, checking PHY...\n");
-
- /* Rev B1 and C1 both have 5182, let's poke at the eth PHY. This is
- * a bit gross but we want to do that without links into the eth
- * driver so let's poke at it directly. We default to rev B1 in
- * case the accesses fail
- */
-
-#define ETH_SMI_REG (ORION5X_ETH_VIRT_BASE + 0x2000 + 0x004)
-#define SMI_BUSY 0x10000000
-#define SMI_READ_VALID 0x08000000
-#define SMI_OPCODE_READ 0x04000000
-#define SMI_OPCODE_WRITE 0x00000000
-
- for (i = 0; i < 1000; i++) {
- reg = readl(ETH_SMI_REG);
- if (!(reg & SMI_BUSY))
- break;
- }
- if (i >= 1000) {
- pr_warn("DNS-323: Timeout accessing PHY, assuming rev B1\n");
- return DNS323_REV_B1;
- }
- writel((3 << 21) /* phy ID reg */ |
- (8 << 16) /* phy addr */ |
- SMI_OPCODE_READ, ETH_SMI_REG);
- for (i = 0; i < 1000; i++) {
- reg = readl(ETH_SMI_REG);
- if (reg & SMI_READ_VALID)
- break;
- }
- if (i >= 1000) {
- pr_warn("DNS-323: Timeout reading PHY, assuming rev B1\n");
- return DNS323_REV_B1;
- }
- pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff);
-
- /* Note: the Marvell tools mask the ID with 0x3f0 before comparison
- * but I don't see that making a difference here, at least with
- * any known Marvell PHY ID
- */
- switch(reg & 0xfff0) {
- case 0x0cc0: /* MV88E1111 */
- return DNS323_REV_B1;
- case 0x0e10: /* MV88E1118 */
- return DNS323_REV_C1;
- default:
- pr_warn("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n",
- reg & 0xffff);
- }
- return DNS323_REV_B1;
-}
-
-static void __init dns323_init(void)
-{
- /* Setup basic Orion functions. Need to be called early. */
- orion5x_init();
-
- /* Identify revision */
- system_rev = dns323_identify_rev();
- pr_info("DNS-323: Identified HW revision %c1\n", 'A' + system_rev);
-
- /* Just to be tricky, the 5182 has a completely different
- * set of MPP modes to the 5181.
- */
- switch(system_rev) {
- case DNS323_REV_A1:
- orion5x_mpp_conf(dns323a_mpp_modes);
- writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */
- break;
- case DNS323_REV_B1:
- orion5x_mpp_conf(dns323b_mpp_modes);
- break;
- case DNS323_REV_C1:
- orion5x_mpp_conf(dns323c_mpp_modes);
- break;
- }
-
- /* setup flash mapping
- * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
- */
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
- ORION_MBUS_DEVBUS_BOOT_ATTR,
- DNS323_NOR_BOOT_BASE,
- DNS323_NOR_BOOT_SIZE);
- platform_device_register(&dns323_nor_flash);
-
- /* Sort out LEDs, Buttons and i2c devices */
- switch(system_rev) {
- case DNS323_REV_A1:
- /* The 5181 power LED is active low and requires
- * DNS323_GPIO_LED_POWER1 to also be low.
- */
- gpiod_add_lookup_table(&dns323a1_leds_gpio_table);
- gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
- gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
- i2c_register_board_info(0, dns323ab_i2c_devices,
- ARRAY_SIZE(dns323ab_i2c_devices));
-
- break;
- case DNS323_REV_B1:
- gpiod_add_lookup_table(&dns323b1_leds_gpio_table);
- i2c_register_board_info(0, dns323ab_i2c_devices,
- ARRAY_SIZE(dns323ab_i2c_devices));
- break;
- case DNS323_REV_C1:
- /* Hookup LEDs & Buttons */
- gpiod_add_lookup_table(&dns323c_leds_gpio_table);
- dns323_gpio_leds.dev.platform_data = &dns323c_led_data;
- dns323_button_device.dev.platform_data = &dns323c_button_data;
-
- /* Hookup i2c devices and fan driver */
- i2c_register_board_info(0, dns323c_i2c_devices,
- ARRAY_SIZE(dns323c_i2c_devices));
- platform_device_register_simple("dns323c-fan", 0, NULL, 0);
-
- /* Register fixup for the PHY LEDs */
- if (!IS_BUILTIN(CONFIG_PHYLIB))
- break;
- phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118,
- MARVELL_PHY_ID_MASK,
- dns323c_phy_fixup);
- }
-
- platform_device_register(&dns323_gpio_leds);
- platform_device_register(&dns323_button_device);
-
- /*
- * Configure peripherals.
- */
- if (dns323_read_mac_addr() < 0)
- printk("DNS-323: Failed to read MAC address\n");
- orion5x_ehci0_init();
- orion5x_eth_init(&dns323_eth_data);
- orion5x_i2c_init();
- orion5x_uart0_init();
-
- /* Remaining GPIOs */
- switch(system_rev) {
- case DNS323_REV_A1:
- /* Poweroff GPIO */
- if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
- gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
- pr_err("DNS-323: failed to setup power-off GPIO\n");
- register_platform_power_off(dns323a_power_off);
- break;
- case DNS323_REV_B1:
- /* 5182 built-in SATA init */
- orion5x_sata_init(&dns323_sata_data);
-
- /* The DNS323 rev B1 has flag to indicate the system is up.
- * Without this flag set, power LED will flash and cannot be
- * controlled via leds-gpio.
- */
- if (gpio_request(DNS323_GPIO_SYSTEM_UP, "SYS_READY") == 0)
- gpio_direction_output(DNS323_GPIO_SYSTEM_UP, 1);
-
- /* Poweroff GPIO */
- if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
- gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
- pr_err("DNS-323: failed to setup power-off GPIO\n");
- register_platform_power_off(dns323b_power_off);
- break;
- case DNS323_REV_C1:
- /* 5182 built-in SATA init */
- orion5x_sata_init(&dns323_sata_data);
-
- /* Poweroff GPIO */
- if (gpio_request(DNS323C_GPIO_POWER_OFF, "POWEROFF") != 0 ||
- gpio_direction_output(DNS323C_GPIO_POWER_OFF, 0) != 0)
- pr_err("DNS-323: failed to setup power-off GPIO\n");
- register_platform_power_off(dns323c_power_off);
-
- /* Now, -this- should theoretically be done by the sata_mv driver
- * once I figure out what's going on there. Maybe the behaviour
- * of the LEDs should be somewhat passed via the platform_data.
- * for now, just whack the register and make the LEDs happy
- *
- * Note: AFAIK, rev B1 needs the same treatment but I'll let
- * somebody else test it.
- */
- writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c);
- break;
- }
-}
-
-/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
-MACHINE_START(DNS323, "D-Link DNS-323")
- /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
- .atag_offset = 0x100,
- .nr_irqs = ORION5X_NR_IRQS,
- .init_machine = dns323_init,
- .map_io = orion5x_map_io,
- .init_early = orion5x_init_early,
- .init_irq = orion5x_init_irq,
- .init_time = orion5x_timer_init,
- .fixup = tag_fixup_mem32,
- .restart = orion5x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
deleted file mode 100644
index e61b9ab06943..000000000000
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ /dev/null
@@ -1,407 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-orion5x/kurobox_pro-setup.c
- *
- * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
- */
-#include <linux/gpio/consumer.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/i2c.h>
-#include <linux/serial_reg.h>
-#include <linux/ata_platform.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include <linux/platform_data/mtd-orion_nand.h>
-#include "common.h"
-#include "mpp.h"
-#include "orion5x.h"
-
-/*****************************************************************************
- * KUROBOX-PRO Info
- ****************************************************************************/
-
-/*
- * 256K NOR flash Device bus boot chip select
- */
-
-#define KUROBOX_PRO_NOR_BOOT_BASE 0xf4000000
-#define KUROBOX_PRO_NOR_BOOT_SIZE SZ_256K
-
-/*
- * 256M NAND flash on Device bus chip select 1
- */
-
-#define KUROBOX_PRO_NAND_BASE 0xfc000000
-#define KUROBOX_PRO_NAND_SIZE SZ_2M
-
-/*****************************************************************************
- * 256MB NAND Flash on Device bus CS0
- ****************************************************************************/
-
-static struct mtd_partition kurobox_pro_nand_parts[] = {
- {
- .name = "uImage",
- .offset = 0,
- .size = SZ_4M,
- }, {
- .name = "rootfs",
- .offset = SZ_4M,
- .size = SZ_64M,
- }, {
- .name = "extra",
- .offset = SZ_4M + SZ_64M,
- .size = SZ_256M - (SZ_4M + SZ_64M),
- },
-};
-
-static struct resource kurobox_pro_nand_resource = {
- .flags = IORESOURCE_MEM,
- .start = KUROBOX_PRO_NAND_BASE,
- .end = KUROBOX_PRO_NAND_BASE + KUROBOX_PRO_NAND_SIZE - 1,
-};
-
-static struct orion_nand_data kurobox_pro_nand_data = {
- .parts = kurobox_pro_nand_parts,
- .nr_parts = ARRAY_SIZE(kurobox_pro_nand_parts),
- .cle = 0,
- .ale = 1,
- .width = 8,
-};
-
-static struct platform_device kurobox_pro_nand_flash = {
- .name = "orion_nand",
- .id = -1,
- .dev = {
- .platform_data = &kurobox_pro_nand_data,
- },
- .resource = &kurobox_pro_nand_resource,
- .num_resources = 1,
-};
-
-/*****************************************************************************
- * 256KB NOR Flash on BOOT Device
- ****************************************************************************/
-
-static struct physmap_flash_data kurobox_pro_nor_flash_data = {
- .width = 1,
-};
-
-static struct resource kurobox_pro_nor_flash_resource = {
- .flags = IORESOURCE_MEM,
- .start = KUROBOX_PRO_NOR_BOOT_BASE,
- .end = KUROBOX_PRO_NOR_BOOT_BASE + KUROBOX_PRO_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device kurobox_pro_nor_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &kurobox_pro_nor_flash_data,
- },
- .num_resources = 1,
- .resource = &kurobox_pro_nor_flash_resource,
-};
-
-/*****************************************************************************
- * PCI
- ****************************************************************************/
-
-static int __init kurobox_pro_pci_map_irq(const struct pci_dev *dev, u8 slot,
- u8 pin)
-{
- int irq;
-
- /*
- * Check for devices with hard-wired IRQs.
- */
- irq = orion5x_pci_map_irq(dev, slot, pin);
- if (irq != -1)
- return irq;
-
- /*
- * PCI isn't used on the Kuro
- */
- return -1;
-}
-
-static struct hw_pci kurobox_pro_pci __initdata = {
- .nr_controllers = 2,
- .setup = orion5x_pci_sys_setup,
- .scan = orion5x_pci_sys_scan_bus,
- .map_irq = kurobox_pro_pci_map_irq,
-};
-
-static int __init kurobox_pro_pci_init(void)
-{
- if (machine_is_kurobox_pro()) {
- orion5x_pci_disable();
- pci_common_init(&kurobox_pro_pci);
- }
-
- return 0;
-}
-
-subsys_initcall(kurobox_pro_pci_init);
-
-/*****************************************************************************
- * Ethernet
- ****************************************************************************/
-
-static struct mv643xx_eth_platform_data kurobox_pro_eth_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
-};
-
-/*****************************************************************************
- * RTC 5C372a on I2C bus
- ****************************************************************************/
-static struct i2c_board_info __initdata kurobox_pro_i2c_rtc = {
- I2C_BOARD_INFO("rs5c372a", 0x32),
-};
-
-/*****************************************************************************
- * SATA
- ****************************************************************************/
-static struct mv_sata_platform_data kurobox_pro_sata_data = {
- .n_ports = 2,
-};
-
-/*****************************************************************************
- * Kurobox Pro specific power off method via UART1-attached microcontroller
- ****************************************************************************/
-
-#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
-
-static int kurobox_pro_miconread(unsigned char *buf, int count)
-{
- int i;
- int timeout;
-
- for (i = 0; i < count; i++) {
- timeout = 10;
-
- while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) {
- if (--timeout == 0)
- break;
- udelay(1000);
- }
-
- if (timeout == 0)
- break;
- buf[i] = readl(UART1_REG(RX));
- }
-
- /* return read bytes */
- return i;
-}
-
-static int kurobox_pro_miconwrite(const unsigned char *buf, int count)
-{
- int i = 0;
-
- while (count--) {
- while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE))
- barrier();
- writel(buf[i++], UART1_REG(TX));
- }
-
- return 0;
-}
-
-static int kurobox_pro_miconsend(const unsigned char *data, int count)
-{
- int i;
- unsigned char checksum = 0;
- unsigned char recv_buf[40];
- unsigned char send_buf[40];
- unsigned char correct_ack[3];
- int retry = 2;
-
- /* Generate checksum */
- for (i = 0; i < count; i++)
- checksum -= data[i];
-
- do {
- /* Send data */
- kurobox_pro_miconwrite(data, count);
-
- /* send checksum */
- kurobox_pro_miconwrite(&checksum, 1);
-
- if (kurobox_pro_miconread(recv_buf, sizeof(recv_buf)) <= 3) {
- printk(KERN_ERR ">%s: receive failed.\n", __func__);
-
- /* send preamble to clear the receive buffer */
- memset(&send_buf, 0xff, sizeof(send_buf));
- kurobox_pro_miconwrite(send_buf, sizeof(send_buf));
-
- /* make dummy reads */
- mdelay(100);
- kurobox_pro_miconread(recv_buf, sizeof(recv_buf));
- } else {
- /* Generate expected ack */
- correct_ack[0] = 0x01;
- correct_ack[1] = data[1];
- correct_ack[2] = 0x00;
-
- /* checksum Check */
- if ((recv_buf[0] + recv_buf[1] + recv_buf[2] +
- recv_buf[3]) & 0xFF) {
- printk(KERN_ERR ">%s: Checksum Error : "
- "Received data[%02x, %02x, %02x, %02x]"
- "\n", __func__, recv_buf[0],
- recv_buf[1], recv_buf[2], recv_buf[3]);
- } else {
- /* Check Received Data */
- if (correct_ack[0] == recv_buf[0] &&
- correct_ack[1] == recv_buf[1] &&
- correct_ack[2] == recv_buf[2]) {
- /* Interval for next command */
- mdelay(10);
-
- /* Receive ACK */
- return 0;
- }
- }
- /* Received NAK or illegal Data */
- printk(KERN_ERR ">%s: Error : NAK or Illegal Data "
- "Received\n", __func__);
- }
- } while (retry--);
-
- /* Interval for next command */
- mdelay(10);
-
- return -1;
-}
-
-static void kurobox_pro_power_off(void)
-{
- const unsigned char watchdogkill[] = {0x01, 0x35, 0x00};
- const unsigned char shutdownwait[] = {0x00, 0x0c};
- const unsigned char poweroff[] = {0x00, 0x06};
- /* 38400 baud divisor */
- const unsigned divisor = ((orion5x_tclk + (8 * 38400)) / (16 * 38400));
-
- pr_info("%s: triggering power-off...\n", __func__);
-
- /* hijack uart1 and reset into sane state (38400,8n1,even parity) */
- writel(0x83, UART1_REG(LCR));
- writel(divisor & 0xff, UART1_REG(DLL));
- writel((divisor >> 8) & 0xff, UART1_REG(DLM));
- writel(0x1b, UART1_REG(LCR));
- writel(0x00, UART1_REG(IER));
- writel(0x07, UART1_REG(FCR));
- writel(0x00, UART1_REG(MCR));
-
- /* Send the commands to shutdown the Kurobox Pro */
- kurobox_pro_miconsend(watchdogkill, sizeof(watchdogkill)) ;
- kurobox_pro_miconsend(shutdownwait, sizeof(shutdownwait)) ;
- kurobox_pro_miconsend(poweroff, sizeof(poweroff));
-}
-
-/*****************************************************************************
- * General Setup
- ****************************************************************************/
-static unsigned int kurobox_pro_mpp_modes[] __initdata = {
- MPP0_UNUSED,
- MPP1_UNUSED,
- MPP2_GPIO, /* GPIO Micon */
- MPP3_GPIO, /* GPIO Rtc */
- MPP4_UNUSED,
- MPP5_UNUSED,
- MPP6_NAND, /* NAND Flash REn */
- MPP7_NAND, /* NAND Flash WEn */
- MPP8_UNUSED,
- MPP9_UNUSED,
- MPP10_UNUSED,
- MPP11_UNUSED,
- MPP12_SATA_LED, /* SATA 0 presence */
- MPP13_SATA_LED, /* SATA 1 presence */
- MPP14_SATA_LED, /* SATA 0 active */
- MPP15_SATA_LED, /* SATA 1 active */
- MPP16_UART, /* UART1 RXD */
- MPP17_UART, /* UART1 TXD */
- MPP18_UART, /* UART1 CTSn */
- MPP19_UART, /* UART1 RTSn */
- 0,
-};
-
-static void __init kurobox_pro_init(void)
-{
- /*
- * Setup basic Orion functions. Need to be called early.
- */
- orion5x_init();
-
- orion5x_mpp_conf(kurobox_pro_mpp_modes);
-
- /*
- * Configure peripherals.
- */
- orion5x_ehci0_init();
- orion5x_ehci1_init();
- orion5x_eth_init(&kurobox_pro_eth_data);
- orion5x_i2c_init();
- orion5x_sata_init(&kurobox_pro_sata_data);
- orion5x_uart0_init();
- orion5x_uart1_init();
- orion5x_xor_init();
-
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
- ORION_MBUS_DEVBUS_BOOT_ATTR,
- KUROBOX_PRO_NOR_BOOT_BASE,
- KUROBOX_PRO_NOR_BOOT_SIZE);
- platform_device_register(&kurobox_pro_nor_flash);
-
- if (machine_is_kurobox_pro()) {
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
- ORION_MBUS_DEVBUS_ATTR(0),
- KUROBOX_PRO_NAND_BASE,
- KUROBOX_PRO_NAND_SIZE);
- platform_device_register(&kurobox_pro_nand_flash);
- }
-
- i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1);
-
- /* register Kurobox Pro specific power-off method */
- register_platform_power_off(kurobox_pro_power_off);
-}
-
-#ifdef CONFIG_MACH_KUROBOX_PRO
-MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
- /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
- .atag_offset = 0x100,
- .nr_irqs = ORION5X_NR_IRQS,
- .init_machine = kurobox_pro_init,
- .map_io = orion5x_map_io,
- .init_early = orion5x_init_early,
- .init_irq = orion5x_init_irq,
- .init_time = orion5x_timer_init,
- .fixup = tag_fixup_mem32,
- .restart = orion5x_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_LINKSTATION_PRO
-MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
- /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
- .atag_offset = 0x100,
- .nr_irqs = ORION5X_NR_IRQS,
- .init_machine = kurobox_pro_init,
- .map_io = orion5x_map_io,
- .init_early = orion5x_init_early,
- .init_irq = orion5x_init_irq,
- .init_time = orion5x_timer_init,
- .fixup = tag_fixup_mem32,
- .restart = orion5x_restart,
-MACHINE_END
-#endif
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
deleted file mode 100644
index b15fe5b7a0f9..000000000000
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
- * Copyright (C) 2008 Martin Michlmayr <tbm@cyrius.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- */
-#include <linux/gpio/legacy.h>
-#include <linux/gpio/machine.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/leds.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/ata_platform.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "common.h"
-#include "mpp.h"
-#include "orion5x.h"
-
-#define MV2120_NOR_BOOT_BASE 0xf4000000
-#define MV2120_NOR_BOOT_SIZE SZ_512K
-
-#define MV2120_GPIO_RTC_IRQ 3
-#define MV2120_GPIO_KEY_RESET 17
-#define MV2120_GPIO_KEY_POWER 18
-#define MV2120_GPIO_POWER_OFF 19
-
-
-/*****************************************************************************
- * Ethernet
- ****************************************************************************/
-static struct mv643xx_eth_platform_data mv2120_eth_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
-};
-
-static struct mv_sata_platform_data mv2120_sata_data = {
- .n_ports = 2,
-};
-
-static struct mtd_partition mv2120_partitions[] = {
- {
- .name = "firmware",
- .size = 0x00080000,
- .offset = 0,
- },
-};
-
-static struct physmap_flash_data mv2120_nor_flash_data = {
- .width = 1,
- .parts = mv2120_partitions,
- .nr_parts = ARRAY_SIZE(mv2120_partitions)
-};
-
-static struct resource mv2120_nor_flash_resource = {
- .flags = IORESOURCE_MEM,
- .start = MV2120_NOR_BOOT_BASE,
- .end = MV2120_NOR_BOOT_BASE + MV2120_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device mv2120_nor_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &mv2120_nor_flash_data,
- },
- .resource = &mv2120_nor_flash_resource,
- .num_resources = 1,
-};
-
-static struct gpio_keys_button mv2120_buttons[] = {
- {
- .code = KEY_RESTART,
- .gpio = MV2120_GPIO_KEY_RESET,
- .desc = "reset",
- .active_low = 1,
- }, {
- .code = KEY_POWER,
- .gpio = MV2120_GPIO_KEY_POWER,
- .desc = "power",
- .active_low = 1,
- },
-};
-
-static struct gpio_keys_platform_data mv2120_button_data = {
- .buttons = mv2120_buttons,
- .nbuttons = ARRAY_SIZE(mv2120_buttons),
-};
-
-static struct platform_device mv2120_button_device = {
- .name = "gpio-keys",
- .id = -1,
- .num_resources = 0,
- .dev = {
- .platform_data = &mv2120_button_data,
- },
-};
-
-
-/****************************************************************************
- * General Setup
- ****************************************************************************/
-static unsigned int mv2120_mpp_modes[] __initdata = {
- MPP0_GPIO, /* Sys status LED */
- MPP1_GPIO, /* Sys error LED */
- MPP2_GPIO, /* OverTemp interrupt */
- MPP3_GPIO, /* RTC interrupt */
- MPP4_GPIO, /* V_LED 5V */
- MPP5_GPIO, /* V_LED 3.3V */
- MPP6_UNUSED,
- MPP7_UNUSED,
- MPP8_GPIO, /* SATA 0 fail LED */
- MPP9_GPIO, /* SATA 1 fail LED */
- MPP10_UNUSED,
- MPP11_UNUSED,
- MPP12_SATA_LED, /* SATA 0 presence */
- MPP13_SATA_LED, /* SATA 1 presence */
- MPP14_SATA_LED, /* SATA 0 active */
- MPP15_SATA_LED, /* SATA 1 active */
- MPP16_UNUSED,
- MPP17_GPIO, /* Reset button */
- MPP18_GPIO, /* Power button */
- MPP19_GPIO, /* Power off */
- 0,
-};
-
-static struct i2c_board_info __initdata mv2120_i2c_rtc = {
- I2C_BOARD_INFO("pcf8563", 0x51),
- .irq = 0,
-};
-
-static struct gpio_led mv2120_led_pins[] = {
- {
- .name = "mv2120:blue:health",
- },
- {
- .name = "mv2120:red:health",
- },
- {
- .name = "mv2120:led:bright",
- .default_trigger = "default-on",
- },
- {
- .name = "mv2120:led:dimmed",
- },
- {
- .name = "mv2120:red:sata0",
- },
- {
- .name = "mv2120:red:sata1",
- },
-
-};
-
-static struct gpiod_lookup_table mv2120_leds_gpio_table = {
- .dev_id = "leds-gpio",
- .table = {
- GPIO_LOOKUP_IDX("orion_gpio0", 0, NULL,
- 0, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("orion_gpio0", 1, NULL,
- 1, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("orion_gpio0", 4, NULL,
- 2, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("orion_gpio0", 5, NULL,
- 3, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("orion_gpio0", 8, NULL,
- 4, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("orion_gpio0", 9, NULL,
- 5, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct gpio_led_platform_data mv2120_led_data = {
- .leds = mv2120_led_pins,
- .num_leds = ARRAY_SIZE(mv2120_led_pins),
-};
-
-static struct platform_device mv2120_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &mv2120_led_data,
- }
-};
-
-static void mv2120_power_off(void)
-{
- pr_info("%s: triggering power-off...\n", __func__);
- gpio_set_value(MV2120_GPIO_POWER_OFF, 0);
-}
-
-static void __init mv2120_init(void)
-{
- /* Setup basic Orion functions. Need to be called early. */
- orion5x_init();
-
- orion5x_mpp_conf(mv2120_mpp_modes);
-
- /*
- * Configure peripherals.
- */
- orion5x_ehci0_init();
- orion5x_ehci1_init();
- orion5x_eth_init(&mv2120_eth_data);
- orion5x_i2c_init();
- orion5x_sata_init(&mv2120_sata_data);
- orion5x_uart0_init();
- orion5x_xor_init();
-
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
- ORION_MBUS_DEVBUS_BOOT_ATTR,
- MV2120_NOR_BOOT_BASE,
- MV2120_NOR_BOOT_SIZE);
- platform_device_register(&mv2120_nor_flash);
-
- platform_device_register(&mv2120_button_device);
-
- if (gpio_request(MV2120_GPIO_RTC_IRQ, "rtc") == 0) {
- if (gpio_direction_input(MV2120_GPIO_RTC_IRQ) == 0)
- mv2120_i2c_rtc.irq = gpio_to_irq(MV2120_GPIO_RTC_IRQ);
- else
- gpio_free(MV2120_GPIO_RTC_IRQ);
- }
- i2c_register_board_info(0, &mv2120_i2c_rtc, 1);
- gpiod_add_lookup_table(&mv2120_leds_gpio_table);
- platform_device_register(&mv2120_leds);
-
- /* register mv2120 specific power-off method */
- if (gpio_request(MV2120_GPIO_POWER_OFF, "POWEROFF") != 0 ||
- gpio_direction_output(MV2120_GPIO_POWER_OFF, 1) != 0)
- pr_err("mv2120: failed to setup power-off GPIO\n");
- register_platform_power_off(mv2120_power_off);
-}
-
-/* Warning: HP uses a wrong mach-type (=526) in their bootloader */
-MACHINE_START(MV2120, "HP Media Vault mv2120")
- /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
- .atag_offset = 0x100,
- .nr_irqs = ORION5X_NR_IRQS,
- .init_machine = mv2120_init,
- .map_io = orion5x_map_io,
- .init_early = orion5x_init_early,
- .init_irq = orion5x_init_irq,
- .init_time = orion5x_timer_init,
- .fixup = tag_fixup_mem32,
- .restart = orion5x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
deleted file mode 100644
index f04571e79805..000000000000
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ /dev/null
@@ -1,444 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-orion5x/net2big-setup.c
- *
- * LaCie 2Big Network NAS setup
- *
- * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/leds.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/ata_platform.h>
-#include <linux/gpio/legacy.h>
-#include <linux/gpio/machine.h>
-#include <linux/delay.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <plat/orion-gpio.h>
-#include "common.h"
-#include "mpp.h"
-#include "orion5x.h"
-
-/*****************************************************************************
- * LaCie 2Big Network Info
- ****************************************************************************/
-
-/*
- * 512KB NOR flash Device bus boot chip select
- */
-
-#define NET2BIG_NOR_BOOT_BASE 0xfff80000
-#define NET2BIG_NOR_BOOT_SIZE SZ_512K
-
-/*****************************************************************************
- * 512KB NOR Flash on Boot Device
- ****************************************************************************/
-
-/*
- * TODO: Check write support on flash MX29LV400CBTC-70G
- */
-
-static struct mtd_partition net2big_partitions[] = {
- {
- .name = "Full512kb",
- .size = MTDPART_SIZ_FULL,
- .offset = 0x00000000,
- .mask_flags = MTD_WRITEABLE,
- },
-};
-
-static struct physmap_flash_data net2big_nor_flash_data = {
- .width = 1,
- .parts = net2big_partitions,
- .nr_parts = ARRAY_SIZE(net2big_partitions),
-};
-
-static struct resource net2big_nor_flash_resource = {
- .flags = IORESOURCE_MEM,
- .start = NET2BIG_NOR_BOOT_BASE,
- .end = NET2BIG_NOR_BOOT_BASE
- + NET2BIG_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device net2big_nor_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &net2big_nor_flash_data,
- },
- .num_resources = 1,
- .resource = &net2big_nor_flash_resource,
-};
-
-/*****************************************************************************
- * Ethernet
- ****************************************************************************/
-
-static struct mv643xx_eth_platform_data net2big_eth_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
-};
-
-/*****************************************************************************
- * I2C devices
- ****************************************************************************/
-
-/*
- * i2c addr | chip | description
- * 0x32 | Ricoh 5C372b | RTC
- * 0x50 | HT24LC08 | eeprom (1kB)
- */
-static struct i2c_board_info __initdata net2big_i2c_devices[] = {
- {
- I2C_BOARD_INFO("rs5c372b", 0x32),
- }, {
- I2C_BOARD_INFO("24c08", 0x50),
- },
-};
-
-/*****************************************************************************
- * SATA
- ****************************************************************************/
-
-static struct mv_sata_platform_data net2big_sata_data = {
- .n_ports = 2,
-};
-
-#define NET2BIG_GPIO_SATA_POWER_REQ 19
-#define NET2BIG_GPIO_SATA0_POWER 23
-#define NET2BIG_GPIO_SATA1_POWER 25
-
-static void __init net2big_sata_power_init(void)
-{
- int err;
-
- /* Configure GPIOs over MPP max number. */
- orion_gpio_set_valid(NET2BIG_GPIO_SATA0_POWER, 1);
- orion_gpio_set_valid(NET2BIG_GPIO_SATA1_POWER, 1);
-
- err = gpio_request(NET2BIG_GPIO_SATA0_POWER, "SATA0 power status");
- if (err == 0) {
- err = gpio_direction_input(NET2BIG_GPIO_SATA0_POWER);
- if (err)
- gpio_free(NET2BIG_GPIO_SATA0_POWER);
- }
- if (err) {
- pr_err("net2big: failed to setup SATA0 power GPIO\n");
- return;
- }
-
- err = gpio_request(NET2BIG_GPIO_SATA1_POWER, "SATA1 power status");
- if (err == 0) {
- err = gpio_direction_input(NET2BIG_GPIO_SATA1_POWER);
- if (err)
- gpio_free(NET2BIG_GPIO_SATA1_POWER);
- }
- if (err) {
- pr_err("net2big: failed to setup SATA1 power GPIO\n");
- goto err_free_1;
- }
-
- err = gpio_request(NET2BIG_GPIO_SATA_POWER_REQ, "SATA power request");
- if (err == 0) {
- err = gpio_direction_output(NET2BIG_GPIO_SATA_POWER_REQ, 0);
- if (err)
- gpio_free(NET2BIG_GPIO_SATA_POWER_REQ);
- }
- if (err) {
- pr_err("net2big: failed to setup SATA power request GPIO\n");
- goto err_free_2;
- }
-
- if (gpio_get_value(NET2BIG_GPIO_SATA0_POWER) &&
- gpio_get_value(NET2BIG_GPIO_SATA1_POWER)) {
- return;
- }
-
- /*
- * SATA power up on both disk is done by pulling high the CPLD power
- * request line. The 300ms delay is related to the CPLD clock and is
- * needed to be sure that the CPLD has take into account the low line
- * status.
- */
- msleep(300);
- gpio_set_value(NET2BIG_GPIO_SATA_POWER_REQ, 1);
- pr_info("net2big: power up SATA hard disks\n");
-
- return;
-
-err_free_2:
- gpio_free(NET2BIG_GPIO_SATA1_POWER);
-err_free_1:
- gpio_free(NET2BIG_GPIO_SATA0_POWER);
-
- return;
-}
-
-/*****************************************************************************
- * GPIO LEDs
- ****************************************************************************/
-
-/*
- * The power front LEDs (blue and red) and SATA red LEDs are controlled via a
- * single GPIO line and are compatible with the leds-gpio driver.
- *
- * The SATA blue LEDs have some hardware blink capabilities which are detailed
- * in the following array:
- *
- * SATAx blue LED | SATAx activity | LED state
- * | |
- * 0 | 0 | blink (rate 300ms)
- * 1 | 0 | off
- * ? | 1 | on
- *
- * Notes: The blue and the red front LED's can't be on at the same time.
- * Blue LED have priority.
- */
-
-#define NET2BIG_GPIO_PWR_RED_LED 6
-#define NET2BIG_GPIO_PWR_BLUE_LED 16
-#define NET2BIG_GPIO_PWR_LED_BLINK_STOP 7
-
-#define NET2BIG_GPIO_SATA0_RED_LED 11
-#define NET2BIG_GPIO_SATA1_RED_LED 10
-
-#define NET2BIG_GPIO_SATA0_BLUE_LED 17
-#define NET2BIG_GPIO_SATA1_BLUE_LED 13
-
-static struct gpio_led net2big_leds[] = {
- {
- .name = "net2big:red:power",
- },
- {
- .name = "net2big:blue:power",
- },
- {
- .name = "net2big:red:sata0",
- },
- {
- .name = "net2big:red:sata1",
- },
-};
-
-static struct gpiod_lookup_table net2big_leds_gpio_table = {
- .dev_id = "leds-gpio",
- .table = {
- GPIO_LOOKUP_IDX("orion_gpio0", NET2BIG_GPIO_PWR_RED_LED, NULL,
- 0, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("orion_gpio0", NET2BIG_GPIO_PWR_BLUE_LED, NULL,
- 1, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("orion_gpio0", NET2BIG_GPIO_SATA0_RED_LED, NULL,
- 2, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("orion_gpio0", NET2BIG_GPIO_SATA1_RED_LED, NULL,
- 3, GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct gpio_led_platform_data net2big_led_data = {
- .num_leds = ARRAY_SIZE(net2big_leds),
- .leds = net2big_leds,
-};
-
-static struct platform_device net2big_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &net2big_led_data,
- },
-};
-
-static void __init net2big_gpio_leds_init(void)
-{
- int err;
-
- /* Stop initial CPLD slow red/blue blinking on power LED. */
- err = gpio_request(NET2BIG_GPIO_PWR_LED_BLINK_STOP,
- "Power LED blink stop");
- if (err == 0) {
- err = gpio_direction_output(NET2BIG_GPIO_PWR_LED_BLINK_STOP, 1);
- if (err)
- gpio_free(NET2BIG_GPIO_PWR_LED_BLINK_STOP);
- }
- if (err)
- pr_err("net2big: failed to setup power LED blink GPIO\n");
-
- /*
- * Configure SATA0 and SATA1 blue LEDs to blink in relation with the
- * hard disk activity.
- */
- err = gpio_request(NET2BIG_GPIO_SATA0_BLUE_LED,
- "SATA0 blue LED control");
- if (err == 0) {
- err = gpio_direction_output(NET2BIG_GPIO_SATA0_BLUE_LED, 1);
- if (err)
- gpio_free(NET2BIG_GPIO_SATA0_BLUE_LED);
- }
- if (err)
- pr_err("net2big: failed to setup SATA0 blue LED GPIO\n");
-
- err = gpio_request(NET2BIG_GPIO_SATA1_BLUE_LED,
- "SATA1 blue LED control");
- if (err == 0) {
- err = gpio_direction_output(NET2BIG_GPIO_SATA1_BLUE_LED, 1);
- if (err)
- gpio_free(NET2BIG_GPIO_SATA1_BLUE_LED);
- }
- if (err)
- pr_err("net2big: failed to setup SATA1 blue LED GPIO\n");
-
- gpiod_add_lookup_table(&net2big_leds_gpio_table);
- platform_device_register(&net2big_gpio_leds);
-}
-
-/****************************************************************************
- * GPIO keys
- ****************************************************************************/
-
-#define NET2BIG_GPIO_PUSH_BUTTON 18
-#define NET2BIG_GPIO_POWER_SWITCH_ON 8
-#define NET2BIG_GPIO_POWER_SWITCH_OFF 9
-
-#define NET2BIG_SWITCH_POWER_ON 0x1
-#define NET2BIG_SWITCH_POWER_OFF 0x2
-
-static struct gpio_keys_button net2big_buttons[] = {
- {
- .type = EV_SW,
- .code = NET2BIG_SWITCH_POWER_OFF,
- .gpio = NET2BIG_GPIO_POWER_SWITCH_OFF,
- .desc = "Power rocker switch (auto|off)",
- .active_low = 0,
- },
- {
- .type = EV_SW,
- .code = NET2BIG_SWITCH_POWER_ON,
- .gpio = NET2BIG_GPIO_POWER_SWITCH_ON,
- .desc = "Power rocker switch (on|auto)",
- .active_low = 0,
- },
- {
- .type = EV_KEY,
- .code = KEY_POWER,
- .gpio = NET2BIG_GPIO_PUSH_BUTTON,
- .desc = "Front Push Button",
- .active_low = 0,
- },
-};
-
-static struct gpio_keys_platform_data net2big_button_data = {
- .buttons = net2big_buttons,
- .nbuttons = ARRAY_SIZE(net2big_buttons),
-};
-
-static struct platform_device net2big_gpio_buttons = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &net2big_button_data,
- },
-};
-
-/*****************************************************************************
- * General Setup
- ****************************************************************************/
-
-static unsigned int net2big_mpp_modes[] __initdata = {
- MPP0_GPIO, /* Raid mode (bit 0) */
- MPP1_GPIO, /* USB port 2 fuse (0 = Fail, 1 = Ok) */
- MPP2_GPIO, /* Raid mode (bit 1) */
- MPP3_GPIO, /* Board ID (bit 0) */
- MPP4_GPIO, /* Fan activity (0 = Off, 1 = On) */
- MPP5_GPIO, /* Fan fail detection */
- MPP6_GPIO, /* Red front LED (0 = Off, 1 = On) */
- MPP7_GPIO, /* Disable initial blinking on front LED */
- MPP8_GPIO, /* Rear power switch (on|auto) */
- MPP9_GPIO, /* Rear power switch (auto|off) */
- MPP10_GPIO, /* SATA 1 red LED (0 = Off, 1 = On) */
- MPP11_GPIO, /* SATA 0 red LED (0 = Off, 1 = On) */
- MPP12_GPIO, /* Board ID (bit 1) */
- MPP13_GPIO, /* SATA 1 blue LED blink control */
- MPP14_SATA_LED,
- MPP15_SATA_LED,
- MPP16_GPIO, /* Blue front LED control */
- MPP17_GPIO, /* SATA 0 blue LED blink control */
- MPP18_GPIO, /* Front button (0 = Released, 1 = Pushed ) */
- MPP19_GPIO, /* SATA{0,1} power On/Off request */
- 0,
- /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
- /* 23: SATA 0 power status */
- /* 24: Board power off */
- /* 25: SATA 1 power status */
-};
-
-#define NET2BIG_GPIO_POWER_OFF 24
-
-static void net2big_power_off(void)
-{
- gpio_set_value(NET2BIG_GPIO_POWER_OFF, 1);
-}
-
-static void __init net2big_init(void)
-{
- /*
- * Setup basic Orion functions. Need to be called early.
- */
- orion5x_init();
-
- orion5x_mpp_conf(net2big_mpp_modes);
-
- /*
- * Configure peripherals.
- */
- orion5x_ehci0_init();
- orion5x_ehci1_init();
- orion5x_eth_init(&net2big_eth_data);
- orion5x_i2c_init();
- orion5x_uart0_init();
- orion5x_xor_init();
-
- net2big_sata_power_init();
- orion5x_sata_init(&net2big_sata_data);
-
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
- ORION_MBUS_DEVBUS_BOOT_ATTR,
- NET2BIG_NOR_BOOT_BASE,
- NET2BIG_NOR_BOOT_SIZE);
- platform_device_register(&net2big_nor_flash);
-
- platform_device_register(&net2big_gpio_buttons);
- net2big_gpio_leds_init();
-
- i2c_register_board_info(0, net2big_i2c_devices,
- ARRAY_SIZE(net2big_i2c_devices));
-
- orion_gpio_set_valid(NET2BIG_GPIO_POWER_OFF, 1);
-
- if (gpio_request(NET2BIG_GPIO_POWER_OFF, "power-off") == 0 &&
- gpio_direction_output(NET2BIG_GPIO_POWER_OFF, 0) == 0)
- register_platform_power_off(net2big_power_off);
- else
- pr_err("net2big: failed to configure power-off GPIO\n");
-
- pr_notice("net2big: Flash writing is not yet supported.\n");
-}
-
-/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
-MACHINE_START(NET2BIG, "LaCie 2Big Network")
- .atag_offset = 0x100,
- .nr_irqs = ORION5X_NR_IRQS,
- .init_machine = net2big_init,
- .map_io = orion5x_map_io,
- .init_early = orion5x_init_early,
- .init_irq = orion5x_init_irq,
- .init_time = orion5x_timer_init,
- .fixup = tag_fixup_mem32,
- .restart = orion5x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 06f5320036b1..3d1e6ad0e14b 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -15,7 +15,6 @@
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
-#include <plat/addr-map.h>
#include "common.h"
#include "orion5x.h"
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
deleted file mode 100644
index c3db3376950a..000000000000
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ /dev/null
@@ -1,366 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Buffalo Terastation Pro II/Live Board Setup
- *
- * Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com>
- */
-#include <linux/gpio/legacy.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/i2c.h>
-#include <linux/serial_reg.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include "common.h"
-#include "mpp.h"
-#include "orion5x.h"
-
-/*****************************************************************************
- * Terastation Pro 2/Live Info
- ****************************************************************************/
-
-/*
- * Terastation Pro 2 hardware :
- * - Marvell 88F5281-D0
- * - Marvell 88SX6042 SATA controller (PCI)
- * - Marvell 88E1118 Gigabit Ethernet PHY
- * - 256KB NOR flash
- * - 128MB of DDR RAM
- * - PCIe port (not equipped)
- */
-
-/*
- * 256K NOR flash Device bus boot chip select
- */
-
-#define TSP2_NOR_BOOT_BASE 0xf4000000
-#define TSP2_NOR_BOOT_SIZE SZ_256K
-
-/*****************************************************************************
- * 256KB NOR Flash on BOOT Device
- ****************************************************************************/
-
-static struct physmap_flash_data tsp2_nor_flash_data = {
- .width = 1,
-};
-
-static struct resource tsp2_nor_flash_resource = {
- .flags = IORESOURCE_MEM,
- .start = TSP2_NOR_BOOT_BASE,
- .end = TSP2_NOR_BOOT_BASE + TSP2_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device tsp2_nor_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &tsp2_nor_flash_data,
- },
- .num_resources = 1,
- .resource = &tsp2_nor_flash_resource,
-};
-
-/*****************************************************************************
- * PCI
- ****************************************************************************/
-#define TSP2_PCI_SLOT0_OFFS 7
-#define TSP2_PCI_SLOT0_IRQ_PIN 11
-
-static void __init tsp2_pci_preinit(void)
-{
- int pin;
-
- /*
- * Configure PCI GPIO IRQ pins
- */
- pin = TSP2_PCI_SLOT0_IRQ_PIN;
- if (gpio_request(pin, "PCI Int1") == 0) {
- if (gpio_direction_input(pin) == 0) {
- irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
- } else {
- printk(KERN_ERR "tsp2_pci_preinit failed "
- "to set_irq_type pin %d\n", pin);
- gpio_free(pin);
- }
- } else {
- printk(KERN_ERR "tsp2_pci_preinit failed to "
- "gpio_request %d\n", pin);
- }
-}
-
-static int __init tsp2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq;
-
- /*
- * Check for devices with hard-wired IRQs.
- */
- irq = orion5x_pci_map_irq(dev, slot, pin);
- if (irq != -1)
- return irq;
-
- /*
- * PCI IRQs are connected via GPIOs.
- */
- if (slot == TSP2_PCI_SLOT0_OFFS)
- return gpio_to_irq(TSP2_PCI_SLOT0_IRQ_PIN);
-
- return -1;
-}
-
-static struct hw_pci tsp2_pci __initdata = {
- .nr_controllers = 2,
- .preinit = tsp2_pci_preinit,
- .setup = orion5x_pci_sys_setup,
- .scan = orion5x_pci_sys_scan_bus,
- .map_irq = tsp2_pci_map_irq,
-};
-
-static int __init tsp2_pci_init(void)
-{
- if (machine_is_terastation_pro2())
- pci_common_init(&tsp2_pci);
-
- return 0;
-}
-
-subsys_initcall(tsp2_pci_init);
-
-/*****************************************************************************
- * Ethernet
- ****************************************************************************/
-
-static struct mv643xx_eth_platform_data tsp2_eth_data = {
- .phy_addr = 0,
-};
-
-/*****************************************************************************
- * RTC 5C372a on I2C bus
- ****************************************************************************/
-
-#define TSP2_RTC_GPIO 9
-
-static struct i2c_board_info __initdata tsp2_i2c_rtc = {
- I2C_BOARD_INFO("rs5c372a", 0x32),
-};
-
-/*****************************************************************************
- * Terastation Pro II specific power off method via UART1-attached
- * microcontroller
- ****************************************************************************/
-
-#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
-
-static int tsp2_miconread(unsigned char *buf, int count)
-{
- int i;
- int timeout;
-
- for (i = 0; i < count; i++) {
- timeout = 10;
-
- while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) {
- if (--timeout == 0)
- break;
- udelay(1000);
- }
-
- if (timeout == 0)
- break;
- buf[i] = readl(UART1_REG(RX));
- }
-
- /* return read bytes */
- return i;
-}
-
-static int tsp2_miconwrite(const unsigned char *buf, int count)
-{
- int i = 0;
-
- while (count--) {
- while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE))
- barrier();
- writel(buf[i++], UART1_REG(TX));
- }
-
- return 0;
-}
-
-static int tsp2_miconsend(const unsigned char *data, int count)
-{
- int i;
- unsigned char checksum = 0;
- unsigned char recv_buf[40];
- unsigned char send_buf[40];
- unsigned char correct_ack[3];
- int retry = 2;
-
- /* Generate checksum */
- for (i = 0; i < count; i++)
- checksum -= data[i];
-
- do {
- /* Send data */
- tsp2_miconwrite(data, count);
-
- /* send checksum */
- tsp2_miconwrite(&checksum, 1);
-
- if (tsp2_miconread(recv_buf, sizeof(recv_buf)) <= 3) {
- printk(KERN_ERR ">%s: receive failed.\n", __func__);
-
- /* send preamble to clear the receive buffer */
- memset(&send_buf, 0xff, sizeof(send_buf));
- tsp2_miconwrite(send_buf, sizeof(send_buf));
-
- /* make dummy reads */
- mdelay(100);
- tsp2_miconread(recv_buf, sizeof(recv_buf));
- } else {
- /* Generate expected ack */
- correct_ack[0] = 0x01;
- correct_ack[1] = data[1];
- correct_ack[2] = 0x00;
-
- /* checksum Check */
- if ((recv_buf[0] + recv_buf[1] + recv_buf[2] +
- recv_buf[3]) & 0xFF) {
- printk(KERN_ERR ">%s: Checksum Error : "
- "Received data[%02x, %02x, %02x, %02x]"
- "\n", __func__, recv_buf[0],
- recv_buf[1], recv_buf[2], recv_buf[3]);
- } else {
- /* Check Received Data */
- if (correct_ack[0] == recv_buf[0] &&
- correct_ack[1] == recv_buf[1] &&
- correct_ack[2] == recv_buf[2]) {
- /* Interval for next command */
- mdelay(10);
-
- /* Receive ACK */
- return 0;
- }
- }
- /* Received NAK or illegal Data */
- printk(KERN_ERR ">%s: Error : NAK or Illegal Data "
- "Received\n", __func__);
- }
- } while (retry--);
-
- /* Interval for next command */
- mdelay(10);
-
- return -1;
-}
-
-static void tsp2_power_off(void)
-{
- const unsigned char watchdogkill[] = {0x01, 0x35, 0x00};
- const unsigned char shutdownwait[] = {0x00, 0x0c};
- const unsigned char poweroff[] = {0x00, 0x06};
- /* 38400 baud divisor */
- const unsigned divisor = ((orion5x_tclk + (8 * 38400)) / (16 * 38400));
-
- pr_info("%s: triggering power-off...\n", __func__);
-
- /* hijack uart1 and reset into sane state (38400,8n1,even parity) */
- writel(0x83, UART1_REG(LCR));
- writel(divisor & 0xff, UART1_REG(DLL));
- writel((divisor >> 8) & 0xff, UART1_REG(DLM));
- writel(0x1b, UART1_REG(LCR));
- writel(0x00, UART1_REG(IER));
- writel(0x07, UART1_REG(FCR));
- writel(0x00, UART1_REG(MCR));
-
- /* Send the commands to shutdown the Terastation Pro II */
- tsp2_miconsend(watchdogkill, sizeof(watchdogkill)) ;
- tsp2_miconsend(shutdownwait, sizeof(shutdownwait)) ;
- tsp2_miconsend(poweroff, sizeof(poweroff));
-}
-
-/*****************************************************************************
- * General Setup
- ****************************************************************************/
-static unsigned int tsp2_mpp_modes[] __initdata = {
- MPP0_PCIE_RST_OUTn,
- MPP1_UNUSED,
- MPP2_UNUSED,
- MPP3_UNUSED,
- MPP4_NAND, /* BOOT NAND Flash REn */
- MPP5_NAND, /* BOOT NAND Flash WEn */
- MPP6_NAND, /* BOOT NAND Flash HREn[0] */
- MPP7_NAND, /* BOOT NAND Flash WEn[0] */
- MPP8_GPIO, /* MICON int */
- MPP9_GPIO, /* RTC int */
- MPP10_UNUSED,
- MPP11_GPIO, /* PCI Int A */
- MPP12_UNUSED,
- MPP13_GPIO, /* UPS on UART0 enable */
- MPP14_GPIO, /* UPS low battery detection */
- MPP15_UNUSED,
- MPP16_UART, /* UART1 RXD */
- MPP17_UART, /* UART1 TXD */
- MPP18_UART, /* UART1 CTSn */
- MPP19_UART, /* UART1 RTSn */
- 0,
-};
-
-static void __init tsp2_init(void)
-{
- /*
- * Setup basic Orion functions. Need to be called early.
- */
- orion5x_init();
-
- orion5x_mpp_conf(tsp2_mpp_modes);
-
- /*
- * Configure peripherals.
- */
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
- ORION_MBUS_DEVBUS_BOOT_ATTR,
- TSP2_NOR_BOOT_BASE,
- TSP2_NOR_BOOT_SIZE);
- platform_device_register(&tsp2_nor_flash);
-
- orion5x_ehci0_init();
- orion5x_eth_init(&tsp2_eth_data);
- orion5x_i2c_init();
- orion5x_uart0_init();
- orion5x_uart1_init();
-
- /* Get RTC IRQ and register the chip */
- if (gpio_request(TSP2_RTC_GPIO, "rtc") == 0) {
- if (gpio_direction_input(TSP2_RTC_GPIO) == 0)
- tsp2_i2c_rtc.irq = gpio_to_irq(TSP2_RTC_GPIO);
- else
- gpio_free(TSP2_RTC_GPIO);
- }
- if (tsp2_i2c_rtc.irq == 0)
- pr_warn("tsp2_init: failed to get RTC IRQ\n");
- i2c_register_board_info(0, &tsp2_i2c_rtc, 1);
-
- /* register Terastation Pro II specific power-off method */
- register_platform_power_off(tsp2_power_off);
-}
-
-MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live")
- /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */
- .atag_offset = 0x100,
- .nr_irqs = ORION5X_NR_IRQS,
- .init_machine = tsp2_init,
- .map_io = orion5x_map_io,
- .init_early = orion5x_init_early,
- .init_irq = orion5x_init_irq,
- .init_time = orion5x_timer_init,
- .fixup = tag_fixup_mem32,
- .restart = orion5x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
deleted file mode 100644
index 25cd50306c65..000000000000
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ /dev/null
@@ -1,331 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * QNAP TS-109/TS-209 Board Setup
- *
- * Maintainer: Byron Bradley <byron.bbradley@gmail.com>
- */
-#include <linux/gpio/legacy.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/serial_reg.h>
-#include <linux/ata_platform.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include "common.h"
-#include "mpp.h"
-#include "orion5x.h"
-#include "tsx09-common.h"
-
-#define QNAP_TS209_NOR_BOOT_BASE 0xf4000000
-#define QNAP_TS209_NOR_BOOT_SIZE SZ_8M
-
-/****************************************************************************
- * 8MiB NOR flash. The struct mtd_partition is not in the same order as the
- * partitions on the device because we want to keep compatibility with
- * existing QNAP firmware.
- *
- * Layout as used by QNAP:
- * [2] 0x00000000-0x00200000 : "Kernel"
- * [3] 0x00200000-0x00600000 : "RootFS1"
- * [4] 0x00600000-0x00700000 : "RootFS2"
- * [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
- * [5] 0x00760000-0x00780000 : "U-Boot Config"
- * [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
- ***************************************************************************/
-static struct mtd_partition qnap_ts209_partitions[] = {
- {
- .name = "U-Boot",
- .size = 0x00080000,
- .offset = 0x00780000,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "Kernel",
- .size = 0x00200000,
- .offset = 0,
- }, {
- .name = "RootFS1",
- .size = 0x00400000,
- .offset = 0x00200000,
- }, {
- .name = "RootFS2",
- .size = 0x00100000,
- .offset = 0x00600000,
- }, {
- .name = "U-Boot Config",
- .size = 0x00020000,
- .offset = 0x00760000,
- }, {
- .name = "NAS Config",
- .size = 0x00060000,
- .offset = 0x00700000,
- .mask_flags = MTD_WRITEABLE,
- },
-};
-
-static struct physmap_flash_data qnap_ts209_nor_flash_data = {
- .width = 1,
- .parts = qnap_ts209_partitions,
- .nr_parts = ARRAY_SIZE(qnap_ts209_partitions)
-};
-
-static struct resource qnap_ts209_nor_flash_resource = {
- .flags = IORESOURCE_MEM,
- .start = QNAP_TS209_NOR_BOOT_BASE,
- .end = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device qnap_ts209_nor_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &qnap_ts209_nor_flash_data,
- },
- .resource = &qnap_ts209_nor_flash_resource,
- .num_resources = 1,
-};
-
-/*****************************************************************************
- * PCI
- ****************************************************************************/
-
-#define QNAP_TS209_PCI_SLOT0_OFFS 7
-#define QNAP_TS209_PCI_SLOT0_IRQ_PIN 6
-#define QNAP_TS209_PCI_SLOT1_IRQ_PIN 7
-
-static void __init qnap_ts209_pci_preinit(void)
-{
- int pin;
-
- /*
- * Configure PCI GPIO IRQ pins
- */
- pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN;
- if (gpio_request(pin, "PCI Int1") == 0) {
- if (gpio_direction_input(pin) == 0) {
- irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
- } else {
- printk(KERN_ERR "qnap_ts209_pci_preinit failed to "
- "set_irq_type pin %d\n", pin);
- gpio_free(pin);
- }
- } else {
- printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request "
- "%d\n", pin);
- }
-
- pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN;
- if (gpio_request(pin, "PCI Int2") == 0) {
- if (gpio_direction_input(pin) == 0) {
- irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
- } else {
- printk(KERN_ERR "qnap_ts209_pci_preinit failed "
- "to set_irq_type pin %d\n", pin);
- gpio_free(pin);
- }
- } else {
- printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request "
- "%d\n", pin);
- }
-}
-
-static int __init qnap_ts209_pci_map_irq(const struct pci_dev *dev, u8 slot,
- u8 pin)
-{
- int irq;
-
- /*
- * Check for devices with hard-wired IRQs.
- */
- irq = orion5x_pci_map_irq(dev, slot, pin);
- if (irq != -1)
- return irq;
-
- /*
- * PCI IRQs are connected via GPIOs.
- */
- switch (slot - QNAP_TS209_PCI_SLOT0_OFFS) {
- case 0:
- return gpio_to_irq(QNAP_TS209_PCI_SLOT0_IRQ_PIN);
- case 1:
- return gpio_to_irq(QNAP_TS209_PCI_SLOT1_IRQ_PIN);
- default:
- return -1;
- }
-}
-
-static struct hw_pci qnap_ts209_pci __initdata = {
- .nr_controllers = 2,
- .preinit = qnap_ts209_pci_preinit,
- .setup = orion5x_pci_sys_setup,
- .scan = orion5x_pci_sys_scan_bus,
- .map_irq = qnap_ts209_pci_map_irq,
-};
-
-static int __init qnap_ts209_pci_init(void)
-{
- if (machine_is_ts209())
- pci_common_init(&qnap_ts209_pci);
-
- return 0;
-}
-
-subsys_initcall(qnap_ts209_pci_init);
-
-/*****************************************************************************
- * RTC S35390A on I2C bus
- ****************************************************************************/
-
-#define TS209_RTC_GPIO 3
-
-static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = {
- I2C_BOARD_INFO("s35390a", 0x30),
- .irq = 0,
-};
-
-/****************************************************************************
- * GPIO Attached Keys
- * Power button is attached to the PIC microcontroller
- ****************************************************************************/
-
-#define QNAP_TS209_GPIO_KEY_MEDIA 1
-#define QNAP_TS209_GPIO_KEY_RESET 2
-
-static struct gpio_keys_button qnap_ts209_buttons[] = {
- {
- .code = KEY_COPY,
- .gpio = QNAP_TS209_GPIO_KEY_MEDIA,
- .desc = "USB Copy Button",
- .active_low = 1,
- }, {
- .code = KEY_RESTART,
- .gpio = QNAP_TS209_GPIO_KEY_RESET,
- .desc = "Reset Button",
- .active_low = 1,
- },
-};
-
-static struct gpio_keys_platform_data qnap_ts209_button_data = {
- .buttons = qnap_ts209_buttons,
- .nbuttons = ARRAY_SIZE(qnap_ts209_buttons),
-};
-
-static struct platform_device qnap_ts209_button_device = {
- .name = "gpio-keys",
- .id = -1,
- .num_resources = 0,
- .dev = {
- .platform_data = &qnap_ts209_button_data,
- },
-};
-
-/*****************************************************************************
- * SATA
- ****************************************************************************/
-static struct mv_sata_platform_data qnap_ts209_sata_data = {
- .n_ports = 2,
-};
-
-/*****************************************************************************
-
- * General Setup
- ****************************************************************************/
-static unsigned int ts209_mpp_modes[] __initdata = {
- MPP0_UNUSED,
- MPP1_GPIO, /* USB copy button */
- MPP2_GPIO, /* Load defaults button */
- MPP3_GPIO, /* GPIO RTC */
- MPP4_UNUSED,
- MPP5_UNUSED,
- MPP6_GPIO, /* PCI Int A */
- MPP7_GPIO, /* PCI Int B */
- MPP8_UNUSED,
- MPP9_UNUSED,
- MPP10_UNUSED,
- MPP11_UNUSED,
- MPP12_SATA_LED, /* SATA 0 presence */
- MPP13_SATA_LED, /* SATA 1 presence */
- MPP14_SATA_LED, /* SATA 0 active */
- MPP15_SATA_LED, /* SATA 1 active */
- MPP16_UART, /* UART1 RXD */
- MPP17_UART, /* UART1 TXD */
- MPP18_GPIO, /* SW_RST */
- MPP19_UNUSED,
- 0,
-};
-
-static void __init qnap_ts209_init(void)
-{
- /*
- * Setup basic Orion functions. Need to be called early.
- */
- orion5x_init();
-
- orion5x_mpp_conf(ts209_mpp_modes);
-
- /*
- * MPP[20] PCI clock 0
- * MPP[21] PCI clock 1
- * MPP[22] USB 0 over current
- * MPP[23-25] Reserved
- */
-
- /*
- * Configure peripherals.
- */
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
- ORION_MBUS_DEVBUS_BOOT_ATTR,
- QNAP_TS209_NOR_BOOT_BASE,
- QNAP_TS209_NOR_BOOT_SIZE);
- platform_device_register(&qnap_ts209_nor_flash);
-
- orion5x_ehci0_init();
- orion5x_ehci1_init();
- qnap_tsx09_find_mac_addr(QNAP_TS209_NOR_BOOT_BASE +
- qnap_ts209_partitions[5].offset,
- qnap_ts209_partitions[5].size);
- orion5x_eth_init(&qnap_tsx09_eth_data);
- orion5x_i2c_init();
- orion5x_sata_init(&qnap_ts209_sata_data);
- orion5x_uart0_init();
- orion5x_uart1_init();
- orion5x_xor_init();
-
- platform_device_register(&qnap_ts209_button_device);
-
- /* Get RTC IRQ and register the chip */
- if (gpio_request(TS209_RTC_GPIO, "rtc") == 0) {
- if (gpio_direction_input(TS209_RTC_GPIO) == 0)
- qnap_ts209_i2c_rtc.irq = gpio_to_irq(TS209_RTC_GPIO);
- else
- gpio_free(TS209_RTC_GPIO);
- }
- if (qnap_ts209_i2c_rtc.irq == 0)
- pr_warn("qnap_ts209_init: failed to get RTC IRQ\n");
- i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
-
- /* register tsx09 specific power-off method */
- register_platform_power_off(qnap_tsx09_power_off);
-}
-
-MACHINE_START(TS209, "QNAP TS-109/TS-209")
- /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
- .atag_offset = 0x100,
- .nr_irqs = ORION5X_NR_IRQS,
- .init_machine = qnap_ts209_init,
- .map_io = orion5x_map_io,
- .init_early = orion5x_init_early,
- .init_irq = orion5x_init_irq,
- .init_time = orion5x_timer_init,
- .fixup = tag_fixup_mem32,
- .restart = orion5x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
deleted file mode 100644
index f92acef0b45f..000000000000
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ /dev/null
@@ -1,329 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * QNAP TS-409 Board Setup
- *
- * Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com>
- *
- * Copyright (C) 2008 Sylver Bruneau <sylver.bruneau@gmail.com>
- * Copyright (C) 2008 Martin Michlmayr <tbm@cyrius.com>
- */
-#include <linux/gpio/legacy.h>
-#include <linux/gpio/machine.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/leds.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/serial_reg.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include "common.h"
-#include "mpp.h"
-#include "orion5x.h"
-#include "tsx09-common.h"
-
-/*****************************************************************************
- * QNAP TS-409 Info
- ****************************************************************************/
-
-/*
- * QNAP TS-409 hardware :
- * - Marvell 88F5281-D0
- * - Marvell 88SX7042 SATA controller (PCIe)
- * - Marvell 88E1118 Gigabit Ethernet PHY
- * - RTC S35390A (@0x30) on I2C bus
- * - 8MB NOR flash
- * - 256MB of DDR-2 RAM
- */
-
-/*
- * 8MB NOR flash Device bus boot chip select
- */
-
-#define QNAP_TS409_NOR_BOOT_BASE 0xff800000
-#define QNAP_TS409_NOR_BOOT_SIZE SZ_8M
-
-/****************************************************************************
- * 8MiB NOR flash. The struct mtd_partition is not in the same order as the
- * partitions on the device because we want to keep compatibility with
- * existing QNAP firmware.
- *
- * Layout as used by QNAP:
- * [2] 0x00000000-0x00200000 : "Kernel"
- * [3] 0x00200000-0x00600000 : "RootFS1"
- * [4] 0x00600000-0x00700000 : "RootFS2"
- * [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
- * [5] 0x00760000-0x00780000 : "U-Boot Config"
- * [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
- ***************************************************************************/
-static struct mtd_partition qnap_ts409_partitions[] = {
- {
- .name = "U-Boot",
- .size = 0x00080000,
- .offset = 0x00780000,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "Kernel",
- .size = 0x00200000,
- .offset = 0,
- }, {
- .name = "RootFS1",
- .size = 0x00400000,
- .offset = 0x00200000,
- }, {
- .name = "RootFS2",
- .size = 0x00100000,
- .offset = 0x00600000,
- }, {
- .name = "U-Boot Config",
- .size = 0x00020000,
- .offset = 0x00760000,
- }, {
- .name = "NAS Config",
- .size = 0x00060000,
- .offset = 0x00700000,
- .mask_flags = MTD_WRITEABLE,
- },
-};
-
-static struct physmap_flash_data qnap_ts409_nor_flash_data = {
- .width = 1,
- .parts = qnap_ts409_partitions,
- .nr_parts = ARRAY_SIZE(qnap_ts409_partitions)
-};
-
-static struct resource qnap_ts409_nor_flash_resource = {
- .flags = IORESOURCE_MEM,
- .start = QNAP_TS409_NOR_BOOT_BASE,
- .end = QNAP_TS409_NOR_BOOT_BASE + QNAP_TS409_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device qnap_ts409_nor_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = { .platform_data = &qnap_ts409_nor_flash_data, },
- .num_resources = 1,
- .resource = &qnap_ts409_nor_flash_resource,
-};
-
-/*****************************************************************************
- * PCI
- ****************************************************************************/
-
-static int __init qnap_ts409_pci_map_irq(const struct pci_dev *dev, u8 slot,
- u8 pin)
-{
- int irq;
-
- /*
- * Check for devices with hard-wired IRQs.
- */
- irq = orion5x_pci_map_irq(dev, slot, pin);
- if (irq != -1)
- return irq;
-
- /*
- * PCI isn't used on the TS-409
- */
- return -1;
-}
-
-static struct hw_pci qnap_ts409_pci __initdata = {
- .nr_controllers = 2,
- .setup = orion5x_pci_sys_setup,
- .scan = orion5x_pci_sys_scan_bus,
- .map_irq = qnap_ts409_pci_map_irq,
-};
-
-static int __init qnap_ts409_pci_init(void)
-{
- if (machine_is_ts409())
- pci_common_init(&qnap_ts409_pci);
-
- return 0;
-}
-
-subsys_initcall(qnap_ts409_pci_init);
-
-/*****************************************************************************
- * RTC S35390A on I2C bus
- ****************************************************************************/
-
-#define TS409_RTC_GPIO 10
-
-static struct i2c_board_info __initdata qnap_ts409_i2c_rtc = {
- I2C_BOARD_INFO("s35390a", 0x30),
-};
-
-/*****************************************************************************
- * LEDs attached to GPIO
- ****************************************************************************/
-
-static struct gpio_led ts409_led_pins[] = {
- {
- .name = "ts409:red:sata1",
- }, {
- .name = "ts409:red:sata2",
- }, {
- .name = "ts409:red:sata3",
- }, {
- .name = "ts409:red:sata4",
- },
-};
-
-static struct gpiod_lookup_table ts409_leds_gpio_table = {
- .dev_id = "leds-gpio",
- .table = {
- GPIO_LOOKUP_IDX("orion_gpio0", 4, NULL,
- 0, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("orion_gpio0", 5, NULL,
- 1, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("orion_gpio0", 6, NULL,
- 2, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("orion_gpio0", 7, NULL,
- 3, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct gpio_led_platform_data ts409_led_data = {
- .leds = ts409_led_pins,
- .num_leds = ARRAY_SIZE(ts409_led_pins),
-};
-
-static struct platform_device ts409_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &ts409_led_data,
- },
-};
-
-/****************************************************************************
- * GPIO Attached Keys
- * Power button is attached to the PIC microcontroller
- ****************************************************************************/
-
-#define QNAP_TS409_GPIO_KEY_RESET 14
-#define QNAP_TS409_GPIO_KEY_MEDIA 15
-
-static struct gpio_keys_button qnap_ts409_buttons[] = {
- {
- .code = KEY_RESTART,
- .gpio = QNAP_TS409_GPIO_KEY_RESET,
- .desc = "Reset Button",
- .active_low = 1,
- }, {
- .code = KEY_COPY,
- .gpio = QNAP_TS409_GPIO_KEY_MEDIA,
- .desc = "USB Copy Button",
- .active_low = 1,
- },
-};
-
-static struct gpio_keys_platform_data qnap_ts409_button_data = {
- .buttons = qnap_ts409_buttons,
- .nbuttons = ARRAY_SIZE(qnap_ts409_buttons),
-};
-
-static struct platform_device qnap_ts409_button_device = {
- .name = "gpio-keys",
- .id = -1,
- .num_resources = 0,
- .dev = {
- .platform_data = &qnap_ts409_button_data,
- },
-};
-
-/*****************************************************************************
- * General Setup
- ****************************************************************************/
-static unsigned int ts409_mpp_modes[] __initdata = {
- MPP0_UNUSED,
- MPP1_UNUSED,
- MPP2_UNUSED,
- MPP3_UNUSED,
- MPP4_GPIO, /* HDD 1 status */
- MPP5_GPIO, /* HDD 2 status */
- MPP6_GPIO, /* HDD 3 status */
- MPP7_GPIO, /* HDD 4 status */
- MPP8_UNUSED,
- MPP9_UNUSED,
- MPP10_GPIO, /* RTC int */
- MPP11_UNUSED,
- MPP12_UNUSED,
- MPP13_UNUSED,
- MPP14_GPIO, /* SW_RST */
- MPP15_GPIO, /* USB copy button */
- MPP16_UART, /* UART1 RXD */
- MPP17_UART, /* UART1 TXD */
- MPP18_UNUSED,
- MPP19_UNUSED,
- 0,
-};
-
-static void __init qnap_ts409_init(void)
-{
- /*
- * Setup basic Orion functions. Need to be called early.
- */
- orion5x_init();
-
- orion5x_mpp_conf(ts409_mpp_modes);
-
- /*
- * Configure peripherals.
- */
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
- ORION_MBUS_DEVBUS_BOOT_ATTR,
- QNAP_TS409_NOR_BOOT_BASE,
- QNAP_TS409_NOR_BOOT_SIZE);
- platform_device_register(&qnap_ts409_nor_flash);
-
- orion5x_ehci0_init();
- qnap_tsx09_find_mac_addr(QNAP_TS409_NOR_BOOT_BASE +
- qnap_ts409_partitions[5].offset,
- qnap_ts409_partitions[5].size);
- orion5x_eth_init(&qnap_tsx09_eth_data);
- orion5x_i2c_init();
- orion5x_uart0_init();
- orion5x_uart1_init();
-
- platform_device_register(&qnap_ts409_button_device);
-
- /* Get RTC IRQ and register the chip */
- if (gpio_request(TS409_RTC_GPIO, "rtc") == 0) {
- if (gpio_direction_input(TS409_RTC_GPIO) == 0)
- qnap_ts409_i2c_rtc.irq = gpio_to_irq(TS409_RTC_GPIO);
- else
- gpio_free(TS409_RTC_GPIO);
- }
- if (qnap_ts409_i2c_rtc.irq == 0)
- pr_warn("qnap_ts409_init: failed to get RTC IRQ\n");
- i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1);
- gpiod_add_lookup_table(&ts409_leds_gpio_table);
- platform_device_register(&ts409_leds);
-
- /* register tsx09 specific power-off method */
- register_platform_power_off(qnap_tsx09_power_off);
-}
-
-MACHINE_START(TS409, "QNAP TS-409")
- /* Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com> */
- .atag_offset = 0x100,
- .nr_irqs = ORION5X_NR_IRQS,
- .init_machine = qnap_ts409_init,
- .map_io = orion5x_map_io,
- .init_early = orion5x_init_early,
- .init_irq = orion5x_init_irq,
- .init_time = orion5x_timer_init,
- .fixup = tag_fixup_mem32,
- .restart = orion5x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-orion5x/ts78xx-fpga.h b/arch/arm/mach-orion5x/ts78xx-fpga.h
deleted file mode 100644
index 2f4fe3ca5c1a..000000000000
--- a/arch/arm/mach-orion5x/ts78xx-fpga.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#define TS7800_FPGA_MAGIC 0x00b480
-#define FPGAID(_magic, _rev) ((_magic << 8) + _rev)
-
-/*
- * get yer id's from http://ts78xx.digriz.org.uk/
- * do *not* make up your own or 'borrow' any!
- */
-enum fpga_ids {
- /* Technologic Systems */
- TS7800_REV_1 = FPGAID(TS7800_FPGA_MAGIC, 0x01),
- TS7800_REV_2 = FPGAID(TS7800_FPGA_MAGIC, 0x02),
- TS7800_REV_3 = FPGAID(TS7800_FPGA_MAGIC, 0x03),
- TS7800_REV_4 = FPGAID(TS7800_FPGA_MAGIC, 0x04),
- TS7800_REV_5 = FPGAID(TS7800_FPGA_MAGIC, 0x05),
- TS7800_REV_6 = FPGAID(TS7800_FPGA_MAGIC, 0x06),
- TS7800_REV_7 = FPGAID(TS7800_FPGA_MAGIC, 0x07),
- TS7800_REV_8 = FPGAID(TS7800_FPGA_MAGIC, 0x08),
- TS7800_REV_9 = FPGAID(TS7800_FPGA_MAGIC, 0x09),
-
- /* Unaffordable & Expensive */
- UAE_DUMMY = FPGAID(0xffffff, 0x01),
-};
-
-struct fpga_device {
- unsigned present:1;
- unsigned init:1;
-};
-
-struct fpga_devices {
- /* Technologic Systems */
- struct fpga_device ts_rtc;
- struct fpga_device ts_nand;
- struct fpga_device ts_rng;
-};
-
-struct ts78xx_fpga_data {
- unsigned int id;
- int state;
-
- struct fpga_devices supports;
-};
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
deleted file mode 100644
index af810e7ccd79..000000000000
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ /dev/null
@@ -1,574 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-orion5x/ts78xx-setup.c
- *
- * Maintainer: Alexander Clouter <alex@digriz.org.uk>
- */
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/sysfs.h>
-#include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ata_platform.h>
-#include <linux/mtd/platnand.h>
-#include <linux/timeriomem-rng.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include "common.h"
-#include "mpp.h"
-#include "orion5x.h"
-#include "ts78xx-fpga.h"
-
-/*****************************************************************************
- * TS-78xx Info
- ****************************************************************************/
-
-/*
- * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
- */
-#define TS78XX_FPGA_REGS_PHYS_BASE 0xe8000000
-#define TS78XX_FPGA_REGS_VIRT_BASE IOMEM(0xff900000)
-#define TS78XX_FPGA_REGS_SIZE SZ_1M
-
-static struct ts78xx_fpga_data ts78xx_fpga = {
- .id = 0,
- .state = 1,
-/* .supports = ... - populated by ts78xx_fpga_supports() */
-};
-
-/*****************************************************************************
- * I/O Address Mapping
- ****************************************************************************/
-static struct map_desc ts78xx_io_desc[] __initdata = {
- {
- .virtual = (unsigned long)TS78XX_FPGA_REGS_VIRT_BASE,
- .pfn = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE),
- .length = TS78XX_FPGA_REGS_SIZE,
- .type = MT_DEVICE,
- },
-};
-
-static void __init ts78xx_map_io(void)
-{
- orion5x_map_io();
- iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));
-}
-
-/*****************************************************************************
- * Ethernet
- ****************************************************************************/
-static struct mv643xx_eth_platform_data ts78xx_eth_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(0),
-};
-
-/*****************************************************************************
- * SATA
- ****************************************************************************/
-static struct mv_sata_platform_data ts78xx_sata_data = {
- .n_ports = 2,
-};
-
-/*****************************************************************************
- * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
- ****************************************************************************/
-#define TS_RTC_CTRL (TS78XX_FPGA_REGS_PHYS_BASE + 0x808)
-#define TS_RTC_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x80c)
-
-static struct resource ts78xx_ts_rtc_resources[] = {
- DEFINE_RES_MEM(TS_RTC_CTRL, 0x01),
- DEFINE_RES_MEM(TS_RTC_DATA, 0x01),
-};
-
-static struct platform_device ts78xx_ts_rtc_device = {
- .name = "rtc-m48t86",
- .id = -1,
- .resource = ts78xx_ts_rtc_resources,
- .num_resources = ARRAY_SIZE(ts78xx_ts_rtc_resources),
-};
-
-static int ts78xx_ts_rtc_load(void)
-{
- int rc;
-
- if (ts78xx_fpga.supports.ts_rtc.init == 0) {
- rc = platform_device_register(&ts78xx_ts_rtc_device);
- if (!rc)
- ts78xx_fpga.supports.ts_rtc.init = 1;
- } else {
- rc = platform_device_add(&ts78xx_ts_rtc_device);
- }
-
- if (rc)
- pr_info("RTC could not be registered: %d\n", rc);
-
- return rc;
-}
-
-static void ts78xx_ts_rtc_unload(void)
-{
- platform_device_del(&ts78xx_ts_rtc_device);
-}
-
-/*****************************************************************************
- * NAND Flash
- ****************************************************************************/
-#define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE + 0x800) /* VIRT */
-#define TS_NAND_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x804) /* PHYS */
-
-/*
- * hardware specific access to control-lines
- *
- * ctrl:
- * NAND_NCE: bit 0 -> bit 2
- * NAND_CLE: bit 1 -> bit 1
- * NAND_ALE: bit 2 -> bit 0
- */
-static void ts78xx_ts_nand_cmd_ctrl(struct nand_chip *this, int cmd,
- unsigned int ctrl)
-{
- if (ctrl & NAND_CTRL_CHANGE) {
- unsigned char bits;
-
- bits = (ctrl & NAND_NCE) << 2;
- bits |= ctrl & NAND_CLE;
- bits |= (ctrl & NAND_ALE) >> 2;
-
- writeb((readb(TS_NAND_CTRL) & ~0x7) | bits, TS_NAND_CTRL);
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->legacy.IO_ADDR_W);
-}
-
-static int ts78xx_ts_nand_dev_ready(struct nand_chip *chip)
-{
- return readb(TS_NAND_CTRL) & 0x20;
-}
-
-static void ts78xx_ts_nand_write_buf(struct nand_chip *chip,
- const uint8_t *buf, int len)
-{
- void __iomem *io_base = chip->legacy.IO_ADDR_W;
- unsigned long off = ((unsigned long)buf & 3);
- int sz;
-
- if (off) {
- sz = min_t(int, 4 - off, len);
- writesb(io_base, buf, sz);
- buf += sz;
- len -= sz;
- }
-
- sz = len >> 2;
- if (sz) {
- u32 *buf32 = (u32 *)buf;
- writesl(io_base, buf32, sz);
- buf += sz << 2;
- len -= sz << 2;
- }
-
- if (len)
- writesb(io_base, buf, len);
-}
-
-static void ts78xx_ts_nand_read_buf(struct nand_chip *chip,
- uint8_t *buf, int len)
-{
- void __iomem *io_base = chip->legacy.IO_ADDR_R;
- unsigned long off = ((unsigned long)buf & 3);
- int sz;
-
- if (off) {
- sz = min_t(int, 4 - off, len);
- readsb(io_base, buf, sz);
- buf += sz;
- len -= sz;
- }
-
- sz = len >> 2;
- if (sz) {
- u32 *buf32 = (u32 *)buf;
- readsl(io_base, buf32, sz);
- buf += sz << 2;
- len -= sz << 2;
- }
-
- if (len)
- readsb(io_base, buf, len);
-}
-
-static struct mtd_partition ts78xx_ts_nand_parts[] = {
- {
- .name = "mbr",
- .offset = 0,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_4M,
- }, {
- .name = "initrd",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_4M,
- }, {
- .name = "rootfs",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct platform_nand_data ts78xx_ts_nand_data = {
- .chip = {
- .nr_chips = 1,
- .partitions = ts78xx_ts_nand_parts,
- .nr_partitions = ARRAY_SIZE(ts78xx_ts_nand_parts),
- .chip_delay = 15,
- .bbt_options = NAND_BBT_USE_FLASH,
- },
- .ctrl = {
- /*
- * The HW ECC offloading functions, used to give about a 9%
- * performance increase for 'dd if=/dev/mtdblockX' and 5% for
- * nanddump. This all however was changed by git commit
- * e6cf5df1838c28bb060ac45b5585e48e71bbc740 so now there is
- * no performance advantage to be had so we no longer bother
- */
- .cmd_ctrl = ts78xx_ts_nand_cmd_ctrl,
- .dev_ready = ts78xx_ts_nand_dev_ready,
- .write_buf = ts78xx_ts_nand_write_buf,
- .read_buf = ts78xx_ts_nand_read_buf,
- },
-};
-
-static struct resource ts78xx_ts_nand_resources
- = DEFINE_RES_MEM(TS_NAND_DATA, 4);
-
-static struct platform_device ts78xx_ts_nand_device = {
- .name = "gen_nand",
- .id = -1,
- .dev = {
- .platform_data = &ts78xx_ts_nand_data,
- },
- .resource = &ts78xx_ts_nand_resources,
- .num_resources = 1,
-};
-
-static int ts78xx_ts_nand_load(void)
-{
- int rc;
-
- if (ts78xx_fpga.supports.ts_nand.init == 0) {
- rc = platform_device_register(&ts78xx_ts_nand_device);
- if (!rc)
- ts78xx_fpga.supports.ts_nand.init = 1;
- } else
- rc = platform_device_add(&ts78xx_ts_nand_device);
-
- if (rc)
- pr_info("NAND could not be registered: %d\n", rc);
- return rc;
-};
-
-static void ts78xx_ts_nand_unload(void)
-{
- platform_device_del(&ts78xx_ts_nand_device);
-}
-
-/*****************************************************************************
- * HW RNG
- ****************************************************************************/
-#define TS_RNG_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x044)
-
-static struct resource ts78xx_ts_rng_resource
- = DEFINE_RES_MEM(TS_RNG_DATA, 4);
-
-static struct timeriomem_rng_data ts78xx_ts_rng_data = {
- .period = 1000000, /* one second */
-};
-
-static struct platform_device ts78xx_ts_rng_device = {
- .name = "timeriomem_rng",
- .id = -1,
- .dev = {
- .platform_data = &ts78xx_ts_rng_data,
- },
- .resource = &ts78xx_ts_rng_resource,
- .num_resources = 1,
-};
-
-static int ts78xx_ts_rng_load(void)
-{
- int rc;
-
- if (ts78xx_fpga.supports.ts_rng.init == 0) {
- rc = platform_device_register(&ts78xx_ts_rng_device);
- if (!rc)
- ts78xx_fpga.supports.ts_rng.init = 1;
- } else
- rc = platform_device_add(&ts78xx_ts_rng_device);
-
- if (rc)
- pr_info("RNG could not be registered: %d\n", rc);
- return rc;
-};
-
-static void ts78xx_ts_rng_unload(void)
-{
- platform_device_del(&ts78xx_ts_rng_device);
-}
-
-/*****************************************************************************
- * FPGA 'hotplug' support code
- ****************************************************************************/
-static void ts78xx_fpga_devices_zero_init(void)
-{
- ts78xx_fpga.supports.ts_rtc.init = 0;
- ts78xx_fpga.supports.ts_nand.init = 0;
- ts78xx_fpga.supports.ts_rng.init = 0;
-}
-
-static void ts78xx_fpga_supports(void)
-{
- /* TODO: put this 'table' into ts78xx-fpga.h */
- switch (ts78xx_fpga.id) {
- case TS7800_REV_1:
- case TS7800_REV_2:
- case TS7800_REV_3:
- case TS7800_REV_4:
- case TS7800_REV_5:
- case TS7800_REV_6:
- case TS7800_REV_7:
- case TS7800_REV_8:
- case TS7800_REV_9:
- ts78xx_fpga.supports.ts_rtc.present = 1;
- ts78xx_fpga.supports.ts_nand.present = 1;
- ts78xx_fpga.supports.ts_rng.present = 1;
- break;
- default:
- /* enable devices if magic matches */
- switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
- case TS7800_FPGA_MAGIC:
- pr_warn("unrecognised FPGA revision 0x%.2x\n",
- ts78xx_fpga.id & 0xff);
- ts78xx_fpga.supports.ts_rtc.present = 1;
- ts78xx_fpga.supports.ts_nand.present = 1;
- ts78xx_fpga.supports.ts_rng.present = 1;
- break;
- default:
- ts78xx_fpga.supports.ts_rtc.present = 0;
- ts78xx_fpga.supports.ts_nand.present = 0;
- ts78xx_fpga.supports.ts_rng.present = 0;
- }
- }
-}
-
-static int ts78xx_fpga_load_devices(void)
-{
- int tmp, ret = 0;
-
- if (ts78xx_fpga.supports.ts_rtc.present == 1) {
- tmp = ts78xx_ts_rtc_load();
- if (tmp)
- ts78xx_fpga.supports.ts_rtc.present = 0;
- ret |= tmp;
- }
- if (ts78xx_fpga.supports.ts_nand.present == 1) {
- tmp = ts78xx_ts_nand_load();
- if (tmp)
- ts78xx_fpga.supports.ts_nand.present = 0;
- ret |= tmp;
- }
- if (ts78xx_fpga.supports.ts_rng.present == 1) {
- tmp = ts78xx_ts_rng_load();
- if (tmp)
- ts78xx_fpga.supports.ts_rng.present = 0;
- ret |= tmp;
- }
-
- return ret;
-}
-
-static int ts78xx_fpga_unload_devices(void)
-{
-
- if (ts78xx_fpga.supports.ts_rtc.present == 1)
- ts78xx_ts_rtc_unload();
- if (ts78xx_fpga.supports.ts_nand.present == 1)
- ts78xx_ts_nand_unload();
- if (ts78xx_fpga.supports.ts_rng.present == 1)
- ts78xx_ts_rng_unload();
-
- return 0;
-}
-
-static int ts78xx_fpga_load(void)
-{
- ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
-
- pr_info("FPGA magic=0x%.6x, rev=0x%.2x\n",
- (ts78xx_fpga.id >> 8) & 0xffffff,
- ts78xx_fpga.id & 0xff);
-
- ts78xx_fpga_supports();
-
- if (ts78xx_fpga_load_devices()) {
- ts78xx_fpga.state = -1;
- return -EBUSY;
- }
-
- return 0;
-};
-
-static int ts78xx_fpga_unload(void)
-{
- unsigned int fpga_id;
-
- fpga_id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
-
- /*
- * There does not seem to be a feasible way to block access to the GPIO
- * pins from userspace (/dev/mem). This if clause should hopefully warn
- * those foolish enough not to follow 'policy' :)
- *
- * UrJTAG SVN since r1381 can be used to reprogram the FPGA
- */
- if (ts78xx_fpga.id != fpga_id) {
- pr_err("FPGA magic/rev mismatch\n"
- "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n",
- (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff,
- (fpga_id >> 8) & 0xffffff, fpga_id & 0xff);
- ts78xx_fpga.state = -1;
- return -EBUSY;
- }
-
- if (ts78xx_fpga_unload_devices()) {
- ts78xx_fpga.state = -1;
- return -EBUSY;
- }
-
- return 0;
-};
-
-static ssize_t ts78xx_fpga_show(struct kobject *kobj,
- struct kobj_attribute *attr, char *buf)
-{
- if (ts78xx_fpga.state < 0)
- return sprintf(buf, "borked\n");
-
- return sprintf(buf, "%s\n", (ts78xx_fpga.state) ? "online" : "offline");
-}
-
-static ssize_t ts78xx_fpga_store(struct kobject *kobj,
- struct kobj_attribute *attr, const char *buf, size_t n)
-{
- int value, ret;
-
- if (ts78xx_fpga.state < 0) {
- pr_err("FPGA borked, you must powercycle ASAP\n");
- return -EBUSY;
- }
-
- if (strncmp(buf, "online", sizeof("online") - 1) == 0)
- value = 1;
- else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0)
- value = 0;
- else
- return -EINVAL;
-
- if (ts78xx_fpga.state == value)
- return n;
-
- ret = (ts78xx_fpga.state == 0)
- ? ts78xx_fpga_load()
- : ts78xx_fpga_unload();
-
- if (!(ret < 0))
- ts78xx_fpga.state = value;
-
- return n;
-}
-
-static struct kobj_attribute ts78xx_fpga_attr =
- __ATTR(ts78xx_fpga, 0644, ts78xx_fpga_show, ts78xx_fpga_store);
-
-/*****************************************************************************
- * General Setup
- ****************************************************************************/
-static unsigned int ts78xx_mpp_modes[] __initdata = {
- MPP0_UNUSED,
- MPP1_GPIO, /* JTAG Clock */
- MPP2_GPIO, /* JTAG Data In */
- MPP3_GPIO, /* Lat ECP2 256 FPGA - PB2B */
- MPP4_GPIO, /* JTAG Data Out */
- MPP5_GPIO, /* JTAG TMS */
- MPP6_GPIO, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
- MPP7_GPIO, /* Lat ECP2 256 FPGA - PB22B */
- MPP8_UNUSED,
- MPP9_UNUSED,
- MPP10_UNUSED,
- MPP11_UNUSED,
- MPP12_UNUSED,
- MPP13_UNUSED,
- MPP14_UNUSED,
- MPP15_UNUSED,
- MPP16_UART,
- MPP17_UART,
- MPP18_UART,
- MPP19_UART,
- /*
- * MPP[20] PCI Clock Out 1
- * MPP[21] PCI Clock Out 0
- * MPP[22] Unused
- * MPP[23] Unused
- * MPP[24] Unused
- * MPP[25] Unused
- */
- 0,
-};
-
-static void __init ts78xx_init(void)
-{
- int ret;
-
- /*
- * Setup basic Orion functions. Need to be called early.
- */
- orion5x_init();
-
- orion5x_mpp_conf(ts78xx_mpp_modes);
-
- /*
- * Configure peripherals.
- */
- orion5x_ehci0_init();
- orion5x_ehci1_init();
- orion5x_eth_init(&ts78xx_eth_data);
- orion5x_sata_init(&ts78xx_sata_data);
- orion5x_uart0_init();
- orion5x_uart1_init();
- orion5x_xor_init();
-
- /* FPGA init */
- ts78xx_fpga_devices_zero_init();
- ret = ts78xx_fpga_load();
- ret = sysfs_create_file(firmware_kobj, &ts78xx_fpga_attr.attr);
- if (ret)
- pr_err("sysfs_create_file failed: %d\n", ret);
-}
-
-MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
- /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
- .atag_offset = 0x100,
- .nr_irqs = ORION5X_NR_IRQS,
- .init_machine = ts78xx_init,
- .map_io = ts78xx_map_io,
- .init_early = orion5x_init_early,
- .init_irq = orion5x_init_irq,
- .init_time = orion5x_timer_init,
- .restart = orion5x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-orion5x/tsx09-common.c b/arch/arm/mach-orion5x/tsx09-common.c
deleted file mode 100644
index 099e6fdfa8e6..000000000000
--- a/arch/arm/mach-orion5x/tsx09-common.c
+++ /dev/null
@@ -1,129 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * QNAP TS-x09 Boards common functions
- *
- * Maintainers: Lennert Buytenhek <buytenh@marvell.com>
- * Byron Bradley <byron.bbradley@gmail.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/timex.h>
-#include <linux/serial_reg.h>
-#include "orion5x.h"
-#include "tsx09-common.h"
-#include "common.h"
-
-/*****************************************************************************
- * QNAP TS-x09 specific power off method via UART1-attached PIC
- ****************************************************************************/
-
-#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
-
-void qnap_tsx09_power_off(void)
-{
- /* 19200 baud divisor */
- const unsigned divisor = ((orion5x_tclk + (8 * 19200)) / (16 * 19200));
-
- pr_info("%s: triggering power-off...\n", __func__);
-
- /* hijack uart1 and reset into sane state (19200,8n1) */
- writel(0x83, UART1_REG(LCR));
- writel(divisor & 0xff, UART1_REG(DLL));
- writel((divisor >> 8) & 0xff, UART1_REG(DLM));
- writel(0x03, UART1_REG(LCR));
- writel(0x00, UART1_REG(IER));
- writel(0x00, UART1_REG(FCR));
- writel(0x00, UART1_REG(MCR));
-
- /* send the power-off command 'A' to PIC */
- writel('A', UART1_REG(TX));
-}
-
-/*****************************************************************************
- * Ethernet
- ****************************************************************************/
-
-struct mv643xx_eth_platform_data qnap_tsx09_eth_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
-};
-
-static int __init qnap_tsx09_parse_hex_nibble(char n)
-{
- if (n >= '0' && n <= '9')
- return n - '0';
-
- if (n >= 'A' && n <= 'F')
- return n - 'A' + 10;
-
- if (n >= 'a' && n <= 'f')
- return n - 'a' + 10;
-
- return -1;
-}
-
-static int __init qnap_tsx09_parse_hex_byte(const char *b)
-{
- int hi;
- int lo;
-
- hi = qnap_tsx09_parse_hex_nibble(b[0]);
- lo = qnap_tsx09_parse_hex_nibble(b[1]);
-
- if (hi < 0 || lo < 0)
- return -1;
-
- return (hi << 4) | lo;
-}
-
-static int __init qnap_tsx09_check_mac_addr(const char *addr_str)
-{
- u_int8_t addr[6];
- int i;
-
- for (i = 0; i < 6; i++) {
- int byte;
-
- /*
- * Enforce "xx:xx:xx:xx:xx:xx\n" format.
- */
- if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n'))
- return -1;
-
- byte = qnap_tsx09_parse_hex_byte(addr_str + (i * 3));
- if (byte < 0)
- return -1;
- addr[i] = byte;
- }
-
- printk(KERN_INFO "tsx09: found ethernet mac address %pM\n", addr);
-
- memcpy(qnap_tsx09_eth_data.mac_addr, addr, 6);
-
- return 0;
-}
-
-/*
- * The 'NAS Config' flash partition has an ext2 filesystem which
- * contains a file that has the ethernet MAC address in plain text
- * (format "xx:xx:xx:xx:xx:xx\n").
- */
-void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size)
-{
- unsigned long addr;
-
- for (addr = mem_base; addr < (mem_base + size); addr += 1024) {
- char *nor_page;
- int ret = 0;
-
- nor_page = ioremap(addr, 1024);
- if (nor_page != NULL) {
- ret = qnap_tsx09_check_mac_addr(nor_page);
- iounmap(nor_page);
- }
-
- if (ret == 0)
- break;
- }
-}
diff --git a/arch/arm/mach-orion5x/tsx09-common.h b/arch/arm/mach-orion5x/tsx09-common.h
deleted file mode 100644
index 72bedc6b82fb..000000000000
--- a/arch/arm/mach-orion5x/tsx09-common.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ARCH_ORION5X_TSX09_COMMON_H
-#define __ARCH_ORION5X_TSX09_COMMON_H
-
-/*
- * QNAP TS-x09 Boards power-off function
- */
-extern void qnap_tsx09_power_off(void);
-
-/*
- * QNAP TS-x09 Boards function to find Ethernet MAC address in flash memory
- */
-extern void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size);
-
-/*
- * QNAP TS-x09 Boards ethernet declaration
- */
-extern struct mv643xx_eth_platform_data qnap_tsx09_eth_data;
-
-
-#endif
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 6574659dfb61..c40cdb2274ea 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -980,7 +980,7 @@ config CACHE_B15_RAC
config CACHE_FEROCEON_L2
bool "Enable the Feroceon L2 cache controller"
- depends on ARCH_MV78XX0 || ARCH_MVEBU
+ depends on ARCH_MVEBU
default y
select OUTER_CACHE
help
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index e8c7580df8ca..dfde39cdd992 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -5,5 +5,5 @@
ccflags-y := -I$(src)/include
orion-gpio-$(CONFIG_GPIOLIB) += gpio.o
-obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o
+obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o mpp.o
obj-$(CONFIG_PLAT_ORION_LEGACY) += $(orion-gpio-y)
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
deleted file mode 100644
index cabe98386245..000000000000
--- a/arch/arm/plat-orion/common.c
+++ /dev/null
@@ -1,826 +0,0 @@
-/*
- * arch/arm/plat-orion/common.c
- *
- * Marvell Orion SoC common setup code used by multiple mach-/common.c
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/serial_8250.h>
-#include <linux/ata_platform.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/mv643xx_i2c.h>
-#include <linux/platform_data/dma-mv_xor.h>
-#include <linux/platform_data/usb-ehci-orion.h>
-#include <plat/common.h>
-#include <linux/phy.h>
-
-/* Create a clkdev entry for a given device/clk */
-void __init orion_clkdev_add(const char *con_id, const char *dev_id,
- struct clk *clk)
-{
- clkdev_create(clk, con_id, "%s", dev_id);
-}
-
-/* Create clkdev entries for all orion platforms except kirkwood.
- Kirkwood has gated clocks for some of its peripherals, so creates
- its own clkdev entries. For all the other orion devices, create
- clkdev entries to the tclk. */
-void __init orion_clkdev_init(struct clk *tclk)
-{
- orion_clkdev_add(NULL, "orion_spi.0", tclk);
- orion_clkdev_add(NULL, "orion_spi.1", tclk);
- orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", tclk);
- orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", tclk);
- orion_clkdev_add(NULL, MV643XX_ETH_NAME ".2", tclk);
- orion_clkdev_add(NULL, MV643XX_ETH_NAME ".3", tclk);
- orion_clkdev_add(NULL, "orion_wdt", tclk);
- orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", tclk);
-}
-
-/* Fill in the resources structure and link it into the platform
- device structure. There is always a memory region, and nearly
- always an interrupt.*/
-static void fill_resources(struct platform_device *device,
- struct resource *resources,
- resource_size_t mapbase,
- resource_size_t size)
-{
- device->resource = resources;
- device->num_resources = 1;
- resources[0].flags = IORESOURCE_MEM;
- resources[0].start = mapbase;
- resources[0].end = mapbase + size;
-}
-
-static void fill_resources_irq(struct platform_device *device,
- struct resource *resources,
- resource_size_t mapbase,
- resource_size_t size,
- unsigned int irq)
-{
- fill_resources(device, resources, mapbase, size);
-
- device->num_resources++;
- resources[1].flags = IORESOURCE_IRQ;
- resources[1].start = irq;
- resources[1].end = irq;
-}
-
-/*****************************************************************************
- * UART
- ****************************************************************************/
-static unsigned long __init uart_get_clk_rate(struct clk *clk)
-{
- clk_prepare_enable(clk);
- return clk_get_rate(clk);
-}
-
-static void __init uart_complete(
- struct platform_device *orion_uart,
- struct plat_serial8250_port *data,
- struct resource *resources,
- void __iomem *membase,
- resource_size_t mapbase,
- unsigned int irq,
- struct clk *clk)
-{
- data->mapbase = mapbase;
- data->membase = membase;
- data->irq = irq;
- data->uartclk = uart_get_clk_rate(clk);
- orion_uart->dev.platform_data = data;
-
- fill_resources_irq(orion_uart, resources, mapbase, 0xff, irq);
- platform_device_register(orion_uart);
-}
-
-/*****************************************************************************
- * UART0
- ****************************************************************************/
-static struct plat_serial8250_port orion_uart0_data[] = {
- {
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- }, {
- },
-};
-
-static struct resource orion_uart0_resources[2];
-
-static struct platform_device orion_uart0 = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
-};
-
-void __init orion_uart0_init(void __iomem *membase,
- resource_size_t mapbase,
- unsigned int irq,
- struct clk *clk)
-{
- uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources,
- membase, mapbase, irq, clk);
-}
-
-/*****************************************************************************
- * UART1
- ****************************************************************************/
-static struct plat_serial8250_port orion_uart1_data[] = {
- {
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- }, {
- },
-};
-
-static struct resource orion_uart1_resources[2];
-
-static struct platform_device orion_uart1 = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM1,
-};
-
-void __init orion_uart1_init(void __iomem *membase,
- resource_size_t mapbase,
- unsigned int irq,
- struct clk *clk)
-{
- uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources,
- membase, mapbase, irq, clk);
-}
-
-/*****************************************************************************
- * UART2
- ****************************************************************************/
-static struct plat_serial8250_port orion_uart2_data[] = {
- {
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- }, {
- },
-};
-
-static struct resource orion_uart2_resources[2];
-
-static struct platform_device orion_uart2 = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM2,
-};
-
-void __init orion_uart2_init(void __iomem *membase,
- resource_size_t mapbase,
- unsigned int irq,
- struct clk *clk)
-{
- uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources,
- membase, mapbase, irq, clk);
-}
-
-/*****************************************************************************
- * UART3
- ****************************************************************************/
-static struct plat_serial8250_port orion_uart3_data[] = {
- {
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- }, {
- },
-};
-
-static struct resource orion_uart3_resources[2];
-
-static struct platform_device orion_uart3 = {
- .name = "serial8250",
- .id = 3,
-};
-
-void __init orion_uart3_init(void __iomem *membase,
- resource_size_t mapbase,
- unsigned int irq,
- struct clk *clk)
-{
- uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources,
- membase, mapbase, irq, clk);
-}
-
-/*****************************************************************************
- * SoC RTC
- ****************************************************************************/
-static struct resource orion_rtc_resource[2];
-
-void __init orion_rtc_init(unsigned long mapbase,
- unsigned long irq)
-{
- orion_rtc_resource[0].start = mapbase;
- orion_rtc_resource[0].end = mapbase + SZ_32 - 1;
- orion_rtc_resource[0].flags = IORESOURCE_MEM;
- orion_rtc_resource[1].start = irq;
- orion_rtc_resource[1].end = irq;
- orion_rtc_resource[1].flags = IORESOURCE_IRQ;
-
- platform_device_register_simple("rtc-mv", -1, orion_rtc_resource, 2);
-}
-
-/*****************************************************************************
- * GE
- ****************************************************************************/
-static __init void ge_complete(
- struct mv643xx_eth_shared_platform_data *orion_ge_shared_data,
- struct resource *orion_ge_resource, unsigned long irq,
- struct platform_device *orion_ge_shared,
- struct platform_device *orion_ge_mvmdio,
- struct mv643xx_eth_platform_data *eth_data,
- struct platform_device *orion_ge)
-{
- orion_ge_resource->start = irq;
- orion_ge_resource->end = irq;
- eth_data->shared = orion_ge_shared;
- orion_ge->dev.platform_data = eth_data;
-
- platform_device_register(orion_ge_shared);
- if (orion_ge_mvmdio)
- platform_device_register(orion_ge_mvmdio);
- platform_device_register(orion_ge);
-}
-
-/*****************************************************************************
- * GE00
- ****************************************************************************/
-static struct mv643xx_eth_shared_platform_data orion_ge00_shared_data;
-
-static struct resource orion_ge00_shared_resources[] = {
- {
- .name = "ge00 base",
- },
-};
-
-static struct platform_device orion_ge00_shared = {
- .name = MV643XX_ETH_SHARED_NAME,
- .id = 0,
- .dev = {
- .platform_data = &orion_ge00_shared_data,
- },
-};
-
-static struct resource orion_ge_mvmdio_resources[] = {
- {
- .name = "ge00 mvmdio base",
- }, {
- .name = "ge00 mvmdio err irq",
- },
-};
-
-static struct platform_device orion_ge_mvmdio = {
- .name = "orion-mdio",
- .id = -1,
-};
-
-static struct resource orion_ge00_resources[] = {
- {
- .name = "ge00 irq",
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device orion_ge00 = {
- .name = MV643XX_ETH_NAME,
- .id = 0,
- .num_resources = 1,
- .resource = orion_ge00_resources,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
- unsigned long mapbase,
- unsigned long irq,
- unsigned long irq_err,
- unsigned int tx_csum_limit)
-{
- fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
- mapbase + 0x2000, SZ_16K - 1);
- fill_resources_irq(&orion_ge_mvmdio, orion_ge_mvmdio_resources,
- mapbase + 0x2004, 0x84 - 1, irq_err);
- orion_ge00_shared_data.tx_csum_limit = tx_csum_limit;
- ge_complete(&orion_ge00_shared_data,
- orion_ge00_resources, irq, &orion_ge00_shared,
- &orion_ge_mvmdio,
- eth_data, &orion_ge00);
-}
-
-/*****************************************************************************
- * GE01
- ****************************************************************************/
-static struct mv643xx_eth_shared_platform_data orion_ge01_shared_data;
-
-static struct resource orion_ge01_shared_resources[] = {
- {
- .name = "ge01 base",
- }
-};
-
-static struct platform_device orion_ge01_shared = {
- .name = MV643XX_ETH_SHARED_NAME,
- .id = 1,
- .dev = {
- .platform_data = &orion_ge01_shared_data,
- },
-};
-
-static struct resource orion_ge01_resources[] = {
- {
- .name = "ge01 irq",
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device orion_ge01 = {
- .name = MV643XX_ETH_NAME,
- .id = 1,
- .num_resources = 1,
- .resource = orion_ge01_resources,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
- unsigned long mapbase,
- unsigned long irq,
- unsigned int tx_csum_limit)
-{
- fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
- mapbase + 0x2000, SZ_16K - 1);
- orion_ge01_shared_data.tx_csum_limit = tx_csum_limit;
- ge_complete(&orion_ge01_shared_data,
- orion_ge01_resources, irq, &orion_ge01_shared,
- NULL,
- eth_data, &orion_ge01);
-}
-
-/*****************************************************************************
- * GE10
- ****************************************************************************/
-static struct mv643xx_eth_shared_platform_data orion_ge10_shared_data;
-
-static struct resource orion_ge10_shared_resources[] = {
- {
- .name = "ge10 base",
- }
-};
-
-static struct platform_device orion_ge10_shared = {
- .name = MV643XX_ETH_SHARED_NAME,
- .id = 2,
- .dev = {
- .platform_data = &orion_ge10_shared_data,
- },
-};
-
-static struct resource orion_ge10_resources[] = {
- {
- .name = "ge10 irq",
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device orion_ge10 = {
- .name = MV643XX_ETH_NAME,
- .id = 2,
- .num_resources = 1,
- .resource = orion_ge10_resources,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
- unsigned long mapbase,
- unsigned long irq)
-{
- fill_resources(&orion_ge10_shared, orion_ge10_shared_resources,
- mapbase + 0x2000, SZ_16K - 1);
- ge_complete(&orion_ge10_shared_data,
- orion_ge10_resources, irq, &orion_ge10_shared,
- NULL,
- eth_data, &orion_ge10);
-}
-
-/*****************************************************************************
- * GE11
- ****************************************************************************/
-static struct mv643xx_eth_shared_platform_data orion_ge11_shared_data;
-
-static struct resource orion_ge11_shared_resources[] = {
- {
- .name = "ge11 base",
- },
-};
-
-static struct platform_device orion_ge11_shared = {
- .name = MV643XX_ETH_SHARED_NAME,
- .id = 3,
- .dev = {
- .platform_data = &orion_ge11_shared_data,
- },
-};
-
-static struct resource orion_ge11_resources[] = {
- {
- .name = "ge11 irq",
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device orion_ge11 = {
- .name = MV643XX_ETH_NAME,
- .id = 3,
- .num_resources = 1,
- .resource = orion_ge11_resources,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
- unsigned long mapbase,
- unsigned long irq)
-{
- fill_resources(&orion_ge11_shared, orion_ge11_shared_resources,
- mapbase + 0x2000, SZ_16K - 1);
- ge_complete(&orion_ge11_shared_data,
- orion_ge11_resources, irq, &orion_ge11_shared,
- NULL,
- eth_data, &orion_ge11);
-}
-
-/*****************************************************************************
- * I2C
- ****************************************************************************/
-static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
- .freq_n = 3,
- .timeout = 1000, /* Default timeout of 1 second */
-};
-
-static struct resource orion_i2c_resources[2];
-
-static struct platform_device orion_i2c = {
- .name = MV64XXX_I2C_CTLR_NAME,
- .id = 0,
- .dev = {
- .platform_data = &orion_i2c_pdata,
- },
-};
-
-static struct mv64xxx_i2c_pdata orion_i2c_1_pdata = {
- .freq_n = 3,
- .timeout = 1000, /* Default timeout of 1 second */
-};
-
-static struct resource orion_i2c_1_resources[2];
-
-static struct platform_device orion_i2c_1 = {
- .name = MV64XXX_I2C_CTLR_NAME,
- .id = 1,
- .dev = {
- .platform_data = &orion_i2c_1_pdata,
- },
-};
-
-void __init orion_i2c_init(unsigned long mapbase,
- unsigned long irq,
- unsigned long freq_m)
-{
- orion_i2c_pdata.freq_m = freq_m;
- fill_resources_irq(&orion_i2c, orion_i2c_resources, mapbase,
- SZ_32 - 1, irq);
- platform_device_register(&orion_i2c);
-}
-
-void __init orion_i2c_1_init(unsigned long mapbase,
- unsigned long irq,
- unsigned long freq_m)
-{
- orion_i2c_1_pdata.freq_m = freq_m;
- fill_resources_irq(&orion_i2c_1, orion_i2c_1_resources, mapbase,
- SZ_32 - 1, irq);
- platform_device_register(&orion_i2c_1);
-}
-
-/*****************************************************************************
- * SPI
- ****************************************************************************/
-static struct resource orion_spi_resources;
-
-static struct platform_device orion_spi = {
- .name = "orion_spi",
- .id = 0,
-};
-
-static struct resource orion_spi_1_resources;
-
-static struct platform_device orion_spi_1 = {
- .name = "orion_spi",
- .id = 1,
-};
-
-/* Note: The SPI silicon core does have interrupts. However the
- * current Linux software driver does not use interrupts. */
-
-void __init orion_spi_init(unsigned long mapbase)
-{
- fill_resources(&orion_spi, &orion_spi_resources,
- mapbase, SZ_512 - 1);
- platform_device_register(&orion_spi);
-}
-
-void __init orion_spi_1_init(unsigned long mapbase)
-{
- fill_resources(&orion_spi_1, &orion_spi_1_resources,
- mapbase, SZ_512 - 1);
- platform_device_register(&orion_spi_1);
-}
-
-/*****************************************************************************
- * XOR
- ****************************************************************************/
-static u64 orion_xor_dmamask = DMA_BIT_MASK(32);
-
-/*****************************************************************************
- * XOR0
- ****************************************************************************/
-static struct resource orion_xor0_shared_resources[] = {
- {
- .name = "xor 0 low",
- .flags = IORESOURCE_MEM,
- }, {
- .name = "xor 0 high",
- .flags = IORESOURCE_MEM,
- }, {
- .name = "irq channel 0",
- .flags = IORESOURCE_IRQ,
- }, {
- .name = "irq channel 1",
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct mv_xor_channel_data orion_xor0_channels_data[2];
-
-static struct mv_xor_platform_data orion_xor0_pdata = {
- .channels = orion_xor0_channels_data,
-};
-
-static struct platform_device orion_xor0_shared = {
- .name = MV_XOR_NAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(orion_xor0_shared_resources),
- .resource = orion_xor0_shared_resources,
- .dev = {
- .dma_mask = &orion_xor_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &orion_xor0_pdata,
- },
-};
-
-void __init orion_xor0_init(unsigned long mapbase_low,
- unsigned long mapbase_high,
- unsigned long irq_0,
- unsigned long irq_1)
-{
- orion_xor0_shared_resources[0].start = mapbase_low;
- orion_xor0_shared_resources[0].end = mapbase_low + 0xff;
- orion_xor0_shared_resources[1].start = mapbase_high;
- orion_xor0_shared_resources[1].end = mapbase_high + 0xff;
-
- orion_xor0_shared_resources[2].start = irq_0;
- orion_xor0_shared_resources[2].end = irq_0;
- orion_xor0_shared_resources[3].start = irq_1;
- orion_xor0_shared_resources[3].end = irq_1;
-
- dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[0].cap_mask);
- dma_cap_set(DMA_XOR, orion_xor0_channels_data[0].cap_mask);
-
- dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[1].cap_mask);
- dma_cap_set(DMA_XOR, orion_xor0_channels_data[1].cap_mask);
-
- platform_device_register(&orion_xor0_shared);
-}
-
-/*****************************************************************************
- * XOR1
- ****************************************************************************/
-static struct resource orion_xor1_shared_resources[] = {
- {
- .name = "xor 1 low",
- .flags = IORESOURCE_MEM,
- }, {
- .name = "xor 1 high",
- .flags = IORESOURCE_MEM,
- }, {
- .name = "irq channel 0",
- .flags = IORESOURCE_IRQ,
- }, {
- .name = "irq channel 1",
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct mv_xor_channel_data orion_xor1_channels_data[2];
-
-static struct mv_xor_platform_data orion_xor1_pdata = {
- .channels = orion_xor1_channels_data,
-};
-
-static struct platform_device orion_xor1_shared = {
- .name = MV_XOR_NAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(orion_xor1_shared_resources),
- .resource = orion_xor1_shared_resources,
- .dev = {
- .dma_mask = &orion_xor_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &orion_xor1_pdata,
- },
-};
-
-void __init orion_xor1_init(unsigned long mapbase_low,
- unsigned long mapbase_high,
- unsigned long irq_0,
- unsigned long irq_1)
-{
- orion_xor1_shared_resources[0].start = mapbase_low;
- orion_xor1_shared_resources[0].end = mapbase_low + 0xff;
- orion_xor1_shared_resources[1].start = mapbase_high;
- orion_xor1_shared_resources[1].end = mapbase_high + 0xff;
-
- orion_xor1_shared_resources[2].start = irq_0;
- orion_xor1_shared_resources[2].end = irq_0;
- orion_xor1_shared_resources[3].start = irq_1;
- orion_xor1_shared_resources[3].end = irq_1;
-
- dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[0].cap_mask);
- dma_cap_set(DMA_XOR, orion_xor1_channels_data[0].cap_mask);
-
- dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[1].cap_mask);
- dma_cap_set(DMA_XOR, orion_xor1_channels_data[1].cap_mask);
-
- platform_device_register(&orion_xor1_shared);
-}
-
-/*****************************************************************************
- * EHCI
- ****************************************************************************/
-static struct orion_ehci_data orion_ehci_data;
-static u64 ehci_dmamask = DMA_BIT_MASK(32);
-
-
-/*****************************************************************************
- * EHCI0
- ****************************************************************************/
-static struct resource orion_ehci_resources[2];
-
-static struct platform_device orion_ehci = {
- .name = "orion-ehci",
- .id = 0,
- .dev = {
- .dma_mask = &ehci_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &orion_ehci_data,
- },
-};
-
-void __init orion_ehci_init(unsigned long mapbase,
- unsigned long irq,
- enum orion_ehci_phy_ver phy_version)
-{
- orion_ehci_data.phy_version = phy_version;
- fill_resources_irq(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
- irq);
-
- platform_device_register(&orion_ehci);
-}
-
-/*****************************************************************************
- * EHCI1
- ****************************************************************************/
-static struct resource orion_ehci_1_resources[2];
-
-static struct platform_device orion_ehci_1 = {
- .name = "orion-ehci",
- .id = 1,
- .dev = {
- .dma_mask = &ehci_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &orion_ehci_data,
- },
-};
-
-void __init orion_ehci_1_init(unsigned long mapbase,
- unsigned long irq)
-{
- fill_resources_irq(&orion_ehci_1, orion_ehci_1_resources,
- mapbase, SZ_4K - 1, irq);
-
- platform_device_register(&orion_ehci_1);
-}
-
-/*****************************************************************************
- * EHCI2
- ****************************************************************************/
-static struct resource orion_ehci_2_resources[2];
-
-static struct platform_device orion_ehci_2 = {
- .name = "orion-ehci",
- .id = 2,
- .dev = {
- .dma_mask = &ehci_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &orion_ehci_data,
- },
-};
-
-void __init orion_ehci_2_init(unsigned long mapbase,
- unsigned long irq)
-{
- fill_resources_irq(&orion_ehci_2, orion_ehci_2_resources,
- mapbase, SZ_4K - 1, irq);
-
- platform_device_register(&orion_ehci_2);
-}
-
-/*****************************************************************************
- * SATA
- ****************************************************************************/
-static struct resource orion_sata_resources[2] = {
- {
- .name = "sata base",
- }, {
- .name = "sata irq",
- },
-};
-
-static struct platform_device orion_sata = {
- .name = "sata_mv",
- .id = 0,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
- unsigned long mapbase,
- unsigned long irq)
-{
- orion_sata.dev.platform_data = sata_data;
- fill_resources_irq(&orion_sata, orion_sata_resources,
- mapbase, 0x5000 - 1, irq);
-
- platform_device_register(&orion_sata);
-}
-
-/*****************************************************************************
- * Cryptographic Engines and Security Accelerator (CESA)
- ****************************************************************************/
-static struct resource orion_crypto_resources[] = {
- {
- .name = "regs",
- }, {
- .name = "crypto interrupt",
- }, {
- .name = "sram",
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device orion_crypto = {
- .name = "mv_crypto",
- .id = -1,
-};
-
-void __init orion_crypto_init(unsigned long mapbase,
- unsigned long srambase,
- unsigned long sram_size,
- unsigned long irq)
-{
- fill_resources_irq(&orion_crypto, orion_crypto_resources,
- mapbase, 0xffff, irq);
- orion_crypto.num_resources = 3;
- orion_crypto_resources[2].start = srambase;
- orion_crypto_resources[2].end = srambase + sram_size - 1;
-
- platform_device_register(&orion_crypto);
-}
diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
deleted file mode 100644
index b76c06569fe5..000000000000
--- a/arch/arm/plat-orion/include/plat/addr-map.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * arch/arm/plat-orion/include/plat/addr-map.h
- *
- * Marvell Orion SoC address map handling.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_ADDR_MAP_H
-#define __PLAT_ADDR_MAP_H
-
-extern struct mbus_dram_target_info orion_mbus_dram_info;
-
-struct orion_addr_map_cfg {
- const int num_wins; /* Total number of windows */
- const int remappable_wins;
- void __iomem *bridge_virt_base;
- int hw_io_coherency;
-
- /* If NULL, the default cpu_win_can_remap will be used, using
- the value in remappable_wins */
- int (*cpu_win_can_remap) (const struct orion_addr_map_cfg *cfg,
- const int win);
- /* If NULL, the default win_cfg_base will be used, using the
- value in bridge_virt_base */
- void __iomem *(*win_cfg_base) (const struct orion_addr_map_cfg *cfg,
- const int win);
-};
-
-/*
- * Information needed to setup one address mapping.
- */
-struct orion_addr_map_info {
- const int win;
- const u32 base;
- const u32 size;
- const u8 target;
- const u8 attr;
- const int remap;
-};
-
-void __init orion_config_wins(struct orion_addr_map_cfg *cfg,
- const struct orion_addr_map_info *info);
-
-void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
- const int win, const u32 base,
- const u32 size, const u8 target,
- const u8 attr, const int remap);
-
-void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
- const void __iomem *ddr_window_cpu_base);
-#endif
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
deleted file mode 100644
index d2aad95d20cb..000000000000
--- a/arch/arm/plat-orion/include/plat/common.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * arch/arm/plat-orion/include/plat/common.h
- *
- * Marvell Orion SoC common setup code used by different mach-/common.c
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_COMMON_H
-#include <linux/mv643xx_eth.h>
-#include <linux/platform_data/usb-ehci-orion.h>
-
-struct mv_sata_platform_data;
-
-void __init orion_uart0_init(void __iomem *membase,
- resource_size_t mapbase,
- unsigned int irq,
- struct clk *clk);
-
-void __init orion_uart1_init(void __iomem *membase,
- resource_size_t mapbase,
- unsigned int irq,
- struct clk *clk);
-
-void __init orion_uart2_init(void __iomem *membase,
- resource_size_t mapbase,
- unsigned int irq,
- struct clk *clk);
-
-void __init orion_uart3_init(void __iomem *membase,
- resource_size_t mapbase,
- unsigned int irq,
- struct clk *clk);
-
-void __init orion_rtc_init(unsigned long mapbase,
- unsigned long irq);
-
-void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
- unsigned long mapbase,
- unsigned long irq,
- unsigned long irq_err,
- unsigned int tx_csum_limit);
-
-void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
- unsigned long mapbase,
- unsigned long irq,
- unsigned int tx_csum_limit);
-
-void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
- unsigned long mapbase,
- unsigned long irq);
-
-void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
- unsigned long mapbase,
- unsigned long irq);
-
-void __init orion_i2c_init(unsigned long mapbase,
- unsigned long irq,
- unsigned long freq_m);
-
-void __init orion_i2c_1_init(unsigned long mapbase,
- unsigned long irq,
- unsigned long freq_m);
-
-void __init orion_spi_init(unsigned long mapbase);
-
-void __init orion_spi_1_init(unsigned long mapbase);
-
-void __init orion_xor0_init(unsigned long mapbase_low,
- unsigned long mapbase_high,
- unsigned long irq_0,
- unsigned long irq_1);
-
-void __init orion_xor1_init(unsigned long mapbase_low,
- unsigned long mapbase_high,
- unsigned long irq_0,
- unsigned long irq_1);
-
-void __init orion_ehci_init(unsigned long mapbase,
- unsigned long irq,
- enum orion_ehci_phy_ver phy_version);
-
-void __init orion_ehci_1_init(unsigned long mapbase,
- unsigned long irq);
-
-void __init orion_ehci_2_init(unsigned long mapbase,
- unsigned long irq);
-
-void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
- unsigned long mapbase,
- unsigned long irq);
-
-void __init orion_crypto_init(unsigned long mapbase,
- unsigned long srambase,
- unsigned long sram_size,
- unsigned long irq);
-
-void __init orion_clkdev_add(const char *con_id, const char *dev_id,
- struct clk *clk);
-
-void __init orion_clkdev_init(struct clk *tclk);
-#endif
diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h
deleted file mode 100644
index 07527e417c62..000000000000
--- a/arch/arm/plat-orion/include/plat/time.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/plat-orion/include/plat/time.h
- *
- * Marvell Orion SoC time handling.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_TIME_H
-#define __PLAT_TIME_H
-
-void orion_time_set_base(void __iomem *timer_base);
-
-void orion_time_init(void __iomem *bridge_base, u32 bridge_timer1_clr_mask,
- unsigned int irq, unsigned int tclk);
-
-
-#endif
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index 8b8c06d2e9c4..e817f20409c4 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -13,7 +13,6 @@
#include <linux/mbus.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
-#include <plat/addr-map.h>
#include <linux/delay.h>
/*
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
deleted file mode 100644
index 509d4824dc1c..000000000000
--- a/arch/arm/plat-orion/time.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * arch/arm/plat-orion/time.c
- *
- * Marvell Orion SoC timer handling.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
- * Timer 0 is used as free-running clocksource, while timer 1 is
- * used as clock_event_device.
- */
-
-#include <linux/kernel.h>
-#include <linux/timer.h>
-#include <linux/clockchips.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/sched_clock.h>
-#include <plat/time.h>
-#include <asm/delay.h>
-
-/*
- * MBus bridge block registers.
- */
-#define BRIDGE_CAUSE_OFF 0x0110
-#define BRIDGE_MASK_OFF 0x0114
-#define BRIDGE_INT_TIMER0 0x0002
-#define BRIDGE_INT_TIMER1 0x0004
-
-
-/*
- * Timer block registers.
- */
-#define TIMER_CTRL_OFF 0x0000
-#define TIMER0_EN 0x0001
-#define TIMER0_RELOAD_EN 0x0002
-#define TIMER1_EN 0x0004
-#define TIMER1_RELOAD_EN 0x0008
-#define TIMER0_RELOAD_OFF 0x0010
-#define TIMER0_VAL_OFF 0x0014
-#define TIMER1_RELOAD_OFF 0x0018
-#define TIMER1_VAL_OFF 0x001c
-
-
-/*
- * SoC-specific data.
- */
-static void __iomem *bridge_base;
-static u32 bridge_timer1_clr_mask;
-static void __iomem *timer_base;
-
-
-/*
- * Number of timer ticks per jiffy.
- */
-static u32 ticks_per_jiffy;
-
-
-/*
- * Orion's sched_clock implementation. It has a resolution of
- * at least 7.5ns (133MHz TCLK).
- */
-
-static u64 notrace orion_read_sched_clock(void)
-{
- return ~readl(timer_base + TIMER0_VAL_OFF);
-}
-
-/*
- * Clockevent handling.
- */
-static int
-orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
-{
- unsigned long flags;
- u32 u;
-
- if (delta == 0)
- return -ETIME;
-
- local_irq_save(flags);
-
- /*
- * Clear and enable clockevent timer interrupt.
- */
- writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
-
- u = readl(bridge_base + BRIDGE_MASK_OFF);
- u |= BRIDGE_INT_TIMER1;
- writel(u, bridge_base + BRIDGE_MASK_OFF);
-
- /*
- * Setup new clockevent timer value.
- */
- writel(delta, timer_base + TIMER1_VAL_OFF);
-
- /*
- * Enable the timer.
- */
- u = readl(timer_base + TIMER_CTRL_OFF);
- u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
- writel(u, timer_base + TIMER_CTRL_OFF);
-
- local_irq_restore(flags);
-
- return 0;
-}
-
-static int orion_clkevt_shutdown(struct clock_event_device *evt)
-{
- unsigned long flags;
- u32 u;
-
- local_irq_save(flags);
-
- /* Disable timer */
- u = readl(timer_base + TIMER_CTRL_OFF);
- writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
-
- /* Disable timer interrupt */
- u = readl(bridge_base + BRIDGE_MASK_OFF);
- writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
-
- /* ACK pending timer interrupt */
- writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
-
- local_irq_restore(flags);
-
- return 0;
-}
-
-static int orion_clkevt_set_periodic(struct clock_event_device *evt)
-{
- unsigned long flags;
- u32 u;
-
- local_irq_save(flags);
-
- /* Setup timer to fire at 1/HZ intervals */
- writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
- writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
-
- /* Enable timer interrupt */
- u = readl(bridge_base + BRIDGE_MASK_OFF);
- writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
-
- /* Enable timer */
- u = readl(timer_base + TIMER_CTRL_OFF);
- writel(u | TIMER1_EN | TIMER1_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
-
- local_irq_restore(flags);
-
- return 0;
-}
-
-static struct clock_event_device orion_clkevt = {
- .name = "orion_tick",
- .features = CLOCK_EVT_FEAT_ONESHOT |
- CLOCK_EVT_FEAT_PERIODIC,
- .rating = 300,
- .set_next_event = orion_clkevt_next_event,
- .set_state_shutdown = orion_clkevt_shutdown,
- .set_state_periodic = orion_clkevt_set_periodic,
- .set_state_oneshot = orion_clkevt_shutdown,
- .tick_resume = orion_clkevt_shutdown,
-};
-
-static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
-{
- /*
- * ACK timer interrupt and call event handler.
- */
- writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
- orion_clkevt.event_handler(&orion_clkevt);
-
- return IRQ_HANDLED;
-}
-
-void __init
-orion_time_set_base(void __iomem *_timer_base)
-{
- timer_base = _timer_base;
-}
-
-static unsigned long orion_delay_timer_read(void)
-{
- return ~readl(timer_base + TIMER0_VAL_OFF);
-}
-
-static struct delay_timer orion_delay_timer = {
- .read_current_timer = orion_delay_timer_read,
-};
-
-void __init
-orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
- unsigned int irq, unsigned int tclk)
-{
- u32 u;
-
- /*
- * Set SoC-specific data.
- */
- bridge_base = _bridge_base;
- bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
-
- ticks_per_jiffy = (tclk + HZ/2) / HZ;
-
- orion_delay_timer.freq = tclk;
- register_current_timer_delay(&orion_delay_timer);
-
- /*
- * Set scale and timer for sched_clock.
- */
- sched_clock_register(orion_read_sched_clock, 32, tclk);
-
- /*
- * Setup free-running clocksource timer (interrupts
- * disabled).
- */
- writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
- writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
- u = readl(bridge_base + BRIDGE_MASK_OFF);
- writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
- u = readl(timer_base + TIMER_CTRL_OFF);
- writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
- clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource",
- tclk, 300, 32, clocksource_mmio_readl_down);
-
- /*
- * Setup clockevent timer (interrupt-driven).
- */
- if (request_irq(irq, orion_timer_interrupt, IRQF_TIMER, "orion_tick",
- NULL))
- pr_err("Failed to request irq %u (orion_tick)\n", irq);
- orion_clkevt.cpumask = cpumask_of(0);
- clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe);
-}
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 28ca856ecc75..434cce3efd96 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -471,8 +471,7 @@ config SATA_HIGHBANK
config SATA_MV
tristate "Marvell SATA support"
- depends on PCI || ARCH_DOVE || ARCH_MV78XX0 || \
- ARCH_MVEBU || ARCH_ORION5X || COMPILE_TEST
+ depends on PCI || ARCH_MVEBU || ARCH_ORION5X || COMPILE_TEST
select GENERIC_PHY
select SATA_HOST
help
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 4f060d3e5636..d06903635335 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -330,7 +330,7 @@ config MMC_SDHCI_ESDHC_IMX
config MMC_SDHCI_DOVE
tristate "SDHCI support on Marvell's Dove SoC"
- depends on ARCH_DOVE || MACH_DOVE || COMPILE_TEST
+ depends on MACH_DOVE || COMPILE_TEST
depends on MMC_SDHCI_PLTFM
select MMC_SDHCI_IO_ACCESSORS
help
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index d246bbe37948..7e550c474b7a 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -197,7 +197,7 @@ config PCI_LOONGSON
config PCI_MVEBU
tristate "Marvell EBU PCIe controller"
- depends on ARCH_MVEBU || ARCH_DOVE || COMPILE_TEST
+ depends on ARCH_MVEBU || COMPILE_TEST
depends on MVEBU_MBUS
depends on ARM
depends on OF
diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig
index bccd72dccb77..c29d2d28ae55 100644
--- a/drivers/phy/marvell/Kconfig
+++ b/drivers/phy/marvell/Kconfig
@@ -77,7 +77,7 @@ config PHY_MVEBU_CP110_UTMI
config PHY_MVEBU_SATA
def_bool y
- depends on ARCH_DOVE || MACH_DOVE || MACH_KIRKWOOD
+ depends on MACH_DOVE || MACH_KIRKWOOD
depends on OF
select GENERIC_PHY
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 55ffee3d75ce..5cb6cdfe6015 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1703,7 +1703,7 @@ config RTC_DRV_STARFIRE
config RTC_DRV_MV
tristate "Marvell SoC RTC"
- depends on ARCH_DOVE || ARCH_MVEBU || COMPILE_TEST
+ depends on ARCH_MVEBU || COMPILE_TEST
help
If you say yes here you will get support for the in-chip RTC
that can be found in some of Marvell's SoC devices, such as
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index c9e689080ceb..6411b96d584c 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -9,7 +9,6 @@ obj-$(CONFIG_ARCH_AT91) += atmel/
obj-y += bcm/
obj-$(CONFIG_ARCH_CANAAN) += canaan/
obj-$(CONFIG_EP93XX_SOC) += cirrus/
-obj-$(CONFIG_ARCH_DOVE) += dove/
obj-$(CONFIG_MACH_DOVE) += dove/
obj-y += fsl/
obj-y += fujitsu/
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 810eeccedfba..8cef9b658191 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -391,7 +391,7 @@ config KIRKWOOD_THERMAL
config DOVE_THERMAL
tristate "Temperature sensor on Marvell Dove SoCs"
- depends on ARCH_DOVE || MACH_DOVE || COMPILE_TEST
+ depends on MACH_DOVE || COMPILE_TEST
depends on HAS_IOMEM
depends on OF
help
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 0ab0dcc6d27d..d83bfb189705 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -690,7 +690,7 @@ config K3_RTI_WATCHDOG
config ORION_WATCHDOG
tristate "Orion watchdog"
- depends on ARCH_ORION5X || ARCH_DOVE || MACH_DOVE || ARCH_MVEBU || COMPILE_TEST
+ depends on ARCH_ORION5X || MACH_DOVE || ARCH_MVEBU || COMPILE_TEST
depends on ARM
select WATCHDOG_CORE
help
diff --git a/sound/soc/kirkwood/Kconfig b/sound/soc/kirkwood/Kconfig
index 924072e402c8..d59c5bb0b391 100644
--- a/sound/soc/kirkwood/Kconfig
+++ b/sound/soc/kirkwood/Kconfig
@@ -3,7 +3,7 @@ menu "Kirkwood"
config SND_KIRKWOOD_SOC
tristate "SoC Audio for the Marvell Kirkwood and Dove chips"
- depends on ARCH_DOVE || ARCH_MVEBU || COMPILE_TEST
+ depends on ARCH_MVEBU || COMPILE_TEST
help
Say Y or M if you want to add support for codecs attached to
the Kirkwood I2S interface. You will also need to select the
--
2.53.0
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 05/13] ARM: orion/dove/mv78xx0: remove all board files
2026-09-08 15:27 ` [PATCH 05/13] ARM: orion/dove/mv78xx0: remove all " Arnd Bergmann
@ 2026-09-08 15:34 ` Mark Brown
2026-09-08 16:12 ` Ulf Hansson
` (4 subsequent siblings)
5 siblings, 0 replies; 70+ messages in thread
From: Mark Brown @ 2026-09-08 15:34 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Arnd Bergmann, Rob Herring,
Conor Dooley, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Alexander Clouter,
Jeremy J. Peper, Damien Le Moal, Niklas Cassel, Ulf Hansson,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
Vinod Koul, Rafael J. Wysocki, Daniel Lezcano, Guenter Roeck,
Bartosz Golaszewski, Thomas Weissschuh, linux-ide, linux-mmc,
linux-pci, linux-phy, linux-rtc, linux-pm, linux-watchdog,
linux-sound, linux-gpio
[-- Attachment #1: Type: text/plain, Size: 388 bytes --]
On Tue, Sep 08, 2026 at 05:27:55PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The 'orion' platform is the predecessor to what linux now calls the
> 'mvebu' line of Marvell SoCs, and originally covered orion5x,
> mv78xx0, kirkwood, dove and a few others that do not have any
> upstream support at the moment.
Acked-by: Mark Brown <broonie@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 05/13] ARM: orion/dove/mv78xx0: remove all board files
2026-09-08 15:27 ` [PATCH 05/13] ARM: orion/dove/mv78xx0: remove all " Arnd Bergmann
2026-09-08 15:34 ` Mark Brown
@ 2026-09-08 16:12 ` Ulf Hansson
2026-09-08 16:18 ` Andrew Lunn
` (3 subsequent siblings)
5 siblings, 0 replies; 70+ messages in thread
From: Ulf Hansson @ 2026-09-08 16:12 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Arnd Bergmann, Rob Herring,
Conor Dooley, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Alexander Clouter,
Jeremy J. Peper, Damien Le Moal, Niklas Cassel, Ulf Hansson,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
Vinod Koul, Rafael J. Wysocki, Daniel Lezcano, Guenter Roeck,
Mark Brown, Bartosz Golaszewski, Thomas Weissschuh, linux-ide,
linux-mmc, linux-pci, linux-phy, linux-rtc, linux-pm,
linux-watchdog, linux-sound, linux-gpio
On Tue, Sep 8, 2026 at 5:29 PM Arnd Bergmann <arnd@kernel.org> wrote:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> The 'orion' platform is the predecessor to what linux now calls the
> 'mvebu' line of Marvell SoCs, and originally covered orion5x,
> mv78xx0, kirkwood, dove and a few others that do not have any
> upstream support at the moment.
>
> Only a few board files remain here, these are the ones left
> in 2022 board file purge because they had some level of support
> in Debian or OpenWRT, mostly for commercial NAS or router boxes.
> This distro support is now gone, and nobody has converted the
> board files to devicetree, though the orion5x and dove platforms
> also come with devicetree support for some other machines.
>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Cc: Gregory Clement <gregory.clement@bootlin.com>
> Cc: Alexander Clouter <alex@digriz.org.uk>
> Cc: Jeremy J. Peper <jeremy@jeremypeper.com>
> Cc: Damien Le Moal <dlemoal@kernel.org>
> Cc: Niklas Cassel <cassel@kernel.org>
> Cc: Ulf Hansson <ulfh@kernel.org>
> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
> Cc: Manivannan Sadhasivam <mani@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Cc: "Rafael J. Wysocki" <rafael@kernel.org>
> Cc: Daniel Lezcano <daniel.lezcano@kernel.org>
> Cc: Guenter Roeck <linux@roeck-us.net>
> Cc: Mark Brown <broonie@kernel.org>
> Cc: Linus Walleij <linusw@kernel.org>
> Cc: Bartosz Golaszewski <brgl@kernel.org>
> Cc: Thomas Weissschuh <thomas.weissschuh@linutronix.de>
> Cc: linux-ide@vger.kernel.org
> Cc: linux-mmc@vger.kernel.org
> Cc: linux-pci@vger.kernel.org
> Cc: linux-phy@lists.infradead.org
> Cc: linux-rtc@vger.kernel.org
> Cc: linux-pm@vger.kernel.org
> Cc: linux-watchdog@vger.kernel.org
> Cc: linux-sound@vger.kernel.org
> Cc: linux-gpio@vger.kernel.org
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Ulf Hansson <ulfh@kernel.org> # For MMC
Kind regards
Uffe
> ---
> MAINTAINERS | 2 -
> arch/arm/Kconfig | 2 -
> arch/arm/Kconfig.debug | 2 +-
> arch/arm/Makefile | 2 -
> arch/arm/configs/dove_defconfig | 134 ---
> arch/arm/configs/mv78xx0_defconfig | 120 ---
> arch/arm/mach-dove/Kconfig | 32 -
> arch/arm/mach-dove/Makefile | 7 -
> arch/arm/mach-dove/bridge-regs.h | 50 --
> arch/arm/mach-dove/cm-a510.c | 94 --
> arch/arm/mach-dove/common.c | 449 ----------
> arch/arm/mach-dove/common.h | 46 -
> arch/arm/mach-dove/dove.h | 185 ----
> arch/arm/mach-dove/irq.c | 81 --
> arch/arm/mach-dove/irqs.h | 89 --
> arch/arm/mach-dove/mpp.c | 159 ----
> arch/arm/mach-dove/mpp.h | 197 -----
> arch/arm/mach-dove/pcie.c | 226 -----
> arch/arm/mach-dove/pm.h | 58 --
> arch/arm/mach-mv78xx0/Kconfig | 27 -
> arch/arm/mach-mv78xx0/Makefile | 5 -
> arch/arm/mach-mv78xx0/bridge-regs.h | 31 -
> arch/arm/mach-mv78xx0/buffalo-wxl-setup.c | 183 ----
> arch/arm/mach-mv78xx0/common.c | 444 ----------
> arch/arm/mach-mv78xx0/common.h | 54 --
> arch/arm/mach-mv78xx0/irq.c | 69 --
> arch/arm/mach-mv78xx0/irqs.h | 87 --
> arch/arm/mach-mv78xx0/mpp.c | 34 -
> arch/arm/mach-mv78xx0/mpp.h | 337 -------
> arch/arm/mach-mv78xx0/mv78xx0.h | 134 ---
> arch/arm/mach-mv78xx0/pcie.c | 280 ------
> arch/arm/mach-orion5x/Kconfig | 95 --
> arch/arm/mach-orion5x/Makefile | 9 -
> arch/arm/mach-orion5x/board-dt.c | 3 +-
> arch/arm/mach-orion5x/common.c | 238 +----
> arch/arm/mach-orion5x/common.h | 15 -
> arch/arm/mach-orion5x/dns323-setup.c | 757 ----------------
> arch/arm/mach-orion5x/kurobox_pro-setup.c | 407 ---------
> arch/arm/mach-orion5x/mv2120-setup.c | 256 ------
> arch/arm/mach-orion5x/net2big-setup.c | 444 ----------
> arch/arm/mach-orion5x/pci.c | 1 -
> .../arm/mach-orion5x/terastation_pro2-setup.c | 366 --------
> arch/arm/mach-orion5x/ts209-setup.c | 331 -------
> arch/arm/mach-orion5x/ts409-setup.c | 329 -------
> arch/arm/mach-orion5x/ts78xx-fpga.h | 42 -
> arch/arm/mach-orion5x/ts78xx-setup.c | 574 ------------
> arch/arm/mach-orion5x/tsx09-common.c | 129 ---
> arch/arm/mach-orion5x/tsx09-common.h | 21 -
> arch/arm/mm/Kconfig | 2 +-
> arch/arm/plat-orion/Makefile | 2 +-
> arch/arm/plat-orion/common.c | 826 ------------------
> arch/arm/plat-orion/include/plat/addr-map.h | 54 --
> arch/arm/plat-orion/include/plat/common.h | 104 ---
> arch/arm/plat-orion/include/plat/time.h | 20 -
> arch/arm/plat-orion/pcie.c | 1 -
> arch/arm/plat-orion/time.c | 238 -----
> drivers/ata/Kconfig | 3 +-
> drivers/mmc/host/Kconfig | 2 +-
> drivers/pci/controller/Kconfig | 2 +-
> drivers/phy/marvell/Kconfig | 2 +-
> drivers/rtc/Kconfig | 2 +-
> drivers/soc/Makefile | 1 -
> drivers/thermal/Kconfig | 2 +-
> drivers/watchdog/Kconfig | 2 +-
> sound/soc/kirkwood/Kconfig | 2 +-
> 65 files changed, 14 insertions(+), 8888 deletions(-)
> delete mode 100644 arch/arm/configs/dove_defconfig
> delete mode 100644 arch/arm/configs/mv78xx0_defconfig
> delete mode 100644 arch/arm/mach-dove/Kconfig
> delete mode 100644 arch/arm/mach-dove/Makefile
> delete mode 100644 arch/arm/mach-dove/bridge-regs.h
> delete mode 100644 arch/arm/mach-dove/cm-a510.c
> delete mode 100644 arch/arm/mach-dove/common.c
> delete mode 100644 arch/arm/mach-dove/common.h
> delete mode 100644 arch/arm/mach-dove/dove.h
> delete mode 100644 arch/arm/mach-dove/irq.c
> delete mode 100644 arch/arm/mach-dove/irqs.h
> delete mode 100644 arch/arm/mach-dove/mpp.c
> delete mode 100644 arch/arm/mach-dove/mpp.h
> delete mode 100644 arch/arm/mach-dove/pcie.c
> delete mode 100644 arch/arm/mach-dove/pm.h
> delete mode 100644 arch/arm/mach-mv78xx0/Kconfig
> delete mode 100644 arch/arm/mach-mv78xx0/Makefile
> delete mode 100644 arch/arm/mach-mv78xx0/bridge-regs.h
> delete mode 100644 arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
> delete mode 100644 arch/arm/mach-mv78xx0/common.c
> delete mode 100644 arch/arm/mach-mv78xx0/common.h
> delete mode 100644 arch/arm/mach-mv78xx0/irq.c
> delete mode 100644 arch/arm/mach-mv78xx0/irqs.h
> delete mode 100644 arch/arm/mach-mv78xx0/mpp.c
> delete mode 100644 arch/arm/mach-mv78xx0/mpp.h
> delete mode 100644 arch/arm/mach-mv78xx0/mv78xx0.h
> delete mode 100644 arch/arm/mach-mv78xx0/pcie.c
> delete mode 100644 arch/arm/mach-orion5x/dns323-setup.c
> delete mode 100644 arch/arm/mach-orion5x/kurobox_pro-setup.c
> delete mode 100644 arch/arm/mach-orion5x/mv2120-setup.c
> delete mode 100644 arch/arm/mach-orion5x/net2big-setup.c
> delete mode 100644 arch/arm/mach-orion5x/terastation_pro2-setup.c
> delete mode 100644 arch/arm/mach-orion5x/ts209-setup.c
> delete mode 100644 arch/arm/mach-orion5x/ts409-setup.c
> delete mode 100644 arch/arm/mach-orion5x/ts78xx-fpga.h
> delete mode 100644 arch/arm/mach-orion5x/ts78xx-setup.c
> delete mode 100644 arch/arm/mach-orion5x/tsx09-common.c
> delete mode 100644 arch/arm/mach-orion5x/tsx09-common.h
> delete mode 100644 arch/arm/plat-orion/common.c
> delete mode 100644 arch/arm/plat-orion/include/plat/addr-map.h
> delete mode 100644 arch/arm/plat-orion/include/plat/common.h
> delete mode 100644 arch/arm/plat-orion/include/plat/time.h
> delete mode 100644 arch/arm/plat-orion/time.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 6e8fe7640064..028db7ad15ad 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3080,8 +3080,6 @@ F: Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.yaml
> F: Documentation/devicetree/bindings/soc/dove/
> F: arch/arm/boot/dts/marvell/dove*
> F: arch/arm/boot/dts/marvell/orion5x*
> -F: arch/arm/mach-dove/
> -F: arch/arm/mach-mv78xx0/
> F: arch/arm/mach-orion5x/
> F: arch/arm/plat-orion/
> F: drivers/bus/mvebu-mbus.c
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 5770deca136d..da29afce309f 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -393,8 +393,6 @@ source "arch/arm/mach-mmp/Kconfig"
>
> source "arch/arm/mach-mstar/Kconfig"
>
> -source "arch/arm/mach-mv78xx0/Kconfig"
> -
> source "arch/arm/mach-mvebu/Kconfig"
>
> source "arch/arm/mach-mxs/Kconfig"
> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index 56c090840c5a..e2fc89055463 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -583,7 +583,7 @@ choice
>
> config DEBUG_MVEBU_UART0_ALTERNATE
> bool "Kernel low-level debugging messages via MVEBU UART0 (new bootloaders)"
> - depends on ARCH_MVEBU || ARCH_DOVE || ARCH_MV78XX0 || ARCH_ORION5X
> + depends on ARCH_MVEBU || ARCH_ORION5X
> select DEBUG_UART_8250
> help
> Say Y here if you want kernel low-level debugging support
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index f5bc9ad7f6f5..5421a3ec3825 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -179,7 +179,6 @@ machine-$(CONFIG_ARCH_BERLIN) += berlin
> machine-$(CONFIG_ARCH_CLPS711X) += clps711x
> machine-$(CONFIG_ARCH_DAVINCI) += davinci
> machine-$(CONFIG_ARCH_DIGICOLOR) += digicolor
> -machine-$(CONFIG_ARCH_DOVE) += dove
> machine-$(CONFIG_ARCH_EXYNOS) += exynos
> machine-$(CONFIG_ARCH_GEMINI) += gemini
> machine-$(CONFIG_ARCH_HIGHBANK) += highbank
> @@ -190,7 +189,6 @@ machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx
> machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
> machine-$(CONFIG_ARCH_MESON) += meson
> machine-$(CONFIG_ARCH_MMP) += mmp
> -machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
> machine-$(CONFIG_ARCH_MVEBU) += mvebu
> machine-$(CONFIG_ARCH_MXC) += imx
> machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
> diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
> deleted file mode 100644
> index 917a864fec74..000000000000
> --- a/arch/arm/configs/dove_defconfig
> +++ /dev/null
> @@ -1,134 +0,0 @@
> -CONFIG_SYSVIPC=y
> -CONFIG_NO_HZ_IDLE=y
> -CONFIG_HIGH_RES_TIMERS=y
> -CONFIG_LOG_BUF_SHIFT=14
> -CONFIG_EXPERT=y
> -# CONFIG_ARCH_MULTI_V6 is not set
> -CONFIG_ARCH_MULTI_V7=y
> -CONFIG_ARCH_DOVE=y
> -CONFIG_MACH_CM_A510=y
> -CONFIG_HIGHMEM=y
> -CONFIG_ATAGS=y
> -CONFIG_ARM_APPENDED_DTB=y
> -CONFIG_ARM_ATAG_DTB_COMPAT=y
> -CONFIG_VFP=y
> -CONFIG_MODULES=y
> -CONFIG_MODULE_UNLOAD=y
> -CONFIG_PARTITION_ADVANCED=y
> -CONFIG_NET=y
> -CONFIG_PACKET=y
> -CONFIG_UNIX=y
> -CONFIG_INET=y
> -CONFIG_IP_MULTICAST=y
> -CONFIG_IP_PNP=y
> -CONFIG_IP_PNP_DHCP=y
> -CONFIG_IP_PNP_BOOTP=y
> -# CONFIG_IPV6 is not set
> -CONFIG_PCI=y
> -CONFIG_PCI_MSI=y
> -CONFIG_PCI_MVEBU=y
> -CONFIG_DEVTMPFS=y
> -CONFIG_DEVTMPFS_MOUNT=y
> -CONFIG_MTD=y
> -CONFIG_MTD_CMDLINE_PARTS=y
> -CONFIG_MTD_BLOCK=y
> -CONFIG_MTD_CFI=y
> -CONFIG_MTD_JEDECPROBE=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_GEOMETRY=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -CONFIG_MTD_CFI_STAA=y
> -CONFIG_MTD_PHYSMAP=y
> -CONFIG_MTD_M25P80=y
> -CONFIG_MTD_SPI_NOR=y
> -CONFIG_BLK_DEV_LOOP=y
> -CONFIG_BLK_DEV_RAM=y
> -CONFIG_BLK_DEV_RAM_COUNT=1
> -# CONFIG_SCSI_PROC_FS is not set
> -CONFIG_BLK_DEV_SD=y
> -# CONFIG_BLK_DEV_BSG is not set
> -# CONFIG_SCSI_LOWLEVEL is not set
> -CONFIG_ATA=y
> -CONFIG_SATA_MV=y
> -CONFIG_NETDEVICES=y
> -CONFIG_MV643XX_ETH=y
> -# CONFIG_INPUT_MOUSEDEV is not set
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_KEYBOARD_ATKBD is not set
> -# CONFIG_MOUSE_PS2 is not set
> -# CONFIG_SERIO is not set
> -CONFIG_LEGACY_PTY_COUNT=16
> -CONFIG_SERIAL_8250=y
> -CONFIG_SERIAL_8250_CONSOLE=y
> -CONFIG_SERIAL_8250_RUNTIME_UARTS=2
> -CONFIG_SERIAL_OF_PLATFORM=y
> -# CONFIG_HW_RANDOM is not set
> -CONFIG_I2C=y
> -CONFIG_I2C_CHARDEV=y
> -CONFIG_I2C_MV64XXX=y
> -CONFIG_SPI=y
> -CONFIG_SPI_ORION=y
> -# CONFIG_HWMON is not set
> -CONFIG_THERMAL=y
> -CONFIG_DOVE_THERMAL=y
> -CONFIG_WATCHDOG=y
> -CONFIG_ORION_WATCHDOG=y
> -CONFIG_USB=y
> -CONFIG_USB_XHCI_HCD=y
> -CONFIG_USB_EHCI_HCD=y
> -CONFIG_USB_EHCI_ROOT_HUB_TT=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_MMC=y
> -CONFIG_MMC_SDHCI=y
> -CONFIG_MMC_SDHCI_PLTFM=y
> -CONFIG_MMC_SDHCI_DOVE=y
> -CONFIG_NEW_LEDS=y
> -CONFIG_LEDS_CLASS=y
> -CONFIG_LEDS_GPIO=y
> -CONFIG_LEDS_TRIGGERS=y
> -CONFIG_LEDS_TRIGGER_TIMER=y
> -CONFIG_LEDS_TRIGGER_HEARTBEAT=y
> -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
> -CONFIG_RTC_CLASS=y
> -CONFIG_RTC_DRV_MV=y
> -CONFIG_DMADEVICES=y
> -CONFIG_MV_XOR=y
> -CONFIG_EXT2_FS=y
> -CONFIG_EXT4_FS=y
> -# CONFIG_EXT4_FS_XATTR is not set
> -CONFIG_ISO9660_FS=y
> -CONFIG_JOLIET=y
> -CONFIG_UDF_FS=m
> -CONFIG_MSDOS_FS=y
> -CONFIG_VFAT_FS=y
> -CONFIG_TMPFS=y
> -CONFIG_JFFS2_FS=y
> -CONFIG_NFS_FS=y
> -CONFIG_ROOT_NFS=y
> -CONFIG_NLS_CODEPAGE_437=y
> -CONFIG_NLS_CODEPAGE_850=y
> -CONFIG_NLS_ISO8859_1=y
> -CONFIG_NLS_ISO8859_2=y
> -CONFIG_NLS_UTF8=y
> -CONFIG_TIMER_STATS=y
> -CONFIG_CRYPTO_NULL=y
> -CONFIG_CRYPTO_BLOWFISH=y
> -CONFIG_CRYPTO_TEA=y
> -CONFIG_CRYPTO_TWOFISH=y
> -CONFIG_CRYPTO_ECB=m
> -CONFIG_CRYPTO_HMAC=y
> -CONFIG_CRYPTO_MD4=y
> -CONFIG_CRYPTO_SHA1=y
> -CONFIG_CRYPTO_SHA256=y
> -CONFIG_CRYPTO_SHA512=y
> -CONFIG_CRYPTO_DEFLATE=y
> -CONFIG_CRYPTO_LZO=y
> -CONFIG_CRYPTO_DEV_MARVELL_CESA=y
> -CONFIG_PRINTK_TIME=y
> -# CONFIG_DEBUG_BUGVERBOSE is not set
> -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
> -CONFIG_MAGIC_SYSRQ=y
> -CONFIG_DEBUG_FS=y
> -# CONFIG_SCHED_DEBUG is not set
> -CONFIG_DEBUG_USER=y
> diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig
> deleted file mode 100644
> index e3cc8de7c1c2..000000000000
> --- a/arch/arm/configs/mv78xx0_defconfig
> +++ /dev/null
> @@ -1,120 +0,0 @@
> -CONFIG_SYSVIPC=y
> -CONFIG_NO_HZ_IDLE=y
> -CONFIG_HIGH_RES_TIMERS=y
> -CONFIG_PREEMPT=y
> -CONFIG_LOG_BUF_SHIFT=14
> -CONFIG_EXPERT=y
> -CONFIG_KALLSYMS_ALL=y
> -CONFIG_PROFILING=y
> -CONFIG_ARCH_MULTI_V5=y
> -# CONFIG_ARCH_MULTI_V6 is not set
> -# CONFIG_ARCH_MULTI_V7 is not set
> -CONFIG_ARCH_MV78XX0=y
> -CONFIG_MACH_TERASTATION_WXL=y
> -CONFIG_HIGHMEM=y
> -CONFIG_ATAGS=y
> -CONFIG_VFP=y
> -CONFIG_KPROBES=y
> -CONFIG_MODULES=y
> -CONFIG_MODULE_UNLOAD=y
> -CONFIG_PARTITION_ADVANCED=y
> -CONFIG_BSD_DISKLABEL=y
> -CONFIG_NET=y
> -CONFIG_PACKET=y
> -CONFIG_UNIX=y
> -CONFIG_INET=y
> -CONFIG_IP_MULTICAST=y
> -CONFIG_IP_PNP=y
> -CONFIG_IP_PNP_DHCP=y
> -CONFIG_IP_PNP_BOOTP=y
> -# CONFIG_IPV6 is not set
> -CONFIG_NET_PKTGEN=m
> -CONFIG_MTD=y
> -CONFIG_MTD_CMDLINE_PARTS=y
> -CONFIG_MTD_BLOCK=y
> -CONFIG_MTD_CFI=y
> -CONFIG_MTD_JEDECPROBE=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_GEOMETRY=y
> -CONFIG_MTD_CFI_INTELEXT=y
> -CONFIG_MTD_CFI_AMDSTD=y
> -CONFIG_MTD_PHYSMAP=y
> -CONFIG_MTD_RAW_NAND=y
> -CONFIG_MTD_NAND_ORION=y
> -CONFIG_BLK_DEV_LOOP=y
> -# CONFIG_SCSI_PROC_FS is not set
> -CONFIG_BLK_DEV_SD=y
> -CONFIG_BLK_DEV_SR=m
> -CONFIG_CHR_DEV_SG=m
> -# CONFIG_BLK_DEV_BSG is not set
> -CONFIG_ATA=y
> -CONFIG_SATA_MV=y
> -CONFIG_NETDEVICES=y
> -CONFIG_MII=y
> -CONFIG_NET_PCI=y
> -CONFIG_MV643XX_ETH=y
> -# CONFIG_INPUT_MOUSEDEV is not set
> -CONFIG_MARVELL_PHY=y
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_INPUT_KEYBOARD is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_SERIO is not set
> -# CONFIG_VT is not set
> -CONFIG_LEGACY_PTY_COUNT=16
> -CONFIG_SERIAL_8250=y
> -CONFIG_SERIAL_8250_CONSOLE=y
> -# CONFIG_SERIAL_8250_PCI is not set
> -CONFIG_SERIAL_8250_RUNTIME_UARTS=2
> -# CONFIG_HW_RANDOM is not set
> -CONFIG_I2C=y
> -CONFIG_I2C_CHARDEV=y
> -CONFIG_I2C_MV64XXX=y
> -CONFIG_USB=y
> -CONFIG_USB_EHCI_HCD=y
> -CONFIG_USB_EHCI_ROOT_HUB_TT=y
> -CONFIG_USB_EHCI_TT_NEWSCHED=y
> -CONFIG_USB_PRINTER=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_USB_STORAGE_DATAFAB=y
> -CONFIG_USB_STORAGE_FREECOM=y
> -CONFIG_USB_STORAGE_SDDR09=y
> -CONFIG_USB_STORAGE_SDDR55=y
> -CONFIG_USB_STORAGE_JUMPSHOT=y
> -CONFIG_NEW_LEDS=y
> -CONFIG_LEDS_CLASS=y
> -CONFIG_LEDS_TRIGGERS=y
> -CONFIG_LEDS_TRIGGER_TIMER=y
> -CONFIG_LEDS_TRIGGER_HEARTBEAT=y
> -CONFIG_RTC_CLASS=y
> -CONFIG_RTC_DRV_DS1307=y
> -CONFIG_RTC_DRV_RS5C372=y
> -CONFIG_RTC_DRV_M41T80=y
> -CONFIG_EXT2_FS=y
> -CONFIG_EXT4_FS=y
> -# CONFIG_EXT4_FS_XATTR is not set
> -CONFIG_ISO9660_FS=m
> -CONFIG_JOLIET=y
> -CONFIG_UDF_FS=m
> -CONFIG_MSDOS_FS=y
> -CONFIG_VFAT_FS=y
> -CONFIG_TMPFS=y
> -CONFIG_JFFS2_FS=y
> -CONFIG_CRAMFS=y
> -CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
> -CONFIG_ROOT_NFS=y
> -CONFIG_NLS_CODEPAGE_437=y
> -CONFIG_NLS_CODEPAGE_850=y
> -CONFIG_NLS_ISO8859_1=y
> -CONFIG_NLS_ISO8859_2=y
> -CONFIG_CRYPTO_CBC=m
> -CONFIG_CRYPTO_ECB=m
> -# CONFIG_DEBUG_BUGVERBOSE is not set
> -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
> -CONFIG_MAGIC_SYSRQ=y
> -CONFIG_DEBUG_FS=y
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_SLUB_DEBUG is not set
> -CONFIG_SCHEDSTATS=y
> -CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_LL=y
> diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
> deleted file mode 100644
> index f547120e223e..000000000000
> --- a/arch/arm/mach-dove/Kconfig
> +++ /dev/null
> @@ -1,32 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0
> -menuconfig ARCH_DOVE
> - bool "Marvell Dove (DEPRECATED)" if ARCH_MULTI_V7
> - depends on ATAGS
> - select CPU_PJ4
> - select GPIOLIB
> - select MVEBU_MBUS
> - select PINCTRL
> - select PINCTRL_DOVE
> - select PLAT_ORION_LEGACY
> - select PM_GENERIC_DOMAINS if PM
> - select PCI_QUIRKS if PCI
> - help
> - Support for the Marvell Dove SoC 88AP510 using board files.
> -
> - Support for this machine will be removed in early 2027, unless
> - there is a strong reason to keep it. Users should migrate to
> - the devicetree-enabled version (CONFIG_MACH_DOVE) instead.
> -
> -if ARCH_DOVE
> -
> -config DOVE_LEGACY
> - bool
> -
> -config MACH_CM_A510
> - bool "CompuLab CM-A510 Board"
> - select DOVE_LEGACY
> - help
> - Say 'Y' here if you want your kernel to support the
> - CompuLab CM-A510 Board.
> -
> -endif
> diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
> deleted file mode 100644
> index 0d31390be069..000000000000
> --- a/arch/arm/mach-dove/Makefile
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0
> -ccflags-y := -I$(srctree)/arch/arm/plat-orion/include
> -
> -obj-y += common.o
> -obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o
> -obj-$(CONFIG_PCI) += pcie.o
> -obj-$(CONFIG_MACH_CM_A510) += cm-a510.o
> diff --git a/arch/arm/mach-dove/bridge-regs.h b/arch/arm/mach-dove/bridge-regs.h
> deleted file mode 100644
> index 6fbc152d0950..000000000000
> --- a/arch/arm/mach-dove/bridge-regs.h
> +++ /dev/null
> @@ -1,50 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/* Mbus-L to Mbus Bridge Registers */
> -
> -#ifndef __ASM_ARCH_BRIDGE_REGS_H
> -#define __ASM_ARCH_BRIDGE_REGS_H
> -
> -#include "dove.h"
> -
> -#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000)
> -
> -#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
> -#define CPU_CTRL_PCIE0_LINK 0x00000001
> -#define CPU_RESET 0x00000002
> -#define CPU_CTRL_PCIE1_LINK 0x00000008
> -
> -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
> -#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
> -#define SOFT_RESET_OUT_EN 0x00000004
> -
> -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
> -#define SOFT_RESET 0x00000001
> -
> -#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
> -#define BRIDGE_INT_TIMER1_CLR (~0x0004)
> -
> -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
> -#define IRQ_CAUSE_LOW_OFF 0x0000
> -#define IRQ_MASK_LOW_OFF 0x0004
> -#define FIQ_MASK_LOW_OFF 0x0008
> -#define ENDPOINT_MASK_LOW_OFF 0x000c
> -#define IRQ_CAUSE_HIGH_OFF 0x0010
> -#define IRQ_MASK_HIGH_OFF 0x0014
> -#define FIQ_MASK_HIGH_OFF 0x0018
> -#define ENDPOINT_MASK_HIGH_OFF 0x001c
> -#define PCIE_INTERRUPT_MASK_OFF 0x0020
> -
> -#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)
> -#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)
> -#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)
> -#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)
> -#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)
> -#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
> -#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
> -
> -#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c)
> -
> -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
> -#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
> -
> -#endif
> diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
> deleted file mode 100644
> index beb532537c22..000000000000
> --- a/arch/arm/mach-dove/cm-a510.c
> +++ /dev/null
> @@ -1,94 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * arch/arm/mach-dove/cm-a510.c
> - *
> - * Copyright (C) 2010 CompuLab, Ltd.
> - * Konstantin Sinyuk <kostyas@compulab.co.il>
> - *
> - * Based on Marvell DB-MV88AP510-BP Development Board Setup
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/platform_device.h>
> -#include <linux/ata_platform.h>
> -#include <linux/mv643xx_eth.h>
> -#include <linux/spi/spi.h>
> -#include <linux/spi/flash.h>
> -
> -#include <asm/mach-types.h>
> -#include <asm/mach/arch.h>
> -
> -#include "dove.h"
> -#include "common.h"
> -
> -static struct mv643xx_eth_platform_data cm_a510_ge00_data = {
> - .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
> -};
> -
> -static struct mv_sata_platform_data cm_a510_sata_data = {
> - .n_ports = 1,
> -};
> -
> -/*
> - * SPI Devices:
> - * SPI0: 1M Flash Winbond w25q32bv
> - */
> -static const struct flash_platform_data cm_a510_spi_flash_data = {
> - .type = "w25q32bv",
> -};
> -
> -static struct spi_board_info __initdata cm_a510_spi_flash_info[] = {
> - {
> - .modalias = "m25p80",
> - .platform_data = &cm_a510_spi_flash_data,
> - .irq = -1,
> - .max_speed_hz = 20000000,
> - .bus_num = 0,
> - .chip_select = 0,
> - },
> -};
> -
> -static int __init cm_a510_pci_init(void)
> -{
> - if (machine_is_cm_a510())
> - dove_pcie_init(1, 1);
> -
> - return 0;
> -}
> -
> -subsys_initcall(cm_a510_pci_init);
> -
> -/* Board Init */
> -static void __init cm_a510_init(void)
> -{
> - /*
> - * Basic Dove setup. Needs to be called early.
> - */
> - dove_init();
> -
> - dove_ge00_init(&cm_a510_ge00_data);
> - dove_ehci0_init();
> - dove_ehci1_init();
> - dove_sata_init(&cm_a510_sata_data);
> - dove_sdio0_init();
> - dove_sdio1_init();
> - dove_spi0_init();
> - dove_spi1_init();
> - dove_uart0_init();
> - dove_uart1_init();
> - dove_i2c_init();
> - spi_register_board_info(cm_a510_spi_flash_info,
> - ARRAY_SIZE(cm_a510_spi_flash_info));
> -}
> -
> -MACHINE_START(CM_A510, "Compulab CM-A510 Board")
> - .atag_offset = 0x100,
> - .nr_irqs = DOVE_NR_IRQS,
> - .init_machine = cm_a510_init,
> - .map_io = dove_map_io,
> - .init_early = dove_init_early,
> - .init_irq = dove_init_irq,
> - .init_time = dove_timer_init,
> - .restart = dove_restart,
> -MACHINE_END
> diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
> deleted file mode 100644
> index 35e978514591..000000000000
> --- a/arch/arm/mach-dove/common.c
> +++ /dev/null
> @@ -1,449 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * arch/arm/mach-dove/common.c
> - *
> - * Core functions for Marvell Dove 88AP510 System On Chip
> - */
> -
> -#include <linux/clk-provider.h>
> -#include <linux/dma-mapping.h>
> -#include <linux/init.h>
> -#include <linux/io.h>
> -#include <linux/platform_data/dma-mv_xor.h>
> -#include <linux/platform_data/usb-ehci-orion.h>
> -#include <linux/platform_device.h>
> -#include <linux/soc/dove/pmu.h>
> -#include <asm/hardware/cache-tauros2.h>
> -#include <asm/mach/arch.h>
> -#include <asm/mach/map.h>
> -#include <asm/mach/time.h>
> -#include <plat/common.h>
> -#include <plat/irq.h>
> -#include <plat/time.h>
> -#include "bridge-regs.h"
> -#include "pm.h"
> -#include "common.h"
> -
> -/* These can go away once Dove uses the mvebu-mbus DT binding */
> -#define DOVE_MBUS_PCIE0_MEM_TARGET 0x4
> -#define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8
> -#define DOVE_MBUS_PCIE0_IO_TARGET 0x4
> -#define DOVE_MBUS_PCIE0_IO_ATTR 0xe0
> -#define DOVE_MBUS_PCIE1_MEM_TARGET 0x8
> -#define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8
> -#define DOVE_MBUS_PCIE1_IO_TARGET 0x8
> -#define DOVE_MBUS_PCIE1_IO_ATTR 0xe0
> -#define DOVE_MBUS_CESA_TARGET 0x3
> -#define DOVE_MBUS_CESA_ATTR 0x1
> -#define DOVE_MBUS_BOOTROM_TARGET 0x1
> -#define DOVE_MBUS_BOOTROM_ATTR 0xfd
> -#define DOVE_MBUS_SCRATCHPAD_TARGET 0xd
> -#define DOVE_MBUS_SCRATCHPAD_ATTR 0x0
> -
> -/*****************************************************************************
> - * I/O Address Mapping
> - ****************************************************************************/
> -static struct map_desc __maybe_unused dove_io_desc[] __initdata = {
> - {
> - .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
> - .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
> - .length = DOVE_SB_REGS_SIZE,
> - .type = MT_DEVICE,
> - }, {
> - .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
> - .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
> - .length = DOVE_NB_REGS_SIZE,
> - .type = MT_DEVICE,
> - },
> -};
> -
> -void __init dove_map_io(void)
> -{
> - iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
> -}
> -
> -/*****************************************************************************
> - * CLK tree
> - ****************************************************************************/
> -static int dove_tclk;
> -
> -static DEFINE_SPINLOCK(gating_lock);
> -static struct clk *tclk;
> -
> -static struct clk __init *dove_register_gate(const char *name,
> - const char *parent, u8 bit_idx)
> -{
> - return clk_register_gate(NULL, name, parent, 0,
> - (void __iomem *)CLOCK_GATING_CONTROL,
> - bit_idx, 0, &gating_lock);
> -}
> -
> -static void __init dove_clk_init(void)
> -{
> - struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
> - struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
> - struct clk *xor0, *xor1, *ge;
> -
> - tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, dove_tclk);
> -
> - usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
> - usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
> - sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
> - pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
> - pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
> - sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
> - sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
> - nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
> - camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
> - i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
> - i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
> - crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
> - ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
> - pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
> - xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
> - xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
> - dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
> - ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
> -
> - orion_clkdev_add(NULL, "orion_spi.0", tclk);
> - orion_clkdev_add(NULL, "orion_spi.1", tclk);
> - orion_clkdev_add(NULL, "orion_wdt", tclk);
> - orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
> -
> - orion_clkdev_add(NULL, "orion-ehci.0", usb0);
> - orion_clkdev_add(NULL, "orion-ehci.1", usb1);
> - orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
> - orion_clkdev_add(NULL, "sata_mv.0", sata);
> - orion_clkdev_add("0", "pcie", pex0);
> - orion_clkdev_add("1", "pcie", pex1);
> - orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
> - orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
> - orion_clkdev_add(NULL, "orion_nand", nand);
> - orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
> - orion_clkdev_add(NULL, "mvebu-audio.0", i2s0);
> - orion_clkdev_add(NULL, "mvebu-audio.1", i2s1);
> - orion_clkdev_add(NULL, "mv_crypto", crypto);
> - orion_clkdev_add(NULL, "dove-ac97", ac97);
> - orion_clkdev_add(NULL, "dove-pdma", pdma);
> - orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
> - orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
> -}
> -
> -/*****************************************************************************
> - * EHCI0
> - ****************************************************************************/
> -void __init dove_ehci0_init(void)
> -{
> - orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
> -}
> -
> -/*****************************************************************************
> - * EHCI1
> - ****************************************************************************/
> -void __init dove_ehci1_init(void)
> -{
> - orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
> -}
> -
> -/*****************************************************************************
> - * GE00
> - ****************************************************************************/
> -void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
> -{
> - orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
> - IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
> - 1600);
> -}
> -
> -/*****************************************************************************
> - * SoC RTC
> - ****************************************************************************/
> -static void __init dove_rtc_init(void)
> -{
> - orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
> -}
> -
> -/*****************************************************************************
> - * SATA
> - ****************************************************************************/
> -void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
> -{
> - orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
> -
> -}
> -
> -/*****************************************************************************
> - * UART0
> - ****************************************************************************/
> -void __init dove_uart0_init(void)
> -{
> - orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
> - IRQ_DOVE_UART_0, tclk);
> -}
> -
> -/*****************************************************************************
> - * UART1
> - ****************************************************************************/
> -void __init dove_uart1_init(void)
> -{
> - orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
> - IRQ_DOVE_UART_1, tclk);
> -}
> -
> -/*****************************************************************************
> - * UART2
> - ****************************************************************************/
> -void __init dove_uart2_init(void)
> -{
> - orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
> - IRQ_DOVE_UART_2, tclk);
> -}
> -
> -/*****************************************************************************
> - * UART3
> - ****************************************************************************/
> -void __init dove_uart3_init(void)
> -{
> - orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
> - IRQ_DOVE_UART_3, tclk);
> -}
> -
> -/*****************************************************************************
> - * SPI
> - ****************************************************************************/
> -void __init dove_spi0_init(void)
> -{
> - orion_spi_init(DOVE_SPI0_PHYS_BASE);
> -}
> -
> -void __init dove_spi1_init(void)
> -{
> - orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
> -}
> -
> -/*****************************************************************************
> - * I2C
> - ****************************************************************************/
> -void __init dove_i2c_init(void)
> -{
> - orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
> -}
> -
> -/*****************************************************************************
> - * Time handling
> - ****************************************************************************/
> -void __init dove_init_early(void)
> -{
> - orion_time_set_base(TIMER_VIRT_BASE);
> - mvebu_mbus_init("marvell,dove-mbus",
> - BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
> - DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
> -}
> -
> -static int __init dove_find_tclk(void)
> -{
> - return 166666667;
> -}
> -
> -void __init dove_timer_init(void)
> -{
> - dove_tclk = dove_find_tclk();
> - orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
> - IRQ_DOVE_BRIDGE, dove_tclk);
> -}
> -
> -/*****************************************************************************
> - * XOR 0
> - ****************************************************************************/
> -static void __init dove_xor0_init(void)
> -{
> - orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
> - IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
> -}
> -
> -/*****************************************************************************
> - * XOR 1
> - ****************************************************************************/
> -static void __init dove_xor1_init(void)
> -{
> - orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
> - IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
> -}
> -
> -/*****************************************************************************
> - * SDIO
> - ****************************************************************************/
> -static u64 sdio_dmamask = DMA_BIT_MASK(32);
> -
> -static struct resource dove_sdio0_resources[] = {
> - {
> - .start = DOVE_SDIO0_PHYS_BASE,
> - .end = DOVE_SDIO0_PHYS_BASE + 0xff,
> - .flags = IORESOURCE_MEM,
> - }, {
> - .start = IRQ_DOVE_SDIO0,
> - .end = IRQ_DOVE_SDIO0,
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -static struct platform_device dove_sdio0 = {
> - .name = "sdhci-dove",
> - .id = 0,
> - .dev = {
> - .dma_mask = &sdio_dmamask,
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - },
> - .resource = dove_sdio0_resources,
> - .num_resources = ARRAY_SIZE(dove_sdio0_resources),
> -};
> -
> -void __init dove_sdio0_init(void)
> -{
> - platform_device_register(&dove_sdio0);
> -}
> -
> -static struct resource dove_sdio1_resources[] = {
> - {
> - .start = DOVE_SDIO1_PHYS_BASE,
> - .end = DOVE_SDIO1_PHYS_BASE + 0xff,
> - .flags = IORESOURCE_MEM,
> - }, {
> - .start = IRQ_DOVE_SDIO1,
> - .end = IRQ_DOVE_SDIO1,
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -static struct platform_device dove_sdio1 = {
> - .name = "sdhci-dove",
> - .id = 1,
> - .dev = {
> - .dma_mask = &sdio_dmamask,
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - },
> - .resource = dove_sdio1_resources,
> - .num_resources = ARRAY_SIZE(dove_sdio1_resources),
> -};
> -
> -void __init dove_sdio1_init(void)
> -{
> - platform_device_register(&dove_sdio1);
> -}
> -
> -void __init dove_setup_cpu_wins(void)
> -{
> - /*
> - * The PCIe windows will no longer be statically allocated
> - * here once Dove is migrated to the pci-mvebu driver. The
> - * non-PCIe windows will no longer be created here once Dove
> - * fully moves to DT.
> - */
> - mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
> - DOVE_MBUS_PCIE0_IO_ATTR,
> - DOVE_PCIE0_IO_PHYS_BASE,
> - DOVE_PCIE0_IO_SIZE,
> - DOVE_PCIE0_IO_BUS_BASE);
> - mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
> - DOVE_MBUS_PCIE1_IO_ATTR,
> - DOVE_PCIE1_IO_PHYS_BASE,
> - DOVE_PCIE1_IO_SIZE,
> - DOVE_PCIE1_IO_BUS_BASE);
> - mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
> - DOVE_MBUS_PCIE0_MEM_ATTR,
> - DOVE_PCIE0_MEM_PHYS_BASE,
> - DOVE_PCIE0_MEM_SIZE);
> - mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
> - DOVE_MBUS_PCIE1_MEM_ATTR,
> - DOVE_PCIE1_MEM_PHYS_BASE,
> - DOVE_PCIE1_MEM_SIZE);
> - mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
> - DOVE_MBUS_CESA_ATTR,
> - DOVE_CESA_PHYS_BASE,
> - DOVE_CESA_SIZE);
> - mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
> - DOVE_MBUS_BOOTROM_ATTR,
> - DOVE_BOOTROM_PHYS_BASE,
> - DOVE_BOOTROM_SIZE);
> - mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
> - DOVE_MBUS_SCRATCHPAD_ATTR,
> - DOVE_SCRATCHPAD_PHYS_BASE,
> - DOVE_SCRATCHPAD_SIZE);
> -}
> -
> -static struct resource orion_wdt_resource[] = {
> - DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
> - DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
> -};
> -
> -static struct platform_device orion_wdt_device = {
> - .name = "orion_wdt",
> - .id = -1,
> - .num_resources = ARRAY_SIZE(orion_wdt_resource),
> - .resource = orion_wdt_resource,
> -};
> -
> -static void __init __maybe_unused orion_wdt_init(void)
> -{
> - platform_device_register(&orion_wdt_device);
> -}
> -
> -static const struct dove_pmu_domain_initdata pmu_domains[] __initconst = {
> - {
> - .pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK,
> - .rst_mask = PMU_SW_RST_VIDEO_MASK,
> - .iso_mask = PMU_ISO_VIDEO_MASK,
> - .name = "vpu-domain",
> - }, {
> - .pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK,
> - .rst_mask = PMU_SW_RST_GPU_MASK,
> - .iso_mask = PMU_ISO_GPU_MASK,
> - .name = "gpu-domain",
> - }, {
> - /* sentinel */
> - },
> -};
> -
> -static const struct dove_pmu_initdata pmu_data __initconst = {
> - .pmc_base = DOVE_PMU_VIRT_BASE,
> - .pmu_base = DOVE_PMU_VIRT_BASE + 0x8000,
> - .irq = IRQ_DOVE_PMU,
> - .irq_domain_start = IRQ_DOVE_PMU_START,
> - .domains = pmu_domains,
> -};
> -
> -void __init dove_init(void)
> -{
> - pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
> - (dove_tclk + 499999) / 1000000);
> -
> -#ifdef CONFIG_CACHE_TAUROS2
> - tauros2_init(0);
> -#endif
> - dove_setup_cpu_wins();
> -
> - /* Setup root of clk tree */
> - dove_clk_init();
> -
> - /* internal devices that every board has */
> - dove_init_pmu_legacy(&pmu_data);
> - dove_rtc_init();
> - dove_xor0_init();
> - dove_xor1_init();
> -}
> -
> -void dove_restart(enum reboot_mode mode, const char *cmd)
> -{
> - /*
> - * Enable soft reset to assert RSTOUTn.
> - */
> - writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
> -
> - /*
> - * Assert soft reset.
> - */
> - writel(SOFT_RESET, SYSTEM_SOFT_RESET);
> -
> - while (1)
> - ;
> -}
> diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
> deleted file mode 100644
> index 57ebc413d68c..000000000000
> --- a/arch/arm/mach-dove/common.h
> +++ /dev/null
> @@ -1,46 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * arch/arm/mach-dove/common.h
> - *
> - * Core functions for Marvell Dove 88AP510 System On Chip
> - */
> -
> -#ifndef __ARCH_DOVE_COMMON_H
> -#define __ARCH_DOVE_COMMON_H
> -
> -#include <linux/reboot.h>
> -
> -struct mv643xx_eth_platform_data;
> -struct mv_sata_platform_data;
> -
> -extern void dove_timer_init(void);
> -
> -/*
> - * Basic Dove init functions used early by machine-setup.
> - */
> -void dove_map_io(void);
> -void dove_init(void);
> -void dove_init_early(void);
> -void dove_init_irq(void);
> -void dove_setup_cpu_wins(void);
> -void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
> -void dove_sata_init(struct mv_sata_platform_data *sata_data);
> -#ifdef CONFIG_PCI
> -void dove_pcie_init(int init_port0, int init_port1);
> -#else
> -static inline void dove_pcie_init(int init_port0, int init_port1) { }
> -#endif
> -void dove_ehci0_init(void);
> -void dove_ehci1_init(void);
> -void dove_uart0_init(void);
> -void dove_uart1_init(void);
> -void dove_uart2_init(void);
> -void dove_uart3_init(void);
> -void dove_spi0_init(void);
> -void dove_spi1_init(void);
> -void dove_i2c_init(void);
> -void dove_sdio0_init(void);
> -void dove_sdio1_init(void);
> -void dove_restart(enum reboot_mode, const char *);
> -
> -#endif
> diff --git a/arch/arm/mach-dove/dove.h b/arch/arm/mach-dove/dove.h
> deleted file mode 100644
> index e5054e3b0b78..000000000000
> --- a/arch/arm/mach-dove/dove.h
> +++ /dev/null
> @@ -1,185 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/* Generic definitions for Marvell Dove 88AP510 SoC */
> -
> -#ifndef __ASM_ARCH_DOVE_H
> -#define __ASM_ARCH_DOVE_H
> -
> -#include "irqs.h"
> -
> -/*
> - * Marvell Dove address maps.
> - *
> - * phys virt size
> - * c8000000 fdb00000 1M Cryptographic SRAM
> - * e0000000 @runtime 128M PCIe-0 Memory space
> - * e8000000 @runtime 128M PCIe-1 Memory space
> - * f1000000 fec00000 1M on-chip south-bridge registers
> - * f1800000 fe400000 8M on-chip north-bridge registers
> - * f2000000 fee00000 1M PCIe-0 I/O space
> - * f2100000 fef00000 1M PCIe-1 I/O space
> - */
> -
> -#define DOVE_CESA_PHYS_BASE 0xc8000000
> -#define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
> -#define DOVE_CESA_SIZE SZ_1M
> -
> -#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
> -#define DOVE_PCIE0_MEM_SIZE SZ_128M
> -
> -#define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
> -#define DOVE_PCIE1_MEM_SIZE SZ_128M
> -
> -#define DOVE_BOOTROM_PHYS_BASE 0xf8000000
> -#define DOVE_BOOTROM_SIZE SZ_128M
> -
> -#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
> -#define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
> -#define DOVE_SCRATCHPAD_SIZE SZ_1M
> -
> -#define DOVE_SB_REGS_PHYS_BASE 0xf1000000
> -#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfec00000)
> -#define DOVE_SB_REGS_SIZE SZ_1M
> -
> -#define DOVE_NB_REGS_PHYS_BASE 0xf1800000
> -#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe400000)
> -#define DOVE_NB_REGS_SIZE SZ_8M
> -
> -#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
> -#define DOVE_PCIE0_IO_BUS_BASE 0x00000000
> -#define DOVE_PCIE0_IO_SIZE SZ_64K
> -
> -#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000
> -#define DOVE_PCIE1_IO_BUS_BASE 0x00010000
> -#define DOVE_PCIE1_IO_SIZE SZ_64K
> -
> -/*
> - * Dove Core Registers Map
> - */
> -
> -/* SPI, I2C, UART */
> -#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000)
> -#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000)
> -#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000)
> -#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100)
> -#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100)
> -#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200)
> -#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200)
> -#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300)
> -#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300)
> -#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600)
> -#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600)
> -
> -/* North-South Bridge */
> -#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000)
> -#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000)
> -#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE)
> -#define BRIDGE_WINS_SZ (0x80)
> -
> -/* Cryptographic Engine */
> -#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000)
> -
> -/* PCIe 0 */
> -#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000)
> -
> -/* USB */
> -#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000)
> -#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000)
> -
> -/* XOR 0 Engine */
> -#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800)
> -#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800)
> -#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00)
> -#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00)
> -
> -/* XOR 1 Engine */
> -#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900)
> -#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900)
> -#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00)
> -#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00)
> -
> -/* Gigabit Ethernet */
> -#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000)
> -
> -/* PCIe 1 */
> -#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000)
> -
> -/* CAFE */
> -#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000)
> -#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000)
> -#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000)
> -#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000)
> -
> -/* SATA */
> -#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000)
> -
> -/* I2S/SPDIF */
> -#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000)
> -#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000)
> -
> -/* NAND Flash Controller */
> -#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000)
> -
> -/* MPP, GPIO, Reset Sampling */
> -#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
> -#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
> -#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014)
> -#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018)
> -#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
> -#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420)
> -#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
> -#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
> -#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
> -#define DOVE_NAND_GPIO_EN (1 << 0)
> -#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
> -#define DOVE_SPI_GPIO_SEL (1 << 5)
> -#define DOVE_UART1_GPIO_SEL (1 << 4)
> -#define DOVE_AU1_GPIO_SEL (1 << 3)
> -#define DOVE_CAM_GPIO_SEL (1 << 2)
> -#define DOVE_SD1_GPIO_SEL (1 << 1)
> -#define DOVE_SD0_GPIO_SEL (1 << 0)
> -
> -/* Power Management */
> -#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000)
> -#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c)
> -
> -/* Real Time Clock */
> -#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500)
> -
> -/* AC97 */
> -#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000)
> -#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000)
> -
> -/* Peripheral DMA */
> -#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000)
> -#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000)
> -
> -#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
> -#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7)
> -#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
> -#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20)
> -#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21)
> -#define DOVE_TWSI_OPTION3_GPIO (1 << 22)
> -#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000)
> -#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
> -#define DOVE_SSP_ON_AU1 (1 << 0)
> -#define DOVE_SSP_CLOCK_ENABLE (1 << 1)
> -#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11)
> -/* Memory Controller */
> -#define DOVE_MC_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x00000)
> -#define DOVE_MC_WINS_BASE (DOVE_MC_PHYS_BASE + 0x100)
> -#define DOVE_MC_WINS_SZ (0x8)
> -#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000)
> -
> -/* LCD Controller */
> -#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
> -#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000)
> -#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
> -#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000)
> -
> -/* Graphic Engine */
> -#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000)
> -
> -/* Video Engine */
> -#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000)
> -
> -#endif
> diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
> deleted file mode 100644
> index 027a8f87bc2e..000000000000
> --- a/arch/arm/mach-dove/irq.c
> +++ /dev/null
> @@ -1,81 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * arch/arm/mach-dove/irq.c
> - *
> - * Dove IRQ handling.
> - */
> -#include <linux/init.h>
> -#include <linux/irq.h>
> -#include <linux/io.h>
> -#include <asm/exception.h>
> -
> -#include <plat/irq.h>
> -#include <plat/orion-gpio.h>
> -
> -#include "pm.h"
> -#include "bridge-regs.h"
> -#include "common.h"
> -
> -static int __initdata gpio0_irqs[4] = {
> - IRQ_DOVE_GPIO_0_7,
> - IRQ_DOVE_GPIO_8_15,
> - IRQ_DOVE_GPIO_16_23,
> - IRQ_DOVE_GPIO_24_31,
> -};
> -
> -static int __initdata gpio1_irqs[4] = {
> - IRQ_DOVE_HIGH_GPIO,
> - 0,
> - 0,
> - 0,
> -};
> -
> -static int __initdata gpio2_irqs[4] = {
> - 0,
> - 0,
> - 0,
> - 0,
> -};
> -
> -static void __iomem *dove_irq_base = IRQ_VIRT_BASE;
> -
> -static asmlinkage void
> -__exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
> -{
> - u32 stat;
> -
> - stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF);
> - stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF);
> - if (stat) {
> - unsigned int hwirq = 1 + __fls(stat);
> - handle_IRQ(hwirq, regs);
> - return;
> - }
> - stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF);
> - stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF);
> - if (stat) {
> - unsigned int hwirq = 33 + __fls(stat);
> - handle_IRQ(hwirq, regs);
> - return;
> - }
> -}
> -
> -void __init dove_init_irq(void)
> -{
> - orion_irq_init(1, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
> - orion_irq_init(33, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
> -
> - set_handle_irq(dove_legacy_handle_irq);
> -
> - /*
> - * Initialize gpiolib for GPIOs 0-71.
> - */
> - orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
> - IRQ_DOVE_GPIO_START, gpio0_irqs);
> -
> - orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
> - IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
> -
> - orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
> - IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
> -}
> diff --git a/arch/arm/mach-dove/irqs.h b/arch/arm/mach-dove/irqs.h
> deleted file mode 100644
> index 5467098c7042..000000000000
> --- a/arch/arm/mach-dove/irqs.h
> +++ /dev/null
> @@ -1,89 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/* IRQ definitions for Marvell Dove 88AP510 SoC */
> -
> -#ifndef __ASM_ARCH_IRQS_H
> -#define __ASM_ARCH_IRQS_H
> -
> -/*
> - * Dove Low Interrupt Controller
> - */
> -#define IRQ_DOVE_BRIDGE (1 + 0)
> -#define IRQ_DOVE_H2C (1 + 1)
> -#define IRQ_DOVE_C2H (1 + 2)
> -#define IRQ_DOVE_NAND (1 + 3)
> -#define IRQ_DOVE_PDMA (1 + 4)
> -#define IRQ_DOVE_SPI1 (1 + 5)
> -#define IRQ_DOVE_SPI0 (1 + 6)
> -#define IRQ_DOVE_UART_0 (1 + 7)
> -#define IRQ_DOVE_UART_1 (1 + 8)
> -#define IRQ_DOVE_UART_2 (1 + 9)
> -#define IRQ_DOVE_UART_3 (1 + 10)
> -#define IRQ_DOVE_I2C (1 + 11)
> -#define IRQ_DOVE_GPIO_0_7 (1 + 12)
> -#define IRQ_DOVE_GPIO_8_15 (1 + 13)
> -#define IRQ_DOVE_GPIO_16_23 (1 + 14)
> -#define IRQ_DOVE_PCIE0_ERR (1 + 15)
> -#define IRQ_DOVE_PCIE0 (1 + 16)
> -#define IRQ_DOVE_PCIE1_ERR (1 + 17)
> -#define IRQ_DOVE_PCIE1 (1 + 18)
> -#define IRQ_DOVE_I2S0 (1 + 19)
> -#define IRQ_DOVE_I2S0_ERR (1 + 20)
> -#define IRQ_DOVE_I2S1 (1 + 21)
> -#define IRQ_DOVE_I2S1_ERR (1 + 22)
> -#define IRQ_DOVE_USB_ERR (1 + 23)
> -#define IRQ_DOVE_USB0 (1 + 24)
> -#define IRQ_DOVE_USB1 (1 + 25)
> -#define IRQ_DOVE_GE00_RX (1 + 26)
> -#define IRQ_DOVE_GE00_TX (1 + 27)
> -#define IRQ_DOVE_GE00_MISC (1 + 28)
> -#define IRQ_DOVE_GE00_SUM (1 + 29)
> -#define IRQ_DOVE_GE00_ERR (1 + 30)
> -#define IRQ_DOVE_CRYPTO (1 + 31)
> -
> -/*
> - * Dove High Interrupt Controller
> - */
> -#define IRQ_DOVE_AC97 (1 + 32)
> -#define IRQ_DOVE_PMU (1 + 33)
> -#define IRQ_DOVE_CAM (1 + 34)
> -#define IRQ_DOVE_SDIO0 (1 + 35)
> -#define IRQ_DOVE_SDIO1 (1 + 36)
> -#define IRQ_DOVE_SDIO0_WAKEUP (1 + 37)
> -#define IRQ_DOVE_SDIO1_WAKEUP (1 + 38)
> -#define IRQ_DOVE_XOR_00 (1 + 39)
> -#define IRQ_DOVE_XOR_01 (1 + 40)
> -#define IRQ_DOVE_XOR0_ERR (1 + 41)
> -#define IRQ_DOVE_XOR_10 (1 + 42)
> -#define IRQ_DOVE_XOR_11 (1 + 43)
> -#define IRQ_DOVE_XOR1_ERR (1 + 44)
> -#define IRQ_DOVE_LCD_DCON (1 + 45)
> -#define IRQ_DOVE_LCD1 (1 + 46)
> -#define IRQ_DOVE_LCD0 (1 + 47)
> -#define IRQ_DOVE_GPU (1 + 48)
> -#define IRQ_DOVE_PERFORM_MNTR (1 + 49)
> -#define IRQ_DOVE_VPRO_DMA1 (1 + 51)
> -#define IRQ_DOVE_SSP_TIMER (1 + 54)
> -#define IRQ_DOVE_SSP (1 + 55)
> -#define IRQ_DOVE_MC_L2_ERR (1 + 56)
> -#define IRQ_DOVE_CRYPTO_ERR (1 + 59)
> -#define IRQ_DOVE_GPIO_24_31 (1 + 60)
> -#define IRQ_DOVE_HIGH_GPIO (1 + 61)
> -#define IRQ_DOVE_SATA (1 + 62)
> -
> -/*
> - * DOVE General Purpose Pins
> - */
> -#define IRQ_DOVE_GPIO_START 65
> -#define NR_GPIO_IRQS 64
> -
> -/*
> - * PMU interrupts
> - */
> -#define IRQ_DOVE_PMU_START (IRQ_DOVE_GPIO_START + NR_GPIO_IRQS)
> -#define NR_PMU_IRQS 7
> -#define IRQ_DOVE_RTC (IRQ_DOVE_PMU_START + 5)
> -
> -#define DOVE_NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
> -
> -
> -#endif
> diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
> deleted file mode 100644
> index e41bd473abe9..000000000000
> --- a/arch/arm/mach-dove/mpp.c
> +++ /dev/null
> @@ -1,159 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * arch/arm/mach-dove/mpp.c
> - *
> - * MPP functions for Marvell Dove SoCs
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/gpio/consumer.h>
> -#include <linux/io.h>
> -#include <plat/mpp.h>
> -#include <plat/orion-gpio.h>
> -#include "dove.h"
> -#include "mpp.h"
> -
> -struct dove_mpp_grp {
> - int start;
> - int end;
> -};
> -
> -/* Map a group to a range of GPIO pins in that group */
> -static const struct dove_mpp_grp dove_mpp_grp[] = {
> - [MPP_24_39] = {
> - .start = 24,
> - .end = 39,
> - },
> - [MPP_40_45] = {
> - .start = 40,
> - .end = 45,
> - },
> - [MPP_46_51] = {
> - .start = 46,
> - .end = 51,
> - },
> - [MPP_58_61] = {
> - .start = 58,
> - .end = 61,
> - },
> - [MPP_62_63] = {
> - .start = 62,
> - .end = 63,
> - },
> -};
> -
> -/* Enable gpio for a range of pins. mode should be a combination of
> - GPIO_OUTPUT_OK | GPIO_INPUT_OK */
> -static void __init dove_mpp_gpio_mode(int start, int end, int gpio_mode)
> -{
> - int i;
> -
> - for (i = start; i <= end; i++)
> - orion_gpio_set_valid(i, gpio_mode);
> -}
> -
> -/* Dump all the extra MPP registers. The platform code will dump the
> - registers for pins 0-23. */
> -static void __init dove_mpp_dump_regs(void)
> -{
> - pr_debug("PMU_CTRL4_CTRL: %08x\n",
> - readl(DOVE_MPP_CTRL4_VIRT_BASE));
> -
> - pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n",
> - readl(DOVE_PMU_MPP_GENERAL_CTRL));
> -
> - pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
> -}
> -
> -static void __init dove_mpp_cfg_nfc(int sel)
> -{
> - u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE);
> -
> - mpp_gen_cfg &= ~0x1;
> - mpp_gen_cfg |= sel;
> - writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE);
> -
> - dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK);
> -}
> -
> -static void __init dove_mpp_cfg_au1(int sel)
> -{
> - u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
> - u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
> - u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
> - u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
> -
> - mpp_ctrl4 &= ~(DOVE_AU1_GPIO_SEL);
> - ssp_ctrl1 &= ~(DOVE_SSP_ON_AU1);
> - mpp_gen_ctrl &= ~(DOVE_AU1_SPDIFO_GPIO_EN);
> - global_cfg_2 &= ~(DOVE_TWSI_OPTION3_GPIO);
> -
> - if (!sel || sel == 0x2)
> - dove_mpp_gpio_mode(52, 57, 0);
> - else
> - dove_mpp_gpio_mode(52, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
> -
> - if (sel & 0x1) {
> - global_cfg_2 |= DOVE_TWSI_OPTION3_GPIO;
> - dove_mpp_gpio_mode(56, 57, 0);
> - }
> - if (sel & 0x2) {
> - mpp_gen_ctrl |= DOVE_AU1_SPDIFO_GPIO_EN;
> - dove_mpp_gpio_mode(57, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
> - }
> - if (sel & 0x4) {
> - ssp_ctrl1 |= DOVE_SSP_ON_AU1;
> - dove_mpp_gpio_mode(52, 55, 0);
> - }
> - if (sel & 0x8)
> - mpp_ctrl4 |= DOVE_AU1_GPIO_SEL;
> -
> - writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
> - writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1);
> - writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE);
> - writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
> -}
> -
> -/* Configure the group registers, enabling GPIO if sel indicates the
> - pin is to be used for GPIO */
> -static void __init dove_mpp_conf_grp(unsigned int *mpp_grp_list)
> -{
> - u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
> - int gpio_mode;
> -
> - for ( ; *mpp_grp_list; mpp_grp_list++) {
> - unsigned int num = MPP_NUM(*mpp_grp_list);
> - unsigned int sel = MPP_SEL(*mpp_grp_list);
> -
> - if (num > MPP_GRP_MAX) {
> - pr_err("dove: invalid MPP GRP number (%u)\n", num);
> - continue;
> - }
> -
> - mpp_ctrl4 &= ~(0x1 << num);
> - mpp_ctrl4 |= sel << num;
> -
> - gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
> - dove_mpp_gpio_mode(dove_mpp_grp[num].start,
> - dove_mpp_grp[num].end, gpio_mode);
> - }
> - writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
> -}
> -
> -/* Configure the various MPP pins on Dove */
> -void __init dove_mpp_conf(unsigned int *mpp_list,
> - unsigned int *mpp_grp_list,
> - unsigned int grp_au1_52_57,
> - unsigned int grp_nfc_64_71)
> -{
> - dove_mpp_dump_regs();
> -
> - /* Use platform code for pins 0-23 */
> - orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE);
> -
> - dove_mpp_conf_grp(mpp_grp_list);
> - dove_mpp_cfg_au1(grp_au1_52_57);
> - dove_mpp_cfg_nfc(grp_nfc_64_71);
> -
> - dove_mpp_dump_regs();
> -}
> diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h
> deleted file mode 100644
> index 2e4b89c86ca8..000000000000
> --- a/arch/arm/mach-dove/mpp.h
> +++ /dev/null
> @@ -1,197 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -#ifndef __ARCH_DOVE_MPP_CODED_H
> -#define __ARCH_DOVE_MPP_CODED_H
> -
> -#define MPP(_num, _sel, _in, _out) ( \
> - /* MPP number */ ((_num) & 0xff) | \
> - /* MPP select value */ (((_sel) & 0xf) << 8) | \
> - /* may be input signal */ ((!!(_in)) << 12) | \
> - /* may be output signal */ ((!!(_out)) << 13))
> -
> -#define MPP0_GPIO0 MPP(0, 0x0, 1, 1)
> -#define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0)
> -#define MPP0_SDIO0_CD MPP(0, 0x3, 0, 0)
> -#define MPP0_LCD0_PWM MPP(0, 0xf, 0, 0)
> -
> -#define MPP1_GPIO1 MPP(1, 0x0, 1, 1)
> -#define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0)
> -#define MPP1_SDIO0_WP MPP(1, 0x3, 0, 0)
> -#define MPP1_LCD1_PWM MPP(1, 0xf, 0, 0)
> -
> -#define MPP2_GPIO2 MPP(2, 0x0, 1, 1)
> -#define MPP2_SATA_PRESENT MPP(2, 0x1, 0, 0)
> -#define MPP2_UA2_TXD MPP(2, 0x2, 0, 0)
> -#define MPP2_SDIO0_BUS_POWER MPP(2, 0x3, 0, 0)
> -#define MPP2_UA_RTSn1 MPP(2, 0x4, 0, 0)
> -
> -#define MPP3_GPIO3 MPP(3, 0x0, 1, 1)
> -#define MPP3_SATA_ACT MPP(3, 0x1, 0, 0)
> -#define MPP3_UA2_RXD MPP(3, 0x2, 0, 0)
> -#define MPP3_SDIO0_LED_CTRL MPP(3, 0x3, 0, 0)
> -#define MPP3_UA_CTSn1 MPP(3, 0x4, 0, 0)
> -#define MPP3_SPI_LCD_CS1 MPP(3, 0xf, 0, 0)
> -
> -#define MPP4_GPIO4 MPP(4, 0x0, 1, 1)
> -#define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0)
> -#define MPP4_SDIO1_CD MPP(4, 0x3, 0, 0)
> -#define MPP4_SPI_1_MISO MPP(4, 0x4, 0, 0)
> -
> -#define MPP5_GPIO5 MPP(5, 0x0, 1, 1)
> -#define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0)
> -#define MPP5_SDIO1_WP MPP(5, 0x3, 0, 0)
> -#define MPP5_SPI_1_CS MPP(5, 0x4, 0, 0)
> -
> -#define MPP6_GPIO6 MPP(6, 0x0, 1, 1)
> -#define MPP6_UA3_TXD MPP(6, 0x2, 0, 0)
> -#define MPP6_SDIO1_BUS_POWER MPP(6, 0x3, 0, 0)
> -#define MPP6_SPI_1_MOSI MPP(6, 0x4, 0, 0)
> -
> -#define MPP7_GPIO7 MPP(7, 0x0, 1, 1)
> -#define MPP7_UA3_RXD MPP(7, 0x2, 0, 0)
> -#define MPP7_SDIO1_LED_CTRL MPP(7, 0x3, 0, 0)
> -#define MPP7_SPI_1_SCK MPP(7, 0x4, 0, 0)
> -
> -#define MPP8_GPIO8 MPP(8, 0x0, 1, 1)
> -#define MPP8_WD_RST_OUT MPP(8, 0x1, 0, 0)
> -
> -#define MPP9_GPIO9 MPP(9, 0x0, 1, 1)
> -#define MPP9_PEX1_CLKREQn MPP(9, 0x5, 0, 0)
> -
> -#define MPP10_GPIO10 MPP(10, 0x0, 1, 1)
> -#define MPP10_SSP_SCLK MPP(10, 0x5, 0, 0)
> -
> -#define MPP11_GPIO11 MPP(11, 0x0, 1, 1)
> -#define MPP11_SATA_PRESENT MPP(11, 0x1, 0, 0)
> -#define MPP11_SATA_ACT MPP(11, 0x2, 0, 0)
> -#define MPP11_SDIO0_LED_CTRL MPP(11, 0x3, 0, 0)
> -#define MPP11_SDIO1_LED_CTRL MPP(11, 0x4, 0, 0)
> -#define MPP11_PEX0_CLKREQn MPP(11, 0x5, 0, 0)
> -
> -#define MPP12_GPIO12 MPP(12, 0x0, 1, 1)
> -#define MPP12_SATA_ACT MPP(12, 0x1, 0, 0)
> -#define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0)
> -#define MPP12_AD0_I2S_EXT_MCLK MPP(12, 0x3, 0, 0)
> -#define MPP12_SDIO1_CD MPP(12, 0x4, 0, 0)
> -
> -#define MPP13_GPIO13 MPP(13, 0x0, 1, 1)
> -#define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0)
> -#define MPP13_AD1_I2S_EXT_MCLK MPP(13, 0x3, 0, 0)
> -#define MPP13_SDIO1WP MPP(13, 0x4, 0, 0)
> -#define MPP13_SSP_EXTCLK MPP(13, 0x5, 0, 0)
> -
> -#define MPP14_GPIO14 MPP(14, 0x0, 1, 1)
> -#define MPP14_UA2_TXD MPP(14, 0x2, 0, 0)
> -#define MPP14_SDIO1_BUS_POWER MPP(14, 0x4, 0, 0)
> -#define MPP14_SSP_RXD MPP(14, 0x5, 0, 0)
> -
> -#define MPP15_GPIO15 MPP(15, 0x0, 1, 1)
> -#define MPP15_UA2_RXD MPP(15, 0x2, 0, 0)
> -#define MPP15_SDIO1_LED_CTRL MPP(15, 0x4, 0, 0)
> -#define MPP15_SSP_SFRM MPP(15, 0x5, 0, 0)
> -
> -#define MPP16_GPIO16 MPP(16, 0x0, 1, 1)
> -#define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0)
> -#define MPP16_SDIO0_CD MPP(16, 0x3, 0, 0)
> -#define MPP16_SPI_LCD_CS1 MPP(16, 0x4, 0, 0)
> -#define MPP16_AC97_SDATA_IN1 MPP(16, 0x5, 0, 0)
> -
> -#define MPP17_GPIO17 MPP(17, 0x0, 1, 1)
> -#define MPP17_AC97_SYSCLK_OUT MPP(17, 0x1, 0, 0)
> -#define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0)
> -#define MPP17_SDIO0_WP MPP(17, 0x3, 0, 0)
> -#define MPP17_TW_SDA2 MPP(17, 0x4, 0, 0)
> -#define MPP17_AC97_SDATA_IN2 MPP(17, 0x5, 0, 0)
> -
> -#define MPP18_GPIO18 MPP(18, 0x0, 1, 1)
> -#define MPP18_UA3_TXD MPP(18, 0x2, 0, 0)
> -#define MPP18_SDIO0_BUS_POWER MPP(18, 0x3, 0, 0)
> -#define MPP18_LCD0_PWM MPP(18, 0x4, 0, 0)
> -#define MPP18_AC_SDATA_IN3 MPP(18, 0x5, 0, 0)
> -
> -#define MPP19_GPIO19 MPP(19, 0x0, 1, 1)
> -#define MPP19_UA3_RXD MPP(19, 0x2, 0, 0)
> -#define MPP19_SDIO0_LED_CTRL MPP(19, 0x3, 0, 0)
> -#define MPP19_TW_SCK2 MPP(19, 0x4, 0, 0)
> -
> -#define MPP20_GPIO20 MPP(20, 0x0, 1, 1)
> -#define MPP20_AC97_SYSCLK_OUT MPP(20, 0x1, 0, 0)
> -#define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0)
> -#define MPP20_SDIO1_CD MPP(20, 0x3, 0, 0)
> -#define MPP20_SDIO0_CD MPP(20, 0x5, 0, 0)
> -#define MPP20_SPI_1_MISO MPP(20, 0x6, 0, 0)
> -
> -#define MPP21_GPIO21 MPP(21, 0x0, 1, 1)
> -#define MPP21_UA1_RTSn MPP(21, 0x1, 0, 0)
> -#define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0)
> -#define MPP21_SDIO1_WP MPP(21, 0x3, 0, 0)
> -#define MPP21_SSP_SFRM MPP(21, 0x4, 0, 0)
> -#define MPP21_SDIO0_WP MPP(21, 0x5, 0, 0)
> -#define MPP21_SPI_1_CS MPP(21, 0x6, 0, 0)
> -
> -#define MPP22_GPIO22 MPP(22, 0x0, 1, 1)
> -#define MPP22_UA1_CTSn MPP(22, 0x1, 0, 0)
> -#define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0)
> -#define MPP22_SDIO1_BUS_POWER MPP(22, 0x3, 0, 0)
> -#define MPP22_SSP_TXD MPP(22, 0x4, 0, 0)
> -#define MPP22_SDIO0_BUS_POWER MPP(22, 0x5, 0, 0)
> -#define MPP22_SPI_1_MOSI MPP(22, 0x6, 0, 0)
> -
> -#define MPP23_GPIO23 MPP(23, 0x0, 1, 1)
> -#define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0)
> -#define MPP23_SDIO1_LED_CTRL MPP(23, 0x3, 0, 0)
> -#define MPP23_SSP_SCLK MPP(23, 0x4, 0, 0)
> -#define MPP23_SDIO0_LED_CTRL MPP(23, 0x5, 0, 0)
> -#define MPP23_SPI_1_SCK MPP(23, 0x6, 0, 0)
> -
> -#define MPP_MAX 23
> -
> -#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 0)
> -
> -/* for MPP groups _num is a group index */
> -enum dove_mpp_grp_idx {
> - MPP_24_39 = 2,
> - MPP_40_45 = 0,
> - MPP_46_51 = 1,
> - MPP_58_61 = 5,
> - MPP_62_63 = 4,
> - MPP_GRP_MAX = 5,
> -};
> -
> -#define MPP_GRP_24_39_GPIO MPP_GRP(MPP_24_39, 0x1)
> -#define MPP_GRP_24_39_CAM MPP_GRP(MPP_24_39, 0x0)
> -
> -#define MPP_GRP_40_45_GPIO MPP_GRP(MPP_40_45, 0x1)
> -#define MPP_GRP_40_45_SD0 MPP_GRP(MPP_40_45, 0x0)
> -
> -#define MPP_GRP_46_51_GPIO MPP_GRP(MPP_46_51, 0x1)
> -#define MPP_GRP_46_51_SD1 MPP_GRP(MPP_46_51, 0x0)
> -
> -#define MPP_GRP_58_61_GPIO MPP_GRP(MPP_58_61, 0x1)
> -#define MPP_GRP_58_61_SPI MPP_GRP(MPP_58_61, 0x0)
> -
> -#define MPP_GRP_62_63_GPIO MPP_GRP(MPP_62_63, 0x1)
> -#define MPP_GRP_62_63_UA1 MPP_GRP(MPP_62_63, 0x0)
> -
> -/* The MPP[64:71] control differs from other groups */
> -#define MPP_GRP_NFC_64_71_GPO 0x1
> -#define MPP_GRP_NFC_64_71_NFC 0x0
> -
> -/*
> - * The MPP[52:57] functionality is encoded by 4 bits in different
> - * registers. The _num field in this case encodes those bits in
> - * correspodence with Table 135 of 88AP510 Functional specification
> - */
> -#define MPP_GRP_AU1_52_57_AU1 0x0
> -#define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2
> -#define MPP_GRP_AU1_52_57_GPIO 0xa
> -#define MPP_GRP_AU1_52_57_TW_GPIO 0xb
> -#define MPP_GRP_AU1_52_57_AU1_SSP 0xc
> -#define MPP_GRP_AU1_52_57_SSP_GPIO 0xe
> -#define MPP_GRP_AU1_52_57_SSP_TW 0xf
> -
> -void dove_mpp_conf(unsigned int *mpp_list,
> - unsigned int *mpp_grp_list,
> - unsigned int grp_au1_52_57,
> - unsigned int grp_nfc_64_71);
> -
> -#endif /* __ARCH_DOVE_MPP_CODED_H */
> diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
> deleted file mode 100644
> index 3044b7e03890..000000000000
> --- a/arch/arm/mach-dove/pcie.c
> +++ /dev/null
> @@ -1,226 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * arch/arm/mach-dove/pcie.c
> - *
> - * PCIe functions for Marvell Dove 88AP510 SoC
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/pci.h>
> -#include <linux/clk.h>
> -#include <video/vga.h>
> -#include <asm/mach/pci.h>
> -#include <asm/mach/arch.h>
> -#include <asm/setup.h>
> -#include <asm/delay.h>
> -#include <plat/pcie.h>
> -#include <plat/addr-map.h>
> -#include "irqs.h"
> -#include "bridge-regs.h"
> -#include "common.h"
> -
> -struct pcie_port {
> - u8 index;
> - u8 root_bus_nr;
> - void __iomem *base;
> - spinlock_t conf_lock;
> - char mem_space_name[16];
> - struct resource res;
> -};
> -
> -static struct pcie_port pcie_port[2];
> -static int num_pcie_ports;
> -
> -
> -static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
> -{
> - struct pcie_port *pp;
> - struct resource realio;
> -
> - if (nr >= num_pcie_ports)
> - return 0;
> -
> - pp = &pcie_port[nr];
> - sys->private_data = pp;
> - pp->root_bus_nr = sys->busnr;
> -
> - /*
> - * Generic PCIe unit setup.
> - */
> - orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
> -
> - orion_pcie_setup(pp->base);
> -
> - realio.start = sys->busnr * SZ_64K;
> - realio.end = realio.start + SZ_64K - 1;
> - pci_remap_iospace(&realio, pp->index == 0 ? DOVE_PCIE0_IO_PHYS_BASE :
> - DOVE_PCIE1_IO_PHYS_BASE);
> -
> - /*
> - * IORESOURCE_MEM
> - */
> - snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
> - "PCIe %d MEM", pp->index);
> - pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
> - pp->res.name = pp->mem_space_name;
> - if (pp->index == 0) {
> - pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
> - pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
> - } else {
> - pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
> - pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
> - }
> - pp->res.flags = IORESOURCE_MEM;
> - if (request_resource(&iomem_resource, &pp->res))
> - panic("Request PCIe Memory resource failed\n");
> - pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
> -
> - return 1;
> -}
> -
> -static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
> -{
> - /*
> - * Don't go out when trying to access nonexisting devices
> - * on the local bus.
> - */
> - if (bus == pp->root_bus_nr && dev > 1)
> - return 0;
> -
> - return 1;
> -}
> -
> -static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
> - int size, u32 *val)
> -{
> - struct pci_sys_data *sys = bus->sysdata;
> - struct pcie_port *pp = sys->private_data;
> - unsigned long flags;
> - int ret;
> -
> - if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
> - *val = 0xffffffff;
> - return PCIBIOS_DEVICE_NOT_FOUND;
> - }
> -
> - spin_lock_irqsave(&pp->conf_lock, flags);
> - ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
> - spin_unlock_irqrestore(&pp->conf_lock, flags);
> -
> - return ret;
> -}
> -
> -static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
> - int where, int size, u32 val)
> -{
> - struct pci_sys_data *sys = bus->sysdata;
> - struct pcie_port *pp = sys->private_data;
> - unsigned long flags;
> - int ret;
> -
> - if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
> - return PCIBIOS_DEVICE_NOT_FOUND;
> -
> - spin_lock_irqsave(&pp->conf_lock, flags);
> - ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
> - spin_unlock_irqrestore(&pp->conf_lock, flags);
> -
> - return ret;
> -}
> -
> -static struct pci_ops pcie_ops = {
> - .read = pcie_rd_conf,
> - .write = pcie_wr_conf,
> -};
> -
> -/*
> - * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
> - * is operating as a root complex this needs to be switched to
> - * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
> - * the device. Decoding setup is handled by the orion code.
> - */
> -static void rc_pci_fixup(struct pci_dev *dev)
> -{
> - if (dev->bus->parent == NULL && dev->devfn == 0) {
> - struct resource *r;
> -
> - dev->class &= 0xff;
> - dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
> - pci_dev_for_each_resource(dev, r) {
> - r->start = 0;
> - r->end = 0;
> - r->flags = 0;
> - }
> - }
> -}
> -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
> -
> -static int __init
> -dove_pcie_scan_bus(int nr, struct pci_host_bridge *bridge)
> -{
> - struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
> -
> - if (nr >= num_pcie_ports) {
> - BUG();
> - return -EINVAL;
> - }
> -
> - list_splice_init(&sys->resources, &bridge->windows);
> - bridge->dev.parent = NULL;
> - bridge->sysdata = sys;
> - bridge->busnr = sys->busnr;
> - bridge->ops = &pcie_ops;
> -
> - return pci_scan_root_bus_bridge(bridge);
> -}
> -
> -static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
> -{
> - struct pci_sys_data *sys = dev->sysdata;
> - struct pcie_port *pp = sys->private_data;
> -
> - return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
> -}
> -
> -static struct hw_pci dove_pci __initdata = {
> - .nr_controllers = 2,
> - .setup = dove_pcie_setup,
> - .scan = dove_pcie_scan_bus,
> - .map_irq = dove_pcie_map_irq,
> -};
> -
> -static void __init add_pcie_port(int index, void __iomem *base)
> -{
> - printk(KERN_INFO "Dove PCIe port %d: ", index);
> -
> - if (orion_pcie_link_up(base)) {
> - struct pcie_port *pp = &pcie_port[num_pcie_ports++];
> - struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0"));
> -
> - if (!IS_ERR(clk))
> - clk_prepare_enable(clk);
> -
> - printk(KERN_INFO "link up\n");
> -
> - pp->index = index;
> - pp->root_bus_nr = -1;
> - pp->base = base;
> - spin_lock_init(&pp->conf_lock);
> - memset(&pp->res, 0, sizeof(pp->res));
> - } else {
> - printk(KERN_INFO "link down, ignoring\n");
> - }
> -}
> -
> -void __init dove_pcie_init(int init_port0, int init_port1)
> -{
> - vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
> -
> - if (init_port0)
> - add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
> -
> - if (init_port1)
> - add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
> -
> - pci_common_init(&dove_pci);
> -}
> diff --git a/arch/arm/mach-dove/pm.h b/arch/arm/mach-dove/pm.h
> deleted file mode 100644
> index a4c3aba1e2d0..000000000000
> --- a/arch/arm/mach-dove/pm.h
> +++ /dev/null
> @@ -1,58 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -
> -#ifndef __ASM_ARCH_PM_H
> -#define __ASM_ARCH_PM_H
> -
> -#include <asm/errno.h>
> -#include "irqs.h"
> -
> -#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)
> -#define CLOCK_GATING_BIT_USB0 0
> -#define CLOCK_GATING_BIT_USB1 1
> -#define CLOCK_GATING_BIT_GBE 2
> -#define CLOCK_GATING_BIT_SATA 3
> -#define CLOCK_GATING_BIT_PCIE0 4
> -#define CLOCK_GATING_BIT_PCIE1 5
> -#define CLOCK_GATING_BIT_SDIO0 8
> -#define CLOCK_GATING_BIT_SDIO1 9
> -#define CLOCK_GATING_BIT_NAND 10
> -#define CLOCK_GATING_BIT_CAMERA 11
> -#define CLOCK_GATING_BIT_I2S0 12
> -#define CLOCK_GATING_BIT_I2S1 13
> -#define CLOCK_GATING_BIT_CRYPTO 15
> -#define CLOCK_GATING_BIT_AC97 21
> -#define CLOCK_GATING_BIT_PDMA 22
> -#define CLOCK_GATING_BIT_XOR0 23
> -#define CLOCK_GATING_BIT_XOR1 24
> -#define CLOCK_GATING_BIT_GIGA_PHY 30
> -#define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0)
> -#define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1)
> -#define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE)
> -#define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA)
> -#define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0)
> -#define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1)
> -#define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0)
> -#define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1)
> -#define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND)
> -#define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA)
> -#define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0)
> -#define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1)
> -#define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO)
> -#define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97)
> -#define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA)
> -#define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0)
> -#define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1)
> -#define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY)
> -
> -#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)
> -
> -#define PMU_SW_RST_VIDEO_MASK BIT(16)
> -#define PMU_SW_RST_GPU_MASK BIT(18)
> -
> -#define PMU_PWR_GPU_PWR_DWN_MASK BIT(2)
> -#define PMU_PWR_VPU_PWR_DWN_MASK BIT(3)
> -
> -#define PMU_ISO_VIDEO_MASK BIT(0)
> -#define PMU_ISO_GPU_MASK BIT(1)
> -
> -#endif
> diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig
> deleted file mode 100644
> index 98b35f5d05ba..000000000000
> --- a/arch/arm/mach-mv78xx0/Kconfig
> +++ /dev/null
> @@ -1,27 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0-only
> -menuconfig ARCH_MV78XX0
> - bool "Marvell MV78xx0 (DEPRECATED)"
> - depends on ARCH_MULTI_V5
> - depends on CPU_LITTLE_ENDIAN
> - depends on ATAGS
> - select CPU_FEROCEON
> - select GPIOLIB
> - select GPIOLIB_LEGACY
> - select MVEBU_MBUS
> - select FORCE_PCI
> - select PLAT_ORION_LEGACY
> - help
> - Support for the following Marvell MV78xx0 series SoCs:
> - MV781x0, MV782x0.
> -
> - This platform is scheduled for removal in early 2027.
> -
> -if ARCH_MV78XX0
> -
> -config MACH_TERASTATION_WXL
> - bool "Buffalo WLX (Terastation Duo) NAS"
> - help
> - Say 'Y' here if you want your kernel to support the
> - Buffalo WXL Nas.
> -
> -endif
> diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile
> deleted file mode 100644
> index ddee6ae501bb..000000000000
> --- a/arch/arm/mach-mv78xx0/Makefile
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0
> -ccflags-y := -I$(srctree)/arch/arm/plat-orion/include
> -
> -obj-y += common.o mpp.o irq.o pcie.o
> -obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o
> diff --git a/arch/arm/mach-mv78xx0/bridge-regs.h b/arch/arm/mach-mv78xx0/bridge-regs.h
> deleted file mode 100644
> index d57ac967c4b3..000000000000
> --- a/arch/arm/mach-mv78xx0/bridge-regs.h
> +++ /dev/null
> @@ -1,31 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -
> -#ifndef __ASM_ARCH_BRIDGE_REGS_H
> -#define __ASM_ARCH_BRIDGE_REGS_H
> -
> -#include "mv78xx0.h"
> -
> -#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
> -#define L2_WRITETHROUGH 0x00020000
> -
> -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
> -#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
> -#define SOFT_RESET_OUT_EN 0x00000004
> -
> -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
> -#define SOFT_RESET 0x00000001
> -
> -#define BRIDGE_INT_TIMER1_CLR (~0x0004)
> -
> -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
> -#define IRQ_CAUSE_ERR_OFF 0x0000
> -#define IRQ_CAUSE_LOW_OFF 0x0004
> -#define IRQ_CAUSE_HIGH_OFF 0x0008
> -#define IRQ_MASK_ERR_OFF 0x000c
> -#define IRQ_MASK_LOW_OFF 0x0010
> -#define IRQ_MASK_HIGH_OFF 0x0014
> -
> -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
> -#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
> -
> -#endif
> diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
> deleted file mode 100644
> index 3b2e381b7383..000000000000
> --- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
> +++ /dev/null
> @@ -1,183 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
> - *
> - * Buffalo WXL (Terastation Duo) Setup routines
> - *
> - * sebastien requiem <sebastien@requiem.fr>
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/platform_device.h>
> -#include <linux/ata_platform.h>
> -#include <linux/mv643xx_eth.h>
> -#include <linux/ethtool.h>
> -#include <linux/i2c.h>
> -#include <linux/gpio/legacy.h>
> -#include <linux/gpio_keys.h>
> -#include <linux/input.h>
> -#include <asm/mach-types.h>
> -#include <asm/mach/arch.h>
> -#include "mv78xx0.h"
> -#include "common.h"
> -#include "mpp.h"
> -
> -
> -#define TSWXL_AUTO_SWITCH 15
> -#define TSWXL_USB_POWER1 30
> -#define TSWXL_USB_POWER2 31
> -
> -
> -/* This arch has 2 Giga Ethernet */
> -
> -static struct mv643xx_eth_platform_data db78x00_ge00_data = {
> - .phy_addr = MV643XX_ETH_PHY_ADDR(0),
> -};
> -
> -static struct mv643xx_eth_platform_data db78x00_ge01_data = {
> - .phy_addr = MV643XX_ETH_PHY_ADDR(8),
> -};
> -
> -
> -/* 2 SATA controller supporting HotPlug */
> -
> -static struct mv_sata_platform_data db78x00_sata_data = {
> - .n_ports = 2,
> -};
> -
> -static struct i2c_board_info __initdata db78x00_i2c_rtc = {
> - I2C_BOARD_INFO("rs5c372a", 0x32),
> -};
> -
> -
> -static unsigned int wxl_mpp_config[] __initdata = {
> - MPP0_GE1_TXCLK,
> - MPP1_GE1_TXCTL,
> - MPP2_GE1_RXCTL,
> - MPP3_GE1_RXCLK,
> - MPP4_GE1_TXD0,
> - MPP5_GE1_TXD1,
> - MPP6_GE1_TXD2,
> - MPP7_GE1_TXD3,
> - MPP8_GE1_RXD0,
> - MPP9_GE1_RXD1,
> - MPP10_GE1_RXD2,
> - MPP11_GE1_RXD3,
> - MPP12_GPIO,
> - MPP13_GPIO,
> - MPP14_GPIO,
> - MPP15_GPIO,
> - MPP16_GPIO,
> - MPP17_GPIO,
> - MPP18_GPIO,
> - MPP19_GPIO,
> - MPP20_GPIO,
> - MPP21_GPIO,
> - MPP22_GPIO,
> - MPP23_GPIO,
> - MPP24_UA2_TXD,
> - MPP25_UA2_RXD,
> - MPP26_UA2_CTSn,
> - MPP27_UA2_RTSn,
> - MPP28_GPIO,
> - MPP29_GPIO,
> - MPP30_GPIO,
> - MPP31_GPIO,
> - MPP32_GPIO,
> - MPP33_GPIO,
> - MPP34_GPIO,
> - MPP35_GPIO,
> - MPP36_GPIO,
> - MPP37_GPIO,
> - MPP38_GPIO,
> - MPP39_GPIO,
> - MPP40_GPIO,
> - MPP41_GPIO,
> - MPP42_GPIO,
> - MPP43_GPIO,
> - MPP44_GPIO,
> - MPP45_GPIO,
> - MPP46_GPIO,
> - MPP47_GPIO,
> - MPP48_GPIO,
> - MPP49_GPIO,
> - 0
> -};
> -
> -static struct gpio_keys_button tswxl_buttons[] = {
> - {
> - .code = KEY_OPTION,
> - .gpio = TSWXL_AUTO_SWITCH,
> - .desc = "Power-auto Switch",
> - .active_low = 1,
> - }
> -};
> -
> -static struct gpio_keys_platform_data tswxl_button_data = {
> - .buttons = tswxl_buttons,
> - .nbuttons = ARRAY_SIZE(tswxl_buttons),
> -};
> -
> -static struct platform_device tswxl_button_device = {
> - .name = "gpio-keys",
> - .id = -1,
> - .num_resources = 0,
> - .dev = {
> - .platform_data = &tswxl_button_data,
> - },
> -};
> -
> -static void __init wxl_init(void)
> -{
> - /*
> - * Basic MV78xx0 setup. Needs to be called early.
> - */
> - mv78xx0_init();
> - mv78xx0_mpp_conf(wxl_mpp_config);
> -
> - /*
> - * Partition on-chip peripherals between the two CPU cores.
> - */
> - mv78xx0_ehci0_init();
> - mv78xx0_ehci1_init();
> - mv78xx0_ge00_init(&db78x00_ge00_data);
> - mv78xx0_ge01_init(&db78x00_ge01_data);
> - mv78xx0_sata_init(&db78x00_sata_data);
> - mv78xx0_uart0_init();
> - mv78xx0_uart1_init();
> - mv78xx0_uart2_init();
> - mv78xx0_uart3_init();
> - mv78xx0_xor_init();
> - mv78xx0_crypto_init();
> - mv78xx0_i2c_init();
> - i2c_register_board_info(0, &db78x00_i2c_rtc, 1);
> -
> - //enable both usb ports
> - gpio_direction_output(TSWXL_USB_POWER1, 1);
> - gpio_direction_output(TSWXL_USB_POWER2, 1);
> -
> - //enable rear switch
> - platform_device_register(&tswxl_button_device);
> -}
> -
> -static int __init wxl_pci_init(void)
> -{
> - if (machine_is_terastation_wxl() && mv78xx0_core_index() == 0)
> - mv78xx0_pcie_init(1, 1);
> -
> - return 0;
> -}
> -subsys_initcall(wxl_pci_init);
> -
> -MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL")
> - /* Maintainer: Sebastien Requiem <sebastien@requiem.fr> */
> - .atag_offset = 0x100,
> - .nr_irqs = MV78XX0_NR_IRQS,
> - .init_machine = wxl_init,
> - .map_io = mv78xx0_map_io,
> - .init_early = mv78xx0_init_early,
> - .init_irq = mv78xx0_init_irq,
> - .init_time = mv78xx0_timer_init,
> - .restart = mv78xx0_restart,
> -MACHINE_END
> diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
> deleted file mode 100644
> index 679753fcc0ef..000000000000
> --- a/arch/arm/mach-mv78xx0/common.c
> +++ /dev/null
> @@ -1,444 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * arch/arm/mach-mv78xx0/common.c
> - *
> - * Core functions for Marvell MV78xx0 SoCs
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/io.h>
> -#include <linux/platform_device.h>
> -#include <linux/serial_8250.h>
> -#include <linux/ata_platform.h>
> -#include <linux/clk-provider.h>
> -#include <linux/ethtool.h>
> -#include <asm/hardware/cache-feroceon-l2.h>
> -#include <asm/mach/map.h>
> -#include <asm/mach/time.h>
> -#include <linux/platform_data/usb-ehci-orion.h>
> -#include <linux/platform_data/mtd-orion_nand.h>
> -#include <plat/time.h>
> -#include <plat/common.h>
> -#include <plat/addr-map.h>
> -#include "mv78xx0.h"
> -#include "bridge-regs.h"
> -#include "common.h"
> -
> -static int get_tclk(void);
> -
> -/*****************************************************************************
> - * Common bits
> - ****************************************************************************/
> -int mv78xx0_core_index(void)
> -{
> - u32 extra;
> -
> - /*
> - * Read Extra Features register.
> - */
> - __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
> -
> - return !!(extra & 0x00004000);
> -}
> -
> -static int get_hclk(void)
> -{
> - int hclk;
> -
> - /*
> - * HCLK tick rate is configured by DEV_D[7:5] pins.
> - */
> - switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
> - case 0:
> - hclk = 166666667;
> - break;
> - case 1:
> - hclk = 200000000;
> - break;
> - case 2:
> - hclk = 266666667;
> - break;
> - case 3:
> - hclk = 333333333;
> - break;
> - case 4:
> - hclk = 400000000;
> - break;
> - default:
> - panic("unknown HCLK PLL setting: %.8x\n",
> - readl(SAMPLE_AT_RESET_LOW));
> - }
> -
> - return hclk;
> -}
> -
> -static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
> -{
> - u32 cfg;
> -
> - /*
> - * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
> - * PCLK/L2CLK by bits [19:14].
> - */
> - if (core_index == 0) {
> - cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
> - } else {
> - cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
> - }
> -
> - /*
> - * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
> - * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
> - */
> - *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
> -
> - /*
> - * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
> - * ratio (1, 2, 3).
> - */
> - *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
> -}
> -
> -static int get_tclk(void)
> -{
> - int tclk_freq;
> -
> - /*
> - * TCLK tick rate is configured by DEV_A[2:0] strap pins.
> - */
> - switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
> - case 1:
> - tclk_freq = 166666667;
> - break;
> - case 3:
> - tclk_freq = 200000000;
> - break;
> - default:
> - panic("unknown TCLK PLL setting: %.8x\n",
> - readl(SAMPLE_AT_RESET_HIGH));
> - }
> -
> - return tclk_freq;
> -}
> -
> -
> -/*****************************************************************************
> - * I/O Address Mapping
> - ****************************************************************************/
> -static struct map_desc mv78xx0_io_desc[] __initdata = {
> - {
> - .virtual = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
> - .pfn = 0,
> - .length = MV78XX0_CORE_REGS_SIZE,
> - .type = MT_DEVICE,
> - }, {
> - .virtual = (unsigned long) MV78XX0_REGS_VIRT_BASE,
> - .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
> - .length = MV78XX0_REGS_SIZE,
> - .type = MT_DEVICE,
> - },
> -};
> -
> -void __init mv78xx0_map_io(void)
> -{
> - unsigned long phys;
> -
> - /*
> - * Map the right set of per-core registers depending on
> - * which core we are running on.
> - */
> - if (mv78xx0_core_index() == 0) {
> - phys = MV78XX0_CORE0_REGS_PHYS_BASE;
> - } else {
> - phys = MV78XX0_CORE1_REGS_PHYS_BASE;
> - }
> - mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
> -
> - iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
> -}
> -
> -
> -/*****************************************************************************
> - * CLK tree
> - ****************************************************************************/
> -static struct clk *tclk;
> -
> -static void __init clk_init(void)
> -{
> - tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, get_tclk());
> -
> - orion_clkdev_init(tclk);
> -}
> -
> -/*****************************************************************************
> - * EHCI
> - ****************************************************************************/
> -void __init mv78xx0_ehci0_init(void)
> -{
> - orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
> -}
> -
> -
> -/*****************************************************************************
> - * EHCI1
> - ****************************************************************************/
> -void __init mv78xx0_ehci1_init(void)
> -{
> - orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
> -}
> -
> -
> -/*****************************************************************************
> - * EHCI2
> - ****************************************************************************/
> -void __init mv78xx0_ehci2_init(void)
> -{
> - orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
> -}
> -
> -
> -/*****************************************************************************
> - * GE00
> - ****************************************************************************/
> -void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
> -{
> - orion_ge00_init(eth_data,
> - GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
> - IRQ_MV78XX0_GE_ERR,
> - MV643XX_TX_CSUM_DEFAULT_LIMIT);
> -}
> -
> -
> -/*****************************************************************************
> - * GE01
> - ****************************************************************************/
> -void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
> -{
> - orion_ge01_init(eth_data,
> - GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
> - MV643XX_TX_CSUM_DEFAULT_LIMIT);
> -}
> -
> -
> -/*****************************************************************************
> - * GE10
> - ****************************************************************************/
> -void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
> -{
> - u32 dev, rev;
> -
> - /*
> - * On the Z0, ge10 and ge11 are internally connected back
> - * to back, and not brought out.
> - */
> - mv78xx0_pcie_id(&dev, &rev);
> - if (dev == MV78X00_Z0_DEV_ID) {
> - eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
> - eth_data->speed = SPEED_1000;
> - eth_data->duplex = DUPLEX_FULL;
> - }
> -
> - orion_ge10_init(eth_data, GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM);
> -}
> -
> -
> -/*****************************************************************************
> - * GE11
> - ****************************************************************************/
> -void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
> -{
> - u32 dev, rev;
> -
> - /*
> - * On the Z0, ge10 and ge11 are internally connected back
> - * to back, and not brought out.
> - */
> - mv78xx0_pcie_id(&dev, &rev);
> - if (dev == MV78X00_Z0_DEV_ID) {
> - eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
> - eth_data->speed = SPEED_1000;
> - eth_data->duplex = DUPLEX_FULL;
> - }
> -
> - orion_ge11_init(eth_data, GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM);
> -}
> -
> -/*****************************************************************************
> - * I2C
> - ****************************************************************************/
> -void __init mv78xx0_i2c_init(void)
> -{
> - orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
> - orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
> -}
> -
> -/*****************************************************************************
> - * SATA
> - ****************************************************************************/
> -void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
> -{
> - orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
> -}
> -
> -
> -/*****************************************************************************
> - * UART0
> - ****************************************************************************/
> -void __init mv78xx0_uart0_init(void)
> -{
> - orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
> - IRQ_MV78XX0_UART_0, tclk);
> -}
> -
> -
> -/*****************************************************************************
> - * UART1
> - ****************************************************************************/
> -void __init mv78xx0_uart1_init(void)
> -{
> - orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
> - IRQ_MV78XX0_UART_1, tclk);
> -}
> -
> -
> -/*****************************************************************************
> - * UART2
> - ****************************************************************************/
> -void __init mv78xx0_uart2_init(void)
> -{
> - orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
> - IRQ_MV78XX0_UART_2, tclk);
> -}
> -
> -/*****************************************************************************
> - * UART3
> - ****************************************************************************/
> -void __init mv78xx0_uart3_init(void)
> -{
> - orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
> - IRQ_MV78XX0_UART_3, tclk);
> -}
> -
> -/*****************************************************************************
> - * Time handling
> - ****************************************************************************/
> -void __init mv78xx0_init_early(void)
> -{
> - orion_time_set_base(TIMER_VIRT_BASE);
> - if (mv78xx0_core_index() == 0)
> - mvebu_mbus_init("marvell,mv78xx0-mbus",
> - BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ,
> - DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ);
> - else
> - mvebu_mbus_init("marvell,mv78xx0-mbus",
> - BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ,
> - DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ);
> -}
> -
> -void __ref mv78xx0_timer_init(void)
> -{
> - orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
> - IRQ_MV78XX0_TIMER_1, get_tclk());
> -}
> -
> -/****************************************************************************
> -* XOR engine
> -****************************************************************************/
> -void __init mv78xx0_xor_init(void)
> -{
> - orion_xor0_init(XOR_PHYS_BASE,
> - XOR_PHYS_BASE + 0x200,
> - IRQ_MV78XX0_XOR_0, IRQ_MV78XX0_XOR_1);
> -}
> -
> -/****************************************************************************
> - * Cryptographic Engines and Security Accelerator (CESA)
> -****************************************************************************/
> -void __init mv78xx0_crypto_init(void)
> -{
> - mvebu_mbus_add_window_by_id(MV78XX0_MBUS_SRAM_TARGET,
> - MV78XX0_MBUS_SRAM_ATTR,
> - MV78XX0_SRAM_PHYS_BASE,
> - MV78XX0_SRAM_SIZE);
> - orion_crypto_init(CRYPTO_PHYS_BASE, MV78XX0_SRAM_PHYS_BASE,
> - SZ_8K, IRQ_MV78XX0_CRYPTO);
> -}
> -
> -
> -/*****************************************************************************
> - * General
> - ****************************************************************************/
> -static char * __init mv78xx0_id(void)
> -{
> - u32 dev, rev;
> -
> - mv78xx0_pcie_id(&dev, &rev);
> -
> - if (dev == MV78X00_Z0_DEV_ID) {
> - if (rev == MV78X00_REV_Z0)
> - return "MV78X00-Z0";
> - else
> - return "MV78X00-Rev-Unsupported";
> - } else if (dev == MV78100_DEV_ID) {
> - if (rev == MV78100_REV_A0)
> - return "MV78100-A0";
> - else if (rev == MV78100_REV_A1)
> - return "MV78100-A1";
> - else
> - return "MV78100-Rev-Unsupported";
> - } else if (dev == MV78200_DEV_ID) {
> - if (rev == MV78100_REV_A0)
> - return "MV78200-A0";
> - else
> - return "MV78200-Rev-Unsupported";
> - } else {
> - return "Device-Unknown";
> - }
> -}
> -
> -static int __init is_l2_writethrough(void)
> -{
> - return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
> -}
> -
> -void __init mv78xx0_init(void)
> -{
> - int core_index;
> - int hclk;
> - int pclk;
> - int l2clk;
> -
> - core_index = mv78xx0_core_index();
> - hclk = get_hclk();
> - get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
> -
> - printk(KERN_INFO "%s ", mv78xx0_id());
> - printk("core #%d, ", core_index);
> - printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
> - printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
> - printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
> - printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
> -
> - if (IS_ENABLED(CONFIG_CACHE_FEROCEON_L2))
> - feroceon_l2_init(is_l2_writethrough());
> -
> - /* Setup root of clk tree */
> - clk_init();
> -}
> -
> -void mv78xx0_restart(enum reboot_mode mode, const char *cmd)
> -{
> - /*
> - * Enable soft reset to assert RSTOUTn.
> - */
> - writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
> -
> - /*
> - * Assert soft reset.
> - */
> - writel(SOFT_RESET, SYSTEM_SOFT_RESET);
> -
> - while (1)
> - ;
> -}
> diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
> deleted file mode 100644
> index 9f1dfd595003..000000000000
> --- a/arch/arm/mach-mv78xx0/common.h
> +++ /dev/null
> @@ -1,54 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * arch/arm/mach-mv78xx0/common.h
> - *
> - * Core functions for Marvell MV78xx0 SoCs
> - */
> -
> -#ifndef __ARCH_MV78XX0_COMMON_H
> -#define __ARCH_MV78XX0_COMMON_H
> -
> -#include <linux/reboot.h>
> -
> -struct mv643xx_eth_platform_data;
> -struct mv_sata_platform_data;
> -
> -/*
> - * Basic MV78xx0 init functions used early by machine-setup.
> - */
> -int mv78xx0_core_index(void);
> -void mv78xx0_map_io(void);
> -void mv78xx0_init(void);
> -void mv78xx0_init_early(void);
> -void mv78xx0_init_irq(void);
> -
> -void mv78xx0_setup_cpu_mbus(void);
> -void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
> - int maj, int min);
> -void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
> - int maj, int min);
> -
> -void mv78xx0_pcie_id(u32 *dev, u32 *rev);
> -
> -void mv78xx0_ehci0_init(void);
> -void mv78xx0_ehci1_init(void);
> -void mv78xx0_ehci2_init(void);
> -void mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data);
> -void mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data);
> -void mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data);
> -void mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data);
> -void mv78xx0_pcie_init(int init_port0, int init_port1);
> -void mv78xx0_sata_init(struct mv_sata_platform_data *sata_data);
> -void mv78xx0_uart0_init(void);
> -void mv78xx0_uart1_init(void);
> -void mv78xx0_uart2_init(void);
> -void mv78xx0_uart3_init(void);
> -void mv78xx0_xor_init(void);
> -void mv78xx0_crypto_init(void);
> -void mv78xx0_i2c_init(void);
> -void mv78xx0_restart(enum reboot_mode, const char *);
> -
> -extern void mv78xx0_timer_init(void);
> -
> -
> -#endif
> diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
> deleted file mode 100644
> index 6e42f6446637..000000000000
> --- a/arch/arm/mach-mv78xx0/irq.c
> +++ /dev/null
> @@ -1,69 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * arch/arm/mach-mv78xx0/irq.c
> - *
> - * MV78xx0 IRQ handling.
> - */
> -#include <linux/gpio/consumer.h>
> -#include <linux/kernel.h>
> -#include <linux/irq.h>
> -#include <linux/io.h>
> -#include <asm/exception.h>
> -#include <plat/orion-gpio.h>
> -#include <plat/irq.h>
> -#include "bridge-regs.h"
> -#include "common.h"
> -
> -static int __initdata gpio0_irqs[4] = {
> - IRQ_MV78XX0_GPIO_0_7,
> - IRQ_MV78XX0_GPIO_8_15,
> - IRQ_MV78XX0_GPIO_16_23,
> - IRQ_MV78XX0_GPIO_24_31,
> -};
> -
> -static void __iomem *mv78xx0_irq_base = IRQ_VIRT_BASE;
> -
> -static asmlinkage void
> -__exception_irq_entry mv78xx0_legacy_handle_irq(struct pt_regs *regs)
> -{
> - u32 stat;
> -
> - stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_LOW_OFF);
> - stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_LOW_OFF);
> - if (stat) {
> - unsigned int hwirq = __fls(stat);
> - handle_IRQ(hwirq, regs);
> - return;
> - }
> - stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_HIGH_OFF);
> - stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_HIGH_OFF);
> - if (stat) {
> - unsigned int hwirq = 32 + __fls(stat);
> - handle_IRQ(hwirq, regs);
> - return;
> - }
> - stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_ERR_OFF);
> - stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_ERR_OFF);
> - if (stat) {
> - unsigned int hwirq = 64 + __fls(stat);
> - handle_IRQ(hwirq, regs);
> - return;
> - }
> -}
> -
> -void __init mv78xx0_init_irq(void)
> -{
> - orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
> - orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
> - orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
> -
> - set_handle_irq(mv78xx0_legacy_handle_irq);
> -
> - /*
> - * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask
> - * registers for core #1 are at an offset of 0x18 from those of
> - * core #0.)
> - */
> - orion_gpio_init(0, 32, GPIO_VIRT_BASE, mv78xx0_core_index() ? 0x18 : 0,
> - IRQ_MV78XX0_GPIO_START, gpio0_irqs);
> -}
> diff --git a/arch/arm/mach-mv78xx0/irqs.h b/arch/arm/mach-mv78xx0/irqs.h
> deleted file mode 100644
> index 12b357d383d8..000000000000
> --- a/arch/arm/mach-mv78xx0/irqs.h
> +++ /dev/null
> @@ -1,87 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/* IRQ definitions for Marvell MV78xx0 SoCs */
> -
> -#ifndef __ASM_ARCH_IRQS_H
> -#define __ASM_ARCH_IRQS_H
> -
> -/*
> - * MV78xx0 Low Interrupt Controller
> - */
> -#define IRQ_MV78XX0_ERR 0
> -#define IRQ_MV78XX0_SPI 1
> -#define IRQ_MV78XX0_I2C_0 2
> -#define IRQ_MV78XX0_I2C_1 3
> -#define IRQ_MV78XX0_IDMA_0 4
> -#define IRQ_MV78XX0_IDMA_1 5
> -#define IRQ_MV78XX0_IDMA_2 6
> -#define IRQ_MV78XX0_IDMA_3 7
> -#define IRQ_MV78XX0_TIMER_0 8
> -#define IRQ_MV78XX0_TIMER_1 9
> -#define IRQ_MV78XX0_TIMER_2 10
> -#define IRQ_MV78XX0_TIMER_3 11
> -#define IRQ_MV78XX0_UART_0 12
> -#define IRQ_MV78XX0_UART_1 13
> -#define IRQ_MV78XX0_UART_2 14
> -#define IRQ_MV78XX0_UART_3 15
> -#define IRQ_MV78XX0_USB_0 16
> -#define IRQ_MV78XX0_USB_1 17
> -#define IRQ_MV78XX0_USB_2 18
> -#define IRQ_MV78XX0_CRYPTO 19
> -#define IRQ_MV78XX0_SDIO_0 20
> -#define IRQ_MV78XX0_SDIO_1 21
> -#define IRQ_MV78XX0_XOR_0 22
> -#define IRQ_MV78XX0_XOR_1 23
> -#define IRQ_MV78XX0_I2S_0 24
> -#define IRQ_MV78XX0_I2S_1 25
> -#define IRQ_MV78XX0_SATA 26
> -#define IRQ_MV78XX0_TDMI 27
> -
> -/*
> - * MV78xx0 High Interrupt Controller
> - */
> -#define IRQ_MV78XX0_PCIE_00 32
> -#define IRQ_MV78XX0_PCIE_01 33
> -#define IRQ_MV78XX0_PCIE_02 34
> -#define IRQ_MV78XX0_PCIE_03 35
> -#define IRQ_MV78XX0_PCIE_10 36
> -#define IRQ_MV78XX0_PCIE_11 37
> -#define IRQ_MV78XX0_PCIE_12 38
> -#define IRQ_MV78XX0_PCIE_13 39
> -#define IRQ_MV78XX0_GE00_SUM 40
> -#define IRQ_MV78XX0_GE00_RX 41
> -#define IRQ_MV78XX0_GE00_TX 42
> -#define IRQ_MV78XX0_GE00_MISC 43
> -#define IRQ_MV78XX0_GE01_SUM 44
> -#define IRQ_MV78XX0_GE01_RX 45
> -#define IRQ_MV78XX0_GE01_TX 46
> -#define IRQ_MV78XX0_GE01_MISC 47
> -#define IRQ_MV78XX0_GE10_SUM 48
> -#define IRQ_MV78XX0_GE10_RX 49
> -#define IRQ_MV78XX0_GE10_TX 50
> -#define IRQ_MV78XX0_GE10_MISC 51
> -#define IRQ_MV78XX0_GE11_SUM 52
> -#define IRQ_MV78XX0_GE11_RX 53
> -#define IRQ_MV78XX0_GE11_TX 54
> -#define IRQ_MV78XX0_GE11_MISC 55
> -#define IRQ_MV78XX0_GPIO_0_7 56
> -#define IRQ_MV78XX0_GPIO_8_15 57
> -#define IRQ_MV78XX0_GPIO_16_23 58
> -#define IRQ_MV78XX0_GPIO_24_31 59
> -#define IRQ_MV78XX0_DB_IN 60
> -#define IRQ_MV78XX0_DB_OUT 61
> -
> -/*
> - * MV78xx0 Error Interrupt Controller
> - */
> -#define IRQ_MV78XX0_GE_ERR 70
> -
> -/*
> - * MV78XX0 General Purpose Pins
> - */
> -#define IRQ_MV78XX0_GPIO_START 96
> -#define NR_GPIO_IRQS 32
> -
> -#define MV78XX0_NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
> -
> -
> -#endif
> diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
> deleted file mode 100644
> index 32bf590d79fe..000000000000
> --- a/arch/arm/mach-mv78xx0/mpp.c
> +++ /dev/null
> @@ -1,34 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * arch/arm/mach-mv78x00/mpp.c
> - *
> - * MPP functions for Marvell MV78x00 SoCs
> - */
> -#include <linux/gpio/consumer.h>
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/io.h>
> -#include <plat/mpp.h>
> -#include "mv78xx0.h"
> -#include "common.h"
> -#include "mpp.h"
> -
> -static unsigned int __init mv78xx0_variant(void)
> -{
> - u32 dev, rev;
> -
> - mv78xx0_pcie_id(&dev, &rev);
> -
> - if (dev == MV78100_DEV_ID && rev >= MV78100_REV_A0)
> - return MPP_78100_A0_MASK;
> -
> - printk(KERN_ERR "MPP setup: unknown mv78x00 variant "
> - "(dev %#x rev %#x)\n", dev, rev);
> - return 0;
> -}
> -
> -void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
> -{
> - orion_mpp_conf(mpp_list, mv78xx0_variant(),
> - MPP_MAX, DEV_BUS_VIRT_BASE);
> -}
> diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h
> deleted file mode 100644
> index 47db52f45546..000000000000
> --- a/arch/arm/mach-mv78xx0/mpp.h
> +++ /dev/null
> @@ -1,337 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * linux/arch/arm/mach-mv78xx0/mpp.h -- Multi Purpose Pins
> - *
> - * sebastien requiem <sebastien@requiem.fr>
> - */
> -
> -#ifndef __MV78X00_MPP_H
> -#define __MV78X00_MPP_H
> -
> -#define MPP(_num, _sel, _in, _out, _78100_A0) (\
> - /* MPP number */ ((_num) & 0xff) | \
> - /* MPP select value */ (((_sel) & 0xf) << 8) | \
> - /* may be input signal */ ((!!(_in)) << 12) | \
> - /* may be output signal */ ((!!(_out)) << 13) | \
> - /* available on A0 */ ((!!(_78100_A0)) << 14))
> -
> - /* num sel i o 78100_A0 */
> -
> -#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1)
> -
> -#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1)
> -#define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1)
> -#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1)
> -#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1)
> -
> -#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1)
> -#define MPP1_GE0_RXERR MPP(1, 0x1, 0, 0, 1)
> -#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1)
> -#define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1)
> -
> -#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1)
> -#define MPP2_GE0_CRS MPP(2, 0x1, 0, 0, 1)
> -#define MPP2_GE1_RXCTL MPP(2, 0x2, 0, 0, 1)
> -#define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1)
> -
> -#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1)
> -#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 0, 1)
> -#define MPP3_GE1_RXCLK MPP(3, 0x2, 0, 0, 1)
> -#define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1)
> -
> -#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1)
> -#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 0, 1)
> -#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 0, 1)
> -#define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1)
> -
> -#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1)
> -#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 0, 1)
> -#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 0, 1)
> -#define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1)
> -
> -#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1)
> -#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 0, 1)
> -#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 0, 1)
> -#define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1)
> -
> -#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1)
> -#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 0, 1)
> -#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 0, 1)
> -#define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1)
> -
> -#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1)
> -#define MPP8_GE0_RXD4 MPP(8, 0x1, 0, 0, 1)
> -#define MPP8_GE1_RXD0 MPP(8, 0x2, 0, 0, 1)
> -#define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1)
> -
> -#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1)
> -#define MPP9_GE0_RXD5 MPP(9, 0x1, 0, 0, 1)
> -#define MPP9_GE1_RXD1 MPP(9, 0x2, 0, 0, 1)
> -#define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1)
> -
> -#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1)
> -#define MPP10_GE0_RXD6 MPP(10, 0x1, 0, 0, 1)
> -#define MPP10_GE1_RXD2 MPP(10, 0x2, 0, 0, 1)
> -#define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1)
> -
> -#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1)
> -#define MPP11_GE0_RXD7 MPP(11, 0x1, 0, 0, 1)
> -#define MPP11_GE1_RXD3 MPP(11, 0x2, 0, 0, 1)
> -#define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1)
> -
> -#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1)
> -#define MPP12_M_BB MPP(12, 0x3, 0, 0, 1)
> -#define MPP12_UA0_CTSn MPP(12, 0x4, 0, 0, 1)
> -#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 0, 1)
> -#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 0, 1)
> -#define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1)
> -
> -#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1)
> -#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 0, 1)
> -#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 0, 1)
> -#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 0, 1)
> -#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 0, 1)
> -#define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1)
> -
> -#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1)
> -#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 0, 1)
> -#define MPP14_UA1_CTSn MPP(14, 0x4, 0, 0, 1)
> -#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 0, 1)
> -#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 0, 1)
> -#define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1)
> -
> -#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1)
> -#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 0, 1)
> -#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 0, 1)
> -#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 0, 1)
> -#define MPP15_TDM_SMISO MPP(15, 0x6, 0, 0, 1)
> -#define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1)
> -
> -#define MPP16_GPIO MPP(16, 0x0, 1, 1, 1)
> -#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 0, 1)
> -#define MPP16_UA2_TXD MPP(16, 0x4, 0, 0, 1)
> -#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 0, 1)
> -#define MPP16_TDM_INTn MPP(16, 0x6, 0, 0, 1)
> -#define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1)
> -
> -
> -#define MPP17_GPIO MPP(17, 0x0, 1, 1, 1)
> -#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 0, 1)
> -#define MPP17_UA2_RXD MPP(17, 0x4, 0, 0, 1)
> -#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 0, 1)
> -#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 0, 1)
> -#define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1)
> -
> -
> -#define MPP18_GPIO MPP(18, 0x0, 1, 1, 1)
> -#define MPP18_UA0_CTSn MPP(18, 0x4, 0, 0, 1)
> -#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 0, 1)
> -#define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1)
> -
> -
> -
> -#define MPP19_GPIO MPP(19, 0x0, 1, 1, 1)
> -#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 0, 1)
> -#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 0, 1)
> -#define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1)
> -
> -
> -#define MPP20_GPIO MPP(20, 0x0, 1, 1, 1)
> -#define MPP20_UA1_CTSs MPP(20, 0x4, 0, 0, 1)
> -#define MPP20_TDM_PCLK MPP(20, 0x6, 0, 0, 0)
> -#define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1)
> -
> -
> -
> -#define MPP21_GPIO MPP(21, 0x0, 1, 1, 1)
> -#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 0, 1)
> -#define MPP21_TDM_FSYNC MPP(21, 0x6, 0, 0, 0)
> -#define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1)
> -
> -
> -
> -#define MPP22_GPIO MPP(22, 0x0, 1, 1, 1)
> -#define MPP22_UA3_TDX MPP(22, 0x4, 0, 0, 1)
> -#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 0, 1)
> -#define MPP22_TDM_DRX MPP(22, 0x6, 0, 0, 1)
> -#define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1)
> -
> -
> -
> -#define MPP23_GPIO MPP(23, 0x0, 1, 1, 1)
> -#define MPP23_UA3_RDX MPP(23, 0x4, 0, 0, 1)
> -#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 0, 1)
> -#define MPP23_TDM_DTX MPP(23, 0x6, 0, 0, 1)
> -#define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1)
> -
> -
> -#define MPP24_GPIO MPP(24, 0x0, 1, 1, 1)
> -#define MPP24_UA2_TXD MPP(24, 0x4, 0, 0, 1)
> -#define MPP24_TDM_INTn MPP(24, 0x6, 0, 0, 1)
> -#define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1)
> -
> -
> -#define MPP25_GPIO MPP(25, 0x0, 1, 1, 1)
> -#define MPP25_UA2_RXD MPP(25, 0x4, 0, 0, 1)
> -#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 0, 1)
> -#define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1)
> -
> -
> -#define MPP26_GPIO MPP(26, 0x0, 1, 1, 1)
> -#define MPP26_UA2_CTSn MPP(26, 0x4, 0, 0, 1)
> -#define MPP26_TDM_PCLK MPP(26, 0x6, 0, 0, 1)
> -#define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1)
> -
> -
> -#define MPP27_GPIO MPP(27, 0x0, 1, 1, 1)
> -#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 0, 1)
> -#define MPP27_TDM_FSYNC MPP(27, 0x6, 0, 0, 1)
> -#define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1)
> -
> -
> -#define MPP28_GPIO MPP(28, 0x0, 1, 1, 1)
> -#define MPP28_UA3_TXD MPP(28, 0x4, 0, 0, 1)
> -#define MPP28_TDM_DRX MPP(28, 0x6, 0, 0, 1)
> -#define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1)
> -
> -#define MPP29_GPIO MPP(29, 0x0, 1, 1, 1)
> -#define MPP29_UA3_RXD MPP(29, 0x4, 0, 0, 1)
> -#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 0, 1)
> -#define MPP29_TDM_DTX MPP(29, 0x6, 0, 0, 1)
> -#define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1)
> -
> -#define MPP30_GPIO MPP(30, 0x0, 1, 1, 1)
> -#define MPP30_UA3_CTSn MPP(30, 0x4, 0, 0, 1)
> -#define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1)
> -
> -#define MPP31_GPIO MPP(31, 0x0, 1, 1, 1)
> -#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 0, 1)
> -#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 0, 1)
> -#define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1)
> -
> -
> -#define MPP32_GPIO MPP(32, 0x1, 1, 1, 1)
> -#define MPP32_UA3_TDX MPP(32, 0x4, 0, 0, 1)
> -#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 0, 1)
> -#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 0, 1)
> -#define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1)
> -
> -
> -#define MPP33_GPIO MPP(33, 0x1, 1, 1, 1)
> -#define MPP33_UA3_RDX MPP(33, 0x4, 0, 0, 1)
> -#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 0, 1)
> -#define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1)
> -
> -
> -
> -#define MPP34_GPIO MPP(34, 0x1, 1, 1, 1)
> -#define MPP34_UA2_TDX MPP(34, 0x4, 0, 0, 1)
> -#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 0, 1)
> -#define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1)
> -
> -
> -
> -#define MPP35_GPIO MPP(35, 0x1, 1, 1, 1)
> -#define MPP35_UA2_RDX MPP(35, 0x4, 0, 0, 1)
> -#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 0, 1)
> -#define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1)
> -
> -#define MPP36_GPIO MPP(36, 0x1, 1, 1, 1)
> -#define MPP36_UA0_CTSn MPP(36, 0x2, 0, 0, 1)
> -#define MPP36_UA2_TDX MPP(36, 0x4, 0, 0, 1)
> -#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 0, 1)
> -#define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1)
> -
> -
> -#define MPP37_GPIO MPP(37, 0x1, 1, 1, 1)
> -#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 0, 1)
> -#define MPP37_UA2_RXD MPP(37, 0x4, 0, 0, 1)
> -#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 0, 1)
> -#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 0, 1)
> -#define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1)
> -
> -
> -
> -
> -#define MPP38_GPIO MPP(38, 0x1, 1, 1, 1)
> -#define MPP38_UA1_CTSn MPP(38, 0x2, 0, 0, 1)
> -#define MPP38_UA3_TXD MPP(38, 0x4, 0, 0, 1)
> -#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 0, 1)
> -#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 0, 1)
> -#define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1)
> -
> -
> -
> -
> -#define MPP39_GPIO MPP(39, 0x1, 1, 1, 1)
> -#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 0, 1)
> -#define MPP39_UA3_RXD MPP(39, 0x4, 0, 0, 1)
> -#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 0, 1)
> -#define MPP39_TDM_SMISO MPP(39, 0x6, 0, 0, 1)
> -#define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1)
> -
> -
> -
> -#define MPP40_GPIO MPP(40, 0x1, 1, 1, 1)
> -#define MPP40_TDM_INTn MPP(40, 0x6, 0, 0, 1)
> -#define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1)
> -
> -
> -
> -#define MPP41_GPIO MPP(41, 0x1, 1, 1, 1)
> -#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 0, 1)
> -#define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1)
> -
> -
> -
> -#define MPP42_GPIO MPP(42, 0x1, 1, 1, 1)
> -#define MPP42_TDM_PCLK MPP(42, 0x6, 0, 0, 1)
> -#define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1)
> -
> -
> -
> -#define MPP43_GPIO MPP(43, 0x1, 1, 1, 1)
> -#define MPP43_TDM_FSYNC MPP(43, 0x6, 0, 0, 1)
> -#define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1)
> -
> -
> -
> -#define MPP44_GPIO MPP(44, 0x1, 1, 1, 1)
> -#define MPP44_TDM_DRX MPP(44, 0x6, 0, 0, 1)
> -#define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1)
> -
> -
> -
> -#define MPP45_GPIO MPP(45, 0x1, 1, 1, 1)
> -#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 0, 1)
> -#define MPP45_TDM_DRX MPP(45, 0x6, 0, 0, 1)
> -#define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1)
> -
> -
> -#define MPP46_GPIO MPP(46, 0x1, 1, 1, 1)
> -#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 0, 1)
> -#define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1)
> -
> -
> -#define MPP47_GPIO MPP(47, 0x1, 1, 1, 1)
> -#define MPP47_UNUSED MPP(47, 0x0, 0, 0, 1)
> -
> -
> -
> -#define MPP48_GPIO MPP(48, 0x1, 1, 1, 1)
> -#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 0, 1)
> -#define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1)
> -
> -
> -
> -#define MPP49_GPIO MPP(49, 0x1, 1, 1, 1)
> -#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 0, 1)
> -#define MPP49_M_BB MPP(49, 0x4, 0, 0, 1)
> -#define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1)
> -
> -
> -#define MPP_MAX 49
> -
> -void mv78xx0_mpp_conf(unsigned int *mpp_list);
> -
> -#endif
> diff --git a/arch/arm/mach-mv78xx0/mv78xx0.h b/arch/arm/mach-mv78xx0/mv78xx0.h
> deleted file mode 100644
> index 88efb1e44142..000000000000
> --- a/arch/arm/mach-mv78xx0/mv78xx0.h
> +++ /dev/null
> @@ -1,134 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * Generic definitions for Marvell MV78xx0 SoC flavors:
> - * MV781x0 and MV782x0.
> - */
> -
> -#ifndef __ASM_ARCH_MV78XX0_H
> -#define __ASM_ARCH_MV78XX0_H
> -
> -#include "irqs.h"
> -
> -/*
> - * Marvell MV78xx0 address maps.
> - *
> - * phys
> - * c0000000 PCIe Memory space
> - * f0800000 PCIe #0 I/O space
> - * f0900000 PCIe #1 I/O space
> - * f0a00000 PCIe #2 I/O space
> - * f0b00000 PCIe #3 I/O space
> - * f0c00000 PCIe #4 I/O space
> - * f0d00000 PCIe #5 I/O space
> - * f0e00000 PCIe #6 I/O space
> - * f0f00000 PCIe #7 I/O space
> - * f1000000 on-chip peripheral registers
> - *
> - * virt phys size
> - * fe400000 f102x000 16K core-specific peripheral registers
> - * fee00000 f0800000 64K PCIe #0 I/O space
> - * fee10000 f0900000 64K PCIe #1 I/O space
> - * fee20000 f0a00000 64K PCIe #2 I/O space
> - * fee30000 f0b00000 64K PCIe #3 I/O space
> - * fee40000 f0c00000 64K PCIe #4 I/O space
> - * fee50000 f0d00000 64K PCIe #5 I/O space
> - * fee60000 f0e00000 64K PCIe #6 I/O space
> - * fee70000 f0f00000 64K PCIe #7 I/O space
> - * fec00000 f1000000 1M on-chip peripheral registers
> - */
> -#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
> -#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
> -#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
> -#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
> -#define MV78XX0_CORE_REGS_SIZE SZ_16K
> -
> -#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
> -#define MV78XX0_PCIE_IO_SIZE SZ_1M
> -
> -#define MV78XX0_REGS_PHYS_BASE 0xf1000000
> -#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
> -#define MV78XX0_REGS_SIZE SZ_1M
> -
> -#define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
> -#define MV78XX0_SRAM_SIZE SZ_8K
> -
> -#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
> -#define MV78XX0_PCIE_MEM_SIZE 0x30000000
> -
> -#define MV78XX0_MBUS_SRAM_TARGET 0x09
> -#define MV78XX0_MBUS_SRAM_ATTR 0x00
> -
> -/*
> - * Core-specific peripheral registers.
> - */
> -#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
> -#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE)
> -#define BRIDGE_WINS_CPU0_BASE (MV78XX0_CORE0_REGS_PHYS_BASE)
> -#define BRIDGE_WINS_CPU1_BASE (MV78XX0_CORE1_REGS_PHYS_BASE)
> -#define BRIDGE_WINS_SZ (0xA000)
> -
> -/*
> - * Register Map
> - */
> -#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000)
> -#define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000)
> -#define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500)
> -#define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570)
> -#define DDR_WINDOW_CPU_SZ (0x20)
> -
> -#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000)
> -#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000)
> -#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030)
> -#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034)
> -#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
> -#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
> -#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100)
> -#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
> -#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
> -#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
> -#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
> -#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200)
> -#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200)
> -#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300)
> -#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300)
> -
> -#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000)
> -#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000)
> -
> -#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000)
> -#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000)
> -#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000)
> -#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000)
> -
> -#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000)
> -#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000)
> -#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000)
> -
> -#define XOR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x60900)
> -
> -#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000)
> -#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000)
> -
> -#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000)
> -#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000)
> -#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000)
> -#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000)
> -
> -#define CRYPTO_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x90000)
> -
> -#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000)
> -
> -/*
> - * Supported devices and revisions.
> - */
> -#define MV78X00_Z0_DEV_ID 0x6381
> -#define MV78X00_REV_Z0 1
> -
> -#define MV78100_DEV_ID 0x7810
> -#define MV78100_REV_A0 1
> -#define MV78100_REV_A1 2
> -
> -#define MV78200_DEV_ID 0x7820
> -#define MV78200_REV_A0 1
> -
> -#endif
> diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
> deleted file mode 100644
> index 533cb7856943..000000000000
> --- a/arch/arm/mach-mv78xx0/pcie.c
> +++ /dev/null
> @@ -1,280 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * arch/arm/mach-mv78xx0/pcie.c
> - *
> - * PCIe functions for Marvell MV78xx0 SoCs
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/pci.h>
> -#include <linux/mbus.h>
> -#include <video/vga.h>
> -#include <asm/irq.h>
> -#include <asm/mach/pci.h>
> -#include <plat/pcie.h>
> -#include "mv78xx0.h"
> -#include "common.h"
> -
> -#define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4)
> -#define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane)))
> -#define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4)
> -#define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane)))
> -
> -struct pcie_port {
> - u8 maj;
> - u8 min;
> - u8 root_bus_nr;
> - void __iomem *base;
> - spinlock_t conf_lock;
> - char mem_space_name[20];
> - struct resource res;
> -};
> -
> -static struct pcie_port pcie_port[8];
> -static int num_pcie_ports;
> -static struct resource pcie_io_space;
> -
> -void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
> -{
> - *dev = orion_pcie_dev_id(PCIE00_VIRT_BASE);
> - *rev = orion_pcie_rev(PCIE00_VIRT_BASE);
> -}
> -
> -u32 pcie_port_size[8] = {
> - 0,
> - 0x20000000,
> - 0x10000000,
> - 0x10000000,
> - 0x08000000,
> - 0x08000000,
> - 0x08000000,
> - 0x04000000,
> -};
> -
> -static void __init mv78xx0_pcie_preinit(void)
> -{
> - int i;
> - u32 size_each;
> - u32 start;
> -
> - pcie_io_space.name = "PCIe I/O Space";
> - pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
> - pcie_io_space.end =
> - MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
> - pcie_io_space.flags = IORESOURCE_MEM;
> - if (request_resource(&iomem_resource, &pcie_io_space))
> - panic("can't allocate PCIe I/O space");
> -
> - if (num_pcie_ports > 7)
> - panic("invalid number of PCIe ports");
> -
> - size_each = pcie_port_size[num_pcie_ports];
> -
> - start = MV78XX0_PCIE_MEM_PHYS_BASE;
> - for (i = 0; i < num_pcie_ports; i++) {
> - struct pcie_port *pp = pcie_port + i;
> -
> - snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
> - "PCIe %d.%d MEM", pp->maj, pp->min);
> - pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
> - pp->res.name = pp->mem_space_name;
> - pp->res.flags = IORESOURCE_MEM;
> - pp->res.start = start;
> - pp->res.end = start + size_each - 1;
> - start += size_each;
> -
> - if (request_resource(&iomem_resource, &pp->res))
> - panic("can't allocate PCIe MEM sub-space");
> -
> - mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min),
> - MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min),
> - pp->res.start, resource_size(&pp->res));
> - mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min),
> - MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min),
> - i * SZ_64K, SZ_64K, 0);
> - }
> -}
> -
> -static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
> -{
> - struct pcie_port *pp;
> - struct resource realio;
> -
> - if (nr >= num_pcie_ports)
> - return 0;
> -
> - pp = &pcie_port[nr];
> - sys->private_data = pp;
> - pp->root_bus_nr = sys->busnr;
> -
> - /*
> - * Generic PCIe unit setup.
> - */
> - orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
> - orion_pcie_setup(pp->base);
> -
> - realio.start = nr * SZ_64K;
> - realio.end = realio.start + SZ_64K - 1;
> - pci_remap_iospace(&realio, MV78XX0_PCIE_IO_PHYS_BASE(nr));
> -
> - pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
> -
> - return 1;
> -}
> -
> -static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
> -{
> - /*
> - * Don't go out when trying to access nonexisting devices
> - * on the local bus.
> - */
> - if (bus == pp->root_bus_nr && dev > 1)
> - return 0;
> -
> - return 1;
> -}
> -
> -static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
> - int size, u32 *val)
> -{
> - struct pci_sys_data *sys = bus->sysdata;
> - struct pcie_port *pp = sys->private_data;
> - unsigned long flags;
> - int ret;
> -
> - if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
> - *val = 0xffffffff;
> - return PCIBIOS_DEVICE_NOT_FOUND;
> - }
> -
> - spin_lock_irqsave(&pp->conf_lock, flags);
> - ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
> - spin_unlock_irqrestore(&pp->conf_lock, flags);
> -
> - return ret;
> -}
> -
> -static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
> - int where, int size, u32 val)
> -{
> - struct pci_sys_data *sys = bus->sysdata;
> - struct pcie_port *pp = sys->private_data;
> - unsigned long flags;
> - int ret;
> -
> - if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
> - return PCIBIOS_DEVICE_NOT_FOUND;
> -
> - spin_lock_irqsave(&pp->conf_lock, flags);
> - ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
> - spin_unlock_irqrestore(&pp->conf_lock, flags);
> -
> - return ret;
> -}
> -
> -static struct pci_ops pcie_ops = {
> - .read = pcie_rd_conf,
> - .write = pcie_wr_conf,
> -};
> -
> -/*
> - * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
> - * is operating as a root complex this needs to be switched to
> - * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
> - * the device. Decoding setup is handled by the orion code.
> - */
> -static void rc_pci_fixup(struct pci_dev *dev)
> -{
> - if (dev->bus->parent == NULL && dev->devfn == 0) {
> - struct resource *r;
> -
> - dev->class &= 0xff;
> - dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
> - pci_dev_for_each_resource(dev, r) {
> - r->start = 0;
> - r->end = 0;
> - r->flags = 0;
> - }
> - }
> -}
> -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
> -
> -static int __init mv78xx0_pcie_scan_bus(int nr, struct pci_host_bridge *bridge)
> -{
> - struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
> -
> - if (nr >= num_pcie_ports) {
> - BUG();
> - return -EINVAL;
> - }
> -
> - list_splice_init(&sys->resources, &bridge->windows);
> - bridge->dev.parent = NULL;
> - bridge->sysdata = sys;
> - bridge->busnr = sys->busnr;
> - bridge->ops = &pcie_ops;
> -
> - return pci_scan_root_bus_bridge(bridge);
> -}
> -
> -static int __init mv78xx0_pcie_map_irq(const struct pci_dev *dev, u8 slot,
> - u8 pin)
> -{
> - struct pci_sys_data *sys = dev->bus->sysdata;
> - struct pcie_port *pp = sys->private_data;
> -
> - return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min;
> -}
> -
> -static struct hw_pci mv78xx0_pci __initdata = {
> - .nr_controllers = 8,
> - .preinit = mv78xx0_pcie_preinit,
> - .setup = mv78xx0_pcie_setup,
> - .scan = mv78xx0_pcie_scan_bus,
> - .map_irq = mv78xx0_pcie_map_irq,
> -};
> -
> -static void __init add_pcie_port(int maj, int min, void __iomem *base)
> -{
> - printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
> -
> - if (orion_pcie_link_up(base)) {
> - struct pcie_port *pp = &pcie_port[num_pcie_ports++];
> -
> - printk("link up\n");
> -
> - pp->maj = maj;
> - pp->min = min;
> - pp->root_bus_nr = -1;
> - pp->base = base;
> - spin_lock_init(&pp->conf_lock);
> - memset(&pp->res, 0, sizeof(pp->res));
> - } else {
> - printk("link down, ignoring\n");
> - }
> -}
> -
> -void __init mv78xx0_pcie_init(int init_port0, int init_port1)
> -{
> - vga_base = MV78XX0_PCIE_MEM_PHYS_BASE;
> -
> - if (init_port0) {
> - add_pcie_port(0, 0, PCIE00_VIRT_BASE);
> - if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) {
> - add_pcie_port(0, 1, PCIE01_VIRT_BASE);
> - add_pcie_port(0, 2, PCIE02_VIRT_BASE);
> - add_pcie_port(0, 3, PCIE03_VIRT_BASE);
> - }
> - }
> -
> - if (init_port1) {
> - add_pcie_port(1, 0, PCIE10_VIRT_BASE);
> - if (!orion_pcie_x4_mode((void __iomem *)PCIE10_VIRT_BASE)) {
> - add_pcie_port(1, 1, PCIE11_VIRT_BASE);
> - add_pcie_port(1, 2, PCIE12_VIRT_BASE);
> - add_pcie_port(1, 3, PCIE13_VIRT_BASE);
> - }
> - }
> -
> - pci_common_init(&mv78xx0_pci);
> -}
> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
> index c61999d01c80..78b8d59d7cc1 100644
> --- a/arch/arm/mach-orion5x/Kconfig
> +++ b/arch/arm/mach-orion5x/Kconfig
> @@ -37,60 +37,6 @@ config MACH_RD88F5182_DT
> Say 'Y' here if you want your kernel to support the Marvell
> Orion-NAS (88F5182) RD2, Flattened Device Tree.
>
> -config MACH_KUROBOX_PRO
> - bool "KuroBox Pro (DEPRECATED)"
> - select I2C_BOARDINFO if I2C
> - depends on ATAGS
> - help
> - Say 'Y' here if you want your kernel to support the
> - KuroBox Pro platform.
> -
> - Support for this machine will go away in early 2027,
> - unless it gets converted to device tree.
> -
> -config MACH_DNS323
> - bool "D-Link DNS-323 (DEPRECATED)"
> - select I2C_BOARDINFO if I2C
> - depends on ATAGS
> - help
> - Say 'Y' here if you want your kernel to support the
> - D-Link DNS-323 platform.
> -
> - Support for this machine will go away in early 2027,
> - unless it gets converted to device tree.
> -
> -config MACH_TS209
> - bool "QNAP TS-109/TS-209 (DEPRECATED)"
> - depends on ATAGS
> - help
> - Say 'Y' here if you want your kernel to support the
> - QNAP TS-109/TS-209 platform.
> -
> - Support for this machine will go away in early 2027,
> - unless it gets converted to device tree.
> -
> -config MACH_TERASTATION_PRO2
> - bool "Buffalo Terastation Pro II/Live (DEPRECATED)"
> - depends on ATAGS
> - help
> - Say 'Y' here if you want your kernel to support the
> - Buffalo Terastation Pro II/Live platform.
> -
> - Support for this machine will go away in early 2027,
> - unless it gets converted to device tree.
> -
> -config MACH_LINKSTATION_PRO
> - bool "Buffalo Linkstation Pro/Live (DEPRECATED)"
> - depends on ATAGS
> - select I2C_BOARDINFO if I2C
> - help
> - Say 'Y' here if you want your kernel to support the
> - Buffalo Linkstation Pro/Live platform. Both v1 and
> - v2 devices are supported.
> -
> - Support for this machine will go away in early 2027,
> - unless it gets converted to device tree.
> -
> config MACH_LINKSTATION_MINI
> bool "Buffalo Linkstation Mini (Flattened Device Tree)"
> select ARCH_ORION5X_DT
> @@ -98,36 +44,6 @@ config MACH_LINKSTATION_MINI
> Say 'Y' here if you want your kernel to support the
> Buffalo Linkstation Mini (LS-WSGL) platform.
>
> -config MACH_TS409
> - bool "QNAP TS-409 (DEPRECATED)"
> - depends on ATAGS
> - help
> - Say 'Y' here if you want your kernel to support the
> - QNAP TS-409 platform.
> -
> - Support for this machine will go away in early 2027,
> - unless it gets converted to device tree.
> -
> -config MACH_TS78XX
> - bool "Technologic Systems TS-78xx (DEPRECATED)"
> - depends on ATAGS
> - help
> - Say 'Y' here if you want your kernel to support the
> - Technologic Systems TS-78xx platform.
> -
> - Support for this machine will go away in early 2027,
> - unless it gets converted to device tree.
> -
> -config MACH_MV2120
> - bool "HP Media Vault mv2120 (DEPRECATED)"
> - depends on ATAGS
> - help
> - Say 'Y' here if you want your kernel to support the
> - HP Media Vault mv2120 or mv5100.
> -
> - Support for this machine will go away in early 2027,
> - unless it gets converted to device tree.
> -
> config MACH_D2NET_DT
> bool "LaCie d2 Network / Big Disk Network (Flattened Device Tree)"
> select ARCH_ORION5X_DT
> @@ -135,17 +51,6 @@ config MACH_D2NET_DT
> Say 'Y' here if you want your kernel to support the
> LaCie d2 Network NAS.
>
> -config MACH_NET2BIG
> - bool "LaCie 2Big Network (DEPRECATED)"
> - depends on ATAGS
> - select I2C_BOARDINFO if I2C
> - help
> - Say 'Y' here if you want your kernel to support the
> - LaCie 2Big Network NAS.
> -
> - Support for this machine will go away in early 2027,
> - unless it gets converted to device tree.
> -
> config MACH_MSS2_DT
> bool "Maxtor Shared Storage II (Flattened Device Tree)"
> select ARCH_ORION5X_DT
> diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
> index 6f54d7fef27a..7e9634e04318 100644
> --- a/arch/arm/mach-orion5x/Makefile
> +++ b/arch/arm/mach-orion5x/Makefile
> @@ -2,15 +2,6 @@
> ccflags-y := -I$(srctree)/arch/arm/plat-orion/include
>
> obj-y += common.o pci.o irq.o mpp.o
> -obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o
> -obj-$(CONFIG_MACH_TERASTATION_PRO2) += terastation_pro2-setup.o
> -obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o
> -obj-$(CONFIG_MACH_DNS323) += dns323-setup.o
> -obj-$(CONFIG_MACH_TS209) += ts209-setup.o tsx09-common.o
> -obj-$(CONFIG_MACH_TS409) += ts409-setup.o tsx09-common.o
> -obj-$(CONFIG_MACH_TS78XX) += ts78xx-setup.o
> -obj-$(CONFIG_MACH_MV2120) += mv2120-setup.o
> -obj-$(CONFIG_MACH_NET2BIG) += net2big-setup.o
>
> obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o
> obj-$(CONFIG_MACH_D2NET_DT) += board-d2net.o
> diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
> index be47492c6640..2614213e2cbc 100644
> --- a/arch/arm/mach-orion5x/board-dt.c
> +++ b/arch/arm/mach-orion5x/board-dt.c
> @@ -18,7 +18,6 @@
> #include <asm/mach/arch.h>
> #include <asm/mach/map.h>
> #include <plat/irq.h>
> -#include <plat/time.h>
> #include "orion5x.h"
> #include "bridge-regs.h"
> #include "common.h"
> @@ -39,7 +38,7 @@ static void __init orion5x_dt_init(void)
> u32 dev, rev;
>
> orion5x_id(&dev, &rev, &dev_name);
> - printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
> + printk(KERN_INFO "Orion ID: %s.\n", dev_name);
>
> BUG_ON(mvebu_mbus_dt_init(false));
>
> diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
> index df056d60b675..050a95af2bbf 100644
> --- a/arch/arm/mach-orion5x/common.c
> +++ b/arch/arm/mach-orion5x/common.c
> @@ -7,27 +7,16 @@
> * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
> */
>
> +#include <linux/delay.h>
> #include <linux/kernel.h>
> #include <linux/init.h>
> #include <linux/io.h>
> -#include <linux/platform_device.h>
> -#include <linux/dma-mapping.h>
> -#include <linux/serial_8250.h>
> -#include <linux/mv643xx_i2c.h>
> -#include <linux/ata_platform.h>
> -#include <linux/delay.h>
> -#include <linux/clk-provider.h>
> -#include <linux/cpu.h>
> +#include <linux/mbus.h>
> #include <asm/page.h>
> #include <asm/setup.h>
> -#include <asm/system_misc.h>
> #include <asm/mach/arch.h>
> #include <asm/mach/map.h>
> #include <asm/mach/time.h>
> -#include <linux/platform_data/mtd-orion_nand.h>
> -#include <linux/platform_data/usb-ehci-orion.h>
> -#include <plat/time.h>
> -#include <plat/common.h>
>
> #include "bridge-regs.h"
> #include "common.h"
> @@ -55,167 +44,6 @@ void __init orion5x_map_io(void)
> iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
> }
>
> -
> -/*****************************************************************************
> - * CLK tree
> - ****************************************************************************/
> -static struct clk *tclk;
> -
> -void __init clk_init(void)
> -{
> - tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, orion5x_tclk);
> -
> - orion_clkdev_init(tclk);
> -}
> -
> -/*****************************************************************************
> - * EHCI0
> - ****************************************************************************/
> -void __init orion5x_ehci0_init(void)
> -{
> - orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
> - EHCI_PHY_ORION);
> -}
> -
> -
> -/*****************************************************************************
> - * EHCI1
> - ****************************************************************************/
> -void __init orion5x_ehci1_init(void)
> -{
> - orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
> -}
> -
> -
> -/*****************************************************************************
> - * GE00
> - ****************************************************************************/
> -void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
> -{
> - orion_ge00_init(eth_data,
> - ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
> - IRQ_ORION5X_ETH_ERR,
> - MV643XX_TX_CSUM_DEFAULT_LIMIT);
> -}
> -
> -
> -/*****************************************************************************
> - * I2C
> - ****************************************************************************/
> -void __init orion5x_i2c_init(void)
> -{
> - orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
> -
> -}
> -
> -
> -/*****************************************************************************
> - * SATA
> - ****************************************************************************/
> -void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
> -{
> - orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
> -}
> -
> -
> -/*****************************************************************************
> - * SPI
> - ****************************************************************************/
> -void __init orion5x_spi_init(void)
> -{
> - orion_spi_init(SPI_PHYS_BASE);
> -}
> -
> -
> -/*****************************************************************************
> - * UART0
> - ****************************************************************************/
> -void __init orion5x_uart0_init(void)
> -{
> - orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
> - IRQ_ORION5X_UART0, tclk);
> -}
> -
> -/*****************************************************************************
> - * UART1
> - ****************************************************************************/
> -void __init orion5x_uart1_init(void)
> -{
> - orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
> - IRQ_ORION5X_UART1, tclk);
> -}
> -
> -/*****************************************************************************
> - * XOR engine
> - ****************************************************************************/
> -void __init orion5x_xor_init(void)
> -{
> - orion_xor0_init(ORION5X_XOR_PHYS_BASE,
> - ORION5X_XOR_PHYS_BASE + 0x200,
> - IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
> -}
> -
> -/*****************************************************************************
> - * Cryptographic Engines and Security Accelerator (CESA)
> - ****************************************************************************/
> -static void __init orion5x_crypto_init(void)
> -{
> - mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET,
> - ORION_MBUS_SRAM_ATTR,
> - ORION5X_SRAM_PHYS_BASE,
> - ORION5X_SRAM_SIZE);
> - orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
> - SZ_8K, IRQ_ORION5X_CESA);
> -}
> -
> -/*****************************************************************************
> - * Watchdog
> - ****************************************************************************/
> -static struct resource orion_wdt_resource[] = {
> - DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
> - DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
> -};
> -
> -static struct platform_device orion_wdt_device = {
> - .name = "orion_wdt",
> - .id = -1,
> - .num_resources = ARRAY_SIZE(orion_wdt_resource),
> - .resource = orion_wdt_resource,
> -};
> -
> -static void __init orion5x_wdt_init(void)
> -{
> - platform_device_register(&orion_wdt_device);
> -}
> -
> -
> -/*****************************************************************************
> - * Time handling
> - ****************************************************************************/
> -void __init orion5x_init_early(void)
> -{
> - u32 rev, dev;
> - const char *mbus_soc_name;
> -
> - orion_time_set_base(TIMER_VIRT_BASE);
> -
> - /* Initialize the MBUS driver */
> - orion5x_pcie_id(&dev, &rev);
> - if (dev == MV88F5281_DEV_ID)
> - mbus_soc_name = "marvell,orion5x-88f5281-mbus";
> - else if (dev == MV88F5182_DEV_ID)
> - mbus_soc_name = "marvell,orion5x-88f5182-mbus";
> - else if (dev == MV88F5181_DEV_ID)
> - mbus_soc_name = "marvell,orion5x-88f5181-mbus";
> - else if (dev == MV88F6183_DEV_ID)
> - mbus_soc_name = "marvell,orion5x-88f6183-mbus";
> - else
> - mbus_soc_name = NULL;
> - mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE,
> - ORION5X_BRIDGE_WINS_SZ,
> - ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ);
> -}
> -
> void orion5x_setup_wins(void)
> {
> /*
> @@ -242,29 +70,6 @@ void orion5x_setup_wins(void)
> ORION5X_PCI_MEM_SIZE);
> }
>
> -int orion5x_tclk;
> -
> -static int __init orion5x_find_tclk(void)
> -{
> - u32 dev, rev;
> -
> - orion5x_pcie_id(&dev, &rev);
> - if (dev == MV88F6183_DEV_ID &&
> - (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
> - return 133333333;
> -
> - return 166666667;
> -}
> -
> -void __init orion5x_timer_init(void)
> -{
> - orion5x_tclk = orion5x_find_tclk();
> -
> - orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
> - IRQ_ORION5X_BRIDGE, orion5x_tclk);
> -}
> -
> -
> /*****************************************************************************
> * General
> ****************************************************************************/
> @@ -310,45 +115,6 @@ void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
> }
> }
>
> -void __init orion5x_init(void)
> -{
> - char *dev_name;
> - u32 dev, rev;
> -
> - orion5x_id(&dev, &rev, &dev_name);
> - printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
> -
> - /*
> - * Setup Orion address map
> - */
> - orion5x_setup_wins();
> -
> - /* Setup root of clk tree */
> - clk_init();
> -
> - /*
> - * Don't issue "Wait for Interrupt" instruction if we are
> - * running on D0 5281 silicon.
> - */
> - if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
> - printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
> - cpu_idle_poll_ctrl(true);
> - }
> -
> - /*
> - * The 5082/5181l/5182/6082/6082l/6183 have crypto
> - * while 5180n/5181/5281 don't have crypto.
> - */
> - if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
> - dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
> - orion5x_crypto_init();
> -
> - /*
> - * Register watchdog driver
> - */
> - orion5x_wdt_init();
> -}
> -
> void orion5x_restart(enum reboot_mode mode, const char *cmd)
> {
> /*
> diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
> index 8df70e23aa82..4dc6c59bde99 100644
> --- a/arch/arm/mach-orion5x/common.h
> +++ b/arch/arm/mach-orion5x/common.h
> @@ -4,9 +4,6 @@
>
> #include <linux/reboot.h>
>
> -struct mv643xx_eth_platform_data;
> -struct mv_sata_platform_data;
> -
> #define ORION_MBUS_PCIE_MEM_TARGET 0x04
> #define ORION_MBUS_PCIE_MEM_ATTR 0x59
> #define ORION_MBUS_PCIE_IO_TARGET 0x04
> @@ -32,21 +29,9 @@ void orion5x_init_early(void);
> void orion5x_init_irq(void);
> void orion5x_init(void);
> void orion5x_id(u32 *dev, u32 *rev, char **dev_name);
> -void clk_init(void);
> -extern int orion5x_tclk;
> -extern void orion5x_timer_init(void);
>
> void orion5x_setup_wins(void);
>
> -void orion5x_ehci0_init(void);
> -void orion5x_ehci1_init(void);
> -void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
> -void orion5x_i2c_init(void);
> -void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
> -void orion5x_spi_init(void);
> -void orion5x_uart0_init(void);
> -void orion5x_uart1_init(void);
> -void orion5x_xor_init(void);
> void orion5x_restart(enum reboot_mode, const char *);
>
> /*
> diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
> deleted file mode 100644
> index 7b81b08b0dda..000000000000
> --- a/arch/arm/mach-orion5x/dns323-setup.c
> +++ /dev/null
> @@ -1,757 +0,0 @@
> -/*
> - * arch/arm/mach-orion5x/dns323-setup.c
> - *
> - * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
> - *
> - * Support for HW Rev C1:
> - *
> - * Copyright (C) 2010 Benjamin Herrenschmidt <benh@kernel.crashing.org>
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU Lesser General Public License as
> - * published by the Free Software Foundation; either version 2 of the
> - * License, or (at your option) any later version.
> - *
> - */
> -#include <linux/gpio/legacy.h>
> -#include <linux/gpio/machine.h>
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/delay.h>
> -#include <linux/platform_device.h>
> -#include <linux/pci.h>
> -#include <linux/irq.h>
> -#include <linux/mtd/physmap.h>
> -#include <linux/mv643xx_eth.h>
> -#include <linux/leds.h>
> -#include <linux/gpio_keys.h>
> -#include <linux/input.h>
> -#include <linux/i2c.h>
> -#include <linux/ata_platform.h>
> -#include <linux/phy.h>
> -#include <linux/marvell_phy.h>
> -#include <asm/mach-types.h>
> -#include <asm/mach/arch.h>
> -#include <asm/mach/pci.h>
> -#include <asm/system_info.h>
> -#include <plat/orion-gpio.h>
> -#include "orion5x.h"
> -#include "common.h"
> -#include "mpp.h"
> -
> -/* Rev A1 and B1 */
> -#define DNS323_GPIO_LED_RIGHT_AMBER 1
> -#define DNS323_GPIO_LED_LEFT_AMBER 2
> -#define DNS323_GPIO_SYSTEM_UP 3
> -#define DNS323_GPIO_LED_POWER1 4
> -#define DNS323_GPIO_LED_POWER2 5
> -#define DNS323_GPIO_OVERTEMP 6
> -#define DNS323_GPIO_RTC 7
> -#define DNS323_GPIO_POWER_OFF 8
> -#define DNS323_GPIO_KEY_POWER 9
> -#define DNS323_GPIO_KEY_RESET 10
> -
> -/* Rev C1 */
> -#define DNS323C_GPIO_KEY_POWER 1
> -#define DNS323C_GPIO_POWER_OFF 2
> -#define DNS323C_GPIO_LED_RIGHT_AMBER 8
> -#define DNS323C_GPIO_LED_LEFT_AMBER 9
> -#define DNS323C_GPIO_LED_POWER 17
> -#define DNS323C_GPIO_FAN_BIT1 18
> -#define DNS323C_GPIO_FAN_BIT0 19
> -
> -/* Exposed to userspace, do not change */
> -enum {
> - DNS323_REV_A1, /* 0 */
> - DNS323_REV_B1, /* 1 */
> - DNS323_REV_C1, /* 2 */
> -};
> -
> -
> -/****************************************************************************
> - * PCI setup
> - */
> -
> -static int __init dns323_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
> -{
> - int irq;
> -
> - /*
> - * Check for devices with hard-wired IRQs.
> - */
> - irq = orion5x_pci_map_irq(dev, slot, pin);
> - if (irq != -1)
> - return irq;
> -
> - return -1;
> -}
> -
> -static struct hw_pci dns323_pci __initdata = {
> - .nr_controllers = 2,
> - .setup = orion5x_pci_sys_setup,
> - .scan = orion5x_pci_sys_scan_bus,
> - .map_irq = dns323_pci_map_irq,
> -};
> -
> -static int __init dns323_pci_init(void)
> -{
> - /* Rev B1 and C1 doesn't really use its PCI bus, and initialising PCI
> - * gets in the way of initialising the SATA controller.
> - */
> - if (machine_is_dns323() && system_rev == DNS323_REV_A1)
> - pci_common_init(&dns323_pci);
> -
> - return 0;
> -}
> -
> -subsys_initcall(dns323_pci_init);
> -
> -/****************************************************************************
> - * 8MiB NOR flash (Spansion S29GL064M90TFIR4)
> - *
> - * Layout as used by D-Link:
> - * 0x00000000-0x00010000 : "MTD1"
> - * 0x00010000-0x00020000 : "MTD2"
> - * 0x00020000-0x001a0000 : "Linux Kernel"
> - * 0x001a0000-0x007d0000 : "File System"
> - * 0x007d0000-0x00800000 : "u-boot"
> - */
> -
> -#define DNS323_NOR_BOOT_BASE 0xf4000000
> -#define DNS323_NOR_BOOT_SIZE SZ_8M
> -
> -static struct mtd_partition dns323_partitions[] = {
> - {
> - .name = "MTD1",
> - .size = 0x00010000,
> - .offset = 0,
> - }, {
> - .name = "MTD2",
> - .size = 0x00010000,
> - .offset = 0x00010000,
> - }, {
> - .name = "Linux Kernel",
> - .size = 0x00180000,
> - .offset = 0x00020000,
> - }, {
> - .name = "File System",
> - .size = 0x00630000,
> - .offset = 0x001A0000,
> - }, {
> - .name = "u-boot",
> - .size = 0x00030000,
> - .offset = 0x007d0000,
> - },
> -};
> -
> -static struct physmap_flash_data dns323_nor_flash_data = {
> - .width = 1,
> - .parts = dns323_partitions,
> - .nr_parts = ARRAY_SIZE(dns323_partitions)
> -};
> -
> -static struct resource dns323_nor_flash_resource = {
> - .flags = IORESOURCE_MEM,
> - .start = DNS323_NOR_BOOT_BASE,
> - .end = DNS323_NOR_BOOT_BASE + DNS323_NOR_BOOT_SIZE - 1,
> -};
> -
> -static struct platform_device dns323_nor_flash = {
> - .name = "physmap-flash",
> - .id = 0,
> - .dev = {
> - .platform_data = &dns323_nor_flash_data,
> - },
> - .resource = &dns323_nor_flash_resource,
> - .num_resources = 1,
> -};
> -
> -/****************************************************************************
> - * Ethernet
> - */
> -
> -static struct mv643xx_eth_platform_data dns323_eth_data = {
> - .phy_addr = MV643XX_ETH_PHY_ADDR(8),
> -};
> -
> -/* dns323_parse_hex_*() taken from tsx09-common.c; should a common copy of these
> - * functions be kept somewhere?
> - */
> -static int __init dns323_parse_hex_nibble(char n)
> -{
> - if (n >= '0' && n <= '9')
> - return n - '0';
> -
> - if (n >= 'A' && n <= 'F')
> - return n - 'A' + 10;
> -
> - if (n >= 'a' && n <= 'f')
> - return n - 'a' + 10;
> -
> - return -1;
> -}
> -
> -static int __init dns323_parse_hex_byte(const char *b)
> -{
> - int hi;
> - int lo;
> -
> - hi = dns323_parse_hex_nibble(b[0]);
> - lo = dns323_parse_hex_nibble(b[1]);
> -
> - if (hi < 0 || lo < 0)
> - return -1;
> -
> - return (hi << 4) | lo;
> -}
> -
> -static int __init dns323_read_mac_addr(void)
> -{
> - u_int8_t addr[6];
> - int i;
> - char *mac_page;
> -
> - /* MAC address is stored as a regular ol' string in /dev/mtdblock4
> - * (0x007d0000-0x00800000) starting at offset 196480 (0x2ff80).
> - */
> - mac_page = ioremap(DNS323_NOR_BOOT_BASE + 0x7d0000 + 196480, 1024);
> - if (!mac_page)
> - return -ENOMEM;
> -
> - /* Sanity check the string we're looking at */
> - for (i = 0; i < 5; i++) {
> - if (*(mac_page + (i * 3) + 2) != ':') {
> - goto error_fail;
> - }
> - }
> -
> - for (i = 0; i < 6; i++) {
> - int byte;
> -
> - byte = dns323_parse_hex_byte(mac_page + (i * 3));
> - if (byte < 0) {
> - goto error_fail;
> - }
> -
> - addr[i] = byte;
> - }
> -
> - iounmap(mac_page);
> - printk("DNS-323: Found ethernet MAC address: %pM\n", addr);
> -
> - memcpy(dns323_eth_data.mac_addr, addr, 6);
> -
> - return 0;
> -
> -error_fail:
> - iounmap(mac_page);
> - return -EINVAL;
> -}
> -
> -/****************************************************************************
> - * GPIO LEDs (simple - doesn't use hardware blinking support)
> - */
> -
> -static struct gpio_led dns323ab_leds[] = {
> - {
> - .name = "power:blue",
> - .default_trigger = "default-on",
> - }, {
> - .name = "right:amber",
> - }, {
> - .name = "left:amber",
> - },
> -};
> -
> -static struct gpiod_lookup_table dns323a1_leds_gpio_table = {
> - .dev_id = "leds-gpio",
> - .table = {
> - GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_POWER2, NULL,
> - 0, GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_RIGHT_AMBER, NULL,
> - 1, GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_LEFT_AMBER, NULL,
> - 2, GPIO_ACTIVE_LOW),
> - { },
> - },
> -};
> -
> -/* B1 is the same but power LED is active high */
> -static struct gpiod_lookup_table dns323b1_leds_gpio_table = {
> - .dev_id = "leds-gpio",
> - .table = {
> - GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_POWER2, NULL,
> - 0, GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_RIGHT_AMBER, NULL,
> - 1, GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_LEFT_AMBER, NULL,
> - 2, GPIO_ACTIVE_LOW),
> - { },
> - },
> -};
> -
> -static struct gpio_led dns323c_leds[] = {
> - {
> - .name = "power:blue",
> - .default_trigger = "timer",
> - }, {
> - .name = "right:amber",
> - }, {
> - .name = "left:amber",
> - },
> -};
> -
> -static struct gpiod_lookup_table dns323c_leds_gpio_table = {
> - .dev_id = "leds-gpio",
> - .table = {
> - GPIO_LOOKUP_IDX("orion_gpio0", DNS323C_GPIO_LED_POWER, NULL,
> - 0, GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP_IDX("orion_gpio0", DNS323C_GPIO_LED_RIGHT_AMBER, NULL,
> - 1, GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP_IDX("orion_gpio0", DNS323C_GPIO_LED_LEFT_AMBER, NULL,
> - 2, GPIO_ACTIVE_LOW),
> - { },
> - },
> -};
> -
> -static struct gpio_led_platform_data dns323ab_led_data = {
> - .num_leds = ARRAY_SIZE(dns323ab_leds),
> - .leds = dns323ab_leds,
> - .gpio_blink_set = orion_gpio_led_blink_set,
> -};
> -
> -static struct gpio_led_platform_data dns323c_led_data = {
> - .num_leds = ARRAY_SIZE(dns323c_leds),
> - .leds = dns323c_leds,
> - .gpio_blink_set = orion_gpio_led_blink_set,
> -};
> -
> -static struct platform_device dns323_gpio_leds = {
> - .name = "leds-gpio",
> - .id = -1,
> - .dev = {
> - .platform_data = &dns323ab_led_data,
> - },
> -};
> -
> -/****************************************************************************
> - * GPIO Attached Keys
> - */
> -
> -static struct gpio_keys_button dns323ab_buttons[] = {
> - {
> - .code = KEY_RESTART,
> - .gpio = DNS323_GPIO_KEY_RESET,
> - .desc = "Reset Button",
> - .active_low = 1,
> - }, {
> - .code = KEY_POWER,
> - .gpio = DNS323_GPIO_KEY_POWER,
> - .desc = "Power Button",
> - .active_low = 1,
> - },
> -};
> -
> -static struct gpio_keys_platform_data dns323ab_button_data = {
> - .buttons = dns323ab_buttons,
> - .nbuttons = ARRAY_SIZE(dns323ab_buttons),
> -};
> -
> -static struct gpio_keys_button dns323c_buttons[] = {
> - {
> - .code = KEY_POWER,
> - .gpio = DNS323C_GPIO_KEY_POWER,
> - .desc = "Power Button",
> - .active_low = 1,
> - },
> -};
> -
> -static struct gpio_keys_platform_data dns323c_button_data = {
> - .buttons = dns323c_buttons,
> - .nbuttons = ARRAY_SIZE(dns323c_buttons),
> -};
> -
> -static struct platform_device dns323_button_device = {
> - .name = "gpio-keys",
> - .id = -1,
> - .num_resources = 0,
> - .dev = {
> - .platform_data = &dns323ab_button_data,
> - },
> -};
> -
> -/*****************************************************************************
> - * SATA
> - */
> -static struct mv_sata_platform_data dns323_sata_data = {
> - .n_ports = 2,
> -};
> -
> -/****************************************************************************
> - * General Setup
> - */
> -static unsigned int dns323a_mpp_modes[] __initdata = {
> - MPP0_PCIE_RST_OUTn,
> - MPP1_GPIO, /* right amber LED (sata ch0) */
> - MPP2_GPIO, /* left amber LED (sata ch1) */
> - MPP3_UNUSED,
> - MPP4_GPIO, /* power button LED */
> - MPP5_GPIO, /* power button LED */
> - MPP6_GPIO, /* GMT G751-2f overtemp */
> - MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */
> - MPP8_GPIO, /* triggers power off */
> - MPP9_GPIO, /* power button switch */
> - MPP10_GPIO, /* reset button switch */
> - MPP11_UNUSED,
> - MPP12_UNUSED,
> - MPP13_UNUSED,
> - MPP14_UNUSED,
> - MPP15_UNUSED,
> - MPP16_UNUSED,
> - MPP17_UNUSED,
> - MPP18_UNUSED,
> - MPP19_UNUSED,
> - 0,
> -};
> -
> -static unsigned int dns323b_mpp_modes[] __initdata = {
> - MPP0_UNUSED,
> - MPP1_GPIO, /* right amber LED (sata ch0) */
> - MPP2_GPIO, /* left amber LED (sata ch1) */
> - MPP3_GPIO, /* system up flag */
> - MPP4_GPIO, /* power button LED */
> - MPP5_GPIO, /* power button LED */
> - MPP6_GPIO, /* GMT G751-2f overtemp */
> - MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */
> - MPP8_GPIO, /* triggers power off */
> - MPP9_GPIO, /* power button switch */
> - MPP10_GPIO, /* reset button switch */
> - MPP11_UNUSED,
> - MPP12_SATA_LED,
> - MPP13_SATA_LED,
> - MPP14_SATA_LED,
> - MPP15_SATA_LED,
> - MPP16_UNUSED,
> - MPP17_UNUSED,
> - MPP18_UNUSED,
> - MPP19_UNUSED,
> - 0,
> -};
> -
> -static unsigned int dns323c_mpp_modes[] __initdata = {
> - MPP0_GPIO, /* ? input */
> - MPP1_GPIO, /* input power switch (0 = pressed) */
> - MPP2_GPIO, /* output power off */
> - MPP3_UNUSED, /* ? output */
> - MPP4_UNUSED, /* ? output */
> - MPP5_UNUSED, /* ? output */
> - MPP6_UNUSED, /* ? output */
> - MPP7_UNUSED, /* ? output */
> - MPP8_GPIO, /* i/o right amber LED */
> - MPP9_GPIO, /* i/o left amber LED */
> - MPP10_GPIO, /* input */
> - MPP11_UNUSED,
> - MPP12_SATA_LED,
> - MPP13_SATA_LED,
> - MPP14_SATA_LED,
> - MPP15_SATA_LED,
> - MPP16_UNUSED,
> - MPP17_GPIO, /* power button LED */
> - MPP18_GPIO, /* fan speed bit 0 */
> - MPP19_GPIO, /* fan speed bit 1 */
> - 0,
> -};
> -
> -/* Rev C1 Fan speed notes:
> - *
> - * The fan is controlled by 2 GPIOs on this board. The settings
> - * of the bits is as follow:
> - *
> - * GPIO 18 GPIO 19 Fan
> - *
> - * 0 0 stopped
> - * 0 1 low speed
> - * 1 0 high speed
> - * 1 1 don't do that (*)
> - *
> - * (*) I think the two bits control two feed-in resistors into a fixed
> - * PWN circuit, setting both bits will basically go a 'bit' faster
> - * than high speed, but d-link doesn't do it and you may get out of
> - * HW spec so don't do it.
> - */
> -
> -/*
> - * On the DNS-323 A1 and B1 the following devices are attached via I2C:
> - *
> - * i2c addr | chip | description
> - * 0x3e | GMT G760Af | fan speed PWM controller
> - * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
> - * 0x68 | ST M41T80 | RTC w/ alarm
> - */
> -static struct i2c_board_info __initdata dns323ab_i2c_devices[] = {
> - {
> - I2C_BOARD_INFO("g760a", 0x3e),
> - }, {
> - I2C_BOARD_INFO("lm75", 0x48),
> - }, {
> - I2C_BOARD_INFO("m41t80", 0x68),
> - },
> -};
> -
> -/*
> - * On the DNS-323 C1 the following devices are attached via I2C:
> - *
> - * i2c addr | chip | description
> - * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
> - * 0x68 | ST M41T80 | RTC w/ alarm
> - */
> -static struct i2c_board_info __initdata dns323c_i2c_devices[] = {
> - {
> - I2C_BOARD_INFO("lm75", 0x48),
> - }, {
> - I2C_BOARD_INFO("m41t80", 0x68),
> - },
> -};
> -
> -/* DNS-323 rev. A specific power off method */
> -static void dns323a_power_off(void)
> -{
> - pr_info("DNS-323: Triggering power-off...\n");
> - gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
> -}
> -
> -/* DNS-323 rev B specific power off method */
> -static void dns323b_power_off(void)
> -{
> - pr_info("DNS-323: Triggering power-off...\n");
> - /* Pin has to be changed to 1 and back to 0 to do actual power off. */
> - gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
> - mdelay(100);
> - gpio_set_value(DNS323_GPIO_POWER_OFF, 0);
> -}
> -
> -/* DNS-323 rev. C specific power off method */
> -static void dns323c_power_off(void)
> -{
> - pr_info("DNS-323: Triggering power-off...\n");
> - gpio_set_value(DNS323C_GPIO_POWER_OFF, 1);
> -}
> -
> -static int dns323c_phy_fixup(struct phy_device *phy)
> -{
> - phy->dev_flags |= MARVELL_PHY_M1118_DNS323_LEDS;
> -
> - return 0;
> -}
> -
> -static int __init dns323_identify_rev(void)
> -{
> - u32 dev, rev, i, reg;
> -
> - pr_debug("DNS-323: Identifying board ... \n");
> -
> - /* Rev A1 has a 5181 */
> - orion5x_pcie_id(&dev, &rev);
> - if (dev == MV88F5181_DEV_ID) {
> - pr_debug("DNS-323: 5181 found, board is A1\n");
> - return DNS323_REV_A1;
> - }
> - pr_debug("DNS-323: 5182 found, board is B1 or C1, checking PHY...\n");
> -
> - /* Rev B1 and C1 both have 5182, let's poke at the eth PHY. This is
> - * a bit gross but we want to do that without links into the eth
> - * driver so let's poke at it directly. We default to rev B1 in
> - * case the accesses fail
> - */
> -
> -#define ETH_SMI_REG (ORION5X_ETH_VIRT_BASE + 0x2000 + 0x004)
> -#define SMI_BUSY 0x10000000
> -#define SMI_READ_VALID 0x08000000
> -#define SMI_OPCODE_READ 0x04000000
> -#define SMI_OPCODE_WRITE 0x00000000
> -
> - for (i = 0; i < 1000; i++) {
> - reg = readl(ETH_SMI_REG);
> - if (!(reg & SMI_BUSY))
> - break;
> - }
> - if (i >= 1000) {
> - pr_warn("DNS-323: Timeout accessing PHY, assuming rev B1\n");
> - return DNS323_REV_B1;
> - }
> - writel((3 << 21) /* phy ID reg */ |
> - (8 << 16) /* phy addr */ |
> - SMI_OPCODE_READ, ETH_SMI_REG);
> - for (i = 0; i < 1000; i++) {
> - reg = readl(ETH_SMI_REG);
> - if (reg & SMI_READ_VALID)
> - break;
> - }
> - if (i >= 1000) {
> - pr_warn("DNS-323: Timeout reading PHY, assuming rev B1\n");
> - return DNS323_REV_B1;
> - }
> - pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff);
> -
> - /* Note: the Marvell tools mask the ID with 0x3f0 before comparison
> - * but I don't see that making a difference here, at least with
> - * any known Marvell PHY ID
> - */
> - switch(reg & 0xfff0) {
> - case 0x0cc0: /* MV88E1111 */
> - return DNS323_REV_B1;
> - case 0x0e10: /* MV88E1118 */
> - return DNS323_REV_C1;
> - default:
> - pr_warn("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n",
> - reg & 0xffff);
> - }
> - return DNS323_REV_B1;
> -}
> -
> -static void __init dns323_init(void)
> -{
> - /* Setup basic Orion functions. Need to be called early. */
> - orion5x_init();
> -
> - /* Identify revision */
> - system_rev = dns323_identify_rev();
> - pr_info("DNS-323: Identified HW revision %c1\n", 'A' + system_rev);
> -
> - /* Just to be tricky, the 5182 has a completely different
> - * set of MPP modes to the 5181.
> - */
> - switch(system_rev) {
> - case DNS323_REV_A1:
> - orion5x_mpp_conf(dns323a_mpp_modes);
> - writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */
> - break;
> - case DNS323_REV_B1:
> - orion5x_mpp_conf(dns323b_mpp_modes);
> - break;
> - case DNS323_REV_C1:
> - orion5x_mpp_conf(dns323c_mpp_modes);
> - break;
> - }
> -
> - /* setup flash mapping
> - * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
> - */
> - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
> - ORION_MBUS_DEVBUS_BOOT_ATTR,
> - DNS323_NOR_BOOT_BASE,
> - DNS323_NOR_BOOT_SIZE);
> - platform_device_register(&dns323_nor_flash);
> -
> - /* Sort out LEDs, Buttons and i2c devices */
> - switch(system_rev) {
> - case DNS323_REV_A1:
> - /* The 5181 power LED is active low and requires
> - * DNS323_GPIO_LED_POWER1 to also be low.
> - */
> - gpiod_add_lookup_table(&dns323a1_leds_gpio_table);
> - gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
> - gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
> - i2c_register_board_info(0, dns323ab_i2c_devices,
> - ARRAY_SIZE(dns323ab_i2c_devices));
> -
> - break;
> - case DNS323_REV_B1:
> - gpiod_add_lookup_table(&dns323b1_leds_gpio_table);
> - i2c_register_board_info(0, dns323ab_i2c_devices,
> - ARRAY_SIZE(dns323ab_i2c_devices));
> - break;
> - case DNS323_REV_C1:
> - /* Hookup LEDs & Buttons */
> - gpiod_add_lookup_table(&dns323c_leds_gpio_table);
> - dns323_gpio_leds.dev.platform_data = &dns323c_led_data;
> - dns323_button_device.dev.platform_data = &dns323c_button_data;
> -
> - /* Hookup i2c devices and fan driver */
> - i2c_register_board_info(0, dns323c_i2c_devices,
> - ARRAY_SIZE(dns323c_i2c_devices));
> - platform_device_register_simple("dns323c-fan", 0, NULL, 0);
> -
> - /* Register fixup for the PHY LEDs */
> - if (!IS_BUILTIN(CONFIG_PHYLIB))
> - break;
> - phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118,
> - MARVELL_PHY_ID_MASK,
> - dns323c_phy_fixup);
> - }
> -
> - platform_device_register(&dns323_gpio_leds);
> - platform_device_register(&dns323_button_device);
> -
> - /*
> - * Configure peripherals.
> - */
> - if (dns323_read_mac_addr() < 0)
> - printk("DNS-323: Failed to read MAC address\n");
> - orion5x_ehci0_init();
> - orion5x_eth_init(&dns323_eth_data);
> - orion5x_i2c_init();
> - orion5x_uart0_init();
> -
> - /* Remaining GPIOs */
> - switch(system_rev) {
> - case DNS323_REV_A1:
> - /* Poweroff GPIO */
> - if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
> - gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
> - pr_err("DNS-323: failed to setup power-off GPIO\n");
> - register_platform_power_off(dns323a_power_off);
> - break;
> - case DNS323_REV_B1:
> - /* 5182 built-in SATA init */
> - orion5x_sata_init(&dns323_sata_data);
> -
> - /* The DNS323 rev B1 has flag to indicate the system is up.
> - * Without this flag set, power LED will flash and cannot be
> - * controlled via leds-gpio.
> - */
> - if (gpio_request(DNS323_GPIO_SYSTEM_UP, "SYS_READY") == 0)
> - gpio_direction_output(DNS323_GPIO_SYSTEM_UP, 1);
> -
> - /* Poweroff GPIO */
> - if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
> - gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
> - pr_err("DNS-323: failed to setup power-off GPIO\n");
> - register_platform_power_off(dns323b_power_off);
> - break;
> - case DNS323_REV_C1:
> - /* 5182 built-in SATA init */
> - orion5x_sata_init(&dns323_sata_data);
> -
> - /* Poweroff GPIO */
> - if (gpio_request(DNS323C_GPIO_POWER_OFF, "POWEROFF") != 0 ||
> - gpio_direction_output(DNS323C_GPIO_POWER_OFF, 0) != 0)
> - pr_err("DNS-323: failed to setup power-off GPIO\n");
> - register_platform_power_off(dns323c_power_off);
> -
> - /* Now, -this- should theoretically be done by the sata_mv driver
> - * once I figure out what's going on there. Maybe the behaviour
> - * of the LEDs should be somewhat passed via the platform_data.
> - * for now, just whack the register and make the LEDs happy
> - *
> - * Note: AFAIK, rev B1 needs the same treatment but I'll let
> - * somebody else test it.
> - */
> - writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c);
> - break;
> - }
> -}
> -
> -/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
> -MACHINE_START(DNS323, "D-Link DNS-323")
> - /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
> - .atag_offset = 0x100,
> - .nr_irqs = ORION5X_NR_IRQS,
> - .init_machine = dns323_init,
> - .map_io = orion5x_map_io,
> - .init_early = orion5x_init_early,
> - .init_irq = orion5x_init_irq,
> - .init_time = orion5x_timer_init,
> - .fixup = tag_fixup_mem32,
> - .restart = orion5x_restart,
> -MACHINE_END
> diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
> deleted file mode 100644
> index e61b9ab06943..000000000000
> --- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
> +++ /dev/null
> @@ -1,407 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * arch/arm/mach-orion5x/kurobox_pro-setup.c
> - *
> - * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
> - */
> -#include <linux/gpio/consumer.h>
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/platform_device.h>
> -#include <linux/pci.h>
> -#include <linux/irq.h>
> -#include <linux/delay.h>
> -#include <linux/mtd/physmap.h>
> -#include <linux/mtd/rawnand.h>
> -#include <linux/mv643xx_eth.h>
> -#include <linux/i2c.h>
> -#include <linux/serial_reg.h>
> -#include <linux/ata_platform.h>
> -#include <asm/mach-types.h>
> -#include <asm/mach/arch.h>
> -#include <asm/mach/pci.h>
> -#include <linux/platform_data/mtd-orion_nand.h>
> -#include "common.h"
> -#include "mpp.h"
> -#include "orion5x.h"
> -
> -/*****************************************************************************
> - * KUROBOX-PRO Info
> - ****************************************************************************/
> -
> -/*
> - * 256K NOR flash Device bus boot chip select
> - */
> -
> -#define KUROBOX_PRO_NOR_BOOT_BASE 0xf4000000
> -#define KUROBOX_PRO_NOR_BOOT_SIZE SZ_256K
> -
> -/*
> - * 256M NAND flash on Device bus chip select 1
> - */
> -
> -#define KUROBOX_PRO_NAND_BASE 0xfc000000
> -#define KUROBOX_PRO_NAND_SIZE SZ_2M
> -
> -/*****************************************************************************
> - * 256MB NAND Flash on Device bus CS0
> - ****************************************************************************/
> -
> -static struct mtd_partition kurobox_pro_nand_parts[] = {
> - {
> - .name = "uImage",
> - .offset = 0,
> - .size = SZ_4M,
> - }, {
> - .name = "rootfs",
> - .offset = SZ_4M,
> - .size = SZ_64M,
> - }, {
> - .name = "extra",
> - .offset = SZ_4M + SZ_64M,
> - .size = SZ_256M - (SZ_4M + SZ_64M),
> - },
> -};
> -
> -static struct resource kurobox_pro_nand_resource = {
> - .flags = IORESOURCE_MEM,
> - .start = KUROBOX_PRO_NAND_BASE,
> - .end = KUROBOX_PRO_NAND_BASE + KUROBOX_PRO_NAND_SIZE - 1,
> -};
> -
> -static struct orion_nand_data kurobox_pro_nand_data = {
> - .parts = kurobox_pro_nand_parts,
> - .nr_parts = ARRAY_SIZE(kurobox_pro_nand_parts),
> - .cle = 0,
> - .ale = 1,
> - .width = 8,
> -};
> -
> -static struct platform_device kurobox_pro_nand_flash = {
> - .name = "orion_nand",
> - .id = -1,
> - .dev = {
> - .platform_data = &kurobox_pro_nand_data,
> - },
> - .resource = &kurobox_pro_nand_resource,
> - .num_resources = 1,
> -};
> -
> -/*****************************************************************************
> - * 256KB NOR Flash on BOOT Device
> - ****************************************************************************/
> -
> -static struct physmap_flash_data kurobox_pro_nor_flash_data = {
> - .width = 1,
> -};
> -
> -static struct resource kurobox_pro_nor_flash_resource = {
> - .flags = IORESOURCE_MEM,
> - .start = KUROBOX_PRO_NOR_BOOT_BASE,
> - .end = KUROBOX_PRO_NOR_BOOT_BASE + KUROBOX_PRO_NOR_BOOT_SIZE - 1,
> -};
> -
> -static struct platform_device kurobox_pro_nor_flash = {
> - .name = "physmap-flash",
> - .id = 0,
> - .dev = {
> - .platform_data = &kurobox_pro_nor_flash_data,
> - },
> - .num_resources = 1,
> - .resource = &kurobox_pro_nor_flash_resource,
> -};
> -
> -/*****************************************************************************
> - * PCI
> - ****************************************************************************/
> -
> -static int __init kurobox_pro_pci_map_irq(const struct pci_dev *dev, u8 slot,
> - u8 pin)
> -{
> - int irq;
> -
> - /*
> - * Check for devices with hard-wired IRQs.
> - */
> - irq = orion5x_pci_map_irq(dev, slot, pin);
> - if (irq != -1)
> - return irq;
> -
> - /*
> - * PCI isn't used on the Kuro
> - */
> - return -1;
> -}
> -
> -static struct hw_pci kurobox_pro_pci __initdata = {
> - .nr_controllers = 2,
> - .setup = orion5x_pci_sys_setup,
> - .scan = orion5x_pci_sys_scan_bus,
> - .map_irq = kurobox_pro_pci_map_irq,
> -};
> -
> -static int __init kurobox_pro_pci_init(void)
> -{
> - if (machine_is_kurobox_pro()) {
> - orion5x_pci_disable();
> - pci_common_init(&kurobox_pro_pci);
> - }
> -
> - return 0;
> -}
> -
> -subsys_initcall(kurobox_pro_pci_init);
> -
> -/*****************************************************************************
> - * Ethernet
> - ****************************************************************************/
> -
> -static struct mv643xx_eth_platform_data kurobox_pro_eth_data = {
> - .phy_addr = MV643XX_ETH_PHY_ADDR(8),
> -};
> -
> -/*****************************************************************************
> - * RTC 5C372a on I2C bus
> - ****************************************************************************/
> -static struct i2c_board_info __initdata kurobox_pro_i2c_rtc = {
> - I2C_BOARD_INFO("rs5c372a", 0x32),
> -};
> -
> -/*****************************************************************************
> - * SATA
> - ****************************************************************************/
> -static struct mv_sata_platform_data kurobox_pro_sata_data = {
> - .n_ports = 2,
> -};
> -
> -/*****************************************************************************
> - * Kurobox Pro specific power off method via UART1-attached microcontroller
> - ****************************************************************************/
> -
> -#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
> -
> -static int kurobox_pro_miconread(unsigned char *buf, int count)
> -{
> - int i;
> - int timeout;
> -
> - for (i = 0; i < count; i++) {
> - timeout = 10;
> -
> - while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) {
> - if (--timeout == 0)
> - break;
> - udelay(1000);
> - }
> -
> - if (timeout == 0)
> - break;
> - buf[i] = readl(UART1_REG(RX));
> - }
> -
> - /* return read bytes */
> - return i;
> -}
> -
> -static int kurobox_pro_miconwrite(const unsigned char *buf, int count)
> -{
> - int i = 0;
> -
> - while (count--) {
> - while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE))
> - barrier();
> - writel(buf[i++], UART1_REG(TX));
> - }
> -
> - return 0;
> -}
> -
> -static int kurobox_pro_miconsend(const unsigned char *data, int count)
> -{
> - int i;
> - unsigned char checksum = 0;
> - unsigned char recv_buf[40];
> - unsigned char send_buf[40];
> - unsigned char correct_ack[3];
> - int retry = 2;
> -
> - /* Generate checksum */
> - for (i = 0; i < count; i++)
> - checksum -= data[i];
> -
> - do {
> - /* Send data */
> - kurobox_pro_miconwrite(data, count);
> -
> - /* send checksum */
> - kurobox_pro_miconwrite(&checksum, 1);
> -
> - if (kurobox_pro_miconread(recv_buf, sizeof(recv_buf)) <= 3) {
> - printk(KERN_ERR ">%s: receive failed.\n", __func__);
> -
> - /* send preamble to clear the receive buffer */
> - memset(&send_buf, 0xff, sizeof(send_buf));
> - kurobox_pro_miconwrite(send_buf, sizeof(send_buf));
> -
> - /* make dummy reads */
> - mdelay(100);
> - kurobox_pro_miconread(recv_buf, sizeof(recv_buf));
> - } else {
> - /* Generate expected ack */
> - correct_ack[0] = 0x01;
> - correct_ack[1] = data[1];
> - correct_ack[2] = 0x00;
> -
> - /* checksum Check */
> - if ((recv_buf[0] + recv_buf[1] + recv_buf[2] +
> - recv_buf[3]) & 0xFF) {
> - printk(KERN_ERR ">%s: Checksum Error : "
> - "Received data[%02x, %02x, %02x, %02x]"
> - "\n", __func__, recv_buf[0],
> - recv_buf[1], recv_buf[2], recv_buf[3]);
> - } else {
> - /* Check Received Data */
> - if (correct_ack[0] == recv_buf[0] &&
> - correct_ack[1] == recv_buf[1] &&
> - correct_ack[2] == recv_buf[2]) {
> - /* Interval for next command */
> - mdelay(10);
> -
> - /* Receive ACK */
> - return 0;
> - }
> - }
> - /* Received NAK or illegal Data */
> - printk(KERN_ERR ">%s: Error : NAK or Illegal Data "
> - "Received\n", __func__);
> - }
> - } while (retry--);
> -
> - /* Interval for next command */
> - mdelay(10);
> -
> - return -1;
> -}
> -
> -static void kurobox_pro_power_off(void)
> -{
> - const unsigned char watchdogkill[] = {0x01, 0x35, 0x00};
> - const unsigned char shutdownwait[] = {0x00, 0x0c};
> - const unsigned char poweroff[] = {0x00, 0x06};
> - /* 38400 baud divisor */
> - const unsigned divisor = ((orion5x_tclk + (8 * 38400)) / (16 * 38400));
> -
> - pr_info("%s: triggering power-off...\n", __func__);
> -
> - /* hijack uart1 and reset into sane state (38400,8n1,even parity) */
> - writel(0x83, UART1_REG(LCR));
> - writel(divisor & 0xff, UART1_REG(DLL));
> - writel((divisor >> 8) & 0xff, UART1_REG(DLM));
> - writel(0x1b, UART1_REG(LCR));
> - writel(0x00, UART1_REG(IER));
> - writel(0x07, UART1_REG(FCR));
> - writel(0x00, UART1_REG(MCR));
> -
> - /* Send the commands to shutdown the Kurobox Pro */
> - kurobox_pro_miconsend(watchdogkill, sizeof(watchdogkill)) ;
> - kurobox_pro_miconsend(shutdownwait, sizeof(shutdownwait)) ;
> - kurobox_pro_miconsend(poweroff, sizeof(poweroff));
> -}
> -
> -/*****************************************************************************
> - * General Setup
> - ****************************************************************************/
> -static unsigned int kurobox_pro_mpp_modes[] __initdata = {
> - MPP0_UNUSED,
> - MPP1_UNUSED,
> - MPP2_GPIO, /* GPIO Micon */
> - MPP3_GPIO, /* GPIO Rtc */
> - MPP4_UNUSED,
> - MPP5_UNUSED,
> - MPP6_NAND, /* NAND Flash REn */
> - MPP7_NAND, /* NAND Flash WEn */
> - MPP8_UNUSED,
> - MPP9_UNUSED,
> - MPP10_UNUSED,
> - MPP11_UNUSED,
> - MPP12_SATA_LED, /* SATA 0 presence */
> - MPP13_SATA_LED, /* SATA 1 presence */
> - MPP14_SATA_LED, /* SATA 0 active */
> - MPP15_SATA_LED, /* SATA 1 active */
> - MPP16_UART, /* UART1 RXD */
> - MPP17_UART, /* UART1 TXD */
> - MPP18_UART, /* UART1 CTSn */
> - MPP19_UART, /* UART1 RTSn */
> - 0,
> -};
> -
> -static void __init kurobox_pro_init(void)
> -{
> - /*
> - * Setup basic Orion functions. Need to be called early.
> - */
> - orion5x_init();
> -
> - orion5x_mpp_conf(kurobox_pro_mpp_modes);
> -
> - /*
> - * Configure peripherals.
> - */
> - orion5x_ehci0_init();
> - orion5x_ehci1_init();
> - orion5x_eth_init(&kurobox_pro_eth_data);
> - orion5x_i2c_init();
> - orion5x_sata_init(&kurobox_pro_sata_data);
> - orion5x_uart0_init();
> - orion5x_uart1_init();
> - orion5x_xor_init();
> -
> - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
> - ORION_MBUS_DEVBUS_BOOT_ATTR,
> - KUROBOX_PRO_NOR_BOOT_BASE,
> - KUROBOX_PRO_NOR_BOOT_SIZE);
> - platform_device_register(&kurobox_pro_nor_flash);
> -
> - if (machine_is_kurobox_pro()) {
> - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
> - ORION_MBUS_DEVBUS_ATTR(0),
> - KUROBOX_PRO_NAND_BASE,
> - KUROBOX_PRO_NAND_SIZE);
> - platform_device_register(&kurobox_pro_nand_flash);
> - }
> -
> - i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1);
> -
> - /* register Kurobox Pro specific power-off method */
> - register_platform_power_off(kurobox_pro_power_off);
> -}
> -
> -#ifdef CONFIG_MACH_KUROBOX_PRO
> -MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
> - /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
> - .atag_offset = 0x100,
> - .nr_irqs = ORION5X_NR_IRQS,
> - .init_machine = kurobox_pro_init,
> - .map_io = orion5x_map_io,
> - .init_early = orion5x_init_early,
> - .init_irq = orion5x_init_irq,
> - .init_time = orion5x_timer_init,
> - .fixup = tag_fixup_mem32,
> - .restart = orion5x_restart,
> -MACHINE_END
> -#endif
> -
> -#ifdef CONFIG_MACH_LINKSTATION_PRO
> -MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
> - /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
> - .atag_offset = 0x100,
> - .nr_irqs = ORION5X_NR_IRQS,
> - .init_machine = kurobox_pro_init,
> - .map_io = orion5x_map_io,
> - .init_early = orion5x_init_early,
> - .init_irq = orion5x_init_irq,
> - .init_time = orion5x_timer_init,
> - .fixup = tag_fixup_mem32,
> - .restart = orion5x_restart,
> -MACHINE_END
> -#endif
> diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
> deleted file mode 100644
> index b15fe5b7a0f9..000000000000
> --- a/arch/arm/mach-orion5x/mv2120-setup.c
> +++ /dev/null
> @@ -1,256 +0,0 @@
> -/*
> - * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
> - * Copyright (C) 2008 Martin Michlmayr <tbm@cyrius.com>
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU Lesser General Public License as
> - * published by the Free Software Foundation; either version 2 of the
> - * License, or (at your option) any later version.
> - */
> -#include <linux/gpio/legacy.h>
> -#include <linux/gpio/machine.h>
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/platform_device.h>
> -#include <linux/irq.h>
> -#include <linux/mtd/physmap.h>
> -#include <linux/mv643xx_eth.h>
> -#include <linux/leds.h>
> -#include <linux/gpio_keys.h>
> -#include <linux/input.h>
> -#include <linux/i2c.h>
> -#include <linux/ata_platform.h>
> -#include <asm/mach-types.h>
> -#include <asm/mach/arch.h>
> -#include "common.h"
> -#include "mpp.h"
> -#include "orion5x.h"
> -
> -#define MV2120_NOR_BOOT_BASE 0xf4000000
> -#define MV2120_NOR_BOOT_SIZE SZ_512K
> -
> -#define MV2120_GPIO_RTC_IRQ 3
> -#define MV2120_GPIO_KEY_RESET 17
> -#define MV2120_GPIO_KEY_POWER 18
> -#define MV2120_GPIO_POWER_OFF 19
> -
> -
> -/*****************************************************************************
> - * Ethernet
> - ****************************************************************************/
> -static struct mv643xx_eth_platform_data mv2120_eth_data = {
> - .phy_addr = MV643XX_ETH_PHY_ADDR(8),
> -};
> -
> -static struct mv_sata_platform_data mv2120_sata_data = {
> - .n_ports = 2,
> -};
> -
> -static struct mtd_partition mv2120_partitions[] = {
> - {
> - .name = "firmware",
> - .size = 0x00080000,
> - .offset = 0,
> - },
> -};
> -
> -static struct physmap_flash_data mv2120_nor_flash_data = {
> - .width = 1,
> - .parts = mv2120_partitions,
> - .nr_parts = ARRAY_SIZE(mv2120_partitions)
> -};
> -
> -static struct resource mv2120_nor_flash_resource = {
> - .flags = IORESOURCE_MEM,
> - .start = MV2120_NOR_BOOT_BASE,
> - .end = MV2120_NOR_BOOT_BASE + MV2120_NOR_BOOT_SIZE - 1,
> -};
> -
> -static struct platform_device mv2120_nor_flash = {
> - .name = "physmap-flash",
> - .id = 0,
> - .dev = {
> - .platform_data = &mv2120_nor_flash_data,
> - },
> - .resource = &mv2120_nor_flash_resource,
> - .num_resources = 1,
> -};
> -
> -static struct gpio_keys_button mv2120_buttons[] = {
> - {
> - .code = KEY_RESTART,
> - .gpio = MV2120_GPIO_KEY_RESET,
> - .desc = "reset",
> - .active_low = 1,
> - }, {
> - .code = KEY_POWER,
> - .gpio = MV2120_GPIO_KEY_POWER,
> - .desc = "power",
> - .active_low = 1,
> - },
> -};
> -
> -static struct gpio_keys_platform_data mv2120_button_data = {
> - .buttons = mv2120_buttons,
> - .nbuttons = ARRAY_SIZE(mv2120_buttons),
> -};
> -
> -static struct platform_device mv2120_button_device = {
> - .name = "gpio-keys",
> - .id = -1,
> - .num_resources = 0,
> - .dev = {
> - .platform_data = &mv2120_button_data,
> - },
> -};
> -
> -
> -/****************************************************************************
> - * General Setup
> - ****************************************************************************/
> -static unsigned int mv2120_mpp_modes[] __initdata = {
> - MPP0_GPIO, /* Sys status LED */
> - MPP1_GPIO, /* Sys error LED */
> - MPP2_GPIO, /* OverTemp interrupt */
> - MPP3_GPIO, /* RTC interrupt */
> - MPP4_GPIO, /* V_LED 5V */
> - MPP5_GPIO, /* V_LED 3.3V */
> - MPP6_UNUSED,
> - MPP7_UNUSED,
> - MPP8_GPIO, /* SATA 0 fail LED */
> - MPP9_GPIO, /* SATA 1 fail LED */
> - MPP10_UNUSED,
> - MPP11_UNUSED,
> - MPP12_SATA_LED, /* SATA 0 presence */
> - MPP13_SATA_LED, /* SATA 1 presence */
> - MPP14_SATA_LED, /* SATA 0 active */
> - MPP15_SATA_LED, /* SATA 1 active */
> - MPP16_UNUSED,
> - MPP17_GPIO, /* Reset button */
> - MPP18_GPIO, /* Power button */
> - MPP19_GPIO, /* Power off */
> - 0,
> -};
> -
> -static struct i2c_board_info __initdata mv2120_i2c_rtc = {
> - I2C_BOARD_INFO("pcf8563", 0x51),
> - .irq = 0,
> -};
> -
> -static struct gpio_led mv2120_led_pins[] = {
> - {
> - .name = "mv2120:blue:health",
> - },
> - {
> - .name = "mv2120:red:health",
> - },
> - {
> - .name = "mv2120:led:bright",
> - .default_trigger = "default-on",
> - },
> - {
> - .name = "mv2120:led:dimmed",
> - },
> - {
> - .name = "mv2120:red:sata0",
> - },
> - {
> - .name = "mv2120:red:sata1",
> - },
> -
> -};
> -
> -static struct gpiod_lookup_table mv2120_leds_gpio_table = {
> - .dev_id = "leds-gpio",
> - .table = {
> - GPIO_LOOKUP_IDX("orion_gpio0", 0, NULL,
> - 0, GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP_IDX("orion_gpio0", 1, NULL,
> - 1, GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP_IDX("orion_gpio0", 4, NULL,
> - 2, GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP_IDX("orion_gpio0", 5, NULL,
> - 3, GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP_IDX("orion_gpio0", 8, NULL,
> - 4, GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP_IDX("orion_gpio0", 9, NULL,
> - 5, GPIO_ACTIVE_LOW),
> - { },
> - },
> -};
> -
> -static struct gpio_led_platform_data mv2120_led_data = {
> - .leds = mv2120_led_pins,
> - .num_leds = ARRAY_SIZE(mv2120_led_pins),
> -};
> -
> -static struct platform_device mv2120_leds = {
> - .name = "leds-gpio",
> - .id = -1,
> - .dev = {
> - .platform_data = &mv2120_led_data,
> - }
> -};
> -
> -static void mv2120_power_off(void)
> -{
> - pr_info("%s: triggering power-off...\n", __func__);
> - gpio_set_value(MV2120_GPIO_POWER_OFF, 0);
> -}
> -
> -static void __init mv2120_init(void)
> -{
> - /* Setup basic Orion functions. Need to be called early. */
> - orion5x_init();
> -
> - orion5x_mpp_conf(mv2120_mpp_modes);
> -
> - /*
> - * Configure peripherals.
> - */
> - orion5x_ehci0_init();
> - orion5x_ehci1_init();
> - orion5x_eth_init(&mv2120_eth_data);
> - orion5x_i2c_init();
> - orion5x_sata_init(&mv2120_sata_data);
> - orion5x_uart0_init();
> - orion5x_xor_init();
> -
> - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
> - ORION_MBUS_DEVBUS_BOOT_ATTR,
> - MV2120_NOR_BOOT_BASE,
> - MV2120_NOR_BOOT_SIZE);
> - platform_device_register(&mv2120_nor_flash);
> -
> - platform_device_register(&mv2120_button_device);
> -
> - if (gpio_request(MV2120_GPIO_RTC_IRQ, "rtc") == 0) {
> - if (gpio_direction_input(MV2120_GPIO_RTC_IRQ) == 0)
> - mv2120_i2c_rtc.irq = gpio_to_irq(MV2120_GPIO_RTC_IRQ);
> - else
> - gpio_free(MV2120_GPIO_RTC_IRQ);
> - }
> - i2c_register_board_info(0, &mv2120_i2c_rtc, 1);
> - gpiod_add_lookup_table(&mv2120_leds_gpio_table);
> - platform_device_register(&mv2120_leds);
> -
> - /* register mv2120 specific power-off method */
> - if (gpio_request(MV2120_GPIO_POWER_OFF, "POWEROFF") != 0 ||
> - gpio_direction_output(MV2120_GPIO_POWER_OFF, 1) != 0)
> - pr_err("mv2120: failed to setup power-off GPIO\n");
> - register_platform_power_off(mv2120_power_off);
> -}
> -
> -/* Warning: HP uses a wrong mach-type (=526) in their bootloader */
> -MACHINE_START(MV2120, "HP Media Vault mv2120")
> - /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
> - .atag_offset = 0x100,
> - .nr_irqs = ORION5X_NR_IRQS,
> - .init_machine = mv2120_init,
> - .map_io = orion5x_map_io,
> - .init_early = orion5x_init_early,
> - .init_irq = orion5x_init_irq,
> - .init_time = orion5x_timer_init,
> - .fixup = tag_fixup_mem32,
> - .restart = orion5x_restart,
> -MACHINE_END
> diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
> deleted file mode 100644
> index f04571e79805..000000000000
> --- a/arch/arm/mach-orion5x/net2big-setup.c
> +++ /dev/null
> @@ -1,444 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * arch/arm/mach-orion5x/net2big-setup.c
> - *
> - * LaCie 2Big Network NAS setup
> - *
> - * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/platform_device.h>
> -#include <linux/mtd/physmap.h>
> -#include <linux/mv643xx_eth.h>
> -#include <linux/leds.h>
> -#include <linux/gpio_keys.h>
> -#include <linux/input.h>
> -#include <linux/i2c.h>
> -#include <linux/ata_platform.h>
> -#include <linux/gpio/legacy.h>
> -#include <linux/gpio/machine.h>
> -#include <linux/delay.h>
> -#include <asm/mach-types.h>
> -#include <asm/mach/arch.h>
> -#include <plat/orion-gpio.h>
> -#include "common.h"
> -#include "mpp.h"
> -#include "orion5x.h"
> -
> -/*****************************************************************************
> - * LaCie 2Big Network Info
> - ****************************************************************************/
> -
> -/*
> - * 512KB NOR flash Device bus boot chip select
> - */
> -
> -#define NET2BIG_NOR_BOOT_BASE 0xfff80000
> -#define NET2BIG_NOR_BOOT_SIZE SZ_512K
> -
> -/*****************************************************************************
> - * 512KB NOR Flash on Boot Device
> - ****************************************************************************/
> -
> -/*
> - * TODO: Check write support on flash MX29LV400CBTC-70G
> - */
> -
> -static struct mtd_partition net2big_partitions[] = {
> - {
> - .name = "Full512kb",
> - .size = MTDPART_SIZ_FULL,
> - .offset = 0x00000000,
> - .mask_flags = MTD_WRITEABLE,
> - },
> -};
> -
> -static struct physmap_flash_data net2big_nor_flash_data = {
> - .width = 1,
> - .parts = net2big_partitions,
> - .nr_parts = ARRAY_SIZE(net2big_partitions),
> -};
> -
> -static struct resource net2big_nor_flash_resource = {
> - .flags = IORESOURCE_MEM,
> - .start = NET2BIG_NOR_BOOT_BASE,
> - .end = NET2BIG_NOR_BOOT_BASE
> - + NET2BIG_NOR_BOOT_SIZE - 1,
> -};
> -
> -static struct platform_device net2big_nor_flash = {
> - .name = "physmap-flash",
> - .id = 0,
> - .dev = {
> - .platform_data = &net2big_nor_flash_data,
> - },
> - .num_resources = 1,
> - .resource = &net2big_nor_flash_resource,
> -};
> -
> -/*****************************************************************************
> - * Ethernet
> - ****************************************************************************/
> -
> -static struct mv643xx_eth_platform_data net2big_eth_data = {
> - .phy_addr = MV643XX_ETH_PHY_ADDR(8),
> -};
> -
> -/*****************************************************************************
> - * I2C devices
> - ****************************************************************************/
> -
> -/*
> - * i2c addr | chip | description
> - * 0x32 | Ricoh 5C372b | RTC
> - * 0x50 | HT24LC08 | eeprom (1kB)
> - */
> -static struct i2c_board_info __initdata net2big_i2c_devices[] = {
> - {
> - I2C_BOARD_INFO("rs5c372b", 0x32),
> - }, {
> - I2C_BOARD_INFO("24c08", 0x50),
> - },
> -};
> -
> -/*****************************************************************************
> - * SATA
> - ****************************************************************************/
> -
> -static struct mv_sata_platform_data net2big_sata_data = {
> - .n_ports = 2,
> -};
> -
> -#define NET2BIG_GPIO_SATA_POWER_REQ 19
> -#define NET2BIG_GPIO_SATA0_POWER 23
> -#define NET2BIG_GPIO_SATA1_POWER 25
> -
> -static void __init net2big_sata_power_init(void)
> -{
> - int err;
> -
> - /* Configure GPIOs over MPP max number. */
> - orion_gpio_set_valid(NET2BIG_GPIO_SATA0_POWER, 1);
> - orion_gpio_set_valid(NET2BIG_GPIO_SATA1_POWER, 1);
> -
> - err = gpio_request(NET2BIG_GPIO_SATA0_POWER, "SATA0 power status");
> - if (err == 0) {
> - err = gpio_direction_input(NET2BIG_GPIO_SATA0_POWER);
> - if (err)
> - gpio_free(NET2BIG_GPIO_SATA0_POWER);
> - }
> - if (err) {
> - pr_err("net2big: failed to setup SATA0 power GPIO\n");
> - return;
> - }
> -
> - err = gpio_request(NET2BIG_GPIO_SATA1_POWER, "SATA1 power status");
> - if (err == 0) {
> - err = gpio_direction_input(NET2BIG_GPIO_SATA1_POWER);
> - if (err)
> - gpio_free(NET2BIG_GPIO_SATA1_POWER);
> - }
> - if (err) {
> - pr_err("net2big: failed to setup SATA1 power GPIO\n");
> - goto err_free_1;
> - }
> -
> - err = gpio_request(NET2BIG_GPIO_SATA_POWER_REQ, "SATA power request");
> - if (err == 0) {
> - err = gpio_direction_output(NET2BIG_GPIO_SATA_POWER_REQ, 0);
> - if (err)
> - gpio_free(NET2BIG_GPIO_SATA_POWER_REQ);
> - }
> - if (err) {
> - pr_err("net2big: failed to setup SATA power request GPIO\n");
> - goto err_free_2;
> - }
> -
> - if (gpio_get_value(NET2BIG_GPIO_SATA0_POWER) &&
> - gpio_get_value(NET2BIG_GPIO_SATA1_POWER)) {
> - return;
> - }
> -
> - /*
> - * SATA power up on both disk is done by pulling high the CPLD power
> - * request line. The 300ms delay is related to the CPLD clock and is
> - * needed to be sure that the CPLD has take into account the low line
> - * status.
> - */
> - msleep(300);
> - gpio_set_value(NET2BIG_GPIO_SATA_POWER_REQ, 1);
> - pr_info("net2big: power up SATA hard disks\n");
> -
> - return;
> -
> -err_free_2:
> - gpio_free(NET2BIG_GPIO_SATA1_POWER);
> -err_free_1:
> - gpio_free(NET2BIG_GPIO_SATA0_POWER);
> -
> - return;
> -}
> -
> -/*****************************************************************************
> - * GPIO LEDs
> - ****************************************************************************/
> -
> -/*
> - * The power front LEDs (blue and red) and SATA red LEDs are controlled via a
> - * single GPIO line and are compatible with the leds-gpio driver.
> - *
> - * The SATA blue LEDs have some hardware blink capabilities which are detailed
> - * in the following array:
> - *
> - * SATAx blue LED | SATAx activity | LED state
> - * | |
> - * 0 | 0 | blink (rate 300ms)
> - * 1 | 0 | off
> - * ? | 1 | on
> - *
> - * Notes: The blue and the red front LED's can't be on at the same time.
> - * Blue LED have priority.
> - */
> -
> -#define NET2BIG_GPIO_PWR_RED_LED 6
> -#define NET2BIG_GPIO_PWR_BLUE_LED 16
> -#define NET2BIG_GPIO_PWR_LED_BLINK_STOP 7
> -
> -#define NET2BIG_GPIO_SATA0_RED_LED 11
> -#define NET2BIG_GPIO_SATA1_RED_LED 10
> -
> -#define NET2BIG_GPIO_SATA0_BLUE_LED 17
> -#define NET2BIG_GPIO_SATA1_BLUE_LED 13
> -
> -static struct gpio_led net2big_leds[] = {
> - {
> - .name = "net2big:red:power",
> - },
> - {
> - .name = "net2big:blue:power",
> - },
> - {
> - .name = "net2big:red:sata0",
> - },
> - {
> - .name = "net2big:red:sata1",
> - },
> -};
> -
> -static struct gpiod_lookup_table net2big_leds_gpio_table = {
> - .dev_id = "leds-gpio",
> - .table = {
> - GPIO_LOOKUP_IDX("orion_gpio0", NET2BIG_GPIO_PWR_RED_LED, NULL,
> - 0, GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP_IDX("orion_gpio0", NET2BIG_GPIO_PWR_BLUE_LED, NULL,
> - 1, GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP_IDX("orion_gpio0", NET2BIG_GPIO_SATA0_RED_LED, NULL,
> - 2, GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP_IDX("orion_gpio0", NET2BIG_GPIO_SATA1_RED_LED, NULL,
> - 3, GPIO_ACTIVE_HIGH),
> - { },
> - },
> -};
> -
> -static struct gpio_led_platform_data net2big_led_data = {
> - .num_leds = ARRAY_SIZE(net2big_leds),
> - .leds = net2big_leds,
> -};
> -
> -static struct platform_device net2big_gpio_leds = {
> - .name = "leds-gpio",
> - .id = -1,
> - .dev = {
> - .platform_data = &net2big_led_data,
> - },
> -};
> -
> -static void __init net2big_gpio_leds_init(void)
> -{
> - int err;
> -
> - /* Stop initial CPLD slow red/blue blinking on power LED. */
> - err = gpio_request(NET2BIG_GPIO_PWR_LED_BLINK_STOP,
> - "Power LED blink stop");
> - if (err == 0) {
> - err = gpio_direction_output(NET2BIG_GPIO_PWR_LED_BLINK_STOP, 1);
> - if (err)
> - gpio_free(NET2BIG_GPIO_PWR_LED_BLINK_STOP);
> - }
> - if (err)
> - pr_err("net2big: failed to setup power LED blink GPIO\n");
> -
> - /*
> - * Configure SATA0 and SATA1 blue LEDs to blink in relation with the
> - * hard disk activity.
> - */
> - err = gpio_request(NET2BIG_GPIO_SATA0_BLUE_LED,
> - "SATA0 blue LED control");
> - if (err == 0) {
> - err = gpio_direction_output(NET2BIG_GPIO_SATA0_BLUE_LED, 1);
> - if (err)
> - gpio_free(NET2BIG_GPIO_SATA0_BLUE_LED);
> - }
> - if (err)
> - pr_err("net2big: failed to setup SATA0 blue LED GPIO\n");
> -
> - err = gpio_request(NET2BIG_GPIO_SATA1_BLUE_LED,
> - "SATA1 blue LED control");
> - if (err == 0) {
> - err = gpio_direction_output(NET2BIG_GPIO_SATA1_BLUE_LED, 1);
> - if (err)
> - gpio_free(NET2BIG_GPIO_SATA1_BLUE_LED);
> - }
> - if (err)
> - pr_err("net2big: failed to setup SATA1 blue LED GPIO\n");
> -
> - gpiod_add_lookup_table(&net2big_leds_gpio_table);
> - platform_device_register(&net2big_gpio_leds);
> -}
> -
> -/****************************************************************************
> - * GPIO keys
> - ****************************************************************************/
> -
> -#define NET2BIG_GPIO_PUSH_BUTTON 18
> -#define NET2BIG_GPIO_POWER_SWITCH_ON 8
> -#define NET2BIG_GPIO_POWER_SWITCH_OFF 9
> -
> -#define NET2BIG_SWITCH_POWER_ON 0x1
> -#define NET2BIG_SWITCH_POWER_OFF 0x2
> -
> -static struct gpio_keys_button net2big_buttons[] = {
> - {
> - .type = EV_SW,
> - .code = NET2BIG_SWITCH_POWER_OFF,
> - .gpio = NET2BIG_GPIO_POWER_SWITCH_OFF,
> - .desc = "Power rocker switch (auto|off)",
> - .active_low = 0,
> - },
> - {
> - .type = EV_SW,
> - .code = NET2BIG_SWITCH_POWER_ON,
> - .gpio = NET2BIG_GPIO_POWER_SWITCH_ON,
> - .desc = "Power rocker switch (on|auto)",
> - .active_low = 0,
> - },
> - {
> - .type = EV_KEY,
> - .code = KEY_POWER,
> - .gpio = NET2BIG_GPIO_PUSH_BUTTON,
> - .desc = "Front Push Button",
> - .active_low = 0,
> - },
> -};
> -
> -static struct gpio_keys_platform_data net2big_button_data = {
> - .buttons = net2big_buttons,
> - .nbuttons = ARRAY_SIZE(net2big_buttons),
> -};
> -
> -static struct platform_device net2big_gpio_buttons = {
> - .name = "gpio-keys",
> - .id = -1,
> - .dev = {
> - .platform_data = &net2big_button_data,
> - },
> -};
> -
> -/*****************************************************************************
> - * General Setup
> - ****************************************************************************/
> -
> -static unsigned int net2big_mpp_modes[] __initdata = {
> - MPP0_GPIO, /* Raid mode (bit 0) */
> - MPP1_GPIO, /* USB port 2 fuse (0 = Fail, 1 = Ok) */
> - MPP2_GPIO, /* Raid mode (bit 1) */
> - MPP3_GPIO, /* Board ID (bit 0) */
> - MPP4_GPIO, /* Fan activity (0 = Off, 1 = On) */
> - MPP5_GPIO, /* Fan fail detection */
> - MPP6_GPIO, /* Red front LED (0 = Off, 1 = On) */
> - MPP7_GPIO, /* Disable initial blinking on front LED */
> - MPP8_GPIO, /* Rear power switch (on|auto) */
> - MPP9_GPIO, /* Rear power switch (auto|off) */
> - MPP10_GPIO, /* SATA 1 red LED (0 = Off, 1 = On) */
> - MPP11_GPIO, /* SATA 0 red LED (0 = Off, 1 = On) */
> - MPP12_GPIO, /* Board ID (bit 1) */
> - MPP13_GPIO, /* SATA 1 blue LED blink control */
> - MPP14_SATA_LED,
> - MPP15_SATA_LED,
> - MPP16_GPIO, /* Blue front LED control */
> - MPP17_GPIO, /* SATA 0 blue LED blink control */
> - MPP18_GPIO, /* Front button (0 = Released, 1 = Pushed ) */
> - MPP19_GPIO, /* SATA{0,1} power On/Off request */
> - 0,
> - /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
> - /* 23: SATA 0 power status */
> - /* 24: Board power off */
> - /* 25: SATA 1 power status */
> -};
> -
> -#define NET2BIG_GPIO_POWER_OFF 24
> -
> -static void net2big_power_off(void)
> -{
> - gpio_set_value(NET2BIG_GPIO_POWER_OFF, 1);
> -}
> -
> -static void __init net2big_init(void)
> -{
> - /*
> - * Setup basic Orion functions. Need to be called early.
> - */
> - orion5x_init();
> -
> - orion5x_mpp_conf(net2big_mpp_modes);
> -
> - /*
> - * Configure peripherals.
> - */
> - orion5x_ehci0_init();
> - orion5x_ehci1_init();
> - orion5x_eth_init(&net2big_eth_data);
> - orion5x_i2c_init();
> - orion5x_uart0_init();
> - orion5x_xor_init();
> -
> - net2big_sata_power_init();
> - orion5x_sata_init(&net2big_sata_data);
> -
> - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
> - ORION_MBUS_DEVBUS_BOOT_ATTR,
> - NET2BIG_NOR_BOOT_BASE,
> - NET2BIG_NOR_BOOT_SIZE);
> - platform_device_register(&net2big_nor_flash);
> -
> - platform_device_register(&net2big_gpio_buttons);
> - net2big_gpio_leds_init();
> -
> - i2c_register_board_info(0, net2big_i2c_devices,
> - ARRAY_SIZE(net2big_i2c_devices));
> -
> - orion_gpio_set_valid(NET2BIG_GPIO_POWER_OFF, 1);
> -
> - if (gpio_request(NET2BIG_GPIO_POWER_OFF, "power-off") == 0 &&
> - gpio_direction_output(NET2BIG_GPIO_POWER_OFF, 0) == 0)
> - register_platform_power_off(net2big_power_off);
> - else
> - pr_err("net2big: failed to configure power-off GPIO\n");
> -
> - pr_notice("net2big: Flash writing is not yet supported.\n");
> -}
> -
> -/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
> -MACHINE_START(NET2BIG, "LaCie 2Big Network")
> - .atag_offset = 0x100,
> - .nr_irqs = ORION5X_NR_IRQS,
> - .init_machine = net2big_init,
> - .map_io = orion5x_map_io,
> - .init_early = orion5x_init_early,
> - .init_irq = orion5x_init_irq,
> - .init_time = orion5x_timer_init,
> - .fixup = tag_fixup_mem32,
> - .restart = orion5x_restart,
> -MACHINE_END
> diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
> index 06f5320036b1..3d1e6ad0e14b 100644
> --- a/arch/arm/mach-orion5x/pci.c
> +++ b/arch/arm/mach-orion5x/pci.c
> @@ -15,7 +15,6 @@
> #include <asm/irq.h>
> #include <asm/mach/pci.h>
> #include <plat/pcie.h>
> -#include <plat/addr-map.h>
> #include "common.h"
> #include "orion5x.h"
>
> diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
> deleted file mode 100644
> index c3db3376950a..000000000000
> --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
> +++ /dev/null
> @@ -1,366 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later
> -/*
> - * Buffalo Terastation Pro II/Live Board Setup
> - *
> - * Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com>
> - */
> -#include <linux/gpio/legacy.h>
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/platform_device.h>
> -#include <linux/pci.h>
> -#include <linux/irq.h>
> -#include <linux/delay.h>
> -#include <linux/mtd/physmap.h>
> -#include <linux/mv643xx_eth.h>
> -#include <linux/i2c.h>
> -#include <linux/serial_reg.h>
> -#include <asm/mach-types.h>
> -#include <asm/mach/arch.h>
> -#include <asm/mach/pci.h>
> -#include "common.h"
> -#include "mpp.h"
> -#include "orion5x.h"
> -
> -/*****************************************************************************
> - * Terastation Pro 2/Live Info
> - ****************************************************************************/
> -
> -/*
> - * Terastation Pro 2 hardware :
> - * - Marvell 88F5281-D0
> - * - Marvell 88SX6042 SATA controller (PCI)
> - * - Marvell 88E1118 Gigabit Ethernet PHY
> - * - 256KB NOR flash
> - * - 128MB of DDR RAM
> - * - PCIe port (not equipped)
> - */
> -
> -/*
> - * 256K NOR flash Device bus boot chip select
> - */
> -
> -#define TSP2_NOR_BOOT_BASE 0xf4000000
> -#define TSP2_NOR_BOOT_SIZE SZ_256K
> -
> -/*****************************************************************************
> - * 256KB NOR Flash on BOOT Device
> - ****************************************************************************/
> -
> -static struct physmap_flash_data tsp2_nor_flash_data = {
> - .width = 1,
> -};
> -
> -static struct resource tsp2_nor_flash_resource = {
> - .flags = IORESOURCE_MEM,
> - .start = TSP2_NOR_BOOT_BASE,
> - .end = TSP2_NOR_BOOT_BASE + TSP2_NOR_BOOT_SIZE - 1,
> -};
> -
> -static struct platform_device tsp2_nor_flash = {
> - .name = "physmap-flash",
> - .id = 0,
> - .dev = {
> - .platform_data = &tsp2_nor_flash_data,
> - },
> - .num_resources = 1,
> - .resource = &tsp2_nor_flash_resource,
> -};
> -
> -/*****************************************************************************
> - * PCI
> - ****************************************************************************/
> -#define TSP2_PCI_SLOT0_OFFS 7
> -#define TSP2_PCI_SLOT0_IRQ_PIN 11
> -
> -static void __init tsp2_pci_preinit(void)
> -{
> - int pin;
> -
> - /*
> - * Configure PCI GPIO IRQ pins
> - */
> - pin = TSP2_PCI_SLOT0_IRQ_PIN;
> - if (gpio_request(pin, "PCI Int1") == 0) {
> - if (gpio_direction_input(pin) == 0) {
> - irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
> - } else {
> - printk(KERN_ERR "tsp2_pci_preinit failed "
> - "to set_irq_type pin %d\n", pin);
> - gpio_free(pin);
> - }
> - } else {
> - printk(KERN_ERR "tsp2_pci_preinit failed to "
> - "gpio_request %d\n", pin);
> - }
> -}
> -
> -static int __init tsp2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
> -{
> - int irq;
> -
> - /*
> - * Check for devices with hard-wired IRQs.
> - */
> - irq = orion5x_pci_map_irq(dev, slot, pin);
> - if (irq != -1)
> - return irq;
> -
> - /*
> - * PCI IRQs are connected via GPIOs.
> - */
> - if (slot == TSP2_PCI_SLOT0_OFFS)
> - return gpio_to_irq(TSP2_PCI_SLOT0_IRQ_PIN);
> -
> - return -1;
> -}
> -
> -static struct hw_pci tsp2_pci __initdata = {
> - .nr_controllers = 2,
> - .preinit = tsp2_pci_preinit,
> - .setup = orion5x_pci_sys_setup,
> - .scan = orion5x_pci_sys_scan_bus,
> - .map_irq = tsp2_pci_map_irq,
> -};
> -
> -static int __init tsp2_pci_init(void)
> -{
> - if (machine_is_terastation_pro2())
> - pci_common_init(&tsp2_pci);
> -
> - return 0;
> -}
> -
> -subsys_initcall(tsp2_pci_init);
> -
> -/*****************************************************************************
> - * Ethernet
> - ****************************************************************************/
> -
> -static struct mv643xx_eth_platform_data tsp2_eth_data = {
> - .phy_addr = 0,
> -};
> -
> -/*****************************************************************************
> - * RTC 5C372a on I2C bus
> - ****************************************************************************/
> -
> -#define TSP2_RTC_GPIO 9
> -
> -static struct i2c_board_info __initdata tsp2_i2c_rtc = {
> - I2C_BOARD_INFO("rs5c372a", 0x32),
> -};
> -
> -/*****************************************************************************
> - * Terastation Pro II specific power off method via UART1-attached
> - * microcontroller
> - ****************************************************************************/
> -
> -#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
> -
> -static int tsp2_miconread(unsigned char *buf, int count)
> -{
> - int i;
> - int timeout;
> -
> - for (i = 0; i < count; i++) {
> - timeout = 10;
> -
> - while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) {
> - if (--timeout == 0)
> - break;
> - udelay(1000);
> - }
> -
> - if (timeout == 0)
> - break;
> - buf[i] = readl(UART1_REG(RX));
> - }
> -
> - /* return read bytes */
> - return i;
> -}
> -
> -static int tsp2_miconwrite(const unsigned char *buf, int count)
> -{
> - int i = 0;
> -
> - while (count--) {
> - while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE))
> - barrier();
> - writel(buf[i++], UART1_REG(TX));
> - }
> -
> - return 0;
> -}
> -
> -static int tsp2_miconsend(const unsigned char *data, int count)
> -{
> - int i;
> - unsigned char checksum = 0;
> - unsigned char recv_buf[40];
> - unsigned char send_buf[40];
> - unsigned char correct_ack[3];
> - int retry = 2;
> -
> - /* Generate checksum */
> - for (i = 0; i < count; i++)
> - checksum -= data[i];
> -
> - do {
> - /* Send data */
> - tsp2_miconwrite(data, count);
> -
> - /* send checksum */
> - tsp2_miconwrite(&checksum, 1);
> -
> - if (tsp2_miconread(recv_buf, sizeof(recv_buf)) <= 3) {
> - printk(KERN_ERR ">%s: receive failed.\n", __func__);
> -
> - /* send preamble to clear the receive buffer */
> - memset(&send_buf, 0xff, sizeof(send_buf));
> - tsp2_miconwrite(send_buf, sizeof(send_buf));
> -
> - /* make dummy reads */
> - mdelay(100);
> - tsp2_miconread(recv_buf, sizeof(recv_buf));
> - } else {
> - /* Generate expected ack */
> - correct_ack[0] = 0x01;
> - correct_ack[1] = data[1];
> - correct_ack[2] = 0x00;
> -
> - /* checksum Check */
> - if ((recv_buf[0] + recv_buf[1] + recv_buf[2] +
> - recv_buf[3]) & 0xFF) {
> - printk(KERN_ERR ">%s: Checksum Error : "
> - "Received data[%02x, %02x, %02x, %02x]"
> - "\n", __func__, recv_buf[0],
> - recv_buf[1], recv_buf[2], recv_buf[3]);
> - } else {
> - /* Check Received Data */
> - if (correct_ack[0] == recv_buf[0] &&
> - correct_ack[1] == recv_buf[1] &&
> - correct_ack[2] == recv_buf[2]) {
> - /* Interval for next command */
> - mdelay(10);
> -
> - /* Receive ACK */
> - return 0;
> - }
> - }
> - /* Received NAK or illegal Data */
> - printk(KERN_ERR ">%s: Error : NAK or Illegal Data "
> - "Received\n", __func__);
> - }
> - } while (retry--);
> -
> - /* Interval for next command */
> - mdelay(10);
> -
> - return -1;
> -}
> -
> -static void tsp2_power_off(void)
> -{
> - const unsigned char watchdogkill[] = {0x01, 0x35, 0x00};
> - const unsigned char shutdownwait[] = {0x00, 0x0c};
> - const unsigned char poweroff[] = {0x00, 0x06};
> - /* 38400 baud divisor */
> - const unsigned divisor = ((orion5x_tclk + (8 * 38400)) / (16 * 38400));
> -
> - pr_info("%s: triggering power-off...\n", __func__);
> -
> - /* hijack uart1 and reset into sane state (38400,8n1,even parity) */
> - writel(0x83, UART1_REG(LCR));
> - writel(divisor & 0xff, UART1_REG(DLL));
> - writel((divisor >> 8) & 0xff, UART1_REG(DLM));
> - writel(0x1b, UART1_REG(LCR));
> - writel(0x00, UART1_REG(IER));
> - writel(0x07, UART1_REG(FCR));
> - writel(0x00, UART1_REG(MCR));
> -
> - /* Send the commands to shutdown the Terastation Pro II */
> - tsp2_miconsend(watchdogkill, sizeof(watchdogkill)) ;
> - tsp2_miconsend(shutdownwait, sizeof(shutdownwait)) ;
> - tsp2_miconsend(poweroff, sizeof(poweroff));
> -}
> -
> -/*****************************************************************************
> - * General Setup
> - ****************************************************************************/
> -static unsigned int tsp2_mpp_modes[] __initdata = {
> - MPP0_PCIE_RST_OUTn,
> - MPP1_UNUSED,
> - MPP2_UNUSED,
> - MPP3_UNUSED,
> - MPP4_NAND, /* BOOT NAND Flash REn */
> - MPP5_NAND, /* BOOT NAND Flash WEn */
> - MPP6_NAND, /* BOOT NAND Flash HREn[0] */
> - MPP7_NAND, /* BOOT NAND Flash WEn[0] */
> - MPP8_GPIO, /* MICON int */
> - MPP9_GPIO, /* RTC int */
> - MPP10_UNUSED,
> - MPP11_GPIO, /* PCI Int A */
> - MPP12_UNUSED,
> - MPP13_GPIO, /* UPS on UART0 enable */
> - MPP14_GPIO, /* UPS low battery detection */
> - MPP15_UNUSED,
> - MPP16_UART, /* UART1 RXD */
> - MPP17_UART, /* UART1 TXD */
> - MPP18_UART, /* UART1 CTSn */
> - MPP19_UART, /* UART1 RTSn */
> - 0,
> -};
> -
> -static void __init tsp2_init(void)
> -{
> - /*
> - * Setup basic Orion functions. Need to be called early.
> - */
> - orion5x_init();
> -
> - orion5x_mpp_conf(tsp2_mpp_modes);
> -
> - /*
> - * Configure peripherals.
> - */
> - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
> - ORION_MBUS_DEVBUS_BOOT_ATTR,
> - TSP2_NOR_BOOT_BASE,
> - TSP2_NOR_BOOT_SIZE);
> - platform_device_register(&tsp2_nor_flash);
> -
> - orion5x_ehci0_init();
> - orion5x_eth_init(&tsp2_eth_data);
> - orion5x_i2c_init();
> - orion5x_uart0_init();
> - orion5x_uart1_init();
> -
> - /* Get RTC IRQ and register the chip */
> - if (gpio_request(TSP2_RTC_GPIO, "rtc") == 0) {
> - if (gpio_direction_input(TSP2_RTC_GPIO) == 0)
> - tsp2_i2c_rtc.irq = gpio_to_irq(TSP2_RTC_GPIO);
> - else
> - gpio_free(TSP2_RTC_GPIO);
> - }
> - if (tsp2_i2c_rtc.irq == 0)
> - pr_warn("tsp2_init: failed to get RTC IRQ\n");
> - i2c_register_board_info(0, &tsp2_i2c_rtc, 1);
> -
> - /* register Terastation Pro II specific power-off method */
> - register_platform_power_off(tsp2_power_off);
> -}
> -
> -MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live")
> - /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */
> - .atag_offset = 0x100,
> - .nr_irqs = ORION5X_NR_IRQS,
> - .init_machine = tsp2_init,
> - .map_io = orion5x_map_io,
> - .init_early = orion5x_init_early,
> - .init_irq = orion5x_init_irq,
> - .init_time = orion5x_timer_init,
> - .fixup = tag_fixup_mem32,
> - .restart = orion5x_restart,
> -MACHINE_END
> diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
> deleted file mode 100644
> index 25cd50306c65..000000000000
> --- a/arch/arm/mach-orion5x/ts209-setup.c
> +++ /dev/null
> @@ -1,331 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later
> -/*
> - * QNAP TS-109/TS-209 Board Setup
> - *
> - * Maintainer: Byron Bradley <byron.bbradley@gmail.com>
> - */
> -#include <linux/gpio/legacy.h>
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/platform_device.h>
> -#include <linux/pci.h>
> -#include <linux/irq.h>
> -#include <linux/mtd/physmap.h>
> -#include <linux/mtd/rawnand.h>
> -#include <linux/mv643xx_eth.h>
> -#include <linux/gpio_keys.h>
> -#include <linux/input.h>
> -#include <linux/i2c.h>
> -#include <linux/serial_reg.h>
> -#include <linux/ata_platform.h>
> -#include <asm/mach-types.h>
> -#include <asm/mach/arch.h>
> -#include <asm/mach/pci.h>
> -#include "common.h"
> -#include "mpp.h"
> -#include "orion5x.h"
> -#include "tsx09-common.h"
> -
> -#define QNAP_TS209_NOR_BOOT_BASE 0xf4000000
> -#define QNAP_TS209_NOR_BOOT_SIZE SZ_8M
> -
> -/****************************************************************************
> - * 8MiB NOR flash. The struct mtd_partition is not in the same order as the
> - * partitions on the device because we want to keep compatibility with
> - * existing QNAP firmware.
> - *
> - * Layout as used by QNAP:
> - * [2] 0x00000000-0x00200000 : "Kernel"
> - * [3] 0x00200000-0x00600000 : "RootFS1"
> - * [4] 0x00600000-0x00700000 : "RootFS2"
> - * [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
> - * [5] 0x00760000-0x00780000 : "U-Boot Config"
> - * [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
> - ***************************************************************************/
> -static struct mtd_partition qnap_ts209_partitions[] = {
> - {
> - .name = "U-Boot",
> - .size = 0x00080000,
> - .offset = 0x00780000,
> - .mask_flags = MTD_WRITEABLE,
> - }, {
> - .name = "Kernel",
> - .size = 0x00200000,
> - .offset = 0,
> - }, {
> - .name = "RootFS1",
> - .size = 0x00400000,
> - .offset = 0x00200000,
> - }, {
> - .name = "RootFS2",
> - .size = 0x00100000,
> - .offset = 0x00600000,
> - }, {
> - .name = "U-Boot Config",
> - .size = 0x00020000,
> - .offset = 0x00760000,
> - }, {
> - .name = "NAS Config",
> - .size = 0x00060000,
> - .offset = 0x00700000,
> - .mask_flags = MTD_WRITEABLE,
> - },
> -};
> -
> -static struct physmap_flash_data qnap_ts209_nor_flash_data = {
> - .width = 1,
> - .parts = qnap_ts209_partitions,
> - .nr_parts = ARRAY_SIZE(qnap_ts209_partitions)
> -};
> -
> -static struct resource qnap_ts209_nor_flash_resource = {
> - .flags = IORESOURCE_MEM,
> - .start = QNAP_TS209_NOR_BOOT_BASE,
> - .end = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1,
> -};
> -
> -static struct platform_device qnap_ts209_nor_flash = {
> - .name = "physmap-flash",
> - .id = 0,
> - .dev = {
> - .platform_data = &qnap_ts209_nor_flash_data,
> - },
> - .resource = &qnap_ts209_nor_flash_resource,
> - .num_resources = 1,
> -};
> -
> -/*****************************************************************************
> - * PCI
> - ****************************************************************************/
> -
> -#define QNAP_TS209_PCI_SLOT0_OFFS 7
> -#define QNAP_TS209_PCI_SLOT0_IRQ_PIN 6
> -#define QNAP_TS209_PCI_SLOT1_IRQ_PIN 7
> -
> -static void __init qnap_ts209_pci_preinit(void)
> -{
> - int pin;
> -
> - /*
> - * Configure PCI GPIO IRQ pins
> - */
> - pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN;
> - if (gpio_request(pin, "PCI Int1") == 0) {
> - if (gpio_direction_input(pin) == 0) {
> - irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
> - } else {
> - printk(KERN_ERR "qnap_ts209_pci_preinit failed to "
> - "set_irq_type pin %d\n", pin);
> - gpio_free(pin);
> - }
> - } else {
> - printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request "
> - "%d\n", pin);
> - }
> -
> - pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN;
> - if (gpio_request(pin, "PCI Int2") == 0) {
> - if (gpio_direction_input(pin) == 0) {
> - irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
> - } else {
> - printk(KERN_ERR "qnap_ts209_pci_preinit failed "
> - "to set_irq_type pin %d\n", pin);
> - gpio_free(pin);
> - }
> - } else {
> - printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request "
> - "%d\n", pin);
> - }
> -}
> -
> -static int __init qnap_ts209_pci_map_irq(const struct pci_dev *dev, u8 slot,
> - u8 pin)
> -{
> - int irq;
> -
> - /*
> - * Check for devices with hard-wired IRQs.
> - */
> - irq = orion5x_pci_map_irq(dev, slot, pin);
> - if (irq != -1)
> - return irq;
> -
> - /*
> - * PCI IRQs are connected via GPIOs.
> - */
> - switch (slot - QNAP_TS209_PCI_SLOT0_OFFS) {
> - case 0:
> - return gpio_to_irq(QNAP_TS209_PCI_SLOT0_IRQ_PIN);
> - case 1:
> - return gpio_to_irq(QNAP_TS209_PCI_SLOT1_IRQ_PIN);
> - default:
> - return -1;
> - }
> -}
> -
> -static struct hw_pci qnap_ts209_pci __initdata = {
> - .nr_controllers = 2,
> - .preinit = qnap_ts209_pci_preinit,
> - .setup = orion5x_pci_sys_setup,
> - .scan = orion5x_pci_sys_scan_bus,
> - .map_irq = qnap_ts209_pci_map_irq,
> -};
> -
> -static int __init qnap_ts209_pci_init(void)
> -{
> - if (machine_is_ts209())
> - pci_common_init(&qnap_ts209_pci);
> -
> - return 0;
> -}
> -
> -subsys_initcall(qnap_ts209_pci_init);
> -
> -/*****************************************************************************
> - * RTC S35390A on I2C bus
> - ****************************************************************************/
> -
> -#define TS209_RTC_GPIO 3
> -
> -static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = {
> - I2C_BOARD_INFO("s35390a", 0x30),
> - .irq = 0,
> -};
> -
> -/****************************************************************************
> - * GPIO Attached Keys
> - * Power button is attached to the PIC microcontroller
> - ****************************************************************************/
> -
> -#define QNAP_TS209_GPIO_KEY_MEDIA 1
> -#define QNAP_TS209_GPIO_KEY_RESET 2
> -
> -static struct gpio_keys_button qnap_ts209_buttons[] = {
> - {
> - .code = KEY_COPY,
> - .gpio = QNAP_TS209_GPIO_KEY_MEDIA,
> - .desc = "USB Copy Button",
> - .active_low = 1,
> - }, {
> - .code = KEY_RESTART,
> - .gpio = QNAP_TS209_GPIO_KEY_RESET,
> - .desc = "Reset Button",
> - .active_low = 1,
> - },
> -};
> -
> -static struct gpio_keys_platform_data qnap_ts209_button_data = {
> - .buttons = qnap_ts209_buttons,
> - .nbuttons = ARRAY_SIZE(qnap_ts209_buttons),
> -};
> -
> -static struct platform_device qnap_ts209_button_device = {
> - .name = "gpio-keys",
> - .id = -1,
> - .num_resources = 0,
> - .dev = {
> - .platform_data = &qnap_ts209_button_data,
> - },
> -};
> -
> -/*****************************************************************************
> - * SATA
> - ****************************************************************************/
> -static struct mv_sata_platform_data qnap_ts209_sata_data = {
> - .n_ports = 2,
> -};
> -
> -/*****************************************************************************
> -
> - * General Setup
> - ****************************************************************************/
> -static unsigned int ts209_mpp_modes[] __initdata = {
> - MPP0_UNUSED,
> - MPP1_GPIO, /* USB copy button */
> - MPP2_GPIO, /* Load defaults button */
> - MPP3_GPIO, /* GPIO RTC */
> - MPP4_UNUSED,
> - MPP5_UNUSED,
> - MPP6_GPIO, /* PCI Int A */
> - MPP7_GPIO, /* PCI Int B */
> - MPP8_UNUSED,
> - MPP9_UNUSED,
> - MPP10_UNUSED,
> - MPP11_UNUSED,
> - MPP12_SATA_LED, /* SATA 0 presence */
> - MPP13_SATA_LED, /* SATA 1 presence */
> - MPP14_SATA_LED, /* SATA 0 active */
> - MPP15_SATA_LED, /* SATA 1 active */
> - MPP16_UART, /* UART1 RXD */
> - MPP17_UART, /* UART1 TXD */
> - MPP18_GPIO, /* SW_RST */
> - MPP19_UNUSED,
> - 0,
> -};
> -
> -static void __init qnap_ts209_init(void)
> -{
> - /*
> - * Setup basic Orion functions. Need to be called early.
> - */
> - orion5x_init();
> -
> - orion5x_mpp_conf(ts209_mpp_modes);
> -
> - /*
> - * MPP[20] PCI clock 0
> - * MPP[21] PCI clock 1
> - * MPP[22] USB 0 over current
> - * MPP[23-25] Reserved
> - */
> -
> - /*
> - * Configure peripherals.
> - */
> - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
> - ORION_MBUS_DEVBUS_BOOT_ATTR,
> - QNAP_TS209_NOR_BOOT_BASE,
> - QNAP_TS209_NOR_BOOT_SIZE);
> - platform_device_register(&qnap_ts209_nor_flash);
> -
> - orion5x_ehci0_init();
> - orion5x_ehci1_init();
> - qnap_tsx09_find_mac_addr(QNAP_TS209_NOR_BOOT_BASE +
> - qnap_ts209_partitions[5].offset,
> - qnap_ts209_partitions[5].size);
> - orion5x_eth_init(&qnap_tsx09_eth_data);
> - orion5x_i2c_init();
> - orion5x_sata_init(&qnap_ts209_sata_data);
> - orion5x_uart0_init();
> - orion5x_uart1_init();
> - orion5x_xor_init();
> -
> - platform_device_register(&qnap_ts209_button_device);
> -
> - /* Get RTC IRQ and register the chip */
> - if (gpio_request(TS209_RTC_GPIO, "rtc") == 0) {
> - if (gpio_direction_input(TS209_RTC_GPIO) == 0)
> - qnap_ts209_i2c_rtc.irq = gpio_to_irq(TS209_RTC_GPIO);
> - else
> - gpio_free(TS209_RTC_GPIO);
> - }
> - if (qnap_ts209_i2c_rtc.irq == 0)
> - pr_warn("qnap_ts209_init: failed to get RTC IRQ\n");
> - i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
> -
> - /* register tsx09 specific power-off method */
> - register_platform_power_off(qnap_tsx09_power_off);
> -}
> -
> -MACHINE_START(TS209, "QNAP TS-109/TS-209")
> - /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
> - .atag_offset = 0x100,
> - .nr_irqs = ORION5X_NR_IRQS,
> - .init_machine = qnap_ts209_init,
> - .map_io = orion5x_map_io,
> - .init_early = orion5x_init_early,
> - .init_irq = orion5x_init_irq,
> - .init_time = orion5x_timer_init,
> - .fixup = tag_fixup_mem32,
> - .restart = orion5x_restart,
> -MACHINE_END
> diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
> deleted file mode 100644
> index f92acef0b45f..000000000000
> --- a/arch/arm/mach-orion5x/ts409-setup.c
> +++ /dev/null
> @@ -1,329 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later
> -/*
> - * QNAP TS-409 Board Setup
> - *
> - * Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com>
> - *
> - * Copyright (C) 2008 Sylver Bruneau <sylver.bruneau@gmail.com>
> - * Copyright (C) 2008 Martin Michlmayr <tbm@cyrius.com>
> - */
> -#include <linux/gpio/legacy.h>
> -#include <linux/gpio/machine.h>
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/platform_device.h>
> -#include <linux/pci.h>
> -#include <linux/irq.h>
> -#include <linux/mtd/physmap.h>
> -#include <linux/mv643xx_eth.h>
> -#include <linux/leds.h>
> -#include <linux/gpio_keys.h>
> -#include <linux/input.h>
> -#include <linux/i2c.h>
> -#include <linux/serial_reg.h>
> -#include <asm/mach-types.h>
> -#include <asm/mach/arch.h>
> -#include <asm/mach/pci.h>
> -#include "common.h"
> -#include "mpp.h"
> -#include "orion5x.h"
> -#include "tsx09-common.h"
> -
> -/*****************************************************************************
> - * QNAP TS-409 Info
> - ****************************************************************************/
> -
> -/*
> - * QNAP TS-409 hardware :
> - * - Marvell 88F5281-D0
> - * - Marvell 88SX7042 SATA controller (PCIe)
> - * - Marvell 88E1118 Gigabit Ethernet PHY
> - * - RTC S35390A (@0x30) on I2C bus
> - * - 8MB NOR flash
> - * - 256MB of DDR-2 RAM
> - */
> -
> -/*
> - * 8MB NOR flash Device bus boot chip select
> - */
> -
> -#define QNAP_TS409_NOR_BOOT_BASE 0xff800000
> -#define QNAP_TS409_NOR_BOOT_SIZE SZ_8M
> -
> -/****************************************************************************
> - * 8MiB NOR flash. The struct mtd_partition is not in the same order as the
> - * partitions on the device because we want to keep compatibility with
> - * existing QNAP firmware.
> - *
> - * Layout as used by QNAP:
> - * [2] 0x00000000-0x00200000 : "Kernel"
> - * [3] 0x00200000-0x00600000 : "RootFS1"
> - * [4] 0x00600000-0x00700000 : "RootFS2"
> - * [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
> - * [5] 0x00760000-0x00780000 : "U-Boot Config"
> - * [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
> - ***************************************************************************/
> -static struct mtd_partition qnap_ts409_partitions[] = {
> - {
> - .name = "U-Boot",
> - .size = 0x00080000,
> - .offset = 0x00780000,
> - .mask_flags = MTD_WRITEABLE,
> - }, {
> - .name = "Kernel",
> - .size = 0x00200000,
> - .offset = 0,
> - }, {
> - .name = "RootFS1",
> - .size = 0x00400000,
> - .offset = 0x00200000,
> - }, {
> - .name = "RootFS2",
> - .size = 0x00100000,
> - .offset = 0x00600000,
> - }, {
> - .name = "U-Boot Config",
> - .size = 0x00020000,
> - .offset = 0x00760000,
> - }, {
> - .name = "NAS Config",
> - .size = 0x00060000,
> - .offset = 0x00700000,
> - .mask_flags = MTD_WRITEABLE,
> - },
> -};
> -
> -static struct physmap_flash_data qnap_ts409_nor_flash_data = {
> - .width = 1,
> - .parts = qnap_ts409_partitions,
> - .nr_parts = ARRAY_SIZE(qnap_ts409_partitions)
> -};
> -
> -static struct resource qnap_ts409_nor_flash_resource = {
> - .flags = IORESOURCE_MEM,
> - .start = QNAP_TS409_NOR_BOOT_BASE,
> - .end = QNAP_TS409_NOR_BOOT_BASE + QNAP_TS409_NOR_BOOT_SIZE - 1,
> -};
> -
> -static struct platform_device qnap_ts409_nor_flash = {
> - .name = "physmap-flash",
> - .id = 0,
> - .dev = { .platform_data = &qnap_ts409_nor_flash_data, },
> - .num_resources = 1,
> - .resource = &qnap_ts409_nor_flash_resource,
> -};
> -
> -/*****************************************************************************
> - * PCI
> - ****************************************************************************/
> -
> -static int __init qnap_ts409_pci_map_irq(const struct pci_dev *dev, u8 slot,
> - u8 pin)
> -{
> - int irq;
> -
> - /*
> - * Check for devices with hard-wired IRQs.
> - */
> - irq = orion5x_pci_map_irq(dev, slot, pin);
> - if (irq != -1)
> - return irq;
> -
> - /*
> - * PCI isn't used on the TS-409
> - */
> - return -1;
> -}
> -
> -static struct hw_pci qnap_ts409_pci __initdata = {
> - .nr_controllers = 2,
> - .setup = orion5x_pci_sys_setup,
> - .scan = orion5x_pci_sys_scan_bus,
> - .map_irq = qnap_ts409_pci_map_irq,
> -};
> -
> -static int __init qnap_ts409_pci_init(void)
> -{
> - if (machine_is_ts409())
> - pci_common_init(&qnap_ts409_pci);
> -
> - return 0;
> -}
> -
> -subsys_initcall(qnap_ts409_pci_init);
> -
> -/*****************************************************************************
> - * RTC S35390A on I2C bus
> - ****************************************************************************/
> -
> -#define TS409_RTC_GPIO 10
> -
> -static struct i2c_board_info __initdata qnap_ts409_i2c_rtc = {
> - I2C_BOARD_INFO("s35390a", 0x30),
> -};
> -
> -/*****************************************************************************
> - * LEDs attached to GPIO
> - ****************************************************************************/
> -
> -static struct gpio_led ts409_led_pins[] = {
> - {
> - .name = "ts409:red:sata1",
> - }, {
> - .name = "ts409:red:sata2",
> - }, {
> - .name = "ts409:red:sata3",
> - }, {
> - .name = "ts409:red:sata4",
> - },
> -};
> -
> -static struct gpiod_lookup_table ts409_leds_gpio_table = {
> - .dev_id = "leds-gpio",
> - .table = {
> - GPIO_LOOKUP_IDX("orion_gpio0", 4, NULL,
> - 0, GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP_IDX("orion_gpio0", 5, NULL,
> - 1, GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP_IDX("orion_gpio0", 6, NULL,
> - 2, GPIO_ACTIVE_LOW),
> - GPIO_LOOKUP_IDX("orion_gpio0", 7, NULL,
> - 3, GPIO_ACTIVE_LOW),
> - { },
> - },
> -};
> -
> -static struct gpio_led_platform_data ts409_led_data = {
> - .leds = ts409_led_pins,
> - .num_leds = ARRAY_SIZE(ts409_led_pins),
> -};
> -
> -static struct platform_device ts409_leds = {
> - .name = "leds-gpio",
> - .id = -1,
> - .dev = {
> - .platform_data = &ts409_led_data,
> - },
> -};
> -
> -/****************************************************************************
> - * GPIO Attached Keys
> - * Power button is attached to the PIC microcontroller
> - ****************************************************************************/
> -
> -#define QNAP_TS409_GPIO_KEY_RESET 14
> -#define QNAP_TS409_GPIO_KEY_MEDIA 15
> -
> -static struct gpio_keys_button qnap_ts409_buttons[] = {
> - {
> - .code = KEY_RESTART,
> - .gpio = QNAP_TS409_GPIO_KEY_RESET,
> - .desc = "Reset Button",
> - .active_low = 1,
> - }, {
> - .code = KEY_COPY,
> - .gpio = QNAP_TS409_GPIO_KEY_MEDIA,
> - .desc = "USB Copy Button",
> - .active_low = 1,
> - },
> -};
> -
> -static struct gpio_keys_platform_data qnap_ts409_button_data = {
> - .buttons = qnap_ts409_buttons,
> - .nbuttons = ARRAY_SIZE(qnap_ts409_buttons),
> -};
> -
> -static struct platform_device qnap_ts409_button_device = {
> - .name = "gpio-keys",
> - .id = -1,
> - .num_resources = 0,
> - .dev = {
> - .platform_data = &qnap_ts409_button_data,
> - },
> -};
> -
> -/*****************************************************************************
> - * General Setup
> - ****************************************************************************/
> -static unsigned int ts409_mpp_modes[] __initdata = {
> - MPP0_UNUSED,
> - MPP1_UNUSED,
> - MPP2_UNUSED,
> - MPP3_UNUSED,
> - MPP4_GPIO, /* HDD 1 status */
> - MPP5_GPIO, /* HDD 2 status */
> - MPP6_GPIO, /* HDD 3 status */
> - MPP7_GPIO, /* HDD 4 status */
> - MPP8_UNUSED,
> - MPP9_UNUSED,
> - MPP10_GPIO, /* RTC int */
> - MPP11_UNUSED,
> - MPP12_UNUSED,
> - MPP13_UNUSED,
> - MPP14_GPIO, /* SW_RST */
> - MPP15_GPIO, /* USB copy button */
> - MPP16_UART, /* UART1 RXD */
> - MPP17_UART, /* UART1 TXD */
> - MPP18_UNUSED,
> - MPP19_UNUSED,
> - 0,
> -};
> -
> -static void __init qnap_ts409_init(void)
> -{
> - /*
> - * Setup basic Orion functions. Need to be called early.
> - */
> - orion5x_init();
> -
> - orion5x_mpp_conf(ts409_mpp_modes);
> -
> - /*
> - * Configure peripherals.
> - */
> - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
> - ORION_MBUS_DEVBUS_BOOT_ATTR,
> - QNAP_TS409_NOR_BOOT_BASE,
> - QNAP_TS409_NOR_BOOT_SIZE);
> - platform_device_register(&qnap_ts409_nor_flash);
> -
> - orion5x_ehci0_init();
> - qnap_tsx09_find_mac_addr(QNAP_TS409_NOR_BOOT_BASE +
> - qnap_ts409_partitions[5].offset,
> - qnap_ts409_partitions[5].size);
> - orion5x_eth_init(&qnap_tsx09_eth_data);
> - orion5x_i2c_init();
> - orion5x_uart0_init();
> - orion5x_uart1_init();
> -
> - platform_device_register(&qnap_ts409_button_device);
> -
> - /* Get RTC IRQ and register the chip */
> - if (gpio_request(TS409_RTC_GPIO, "rtc") == 0) {
> - if (gpio_direction_input(TS409_RTC_GPIO) == 0)
> - qnap_ts409_i2c_rtc.irq = gpio_to_irq(TS409_RTC_GPIO);
> - else
> - gpio_free(TS409_RTC_GPIO);
> - }
> - if (qnap_ts409_i2c_rtc.irq == 0)
> - pr_warn("qnap_ts409_init: failed to get RTC IRQ\n");
> - i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1);
> - gpiod_add_lookup_table(&ts409_leds_gpio_table);
> - platform_device_register(&ts409_leds);
> -
> - /* register tsx09 specific power-off method */
> - register_platform_power_off(qnap_tsx09_power_off);
> -}
> -
> -MACHINE_START(TS409, "QNAP TS-409")
> - /* Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com> */
> - .atag_offset = 0x100,
> - .nr_irqs = ORION5X_NR_IRQS,
> - .init_machine = qnap_ts409_init,
> - .map_io = orion5x_map_io,
> - .init_early = orion5x_init_early,
> - .init_irq = orion5x_init_irq,
> - .init_time = orion5x_timer_init,
> - .fixup = tag_fixup_mem32,
> - .restart = orion5x_restart,
> -MACHINE_END
> diff --git a/arch/arm/mach-orion5x/ts78xx-fpga.h b/arch/arm/mach-orion5x/ts78xx-fpga.h
> deleted file mode 100644
> index 2f4fe3ca5c1a..000000000000
> --- a/arch/arm/mach-orion5x/ts78xx-fpga.h
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -#define TS7800_FPGA_MAGIC 0x00b480
> -#define FPGAID(_magic, _rev) ((_magic << 8) + _rev)
> -
> -/*
> - * get yer id's from http://ts78xx.digriz.org.uk/
> - * do *not* make up your own or 'borrow' any!
> - */
> -enum fpga_ids {
> - /* Technologic Systems */
> - TS7800_REV_1 = FPGAID(TS7800_FPGA_MAGIC, 0x01),
> - TS7800_REV_2 = FPGAID(TS7800_FPGA_MAGIC, 0x02),
> - TS7800_REV_3 = FPGAID(TS7800_FPGA_MAGIC, 0x03),
> - TS7800_REV_4 = FPGAID(TS7800_FPGA_MAGIC, 0x04),
> - TS7800_REV_5 = FPGAID(TS7800_FPGA_MAGIC, 0x05),
> - TS7800_REV_6 = FPGAID(TS7800_FPGA_MAGIC, 0x06),
> - TS7800_REV_7 = FPGAID(TS7800_FPGA_MAGIC, 0x07),
> - TS7800_REV_8 = FPGAID(TS7800_FPGA_MAGIC, 0x08),
> - TS7800_REV_9 = FPGAID(TS7800_FPGA_MAGIC, 0x09),
> -
> - /* Unaffordable & Expensive */
> - UAE_DUMMY = FPGAID(0xffffff, 0x01),
> -};
> -
> -struct fpga_device {
> - unsigned present:1;
> - unsigned init:1;
> -};
> -
> -struct fpga_devices {
> - /* Technologic Systems */
> - struct fpga_device ts_rtc;
> - struct fpga_device ts_nand;
> - struct fpga_device ts_rng;
> -};
> -
> -struct ts78xx_fpga_data {
> - unsigned int id;
> - int state;
> -
> - struct fpga_devices supports;
> -};
> diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
> deleted file mode 100644
> index af810e7ccd79..000000000000
> --- a/arch/arm/mach-orion5x/ts78xx-setup.c
> +++ /dev/null
> @@ -1,574 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * arch/arm/mach-orion5x/ts78xx-setup.c
> - *
> - * Maintainer: Alexander Clouter <alex@digriz.org.uk>
> - */
> -
> -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
> -
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/sysfs.h>
> -#include <linux/platform_device.h>
> -#include <linux/mv643xx_eth.h>
> -#include <linux/ata_platform.h>
> -#include <linux/mtd/platnand.h>
> -#include <linux/timeriomem-rng.h>
> -#include <asm/mach-types.h>
> -#include <asm/mach/arch.h>
> -#include <asm/mach/map.h>
> -#include "common.h"
> -#include "mpp.h"
> -#include "orion5x.h"
> -#include "ts78xx-fpga.h"
> -
> -/*****************************************************************************
> - * TS-78xx Info
> - ****************************************************************************/
> -
> -/*
> - * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
> - */
> -#define TS78XX_FPGA_REGS_PHYS_BASE 0xe8000000
> -#define TS78XX_FPGA_REGS_VIRT_BASE IOMEM(0xff900000)
> -#define TS78XX_FPGA_REGS_SIZE SZ_1M
> -
> -static struct ts78xx_fpga_data ts78xx_fpga = {
> - .id = 0,
> - .state = 1,
> -/* .supports = ... - populated by ts78xx_fpga_supports() */
> -};
> -
> -/*****************************************************************************
> - * I/O Address Mapping
> - ****************************************************************************/
> -static struct map_desc ts78xx_io_desc[] __initdata = {
> - {
> - .virtual = (unsigned long)TS78XX_FPGA_REGS_VIRT_BASE,
> - .pfn = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE),
> - .length = TS78XX_FPGA_REGS_SIZE,
> - .type = MT_DEVICE,
> - },
> -};
> -
> -static void __init ts78xx_map_io(void)
> -{
> - orion5x_map_io();
> - iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));
> -}
> -
> -/*****************************************************************************
> - * Ethernet
> - ****************************************************************************/
> -static struct mv643xx_eth_platform_data ts78xx_eth_data = {
> - .phy_addr = MV643XX_ETH_PHY_ADDR(0),
> -};
> -
> -/*****************************************************************************
> - * SATA
> - ****************************************************************************/
> -static struct mv_sata_platform_data ts78xx_sata_data = {
> - .n_ports = 2,
> -};
> -
> -/*****************************************************************************
> - * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
> - ****************************************************************************/
> -#define TS_RTC_CTRL (TS78XX_FPGA_REGS_PHYS_BASE + 0x808)
> -#define TS_RTC_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x80c)
> -
> -static struct resource ts78xx_ts_rtc_resources[] = {
> - DEFINE_RES_MEM(TS_RTC_CTRL, 0x01),
> - DEFINE_RES_MEM(TS_RTC_DATA, 0x01),
> -};
> -
> -static struct platform_device ts78xx_ts_rtc_device = {
> - .name = "rtc-m48t86",
> - .id = -1,
> - .resource = ts78xx_ts_rtc_resources,
> - .num_resources = ARRAY_SIZE(ts78xx_ts_rtc_resources),
> -};
> -
> -static int ts78xx_ts_rtc_load(void)
> -{
> - int rc;
> -
> - if (ts78xx_fpga.supports.ts_rtc.init == 0) {
> - rc = platform_device_register(&ts78xx_ts_rtc_device);
> - if (!rc)
> - ts78xx_fpga.supports.ts_rtc.init = 1;
> - } else {
> - rc = platform_device_add(&ts78xx_ts_rtc_device);
> - }
> -
> - if (rc)
> - pr_info("RTC could not be registered: %d\n", rc);
> -
> - return rc;
> -}
> -
> -static void ts78xx_ts_rtc_unload(void)
> -{
> - platform_device_del(&ts78xx_ts_rtc_device);
> -}
> -
> -/*****************************************************************************
> - * NAND Flash
> - ****************************************************************************/
> -#define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE + 0x800) /* VIRT */
> -#define TS_NAND_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x804) /* PHYS */
> -
> -/*
> - * hardware specific access to control-lines
> - *
> - * ctrl:
> - * NAND_NCE: bit 0 -> bit 2
> - * NAND_CLE: bit 1 -> bit 1
> - * NAND_ALE: bit 2 -> bit 0
> - */
> -static void ts78xx_ts_nand_cmd_ctrl(struct nand_chip *this, int cmd,
> - unsigned int ctrl)
> -{
> - if (ctrl & NAND_CTRL_CHANGE) {
> - unsigned char bits;
> -
> - bits = (ctrl & NAND_NCE) << 2;
> - bits |= ctrl & NAND_CLE;
> - bits |= (ctrl & NAND_ALE) >> 2;
> -
> - writeb((readb(TS_NAND_CTRL) & ~0x7) | bits, TS_NAND_CTRL);
> - }
> -
> - if (cmd != NAND_CMD_NONE)
> - writeb(cmd, this->legacy.IO_ADDR_W);
> -}
> -
> -static int ts78xx_ts_nand_dev_ready(struct nand_chip *chip)
> -{
> - return readb(TS_NAND_CTRL) & 0x20;
> -}
> -
> -static void ts78xx_ts_nand_write_buf(struct nand_chip *chip,
> - const uint8_t *buf, int len)
> -{
> - void __iomem *io_base = chip->legacy.IO_ADDR_W;
> - unsigned long off = ((unsigned long)buf & 3);
> - int sz;
> -
> - if (off) {
> - sz = min_t(int, 4 - off, len);
> - writesb(io_base, buf, sz);
> - buf += sz;
> - len -= sz;
> - }
> -
> - sz = len >> 2;
> - if (sz) {
> - u32 *buf32 = (u32 *)buf;
> - writesl(io_base, buf32, sz);
> - buf += sz << 2;
> - len -= sz << 2;
> - }
> -
> - if (len)
> - writesb(io_base, buf, len);
> -}
> -
> -static void ts78xx_ts_nand_read_buf(struct nand_chip *chip,
> - uint8_t *buf, int len)
> -{
> - void __iomem *io_base = chip->legacy.IO_ADDR_R;
> - unsigned long off = ((unsigned long)buf & 3);
> - int sz;
> -
> - if (off) {
> - sz = min_t(int, 4 - off, len);
> - readsb(io_base, buf, sz);
> - buf += sz;
> - len -= sz;
> - }
> -
> - sz = len >> 2;
> - if (sz) {
> - u32 *buf32 = (u32 *)buf;
> - readsl(io_base, buf32, sz);
> - buf += sz << 2;
> - len -= sz << 2;
> - }
> -
> - if (len)
> - readsb(io_base, buf, len);
> -}
> -
> -static struct mtd_partition ts78xx_ts_nand_parts[] = {
> - {
> - .name = "mbr",
> - .offset = 0,
> - .size = SZ_128K,
> - .mask_flags = MTD_WRITEABLE,
> - }, {
> - .name = "kernel",
> - .offset = MTDPART_OFS_APPEND,
> - .size = SZ_4M,
> - }, {
> - .name = "initrd",
> - .offset = MTDPART_OFS_APPEND,
> - .size = SZ_4M,
> - }, {
> - .name = "rootfs",
> - .offset = MTDPART_OFS_APPEND,
> - .size = MTDPART_SIZ_FULL,
> - }
> -};
> -
> -static struct platform_nand_data ts78xx_ts_nand_data = {
> - .chip = {
> - .nr_chips = 1,
> - .partitions = ts78xx_ts_nand_parts,
> - .nr_partitions = ARRAY_SIZE(ts78xx_ts_nand_parts),
> - .chip_delay = 15,
> - .bbt_options = NAND_BBT_USE_FLASH,
> - },
> - .ctrl = {
> - /*
> - * The HW ECC offloading functions, used to give about a 9%
> - * performance increase for 'dd if=/dev/mtdblockX' and 5% for
> - * nanddump. This all however was changed by git commit
> - * e6cf5df1838c28bb060ac45b5585e48e71bbc740 so now there is
> - * no performance advantage to be had so we no longer bother
> - */
> - .cmd_ctrl = ts78xx_ts_nand_cmd_ctrl,
> - .dev_ready = ts78xx_ts_nand_dev_ready,
> - .write_buf = ts78xx_ts_nand_write_buf,
> - .read_buf = ts78xx_ts_nand_read_buf,
> - },
> -};
> -
> -static struct resource ts78xx_ts_nand_resources
> - = DEFINE_RES_MEM(TS_NAND_DATA, 4);
> -
> -static struct platform_device ts78xx_ts_nand_device = {
> - .name = "gen_nand",
> - .id = -1,
> - .dev = {
> - .platform_data = &ts78xx_ts_nand_data,
> - },
> - .resource = &ts78xx_ts_nand_resources,
> - .num_resources = 1,
> -};
> -
> -static int ts78xx_ts_nand_load(void)
> -{
> - int rc;
> -
> - if (ts78xx_fpga.supports.ts_nand.init == 0) {
> - rc = platform_device_register(&ts78xx_ts_nand_device);
> - if (!rc)
> - ts78xx_fpga.supports.ts_nand.init = 1;
> - } else
> - rc = platform_device_add(&ts78xx_ts_nand_device);
> -
> - if (rc)
> - pr_info("NAND could not be registered: %d\n", rc);
> - return rc;
> -};
> -
> -static void ts78xx_ts_nand_unload(void)
> -{
> - platform_device_del(&ts78xx_ts_nand_device);
> -}
> -
> -/*****************************************************************************
> - * HW RNG
> - ****************************************************************************/
> -#define TS_RNG_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x044)
> -
> -static struct resource ts78xx_ts_rng_resource
> - = DEFINE_RES_MEM(TS_RNG_DATA, 4);
> -
> -static struct timeriomem_rng_data ts78xx_ts_rng_data = {
> - .period = 1000000, /* one second */
> -};
> -
> -static struct platform_device ts78xx_ts_rng_device = {
> - .name = "timeriomem_rng",
> - .id = -1,
> - .dev = {
> - .platform_data = &ts78xx_ts_rng_data,
> - },
> - .resource = &ts78xx_ts_rng_resource,
> - .num_resources = 1,
> -};
> -
> -static int ts78xx_ts_rng_load(void)
> -{
> - int rc;
> -
> - if (ts78xx_fpga.supports.ts_rng.init == 0) {
> - rc = platform_device_register(&ts78xx_ts_rng_device);
> - if (!rc)
> - ts78xx_fpga.supports.ts_rng.init = 1;
> - } else
> - rc = platform_device_add(&ts78xx_ts_rng_device);
> -
> - if (rc)
> - pr_info("RNG could not be registered: %d\n", rc);
> - return rc;
> -};
> -
> -static void ts78xx_ts_rng_unload(void)
> -{
> - platform_device_del(&ts78xx_ts_rng_device);
> -}
> -
> -/*****************************************************************************
> - * FPGA 'hotplug' support code
> - ****************************************************************************/
> -static void ts78xx_fpga_devices_zero_init(void)
> -{
> - ts78xx_fpga.supports.ts_rtc.init = 0;
> - ts78xx_fpga.supports.ts_nand.init = 0;
> - ts78xx_fpga.supports.ts_rng.init = 0;
> -}
> -
> -static void ts78xx_fpga_supports(void)
> -{
> - /* TODO: put this 'table' into ts78xx-fpga.h */
> - switch (ts78xx_fpga.id) {
> - case TS7800_REV_1:
> - case TS7800_REV_2:
> - case TS7800_REV_3:
> - case TS7800_REV_4:
> - case TS7800_REV_5:
> - case TS7800_REV_6:
> - case TS7800_REV_7:
> - case TS7800_REV_8:
> - case TS7800_REV_9:
> - ts78xx_fpga.supports.ts_rtc.present = 1;
> - ts78xx_fpga.supports.ts_nand.present = 1;
> - ts78xx_fpga.supports.ts_rng.present = 1;
> - break;
> - default:
> - /* enable devices if magic matches */
> - switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
> - case TS7800_FPGA_MAGIC:
> - pr_warn("unrecognised FPGA revision 0x%.2x\n",
> - ts78xx_fpga.id & 0xff);
> - ts78xx_fpga.supports.ts_rtc.present = 1;
> - ts78xx_fpga.supports.ts_nand.present = 1;
> - ts78xx_fpga.supports.ts_rng.present = 1;
> - break;
> - default:
> - ts78xx_fpga.supports.ts_rtc.present = 0;
> - ts78xx_fpga.supports.ts_nand.present = 0;
> - ts78xx_fpga.supports.ts_rng.present = 0;
> - }
> - }
> -}
> -
> -static int ts78xx_fpga_load_devices(void)
> -{
> - int tmp, ret = 0;
> -
> - if (ts78xx_fpga.supports.ts_rtc.present == 1) {
> - tmp = ts78xx_ts_rtc_load();
> - if (tmp)
> - ts78xx_fpga.supports.ts_rtc.present = 0;
> - ret |= tmp;
> - }
> - if (ts78xx_fpga.supports.ts_nand.present == 1) {
> - tmp = ts78xx_ts_nand_load();
> - if (tmp)
> - ts78xx_fpga.supports.ts_nand.present = 0;
> - ret |= tmp;
> - }
> - if (ts78xx_fpga.supports.ts_rng.present == 1) {
> - tmp = ts78xx_ts_rng_load();
> - if (tmp)
> - ts78xx_fpga.supports.ts_rng.present = 0;
> - ret |= tmp;
> - }
> -
> - return ret;
> -}
> -
> -static int ts78xx_fpga_unload_devices(void)
> -{
> -
> - if (ts78xx_fpga.supports.ts_rtc.present == 1)
> - ts78xx_ts_rtc_unload();
> - if (ts78xx_fpga.supports.ts_nand.present == 1)
> - ts78xx_ts_nand_unload();
> - if (ts78xx_fpga.supports.ts_rng.present == 1)
> - ts78xx_ts_rng_unload();
> -
> - return 0;
> -}
> -
> -static int ts78xx_fpga_load(void)
> -{
> - ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
> -
> - pr_info("FPGA magic=0x%.6x, rev=0x%.2x\n",
> - (ts78xx_fpga.id >> 8) & 0xffffff,
> - ts78xx_fpga.id & 0xff);
> -
> - ts78xx_fpga_supports();
> -
> - if (ts78xx_fpga_load_devices()) {
> - ts78xx_fpga.state = -1;
> - return -EBUSY;
> - }
> -
> - return 0;
> -};
> -
> -static int ts78xx_fpga_unload(void)
> -{
> - unsigned int fpga_id;
> -
> - fpga_id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
> -
> - /*
> - * There does not seem to be a feasible way to block access to the GPIO
> - * pins from userspace (/dev/mem). This if clause should hopefully warn
> - * those foolish enough not to follow 'policy' :)
> - *
> - * UrJTAG SVN since r1381 can be used to reprogram the FPGA
> - */
> - if (ts78xx_fpga.id != fpga_id) {
> - pr_err("FPGA magic/rev mismatch\n"
> - "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n",
> - (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff,
> - (fpga_id >> 8) & 0xffffff, fpga_id & 0xff);
> - ts78xx_fpga.state = -1;
> - return -EBUSY;
> - }
> -
> - if (ts78xx_fpga_unload_devices()) {
> - ts78xx_fpga.state = -1;
> - return -EBUSY;
> - }
> -
> - return 0;
> -};
> -
> -static ssize_t ts78xx_fpga_show(struct kobject *kobj,
> - struct kobj_attribute *attr, char *buf)
> -{
> - if (ts78xx_fpga.state < 0)
> - return sprintf(buf, "borked\n");
> -
> - return sprintf(buf, "%s\n", (ts78xx_fpga.state) ? "online" : "offline");
> -}
> -
> -static ssize_t ts78xx_fpga_store(struct kobject *kobj,
> - struct kobj_attribute *attr, const char *buf, size_t n)
> -{
> - int value, ret;
> -
> - if (ts78xx_fpga.state < 0) {
> - pr_err("FPGA borked, you must powercycle ASAP\n");
> - return -EBUSY;
> - }
> -
> - if (strncmp(buf, "online", sizeof("online") - 1) == 0)
> - value = 1;
> - else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0)
> - value = 0;
> - else
> - return -EINVAL;
> -
> - if (ts78xx_fpga.state == value)
> - return n;
> -
> - ret = (ts78xx_fpga.state == 0)
> - ? ts78xx_fpga_load()
> - : ts78xx_fpga_unload();
> -
> - if (!(ret < 0))
> - ts78xx_fpga.state = value;
> -
> - return n;
> -}
> -
> -static struct kobj_attribute ts78xx_fpga_attr =
> - __ATTR(ts78xx_fpga, 0644, ts78xx_fpga_show, ts78xx_fpga_store);
> -
> -/*****************************************************************************
> - * General Setup
> - ****************************************************************************/
> -static unsigned int ts78xx_mpp_modes[] __initdata = {
> - MPP0_UNUSED,
> - MPP1_GPIO, /* JTAG Clock */
> - MPP2_GPIO, /* JTAG Data In */
> - MPP3_GPIO, /* Lat ECP2 256 FPGA - PB2B */
> - MPP4_GPIO, /* JTAG Data Out */
> - MPP5_GPIO, /* JTAG TMS */
> - MPP6_GPIO, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
> - MPP7_GPIO, /* Lat ECP2 256 FPGA - PB22B */
> - MPP8_UNUSED,
> - MPP9_UNUSED,
> - MPP10_UNUSED,
> - MPP11_UNUSED,
> - MPP12_UNUSED,
> - MPP13_UNUSED,
> - MPP14_UNUSED,
> - MPP15_UNUSED,
> - MPP16_UART,
> - MPP17_UART,
> - MPP18_UART,
> - MPP19_UART,
> - /*
> - * MPP[20] PCI Clock Out 1
> - * MPP[21] PCI Clock Out 0
> - * MPP[22] Unused
> - * MPP[23] Unused
> - * MPP[24] Unused
> - * MPP[25] Unused
> - */
> - 0,
> -};
> -
> -static void __init ts78xx_init(void)
> -{
> - int ret;
> -
> - /*
> - * Setup basic Orion functions. Need to be called early.
> - */
> - orion5x_init();
> -
> - orion5x_mpp_conf(ts78xx_mpp_modes);
> -
> - /*
> - * Configure peripherals.
> - */
> - orion5x_ehci0_init();
> - orion5x_ehci1_init();
> - orion5x_eth_init(&ts78xx_eth_data);
> - orion5x_sata_init(&ts78xx_sata_data);
> - orion5x_uart0_init();
> - orion5x_uart1_init();
> - orion5x_xor_init();
> -
> - /* FPGA init */
> - ts78xx_fpga_devices_zero_init();
> - ret = ts78xx_fpga_load();
> - ret = sysfs_create_file(firmware_kobj, &ts78xx_fpga_attr.attr);
> - if (ret)
> - pr_err("sysfs_create_file failed: %d\n", ret);
> -}
> -
> -MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
> - /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
> - .atag_offset = 0x100,
> - .nr_irqs = ORION5X_NR_IRQS,
> - .init_machine = ts78xx_init,
> - .map_io = ts78xx_map_io,
> - .init_early = orion5x_init_early,
> - .init_irq = orion5x_init_irq,
> - .init_time = orion5x_timer_init,
> - .restart = orion5x_restart,
> -MACHINE_END
> diff --git a/arch/arm/mach-orion5x/tsx09-common.c b/arch/arm/mach-orion5x/tsx09-common.c
> deleted file mode 100644
> index 099e6fdfa8e6..000000000000
> --- a/arch/arm/mach-orion5x/tsx09-common.c
> +++ /dev/null
> @@ -1,129 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later
> -/*
> - * QNAP TS-x09 Boards common functions
> - *
> - * Maintainers: Lennert Buytenhek <buytenh@marvell.com>
> - * Byron Bradley <byron.bbradley@gmail.com>
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/pci.h>
> -#include <linux/mv643xx_eth.h>
> -#include <linux/timex.h>
> -#include <linux/serial_reg.h>
> -#include "orion5x.h"
> -#include "tsx09-common.h"
> -#include "common.h"
> -
> -/*****************************************************************************
> - * QNAP TS-x09 specific power off method via UART1-attached PIC
> - ****************************************************************************/
> -
> -#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
> -
> -void qnap_tsx09_power_off(void)
> -{
> - /* 19200 baud divisor */
> - const unsigned divisor = ((orion5x_tclk + (8 * 19200)) / (16 * 19200));
> -
> - pr_info("%s: triggering power-off...\n", __func__);
> -
> - /* hijack uart1 and reset into sane state (19200,8n1) */
> - writel(0x83, UART1_REG(LCR));
> - writel(divisor & 0xff, UART1_REG(DLL));
> - writel((divisor >> 8) & 0xff, UART1_REG(DLM));
> - writel(0x03, UART1_REG(LCR));
> - writel(0x00, UART1_REG(IER));
> - writel(0x00, UART1_REG(FCR));
> - writel(0x00, UART1_REG(MCR));
> -
> - /* send the power-off command 'A' to PIC */
> - writel('A', UART1_REG(TX));
> -}
> -
> -/*****************************************************************************
> - * Ethernet
> - ****************************************************************************/
> -
> -struct mv643xx_eth_platform_data qnap_tsx09_eth_data = {
> - .phy_addr = MV643XX_ETH_PHY_ADDR(8),
> -};
> -
> -static int __init qnap_tsx09_parse_hex_nibble(char n)
> -{
> - if (n >= '0' && n <= '9')
> - return n - '0';
> -
> - if (n >= 'A' && n <= 'F')
> - return n - 'A' + 10;
> -
> - if (n >= 'a' && n <= 'f')
> - return n - 'a' + 10;
> -
> - return -1;
> -}
> -
> -static int __init qnap_tsx09_parse_hex_byte(const char *b)
> -{
> - int hi;
> - int lo;
> -
> - hi = qnap_tsx09_parse_hex_nibble(b[0]);
> - lo = qnap_tsx09_parse_hex_nibble(b[1]);
> -
> - if (hi < 0 || lo < 0)
> - return -1;
> -
> - return (hi << 4) | lo;
> -}
> -
> -static int __init qnap_tsx09_check_mac_addr(const char *addr_str)
> -{
> - u_int8_t addr[6];
> - int i;
> -
> - for (i = 0; i < 6; i++) {
> - int byte;
> -
> - /*
> - * Enforce "xx:xx:xx:xx:xx:xx\n" format.
> - */
> - if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n'))
> - return -1;
> -
> - byte = qnap_tsx09_parse_hex_byte(addr_str + (i * 3));
> - if (byte < 0)
> - return -1;
> - addr[i] = byte;
> - }
> -
> - printk(KERN_INFO "tsx09: found ethernet mac address %pM\n", addr);
> -
> - memcpy(qnap_tsx09_eth_data.mac_addr, addr, 6);
> -
> - return 0;
> -}
> -
> -/*
> - * The 'NAS Config' flash partition has an ext2 filesystem which
> - * contains a file that has the ethernet MAC address in plain text
> - * (format "xx:xx:xx:xx:xx:xx\n").
> - */
> -void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size)
> -{
> - unsigned long addr;
> -
> - for (addr = mem_base; addr < (mem_base + size); addr += 1024) {
> - char *nor_page;
> - int ret = 0;
> -
> - nor_page = ioremap(addr, 1024);
> - if (nor_page != NULL) {
> - ret = qnap_tsx09_check_mac_addr(nor_page);
> - iounmap(nor_page);
> - }
> -
> - if (ret == 0)
> - break;
> - }
> -}
> diff --git a/arch/arm/mach-orion5x/tsx09-common.h b/arch/arm/mach-orion5x/tsx09-common.h
> deleted file mode 100644
> index 72bedc6b82fb..000000000000
> --- a/arch/arm/mach-orion5x/tsx09-common.h
> +++ /dev/null
> @@ -1,21 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -#ifndef __ARCH_ORION5X_TSX09_COMMON_H
> -#define __ARCH_ORION5X_TSX09_COMMON_H
> -
> -/*
> - * QNAP TS-x09 Boards power-off function
> - */
> -extern void qnap_tsx09_power_off(void);
> -
> -/*
> - * QNAP TS-x09 Boards function to find Ethernet MAC address in flash memory
> - */
> -extern void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size);
> -
> -/*
> - * QNAP TS-x09 Boards ethernet declaration
> - */
> -extern struct mv643xx_eth_platform_data qnap_tsx09_eth_data;
> -
> -
> -#endif
> diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
> index 6574659dfb61..c40cdb2274ea 100644
> --- a/arch/arm/mm/Kconfig
> +++ b/arch/arm/mm/Kconfig
> @@ -980,7 +980,7 @@ config CACHE_B15_RAC
>
> config CACHE_FEROCEON_L2
> bool "Enable the Feroceon L2 cache controller"
> - depends on ARCH_MV78XX0 || ARCH_MVEBU
> + depends on ARCH_MVEBU
> default y
> select OUTER_CACHE
> help
> diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
> index e8c7580df8ca..dfde39cdd992 100644
> --- a/arch/arm/plat-orion/Makefile
> +++ b/arch/arm/plat-orion/Makefile
> @@ -5,5 +5,5 @@
> ccflags-y := -I$(src)/include
>
> orion-gpio-$(CONFIG_GPIOLIB) += gpio.o
> -obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o
> +obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o mpp.o
> obj-$(CONFIG_PLAT_ORION_LEGACY) += $(orion-gpio-y)
> diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
> deleted file mode 100644
> index cabe98386245..000000000000
> --- a/arch/arm/plat-orion/common.c
> +++ /dev/null
> @@ -1,826 +0,0 @@
> -/*
> - * arch/arm/plat-orion/common.c
> - *
> - * Marvell Orion SoC common setup code used by multiple mach-/common.c
> - *
> - * This file is licensed under the terms of the GNU General Public
> - * License version 2. This program is licensed "as is" without any
> - * warranty of any kind, whether express or implied.
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/platform_device.h>
> -#include <linux/dma-mapping.h>
> -#include <linux/serial_8250.h>
> -#include <linux/ata_platform.h>
> -#include <linux/clk.h>
> -#include <linux/clkdev.h>
> -#include <linux/mv643xx_eth.h>
> -#include <linux/mv643xx_i2c.h>
> -#include <linux/platform_data/dma-mv_xor.h>
> -#include <linux/platform_data/usb-ehci-orion.h>
> -#include <plat/common.h>
> -#include <linux/phy.h>
> -
> -/* Create a clkdev entry for a given device/clk */
> -void __init orion_clkdev_add(const char *con_id, const char *dev_id,
> - struct clk *clk)
> -{
> - clkdev_create(clk, con_id, "%s", dev_id);
> -}
> -
> -/* Create clkdev entries for all orion platforms except kirkwood.
> - Kirkwood has gated clocks for some of its peripherals, so creates
> - its own clkdev entries. For all the other orion devices, create
> - clkdev entries to the tclk. */
> -void __init orion_clkdev_init(struct clk *tclk)
> -{
> - orion_clkdev_add(NULL, "orion_spi.0", tclk);
> - orion_clkdev_add(NULL, "orion_spi.1", tclk);
> - orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", tclk);
> - orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", tclk);
> - orion_clkdev_add(NULL, MV643XX_ETH_NAME ".2", tclk);
> - orion_clkdev_add(NULL, MV643XX_ETH_NAME ".3", tclk);
> - orion_clkdev_add(NULL, "orion_wdt", tclk);
> - orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", tclk);
> -}
> -
> -/* Fill in the resources structure and link it into the platform
> - device structure. There is always a memory region, and nearly
> - always an interrupt.*/
> -static void fill_resources(struct platform_device *device,
> - struct resource *resources,
> - resource_size_t mapbase,
> - resource_size_t size)
> -{
> - device->resource = resources;
> - device->num_resources = 1;
> - resources[0].flags = IORESOURCE_MEM;
> - resources[0].start = mapbase;
> - resources[0].end = mapbase + size;
> -}
> -
> -static void fill_resources_irq(struct platform_device *device,
> - struct resource *resources,
> - resource_size_t mapbase,
> - resource_size_t size,
> - unsigned int irq)
> -{
> - fill_resources(device, resources, mapbase, size);
> -
> - device->num_resources++;
> - resources[1].flags = IORESOURCE_IRQ;
> - resources[1].start = irq;
> - resources[1].end = irq;
> -}
> -
> -/*****************************************************************************
> - * UART
> - ****************************************************************************/
> -static unsigned long __init uart_get_clk_rate(struct clk *clk)
> -{
> - clk_prepare_enable(clk);
> - return clk_get_rate(clk);
> -}
> -
> -static void __init uart_complete(
> - struct platform_device *orion_uart,
> - struct plat_serial8250_port *data,
> - struct resource *resources,
> - void __iomem *membase,
> - resource_size_t mapbase,
> - unsigned int irq,
> - struct clk *clk)
> -{
> - data->mapbase = mapbase;
> - data->membase = membase;
> - data->irq = irq;
> - data->uartclk = uart_get_clk_rate(clk);
> - orion_uart->dev.platform_data = data;
> -
> - fill_resources_irq(orion_uart, resources, mapbase, 0xff, irq);
> - platform_device_register(orion_uart);
> -}
> -
> -/*****************************************************************************
> - * UART0
> - ****************************************************************************/
> -static struct plat_serial8250_port orion_uart0_data[] = {
> - {
> - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
> - .iotype = UPIO_MEM,
> - .regshift = 2,
> - }, {
> - },
> -};
> -
> -static struct resource orion_uart0_resources[2];
> -
> -static struct platform_device orion_uart0 = {
> - .name = "serial8250",
> - .id = PLAT8250_DEV_PLATFORM,
> -};
> -
> -void __init orion_uart0_init(void __iomem *membase,
> - resource_size_t mapbase,
> - unsigned int irq,
> - struct clk *clk)
> -{
> - uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources,
> - membase, mapbase, irq, clk);
> -}
> -
> -/*****************************************************************************
> - * UART1
> - ****************************************************************************/
> -static struct plat_serial8250_port orion_uart1_data[] = {
> - {
> - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
> - .iotype = UPIO_MEM,
> - .regshift = 2,
> - }, {
> - },
> -};
> -
> -static struct resource orion_uart1_resources[2];
> -
> -static struct platform_device orion_uart1 = {
> - .name = "serial8250",
> - .id = PLAT8250_DEV_PLATFORM1,
> -};
> -
> -void __init orion_uart1_init(void __iomem *membase,
> - resource_size_t mapbase,
> - unsigned int irq,
> - struct clk *clk)
> -{
> - uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources,
> - membase, mapbase, irq, clk);
> -}
> -
> -/*****************************************************************************
> - * UART2
> - ****************************************************************************/
> -static struct plat_serial8250_port orion_uart2_data[] = {
> - {
> - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
> - .iotype = UPIO_MEM,
> - .regshift = 2,
> - }, {
> - },
> -};
> -
> -static struct resource orion_uart2_resources[2];
> -
> -static struct platform_device orion_uart2 = {
> - .name = "serial8250",
> - .id = PLAT8250_DEV_PLATFORM2,
> -};
> -
> -void __init orion_uart2_init(void __iomem *membase,
> - resource_size_t mapbase,
> - unsigned int irq,
> - struct clk *clk)
> -{
> - uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources,
> - membase, mapbase, irq, clk);
> -}
> -
> -/*****************************************************************************
> - * UART3
> - ****************************************************************************/
> -static struct plat_serial8250_port orion_uart3_data[] = {
> - {
> - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
> - .iotype = UPIO_MEM,
> - .regshift = 2,
> - }, {
> - },
> -};
> -
> -static struct resource orion_uart3_resources[2];
> -
> -static struct platform_device orion_uart3 = {
> - .name = "serial8250",
> - .id = 3,
> -};
> -
> -void __init orion_uart3_init(void __iomem *membase,
> - resource_size_t mapbase,
> - unsigned int irq,
> - struct clk *clk)
> -{
> - uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources,
> - membase, mapbase, irq, clk);
> -}
> -
> -/*****************************************************************************
> - * SoC RTC
> - ****************************************************************************/
> -static struct resource orion_rtc_resource[2];
> -
> -void __init orion_rtc_init(unsigned long mapbase,
> - unsigned long irq)
> -{
> - orion_rtc_resource[0].start = mapbase;
> - orion_rtc_resource[0].end = mapbase + SZ_32 - 1;
> - orion_rtc_resource[0].flags = IORESOURCE_MEM;
> - orion_rtc_resource[1].start = irq;
> - orion_rtc_resource[1].end = irq;
> - orion_rtc_resource[1].flags = IORESOURCE_IRQ;
> -
> - platform_device_register_simple("rtc-mv", -1, orion_rtc_resource, 2);
> -}
> -
> -/*****************************************************************************
> - * GE
> - ****************************************************************************/
> -static __init void ge_complete(
> - struct mv643xx_eth_shared_platform_data *orion_ge_shared_data,
> - struct resource *orion_ge_resource, unsigned long irq,
> - struct platform_device *orion_ge_shared,
> - struct platform_device *orion_ge_mvmdio,
> - struct mv643xx_eth_platform_data *eth_data,
> - struct platform_device *orion_ge)
> -{
> - orion_ge_resource->start = irq;
> - orion_ge_resource->end = irq;
> - eth_data->shared = orion_ge_shared;
> - orion_ge->dev.platform_data = eth_data;
> -
> - platform_device_register(orion_ge_shared);
> - if (orion_ge_mvmdio)
> - platform_device_register(orion_ge_mvmdio);
> - platform_device_register(orion_ge);
> -}
> -
> -/*****************************************************************************
> - * GE00
> - ****************************************************************************/
> -static struct mv643xx_eth_shared_platform_data orion_ge00_shared_data;
> -
> -static struct resource orion_ge00_shared_resources[] = {
> - {
> - .name = "ge00 base",
> - },
> -};
> -
> -static struct platform_device orion_ge00_shared = {
> - .name = MV643XX_ETH_SHARED_NAME,
> - .id = 0,
> - .dev = {
> - .platform_data = &orion_ge00_shared_data,
> - },
> -};
> -
> -static struct resource orion_ge_mvmdio_resources[] = {
> - {
> - .name = "ge00 mvmdio base",
> - }, {
> - .name = "ge00 mvmdio err irq",
> - },
> -};
> -
> -static struct platform_device orion_ge_mvmdio = {
> - .name = "orion-mdio",
> - .id = -1,
> -};
> -
> -static struct resource orion_ge00_resources[] = {
> - {
> - .name = "ge00 irq",
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -static struct platform_device orion_ge00 = {
> - .name = MV643XX_ETH_NAME,
> - .id = 0,
> - .num_resources = 1,
> - .resource = orion_ge00_resources,
> - .dev = {
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - },
> -};
> -
> -void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
> - unsigned long mapbase,
> - unsigned long irq,
> - unsigned long irq_err,
> - unsigned int tx_csum_limit)
> -{
> - fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
> - mapbase + 0x2000, SZ_16K - 1);
> - fill_resources_irq(&orion_ge_mvmdio, orion_ge_mvmdio_resources,
> - mapbase + 0x2004, 0x84 - 1, irq_err);
> - orion_ge00_shared_data.tx_csum_limit = tx_csum_limit;
> - ge_complete(&orion_ge00_shared_data,
> - orion_ge00_resources, irq, &orion_ge00_shared,
> - &orion_ge_mvmdio,
> - eth_data, &orion_ge00);
> -}
> -
> -/*****************************************************************************
> - * GE01
> - ****************************************************************************/
> -static struct mv643xx_eth_shared_platform_data orion_ge01_shared_data;
> -
> -static struct resource orion_ge01_shared_resources[] = {
> - {
> - .name = "ge01 base",
> - }
> -};
> -
> -static struct platform_device orion_ge01_shared = {
> - .name = MV643XX_ETH_SHARED_NAME,
> - .id = 1,
> - .dev = {
> - .platform_data = &orion_ge01_shared_data,
> - },
> -};
> -
> -static struct resource orion_ge01_resources[] = {
> - {
> - .name = "ge01 irq",
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -static struct platform_device orion_ge01 = {
> - .name = MV643XX_ETH_NAME,
> - .id = 1,
> - .num_resources = 1,
> - .resource = orion_ge01_resources,
> - .dev = {
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - },
> -};
> -
> -void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
> - unsigned long mapbase,
> - unsigned long irq,
> - unsigned int tx_csum_limit)
> -{
> - fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
> - mapbase + 0x2000, SZ_16K - 1);
> - orion_ge01_shared_data.tx_csum_limit = tx_csum_limit;
> - ge_complete(&orion_ge01_shared_data,
> - orion_ge01_resources, irq, &orion_ge01_shared,
> - NULL,
> - eth_data, &orion_ge01);
> -}
> -
> -/*****************************************************************************
> - * GE10
> - ****************************************************************************/
> -static struct mv643xx_eth_shared_platform_data orion_ge10_shared_data;
> -
> -static struct resource orion_ge10_shared_resources[] = {
> - {
> - .name = "ge10 base",
> - }
> -};
> -
> -static struct platform_device orion_ge10_shared = {
> - .name = MV643XX_ETH_SHARED_NAME,
> - .id = 2,
> - .dev = {
> - .platform_data = &orion_ge10_shared_data,
> - },
> -};
> -
> -static struct resource orion_ge10_resources[] = {
> - {
> - .name = "ge10 irq",
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -static struct platform_device orion_ge10 = {
> - .name = MV643XX_ETH_NAME,
> - .id = 2,
> - .num_resources = 1,
> - .resource = orion_ge10_resources,
> - .dev = {
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - },
> -};
> -
> -void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
> - unsigned long mapbase,
> - unsigned long irq)
> -{
> - fill_resources(&orion_ge10_shared, orion_ge10_shared_resources,
> - mapbase + 0x2000, SZ_16K - 1);
> - ge_complete(&orion_ge10_shared_data,
> - orion_ge10_resources, irq, &orion_ge10_shared,
> - NULL,
> - eth_data, &orion_ge10);
> -}
> -
> -/*****************************************************************************
> - * GE11
> - ****************************************************************************/
> -static struct mv643xx_eth_shared_platform_data orion_ge11_shared_data;
> -
> -static struct resource orion_ge11_shared_resources[] = {
> - {
> - .name = "ge11 base",
> - },
> -};
> -
> -static struct platform_device orion_ge11_shared = {
> - .name = MV643XX_ETH_SHARED_NAME,
> - .id = 3,
> - .dev = {
> - .platform_data = &orion_ge11_shared_data,
> - },
> -};
> -
> -static struct resource orion_ge11_resources[] = {
> - {
> - .name = "ge11 irq",
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -static struct platform_device orion_ge11 = {
> - .name = MV643XX_ETH_NAME,
> - .id = 3,
> - .num_resources = 1,
> - .resource = orion_ge11_resources,
> - .dev = {
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - },
> -};
> -
> -void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
> - unsigned long mapbase,
> - unsigned long irq)
> -{
> - fill_resources(&orion_ge11_shared, orion_ge11_shared_resources,
> - mapbase + 0x2000, SZ_16K - 1);
> - ge_complete(&orion_ge11_shared_data,
> - orion_ge11_resources, irq, &orion_ge11_shared,
> - NULL,
> - eth_data, &orion_ge11);
> -}
> -
> -/*****************************************************************************
> - * I2C
> - ****************************************************************************/
> -static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
> - .freq_n = 3,
> - .timeout = 1000, /* Default timeout of 1 second */
> -};
> -
> -static struct resource orion_i2c_resources[2];
> -
> -static struct platform_device orion_i2c = {
> - .name = MV64XXX_I2C_CTLR_NAME,
> - .id = 0,
> - .dev = {
> - .platform_data = &orion_i2c_pdata,
> - },
> -};
> -
> -static struct mv64xxx_i2c_pdata orion_i2c_1_pdata = {
> - .freq_n = 3,
> - .timeout = 1000, /* Default timeout of 1 second */
> -};
> -
> -static struct resource orion_i2c_1_resources[2];
> -
> -static struct platform_device orion_i2c_1 = {
> - .name = MV64XXX_I2C_CTLR_NAME,
> - .id = 1,
> - .dev = {
> - .platform_data = &orion_i2c_1_pdata,
> - },
> -};
> -
> -void __init orion_i2c_init(unsigned long mapbase,
> - unsigned long irq,
> - unsigned long freq_m)
> -{
> - orion_i2c_pdata.freq_m = freq_m;
> - fill_resources_irq(&orion_i2c, orion_i2c_resources, mapbase,
> - SZ_32 - 1, irq);
> - platform_device_register(&orion_i2c);
> -}
> -
> -void __init orion_i2c_1_init(unsigned long mapbase,
> - unsigned long irq,
> - unsigned long freq_m)
> -{
> - orion_i2c_1_pdata.freq_m = freq_m;
> - fill_resources_irq(&orion_i2c_1, orion_i2c_1_resources, mapbase,
> - SZ_32 - 1, irq);
> - platform_device_register(&orion_i2c_1);
> -}
> -
> -/*****************************************************************************
> - * SPI
> - ****************************************************************************/
> -static struct resource orion_spi_resources;
> -
> -static struct platform_device orion_spi = {
> - .name = "orion_spi",
> - .id = 0,
> -};
> -
> -static struct resource orion_spi_1_resources;
> -
> -static struct platform_device orion_spi_1 = {
> - .name = "orion_spi",
> - .id = 1,
> -};
> -
> -/* Note: The SPI silicon core does have interrupts. However the
> - * current Linux software driver does not use interrupts. */
> -
> -void __init orion_spi_init(unsigned long mapbase)
> -{
> - fill_resources(&orion_spi, &orion_spi_resources,
> - mapbase, SZ_512 - 1);
> - platform_device_register(&orion_spi);
> -}
> -
> -void __init orion_spi_1_init(unsigned long mapbase)
> -{
> - fill_resources(&orion_spi_1, &orion_spi_1_resources,
> - mapbase, SZ_512 - 1);
> - platform_device_register(&orion_spi_1);
> -}
> -
> -/*****************************************************************************
> - * XOR
> - ****************************************************************************/
> -static u64 orion_xor_dmamask = DMA_BIT_MASK(32);
> -
> -/*****************************************************************************
> - * XOR0
> - ****************************************************************************/
> -static struct resource orion_xor0_shared_resources[] = {
> - {
> - .name = "xor 0 low",
> - .flags = IORESOURCE_MEM,
> - }, {
> - .name = "xor 0 high",
> - .flags = IORESOURCE_MEM,
> - }, {
> - .name = "irq channel 0",
> - .flags = IORESOURCE_IRQ,
> - }, {
> - .name = "irq channel 1",
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -static struct mv_xor_channel_data orion_xor0_channels_data[2];
> -
> -static struct mv_xor_platform_data orion_xor0_pdata = {
> - .channels = orion_xor0_channels_data,
> -};
> -
> -static struct platform_device orion_xor0_shared = {
> - .name = MV_XOR_NAME,
> - .id = 0,
> - .num_resources = ARRAY_SIZE(orion_xor0_shared_resources),
> - .resource = orion_xor0_shared_resources,
> - .dev = {
> - .dma_mask = &orion_xor_dmamask,
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - .platform_data = &orion_xor0_pdata,
> - },
> -};
> -
> -void __init orion_xor0_init(unsigned long mapbase_low,
> - unsigned long mapbase_high,
> - unsigned long irq_0,
> - unsigned long irq_1)
> -{
> - orion_xor0_shared_resources[0].start = mapbase_low;
> - orion_xor0_shared_resources[0].end = mapbase_low + 0xff;
> - orion_xor0_shared_resources[1].start = mapbase_high;
> - orion_xor0_shared_resources[1].end = mapbase_high + 0xff;
> -
> - orion_xor0_shared_resources[2].start = irq_0;
> - orion_xor0_shared_resources[2].end = irq_0;
> - orion_xor0_shared_resources[3].start = irq_1;
> - orion_xor0_shared_resources[3].end = irq_1;
> -
> - dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[0].cap_mask);
> - dma_cap_set(DMA_XOR, orion_xor0_channels_data[0].cap_mask);
> -
> - dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[1].cap_mask);
> - dma_cap_set(DMA_XOR, orion_xor0_channels_data[1].cap_mask);
> -
> - platform_device_register(&orion_xor0_shared);
> -}
> -
> -/*****************************************************************************
> - * XOR1
> - ****************************************************************************/
> -static struct resource orion_xor1_shared_resources[] = {
> - {
> - .name = "xor 1 low",
> - .flags = IORESOURCE_MEM,
> - }, {
> - .name = "xor 1 high",
> - .flags = IORESOURCE_MEM,
> - }, {
> - .name = "irq channel 0",
> - .flags = IORESOURCE_IRQ,
> - }, {
> - .name = "irq channel 1",
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -static struct mv_xor_channel_data orion_xor1_channels_data[2];
> -
> -static struct mv_xor_platform_data orion_xor1_pdata = {
> - .channels = orion_xor1_channels_data,
> -};
> -
> -static struct platform_device orion_xor1_shared = {
> - .name = MV_XOR_NAME,
> - .id = 1,
> - .num_resources = ARRAY_SIZE(orion_xor1_shared_resources),
> - .resource = orion_xor1_shared_resources,
> - .dev = {
> - .dma_mask = &orion_xor_dmamask,
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - .platform_data = &orion_xor1_pdata,
> - },
> -};
> -
> -void __init orion_xor1_init(unsigned long mapbase_low,
> - unsigned long mapbase_high,
> - unsigned long irq_0,
> - unsigned long irq_1)
> -{
> - orion_xor1_shared_resources[0].start = mapbase_low;
> - orion_xor1_shared_resources[0].end = mapbase_low + 0xff;
> - orion_xor1_shared_resources[1].start = mapbase_high;
> - orion_xor1_shared_resources[1].end = mapbase_high + 0xff;
> -
> - orion_xor1_shared_resources[2].start = irq_0;
> - orion_xor1_shared_resources[2].end = irq_0;
> - orion_xor1_shared_resources[3].start = irq_1;
> - orion_xor1_shared_resources[3].end = irq_1;
> -
> - dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[0].cap_mask);
> - dma_cap_set(DMA_XOR, orion_xor1_channels_data[0].cap_mask);
> -
> - dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[1].cap_mask);
> - dma_cap_set(DMA_XOR, orion_xor1_channels_data[1].cap_mask);
> -
> - platform_device_register(&orion_xor1_shared);
> -}
> -
> -/*****************************************************************************
> - * EHCI
> - ****************************************************************************/
> -static struct orion_ehci_data orion_ehci_data;
> -static u64 ehci_dmamask = DMA_BIT_MASK(32);
> -
> -
> -/*****************************************************************************
> - * EHCI0
> - ****************************************************************************/
> -static struct resource orion_ehci_resources[2];
> -
> -static struct platform_device orion_ehci = {
> - .name = "orion-ehci",
> - .id = 0,
> - .dev = {
> - .dma_mask = &ehci_dmamask,
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - .platform_data = &orion_ehci_data,
> - },
> -};
> -
> -void __init orion_ehci_init(unsigned long mapbase,
> - unsigned long irq,
> - enum orion_ehci_phy_ver phy_version)
> -{
> - orion_ehci_data.phy_version = phy_version;
> - fill_resources_irq(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
> - irq);
> -
> - platform_device_register(&orion_ehci);
> -}
> -
> -/*****************************************************************************
> - * EHCI1
> - ****************************************************************************/
> -static struct resource orion_ehci_1_resources[2];
> -
> -static struct platform_device orion_ehci_1 = {
> - .name = "orion-ehci",
> - .id = 1,
> - .dev = {
> - .dma_mask = &ehci_dmamask,
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - .platform_data = &orion_ehci_data,
> - },
> -};
> -
> -void __init orion_ehci_1_init(unsigned long mapbase,
> - unsigned long irq)
> -{
> - fill_resources_irq(&orion_ehci_1, orion_ehci_1_resources,
> - mapbase, SZ_4K - 1, irq);
> -
> - platform_device_register(&orion_ehci_1);
> -}
> -
> -/*****************************************************************************
> - * EHCI2
> - ****************************************************************************/
> -static struct resource orion_ehci_2_resources[2];
> -
> -static struct platform_device orion_ehci_2 = {
> - .name = "orion-ehci",
> - .id = 2,
> - .dev = {
> - .dma_mask = &ehci_dmamask,
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - .platform_data = &orion_ehci_data,
> - },
> -};
> -
> -void __init orion_ehci_2_init(unsigned long mapbase,
> - unsigned long irq)
> -{
> - fill_resources_irq(&orion_ehci_2, orion_ehci_2_resources,
> - mapbase, SZ_4K - 1, irq);
> -
> - platform_device_register(&orion_ehci_2);
> -}
> -
> -/*****************************************************************************
> - * SATA
> - ****************************************************************************/
> -static struct resource orion_sata_resources[2] = {
> - {
> - .name = "sata base",
> - }, {
> - .name = "sata irq",
> - },
> -};
> -
> -static struct platform_device orion_sata = {
> - .name = "sata_mv",
> - .id = 0,
> - .dev = {
> - .coherent_dma_mask = DMA_BIT_MASK(32),
> - },
> -};
> -
> -void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
> - unsigned long mapbase,
> - unsigned long irq)
> -{
> - orion_sata.dev.platform_data = sata_data;
> - fill_resources_irq(&orion_sata, orion_sata_resources,
> - mapbase, 0x5000 - 1, irq);
> -
> - platform_device_register(&orion_sata);
> -}
> -
> -/*****************************************************************************
> - * Cryptographic Engines and Security Accelerator (CESA)
> - ****************************************************************************/
> -static struct resource orion_crypto_resources[] = {
> - {
> - .name = "regs",
> - }, {
> - .name = "crypto interrupt",
> - }, {
> - .name = "sram",
> - .flags = IORESOURCE_MEM,
> - },
> -};
> -
> -static struct platform_device orion_crypto = {
> - .name = "mv_crypto",
> - .id = -1,
> -};
> -
> -void __init orion_crypto_init(unsigned long mapbase,
> - unsigned long srambase,
> - unsigned long sram_size,
> - unsigned long irq)
> -{
> - fill_resources_irq(&orion_crypto, orion_crypto_resources,
> - mapbase, 0xffff, irq);
> - orion_crypto.num_resources = 3;
> - orion_crypto_resources[2].start = srambase;
> - orion_crypto_resources[2].end = srambase + sram_size - 1;
> -
> - platform_device_register(&orion_crypto);
> -}
> diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
> deleted file mode 100644
> index b76c06569fe5..000000000000
> --- a/arch/arm/plat-orion/include/plat/addr-map.h
> +++ /dev/null
> @@ -1,54 +0,0 @@
> -/*
> - * arch/arm/plat-orion/include/plat/addr-map.h
> - *
> - * Marvell Orion SoC address map handling.
> - *
> - * This file is licensed under the terms of the GNU General Public
> - * License version 2. This program is licensed "as is" without any
> - * warranty of any kind, whether express or implied.
> - */
> -
> -#ifndef __PLAT_ADDR_MAP_H
> -#define __PLAT_ADDR_MAP_H
> -
> -extern struct mbus_dram_target_info orion_mbus_dram_info;
> -
> -struct orion_addr_map_cfg {
> - const int num_wins; /* Total number of windows */
> - const int remappable_wins;
> - void __iomem *bridge_virt_base;
> - int hw_io_coherency;
> -
> - /* If NULL, the default cpu_win_can_remap will be used, using
> - the value in remappable_wins */
> - int (*cpu_win_can_remap) (const struct orion_addr_map_cfg *cfg,
> - const int win);
> - /* If NULL, the default win_cfg_base will be used, using the
> - value in bridge_virt_base */
> - void __iomem *(*win_cfg_base) (const struct orion_addr_map_cfg *cfg,
> - const int win);
> -};
> -
> -/*
> - * Information needed to setup one address mapping.
> - */
> -struct orion_addr_map_info {
> - const int win;
> - const u32 base;
> - const u32 size;
> - const u8 target;
> - const u8 attr;
> - const int remap;
> -};
> -
> -void __init orion_config_wins(struct orion_addr_map_cfg *cfg,
> - const struct orion_addr_map_info *info);
> -
> -void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
> - const int win, const u32 base,
> - const u32 size, const u8 target,
> - const u8 attr, const int remap);
> -
> -void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
> - const void __iomem *ddr_window_cpu_base);
> -#endif
> diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
> deleted file mode 100644
> index d2aad95d20cb..000000000000
> --- a/arch/arm/plat-orion/include/plat/common.h
> +++ /dev/null
> @@ -1,104 +0,0 @@
> -/*
> - * arch/arm/plat-orion/include/plat/common.h
> - *
> - * Marvell Orion SoC common setup code used by different mach-/common.c
> - *
> - * This file is licensed under the terms of the GNU General Public
> - * License version 2. This program is licensed "as is" without any
> - * warranty of any kind, whether express or implied.
> - */
> -
> -#ifndef __PLAT_COMMON_H
> -#include <linux/mv643xx_eth.h>
> -#include <linux/platform_data/usb-ehci-orion.h>
> -
> -struct mv_sata_platform_data;
> -
> -void __init orion_uart0_init(void __iomem *membase,
> - resource_size_t mapbase,
> - unsigned int irq,
> - struct clk *clk);
> -
> -void __init orion_uart1_init(void __iomem *membase,
> - resource_size_t mapbase,
> - unsigned int irq,
> - struct clk *clk);
> -
> -void __init orion_uart2_init(void __iomem *membase,
> - resource_size_t mapbase,
> - unsigned int irq,
> - struct clk *clk);
> -
> -void __init orion_uart3_init(void __iomem *membase,
> - resource_size_t mapbase,
> - unsigned int irq,
> - struct clk *clk);
> -
> -void __init orion_rtc_init(unsigned long mapbase,
> - unsigned long irq);
> -
> -void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
> - unsigned long mapbase,
> - unsigned long irq,
> - unsigned long irq_err,
> - unsigned int tx_csum_limit);
> -
> -void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
> - unsigned long mapbase,
> - unsigned long irq,
> - unsigned int tx_csum_limit);
> -
> -void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
> - unsigned long mapbase,
> - unsigned long irq);
> -
> -void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
> - unsigned long mapbase,
> - unsigned long irq);
> -
> -void __init orion_i2c_init(unsigned long mapbase,
> - unsigned long irq,
> - unsigned long freq_m);
> -
> -void __init orion_i2c_1_init(unsigned long mapbase,
> - unsigned long irq,
> - unsigned long freq_m);
> -
> -void __init orion_spi_init(unsigned long mapbase);
> -
> -void __init orion_spi_1_init(unsigned long mapbase);
> -
> -void __init orion_xor0_init(unsigned long mapbase_low,
> - unsigned long mapbase_high,
> - unsigned long irq_0,
> - unsigned long irq_1);
> -
> -void __init orion_xor1_init(unsigned long mapbase_low,
> - unsigned long mapbase_high,
> - unsigned long irq_0,
> - unsigned long irq_1);
> -
> -void __init orion_ehci_init(unsigned long mapbase,
> - unsigned long irq,
> - enum orion_ehci_phy_ver phy_version);
> -
> -void __init orion_ehci_1_init(unsigned long mapbase,
> - unsigned long irq);
> -
> -void __init orion_ehci_2_init(unsigned long mapbase,
> - unsigned long irq);
> -
> -void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
> - unsigned long mapbase,
> - unsigned long irq);
> -
> -void __init orion_crypto_init(unsigned long mapbase,
> - unsigned long srambase,
> - unsigned long sram_size,
> - unsigned long irq);
> -
> -void __init orion_clkdev_add(const char *con_id, const char *dev_id,
> - struct clk *clk);
> -
> -void __init orion_clkdev_init(struct clk *tclk);
> -#endif
> diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h
> deleted file mode 100644
> index 07527e417c62..000000000000
> --- a/arch/arm/plat-orion/include/plat/time.h
> +++ /dev/null
> @@ -1,20 +0,0 @@
> -/*
> - * arch/arm/plat-orion/include/plat/time.h
> - *
> - * Marvell Orion SoC time handling.
> - *
> - * This file is licensed under the terms of the GNU General Public
> - * License version 2. This program is licensed "as is" without any
> - * warranty of any kind, whether express or implied.
> - */
> -
> -#ifndef __PLAT_TIME_H
> -#define __PLAT_TIME_H
> -
> -void orion_time_set_base(void __iomem *timer_base);
> -
> -void orion_time_init(void __iomem *bridge_base, u32 bridge_timer1_clr_mask,
> - unsigned int irq, unsigned int tclk);
> -
> -
> -#endif
> diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
> index 8b8c06d2e9c4..e817f20409c4 100644
> --- a/arch/arm/plat-orion/pcie.c
> +++ b/arch/arm/plat-orion/pcie.c
> @@ -13,7 +13,6 @@
> #include <linux/mbus.h>
> #include <asm/mach/pci.h>
> #include <plat/pcie.h>
> -#include <plat/addr-map.h>
> #include <linux/delay.h>
>
> /*
> diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
> deleted file mode 100644
> index 509d4824dc1c..000000000000
> --- a/arch/arm/plat-orion/time.c
> +++ /dev/null
> @@ -1,238 +0,0 @@
> -/*
> - * arch/arm/plat-orion/time.c
> - *
> - * Marvell Orion SoC timer handling.
> - *
> - * This file is licensed under the terms of the GNU General Public
> - * License version 2. This program is licensed "as is" without any
> - * warranty of any kind, whether express or implied.
> - *
> - * Timer 0 is used as free-running clocksource, while timer 1 is
> - * used as clock_event_device.
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/timer.h>
> -#include <linux/clockchips.h>
> -#include <linux/interrupt.h>
> -#include <linux/irq.h>
> -#include <linux/sched_clock.h>
> -#include <plat/time.h>
> -#include <asm/delay.h>
> -
> -/*
> - * MBus bridge block registers.
> - */
> -#define BRIDGE_CAUSE_OFF 0x0110
> -#define BRIDGE_MASK_OFF 0x0114
> -#define BRIDGE_INT_TIMER0 0x0002
> -#define BRIDGE_INT_TIMER1 0x0004
> -
> -
> -/*
> - * Timer block registers.
> - */
> -#define TIMER_CTRL_OFF 0x0000
> -#define TIMER0_EN 0x0001
> -#define TIMER0_RELOAD_EN 0x0002
> -#define TIMER1_EN 0x0004
> -#define TIMER1_RELOAD_EN 0x0008
> -#define TIMER0_RELOAD_OFF 0x0010
> -#define TIMER0_VAL_OFF 0x0014
> -#define TIMER1_RELOAD_OFF 0x0018
> -#define TIMER1_VAL_OFF 0x001c
> -
> -
> -/*
> - * SoC-specific data.
> - */
> -static void __iomem *bridge_base;
> -static u32 bridge_timer1_clr_mask;
> -static void __iomem *timer_base;
> -
> -
> -/*
> - * Number of timer ticks per jiffy.
> - */
> -static u32 ticks_per_jiffy;
> -
> -
> -/*
> - * Orion's sched_clock implementation. It has a resolution of
> - * at least 7.5ns (133MHz TCLK).
> - */
> -
> -static u64 notrace orion_read_sched_clock(void)
> -{
> - return ~readl(timer_base + TIMER0_VAL_OFF);
> -}
> -
> -/*
> - * Clockevent handling.
> - */
> -static int
> -orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
> -{
> - unsigned long flags;
> - u32 u;
> -
> - if (delta == 0)
> - return -ETIME;
> -
> - local_irq_save(flags);
> -
> - /*
> - * Clear and enable clockevent timer interrupt.
> - */
> - writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
> -
> - u = readl(bridge_base + BRIDGE_MASK_OFF);
> - u |= BRIDGE_INT_TIMER1;
> - writel(u, bridge_base + BRIDGE_MASK_OFF);
> -
> - /*
> - * Setup new clockevent timer value.
> - */
> - writel(delta, timer_base + TIMER1_VAL_OFF);
> -
> - /*
> - * Enable the timer.
> - */
> - u = readl(timer_base + TIMER_CTRL_OFF);
> - u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
> - writel(u, timer_base + TIMER_CTRL_OFF);
> -
> - local_irq_restore(flags);
> -
> - return 0;
> -}
> -
> -static int orion_clkevt_shutdown(struct clock_event_device *evt)
> -{
> - unsigned long flags;
> - u32 u;
> -
> - local_irq_save(flags);
> -
> - /* Disable timer */
> - u = readl(timer_base + TIMER_CTRL_OFF);
> - writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
> -
> - /* Disable timer interrupt */
> - u = readl(bridge_base + BRIDGE_MASK_OFF);
> - writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
> -
> - /* ACK pending timer interrupt */
> - writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
> -
> - local_irq_restore(flags);
> -
> - return 0;
> -}
> -
> -static int orion_clkevt_set_periodic(struct clock_event_device *evt)
> -{
> - unsigned long flags;
> - u32 u;
> -
> - local_irq_save(flags);
> -
> - /* Setup timer to fire at 1/HZ intervals */
> - writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
> - writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
> -
> - /* Enable timer interrupt */
> - u = readl(bridge_base + BRIDGE_MASK_OFF);
> - writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
> -
> - /* Enable timer */
> - u = readl(timer_base + TIMER_CTRL_OFF);
> - writel(u | TIMER1_EN | TIMER1_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
> -
> - local_irq_restore(flags);
> -
> - return 0;
> -}
> -
> -static struct clock_event_device orion_clkevt = {
> - .name = "orion_tick",
> - .features = CLOCK_EVT_FEAT_ONESHOT |
> - CLOCK_EVT_FEAT_PERIODIC,
> - .rating = 300,
> - .set_next_event = orion_clkevt_next_event,
> - .set_state_shutdown = orion_clkevt_shutdown,
> - .set_state_periodic = orion_clkevt_set_periodic,
> - .set_state_oneshot = orion_clkevt_shutdown,
> - .tick_resume = orion_clkevt_shutdown,
> -};
> -
> -static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
> -{
> - /*
> - * ACK timer interrupt and call event handler.
> - */
> - writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
> - orion_clkevt.event_handler(&orion_clkevt);
> -
> - return IRQ_HANDLED;
> -}
> -
> -void __init
> -orion_time_set_base(void __iomem *_timer_base)
> -{
> - timer_base = _timer_base;
> -}
> -
> -static unsigned long orion_delay_timer_read(void)
> -{
> - return ~readl(timer_base + TIMER0_VAL_OFF);
> -}
> -
> -static struct delay_timer orion_delay_timer = {
> - .read_current_timer = orion_delay_timer_read,
> -};
> -
> -void __init
> -orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
> - unsigned int irq, unsigned int tclk)
> -{
> - u32 u;
> -
> - /*
> - * Set SoC-specific data.
> - */
> - bridge_base = _bridge_base;
> - bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
> -
> - ticks_per_jiffy = (tclk + HZ/2) / HZ;
> -
> - orion_delay_timer.freq = tclk;
> - register_current_timer_delay(&orion_delay_timer);
> -
> - /*
> - * Set scale and timer for sched_clock.
> - */
> - sched_clock_register(orion_read_sched_clock, 32, tclk);
> -
> - /*
> - * Setup free-running clocksource timer (interrupts
> - * disabled).
> - */
> - writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
> - writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
> - u = readl(bridge_base + BRIDGE_MASK_OFF);
> - writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
> - u = readl(timer_base + TIMER_CTRL_OFF);
> - writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
> - clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource",
> - tclk, 300, 32, clocksource_mmio_readl_down);
> -
> - /*
> - * Setup clockevent timer (interrupt-driven).
> - */
> - if (request_irq(irq, orion_timer_interrupt, IRQF_TIMER, "orion_tick",
> - NULL))
> - pr_err("Failed to request irq %u (orion_tick)\n", irq);
> - orion_clkevt.cpumask = cpumask_of(0);
> - clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe);
> -}
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> index 28ca856ecc75..434cce3efd96 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -471,8 +471,7 @@ config SATA_HIGHBANK
>
> config SATA_MV
> tristate "Marvell SATA support"
> - depends on PCI || ARCH_DOVE || ARCH_MV78XX0 || \
> - ARCH_MVEBU || ARCH_ORION5X || COMPILE_TEST
> + depends on PCI || ARCH_MVEBU || ARCH_ORION5X || COMPILE_TEST
> select GENERIC_PHY
> select SATA_HOST
> help
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 4f060d3e5636..d06903635335 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -330,7 +330,7 @@ config MMC_SDHCI_ESDHC_IMX
>
> config MMC_SDHCI_DOVE
> tristate "SDHCI support on Marvell's Dove SoC"
> - depends on ARCH_DOVE || MACH_DOVE || COMPILE_TEST
> + depends on MACH_DOVE || COMPILE_TEST
> depends on MMC_SDHCI_PLTFM
> select MMC_SDHCI_IO_ACCESSORS
> help
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index d246bbe37948..7e550c474b7a 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -197,7 +197,7 @@ config PCI_LOONGSON
>
> config PCI_MVEBU
> tristate "Marvell EBU PCIe controller"
> - depends on ARCH_MVEBU || ARCH_DOVE || COMPILE_TEST
> + depends on ARCH_MVEBU || COMPILE_TEST
> depends on MVEBU_MBUS
> depends on ARM
> depends on OF
> diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig
> index bccd72dccb77..c29d2d28ae55 100644
> --- a/drivers/phy/marvell/Kconfig
> +++ b/drivers/phy/marvell/Kconfig
> @@ -77,7 +77,7 @@ config PHY_MVEBU_CP110_UTMI
>
> config PHY_MVEBU_SATA
> def_bool y
> - depends on ARCH_DOVE || MACH_DOVE || MACH_KIRKWOOD
> + depends on MACH_DOVE || MACH_KIRKWOOD
> depends on OF
> select GENERIC_PHY
>
> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
> index 55ffee3d75ce..5cb6cdfe6015 100644
> --- a/drivers/rtc/Kconfig
> +++ b/drivers/rtc/Kconfig
> @@ -1703,7 +1703,7 @@ config RTC_DRV_STARFIRE
>
> config RTC_DRV_MV
> tristate "Marvell SoC RTC"
> - depends on ARCH_DOVE || ARCH_MVEBU || COMPILE_TEST
> + depends on ARCH_MVEBU || COMPILE_TEST
> help
> If you say yes here you will get support for the in-chip RTC
> that can be found in some of Marvell's SoC devices, such as
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index c9e689080ceb..6411b96d584c 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -9,7 +9,6 @@ obj-$(CONFIG_ARCH_AT91) += atmel/
> obj-y += bcm/
> obj-$(CONFIG_ARCH_CANAAN) += canaan/
> obj-$(CONFIG_EP93XX_SOC) += cirrus/
> -obj-$(CONFIG_ARCH_DOVE) += dove/
> obj-$(CONFIG_MACH_DOVE) += dove/
> obj-y += fsl/
> obj-y += fujitsu/
> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
> index 810eeccedfba..8cef9b658191 100644
> --- a/drivers/thermal/Kconfig
> +++ b/drivers/thermal/Kconfig
> @@ -391,7 +391,7 @@ config KIRKWOOD_THERMAL
>
> config DOVE_THERMAL
> tristate "Temperature sensor on Marvell Dove SoCs"
> - depends on ARCH_DOVE || MACH_DOVE || COMPILE_TEST
> + depends on MACH_DOVE || COMPILE_TEST
> depends on HAS_IOMEM
> depends on OF
> help
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index 0ab0dcc6d27d..d83bfb189705 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -690,7 +690,7 @@ config K3_RTI_WATCHDOG
>
> config ORION_WATCHDOG
> tristate "Orion watchdog"
> - depends on ARCH_ORION5X || ARCH_DOVE || MACH_DOVE || ARCH_MVEBU || COMPILE_TEST
> + depends on ARCH_ORION5X || MACH_DOVE || ARCH_MVEBU || COMPILE_TEST
> depends on ARM
> select WATCHDOG_CORE
> help
> diff --git a/sound/soc/kirkwood/Kconfig b/sound/soc/kirkwood/Kconfig
> index 924072e402c8..d59c5bb0b391 100644
> --- a/sound/soc/kirkwood/Kconfig
> +++ b/sound/soc/kirkwood/Kconfig
> @@ -3,7 +3,7 @@ menu "Kirkwood"
>
> config SND_KIRKWOOD_SOC
> tristate "SoC Audio for the Marvell Kirkwood and Dove chips"
> - depends on ARCH_DOVE || ARCH_MVEBU || COMPILE_TEST
> + depends on ARCH_MVEBU || COMPILE_TEST
> help
> Say Y or M if you want to add support for codecs attached to
> the Kirkwood I2S interface. You will also need to select the
> --
> 2.53.0
>
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 05/13] ARM: orion/dove/mv78xx0: remove all board files
2026-09-08 15:27 ` [PATCH 05/13] ARM: orion/dove/mv78xx0: remove all " Arnd Bergmann
2026-09-08 15:34 ` Mark Brown
2026-09-08 16:12 ` Ulf Hansson
@ 2026-09-08 16:18 ` Andrew Lunn
2026-09-08 17:33 ` Linus Walleij
` (2 subsequent siblings)
5 siblings, 0 replies; 70+ messages in thread
From: Andrew Lunn @ 2026-09-08 16:18 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Arnd Bergmann, Rob Herring,
Conor Dooley, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Sebastian Hesselbarth, Gregory Clement, Robert Jarzmik,
Kristoffer Ericson, Ethan Nelson-Moore, Geert Uytterhoeven,
Alexander Sverdlin, Shawn Guo, Karl Mehltretter,
David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Alexander Clouter,
Jeremy J. Peper, Damien Le Moal, Niklas Cassel, Ulf Hansson,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
Vinod Koul, Rafael J. Wysocki, Daniel Lezcano, Guenter Roeck,
Mark Brown, Bartosz Golaszewski, Thomas Weissschuh, linux-ide,
linux-mmc, linux-pci, linux-phy, linux-rtc, linux-pm,
linux-watchdog, linux-sound, linux-gpio
On Tue, Sep 08, 2026 at 05:27:55PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The 'orion' platform is the predecessor to what linux now calls the
> 'mvebu' line of Marvell SoCs, and originally covered orion5x,
> mv78xx0, kirkwood, dove and a few others that do not have any
> upstream support at the moment.
>
> Only a few board files remain here, these are the ones left
> in 2022 board file purge because they had some level of support
> in Debian or OpenWRT, mostly for commercial NAS or router boxes.
> This distro support is now gone, and nobody has converted the
> board files to devicetree, though the orion5x and dove platforms
> also come with devicetree support for some other machines.
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 05/13] ARM: orion/dove/mv78xx0: remove all board files
2026-09-08 15:27 ` [PATCH 05/13] ARM: orion/dove/mv78xx0: remove all " Arnd Bergmann
` (2 preceding siblings ...)
2026-09-08 16:18 ` Andrew Lunn
@ 2026-09-08 17:33 ` Linus Walleij
2026-09-08 20:14 ` Niklas Cassel
2026-09-09 12:54 ` Gregory CLEMENT
5 siblings, 0 replies; 70+ messages in thread
From: Linus Walleij @ 2026-09-08 17:33 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Russell King,
Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Alexander Clouter,
Jeremy J. Peper, Damien Le Moal, Niklas Cassel, Ulf Hansson,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
Vinod Koul, Rafael J. Wysocki, Daniel Lezcano, Guenter Roeck,
Mark Brown, Bartosz Golaszewski, Thomas Weissschuh, linux-ide,
linux-mmc, linux-pci, linux-phy, linux-rtc, linux-pm,
linux-watchdog, linux-sound, linux-gpio
On Tue, Sep 8, 2026 at 5:29 PM Arnd Bergmann <arnd@kernel.org> wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The 'orion' platform is the predecessor to what linux now calls the
> 'mvebu' line of Marvell SoCs, and originally covered orion5x,
> mv78xx0, kirkwood, dove and a few others that do not have any
> upstream support at the moment.
>
> Only a few board files remain here, these are the ones left
> in 2022 board file purge because they had some level of support
> in Debian or OpenWRT, mostly for commercial NAS or router boxes.
> This distro support is now gone, and nobody has converted the
> board files to devicetree, though the orion5x and dove platforms
> also come with devicetree support for some other machines.
>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Cc: Gregory Clement <gregory.clement@bootlin.com>
> Cc: Alexander Clouter <alex@digriz.org.uk>
> Cc: Jeremy J. Peper <jeremy@jeremypeper.com>
> Cc: Damien Le Moal <dlemoal@kernel.org>
> Cc: Niklas Cassel <cassel@kernel.org>
> Cc: Ulf Hansson <ulfh@kernel.org>
> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
> Cc: Manivannan Sadhasivam <mani@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Cc: "Rafael J. Wysocki" <rafael@kernel.org>
> Cc: Daniel Lezcano <daniel.lezcano@kernel.org>
> Cc: Guenter Roeck <linux@roeck-us.net>
> Cc: Mark Brown <broonie@kernel.org>
> Cc: Linus Walleij <linusw@kernel.org>
> Cc: Bartosz Golaszewski <brgl@kernel.org>
> Cc: Thomas Weissschuh <thomas.weissschuh@linutronix.de>
> Cc: linux-ide@vger.kernel.org
> Cc: linux-mmc@vger.kernel.org
> Cc: linux-pci@vger.kernel.org
> Cc: linux-phy@lists.infradead.org
> Cc: linux-rtc@vger.kernel.org
> Cc: linux-pm@vger.kernel.org
> Cc: linux-watchdog@vger.kernel.org
> Cc: linux-sound@vger.kernel.org
> Cc: linux-gpio@vger.kernel.org
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linusw@kernel.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 05/13] ARM: orion/dove/mv78xx0: remove all board files
2026-09-08 15:27 ` [PATCH 05/13] ARM: orion/dove/mv78xx0: remove all " Arnd Bergmann
` (3 preceding siblings ...)
2026-09-08 17:33 ` Linus Walleij
@ 2026-09-08 20:14 ` Niklas Cassel
2026-09-09 12:54 ` Gregory CLEMENT
5 siblings, 0 replies; 70+ messages in thread
From: Niklas Cassel @ 2026-09-08 20:14 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Arnd Bergmann, Rob Herring,
Conor Dooley, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Alexander Clouter,
Jeremy J. Peper, Damien Le Moal, Ulf Hansson,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
Vinod Koul, Rafael J. Wysocki, Daniel Lezcano, Guenter Roeck,
Mark Brown, Bartosz Golaszewski, Thomas Weissschuh, linux-ide,
linux-mmc, linux-pci, linux-phy, linux-rtc, linux-pm,
linux-watchdog, linux-sound, linux-gpio
On Tue, Sep 08, 2026 at 05:27:55PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The 'orion' platform is the predecessor to what linux now calls the
> 'mvebu' line of Marvell SoCs, and originally covered orion5x,
> mv78xx0, kirkwood, dove and a few others that do not have any
> upstream support at the moment.
>
> Only a few board files remain here, these are the ones left
> in 2022 board file purge because they had some level of support
> in Debian or OpenWRT, mostly for commercial NAS or router boxes.
> This distro support is now gone, and nobody has converted the
> board files to devicetree, though the orion5x and dove platforms
> also come with devicetree support for some other machines.
>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Cc: Gregory Clement <gregory.clement@bootlin.com>
> Cc: Alexander Clouter <alex@digriz.org.uk>
> Cc: Jeremy J. Peper <jeremy@jeremypeper.com>
> Cc: Damien Le Moal <dlemoal@kernel.org>
> Cc: Niklas Cassel <cassel@kernel.org>
> Cc: Ulf Hansson <ulfh@kernel.org>
> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
> Cc: Manivannan Sadhasivam <mani@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Cc: "Rafael J. Wysocki" <rafael@kernel.org>
> Cc: Daniel Lezcano <daniel.lezcano@kernel.org>
> Cc: Guenter Roeck <linux@roeck-us.net>
> Cc: Mark Brown <broonie@kernel.org>
> Cc: Linus Walleij <linusw@kernel.org>
> Cc: Bartosz Golaszewski <brgl@kernel.org>
> Cc: Thomas Weissschuh <thomas.weissschuh@linutronix.de>
> Cc: linux-ide@vger.kernel.org
> Cc: linux-mmc@vger.kernel.org
> Cc: linux-pci@vger.kernel.org
> Cc: linux-phy@lists.infradead.org
> Cc: linux-rtc@vger.kernel.org
> Cc: linux-pm@vger.kernel.org
> Cc: linux-watchdog@vger.kernel.org
> Cc: linux-sound@vger.kernel.org
> Cc: linux-gpio@vger.kernel.org
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Niklas Cassel <cassel@kernel.org> # ata parts
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 05/13] ARM: orion/dove/mv78xx0: remove all board files
2026-09-08 15:27 ` [PATCH 05/13] ARM: orion/dove/mv78xx0: remove all " Arnd Bergmann
` (4 preceding siblings ...)
2026-09-08 20:14 ` Niklas Cassel
@ 2026-09-09 12:54 ` Gregory CLEMENT
5 siblings, 0 replies; 70+ messages in thread
From: Gregory CLEMENT @ 2026-09-09 12:54 UTC (permalink / raw)
To: Arnd Bergmann, Krzysztof Kozlowski, Alexandre Belloni,
Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Robert Jarzmik,
Kristoffer Ericson, Ethan Nelson-Moore, Geert Uytterhoeven,
Alexander Sverdlin, Shawn Guo, Karl Mehltretter,
David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Alexander Clouter,
Jeremy J. Peper, Damien Le Moal, Niklas Cassel, Ulf Hansson,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
Vinod Koul, Rafael J. Wysocki, Daniel Lezcano, Guenter Roeck,
Mark Brown, Bartosz Golaszewski, Thomas Weissschuh, linux-ide,
linux-mmc, linux-pci, linux-phy, linux-rtc, linux-pm,
linux-watchdog, linux-sound, linux-gpio
Arnd Bergmann <arnd@kernel.org> writes:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The 'orion' platform is the predecessor to what linux now calls the
> 'mvebu' line of Marvell SoCs, and originally covered orion5x,
> mv78xx0, kirkwood, dove and a few others that do not have any
> upstream support at the moment.
>
> Only a few board files remain here, these are the ones left
> in 2022 board file purge because they had some level of support
> in Debian or OpenWRT, mostly for commercial NAS or router boxes.
> This distro support is now gone, and nobody has converted the
> board files to devicetree, though the orion5x and dove platforms
> also come with devicetree support for some other machines.
>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Thanks,
Gregory
--
Grégory CLEMENT, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH 06/13] ARM: omap2: remove omap24xx support
2026-09-08 15:27 [PATCH 00/13] ARM: deprecated platform removal Arnd Bergmann
` (4 preceding siblings ...)
2026-09-08 15:27 ` [PATCH 05/13] ARM: orion/dove/mv78xx0: remove all " Arnd Bergmann
@ 2026-09-08 15:27 ` Arnd Bergmann
2026-09-08 17:18 ` Aaro Koskinen
` (3 more replies)
2026-09-08 15:27 ` [PATCH 07/13] ARM: imx: remove i.MX31 SoC support Arnd Bergmann
` (7 subsequent siblings)
13 siblings, 4 replies; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 15:27 UTC (permalink / raw)
To: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Paul Walmsley,
Herbert Xu, David S. Miller, Mauro Carvalho Chehab,
Kyungmin Park, Helge Deller, Tero Kristo, Stephen Boyd,
Thomas Zimmermann, linux-media, linux-mtd, linux-fbdev,
dri-devel, linux-clk
From: Arnd Bergmann <arnd@arndb.de>
The omap24xx SoC platform was used in the Nokia N800 and N810 tablets
released on 2007 and was among the first ARMv6 CPUs in products that
made it into products.
Unfortunately the early ARM1136r0 CPU cores had a number of quirks that
caused a disproportionate amount of work to keep them compatible with
later ARMv6K/v7/v8 implementations.
Drop the support for this SoC in order to allow removing ARM1136r0.
Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: Andreas Kemnade <andreas@kemnade.info>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: Roger Quadros <rogerq@kernel.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Helge Deller <deller@gmx.de>
Cc: Tero Kristo <kristo@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-media@vger.kernel.org
Cc: linux-mtd@lists.infradead.org
Cc: linux-fbdev@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
MAINTAINERS | 2 -
arch/arm/boot/dts/ti/omap/Makefile | 6 -
arch/arm/boot/dts/ti/omap/omap2.dtsi | 338 -----
.../arm/boot/dts/ti/omap/omap2420-clocks.dtsi | 267 ----
arch/arm/boot/dts/ti/omap/omap2420-h4.dts | 63 -
arch/arm/boot/dts/ti/omap/omap2420-n800.dts | 9 -
.../boot/dts/ti/omap/omap2420-n810-wimax.dts | 9 -
arch/arm/boot/dts/ti/omap/omap2420-n810.dts | 75 -
.../dts/ti/omap/omap2420-n8x0-common.dtsi | 123 --
arch/arm/boot/dts/ti/omap/omap2420.dtsi | 262 ----
.../arm/boot/dts/ti/omap/omap2430-clocks.dtsi | 341 -----
arch/arm/boot/dts/ti/omap/omap2430-sdp.dts | 70 -
arch/arm/boot/dts/ti/omap/omap2430.dtsi | 366 -----
.../arm/boot/dts/ti/omap/omap24xx-clocks.dtsi | 1241 -----------------
arch/arm/configs/omap2plus_defconfig | 2 -
arch/arm/mach-omap2/Kconfig | 62 +-
arch/arm/mach-omap2/Makefile | 63 +-
arch/arm/mach-omap2/board-generic.c | 34 -
arch/arm/mach-omap2/board-n8x0.c | 512 -------
arch/arm/mach-omap2/clkt2xxx_dpll.c | 56 -
arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 194 ---
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 259 ----
arch/arm/mach-omap2/clock.c | 12 +-
arch/arm/mach-omap2/clock2xxx.h | 17 -
arch/arm/mach-omap2/clockdomain.c | 4 +-
arch/arm/mach-omap2/clockdomain.h | 5 -
arch/arm/mach-omap2/clockdomains2420_data.c | 154 --
arch/arm/mach-omap2/clockdomains2430_data.c | 181 ---
.../mach-omap2/clockdomains2xxx_3xxx_data.c | 29 +-
arch/arm/mach-omap2/cm-regbits-24xx.h | 51 -
arch/arm/mach-omap2/cm2xxx.c | 302 ----
arch/arm/mach-omap2/cm2xxx.h | 60 -
arch/arm/mach-omap2/cm_common.c | 12 -
arch/arm/mach-omap2/common-board-devices.h | 11 -
arch/arm/mach-omap2/common.h | 12 -
arch/arm/mach-omap2/control.h | 56 -
arch/arm/mach-omap2/display.c | 4 +-
arch/arm/mach-omap2/dma.c | 53 +-
arch/arm/mach-omap2/fb.c | 14 +-
arch/arm/mach-omap2/gpmc.h | 10 -
arch/arm/mach-omap2/i2c.c | 2 +-
arch/arm/mach-omap2/id.c | 80 +-
arch/arm/mach-omap2/io.c | 140 +-
arch/arm/mach-omap2/iomap.h | 46 -
arch/arm/mach-omap2/l3_2xxx.h | 15 -
arch/arm/mach-omap2/l4_2xxx.h | 19 -
arch/arm/mach-omap2/mmc.h | 18 -
arch/arm/mach-omap2/msdi.c | 75 -
arch/arm/mach-omap2/omap2-restart.c | 62 -
arch/arm/mach-omap2/omap24xx.h | 73 -
arch/arm/mach-omap2/omap_hwmod.c | 18 +-
arch/arm/mach-omap2/omap_hwmod.h | 2 -
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 402 ------
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 606 --------
.../omap_hwmod_2xxx_interconnect_data.c | 256 ----
.../mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 668 ---------
arch/arm/mach-omap2/omap_hwmod_common_data.h | 66 -
arch/arm/mach-omap2/opp2420_data.c | 131 --
arch/arm/mach-omap2/opp2430_data.c | 136 --
arch/arm/mach-omap2/opp2xxx.h | 430 ------
arch/arm/mach-omap2/pdata-quirks.c | 35 +-
arch/arm/mach-omap2/pm.h | 5 -
arch/arm/mach-omap2/powerdomain.h | 3 -
arch/arm/mach-omap2/powerdomains2xxx_data.c | 134 --
arch/arm/mach-omap2/prcm-common.h | 147 --
arch/arm/mach-omap2/prm-regbits-24xx.h | 39 -
arch/arm/mach-omap2/prm2xxx.c | 229 ---
arch/arm/mach-omap2/prm2xxx.h | 128 --
arch/arm/mach-omap2/prm2xxx_3xxx.c | 1 -
arch/arm/mach-omap2/prm_common.c | 11 -
arch/arm/mach-omap2/sdrc.h | 21 -
arch/arm/mach-omap2/sdrc2xxx.c | 164 ---
arch/arm/mach-omap2/sleep24xx.S | 91 --
arch/arm/mach-omap2/soc.h | 59 -
arch/arm/mach-omap2/sram.c | 159 +--
arch/arm/mach-omap2/sram.h | 32 -
arch/arm/mach-omap2/sram242x.S | 317 -----
arch/arm/mach-omap2/sram243x.S | 317 -----
arch/arm/mach-omap2/usb-tusb6010.c | 217 ---
arch/arm/mach-omap2/usb-tusb6010.h | 12 -
arch/arm/mach-omap2/voltagedomains2xxx_data.c | 29 -
drivers/crypto/Kconfig | 2 +-
drivers/media/platform/ti/omap/Kconfig | 4 +-
drivers/mtd/nand/onenand/Kconfig | 4 +-
drivers/video/fbdev/omap2/omapfb/Kconfig | 2 +-
include/linux/clk/ti.h | 8 -
86 files changed, 60 insertions(+), 10696 deletions(-)
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-h4.dts
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-n800.dts
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-n810.dts
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2430-sdp.dts
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2430.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi
delete mode 100644 arch/arm/mach-omap2/board-n8x0.c
delete mode 100644 arch/arm/mach-omap2/clkt2xxx_dpll.c
delete mode 100644 arch/arm/mach-omap2/clkt2xxx_dpllcore.c
delete mode 100644 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
delete mode 100644 arch/arm/mach-omap2/clock2xxx.h
delete mode 100644 arch/arm/mach-omap2/clockdomains2420_data.c
delete mode 100644 arch/arm/mach-omap2/clockdomains2430_data.c
delete mode 100644 arch/arm/mach-omap2/cm-regbits-24xx.h
delete mode 100644 arch/arm/mach-omap2/cm2xxx.c
delete mode 100644 arch/arm/mach-omap2/cm2xxx.h
delete mode 100644 arch/arm/mach-omap2/common-board-devices.h
delete mode 100644 arch/arm/mach-omap2/gpmc.h
delete mode 100644 arch/arm/mach-omap2/l3_2xxx.h
delete mode 100644 arch/arm/mach-omap2/l4_2xxx.h
delete mode 100644 arch/arm/mach-omap2/mmc.h
delete mode 100644 arch/arm/mach-omap2/msdi.c
delete mode 100644 arch/arm/mach-omap2/omap2-restart.c
delete mode 100644 arch/arm/mach-omap2/omap24xx.h
delete mode 100644 arch/arm/mach-omap2/omap_hwmod_2420_data.c
delete mode 100644 arch/arm/mach-omap2/omap_hwmod_2430_data.c
delete mode 100644 arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
delete mode 100644 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
delete mode 100644 arch/arm/mach-omap2/opp2420_data.c
delete mode 100644 arch/arm/mach-omap2/opp2430_data.c
delete mode 100644 arch/arm/mach-omap2/opp2xxx.h
delete mode 100644 arch/arm/mach-omap2/powerdomains2xxx_data.c
delete mode 100644 arch/arm/mach-omap2/prm-regbits-24xx.h
delete mode 100644 arch/arm/mach-omap2/prm2xxx.c
delete mode 100644 arch/arm/mach-omap2/prm2xxx.h
delete mode 100644 arch/arm/mach-omap2/sdrc2xxx.c
delete mode 100644 arch/arm/mach-omap2/sleep24xx.S
delete mode 100644 arch/arm/mach-omap2/sram242x.S
delete mode 100644 arch/arm/mach-omap2/sram243x.S
delete mode 100644 arch/arm/mach-omap2/usb-tusb6010.c
delete mode 100644 arch/arm/mach-omap2/usb-tusb6010.h
delete mode 100644 arch/arm/mach-omap2/voltagedomains2xxx_data.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 028db7ad15ad..0d10f778800d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19874,7 +19874,6 @@ M: Jarkko Nikula <jarkko.nikula@bitmer.com>
L: linux-sound@vger.kernel.org
L: linux-omap@vger.kernel.org
S: Maintained
-F: sound/soc/ti/n810.c
F: sound/soc/ti/omap*
F: sound/soc/ti/rx51.c
F: sound/soc/ti/sdma-pcm.*
@@ -20027,7 +20026,6 @@ F: drivers/gpio/gpio-tps65219.c
F: drivers/i2c/busses/i2c-omap.c
F: drivers/irqchip/irq-omap-intc.c
F: drivers/mfd/*omap*.c
-F: drivers/mfd/menelaus.c
F: drivers/mfd/palmas.c
F: drivers/mfd/tps65217.c
F: drivers/mfd/tps65218.c
diff --git a/arch/arm/boot/dts/ti/omap/Makefile b/arch/arm/boot/dts/ti/omap/Makefile
index 498c36ccb5ea..3c5d378df6b9 100644
--- a/arch/arm/boot/dts/ti/omap/Makefile
+++ b/arch/arm/boot/dts/ti/omap/Makefile
@@ -1,10 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_ARCH_OMAP2) += \
- omap2420-h4.dtb \
- omap2420-n800.dtb \
- omap2420-n810.dtb \
- omap2420-n810-wimax.dtb \
- omap2430-sdp.dtb
dtb-$(CONFIG_ARCH_OMAP3) += \
am3517-craneboard.dtb \
am3517-evm.dtb \
diff --git a/arch/arm/boot/dts/ti/omap/omap2.dtsi b/arch/arm/boot/dts/ti/omap/omap2.dtsi
deleted file mode 100644
index fdc1790adf43..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2.dtsi
+++ /dev/null
@@ -1,338 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for OMAP2 SoC
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/bus/ti-sysc.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/omap.h>
-
-/ {
- compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
- interrupt-parent = <&intc>;
- #address-cells = <1>;
- #size-cells = <1>;
- chosen { };
-
- aliases {
- serial0 = &uart1;
- serial1 = &uart2;
- serial2 = &uart3;
- i2c0 = &i2c1;
- i2c1 = &i2c2;
- };
-
- cpus {
- #address-cells = <0>;
- #size-cells = <0>;
-
- cpu {
- compatible = "arm,arm1136jf-s";
- device_type = "cpu";
- };
- };
-
- pmu {
- compatible = "arm,arm1136-pmu";
- interrupts = <3>;
- };
-
- soc {
- compatible = "ti,omap-infra";
- mpu {
- compatible = "ti,omap2-mpu";
- ti,hwmods = "mpu";
- };
- };
-
- ocp {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,hwmods = "l3_main";
-
- aes: aes@480a6000 {
- compatible = "ti,omap2-aes";
- ti,hwmods = "aes";
- reg = <0x480a6000 0x50>;
- dmas = <&sdma 9 &sdma 10>;
- dma-names = "tx", "rx";
- };
-
- hdq1w: 1w@480b2000 {
- compatible = "ti,omap2420-1w";
- ti,hwmods = "hdq1w";
- reg = <0x480b2000 0x1000>;
- interrupts = <58>;
- };
-
- intc: interrupt-controller@1 {
- compatible = "ti,omap2-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x480FE000 0x1000>;
- };
-
- target-module@48056000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x48056000 0x4>,
- <0x4805602c 0x4>,
- <0x48056028 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_EMUFREE |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- clocks = <&core_l3_ck>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x48056000 0x1000>;
-
- sdma: dma-controller@0 {
- compatible = "ti,omap2420-sdma", "ti,omap-sdma";
- reg = <0 0x1000>;
- interrupts = <12>,
- <13>,
- <14>,
- <15>;
- #dma-cells = <1>;
- dma-channels = <32>;
- dma-requests = <64>;
- };
- };
-
- i2c1: i2c@48070000 {
- compatible = "ti,omap2-i2c";
- ti,hwmods = "i2c1";
- reg = <0x48070000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <56>;
- };
-
- i2c2: i2c@48072000 {
- compatible = "ti,omap2-i2c";
- ti,hwmods = "i2c2";
- reg = <0x48072000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <57>;
- };
-
- mcspi1: spi@48098000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "ti,omap2-mcspi";
- ti,hwmods = "mcspi1";
- reg = <0x48098000 0x100>;
- interrupts = <65>;
- dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
- &sdma 39 &sdma 40 &sdma 41 &sdma 42>;
- dma-names = "tx0", "rx0", "tx1", "rx1",
- "tx2", "rx2", "tx3", "rx3";
- };
-
- mcspi2: spi@4809a000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "ti,omap2-mcspi";
- ti,hwmods = "mcspi2";
- reg = <0x4809a000 0x100>;
- interrupts = <66>;
- dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
- dma-names = "tx0", "rx0", "tx1", "rx1";
- };
-
- rng: rng@480a0000 {
- compatible = "ti,omap2-rng";
- ti,hwmods = "rng";
- reg = <0x480a0000 0x50>;
- interrupts = <52>;
- };
-
- sham: sham@480a4000 {
- compatible = "ti,omap2-sham";
- ti,hwmods = "sham";
- reg = <0x480a4000 0x64>;
- interrupts = <51>;
- dmas = <&sdma 13>;
- dma-names = "rx";
- };
-
- uart1: serial@4806a000 {
- compatible = "ti,omap2-uart";
- ti,hwmods = "uart1";
- reg = <0x4806a000 0x2000>;
- interrupts = <72>;
- dmas = <&sdma 49 &sdma 50>;
- dma-names = "tx", "rx";
- clock-frequency = <48000000>;
- };
-
- uart2: serial@4806c000 {
- compatible = "ti,omap2-uart";
- ti,hwmods = "uart2";
- reg = <0x4806c000 0x400>;
- interrupts = <73>;
- dmas = <&sdma 51 &sdma 52>;
- dma-names = "tx", "rx";
- clock-frequency = <48000000>;
- };
-
- uart3: serial@4806e000 {
- compatible = "ti,omap2-uart";
- ti,hwmods = "uart3";
- reg = <0x4806e000 0x400>;
- interrupts = <74>;
- dmas = <&sdma 53 &sdma 54>;
- dma-names = "tx", "rx";
- clock-frequency = <48000000>;
- };
-
- timer2_target: target-module@4802a000 {
- compatible = "ti,sysc-omap2-timer", "ti,sysc";
- reg = <0x4802a000 0x4>,
- <0x4802a010 0x4>,
- <0x4802a014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_EMUFREE |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- clocks = <&gpt2_fck>, <&gpt2_ick>;
- clock-names = "fck", "ick";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x4802a000 0x1000>;
-
- timer2: timer@0 {
- compatible = "ti,omap2420-timer";
- reg = <0 0x400>;
- interrupts = <38>;
- };
- };
-
- timer3: timer@48078000 {
- compatible = "ti,omap2420-timer";
- reg = <0x48078000 0x400>;
- interrupts = <39>;
- ti,hwmods = "timer3";
- };
-
- timer4: timer@4807a000 {
- compatible = "ti,omap2420-timer";
- reg = <0x4807a000 0x400>;
- interrupts = <40>;
- ti,hwmods = "timer4";
- };
-
- timer5: timer@4807c000 {
- compatible = "ti,omap2420-timer";
- reg = <0x4807c000 0x400>;
- interrupts = <41>;
- ti,hwmods = "timer5";
- ti,timer-dsp;
- };
-
- timer6: timer@4807e000 {
- compatible = "ti,omap2420-timer";
- reg = <0x4807e000 0x400>;
- interrupts = <42>;
- ti,hwmods = "timer6";
- ti,timer-dsp;
- };
-
- timer7: timer@48080000 {
- compatible = "ti,omap2420-timer";
- reg = <0x48080000 0x400>;
- interrupts = <43>;
- ti,hwmods = "timer7";
- ti,timer-dsp;
- };
-
- timer8: timer@48082000 {
- compatible = "ti,omap2420-timer";
- reg = <0x48082000 0x400>;
- interrupts = <44>;
- ti,hwmods = "timer8";
- ti,timer-dsp;
- };
-
- timer9: timer@48084000 {
- compatible = "ti,omap2420-timer";
- reg = <0x48084000 0x400>;
- interrupts = <45>;
- ti,hwmods = "timer9";
- ti,timer-pwm;
- };
-
- timer10: timer@48086000 {
- compatible = "ti,omap2420-timer";
- reg = <0x48086000 0x400>;
- interrupts = <46>;
- ti,hwmods = "timer10";
- ti,timer-pwm;
- };
-
- timer11: timer@48088000 {
- compatible = "ti,omap2420-timer";
- reg = <0x48088000 0x400>;
- interrupts = <47>;
- ti,hwmods = "timer11";
- ti,timer-pwm;
- };
-
- timer12: timer@4808a000 {
- compatible = "ti,omap2420-timer";
- reg = <0x4808a000 0x400>;
- interrupts = <48>;
- ti,hwmods = "timer12";
- ti,timer-pwm;
- };
-
- dss: dss@48050000 {
- compatible = "ti,omap2-dss";
- reg = <0x48050000 0x400>;
- status = "disabled";
- ti,hwmods = "dss_core";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- dispc@48050400 {
- compatible = "ti,omap2-dispc";
- reg = <0x48050400 0x400>;
- interrupts = <25>;
- ti,hwmods = "dss_dispc";
- };
-
- rfbi: encoder@48050800 {
- compatible = "ti,omap2-rfbi";
- reg = <0x48050800 0x400>;
- status = "disabled";
- ti,hwmods = "dss_rfbi";
- };
-
- venc: encoder@48050c00 {
- compatible = "ti,omap2-venc";
- reg = <0x48050c00 0x400>;
- status = "disabled";
- ti,hwmods = "dss_venc";
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi
deleted file mode 100644
index 00a7a199a91c..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi
+++ /dev/null
@@ -1,267 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for OMAP2420 clock data
- *
- * Copyright (C) 2014 Texas Instruments, Inc.
- */
-
-&prcm_clocks {
- sys_clkout2_src_gate: sys_clkout2_src_gate@70 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <15>;
- reg = <0x0070>;
- };
-
- sys_clkout2_src_mux: sys_clkout2_src_mux@70 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
- ti,bit-shift = <8>;
- reg = <0x0070>;
- };
-
- sys_clkout2_src: sys_clkout2_src {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
- };
-
- sys_clkout2: sys_clkout2@70 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&sys_clkout2_src>;
- ti,bit-shift = <11>;
- ti,max-div = <64>;
- reg = <0x0070>;
- ti,index-power-of-two;
- };
-
- dsp_gate_ick: dsp_gate_ick@810 {
- #clock-cells = <0>;
- compatible = "ti,composite-interface-clock";
- clocks = <&dsp_fck>;
- ti,bit-shift = <1>;
- reg = <0x0810>;
- };
-
- dsp_div_ick: dsp_div_ick@840 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&dsp_fck>;
- ti,bit-shift = <5>;
- ti,max-div = <3>;
- reg = <0x0840>;
- ti,index-starts-at-one;
- };
-
- dsp_ick: dsp_ick {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
- };
-
- iva1_gate_ifck: iva1_gate_ifck@800 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <10>;
- reg = <0x0800>;
- };
-
- iva1_div_ifck: iva1_div_ifck@840 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <8>;
- reg = <0x0840>;
- ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
- };
-
- iva1_ifck: iva1_ifck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
- };
-
- iva1_ifck_div: iva1_ifck_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&iva1_ifck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- iva1_mpu_int_ifck: iva1_mpu_int_ifck@800 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&iva1_ifck_div>;
- ti,bit-shift = <8>;
- reg = <0x0800>;
- };
-
- wdt3_ick: wdt3_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <28>;
- reg = <0x0210>;
- };
-
- wdt3_fck: wdt3_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <28>;
- reg = <0x0200>;
- };
-
- mmc_ick: mmc_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <26>;
- reg = <0x0210>;
- };
-
- mmc_fck: mmc_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_96m_ck>;
- ti,bit-shift = <26>;
- reg = <0x0200>;
- };
-
- eac_ick: eac_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <24>;
- reg = <0x0210>;
- };
-
- eac_fck: eac_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_96m_ck>;
- ti,bit-shift = <24>;
- reg = <0x0200>;
- };
-
- i2c1_fck: i2c1_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_12m_ck>;
- ti,bit-shift = <19>;
- reg = <0x0200>;
- };
-
- i2c2_fck: i2c2_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_12m_ck>;
- ti,bit-shift = <20>;
- reg = <0x0200>;
- };
-
- vlynq_ick: vlynq_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l3_ck>;
- ti,bit-shift = <3>;
- reg = <0x0210>;
- };
-
- vlynq_gate_fck: vlynq_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <3>;
- reg = <0x0200>;
- };
-
- core_d18_ck: core_d18_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <18>;
- };
-
- vlynq_mux_fck: vlynq_mux_fck@240 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;
- ti,bit-shift = <15>;
- reg = <0x0240>;
- };
-
- vlynq_fck: vlynq_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>;
- };
-};
-
-&prcm_clockdomains {
- gfx_clkdm: gfx_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&gfx_ick>;
- };
-
- core_l3_clkdm: core_l3_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>;
- };
-
- wkup_clkdm: wkup_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
- <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
- <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>;
- };
-
- iva1_clkdm: iva1_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&iva1_mpu_int_ifck>;
- };
-
- dss_clkdm: dss_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dss_ick>, <&dss_54m_fck>;
- };
-
- core_l4_clkdm: core_l4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
- <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
- <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
- <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>,
- <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
- <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>,
- <&uart3_ick>, <&uart3_fck>, <&cam_ick>,
- <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>,
- <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>,
- <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>,
- <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>,
- <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>,
- <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
- <&pka_ick>;
- };
-};
-
-&func_96m_ck {
- compatible = "fixed-factor-clock";
- clocks = <&apll96_ck>;
- clock-mult = <1>;
- clock-div = <1>;
-};
-
-&dsp_div_fck {
- ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
-};
-
-&ssi_ssr_sst_div_fck {
- ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2420-h4.dts b/arch/arm/boot/dts/ti/omap/omap2420-h4.dts
deleted file mode 100644
index 5acf5dd87c59..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2420-h4.dts
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "omap2420.dtsi"
-
-/ {
- model = "TI OMAP2420 H4 board";
- compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2";
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x4000000>; /* 64 MB */
- };
-};
-
-&gpmc {
- ranges = <0 0 0x08000000 0x04000000>;
-
- nor@0,0 {
- compatible = "cfi-flash";
- linux,mtd-name = "intel,ge28f256l18b85";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0 0 0x04000000>;
- bank-width = <2>;
-
- gpmc,mux-add-data = <2>;
- gpmc,cs-on-ns = <10>;
- gpmc,cs-rd-off-ns = <160>;
- gpmc,cs-wr-off-ns = <160>;
- gpmc,adv-on-ns = <20>;
- gpmc,adv-rd-off-ns = <50>;
- gpmc,adv-wr-off-ns = <50>;
- gpmc,oe-on-ns = <60>;
- gpmc,oe-off-ns = <120>;
- gpmc,we-on-ns = <60>;
- gpmc,we-off-ns = <120>;
- gpmc,rd-cycle-ns = <170>;
- gpmc,wr-cycle-ns = <170>;
- gpmc,access-ns = <150>;
- gpmc,page-burst-access-ns = <10>;
-
- partition@0 {
- label = "bootloader";
- reg = <0 0x20000>;
- };
- partition@20000 {
- label = "params";
- reg = <0x20000 0x20000>;
- };
- partition@40000 {
- label = "kernel";
- reg = <0x40000 0x200000>;
- };
- partition@240000 {
- label = "file-system";
- reg = <0x240000 0x3dc0000>;
- };
- };
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2420-n800.dts b/arch/arm/boot/dts/ti/omap/omap2420-n800.dts
deleted file mode 100644
index f06d767e818b..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2420-n800.dts
+++ /dev/null
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "omap2420-n8x0-common.dtsi"
-
-/ {
- model = "Nokia N800";
- compatible = "nokia,n800", "nokia,n8x0", "ti,omap2420", "ti,omap2";
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts b/arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts
deleted file mode 100644
index ac9acbd609b6..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts
+++ /dev/null
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "omap2420-n8x0-common.dtsi"
-
-/ {
- model = "Nokia N810 WiMax";
- compatible = "nokia,n810-wimax", "nokia,n8x0", "ti,omap2420", "ti,omap2";
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2420-n810.dts b/arch/arm/boot/dts/ti/omap/omap2420-n810.dts
deleted file mode 100644
index 3bf8175d85a8..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2420-n810.dts
+++ /dev/null
@@ -1,75 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "omap2420-n8x0-common.dtsi"
-
-/ {
- model = "Nokia N810";
- compatible = "nokia,n810", "nokia,n8x0", "ti,omap2420", "ti,omap2";
-
- vio_ape: vio_ape {
- compatible = "regulator-fixed";
- regulator-name = "vio_ape";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- v28_aic: v28_aic {
- compatible = "regulator-fixed";
- regulator-name = "v28_aic";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-};
-
-&omap2420_pmx {
- mcbsp2_pins: mcbsp2-pins {
- pinctrl-single,pins = <
- OMAP2420_CORE_IOPAD(0x0124, PIN_INPUT | MUX_MODE1) /* eac_ac_sclk.mcbsp2_clkx */
- OMAP2420_CORE_IOPAD(0x0125, PIN_INPUT | MUX_MODE1) /* eac_ac_fs.mcbsp2_fsx */
- OMAP2420_CORE_IOPAD(0x0126, PIN_INPUT | MUX_MODE1) /* eac_ac_din.mcbsp2_dr */
- OMAP2420_CORE_IOPAD(0x0127, PIN_OUTPUT | MUX_MODE1) /* eac_ac_dout.mcbsp2_dx */
- >;
- };
-
- aic33_pins: aic33-pins {
- pinctrl-single,pins = <
- OMAP2420_CORE_IOPAD(0x0129, PIN_OUTPUT | MUX_MODE3) /* eac_ac_rst.gpio118 */
- OMAP2420_CORE_IOPAD(0x00e8, PIN_OUTPUT | MUX_MODE2) /* vlynq_tx1.sys_clkout2 */
- >;
- };
-};
-
-&i2c2 {
- aic33@18 {
- compatible = "ti,tlv320aic33";
- reg = <0x18>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&aic33_pins>;
-
- reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; /* gpio118 */
-
- ai3x-gpio-func = <
- 10 /* AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK */
- 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */
- >;
- ai3x-micbias-vg = <1>; /* 2V */
-
- AVDD-supply = <&v28_aic>;
- DRVDD-supply = <&v28_aic>;
- IOVDD-supply = <&vio_ape>;
- DVDD-supply = <&vio_ape>;
-
- assigned-clocks = <&sys_clkout2_src>, <&sys_clkout2>;
- assigned-clock-parents = <&func_96m_ck>;
- assigned-clock-rates = <0>, <12000000>;
- };
-};
-
-&mcbsp2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcbsp2_pins>;
-
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi
deleted file mode 100644
index fe9dd8bbfc85..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi
+++ /dev/null
@@ -1,123 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include "omap2420.dtsi"
-
-/ {
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x8000000>; /* 128 MB */
- };
-
- chosen {
- stdout-path = &uart3;
- };
-
- ocp {
- i2c0 {
- compatible = "i2c-cbus-gpio";
- gpios = <&gpio3 2 GPIO_ACTIVE_HIGH /* gpio66 clk */
- &gpio3 1 GPIO_ACTIVE_HIGH /* gpio65 dat */
- &gpio3 0 GPIO_ACTIVE_HIGH /* gpio64 sel */
- >;
- #address-cells = <1>;
- #size-cells = <0>;
- retu: retu@1 {
- compatible = "nokia,retu";
- interrupt-parent = <&gpio4>;
- interrupts = <12 IRQ_TYPE_EDGE_RISING>;
- reg = <0x1>;
- };
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <400000>;
-
- pmic@72 {
- compatible = "menelaus";
- reg = <0x72>;
- interrupts = <7 IRQ_TYPE_EDGE_RISING>;
- };
-};
-
-&i2c2 {
- clock-frequency = <400000>;
-};
-
-&gpmc {
- ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
-
- /* gpio-irq for dma: 26 */
-
- onenand@0,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "ti,omap2-onenand";
- reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
-
- gpmc,sync-read;
- gpmc,burst-length = <16>;
- gpmc,burst-read;
- gpmc,burst-wrap;
- gpmc,device-width = <2>;
- gpmc,mux-add-data = <2>;
- gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <127>;
- gpmc,cs-wr-off-ns = <109>;
- gpmc,adv-on-ns = <0>;
- gpmc,adv-rd-off-ns = <18>;
- gpmc,adv-wr-off-ns = <18>;
- gpmc,oe-on-ns = <27>;
- gpmc,oe-off-ns = <127>;
- gpmc,we-on-ns = <27>;
- gpmc,we-off-ns = <72>;
- gpmc,rd-cycle-ns = <145>;
- gpmc,wr-cycle-ns = <136>;
- gpmc,access-ns = <118>;
- gpmc,page-burst-access-ns = <27>;
- gpmc,bus-turnaround-ns = <0>;
- gpmc,cycle2cycle-delay-ns = <0>;
- gpmc,wait-monitoring-ns = <0>;
- gpmc,clk-activation-ns = <9>;
- gpmc,sync-clk-ps = <27000>;
-
- /* MTD partition table corresponding to old board-n8x0 file. */
- partition@0 {
- label = "bootloader";
- reg = <0x00000000 0x00020000>;
- read-only;
- };
- partition@1 {
- label = "config";
- reg = <0x00020000 0x00060000>;
- };
- partition@2 {
- label = "kernel";
- reg = <0x00080000 0x00200000>;
- };
- partition@3 {
- label = "initfs";
- reg = <0x00280000 0x00400000>;
- };
- partition@4 {
- label = "rootfs";
- reg = <0x00680000 0x0f980000>;
- };
- partition@5 {
- label = "omap2-onenand";
- reg = <0x00000000 0x10000000>;
- };
- };
-};
-
-&mcspi2 {
- status = "okay";
-
- wifi@0 {
- reg = <0>;
- compatible = "st,stlc4560";
- spi-max-frequency = <48000000>;
- interrupts-extended = <&gpio3 23 IRQ_TYPE_EDGE_RISING>;
- powerdown-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; /* gpio 97 */
- };
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2420.dtsi b/arch/arm/boot/dts/ti/omap/omap2420.dtsi
deleted file mode 100644
index 821da51cb870..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2420.dtsi
+++ /dev/null
@@ -1,262 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for OMAP2420 SoC
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include "omap2.dtsi"
-
-/ {
- compatible = "ti,omap2420", "ti,omap2";
-
- ocp {
- l4: l4@48000000 {
- compatible = "ti,omap2-l4", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x48000000 0x100000>;
-
- prcm: prcm@8000 {
- compatible = "ti,omap2-prcm";
- reg = <0x8000 0x1000>;
-
- prcm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- prcm_clockdomains: clockdomains {
- };
- };
-
- scm: scm@0 {
- compatible = "ti,omap2-scm", "simple-bus";
- reg = <0x0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- #pinctrl-cells = <1>;
- ranges = <0 0x0 0x1000>;
-
- omap2420_pmx: pinmux@30 {
- compatible = "ti,omap2420-padconf",
- "pinctrl-single";
- reg = <0x30 0x0113>;
- #address-cells = <1>;
- #size-cells = <0>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <8>;
- pinctrl-single,function-mask = <0x3f>;
- };
-
- scm_conf: scm_conf@270 {
- compatible = "syscon";
- reg = <0x270 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- scm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- scm_clockdomains: clockdomains {
- };
- };
-
- target-module@4000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x4000 0x4>,
- <0x4004 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>;
- clocks = <&func_32k_ck>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x4000 0x1000>;
-
- counter32k: counter@0 {
- compatible = "ti,omap-counter32k";
- reg = <0 0x20>;
- };
- };
- };
-
- gpio1: gpio@48018000 {
- compatible = "ti,omap2-gpio";
- reg = <0x48018000 0x200>;
- interrupts = <29>;
- ti,hwmods = "gpio1";
- ti,gpio-always-on;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpio2: gpio@4801a000 {
- compatible = "ti,omap2-gpio";
- reg = <0x4801a000 0x200>;
- interrupts = <30>;
- ti,hwmods = "gpio2";
- ti,gpio-always-on;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpio3: gpio@4801c000 {
- compatible = "ti,omap2-gpio";
- reg = <0x4801c000 0x200>;
- interrupts = <31>;
- ti,hwmods = "gpio3";
- ti,gpio-always-on;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpio4: gpio@4801e000 {
- compatible = "ti,omap2-gpio";
- reg = <0x4801e000 0x200>;
- interrupts = <32>;
- ti,hwmods = "gpio4";
- ti,gpio-always-on;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpmc: gpmc@6800a000 {
- compatible = "ti,omap2420-gpmc";
- reg = <0x6800a000 0x1000>;
- #address-cells = <2>;
- #size-cells = <1>;
- interrupts = <20>;
- gpmc,num-cs = <8>;
- gpmc,num-waitpins = <4>;
- ti,hwmods = "gpmc";
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- mcbsp1: mcbsp@48074000 {
- compatible = "ti,omap2420-mcbsp";
- reg = <0x48074000 0xff>;
- reg-names = "mpu";
- interrupts = <59>, /* TX interrupt */
- <60>; /* RX interrupt */
- interrupt-names = "tx", "rx";
- ti,hwmods = "mcbsp1";
- dmas = <&sdma 31>,
- <&sdma 32>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- mcbsp2: mcbsp@48076000 {
- compatible = "ti,omap2420-mcbsp";
- reg = <0x48076000 0xff>;
- reg-names = "mpu";
- interrupts = <62>, /* TX interrupt */
- <63>; /* RX interrupt */
- interrupt-names = "tx", "rx";
- ti,hwmods = "mcbsp2";
- dmas = <&sdma 33>,
- <&sdma 34>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- msdi1: mmc@4809c000 {
- compatible = "ti,omap2420-mmc";
- ti,hwmods = "msdi1";
- reg = <0x4809c000 0x80>;
- interrupts = <83>;
- dmas = <&sdma 61 &sdma 62>;
- dma-names = "tx", "rx";
- };
-
- mailbox: mailbox@48094000 {
- compatible = "ti,omap2-mailbox";
- reg = <0x48094000 0x200>;
- interrupts = <26>, <34>;
- ti,hwmods = "mailbox";
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <6>;
- mbox_dsp: mbox-dsp {
- ti,mbox-tx = <0 0 0>;
- ti,mbox-rx = <1 0 0>;
- };
- mbox_iva: mbox-iva {
- ti,mbox-tx = <2 1 3>;
- ti,mbox-rx = <3 1 3>;
- };
- };
-
- timer1_target: target-module@48028000 {
- compatible = "ti,sysc-omap2-timer", "ti,sysc";
- reg = <0x48028000 0x4>,
- <0x48028010 0x4>,
- <0x48028014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_EMUFREE |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- clocks = <&gpt1_fck>, <&gpt1_ick>;
- clock-names = "fck", "ick";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x48028000 0x1000>;
-
- timer1: timer@0 {
- compatible = "ti,omap2420-timer";
- reg = <0 0x400>;
- interrupts = <37>;
- ti,timer-alwon;
- };
- };
-
- wd_timer2: wdt@48022000 {
- compatible = "ti,omap2-wdt";
- ti,hwmods = "wd_timer2";
- reg = <0x48022000 0x80>;
- };
- };
-};
-
-&i2c1 {
- compatible = "ti,omap2420-i2c";
-};
-
-&i2c2 {
- compatible = "ti,omap2420-i2c";
-};
-
-#include "omap24xx-clocks.dtsi"
-#include "omap2420-clocks.dtsi"
-
-/* Preferred always-on timer for clockevent */
-&timer1_target {
- ti,no-reset-on-init;
- ti,no-idle;
- timer@0 {
- assigned-clocks = <&gpt1_fck>;
- assigned-clock-parents = <&func_32k_ck>;
- };
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi
deleted file mode 100644
index 4e5ab5189476..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi
+++ /dev/null
@@ -1,341 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for OMAP2430 clock data
- *
- * Copyright (C) 2014 Texas Instruments, Inc.
- */
-
-&scm_clocks {
- mcbsp3_mux_fck: mcbsp3_mux_fck@78 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_96m_ck>, <&mcbsp_clks>;
- reg = <0x78>;
- };
-
- mcbsp3_fck: mcbsp3_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
- };
-
- mcbsp4_mux_fck: mcbsp4_mux_fck@78 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_96m_ck>, <&mcbsp_clks>;
- ti,bit-shift = <2>;
- reg = <0x78>;
- };
-
- mcbsp4_fck: mcbsp4_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
- };
-
- mcbsp5_mux_fck: mcbsp5_mux_fck@78 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_96m_ck>, <&mcbsp_clks>;
- ti,bit-shift = <4>;
- reg = <0x78>;
- };
-
- mcbsp5_fck: mcbsp5_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
- };
-};
-
-&prcm_clocks {
- iva2_1_gate_ick: iva2_1_gate_ick@800 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&dsp_fck>;
- ti,bit-shift = <0>;
- reg = <0x0800>;
- };
-
- iva2_1_div_ick: iva2_1_div_ick@840 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&dsp_fck>;
- ti,bit-shift = <5>;
- ti,max-div = <3>;
- reg = <0x0840>;
- ti,index-starts-at-one;
- };
-
- iva2_1_ick: iva2_1_ick {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
- };
-
- mdm_gate_ick: mdm_gate_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,composite-interface-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <0>;
- reg = <0x0c10>;
- };
-
- mdm_div_ick: mdm_div_ick@c40 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&core_ck>;
- reg = <0x0c40>;
- ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>;
- };
-
- mdm_ick: mdm_ick {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mdm_gate_ick>, <&mdm_div_ick>;
- };
-
- mdm_osc_ck: mdm_osc_ck@c00 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&osc_ck>;
- ti,bit-shift = <1>;
- reg = <0x0c00>;
- };
-
- mcbsp3_ick: mcbsp3_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <3>;
- reg = <0x0214>;
- };
-
- mcbsp3_gate_fck: mcbsp3_gate_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <3>;
- reg = <0x0204>;
- };
-
- mcbsp4_ick: mcbsp4_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <4>;
- reg = <0x0214>;
- };
-
- mcbsp4_gate_fck: mcbsp4_gate_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <4>;
- reg = <0x0204>;
- };
-
- mcbsp5_ick: mcbsp5_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <5>;
- reg = <0x0214>;
- };
-
- mcbsp5_gate_fck: mcbsp5_gate_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <5>;
- reg = <0x0204>;
- };
-
- mcspi3_ick: mcspi3_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <9>;
- reg = <0x0214>;
- };
-
- mcspi3_fck: mcspi3_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_48m_ck>;
- ti,bit-shift = <9>;
- reg = <0x0204>;
- };
-
- icr_ick: icr_ick@410 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <6>;
- reg = <0x0410>;
- };
-
- i2chs1_fck: i2chs1_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,omap2430-interface-clock";
- clocks = <&func_96m_ck>;
- ti,bit-shift = <19>;
- reg = <0x0204>;
- };
-
- i2chs2_fck: i2chs2_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,omap2430-interface-clock";
- clocks = <&func_96m_ck>;
- ti,bit-shift = <20>;
- reg = <0x0204>;
- };
-
- usbhs_ick: usbhs_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l3_ck>;
- ti,bit-shift = <6>;
- reg = <0x0214>;
- };
-
- mmchs1_ick: mmchs1_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <7>;
- reg = <0x0214>;
- };
-
- mmchs1_fck: mmchs1_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_96m_ck>;
- ti,bit-shift = <7>;
- reg = <0x0204>;
- };
-
- mmchs2_ick: mmchs2_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <8>;
- reg = <0x0214>;
- };
-
- mmchs2_fck: mmchs2_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_96m_ck>;
- ti,bit-shift = <8>;
- reg = <0x0204>;
- };
-
- gpio5_ick: gpio5_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <10>;
- reg = <0x0214>;
- };
-
- gpio5_fck: gpio5_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <10>;
- reg = <0x0204>;
- };
-
- mdm_intc_ick: mdm_intc_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <11>;
- reg = <0x0214>;
- };
-
- mmchsdb1_fck: mmchsdb1_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <16>;
- reg = <0x0204>;
- };
-
- mmchsdb2_fck: mmchsdb2_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <17>;
- reg = <0x0204>;
- };
-};
-
-&prcm_clockdomains {
- gfx_clkdm: gfx_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&gfx_ick>;
- };
-
- core_l3_clkdm: core_l3_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>;
- };
-
- wkup_clkdm: wkup_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
- <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
- <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>,
- <&icr_ick>;
- };
-
- dss_clkdm: dss_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dss_ick>, <&dss_54m_fck>;
- };
-
- core_l4_clkdm: core_l4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
- <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
- <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
- <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
- <&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>,
- <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
- <&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>,
- <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>,
- <&uart3_fck>, <&cam_ick>, <&mailboxes_ick>,
- <&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>,
- <&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>,
- <&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>,
- <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
- <&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>,
- <&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>,
- <&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>,
- <&mmchsdb2_fck>;
- };
-
- mdm_clkdm: mdm_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&mdm_osc_ck>;
- };
-};
-
-&func_96m_ck {
- compatible = "ti,mux-clock";
- clocks = <&apll96_ck>, <&alt_ck>;
- ti,bit-shift = <4>;
- reg = <0x0540>;
-};
-
-&dsp_div_fck {
- ti,max-div = <4>;
- ti,index-starts-at-one;
-};
-
-&ssi_ssr_sst_div_fck {
- ti,max-div = <5>;
- ti,index-starts-at-one;
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2430-sdp.dts b/arch/arm/boot/dts/ti/omap/omap2430-sdp.dts
deleted file mode 100644
index 207070677e3a..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2430-sdp.dts
+++ /dev/null
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "omap2430.dtsi"
-
-/ {
- model = "TI OMAP2430 SDP";
- compatible = "ti,omap2430-sdp", "ti,omap2430", "ti,omap2";
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x8000000>; /* 128 MB */
- };
-};
-
-&i2c2 {
- clock-frequency = <100000>;
-
- twl: twl@48 {
- reg = <0x48>;
- interrupts = <7>; /* SYS_NIRQ cascaded to intc */
- };
-};
-
-#include "twl4030.dtsi"
-
-&mmc1 {
- vmmc-supply = <&vmmc1>;
- bus-width = <4>;
-};
-
-&gpmc {
- ranges = <5 0 0x08000000 0x01000000>;
- ethernet@gpmc {
- compatible = "smsc,lan91c94";
- interrupt-parent = <&gpio5>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */
- reg = <5 0x300 0xf>;
- bank-width = <2>;
- gpmc,sync-clk-ps = <0>;
- gpmc,mux-add-data = <2>;
- gpmc,device-width = <1>;
- gpmc,cycle2cycle-samecsen;
- gpmc,cycle2cycle-diffcsen;
- gpmc,cs-on-ns = <6>;
- gpmc,cs-rd-off-ns = <187>;
- gpmc,cs-wr-off-ns = <187>;
- gpmc,adv-on-ns = <18>;
- gpmc,adv-rd-off-ns = <48>;
- gpmc,adv-wr-off-ns = <48>;
- gpmc,oe-on-ns = <60>;
- gpmc,oe-off-ns = <169>;
- gpmc,we-on-ns = <66>;
- gpmc,we-off-ns = <169>;
- gpmc,rd-cycle-ns = <187>;
- gpmc,wr-cycle-ns = <187>;
- gpmc,access-ns = <187>;
- gpmc,page-burst-access-ns = <24>;
- gpmc,bus-turnaround-ns = <24>;
- gpmc,cycle2cycle-delay-ns = <24>;
- gpmc,wait-monitoring-ns = <0>;
- gpmc,clk-activation-ns = <0>;
- gpmc,wr-data-mux-bus-ns = <0>;
- gpmc,wr-access-ns = <0>;
- };
-};
-
diff --git a/arch/arm/boot/dts/ti/omap/omap2430.dtsi b/arch/arm/boot/dts/ti/omap/omap2430.dtsi
deleted file mode 100644
index 01bd471f9223..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2430.dtsi
+++ /dev/null
@@ -1,366 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for OMAP243x SoC
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include "omap2.dtsi"
-
-/ {
- compatible = "ti,omap2430", "ti,omap2";
-
- ocp {
- l4_wkup: l4_wkup@49000000 {
- compatible = "ti,omap2-l4-wkup", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x49000000 0x31000>;
-
- prcm: prcm@6000 {
- compatible = "ti,omap2-prcm";
- reg = <0x6000 0x1000>;
-
- prcm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- prcm_clockdomains: clockdomains {
- };
- };
-
- scm: scm@2000 {
- compatible = "ti,omap2-scm", "simple-bus";
- reg = <0x2000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- #pinctrl-cells = <1>;
- ranges = <0 0x2000 0x1000>;
-
- omap2430_pmx: pinmux@30 {
- compatible = "ti,omap2430-padconf",
- "pinctrl-single";
- reg = <0x30 0x0154>;
- #address-cells = <1>;
- #size-cells = <0>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <8>;
- pinctrl-single,function-mask = <0x3f>;
- };
-
- scm_conf: scm_conf@270 {
- compatible = "ti,omap2-scm-conf", "syscon",
- "simple-bus";
- reg = <0x270 0x240>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x270 0x240>;
-
- scm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pbias_regulator: pbias_regulator@230 {
- compatible = "ti,pbias-omap2", "ti,pbias-omap";
- reg = <0x230 0x4>;
- syscon = <&scm_conf>;
- pbias_mmc_reg: pbias_mmc_omap2430 {
- regulator-name = "pbias_mmc_omap2430";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- };
- };
- };
-
- scm_clockdomains: clockdomains {
- };
- };
-
- target-module@20000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x20000 0x4>,
- <0x20004 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>;
- clocks = <&func_32k_ck>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x20000 0x1000>;
-
- counter32k: counter@0 {
- compatible = "ti,omap-counter32k";
- reg = <0 0x20>;
- };
- };
- };
-
- gpio1: gpio@4900c000 {
- compatible = "ti,omap2-gpio";
- reg = <0x4900c000 0x200>;
- interrupts = <29>;
- ti,hwmods = "gpio1";
- ti,gpio-always-on;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpio2: gpio@4900e000 {
- compatible = "ti,omap2-gpio";
- reg = <0x4900e000 0x200>;
- interrupts = <30>;
- ti,hwmods = "gpio2";
- ti,gpio-always-on;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpio3: gpio@49010000 {
- compatible = "ti,omap2-gpio";
- reg = <0x49010000 0x200>;
- interrupts = <31>;
- ti,hwmods = "gpio3";
- ti,gpio-always-on;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpio4: gpio@49012000 {
- compatible = "ti,omap2-gpio";
- reg = <0x49012000 0x200>;
- interrupts = <32>;
- ti,hwmods = "gpio4";
- ti,gpio-always-on;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpio5: gpio@480b6000 {
- compatible = "ti,omap2-gpio";
- reg = <0x480b6000 0x200>;
- interrupts = <33>;
- ti,hwmods = "gpio5";
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpmc: gpmc@6e000000 {
- compatible = "ti,omap2430-gpmc";
- reg = <0x6e000000 0x1000>;
- #address-cells = <2>;
- #size-cells = <1>;
- interrupts = <20>;
- gpmc,num-cs = <8>;
- gpmc,num-waitpins = <4>;
- ti,hwmods = "gpmc";
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- mcbsp1: mcbsp@48074000 {
- compatible = "ti,omap2430-mcbsp";
- reg = <0x48074000 0xff>;
- reg-names = "mpu";
- interrupts = <64>, /* OCP compliant interrupt */
- <59>, /* TX interrupt */
- <60>, /* RX interrupt */
- <61>; /* RX overflow interrupt */
- interrupt-names = "common", "tx", "rx", "rx_overflow";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp1";
- dmas = <&sdma 31>,
- <&sdma 32>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- mcbsp2: mcbsp@48076000 {
- compatible = "ti,omap2430-mcbsp";
- reg = <0x48076000 0xff>;
- reg-names = "mpu";
- interrupts = <16>, /* OCP compliant interrupt */
- <62>, /* TX interrupt */
- <63>; /* RX interrupt */
- interrupt-names = "common", "tx", "rx";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp2";
- dmas = <&sdma 33>,
- <&sdma 34>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- mcbsp3: mcbsp@4808c000 {
- compatible = "ti,omap2430-mcbsp";
- reg = <0x4808c000 0xff>;
- reg-names = "mpu";
- interrupts = <17>, /* OCP compliant interrupt */
- <89>, /* TX interrupt */
- <90>; /* RX interrupt */
- interrupt-names = "common", "tx", "rx";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp3";
- dmas = <&sdma 17>,
- <&sdma 18>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- mcbsp4: mcbsp@4808e000 {
- compatible = "ti,omap2430-mcbsp";
- reg = <0x4808e000 0xff>;
- reg-names = "mpu";
- interrupts = <18>, /* OCP compliant interrupt */
- <54>, /* TX interrupt */
- <55>; /* RX interrupt */
- interrupt-names = "common", "tx", "rx";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp4";
- dmas = <&sdma 19>,
- <&sdma 20>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- mcbsp5: mcbsp@48096000 {
- compatible = "ti,omap2430-mcbsp";
- reg = <0x48096000 0xff>;
- reg-names = "mpu";
- interrupts = <19>, /* OCP compliant interrupt */
- <81>, /* TX interrupt */
- <82>; /* RX interrupt */
- interrupt-names = "common", "tx", "rx";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp5";
- dmas = <&sdma 21>,
- <&sdma 22>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- mmc1: mmc@4809c000 {
- compatible = "ti,omap2-hsmmc";
- reg = <0x4809c000 0x200>;
- interrupts = <83>;
- ti,hwmods = "mmc1";
- ti,dual-volt;
- dmas = <&sdma 61>, <&sdma 62>;
- dma-names = "tx", "rx";
- pbias-supply = <&pbias_mmc_reg>;
- };
-
- mmc2: mmc@480b4000 {
- compatible = "ti,omap2-hsmmc";
- reg = <0x480b4000 0x200>;
- interrupts = <86>;
- ti,hwmods = "mmc2";
- dmas = <&sdma 47>, <&sdma 48>;
- dma-names = "tx", "rx";
- };
-
- mailbox: mailbox@48094000 {
- compatible = "ti,omap2-mailbox";
- reg = <0x48094000 0x200>;
- interrupts = <26>;
- ti,hwmods = "mailbox";
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <6>;
- mbox_dsp: mbox-dsp {
- ti,mbox-tx = <0 0 0>;
- ti,mbox-rx = <1 0 0>;
- };
- };
-
- timer1_target: target-module@49018000 {
- compatible = "ti,sysc-omap2-timer", "ti,sysc";
- reg = <0x49018000 0x4>,
- <0x49018010 0x4>,
- <0x49018014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_EMUFREE |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- clocks = <&gpt1_fck>, <&gpt1_ick>;
- clock-names = "fck", "ick";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x49018000 0x1000>;
-
- timer1: timer@0 {
- compatible = "ti,omap2420-timer";
- reg = <0 0x400>;
- interrupts = <37>;
- ti,timer-alwon;
- };
- };
-
- mcspi3: spi@480b8000 {
- compatible = "ti,omap2-mcspi";
- ti,hwmods = "mcspi3";
- reg = <0x480b8000 0x100>;
- interrupts = <91>;
- dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>;
- dma-names = "tx0", "rx0", "tx1", "rx1";
- };
-
- usb_otg_hs: usb_otg_hs@480ac000 {
- compatible = "ti,omap2-musb";
- ti,hwmods = "usb_otg_hs";
- reg = <0x480ac000 0x1000>;
- interrupts = <93>;
- };
-
- wd_timer2: watchdog@49016000 {
- compatible = "ti,omap2-wdt";
- ti,hwmods = "wd_timer2";
- reg = <0x49016000 0x80>;
- };
- };
-};
-
-&sdma {
- compatible = "ti,omap2430-sdma", "ti,omap-sdma";
-};
-
-&i2c1 {
- compatible = "ti,omap2430-i2c";
-};
-
-&i2c2 {
- compatible = "ti,omap2430-i2c";
-};
-
-#include "omap24xx-clocks.dtsi"
-#include "omap2430-clocks.dtsi"
-
-/* Preferred always-on timer for clockevent */
-&timer1_target {
- ti,no-reset-on-init;
- ti,no-idle;
- timer@0 {
- assigned-clocks = <&gpt1_fck>;
- assigned-clock-parents = <&func_32k_ck>;
- };
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi
deleted file mode 100644
index 07af87edf0e2..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi
+++ /dev/null
@@ -1,1241 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for OMAP24xx clock data
- *
- * Copyright (C) 2014 Texas Instruments, Inc.
- */
-&scm_clocks {
- mcbsp1_mux_fck: mcbsp1_mux_fck@4 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_96m_ck>, <&mcbsp_clks>;
- ti,bit-shift = <2>;
- reg = <0x4>;
- };
-
- mcbsp1_fck: mcbsp1_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
- };
-
- mcbsp2_mux_fck: mcbsp2_mux_fck@4 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_96m_ck>, <&mcbsp_clks>;
- ti,bit-shift = <6>;
- reg = <0x4>;
- };
-
- mcbsp2_fck: mcbsp2_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
- };
-};
-
-&prcm_clocks {
- func_32k_ck: func_32k_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- secure_32k_ck: secure_32k_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- virt_12m_ck: virt_12m_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <12000000>;
- };
-
- virt_13m_ck: virt_13m_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <13000000>;
- };
-
- virt_19200000_ck: virt_19200000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <19200000>;
- };
-
- virt_26m_ck: virt_26m_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <26000000>;
- };
-
- aplls_clkin_ck: aplls_clkin_ck@540 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
- ti,bit-shift = <23>;
- reg = <0x0540>;
- };
-
- aplls_clkin_x2_ck: aplls_clkin_x2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&aplls_clkin_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- osc_ck: osc_ck@60 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
- ti,bit-shift = <6>;
- reg = <0x0060>;
- ti,index-starts-at-one;
- };
-
- sys_ck: sys_ck@60 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&osc_ck>;
- ti,bit-shift = <6>;
- ti,max-div = <3>;
- reg = <0x0060>;
- ti,index-starts-at-one;
- };
-
- alt_ck: alt_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <54000000>;
- };
-
- mcbsp_clks: mcbsp_clks {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0x0>;
- };
-
- dpll_ck: dpll_ck@500 {
- #clock-cells = <0>;
- compatible = "ti,omap2-dpll-core-clock";
- clocks = <&sys_ck>, <&sys_ck>;
- reg = <0x0500>, <0x0540>;
- };
-
- apll96_ck: apll96_ck@500 {
- #clock-cells = <0>;
- compatible = "ti,omap2-apll-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <2>;
- ti,idlest-shift = <8>;
- ti,clock-frequency = <96000000>;
- reg = <0x0500>, <0x0530>, <0x0520>;
- };
-
- apll54_ck: apll54_ck@500 {
- #clock-cells = <0>;
- compatible = "ti,omap2-apll-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <6>;
- ti,idlest-shift = <9>;
- ti,clock-frequency = <54000000>;
- reg = <0x0500>, <0x0530>, <0x0520>;
- };
-
- func_54m_ck: func_54m_ck@540 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&apll54_ck>, <&alt_ck>;
- ti,bit-shift = <5>;
- reg = <0x0540>;
- };
-
- core_ck: core_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- func_96m_ck: func_96m_ck@540 {
- #clock-cells = <0>;
- };
-
- apll96_d2_ck: apll96_d2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&apll96_ck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- func_48m_ck: func_48m_ck@540 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&apll96_d2_ck>, <&alt_ck>;
- ti,bit-shift = <3>;
- reg = <0x0540>;
- };
-
- func_12m_ck: func_12m_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&func_48m_ck>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-
- sys_clkout_src_gate: sys_clkout_src_gate@70 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <7>;
- reg = <0x0070>;
- };
-
- sys_clkout_src_mux: sys_clkout_src_mux@70 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
- reg = <0x0070>;
- };
-
- sys_clkout_src: sys_clkout_src {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>;
- };
-
- sys_clkout: sys_clkout@70 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&sys_clkout_src>;
- ti,bit-shift = <3>;
- ti,max-div = <64>;
- reg = <0x0070>;
- ti,index-power-of-two;
- };
-
- emul_ck: emul_ck@78 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_54m_ck>;
- ti,bit-shift = <0>;
- reg = <0x0078>;
- };
-
- mpu_ck: mpu_ck@140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&core_ck>;
- ti,max-div = <31>;
- reg = <0x0140>;
- ti,index-starts-at-one;
- };
-
- dsp_gate_fck: dsp_gate_fck@800 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <0>;
- reg = <0x0800>;
- };
-
- dsp_div_fck: dsp_div_fck@840 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&core_ck>;
- reg = <0x0840>;
- };
-
- dsp_fck: dsp_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&dsp_gate_fck>, <&dsp_div_fck>;
- };
-
- core_l3_ck: core_l3_ck@240 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&core_ck>;
- ti,max-div = <31>;
- reg = <0x0240>;
- ti,index-starts-at-one;
- };
-
- gfx_3d_gate_fck: gfx_3d_gate_fck@300 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&core_l3_ck>;
- ti,bit-shift = <2>;
- reg = <0x0300>;
- };
-
- gfx_3d_div_fck: gfx_3d_div_fck@340 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&core_l3_ck>;
- ti,max-div = <4>;
- reg = <0x0340>;
- ti,index-starts-at-one;
- };
-
- gfx_3d_fck: gfx_3d_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>;
- };
-
- gfx_2d_gate_fck: gfx_2d_gate_fck@300 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&core_l3_ck>;
- ti,bit-shift = <1>;
- reg = <0x0300>;
- };
-
- gfx_2d_div_fck: gfx_2d_div_fck@340 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&core_l3_ck>;
- ti,max-div = <4>;
- reg = <0x0340>;
- ti,index-starts-at-one;
- };
-
- gfx_2d_fck: gfx_2d_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>;
- };
-
- gfx_ick: gfx_ick@310 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_l3_ck>;
- ti,bit-shift = <0>;
- reg = <0x0310>;
- };
-
- l4_ck: l4_ck@240 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&core_l3_ck>;
- ti,bit-shift = <5>;
- ti,max-div = <3>;
- reg = <0x0240>;
- ti,index-starts-at-one;
- };
-
- dss_ick: dss_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-no-wait-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <0>;
- reg = <0x0210>;
- };
-
- dss1_gate_fck: dss1_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <0>;
- reg = <0x0200>;
- };
-
- core_d2_ck: core_d2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- core_d3_ck: core_d3_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <3>;
- };
-
- core_d4_ck: core_d4_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-
- core_d5_ck: core_d5_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <5>;
- };
-
- core_d6_ck: core_d6_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <6>;
- };
-
- dummy_ck: dummy_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- core_d8_ck: core_d8_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <8>;
- };
-
- core_d9_ck: core_d9_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <9>;
- };
-
- core_d12_ck: core_d12_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <12>;
- };
-
- core_d16_ck: core_d16_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <16>;
- };
-
- dss1_mux_fck: dss1_mux_fck@240 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>;
- ti,bit-shift = <8>;
- reg = <0x0240>;
- };
-
- dss1_fck: dss1_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&dss1_gate_fck>, <&dss1_mux_fck>;
- };
-
- dss2_gate_fck: dss2_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&func_48m_ck>;
- ti,bit-shift = <1>;
- reg = <0x0200>;
- };
-
- dss2_mux_fck: dss2_mux_fck@240 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&sys_ck>, <&func_48m_ck>;
- ti,bit-shift = <13>;
- reg = <0x0240>;
- };
-
- dss2_fck: dss2_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&dss2_gate_fck>, <&dss2_mux_fck>;
- };
-
- dss_54m_fck: dss_54m_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_54m_ck>;
- ti,bit-shift = <2>;
- reg = <0x0200>;
- };
-
- ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <1>;
- reg = <0x0204>;
- };
-
- ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck@240 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <20>;
- reg = <0x0240>;
- };
-
- ssi_ssr_sst_fck: ssi_ssr_sst_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>;
- };
-
- usb_l4_gate_ick: usb_l4_gate_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,composite-interface-clock";
- clocks = <&core_l3_ck>;
- ti,bit-shift = <0>;
- reg = <0x0214>;
- };
-
- usb_l4_div_ick: usb_l4_div_ick@240 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&core_l3_ck>;
- ti,bit-shift = <25>;
- reg = <0x0240>;
- ti,dividers = <0>, <1>, <2>, <0>, <4>;
- };
-
- usb_l4_ick: usb_l4_ick {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
- };
-
- ssi_l4_ick: ssi_l4_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <1>;
- reg = <0x0214>;
- };
-
- gpt1_ick: gpt1_ick@410 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <0>;
- reg = <0x0410>;
- };
-
- gpt1_gate_fck: gpt1_gate_fck@400 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <0>;
- reg = <0x0400>;
- };
-
- gpt1_mux_fck: gpt1_mux_fck@440 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- reg = <0x0440>;
- };
-
- gpt1_fck: gpt1_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
- };
-
- gpt2_ick: gpt2_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <4>;
- reg = <0x0210>;
- };
-
- gpt2_gate_fck: gpt2_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <4>;
- reg = <0x0200>;
- };
-
- gpt2_mux_fck: gpt2_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <2>;
- reg = <0x0244>;
- };
-
- gpt2_fck: gpt2_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
- };
-
- gpt3_ick: gpt3_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <5>;
- reg = <0x0210>;
- };
-
- gpt3_gate_fck: gpt3_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <5>;
- reg = <0x0200>;
- };
-
- gpt3_mux_fck: gpt3_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <4>;
- reg = <0x0244>;
- };
-
- gpt3_fck: gpt3_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
- };
-
- gpt4_ick: gpt4_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <6>;
- reg = <0x0210>;
- };
-
- gpt4_gate_fck: gpt4_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <6>;
- reg = <0x0200>;
- };
-
- gpt4_mux_fck: gpt4_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <6>;
- reg = <0x0244>;
- };
-
- gpt4_fck: gpt4_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
- };
-
- gpt5_ick: gpt5_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <7>;
- reg = <0x0210>;
- };
-
- gpt5_gate_fck: gpt5_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <7>;
- reg = <0x0200>;
- };
-
- gpt5_mux_fck: gpt5_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <8>;
- reg = <0x0244>;
- };
-
- gpt5_fck: gpt5_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
- };
-
- gpt6_ick: gpt6_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <8>;
- reg = <0x0210>;
- };
-
- gpt6_gate_fck: gpt6_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x0200>;
- };
-
- gpt6_mux_fck: gpt6_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <10>;
- reg = <0x0244>;
- };
-
- gpt6_fck: gpt6_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
- };
-
- gpt7_ick: gpt7_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <9>;
- reg = <0x0210>;
- };
-
- gpt7_gate_fck: gpt7_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <9>;
- reg = <0x0200>;
- };
-
- gpt7_mux_fck: gpt7_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <12>;
- reg = <0x0244>;
- };
-
- gpt7_fck: gpt7_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
- };
-
- gpt8_ick: gpt8_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <10>;
- reg = <0x0210>;
- };
-
- gpt8_gate_fck: gpt8_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <10>;
- reg = <0x0200>;
- };
-
- gpt8_mux_fck: gpt8_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <14>;
- reg = <0x0244>;
- };
-
- gpt8_fck: gpt8_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
- };
-
- gpt9_ick: gpt9_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <11>;
- reg = <0x0210>;
- };
-
- gpt9_gate_fck: gpt9_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <11>;
- reg = <0x0200>;
- };
-
- gpt9_mux_fck: gpt9_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <16>;
- reg = <0x0244>;
- };
-
- gpt9_fck: gpt9_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
- };
-
- gpt10_ick: gpt10_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <12>;
- reg = <0x0210>;
- };
-
- gpt10_gate_fck: gpt10_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <12>;
- reg = <0x0200>;
- };
-
- gpt10_mux_fck: gpt10_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <18>;
- reg = <0x0244>;
- };
-
- gpt10_fck: gpt10_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
- };
-
- gpt11_ick: gpt11_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <13>;
- reg = <0x0210>;
- };
-
- gpt11_gate_fck: gpt11_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <13>;
- reg = <0x0200>;
- };
-
- gpt11_mux_fck: gpt11_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <20>;
- reg = <0x0244>;
- };
-
- gpt11_fck: gpt11_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
- };
-
- gpt12_ick: gpt12_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <14>;
- reg = <0x0210>;
- };
-
- gpt12_gate_fck: gpt12_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <14>;
- reg = <0x0200>;
- };
-
- gpt12_mux_fck: gpt12_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <22>;
- reg = <0x0244>;
- };
-
- gpt12_fck: gpt12_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>;
- };
-
- mcbsp1_ick: mcbsp1_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <15>;
- reg = <0x0210>;
- };
-
- mcbsp1_gate_fck: mcbsp1_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <15>;
- reg = <0x0200>;
- };
-
- mcbsp2_ick: mcbsp2_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <16>;
- reg = <0x0210>;
- };
-
- mcbsp2_gate_fck: mcbsp2_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <16>;
- reg = <0x0200>;
- };
-
- mcspi1_ick: mcspi1_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <17>;
- reg = <0x0210>;
- };
-
- mcspi1_fck: mcspi1_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_48m_ck>;
- ti,bit-shift = <17>;
- reg = <0x0200>;
- };
-
- mcspi2_ick: mcspi2_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <18>;
- reg = <0x0210>;
- };
-
- mcspi2_fck: mcspi2_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_48m_ck>;
- ti,bit-shift = <18>;
- reg = <0x0200>;
- };
-
- uart1_ick: uart1_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <21>;
- reg = <0x0210>;
- };
-
- uart1_fck: uart1_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_48m_ck>;
- ti,bit-shift = <21>;
- reg = <0x0200>;
- };
-
- uart2_ick: uart2_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <22>;
- reg = <0x0210>;
- };
-
- uart2_fck: uart2_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_48m_ck>;
- ti,bit-shift = <22>;
- reg = <0x0200>;
- };
-
- uart3_ick: uart3_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <2>;
- reg = <0x0214>;
- };
-
- uart3_fck: uart3_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_48m_ck>;
- ti,bit-shift = <2>;
- reg = <0x0204>;
- };
-
- gpios_ick: gpios_ick@410 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <2>;
- reg = <0x0410>;
- };
-
- gpios_fck: gpios_fck@400 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <2>;
- reg = <0x0400>;
- };
-
- mpu_wdt_ick: mpu_wdt_ick@410 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <3>;
- reg = <0x0410>;
- };
-
- mpu_wdt_fck: mpu_wdt_fck@400 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <3>;
- reg = <0x0400>;
- };
-
- sync_32k_ick: sync_32k_ick@410 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <1>;
- reg = <0x0410>;
- };
-
- wdt1_ick: wdt1_ick@410 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <4>;
- reg = <0x0410>;
- };
-
- omapctrl_ick: omapctrl_ick@410 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <5>;
- reg = <0x0410>;
- };
-
- cam_fck: cam_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_96m_ck>;
- ti,bit-shift = <31>;
- reg = <0x0200>;
- };
-
- cam_ick: cam_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-no-wait-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <31>;
- reg = <0x0210>;
- };
-
- mailboxes_ick: mailboxes_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <30>;
- reg = <0x0210>;
- };
-
- wdt4_ick: wdt4_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <29>;
- reg = <0x0210>;
- };
-
- wdt4_fck: wdt4_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <29>;
- reg = <0x0200>;
- };
-
- mspro_ick: mspro_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <27>;
- reg = <0x0210>;
- };
-
- mspro_fck: mspro_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_96m_ck>;
- ti,bit-shift = <27>;
- reg = <0x0200>;
- };
-
- fac_ick: fac_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <25>;
- reg = <0x0210>;
- };
-
- fac_fck: fac_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_12m_ck>;
- ti,bit-shift = <25>;
- reg = <0x0200>;
- };
-
- hdq_ick: hdq_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <23>;
- reg = <0x0210>;
- };
-
- hdq_fck: hdq_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_12m_ck>;
- ti,bit-shift = <23>;
- reg = <0x0200>;
- };
-
- i2c1_ick: i2c1_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <19>;
- reg = <0x0210>;
- };
-
- i2c2_ick: i2c2_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <20>;
- reg = <0x0210>;
- };
-
- gpmc_fck: gpmc_fck@238 {
- #clock-cells = <0>;
- compatible = "ti,fixed-factor-clock";
- clocks = <&core_l3_ck>;
- ti,clock-div = <1>;
- ti,autoidle-shift = <1>;
- reg = <0x0238>;
- ti,clock-mult = <1>;
- };
-
- sdma_fck: sdma_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_l3_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- sdma_ick: sdma_ick@238 {
- #clock-cells = <0>;
- compatible = "ti,fixed-factor-clock";
- clocks = <&core_l3_ck>;
- ti,clock-div = <1>;
- ti,autoidle-shift = <0>;
- reg = <0x0238>;
- ti,clock-mult = <1>;
- };
-
- sdrc_ick: sdrc_ick@238 {
- #clock-cells = <0>;
- compatible = "ti,fixed-factor-clock";
- clocks = <&core_l3_ck>;
- ti,clock-div = <1>;
- ti,autoidle-shift = <2>;
- reg = <0x0238>;
- ti,clock-mult = <1>;
- };
-
- des_ick: des_ick@21c {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <0>;
- reg = <0x021c>;
- };
-
- sha_ick: sha_ick@21c {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <1>;
- reg = <0x021c>;
- };
-
- rng_ick: rng_ick@21c {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <2>;
- reg = <0x021c>;
- };
-
- aes_ick: aes_ick@21c {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <3>;
- reg = <0x021c>;
- };
-
- pka_ick: pka_ick@21c {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <4>;
- reg = <0x021c>;
- };
-
- usb_fck: usb_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_48m_ck>;
- ti,bit-shift = <0>;
- reg = <0x0204>;
- };
-};
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index f827f89567fd..2e9597f50c58 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -22,9 +22,7 @@ CONFIG_NAMESPACES=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_PROFILING=y
-CONFIG_ARCH_MULTI_V6=y
CONFIG_OMAP_RESET_CLOCKS=y
-CONFIG_ARCH_OMAP2=y
CONFIG_ARCH_OMAP3=y
CONFIG_ARCH_OMAP4=y
CONFIG_SOC_OMAP5=y
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 79f8afe3a6bf..37ecbfc0a19f 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -5,15 +5,6 @@ menu "TI OMAP/AM/DM/DRA Family"
config OMAP_HWMOD
bool
-config ARCH_OMAP2
- bool "TI OMAP2"
- depends on ARCH_MULTI_V6
- depends on !SMP
- select ARCH_OMAP2PLUS
- select CPU_ARM1136R0
- select OMAP_HWMOD
- select SOC_HAS_OMAP2_SDRC
-
config ARCH_OMAP3
bool "TI OMAP3"
depends on ARCH_MULTI_V7
@@ -118,7 +109,7 @@ config ARCH_OMAP2PLUS
select OMAP_IRQCHIP
select CLKSRC_TI_32K
help
- Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
+ Systems based on OMAP3, OMAP4 or OMAP5
config OMAP_INTERCONNECT_BARRIER
bool
@@ -129,7 +120,7 @@ config ARCH_OMAP
if ARCH_OMAP2PLUS
-menu "TI OMAP2/3/4 Specific Features"
+menu "TI OMAP3/4 Specific Features"
config ARCH_OMAP2PLUS_TYPICAL
bool "Typical OMAP configuration"
@@ -138,8 +129,7 @@ config ARCH_OMAP2PLUS_TYPICAL
select HIGHMEM
select I2C
select I2C_OMAP
- select MENELAUS if ARCH_OMAP2
- select NEON if CPU_V7
+ select NEON
select REGULATOR
select REGULATOR_FIXED_VOLTAGE
select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
@@ -204,27 +194,7 @@ config OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
PPA routine service ID for setting L2 auxiliary control register.
comment "OMAP Core Type"
- depends on ARCH_OMAP2
-
-config SOC_OMAP2420
- bool "OMAP2420 support (DEPRECATED)"
- depends on ARCH_OMAP2
- default y
- select OMAP_DM_SYSTIMER
- select OMAP_DM_TIMER
- select SOC_HAS_OMAP2_SDRC
- help
- This SoC is scheduled for removal in early 2027,
- since it uses the ARM1136r0 CPU revision.
-
-config SOC_OMAP2430
- bool "OMAP2430 support (DEPRECATED)"
- depends on ARCH_OMAP2
- default y
- select SOC_HAS_OMAP2_SDRC
- help
- This SoC is scheduled for removal in early 2027,
- since it uses the ARM1136r0 CPU revision.
+ depends on ARCH_OMAP3
config SOC_OMAP3430
bool "OMAP3430 support"
@@ -237,33 +207,9 @@ config SOC_TI81XX
depends on ARCH_OMAP3
default y
-comment "OMAP Legacy Platform Data Board Type"
- depends on ARCH_OMAP2PLUS
-
config MACH_OMAP_GENERIC
bool
-config MACH_OMAP2_TUSB6010
- bool
- depends on ARCH_OMAP2 && SOC_OMAP2420
- default y if MACH_NOKIA_N8X0
-
-config MACH_NOKIA_N810
- bool
-
-config MACH_NOKIA_N810_WIMAX
- bool
-
-config MACH_NOKIA_N8X0
- bool "Nokia N800/N810 (DEPRECATED)"
- depends on SOC_OMAP2420
- default y
- select MACH_NOKIA_N810
- select MACH_NOKIA_N810_WIMAX
- help
- This machine is scheduled for removal in early 2027,
- since it uses the ARM1136r0 CPU revision.
-
endmenu
endif
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index daf21127c82f..6c741442dc0d 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -5,23 +5,17 @@
# Common support
obj-y := id.o io.o control.o devices.o fb.o pm.o \
- common.o dma.o omap-headsmp.o sram.o
+ common.o dma.o omap-headsmp.o
-hwmod-common = omap_hwmod.o \
+# OMAP3 hwmod specific
+obj-$(CONFIG_ARCH_OMAP3) += sram.o omap_hwmod.o \
omap_hwmod_common_data.o \
omap_hwmod_common_ipblock_data.o \
omap_device.o display.o hdq1w.o \
i2c.o wd_timer.o
-clock-common = clock.o
-secure-common = omap-smc.o omap-secure.o
-obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
-obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
-obj-$(CONFIG_ARCH_OMAP4) += $(secure-common)
-obj-$(CONFIG_SOC_AM33XX) += $(secure-common)
-obj-$(CONFIG_SOC_OMAP5) += $(secure-common)
-obj-$(CONFIG_SOC_AM43XX) += $(secure-common)
-obj-$(CONFIG_SOC_DRA7XX) += $(secure-common)
+# secure world
+obj-y += omap-smc.o omap-secure.o
ifneq ($(CONFIG_SND_SOC_OMAP_MCBSP),)
obj-$(CONFIG_OMAP_HWMOD) += mcbsp.o
@@ -49,13 +43,7 @@ omap5-dra7-common-$(CONFIG_SOC_HAS_REALTIME_COUNTER) = timer.o
obj-$(CONFIG_SOC_OMAP5) += $(omap5-dra7-common-y)
obj-$(CONFIG_SOC_DRA7XX) += $(omap5-dra7-common-y)
-# Functions loaded to SRAM
-obj-$(CONFIG_SOC_OMAP2420) += sram242x.o
-obj-$(CONFIG_SOC_OMAP2430) += sram243x.o
-
# Restart code (OMAP4/5 currently in omap4-common.c)
-obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o
-obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o
obj-$(CONFIG_SOC_TI81XX) += ti81xx-restart.o
obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o
obj-$(CONFIG_SOC_AM43XX) += omap4-restart.o
@@ -65,7 +53,6 @@ obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
# SMS/SDRC
-obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
# OPP table initialization
@@ -80,7 +67,6 @@ obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-pm-common)
ifeq ($(CONFIG_PM),y)
-obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
omap-4-5-pm-common += pm44xx.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common)
@@ -105,7 +91,6 @@ endif
# PRCM
obj-y += prm_common.o cm_common.o
-obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
omap-prcm-4-5-common = cminst44xx.o prm44xx.o \
@@ -122,8 +107,6 @@ obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common) \
# OMAP voltage domains
voltagedomain-common := voltage.o vc.o vp.o
-obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common)
-obj-$(CONFIG_ARCH_OMAP2) += voltagedomains2xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
@@ -136,9 +119,6 @@ obj-$(CONFIG_SOC_DRA7XX) += $(voltagedomain-common)
# OMAP powerdomain framework
powerdomain-common += powerdomain.o powerdomain-common.o
-obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common)
-obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_data.o
-obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common)
obj-$(CONFIG_ARCH_OMAP3) += powerdomains3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
@@ -155,10 +135,6 @@ obj-$(CONFIG_SOC_DRA7XX) += powerdomains7xx_data.o
# PRCM clockdomain control
clockdomain-common += clockdomain.o
-obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common)
-obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o
-obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o
-obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common)
obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
@@ -176,47 +152,20 @@ obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
# Clock framework
-obj-$(CONFIG_ARCH_OMAP2) += $(clock-common)
-obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
-obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
-obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o
-obj-$(CONFIG_ARCH_OMAP3) += $(clock-common)
-obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
-obj-$(CONFIG_SOC_AM33XX) += $(clock-common)
-obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
-obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
-obj-$(CONFIG_SOC_AM43XX) += $(clock-common)
-
-# OMAP2 clock rate set data (old "OPP" data)
-obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
-obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
+obj-y += clock.o
# hwmod data
-obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o
-obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o
-obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o
-obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o
-obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o
-obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_3xxx_ipblock_data.o
-obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o
-obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
obj-$(CONFIG_SOC_TI81XX) += omap_hwmod_81xx_data.o
-# OMAP2420 MSDI controller integration support ("MMC")
-obj-$(CONFIG_SOC_OMAP2420) += msdi.o
-
# Specific board support
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o
-obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
# Platform specific device init code
obj-y += omap_phy_internal.o
-obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
-
$(obj)/pm-asm-offsets.h: $(obj)/pm-asm-offsets.s FORCE
$(call filechk,offsets,__TI_PM_ASM_OFFSETS_H__)
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index bff673e932fe..972b8cf0547f 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -45,40 +45,6 @@ void tick_broadcast(const struct cpumask *mask)
}
#endif
-#ifdef CONFIG_SOC_OMAP2420
-static const char *const omap242x_boards_compat[] __initconst = {
- "ti,omap2420",
- NULL,
-};
-
-DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
- .reserve = omap_reserve,
- .map_io = omap242x_map_io,
- .init_early = omap2420_init_early,
- .init_machine = omap_generic_init,
- .init_time = omap_init_time_of,
- .dt_compat = omap242x_boards_compat,
- .restart = omap2xxx_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_SOC_OMAP2430
-static const char *const omap243x_boards_compat[] __initconst = {
- "ti,omap2430",
- NULL,
-};
-
-DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
- .reserve = omap_reserve,
- .map_io = omap243x_map_io,
- .init_early = omap2430_init_early,
- .init_machine = omap_generic_init,
- .init_time = omap_init_time_of,
- .dt_compat = omap243x_boards_compat,
- .restart = omap2xxx_restart,
-MACHINE_END
-#endif
-
#ifdef CONFIG_ARCH_OMAP3
/* Some boards need board name for legacy userspace in /proc/cpuinfo */
static const char *const n900_boards_compat[] __initconst = {
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
deleted file mode 100644
index d9acd32c5457..000000000000
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ /dev/null
@@ -1,512 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap2/board-n8x0.c
- *
- * Copyright (C) 2005-2009 Nokia Corporation
- * Author: Juha Yrjola <juha.yrjola@nokia.com>
- *
- * Modified from mach-omap2/board-generic.c
- */
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio/consumer.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/stddef.h>
-#include <linux/i2c.h>
-#include <linux/spi/spi.h>
-#include <linux/usb/musb.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_data/mmc-omap.h>
-#include <linux/mfd/menelaus.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include "common.h"
-#include "mmc.h"
-#include "usb-tusb6010.h"
-#include "soc.h"
-#include "common-board-devices.h"
-
-#define TUSB6010_ASYNC_CS 1
-#define TUSB6010_SYNC_CS 4
-#define TUSB6010_DMACHAN 0x3f
-
-#define NOKIA_N810_WIMAX (1 << 2)
-#define NOKIA_N810 (1 << 1)
-#define NOKIA_N800 (1 << 0)
-
-static u32 board_caps;
-
-#define board_is_n800() (board_caps & NOKIA_N800)
-#define board_is_n810() (board_caps & NOKIA_N810)
-#define board_is_n810_wimax() (board_caps & NOKIA_N810_WIMAX)
-
-static void board_check_revision(void)
-{
- if (of_machine_is_compatible("nokia,n800"))
- board_caps = NOKIA_N800;
- else if (of_machine_is_compatible("nokia,n810"))
- board_caps = NOKIA_N810;
- else if (of_machine_is_compatible("nokia,n810-wimax"))
- board_caps = NOKIA_N810_WIMAX;
-
- if (!board_caps)
- pr_err("Unknown board\n");
-}
-
-#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 1,
- .dyn_fifo = 1,
- .num_eps = 16,
- .ram_bits = 12,
-};
-
-static struct musb_hdrc_platform_data tusb_data = {
- .mode = MUSB_OTG,
- .min_power = 25, /* x2 = 50 mA drawn from VBUS as peripheral */
- .power = 100, /* Max 100 mA VBUS for host mode */
- .config = &musb_config,
-};
-
-static struct gpiod_lookup_table tusb_gpio_table = {
- .dev_id = "musb-tusb",
- .table = {
- GPIO_LOOKUP("gpio-0-31", 0, "enable", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-32-63", 26, "int", GPIO_ACTIVE_HIGH),
- { }
- },
-};
-
-static void __init n8x0_usb_init(void)
-{
- int ret = 0;
-
- gpiod_add_lookup_table(&tusb_gpio_table);
- ret = tusb6010_setup_interface(&tusb_data, TUSB6010_REFCLK_19, 2,
- TUSB6010_ASYNC_CS, TUSB6010_SYNC_CS,
- TUSB6010_DMACHAN);
- if (ret != 0)
- return;
-
- pr_info("TUSB 6010\n");
-
- return;
-}
-#else
-
-static void __init n8x0_usb_init(void) {}
-
-#endif /*CONFIG_USB_MUSB_TUSB6010 */
-
-#if defined(CONFIG_MENELAUS) && IS_ENABLED(CONFIG_MMC_OMAP)
-
-/*
- * On both N800 and N810, only the first of the two MMC controllers is in use.
- * The two MMC slots are multiplexed via Menelaus companion chip over I2C.
- * On N800, both slots are powered via Menelaus. On N810, only one of the
- * slots is powered via Menelaus. The N810 EMMC is powered via GPIO.
- *
- * VMMC slot 1 on both N800 and N810
- * VDCDC3_APE and VMCS2_APE slot 2 on N800
- * GPIO23 and GPIO9 slot 2 EMMC on N810
- *
- */
-static int slot1_cover_open;
-static int slot2_cover_open;
-static struct device *mmc_device;
-
-static struct gpiod_lookup_table nokia800_mmc_gpio_table = {
- .dev_id = "mmci-omap.0",
- .table = {
- /* Slot switch, GPIO 96 */
- GPIO_LOOKUP("gpio-96-127", 0, "switch", GPIO_ACTIVE_HIGH),
- { }
- },
-};
-
-static struct gpiod_lookup_table nokia810_mmc_gpio_table = {
- .dev_id = "mmci-omap.0",
- .table = {
- /* Slot switch, GPIO 96 */
- GPIO_LOOKUP("gpio-96-127", 0, "switch", GPIO_ACTIVE_HIGH),
- /* Slot index 1, VSD power, GPIO 23 */
- GPIO_LOOKUP_IDX("gpio-0-31", 23, "vsd", 1, GPIO_ACTIVE_HIGH),
- /* Slot index 1, VIO power, GPIO 9 */
- GPIO_LOOKUP_IDX("gpio-0-31", 9, "vio", 1, GPIO_ACTIVE_HIGH),
- { }
- },
-};
-
-static int n8x0_mmc_set_power_menelaus(struct device *dev, int slot,
- int power_on, int vdd)
-{
- int mV;
-
-#ifdef CONFIG_MMC_DEBUG
- dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1,
- str_on_off(power_on), vdd);
-#endif
- if (slot == 0) {
- if (!power_on)
- return menelaus_set_vmmc(0);
- switch (1 << vdd) {
- case MMC_VDD_33_34:
- case MMC_VDD_32_33:
- case MMC_VDD_31_32:
- mV = 3100;
- break;
- case MMC_VDD_30_31:
- mV = 3000;
- break;
- case MMC_VDD_28_29:
- mV = 2800;
- break;
- case MMC_VDD_165_195:
- mV = 1850;
- break;
- default:
- BUG();
- }
- return menelaus_set_vmmc(mV);
- } else {
- if (!power_on)
- return menelaus_set_vdcdc(3, 0);
- switch (1 << vdd) {
- case MMC_VDD_33_34:
- case MMC_VDD_32_33:
- mV = 3300;
- break;
- case MMC_VDD_30_31:
- case MMC_VDD_29_30:
- mV = 3000;
- break;
- case MMC_VDD_28_29:
- case MMC_VDD_27_28:
- mV = 2800;
- break;
- case MMC_VDD_24_25:
- case MMC_VDD_23_24:
- mV = 2400;
- break;
- case MMC_VDD_22_23:
- case MMC_VDD_21_22:
- mV = 2200;
- break;
- case MMC_VDD_20_21:
- mV = 2000;
- break;
- case MMC_VDD_165_195:
- mV = 1800;
- break;
- default:
- BUG();
- }
- return menelaus_set_vdcdc(3, mV);
- }
- return 0;
-}
-
-static int n8x0_mmc_set_power(struct device *dev, int slot, int power_on,
- int vdd)
-{
- if (board_is_n800() || slot == 0)
- return n8x0_mmc_set_power_menelaus(dev, slot, power_on, vdd);
-
- /* The n810 power will be handled by GPIO code in the driver */
-
- return 0;
-}
-
-static int n8x0_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode)
-{
- int r;
-
- dev_dbg(dev, "Set slot %d bus mode %s\n", slot + 1,
- bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull");
- BUG_ON(slot != 0 && slot != 1);
- slot++;
- switch (bus_mode) {
- case MMC_BUSMODE_OPENDRAIN:
- r = menelaus_set_mmc_opendrain(slot, 1);
- break;
- case MMC_BUSMODE_PUSHPULL:
- r = menelaus_set_mmc_opendrain(slot, 0);
- break;
- default:
- BUG();
- }
- if (r != 0 && printk_ratelimit())
- dev_err(dev, "MMC: unable to set bus mode for slot %d\n",
- slot);
- return r;
-}
-
-static int n8x0_mmc_get_cover_state(struct device *dev, int slot)
-{
- slot++;
- BUG_ON(slot != 1 && slot != 2);
- if (slot == 1)
- return slot1_cover_open;
- else
- return slot2_cover_open;
-}
-
-static void n8x0_mmc_callback(void *data, u8 card_mask)
-{
-#ifdef CONFIG_MMC_OMAP
- int bit, *openp, index;
-
- if (board_is_n800()) {
- bit = 1 << 1;
- openp = &slot2_cover_open;
- index = 1;
- } else {
- bit = 1;
- openp = &slot1_cover_open;
- index = 0;
- }
-
- if (card_mask & bit)
- *openp = 1;
- else
- *openp = 0;
-
- omap_mmc_notify_cover_event(mmc_device, index, *openp);
-#else
- pr_warn("MMC: notify cover event not available\n");
-#endif
-}
-
-static int n8x0_mmc_late_init(struct device *dev)
-{
- int r, bit, *openp;
- int vs2sel;
-
- mmc_device = dev;
-
- r = menelaus_set_slot_sel(1);
- if (r < 0)
- return r;
-
- if (board_is_n800())
- vs2sel = 0;
- else
- vs2sel = 2;
-
- r = menelaus_set_mmc_slot(2, 0, vs2sel, 1);
- if (r < 0)
- return r;
-
- n8x0_mmc_set_power(dev, 0, MMC_POWER_ON, 16); /* MMC_VDD_28_29 */
- n8x0_mmc_set_power(dev, 1, MMC_POWER_ON, 16);
-
- r = menelaus_set_mmc_slot(1, 1, 0, 1);
- if (r < 0)
- return r;
- r = menelaus_set_mmc_slot(2, 1, vs2sel, 1);
- if (r < 0)
- return r;
-
- r = menelaus_get_slot_pin_states();
- if (r < 0)
- return r;
-
- if (board_is_n800()) {
- bit = 1 << 1;
- openp = &slot2_cover_open;
- } else {
- bit = 1;
- openp = &slot1_cover_open;
- slot2_cover_open = 0;
- }
-
- /* All slot pin bits seem to be inversed until first switch change */
- if (r == 0xf || r == (0xf & ~bit))
- r = ~r;
-
- if (r & bit)
- *openp = 1;
- else
- *openp = 0;
-
- r = menelaus_register_mmc_callback(n8x0_mmc_callback, NULL);
-
- return r;
-}
-
-static void n8x0_mmc_shutdown(struct device *dev)
-{
- int vs2sel;
-
- if (board_is_n800())
- vs2sel = 0;
- else
- vs2sel = 2;
-
- menelaus_set_mmc_slot(1, 0, 0, 0);
- menelaus_set_mmc_slot(2, 0, vs2sel, 0);
-}
-
-static void n8x0_mmc_cleanup(struct device *dev)
-{
- menelaus_unregister_mmc_callback();
-}
-
-/*
- * MMC controller1 has two slots that are multiplexed via I2C.
- * MMC controller2 is not in use.
- */
-static struct omap_mmc_platform_data mmc1_data = {
- .nr_slots = 0,
- .init = n8x0_mmc_late_init,
- .cleanup = n8x0_mmc_cleanup,
- .shutdown = n8x0_mmc_shutdown,
- .max_freq = 24000000,
- .slots[0] = {
- .wires = 4,
- .set_power = n8x0_mmc_set_power,
- .set_bus_mode = n8x0_mmc_set_bus_mode,
- .get_cover_state = n8x0_mmc_get_cover_state,
- .ocr_mask = MMC_VDD_165_195 | MMC_VDD_30_31 |
- MMC_VDD_32_33 | MMC_VDD_33_34,
- .name = "internal",
- },
- .slots[1] = {
- .set_power = n8x0_mmc_set_power,
- .set_bus_mode = n8x0_mmc_set_bus_mode,
- .get_cover_state = n8x0_mmc_get_cover_state,
- .ocr_mask = MMC_VDD_165_195 | MMC_VDD_20_21 |
- MMC_VDD_21_22 | MMC_VDD_22_23 |
- MMC_VDD_23_24 | MMC_VDD_24_25 |
- MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 |
- MMC_VDD_32_33 | MMC_VDD_33_34,
- .name = "external",
- },
-};
-
-static struct omap_mmc_platform_data *mmc_data[OMAP24XX_NR_MMC];
-
-static void __init n8x0_mmc_init(void)
-{
- if (board_is_n810()) {
- mmc1_data.slots[0].name = "external";
-
- /*
- * Some Samsung Movinand chips do not like open-ended
- * multi-block reads and fall to braind-dead state
- * while doing so. Reducing the number of blocks in
- * the transfer or delays in clock disable do not help
- */
- mmc1_data.slots[1].name = "internal";
- mmc1_data.slots[1].ban_openended = 1;
- gpiod_add_lookup_table(&nokia810_mmc_gpio_table);
- } else {
- gpiod_add_lookup_table(&nokia800_mmc_gpio_table);
- }
-
- mmc1_data.nr_slots = 2;
- mmc_data[0] = &mmc1_data;
-}
-#else
-static struct omap_mmc_platform_data mmc1_data;
-static void __init n8x0_mmc_init(void)
-{
-}
-#endif /* CONFIG_MMC_OMAP */
-
-#ifdef CONFIG_MENELAUS
-
-static int n8x0_auto_sleep_regulators(void)
-{
- u32 val;
- int ret;
-
- val = EN_VPLL_SLEEP | EN_VMMC_SLEEP \
- | EN_VAUX_SLEEP | EN_VIO_SLEEP \
- | EN_VMEM_SLEEP | EN_DC3_SLEEP \
- | EN_VC_SLEEP | EN_DC2_SLEEP;
-
- ret = menelaus_set_regulator_sleep(1, val);
- if (ret < 0) {
- pr_err("Could not set regulators to sleep on menelaus: %u\n",
- ret);
- return ret;
- }
- return 0;
-}
-
-static int n8x0_auto_voltage_scale(void)
-{
- int ret;
-
- ret = menelaus_set_vcore_hw(1400, 1050);
- if (ret < 0) {
- pr_err("Could not set VCORE voltage on menelaus: %u\n", ret);
- return ret;
- }
- return 0;
-}
-
-static int n8x0_menelaus_late_init(struct device *dev)
-{
- int ret;
-
- ret = n8x0_auto_voltage_scale();
- if (ret < 0)
- return ret;
- ret = n8x0_auto_sleep_regulators();
- if (ret < 0)
- return ret;
- return 0;
-}
-
-#else
-static int n8x0_menelaus_late_init(struct device *dev)
-{
- return 0;
-}
-#endif
-
-struct menelaus_platform_data n8x0_menelaus_platform_data = {
- .late_init = n8x0_menelaus_late_init,
-};
-
-static struct gpiod_lookup_table nokia810_asoc_gpio_table = {
- .dev_id = "soc-audio",
- .table = {
- GPIO_LOOKUP("gpio-0-15", 10, "headset", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-80-111", 21, "speaker", GPIO_ACTIVE_HIGH),
- { }
- },
-};
-
-static int __init n8x0_late_initcall(void)
-{
- if (!board_caps)
- return -ENODEV;
-
- n8x0_mmc_init();
- n8x0_usb_init();
- gpiod_add_lookup_table(&nokia810_asoc_gpio_table);
-
- return 0;
-}
-omap_late_initcall(n8x0_late_initcall);
-
-/*
- * Legacy init pdata init for n8x0. Note that we want to follow the
- * I2C bus numbering starting at 0 for device tree like other omaps.
- */
-void * __init n8x0_legacy_init(void)
-{
- board_check_revision();
- return &mmc1_data;
-}
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c
deleted file mode 100644
index 0edebf3355fa..000000000000
--- a/arch/arm/mach-omap2/clkt2xxx_dpll.c
+++ /dev/null
@@ -1,56 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * OMAP2-specific DPLL control functions
- *
- * Copyright (C) 2011 Nokia Corporation
- * Paul Walmsley
- */
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include "clock.h"
-#include "cm2xxx.h"
-#include "cm-regbits-24xx.h"
-
-/* Private functions */
-
-/**
- * _allow_idle - enable DPLL autoidle bits
- * @clk: struct clk * of the DPLL to operate on
- *
- * Enable DPLL automatic idle control. The DPLL will enter low-power
- * stop when its downstream clocks are gated. No return value.
- * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
- * instead. Add some mechanism to optionally enter this mode.
- */
-static void _allow_idle(struct clk_hw_omap *clk)
-{
- if (!clk || !clk->dpll_data)
- return;
-
- omap2xxx_cm_set_dpll_auto_low_power_stop();
-}
-
-/**
- * _deny_idle - prevent DPLL from automatically idling
- * @clk: struct clk * of the DPLL to operate on
- *
- * Disable DPLL automatic idle control. No return value.
- */
-static void _deny_idle(struct clk_hw_omap *clk)
-{
- if (!clk || !clk->dpll_data)
- return;
-
- omap2xxx_cm_set_dpll_disable_autoidle();
-}
-
-
-/* Public data */
-const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = {
- .allow_idle = _allow_idle,
- .deny_idle = _deny_idle,
-};
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
deleted file mode 100644
index 93f6d3cd9525..000000000000
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ /dev/null
@@ -1,194 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * DPLL + CORE_CLK composite clock functions
- *
- * Copyright (C) 2005-2008 Texas Instruments, Inc.
- * Copyright (C) 2004-2010 Nokia Corporation
- *
- * Contacts:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Paul Walmsley
- *
- * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
- * Gordon McNutt and RidgeRun, Inc.
- *
- * XXX The DPLL and CORE clocks should be split into two separate clock
- * types.
- */
-#undef DEBUG
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/clk/ti.h>
-#include <linux/io.h>
-
-#include "clock.h"
-#include "clock2xxx.h"
-#include "opp2xxx.h"
-#include "cm2xxx.h"
-#include "cm-regbits-24xx.h"
-#include "sdrc.h"
-#include "sram.h"
-
-/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
-
-/*
- * dpll_core_ck: pointer to the combined dpll_ck + core_ck on OMAP2xxx
- * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set
- * during dpll_ck init and used later by omap2xxx_clk_get_core_rate().
- */
-static struct clk_hw_omap *dpll_core_ck;
-
-/**
- * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
- *
- * Returns the CORE_CLK rate. CORE_CLK can have one of three rate
- * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
- * (the latter is unusual). This currently should be called with
- * struct clk *dpll_ck, which is a composite clock of dpll_ck and
- * core_ck.
- */
-unsigned long omap2xxx_clk_get_core_rate(void)
-{
- long long core_clk;
- u32 v;
-
- WARN_ON(!dpll_core_ck);
-
- core_clk = omap2_get_dpll_rate(dpll_core_ck);
-
- v = omap2xxx_cm_get_core_clk_src();
-
- if (v == CORE_CLK_SRC_32K)
- core_clk = 32768;
- else
- core_clk *= v;
-
- return core_clk;
-}
-
-/*
- * Uses the current prcm set to tell if a rate is valid.
- * You can go slower, but not faster within a given rate set.
- */
-static long omap2_dpllcore_round_rate(unsigned long target_rate)
-{
- u32 high, low, core_clk_src;
-
- core_clk_src = omap2xxx_cm_get_core_clk_src();
-
- if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
- high = curr_prcm_set->dpll_speed * 2;
- low = curr_prcm_set->dpll_speed;
- } else { /* DPLL clockout x 2 */
- high = curr_prcm_set->dpll_speed;
- low = curr_prcm_set->dpll_speed / 2;
- }
-
-#ifdef DOWN_VARIABLE_DPLL
- if (target_rate > high)
- return high;
- else
- return target_rate;
-#else
- if (target_rate > low)
- return high;
- else
- return low;
-#endif
-
-}
-
-unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- return omap2xxx_clk_get_core_rate();
-}
-
-int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
-{
- struct clk_hw_omap *clk = to_clk_hw_omap(hw);
- u32 cur_rate, low, mult, div, valid_rate, done_rate;
- u32 bypass = 0;
- struct prcm_config tmpset;
- const struct dpll_data *dd;
-
- cur_rate = omap2xxx_clk_get_core_rate();
- mult = omap2xxx_cm_get_core_clk_src();
-
- if ((rate == (cur_rate / 2)) && (mult == 2)) {
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
- } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
- } else if (rate != cur_rate) {
- valid_rate = omap2_dpllcore_round_rate(rate);
- if (valid_rate != rate)
- return -EINVAL;
-
- if (mult == 1)
- low = curr_prcm_set->dpll_speed;
- else
- low = curr_prcm_set->dpll_speed / 2;
-
- dd = clk->dpll_data;
- if (!dd)
- return -EINVAL;
-
- tmpset.cm_clksel1_pll =
- omap_clk_ll_ops.clk_readl(&dd->mult_div1_reg);
- tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
- dd->div1_mask);
- div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
- tmpset.cm_clksel2_pll = omap2xxx_cm_get_core_pll_config();
- tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
- if (rate > low) {
- tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
- mult = ((rate / 2) / 1000000);
- done_rate = CORE_CLK_SRC_DPLL_X2;
- } else {
- tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
- mult = (rate / 1000000);
- done_rate = CORE_CLK_SRC_DPLL;
- }
- tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
- tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
-
- /* Worst case */
- tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
-
- if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
- bypass = 1;
-
- /* For omap2xxx_sdrc_init_params() */
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-
- /* Force dll lock mode */
- omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
- bypass);
-
- /* Errata: ret dll entry state */
- omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
- omap2xxx_sdrc_reprogram(done_rate, 0);
- }
-
- return 0;
-}
-
-/**
- * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck
- * @clk: struct clk *dpll_ck
- *
- * Store a local copy of @clk in dpll_core_ck so other code can query
- * the core rate without having to clk_get(), which can sleep. Must
- * only be called once. No return value. XXX If the clock
- * registration process is ever changed such that dpll_ck is no longer
- * statically defined, this code may need to change to increment some
- * kind of use count on dpll_ck.
- */
-void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw)
-{
- WARN(dpll_core_ck, "dpll_core_ck already set - should never happen");
- dpll_core_ck = to_clk_hw_omap(hw);
-}
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
deleted file mode 100644
index 2b04e422b46c..000000000000
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ /dev/null
@@ -1,259 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * OMAP2xxx DVFS virtual clock functions
- *
- * Copyright (C) 2005-2008, 2012 Texas Instruments, Inc.
- * Copyright (C) 2004-2010 Nokia Corporation
- *
- * Contacts:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Paul Walmsley
- *
- * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
- * Gordon McNutt and RidgeRun, Inc.
- *
- * XXX Some of this code should be replaceable by the upcoming OPP layer
- * code. However, some notion of "rate set" is probably still necessary
- * for OMAP2xxx at least. Rate sets should be generalized so they can be
- * used for any OMAP chip, not just OMAP2xxx. In particular, Richard Woodruff
- * has in the past expressed a preference to use rate sets for OPP changes,
- * rather than dynamically recalculating the clock tree, so if someone wants
- * this badly enough to write the code to handle it, we should support it
- * as an option.
- */
-#undef DEBUG
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/cpufreq.h>
-#include <linux/slab.h>
-
-#include "soc.h"
-#include "clock.h"
-#include "clock2xxx.h"
-#include "opp2xxx.h"
-#include "cm2xxx.h"
-#include "cm-regbits-24xx.h"
-#include "sdrc.h"
-#include "sram.h"
-
-static u16 cpu_mask;
-
-const struct prcm_config *curr_prcm_set;
-const struct prcm_config *rate_table;
-
-/*
- * sys_ck_rate: the rate of the external high-frequency clock
- * oscillator on the board. Set by the SoC-specific clock init code.
- * Once set during a boot, will not change.
- */
-static unsigned long sys_ck_rate;
-
-/**
- * omap2_table_mpu_recalc - just return the MPU speed
- * @clk: virt_prcm_set struct clk
- *
- * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
- */
-static unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
- unsigned long parent_rate)
-{
- return curr_prcm_set->mpu_speed;
-}
-
-/*
- * Look for a rate equal or less than the target rate given a configuration set.
- *
- * What's not entirely clear is "which" field represents the key field.
- * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
- * just uses the ARM rates.
- */
-static int omap2_determine_rate_to_table(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- const struct prcm_config *ptr;
- long highest_rate;
-
- highest_rate = -EINVAL;
-
- for (ptr = rate_table; ptr->mpu_speed; ptr++) {
- if (!(ptr->flags & cpu_mask))
- continue;
- if (ptr->xtal_speed != sys_ck_rate)
- continue;
-
- highest_rate = ptr->mpu_speed;
-
- /* Can check only after xtal frequency check */
- if (ptr->mpu_speed <= req->rate)
- break;
- }
- req->rate = highest_rate;
-
- return 0;
-}
-
-/* Sets basic clocks based on the specified rate */
-static int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
-{
- u32 cur_rate, done_rate, bypass = 0;
- const struct prcm_config *prcm;
- unsigned long found_speed = 0;
- unsigned long flags;
-
- for (prcm = rate_table; prcm->mpu_speed; prcm++) {
- if (!(prcm->flags & cpu_mask))
- continue;
-
- if (prcm->xtal_speed != sys_ck_rate)
- continue;
-
- if (prcm->mpu_speed <= rate) {
- found_speed = prcm->mpu_speed;
- break;
- }
- }
-
- if (!found_speed) {
- printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
- rate / 1000000);
- return -EINVAL;
- }
-
- curr_prcm_set = prcm;
- cur_rate = omap2xxx_clk_get_core_rate();
-
- if (prcm->dpll_speed == cur_rate / 2) {
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
- } else if (prcm->dpll_speed == cur_rate * 2) {
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
- } else if (prcm->dpll_speed != cur_rate) {
- local_irq_save(flags);
-
- if (prcm->dpll_speed == prcm->xtal_speed)
- bypass = 1;
-
- if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
- CORE_CLK_SRC_DPLL_X2)
- done_rate = CORE_CLK_SRC_DPLL_X2;
- else
- done_rate = CORE_CLK_SRC_DPLL;
-
- omap2xxx_cm_set_mod_dividers(prcm->cm_clksel_mpu,
- prcm->cm_clksel_dsp,
- prcm->cm_clksel_gfx,
- prcm->cm_clksel1_core,
- prcm->cm_clksel_mdm);
-
- /* x2 to enter omap2xxx_sdrc_init_params() */
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-
- omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
- bypass);
-
- omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
- omap2xxx_sdrc_reprogram(done_rate, 0);
-
- local_irq_restore(flags);
- }
-
- return 0;
-}
-
-/**
- * omap2xxx_clkt_vps_check_bootloader_rates - determine which of the rate
- * table sets matches the current CORE DPLL hardware rate
- *
- * Check the MPU rate set by bootloader. Sets the 'curr_prcm_set'
- * global to point to the active rate set when found; otherwise, sets
- * it to NULL. No return value;
- */
-static void omap2xxx_clkt_vps_check_bootloader_rates(void)
-{
- const struct prcm_config *prcm = NULL;
- unsigned long rate;
-
- rate = omap2xxx_clk_get_core_rate();
- for (prcm = rate_table; prcm->mpu_speed; prcm++) {
- if (!(prcm->flags & cpu_mask))
- continue;
- if (prcm->xtal_speed != sys_ck_rate)
- continue;
- if (prcm->dpll_speed <= rate)
- break;
- }
- curr_prcm_set = prcm;
-}
-
-/**
- * omap2xxx_clkt_vps_late_init - store a copy of the sys_ck rate
- *
- * Store a copy of the sys_ck rate for later use by the OMAP2xxx DVFS
- * code. (The sys_ck rate does not -- or rather, must not -- change
- * during kernel runtime.) Must be called after we have a valid
- * sys_ck rate, but before the virt_prcm_set clock rate is
- * recalculated. No return value.
- */
-static void omap2xxx_clkt_vps_late_init(void)
-{
- struct clk *c;
-
- c = clk_get(NULL, "sys_ck");
- if (IS_ERR(c)) {
- WARN(1, "could not locate sys_ck\n");
- } else {
- sys_ck_rate = clk_get_rate(c);
- clk_put(c);
- }
-}
-
-#ifdef CONFIG_OF
-#include <linux/clk-provider.h>
-#include <linux/clkdev.h>
-
-static const struct clk_ops virt_prcm_set_ops = {
- .recalc_rate = &omap2_table_mpu_recalc,
- .set_rate = &omap2_select_table_rate,
- .determine_rate = &omap2_determine_rate_to_table,
-};
-
-/**
- * omap2xxx_clkt_vps_init - initialize virt_prcm_set clock
- *
- * Does a manual init for the virtual prcm DVFS clock for OMAP2. This
- * function is called only from omap2 DT clock init, as the virtual
- * node is not modelled in the DT clock data.
- */
-void omap2xxx_clkt_vps_init(void)
-{
- struct clk_init_data init = { NULL };
- struct clk_hw_omap *hw = NULL;
- struct clk *clk;
- const char *parent_name = "mpu_ck";
-
- omap2xxx_clkt_vps_late_init();
- omap2xxx_clkt_vps_check_bootloader_rates();
-
- hw = kzalloc_obj(*hw);
- if (!hw)
- return;
- init.name = "virt_prcm_set";
- init.ops = &virt_prcm_set_ops;
- init.parent_names = &parent_name;
- init.num_parents = 1;
-
- hw->hw.init = &init;
-
- clk = clk_register(NULL, &hw->hw);
- if (IS_ERR(clk)) {
- printk(KERN_ERR "Failed to register clock\n");
- kfree(hw);
- return;
- }
-
- clkdev_create(clk, "cpufreq_ck", NULL);
-}
-#endif
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 83fae51722a9..b73a80503da8 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -30,9 +30,7 @@
#include "clockdomain.h"
#include "clock.h"
#include "cm.h"
-#include "cm2xxx.h"
#include "cm3xxx.h"
-#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
#include "common.h"
@@ -94,11 +92,7 @@ void __init ti_clk_init_features(void)
}
/* Bypass value setup for DPLLs */
- if (cpu_is_omap24xx()) {
- features.dpll_bypass_vals |=
- (1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
- (1 << OMAP2XXX_EN_DPLL_FRBYPASS);
- } else if (cpu_is_omap34xx()) {
+ if (cpu_is_omap34xx()) {
features.dpll_bypass_vals |=
(1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
(1 << OMAP3XXX_EN_DPLL_FRBYPASS);
@@ -122,9 +116,7 @@ void __init ti_clk_init_features(void)
* 34xx reverses this, just to keep us on our toes
* AM35xx uses both, depending on the module.
*/
- if (cpu_is_omap24xx())
- features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
- else if (cpu_is_omap34xx())
+ if (cpu_is_omap34xx())
features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
/* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
deleted file mode 100644
index 73c011dadfd2..000000000000
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * OMAP2 clock function prototypes and macros
- *
- * Copyright (C) 2005-2010 Texas Instruments, Inc.
- * Copyright (C) 2004-2010 Nokia Corporation
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
-#define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
-
-#include <linux/clk-provider.h>
-#include "clock.h"
-
-unsigned long omap2xxx_clk_get_core_rate(void);
-
-#endif
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 69dc5b839335..4b5ae1f40d50 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -1213,7 +1213,7 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
{
/* The clkdm attribute does not exist yet prior OMAP4 */
- if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ if (cpu_is_omap34xx())
return 0;
/*
@@ -1244,7 +1244,7 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
{
/* The clkdm attribute does not exist yet prior OMAP4 */
- if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ if (cpu_is_omap34xx())
return 0;
if (!oh)
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 86a2f9e5d0ef..2d422b5f121f 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -216,8 +216,6 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
void clkdm_save_context(void);
void clkdm_restore_context(void);
-extern void __init omap242x_clockdomains_init(void);
-extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
extern void __init am33xx_clockdomains_init(void);
extern void __init ti814x_clockdomains_init(void);
@@ -230,14 +228,11 @@ void am43xx_clockdomains_init(void);
extern void clkdm_add_autodeps(struct clockdomain *clkdm);
extern void clkdm_del_autodeps(struct clockdomain *clkdm);
-extern struct clkdm_ops omap2_clkdm_operations;
extern struct clkdm_ops omap3_clkdm_operations;
extern struct clkdm_ops omap4_clkdm_operations;
extern struct clkdm_ops am33xx_clkdm_operations;
extern struct clkdm_ops am43xx_clkdm_operations;
-extern struct clkdm_dep gfx_24xx_wkdeps[];
-extern struct clkdm_dep dsp_24xx_wkdeps[];
extern struct clockdomain wkup_common_clkdm;
#endif
diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c
deleted file mode 100644
index ac4ffb5d2ffc..000000000000
--- a/arch/arm/mach-omap2/clockdomains2420_data.c
+++ /dev/null
@@ -1,154 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * OMAP2420 clockdomains
- *
- * Copyright (C) 2008-2011 Texas Instruments, Inc.
- * Copyright (C) 2008-2010 Nokia Corporation
- *
- * Paul Walmsley, Jouni Högander
- *
- * This file contains clockdomains and clockdomain wakeup dependencies
- * for OMAP2420 chips. Some notes:
- *
- * A useful validation rule for struct clockdomain: Any clockdomain
- * referenced by a wkdep_srcs must have a dep_bit assigned. So
- * wkdep_srcs are really just software-controllable dependencies.
- * Non-software-controllable dependencies do exist, but they are not
- * encoded below (yet).
- *
- * 24xx does not support programmable sleep dependencies (SLEEPDEP)
- *
- * The overly-specific dep_bit names are due to a bit name collision
- * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
- * value are the same for all powerdomains: 2
- *
- * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
- * sanity check?
- * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
- */
-
-/*
- * To-Do List
- * -> Port the Sleep/Wakeup dependencies for the domains
- * from the Power domain framework
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-
-#include "soc.h"
-#include "clockdomain.h"
-#include "prm2xxx_3xxx.h"
-#include "cm2xxx_3xxx.h"
-#include "cm-regbits-24xx.h"
-#include "prm-regbits-24xx.h"
-
-/*
- * Clockdomain dependencies for wkdeps
- *
- * XXX Hardware dependencies (e.g., dependencies that cannot be
- * changed in software) are not included here yet, but should be.
- */
-
-/* Wakeup dependency source arrays */
-
-/* 2420-specific possible wakeup dependencies */
-
-/* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP */
-static struct clkdm_dep mpu_2420_wkdeps[] = {
- { .clkdm_name = "core_l3_clkdm" },
- { .clkdm_name = "core_l4_clkdm" },
- { .clkdm_name = "dsp_clkdm" },
- { .clkdm_name = "wkup_clkdm" },
- { NULL },
-};
-
-/* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP */
-static struct clkdm_dep core_2420_wkdeps[] = {
- { .clkdm_name = "dsp_clkdm" },
- { .clkdm_name = "gfx_clkdm" },
- { .clkdm_name = "mpu_clkdm" },
- { .clkdm_name = "wkup_clkdm" },
- { NULL },
-};
-
-/*
- * 2420-only clockdomains
- */
-
-static struct clockdomain mpu_2420_clkdm = {
- .name = "mpu_clkdm",
- .pwrdm = { .name = "mpu_pwrdm" },
- .flags = CLKDM_CAN_HWSUP,
- .wkdep_srcs = mpu_2420_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
-};
-
-static struct clockdomain iva1_2420_clkdm = {
- .name = "iva1_clkdm",
- .pwrdm = { .name = "dsp_pwrdm" },
- .flags = CLKDM_CAN_HWSUP_SWSUP,
- .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
- .wkdep_srcs = dsp_24xx_wkdeps,
- .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
-};
-
-static struct clockdomain dsp_2420_clkdm = {
- .name = "dsp_clkdm",
- .pwrdm = { .name = "dsp_pwrdm" },
- .flags = CLKDM_CAN_HWSUP_SWSUP,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
-};
-
-static struct clockdomain gfx_2420_clkdm = {
- .name = "gfx_clkdm",
- .pwrdm = { .name = "gfx_pwrdm" },
- .flags = CLKDM_CAN_HWSUP_SWSUP,
- .wkdep_srcs = gfx_24xx_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
-};
-
-static struct clockdomain core_l3_2420_clkdm = {
- .name = "core_l3_clkdm",
- .pwrdm = { .name = "core_pwrdm" },
- .flags = CLKDM_CAN_HWSUP,
- .wkdep_srcs = core_2420_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
-};
-
-static struct clockdomain core_l4_2420_clkdm = {
- .name = "core_l4_clkdm",
- .pwrdm = { .name = "core_pwrdm" },
- .flags = CLKDM_CAN_HWSUP,
- .wkdep_srcs = core_2420_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
-};
-
-static struct clockdomain dss_2420_clkdm = {
- .name = "dss_clkdm",
- .pwrdm = { .name = "core_pwrdm" },
- .flags = CLKDM_CAN_HWSUP,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
-};
-
-static struct clockdomain *clockdomains_omap242x[] __initdata = {
- &wkup_common_clkdm,
- &mpu_2420_clkdm,
- &iva1_2420_clkdm,
- &dsp_2420_clkdm,
- &gfx_2420_clkdm,
- &core_l3_2420_clkdm,
- &core_l4_2420_clkdm,
- &dss_2420_clkdm,
- NULL,
-};
-
-void __init omap242x_clockdomains_init(void)
-{
- if (!cpu_is_omap242x())
- return;
-
- clkdm_register_platform_funcs(&omap2_clkdm_operations);
- clkdm_register_clkdms(clockdomains_omap242x);
- clkdm_complete_init();
-}
diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c
deleted file mode 100644
index 0e97e178abaa..000000000000
--- a/arch/arm/mach-omap2/clockdomains2430_data.c
+++ /dev/null
@@ -1,181 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * OMAP2xxx clockdomains
- *
- * Copyright (C) 2008-2009 Texas Instruments, Inc.
- * Copyright (C) 2008-2010 Nokia Corporation
- *
- * Paul Walmsley, Jouni Högander
- *
- * This file contains clockdomains and clockdomain wakeup dependencies
- * for OMAP2xxx chips. Some notes:
- *
- * A useful validation rule for struct clockdomain: Any clockdomain
- * referenced by a wkdep_srcs must have a dep_bit assigned. So
- * wkdep_srcs are really just software-controllable dependencies.
- * Non-software-controllable dependencies do exist, but they are not
- * encoded below (yet).
- *
- * 24xx does not support programmable sleep dependencies (SLEEPDEP)
- *
- * The overly-specific dep_bit names are due to a bit name collision
- * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
- * value are the same for all powerdomains: 2
- *
- * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
- * sanity check?
- * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
- */
-
-/*
- * To-Do List
- * -> Port the Sleep/Wakeup dependencies for the domains
- * from the Power domain framework
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-
-#include "soc.h"
-#include "clockdomain.h"
-#include "prm2xxx_3xxx.h"
-#include "cm2xxx_3xxx.h"
-#include "cm-regbits-24xx.h"
-#include "prm-regbits-24xx.h"
-
-/*
- * Clockdomain dependencies for wkdeps
- *
- * XXX Hardware dependencies (e.g., dependencies that cannot be
- * changed in software) are not included here yet, but should be.
- */
-
-/* Wakeup dependency source arrays */
-
-/* 2430-specific possible wakeup dependencies */
-
-/* 2430 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP, MDM */
-static struct clkdm_dep core_2430_wkdeps[] = {
- { .clkdm_name = "dsp_clkdm" },
- { .clkdm_name = "gfx_clkdm" },
- { .clkdm_name = "mpu_clkdm" },
- { .clkdm_name = "wkup_clkdm" },
- { .clkdm_name = "mdm_clkdm" },
- { NULL },
-};
-
-/* 2430 PM_WKDEP_MPU: CORE, DSP, WKUP, MDM */
-static struct clkdm_dep mpu_2430_wkdeps[] = {
- { .clkdm_name = "core_l3_clkdm" },
- { .clkdm_name = "core_l4_clkdm" },
- { .clkdm_name = "dsp_clkdm" },
- { .clkdm_name = "wkup_clkdm" },
- { .clkdm_name = "mdm_clkdm" },
- { NULL },
-};
-
-/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
-static struct clkdm_dep mdm_2430_wkdeps[] = {
- { .clkdm_name = "core_l3_clkdm" },
- { .clkdm_name = "core_l4_clkdm" },
- { .clkdm_name = "mpu_clkdm" },
- { .clkdm_name = "wkup_clkdm" },
- { NULL },
-};
-
-/*
- * 2430-only clockdomains
- */
-
-static struct clockdomain mpu_2430_clkdm = {
- .name = "mpu_clkdm",
- .pwrdm = { .name = "mpu_pwrdm" },
- .flags = CLKDM_CAN_HWSUP_SWSUP,
- .wkdep_srcs = mpu_2430_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
-};
-
-/* Another case of bit name collisions between several registers: EN_MDM */
-static struct clockdomain mdm_clkdm = {
- .name = "mdm_clkdm",
- .pwrdm = { .name = "mdm_pwrdm" },
- .flags = CLKDM_CAN_HWSUP_SWSUP,
- .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
- .wkdep_srcs = mdm_2430_wkdeps,
- .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
-};
-
-static struct clockdomain dsp_2430_clkdm = {
- .name = "dsp_clkdm",
- .pwrdm = { .name = "dsp_pwrdm" },
- .flags = CLKDM_CAN_HWSUP_SWSUP,
- .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
- .wkdep_srcs = dsp_24xx_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
-};
-
-static struct clockdomain gfx_2430_clkdm = {
- .name = "gfx_clkdm",
- .pwrdm = { .name = "gfx_pwrdm" },
- .flags = CLKDM_CAN_HWSUP_SWSUP,
- .wkdep_srcs = gfx_24xx_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
-};
-
-/*
- * XXX add usecounting for clkdm dependencies, otherwise the presence
- * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
- * could cause trouble
- */
-static struct clockdomain core_l3_2430_clkdm = {
- .name = "core_l3_clkdm",
- .pwrdm = { .name = "core_pwrdm" },
- .flags = CLKDM_CAN_HWSUP,
- .dep_bit = OMAP24XX_EN_CORE_SHIFT,
- .wkdep_srcs = core_2430_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
-};
-
-/*
- * XXX add usecounting for clkdm dependencies, otherwise the presence
- * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
- * could cause trouble
- */
-static struct clockdomain core_l4_2430_clkdm = {
- .name = "core_l4_clkdm",
- .pwrdm = { .name = "core_pwrdm" },
- .flags = CLKDM_CAN_HWSUP,
- .dep_bit = OMAP24XX_EN_CORE_SHIFT,
- .wkdep_srcs = core_2430_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
-};
-
-static struct clockdomain dss_2430_clkdm = {
- .name = "dss_clkdm",
- .pwrdm = { .name = "core_pwrdm" },
- .flags = CLKDM_CAN_HWSUP,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
-};
-
-static struct clockdomain *clockdomains_omap243x[] __initdata = {
- &wkup_common_clkdm,
- &mpu_2430_clkdm,
- &mdm_clkdm,
- &dsp_2430_clkdm,
- &gfx_2430_clkdm,
- &core_l3_2430_clkdm,
- &core_l4_2430_clkdm,
- &dss_2430_clkdm,
- NULL,
-};
-
-void __init omap243x_clockdomains_init(void)
-{
- if (!cpu_is_omap243x())
- return;
-
- clkdm_register_platform_funcs(&omap2_clkdm_operations);
- clkdm_register_clkdms(clockdomains_omap243x);
- clkdm_complete_init();
-}
-
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 220c22f5e0f5..4d20c2720660 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -8,7 +8,7 @@
* Paul Walmsley, Jouni Högander
*
* This file contains clockdomains and clockdomain wakeup/sleep
- * dependencies for the OMAP2/3 chips. Some notes:
+ * dependencies for the OMAP3 chips. Some notes:
*
* A useful validation rule for struct clockdomain: Any clockdomain
* referenced by a wkdep_srcs or sleepdep_srcs array must have a
@@ -16,8 +16,6 @@
* software-controllable dependencies. Non-software-controllable
* dependencies do exist, but they are not encoded below (yet).
*
- * 24xx does not support programmable sleep dependencies (SLEEPDEP)
- *
* The overly-specific dep_bit names are due to a bit name collision
* with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
* value are the same for all powerdomains: 2
@@ -39,10 +37,8 @@
#include "clockdomain.h"
#include "prm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
-#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
#include "cm-regbits-44xx.h"
-#include "prm-regbits-24xx.h"
#include "prm-regbits-34xx.h"
/*
@@ -54,29 +50,8 @@
/* Wakeup dependency source arrays */
-/* 2xxx-specific possible dependencies */
-
-/* 2xxx PM_WKDEP_GFX: CORE, MPU, WKUP */
-struct clkdm_dep gfx_24xx_wkdeps[] = {
- { .clkdm_name = "core_l3_clkdm" },
- { .clkdm_name = "core_l4_clkdm" },
- { .clkdm_name = "mpu_clkdm" },
- { .clkdm_name = "wkup_clkdm" },
- { NULL },
-};
-
-/* 2xxx PM_WKDEP_DSP: CORE, MPU, WKUP */
-struct clkdm_dep dsp_24xx_wkdeps[] = {
- { .clkdm_name = "core_l3_clkdm" },
- { .clkdm_name = "core_l4_clkdm" },
- { .clkdm_name = "mpu_clkdm" },
- { .clkdm_name = "wkup_clkdm" },
- { NULL },
-};
-
-
/*
- * OMAP2/3-common clockdomains
+ * OMAP3-common clockdomains
*
* Even though the 2420 has a single PRCM module from the
* interconnect's perspective, internally it does appear to have
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
deleted file mode 100644
index 59c14dbb6f87..000000000000
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
-#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
-
-/*
- * OMAP24XX Clock Management register bits
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
- *
- * Written by Paul Walmsley
- */
-
-#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
-#define OMAP24XX_EN_DSS1_MASK (1 << 0)
-#define OMAP24XX_ST_MAILBOXES_SHIFT 30
-#define OMAP24XX_ST_HDQ_SHIFT 23
-#define OMAP2420_ST_I2C2_SHIFT 20
-#define OMAP2430_ST_I2CHS1_SHIFT 19
-#define OMAP2420_ST_I2C1_SHIFT 19
-#define OMAP2430_ST_I2CHS2_SHIFT 20
-#define OMAP24XX_ST_MCBSP2_SHIFT 16
-#define OMAP24XX_ST_MCBSP1_SHIFT 15
-#define OMAP2430_ST_MCBSP5_SHIFT 5
-#define OMAP2430_ST_MCBSP4_SHIFT 4
-#define OMAP2430_ST_MCBSP3_SHIFT 3
-#define OMAP24XX_ST_AES_SHIFT 3
-#define OMAP24XX_ST_RNG_SHIFT 2
-#define OMAP24XX_ST_SHA_SHIFT 1
-#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
-#define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
-#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
-#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
-#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
-#define OMAP24XX_ST_MPU_WDT_SHIFT 3
-#define OMAP24XX_ST_32KSYNC_SHIFT 1
-#define OMAP24XX_EN_54M_PLL_SHIFT 6
-#define OMAP24XX_EN_96M_PLL_SHIFT 2
-#define OMAP24XX_ST_54M_APLL_SHIFT 9
-#define OMAP24XX_ST_96M_APLL_SHIFT 8
-#define OMAP24XX_AUTO_54M_MASK (0x3 << 6)
-#define OMAP24XX_AUTO_96M_MASK (0x3 << 2)
-#define OMAP24XX_AUTO_DPLL_SHIFT 0
-#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
-#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0)
-#define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
-#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
-#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
-#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
-#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
-#endif
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
deleted file mode 100644
index 1c6d69f4bf49..000000000000
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ /dev/null
@@ -1,302 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * OMAP2xxx CM module functions
- *
- * Copyright (C) 2009 Nokia Corporation
- * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
- * Paul Walmsley
- * Rajendra Nayak <rnayak@ti.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include "prm2xxx.h"
-#include "cm.h"
-#include "cm2xxx.h"
-#include "cm-regbits-24xx.h"
-#include "clockdomain.h"
-
-/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
-#define DPLL_AUTOIDLE_DISABLE 0x0
-#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
-
-/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
-#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0
-#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
-
-/* CM_IDLEST_PLL bit value offset for APLLs (OMAP2xxx only) */
-#define EN_APLL_LOCKED 3
-
-static const u8 omap2xxx_cm_idlest_offs[] = {
- CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
-};
-
-/*
- *
- */
-
-static void _write_clktrctrl(u8 c, s16 module, u32 mask)
-{
- u32 v;
-
- v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
- v &= ~mask;
- v |= c << __ffs(mask);
- omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
-}
-
-static bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
-{
- u32 v;
-
- v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
- v &= mask;
- v >>= __ffs(mask);
-
- return (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
-}
-
-static void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
-{
- _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
-}
-
-static void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
-{
- _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
-}
-
-/*
- * DPLL autoidle control
- */
-
-static void _omap2xxx_set_dpll_autoidle(u8 m)
-{
- u32 v;
-
- v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
- v &= ~OMAP24XX_AUTO_DPLL_MASK;
- v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
- omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
-}
-
-void omap2xxx_cm_set_dpll_disable_autoidle(void)
-{
- _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
-}
-
-void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
-{
- _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
-}
-
-/**
- * omap2xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
- * @idlest_reg: CM_IDLEST* virtual address
- * @prcm_inst: pointer to an s16 to return the PRCM instance offset
- * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
- *
- * XXX This function is only needed until absolute register addresses are
- * removed from the OMAP struct clk records.
- */
-static int omap2xxx_cm_split_idlest_reg(struct clk_omap_reg *idlest_reg,
- s16 *prcm_inst,
- u8 *idlest_reg_id)
-{
- unsigned long offs;
- u8 idlest_offs;
- int i;
-
- idlest_offs = idlest_reg->offset & 0xff;
- for (i = 0; i < ARRAY_SIZE(omap2xxx_cm_idlest_offs); i++) {
- if (idlest_offs == omap2xxx_cm_idlest_offs[i]) {
- *idlest_reg_id = i + 1;
- break;
- }
- }
-
- if (i == ARRAY_SIZE(omap2xxx_cm_idlest_offs))
- return -EINVAL;
-
- offs = idlest_reg->offset;
- offs &= 0xff00;
- *prcm_inst = offs;
-
- return 0;
-}
-
-/*
- *
- */
-
-/**
- * omap2xxx_cm_wait_module_ready - wait for a module to leave idle or standby
- * @part: PRCM partition, ignored for OMAP2
- * @prcm_mod: PRCM module offset
- * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
- * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
- *
- * Wait for the PRCM to indicate that the module identified by
- * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon
- * success or -EBUSY if the module doesn't enable in time.
- */
-static int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
- u8 idlest_shift)
-{
- int ena = 0, i = 0;
- u8 cm_idlest_reg;
- u32 mask;
-
- if (!idlest_id || (idlest_id > ARRAY_SIZE(omap2xxx_cm_idlest_offs)))
- return -EINVAL;
-
- cm_idlest_reg = omap2xxx_cm_idlest_offs[idlest_id - 1];
-
- mask = 1 << idlest_shift;
- ena = mask;
-
- omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
- mask) == ena), MAX_MODULE_READY_TIME, i);
-
- return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
-}
-
-/* Clockdomain low-level functions */
-
-static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm)
-{
- omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
- clkdm->clktrctrl_mask);
-}
-
-static void omap2xxx_clkdm_deny_idle(struct clockdomain *clkdm)
-{
- omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
- clkdm->clktrctrl_mask);
-}
-
-static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
-{
- bool hwsup = false;
-
- if (!clkdm->clktrctrl_mask)
- return 0;
-
- hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
- clkdm->clktrctrl_mask);
- if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
- omap2xxx_clkdm_wakeup(clkdm);
-
- return 0;
-}
-
-static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm)
-{
- bool hwsup = false;
-
- if (!clkdm->clktrctrl_mask)
- return 0;
-
- hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
- clkdm->clktrctrl_mask);
-
- if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
- omap2xxx_clkdm_sleep(clkdm);
-
- return 0;
-}
-
-struct clkdm_ops omap2_clkdm_operations = {
- .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
- .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
- .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
- .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
- .clkdm_sleep = omap2xxx_clkdm_sleep,
- .clkdm_wakeup = omap2xxx_clkdm_wakeup,
- .clkdm_allow_idle = omap2xxx_clkdm_allow_idle,
- .clkdm_deny_idle = omap2xxx_clkdm_deny_idle,
- .clkdm_clk_enable = omap2xxx_clkdm_clk_enable,
- .clkdm_clk_disable = omap2xxx_clkdm_clk_disable,
-};
-
-int omap2xxx_cm_fclks_active(void)
-{
- u32 f1, f2;
-
- f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
- f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
-
- return (f1 | f2) ? 1 : 0;
-}
-
-int omap2xxx_cm_mpu_retention_allowed(void)
-{
- u32 l;
-
- /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
- l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
- if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
- OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
- OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
- return 0;
- /* Check for UART3. */
- l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
- if (l & OMAP24XX_EN_UART3_MASK)
- return 0;
-
- return 1;
-}
-
-u32 omap2xxx_cm_get_core_clk_src(void)
-{
- u32 v;
-
- v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
- v &= OMAP24XX_CORE_CLK_SRC_MASK;
-
- return v;
-}
-
-u32 omap2xxx_cm_get_core_pll_config(void)
-{
- return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-}
-
-void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
-{
- u32 tmp;
-
- omap2_cm_write_mod_reg(mpu, MPU_MOD, CM_CLKSEL);
- omap2_cm_write_mod_reg(dsp, OMAP24XX_DSP_MOD, CM_CLKSEL);
- omap2_cm_write_mod_reg(gfx, GFX_MOD, CM_CLKSEL);
- tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) &
- OMAP24XX_CLKSEL_DSS2_MASK;
- omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1);
- if (mdm)
- omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL);
-}
-
-/*
- *
- */
-
-static const struct cm_ll_data omap2xxx_cm_ll_data = {
- .split_idlest_reg = &omap2xxx_cm_split_idlest_reg,
- .wait_module_ready = &omap2xxx_cm_wait_module_ready,
-};
-
-int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data)
-{
- return cm_register(&omap2xxx_cm_ll_data);
-}
-
-static void __exit omap2xxx_cm_exit(void)
-{
- cm_unregister(&omap2xxx_cm_ll_data);
-}
-__exitcall(omap2xxx_cm_exit);
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
deleted file mode 100644
index 7cbeff15ffb0..000000000000
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * OMAP2xxx Clock Management (CM) register definitions
- *
- * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
- * Paul Walmsley
- *
- * The CM hardware modules on the OMAP2/3 are quite similar to each
- * other. The CM modules/instances on OMAP4 are quite different, so
- * they are handled in a separate file.
- */
-#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_H
-#define __ARCH_ASM_MACH_OMAP2_CM2XXX_H
-
-#include "prcm-common.h"
-#include "cm2xxx_3xxx.h"
-
-#define OMAP2420_CM_REGADDR(module, reg) \
- OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
-#define OMAP2430_CM_REGADDR(module, reg) \
- OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
-
-/*
- * Module specific CM register offsets from CM_BASE + domain offset
- * Use cm_{read,write}_mod_reg() with these registers.
- * These register offsets generally appear in more than one PRCM submodule.
- */
-
-/* OMAP2-specific register offsets */
-
-#define OMAP24XX_CM_FCLKEN2 0x0004
-#define OMAP24XX_CM_ICLKEN4 0x001c
-#define OMAP24XX_CM_AUTOIDLE4 0x003c
-#define OMAP24XX_CM_IDLEST4 0x002c
-
-/* CM_IDLEST bit field values to indicate deasserted IdleReq */
-
-#define OMAP24XX_CM_IDLEST_VAL 0
-
-
-/* Clock management domain register get/set */
-
-#ifndef __ASSEMBLER__
-
-extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
-extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
-
-extern int omap2xxx_cm_fclks_active(void);
-extern int omap2xxx_cm_mpu_retention_allowed(void);
-extern u32 omap2xxx_cm_get_core_clk_src(void);
-extern u32 omap2xxx_cm_get_core_pll_config(void);
-extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
- u32 mdm);
-
-int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data);
-
-#endif
-
-#endif
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 87f2c2d2d754..fc16cd1fd2d5 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -15,7 +15,6 @@
#include <linux/of.h>
#include <linux/of_address.h>
-#include "cm2xxx.h"
#include "cm3xxx.h"
#include "cm33xx.h"
#include "cm44xx.h"
@@ -230,14 +229,6 @@ static struct omap_prcm_init_data cm2_data __initdata = {
};
#endif
-#ifdef CONFIG_ARCH_OMAP2
-static struct omap_prcm_init_data omap2_prcm_data __initdata = {
- .index = TI_CLKM_CM,
- .init = omap2xxx_cm_init,
- .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
-};
-#endif
-
#ifdef CONFIG_ARCH_OMAP3
static struct omap_prcm_init_data omap3_cm_data __initdata = {
.index = TI_CLKM_CM,
@@ -269,9 +260,6 @@ static struct omap_prcm_init_data am4_prcm_data __initdata = {
#endif
static const struct of_device_id omap_cm_dt_match_table[] __initconst = {
-#ifdef CONFIG_ARCH_OMAP2
- { .compatible = "ti,omap2-prcm", .data = &omap2_prcm_data },
-#endif
#ifdef CONFIG_ARCH_OMAP3
{ .compatible = "ti,omap3-cm", .data = &omap3_cm_data },
#endif
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
deleted file mode 100644
index 69694af71475..000000000000
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __OMAP_COMMON_BOARD_DEVICES__
-#define __OMAP_COMMON_BOARD_DEVICES__
-
-#include <linux/mfd/menelaus.h>
-
-void *n8x0_legacy_init(void);
-
-extern struct menelaus_platform_data n8x0_menelaus_platform_data;
-
-#endif /* __OMAP_COMMON_BOARD_DEVICES__ */
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 9d60799e9752..f8ed97044ade 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -102,8 +102,6 @@ static inline void omap5_realtime_timer_init(void)
}
#endif
-void omap2420_init_early(void);
-void omap2430_init_early(void);
void omap3430_init_early(void);
void omap3630_init_early(void);
void am33xx_init_early(void);
@@ -130,14 +128,6 @@ static inline void omap_soc_device_init(void)
}
#endif
-#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
-void omap2xxx_restart(enum reboot_mode mode, const char *cmd);
-#else
-static inline void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
-{
-}
-#endif
-
#ifdef CONFIG_SOC_AM33XX
void am33xx_restart(enum reboot_mode mode, const char *cmd);
#else
@@ -183,8 +173,6 @@ static inline void omap_barrier_reserve_memblock(void)
/* This gets called from mach-omap2/io.c, do not call this */
void __init omap2_set_globals_tap(u32 class, void __iomem *tap);
-void __init omap242x_map_io(void);
-void __init omap243x_map_io(void);
void __init omap3_map_io(void);
void __init am33xx_map_io(void);
void __init omap4_map_io(void);
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 7e7440533bf9..3ab1c6e6dde6 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -19,19 +19,11 @@
#include "am33xx.h"
#ifndef __ASSEMBLY__
-#define OMAP242X_CTRL_REGADDR(reg) \
- OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
-#define OMAP243X_CTRL_REGADDR(reg) \
- OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
#define OMAP343X_CTRL_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
#define AM33XX_CTRL_REGADDR(reg) \
AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
#else
-#define OMAP242X_CTRL_REGADDR(reg) \
- OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
-#define OMAP243X_CTRL_REGADDR(reg) \
- OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
#define OMAP343X_CTRL_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
#define AM33XX_CTRL_REGADDR(reg) \
@@ -74,52 +66,6 @@
#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
-/* 242x-only CONTROL_GENERAL register offsets */
-#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
-#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
-
-/* 243x-only CONTROL_GENERAL register offsets */
-/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
-#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
-#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
-#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
-#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
-#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
-#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
-
-/* 24xx-only CONTROL_GENERAL register offsets */
-#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
-#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
-#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
-#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
-#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
-#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
-#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
-#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
-#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
-#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
-#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
-#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
-#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
-#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
-#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
-#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
-#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
-#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
-#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
-#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
-#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
-#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
-#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
-#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
-#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
-#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
-#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
-#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
-#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
-#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
-#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
-
#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
/* 34xx-only CONTROL_GENERAL register offsets */
@@ -311,14 +257,12 @@
*/
/* CONTROL_DEVCONF0 bits */
#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
-#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
#define OMAP2_MCBSP1_FSR_MASK (1 << 4)
#define OMAP2_MCBSP1_CLKR_MASK (1 << 3)
#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
/* CONTROL_DEVCONF1 bits */
-#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index dbec3bb9fbf4..addc14898bd5 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -124,9 +124,7 @@ static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
static enum omapdss_version __init omap_display_get_version(void)
{
- if (cpu_is_omap24xx())
- return OMAPDSS_VER_OMAP24xx;
- else if (cpu_is_omap3630())
+ if (cpu_is_omap3630())
return OMAPDSS_VER_OMAP3630;
else if (cpu_is_omap34xx()) {
if (soc_is_am35xx()) {
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 830cd4e7eb44..3a6b7b4620ca 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -82,39 +82,6 @@ static unsigned configure_dma_errata(void)
{
unsigned errata = 0;
- /*
- * Errata applicable for OMAP2430ES1.0 and all omap2420
- *
- * I.
- * Erratum ID: Not Available
- * Inter Frame DMA buffering issue DMA will wrongly
- * buffer elements if packing and bursting is enabled. This might
- * result in data gets stalled in FIFO at the end of the block.
- * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
- * guarantee no data will stay in the DMA FIFO in case inter frame
- * buffering occurs
- *
- * II.
- * Erratum ID: Not Available
- * DMA may hang when several channels are used in parallel
- * In the following configuration, DMA channel hanging can occur:
- * a. Channel i, hardware synchronized, is enabled
- * b. Another channel (Channel x), software synchronized, is enabled.
- * c. Channel i is disabled before end of transfer
- * d. Channel i is reenabled.
- * e. Steps 1 to 4 are repeated a certain number of times.
- * f. A third channel (Channel y), software synchronized, is enabled.
- * Channel x and Channel y may hang immediately after step 'f'.
- * Workaround:
- * For any channel used - make sure NextLCH_ID is set to the value j.
- */
- if (cpu_is_omap2420() || (cpu_is_omap2430() &&
- (omap_type() == OMAP2430_REV_ES1_0))) {
-
- SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
- SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
- }
-
/*
* Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
* after a transaction error.
@@ -162,16 +129,6 @@ static unsigned configure_dma_errata(void)
return errata;
}
-static const struct dma_slave_map omap24xx_sdma_dt_map[] = {
- /* external DMA requests when tusb6010 is used */
- { "musb-hdrc.1.auto", "dmareq0", SDMA_FILTER_PARAM(2) },
- { "musb-hdrc.1.auto", "dmareq1", SDMA_FILTER_PARAM(3) },
- { "musb-hdrc.1.auto", "dmareq2", SDMA_FILTER_PARAM(14) }, /* OMAP2420 only */
- { "musb-hdrc.1.auto", "dmareq3", SDMA_FILTER_PARAM(15) }, /* OMAP2420 only */
- { "musb-hdrc.1.auto", "dmareq4", SDMA_FILTER_PARAM(16) }, /* OMAP2420 only */
- { "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */
-};
-
static struct omap_dma_dev_attr dma_attr = {
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
IS_CSSA_32 | IS_CDSA_32,
@@ -188,15 +145,7 @@ struct omap_system_dma_plat_info dma_plat_info = {
static int __init omap2_system_dma_init(void)
{
dma_plat_info.errata = configure_dma_errata();
-
- if (soc_is_omap24xx()) {
- /* DMA slave map for drivers not yet converted to DT */
- dma_plat_info.slave_map = omap24xx_sdma_dt_map;
- dma_plat_info.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
- }
-
- if (!soc_is_omap242x())
- dma_attr.dev_caps |= IS_RW_PRIORITY;
+ dma_attr.dev_caps |= IS_RW_PRIORITY;
if (soc_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
dma_attr.dev_caps |= HS_CHANNELS_RESERVED;
diff --git a/arch/arm/mach-omap2/fb.c b/arch/arm/mach-omap2/fb.c
index 0f8c8efe3ae8..9a425c36f996 100644
--- a/arch/arm/mach-omap2/fb.c
+++ b/arch/arm/mach-omap2/fb.c
@@ -27,15 +27,6 @@
* The first memory resource is the register region for VRFB,
* the rest are VRFB virtual memory areas for each VRFB context.
*/
-
-static const struct resource omap2_vrfb_resources[] = {
- DEFINE_RES_MEM_NAMED(0x68008000u, 0x40, "vrfb-regs"),
- DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
- DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
- DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
- DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
-};
-
static const struct resource omap3_vrfb_resources[] = {
DEFINE_RES_MEM_NAMED(0x6C000180u, 0xc0, "vrfb-regs"),
DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
@@ -58,10 +49,7 @@ int __init omap_init_vrfb(void)
const struct resource *res;
unsigned int num_res;
- if (cpu_is_omap24xx()) {
- res = omap2_vrfb_resources;
- num_res = ARRAY_SIZE(omap2_vrfb_resources);
- } else if (cpu_is_omap34xx()) {
+ if (cpu_is_omap34xx()) {
res = omap3_vrfb_resources;
num_res = ARRAY_SIZE(omap3_vrfb_resources);
} else {
diff --git a/arch/arm/mach-omap2/gpmc.h b/arch/arm/mach-omap2/gpmc.h
deleted file mode 100644
index e060f1b5c27d..000000000000
--- a/arch/arm/mach-omap2/gpmc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * General-Purpose Memory Controller for OMAP2
- *
- * Copyright (C) 2005-2006 Nokia Corporation
- *
- * Do not include this file in any new code, this will get removed
- * once omap3 boots in device tree only mode.
- */
-#include <linux/omap-gpmc.h>
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index 3b4b9514f4fa..d956c70f8899 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -39,7 +39,7 @@ int omap_i2c_reset(struct omap_hwmod *oh)
u16 i2c_con;
int c = 0;
- if (soc_is_omap24xx() || soc_is_omap34xx() || soc_is_am35xx())
+ if (soc_is_omap34xx() || soc_is_am35xx())
i2c_con = OMAP2_I2C_CON_OFFSET;
else
i2c_con = OMAP4_I2C_CON_OFFSET;
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index cf2bfb447ee2..3e731dd21311 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -55,9 +55,7 @@ int omap_type(void)
if (val < OMAP2_DEVICETYPE_MASK)
return val;
- if (soc_is_omap24xx()) {
- val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
- } else if (soc_is_ti81xx()) {
+ if (soc_is_ti81xx()) {
val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
} else if (soc_is_am33xx() || soc_is_am43xx()) {
val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
@@ -99,22 +97,6 @@ EXPORT_SYMBOL(omap_type);
#define read_tap_reg(reg) readl_relaxed(tap_base + (reg))
-struct omap_id {
- u16 hawkeye; /* Silicon type (Hawkeye id) */
- u8 dev; /* Device type from production_id reg */
- u32 type; /* Combined type id copied to omap_revision */
-};
-
-/* Register values to detect the OMAP version */
-static struct omap_id omap_ids[] __initdata = {
- { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
- { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
- { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
- { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
- { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
- { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
-};
-
static void __iomem *tap_base;
static u16 tap_prod_id;
@@ -145,62 +127,6 @@ static int __init omap_feed_randpool(void)
}
omap_device_initcall(omap_feed_randpool);
-void __init omap2xxx_check_revision(void)
-{
- int i, j;
- u32 idcode, prod_id;
- u16 hawkeye;
- u8 dev_type, rev;
- struct omap_die_id odi;
-
- idcode = read_tap_reg(OMAP_TAP_IDCODE);
- prod_id = read_tap_reg(tap_prod_id);
- hawkeye = (idcode >> 12) & 0xffff;
- rev = (idcode >> 28) & 0x0f;
- dev_type = (prod_id >> 16) & 0x0f;
- omap_get_die_id(&odi);
-
- pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
- idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
- pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
- pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
- odi.id_1, (odi.id_1 >> 28) & 0xf);
- pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
- pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
- pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
- prod_id, dev_type);
-
- /* Check hawkeye ids */
- for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
- if (hawkeye == omap_ids[i].hawkeye)
- break;
- }
-
- if (i == ARRAY_SIZE(omap_ids)) {
- printk(KERN_ERR "Unknown OMAP CPU id\n");
- return;
- }
-
- for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
- if (dev_type == omap_ids[j].dev)
- break;
- }
-
- if (j == ARRAY_SIZE(omap_ids)) {
- pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
- omap_ids[i].type >> 16);
- j = i;
- }
-
- sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
- sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
-
- pr_info("%s", soc_name);
- if ((omap_rev() >> 8) & 0x0f)
- pr_cont("%s", soc_rev);
- pr_cont("\n");
-}
-
#define OMAP3_SHOW_FEATURE(feat) \
if (omap3_has_ ##feat()) \
n += scnprintf(buf + n, sizeof(buf) - n, #feat " ");
@@ -750,9 +676,7 @@ static const char * const omap_types[] = {
static const char * __init omap_get_family(void)
{
- if (soc_is_omap24xx())
- return kasprintf(GFP_KERNEL, "OMAP2");
- else if (soc_is_omap34xx())
+ if (soc_is_omap34xx())
return kasprintf(GFP_KERNEL, "OMAP3");
else if (soc_is_omap44xx())
return kasprintf(GFP_KERNEL, "OMAP4");
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 14ec3f78000b..1c945be5e7cc 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -35,7 +35,6 @@
#include "sdrc.h"
#include "control.h"
#include "sram.h"
-#include "cm2xxx.h"
#include "cm3xxx.h"
#include "cm33xx.h"
#include "cm44xx.h"
@@ -43,11 +42,9 @@
#include "cm.h"
#include "prcm_mpu44xx.h"
#include "prminst44xx.h"
-#include "prm2xxx.h"
#include "prm3xxx.h"
#include "prm33xx.h"
#include "prm44xx.h"
-#include "opp2xxx.h"
#include "omap-secure.h"
/*
@@ -61,76 +58,6 @@ static int (*omap_clk_soc_init)(void);
* default mapping provided here.
*/
-#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
-static struct map_desc omap24xx_io_desc[] __initdata = {
- {
- .virtual = L3_24XX_VIRT,
- .pfn = __phys_to_pfn(L3_24XX_PHYS),
- .length = L3_24XX_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = L4_24XX_VIRT,
- .pfn = __phys_to_pfn(L4_24XX_PHYS),
- .length = L4_24XX_SIZE,
- .type = MT_DEVICE
- },
-};
-
-#ifdef CONFIG_SOC_OMAP2420
-static struct map_desc omap242x_io_desc[] __initdata = {
- {
- .virtual = DSP_MEM_2420_VIRT,
- .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
- .length = DSP_MEM_2420_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = DSP_IPI_2420_VIRT,
- .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
- .length = DSP_IPI_2420_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = DSP_MMU_2420_VIRT,
- .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
- .length = DSP_MMU_2420_SIZE,
- .type = MT_DEVICE
- },
-};
-
-#endif
-
-#ifdef CONFIG_SOC_OMAP2430
-static struct map_desc omap243x_io_desc[] __initdata = {
- {
- .virtual = L4_WK_243X_VIRT,
- .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
- .length = L4_WK_243X_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = OMAP243X_GPMC_VIRT,
- .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
- .length = OMAP243X_GPMC_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = OMAP243X_SDRC_VIRT,
- .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
- .length = OMAP243X_SDRC_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = OMAP243X_SMS_VIRT,
- .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
- .length = OMAP243X_SMS_SIZE,
- .type = MT_DEVICE
- },
-};
-#endif
-#endif
-
#ifdef CONFIG_ARCH_OMAP3
static struct map_desc omap34xx_io_desc[] __initdata = {
{
@@ -305,22 +232,6 @@ static struct map_desc dra7xx_io_desc[] __initdata = {
};
#endif
-#ifdef CONFIG_SOC_OMAP2420
-void __init omap242x_map_io(void)
-{
- iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
- iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
-}
-#endif
-
-#ifdef CONFIG_SOC_OMAP2430
-void __init omap243x_map_io(void)
-{
- iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
- iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
-}
-#endif
-
#ifdef CONFIG_ARCH_OMAP3
void __init omap3_map_io(void)
{
@@ -365,6 +276,8 @@ void __init dra7xx_map_io(void)
omap_barriers_init();
}
#endif
+
+#ifdef CONFIG_ARCH_OMAP3
/*
* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
*
@@ -399,7 +312,6 @@ static int __init _omap2_init_reprogram_sdrc(void)
return v;
}
-#ifdef CONFIG_OMAP_HWMOD
static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
{
return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
@@ -412,55 +324,11 @@ static void __init __maybe_unused omap_hwmod_init_postsetup(void)
/* Set the default postsetup state for all hwmods */
omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
}
-#else
-static inline void omap_hwmod_init_postsetup(void)
-{
-}
-#endif
-
-#ifdef CONFIG_SOC_OMAP2420
-void __init omap2420_init_early(void)
-{
- omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
- omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
- OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
- omap2_control_base_init();
- omap2xxx_check_revision();
- omap2_prcm_base_init();
- omap2xxx_voltagedomains_init();
- omap242x_powerdomains_init();
- omap242x_clockdomains_init();
- omap2420_hwmod_init();
- omap_hwmod_init_postsetup();
- omap_clk_soc_init = omap2420_dt_clk_init;
- rate_table = omap2420_rate_table;
-}
-#endif
-
-#ifdef CONFIG_SOC_OMAP2430
-void __init omap2430_init_early(void)
-{
- omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
- omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
- OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
- omap2_control_base_init();
- omap2xxx_check_revision();
- omap2_prcm_base_init();
- omap2xxx_voltagedomains_init();
- omap243x_powerdomains_init();
- omap243x_clockdomains_init();
- omap2430_hwmod_init();
- omap_hwmod_init_postsetup();
- omap_clk_soc_init = omap2430_dt_clk_init;
- rate_table = omap2430_rate_table;
-}
-#endif
/*
* Currently only board-omap3beagle.c should call this because of the
* same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
*/
-#ifdef CONFIG_ARCH_OMAP3
static void __init omap3_init_early(void)
{
omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
@@ -661,16 +529,18 @@ void __init dra7xx_init_late(void)
#endif
+#ifdef CONFIG_ARCH_OMAP3
void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
omap_sram_init();
- if (cpu_is_omap24xx() || omap3_has_sdrc()) {
+ if (omap3_has_sdrc()) {
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
_omap2_init_reprogram_sdrc();
}
}
+#endif
int __init omap_clk_init(void)
{
diff --git a/arch/arm/mach-omap2/iomap.h b/arch/arm/mach-omap2/iomap.h
index 6191d244438a..403444bb6924 100644
--- a/arch/arm/mach-omap2/iomap.h
+++ b/arch/arm/mach-omap2/iomap.h
@@ -48,52 +48,6 @@
#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
-/*
- * ----------------------------------------------------------------------------
- * Omap2 specific IO mapping
- * ----------------------------------------------------------------------------
- */
-
-/* We map both L3 and L4 on OMAP2 */
-#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
-#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
-#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
-#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
-#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
-#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
-
-#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
-#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
-#define L4_WK_243X_SIZE SZ_1M
-#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
-#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
- /* 0x6e000000 --> 0xfe000000 */
-#define OMAP243X_GPMC_SIZE SZ_1M
-#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
- /* 0x6D000000 --> 0xfd000000 */
-#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
-#define OMAP243X_SDRC_SIZE SZ_1M
-#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
- /* 0x6c000000 --> 0xfc000000 */
-#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
-#define OMAP243X_SMS_SIZE SZ_1M
-
-/* 2420 IVA */
-#define DSP_MEM_2420_PHYS OMAP2420_DSP_MEM_BASE
- /* 0x58000000 --> 0xfc100000 */
-#define DSP_MEM_2420_VIRT 0xfc100000
-#define DSP_MEM_2420_SIZE 0x28000
-#define DSP_IPI_2420_PHYS OMAP2420_DSP_IPI_BASE
- /* 0x59000000 --> 0xfc128000 */
-#define DSP_IPI_2420_VIRT 0xfc128000
-#define DSP_IPI_2420_SIZE SZ_4K
-#define DSP_MMU_2420_PHYS OMAP2420_DSP_MMU_BASE
- /* 0x5a000000 --> 0xfc129000 */
-#define DSP_MMU_2420_VIRT 0xfc129000
-#define DSP_MMU_2420_SIZE SZ_4K
-
-/* 2430 IVA2.1 - currently unmapped */
-
/*
* ----------------------------------------------------------------------------
* Omap3 specific IO mapping
diff --git a/arch/arm/mach-omap2/l3_2xxx.h b/arch/arm/mach-omap2/l3_2xxx.h
deleted file mode 100644
index 6297c62428ac..000000000000
--- a/arch/arm/mach-omap2/l3_2xxx.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
- * Sumit Semwal
- */
-#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
-#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
-
-/* L3 CONNIDs */
-/* Display Sub system (DSS) */
-#define OMAP2_L3_CORE_FW_CONNID_DSS 8
-
-#endif
diff --git a/arch/arm/mach-omap2/l4_2xxx.h b/arch/arm/mach-omap2/l4_2xxx.h
deleted file mode 100644
index 418e1072d730..000000000000
--- a/arch/arm/mach-omap2/l4_2xxx.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
- * Sumit Semwal
- */
-#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
-#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
-
-/* L4 CORE */
-/* Display Sub system (DSS) */
-#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION 28
-#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION 29
-#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION 30
-#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION 31
-#define OMAP2420_L4_CORE_FW_DSS_TA_REGION 32
-
-#endif
diff --git a/arch/arm/mach-omap2/mmc.h b/arch/arm/mach-omap2/mmc.h
deleted file mode 100644
index b5533e93cb63..000000000000
--- a/arch/arm/mach-omap2/mmc.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#define OMAP24XX_NR_MMC 2
-#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE
-#define OMAP2_MMC1_BASE 0x4809c000
-
-#define OMAP4_MMC_REG_OFFSET 0x100
-
-struct omap_hwmod;
-
-#ifdef CONFIG_SOC_OMAP2420
-int omap_msdi_reset(struct omap_hwmod *oh);
-#else
-static inline int omap_msdi_reset(struct omap_hwmod *oh)
-{
- return 0;
-}
-#endif
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
deleted file mode 100644
index 552b2fa4e4f1..000000000000
--- a/arch/arm/mach-omap2/msdi.c
+++ /dev/null
@@ -1,75 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * MSDI IP block reset
- *
- * Copyright (C) 2012 Texas Instruments, Inc.
- * Paul Walmsley
- *
- * XXX What about pad muxing?
- */
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-
-#include "prm.h"
-#include "common.h"
-#include "control.h"
-#include "omap_hwmod.h"
-#include "omap_device.h"
-#include "mmc.h"
-
-/*
- * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register
- * from the IP block's base address
- */
-#define MSDI_CON_OFFSET 0x0c
-
-/* Register bitfields in the CON register */
-#define MSDI_CON_POW_MASK BIT(11)
-#define MSDI_CON_CLKD_MASK (0x3f << 0)
-#define MSDI_CON_CLKD_SHIFT 0
-
-/* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
-#define MSDI_TARGET_RESET_CLKD 0x3ff
-
-/**
- * omap_msdi_reset - reset the MSDI IP block
- * @oh: struct omap_hwmod *
- *
- * The MSDI IP block on OMAP2420 has to have both the POW and CLKD
- * fields set inside its CON register for a reset to complete
- * successfully. This is not documented in the TRM. For CLKD, we use
- * the value that results in the lowest possible clock rate, to attempt
- * to avoid disturbing any cards.
- */
-int omap_msdi_reset(struct omap_hwmod *oh)
-{
- u16 v = 0;
- int c = 0;
-
- /* Write to the SOFTRESET bit */
- omap_hwmod_softreset(oh);
-
- /* Enable the MSDI core and internal clock */
- v |= MSDI_CON_POW_MASK;
- v |= MSDI_TARGET_RESET_CLKD << MSDI_CON_CLKD_SHIFT;
- omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
-
- /* Poll on RESETDONE bit */
- omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
- & SYSS_RESETDONE_MASK),
- MAX_MODULE_SOFTRESET_WAIT, c);
-
- if (c == MAX_MODULE_SOFTRESET_WAIT)
- pr_warn("%s: %s: softreset failed (waited %d usec)\n",
- __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
- else
- pr_debug("%s: %s: softreset in %d usec\n", __func__,
- oh->name, c);
-
- /* Disable the MSDI internal clock */
- v &= ~MSDI_CON_CLKD_MASK;
- omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
-
- return 0;
-}
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
deleted file mode 100644
index fdcc75c97d70..000000000000
--- a/arch/arm/mach-omap2/omap2-restart.c
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * omap2-restart.c - code common to all OMAP2xxx machines.
- *
- * Copyright (C) 2012 Texas Instruments
- * Paul Walmsley
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include "soc.h"
-#include "common.h"
-#include "prm.h"
-
-/*
- * reset_virt_prcm_set_ck, reset_sys_ck: pointers to the virt_prcm_set
- * clock and the sys_ck. Used during the reset process
- */
-static struct clk *reset_virt_prcm_set_ck, *reset_sys_ck;
-
-/* Reboot handling */
-
-/**
- * omap2xxx_restart - Set DPLL to bypass mode for reboot to work
- *
- * Set the DPLL to bypass so that reboot completes successfully. No
- * return value.
- */
-void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
-{
- u32 rate;
-
- rate = clk_get_rate(reset_sys_ck);
- clk_set_rate(reset_virt_prcm_set_ck, rate);
-
- /* XXX Should save the cmd argument for use after the reboot */
-
- omap_prm_reset_system();
-}
-
-/**
- * omap2xxx_common_look_up_clks_for_reset - look up clocks needed for restart
- *
- * Some clocks need to be looked up in advance for the SoC restart
- * operation to work - see omap2xxx_restart(). Returns -EINVAL upon
- * error or 0 upon success.
- */
-static int __init omap2xxx_common_look_up_clks_for_reset(void)
-{
- reset_virt_prcm_set_ck = clk_get(NULL, "virt_prcm_set");
- if (IS_ERR(reset_virt_prcm_set_ck))
- return -EINVAL;
-
- reset_sys_ck = clk_get(NULL, "sys_ck");
- if (IS_ERR(reset_sys_ck))
- return -EINVAL;
-
- return 0;
-}
-omap_postcore_initcall(omap2xxx_common_look_up_clks_for_reset);
diff --git a/arch/arm/mach-omap2/omap24xx.h b/arch/arm/mach-omap2/omap24xx.h
deleted file mode 100644
index d9ecc0578292..000000000000
--- a/arch/arm/mach-omap2/omap24xx.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * This file contains the processor specific definitions
- * of the TI OMAP24XX.
- *
- * Copyright (C) 2007 Texas Instruments.
- * Copyright (C) 2007 Nokia Corporation.
- */
-
-#ifndef __ASM_ARCH_OMAP2_H
-#define __ASM_ARCH_OMAP2_H
-
-/*
- * Please place only base defines here and put the rest in device
- * specific headers. Note also that some of these defines are needed
- * for omap1 to compile without adding ifdefs.
- */
-
-#define L4_24XX_BASE 0x48000000
-#define L4_WK_243X_BASE 0x49000000
-#define L3_24XX_BASE 0x68000000
-
-/* interrupt controller */
-#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
-#define OMAP24XX_IVA_INTC_BASE 0x40000000
-
-#define OMAP242X_CTRL_BASE L4_24XX_BASE
-#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
-#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
-#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
-#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
-#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
-#define OMAP2420_SMS_BASE 0x68008000
-#define OMAP2420_GPMC_BASE 0x6800a000
-
-#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
-#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
-#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000)
-#define OMAP2430_PRM_BASE OMAP2430_CM_BASE
-
-#define OMAP243X_SMS_BASE 0x6C000000
-#define OMAP243X_SDRC_BASE 0x6D000000
-#define OMAP243X_GPMC_BASE 0x6E000000
-#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000)
-#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE
-#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000)
-
-/* DSP SS */
-#define OMAP2420_DSP_BASE 0x58000000
-#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0)
-#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000)
-#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000)
-
-#define OMAP243X_DSP_BASE 0x5C000000
-#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0)
-#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000)
-
-/* Mailbox */
-#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000)
-
-/* Camera */
-#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000)
-
-/* Security */
-#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000)
-#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000)
-#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000)
-#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
-#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
-#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
-
-#endif /* __ASM_ARCH_OMAP2_H */
-
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 03cd523dff87..c918399ea735 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -153,9 +153,7 @@
#include "common.h"
#include "clockdomain.h"
#include "hdq1w.h"
-#include "mmc.h"
#include "powerdomain.h"
-#include "cm2xxx.h"
#include "cm3xxx.h"
#include "cm33xx.h"
#include "prm.h"
@@ -3469,10 +3467,6 @@ static int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh,
return -ENOMEM;
}
-static const struct omap_hwmod_reset omap24xx_reset_quirks[] = {
- { .match = "msdi", .len = 4, .reset = omap_msdi_reset, },
-};
-
static const struct omap_hwmod_reset omap_reset_quirks[] = {
{ .match = "dss_core", .len = 8, .reset = omap_dss_reset, },
{ .match = "hdq1w", .len = 5, .reset = omap_hdq1w_reset, },
@@ -3503,11 +3497,6 @@ static void
omap_hwmod_init_reset_quirks(struct device *dev, struct omap_hwmod *oh,
const struct ti_sysc_module_data *data)
{
- if (soc_is_omap24xx())
- omap_hwmod_init_reset_quirk(dev, oh, data,
- omap24xx_reset_quirks,
- ARRAY_SIZE(omap24xx_reset_quirks));
-
omap_hwmod_init_reset_quirk(dev, oh, data, omap_reset_quirks,
ARRAY_SIZE(omap_reset_quirks));
}
@@ -3914,12 +3903,7 @@ int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
*/
void __init omap_hwmod_init(void)
{
- if (cpu_is_omap24xx()) {
- soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready;
- soc_ops.assert_hardreset = _omap2_assert_hardreset;
- soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
- soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
- } else if (cpu_is_omap34xx()) {
+ if (cpu_is_omap34xx()) {
soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready;
soc_ops.assert_hardreset = _omap2_assert_hardreset;
soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index dcab7a01c10e..b60cd09c1997 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -663,8 +663,6 @@ omap_hwmod_for_each_by_class(const char *classname,
* Chip variant-specific hwmod init routines - XXX should be converted
* to use initcalls once the initial boot ordering is straightened out
*/
-extern int omap2420_hwmod_init(void);
-extern int omap2430_hwmod_init(void);
extern int omap3xxx_hwmod_init(void);
extern int dm814x_hwmod_init(void);
extern int dm816x_hwmod_init(void);
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
deleted file mode 100644
index dbd9dc9f0962..000000000000
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ /dev/null
@@ -1,402 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
- *
- * Copyright (C) 2009-2011 Nokia Corporation
- * Copyright (C) 2012 Texas Instruments, Inc.
- * Paul Walmsley
- *
- * XXX handle crossbar/shared link difference for L3?
- * XXX these should be marked initdata for multi-OMAP kernels
- */
-
-#include <linux/platform_data/i2c-omap.h>
-
-#include "omap_hwmod.h"
-#include "l3_2xxx.h"
-#include "l4_2xxx.h"
-
-#include "omap_hwmod_common_data.h"
-
-#include "cm-regbits-24xx.h"
-#include "prm-regbits-24xx.h"
-#include "i2c.h"
-#include "mmc.h"
-#include "wd_timer.h"
-
-/*
- * OMAP2420 hardware module integration data
- *
- * All of the data in this section should be autogeneratable from the
- * TI hardware database or other technical documentation. Data that
- * is driver-specific or driver-kernel integration-specific belongs
- * elsewhere.
- */
-
-/*
- * IP blocks
- */
-
-/* IVA1 (IVA1) */
-static struct omap_hwmod_class iva1_hwmod_class = {
- .name = "iva1",
-};
-
-static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
- { .name = "iva", .rst_shift = 8 },
-};
-
-static struct omap_hwmod omap2420_iva_hwmod = {
- .name = "iva",
- .class = &iva1_hwmod_class,
- .clkdm_name = "iva1_clkdm",
- .rst_lines = omap2420_iva_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
- .main_clk = "iva1_ifck",
-};
-
-/* DSP */
-static struct omap_hwmod_class dsp_hwmod_class = {
- .name = "dsp",
-};
-
-static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
- { .name = "logic", .rst_shift = 0 },
- { .name = "mmu", .rst_shift = 1 },
-};
-
-static struct omap_hwmod omap2420_dsp_hwmod = {
- .name = "dsp",
- .class = &dsp_hwmod_class,
- .clkdm_name = "dsp_clkdm",
- .rst_lines = omap2420_dsp_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
- .main_clk = "dsp_fck",
-};
-
-/* I2C common */
-static struct omap_hwmod_class_sysconfig i2c_sysc = {
- .rev_offs = 0x00,
- .sysc_offs = 0x20,
- .syss_offs = 0x10,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class i2c_class = {
- .name = "i2c",
- .sysc = &i2c_sysc,
- .reset = &omap_i2c_reset,
-};
-
-/* I2C1 */
-static struct omap_hwmod omap2420_i2c1_hwmod = {
- .name = "i2c1",
- .main_clk = "i2c1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
- },
- },
- .class = &i2c_class,
- /*
- * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
- * while a transfer is active seems to cause the I2C block to
- * timeout. Why? Good question."
- */
- .flags = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
-};
-
-/* I2C2 */
-static struct omap_hwmod omap2420_i2c2_hwmod = {
- .name = "i2c2",
- .main_clk = "i2c2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
- },
- },
- .class = &i2c_class,
- .flags = HWMOD_16BIT_REG,
-};
-
-/* mailbox */
-static struct omap_hwmod omap2420_mailbox_hwmod = {
- .name = "mailbox",
- .class = &omap2xxx_mailbox_hwmod_class,
- .main_clk = "mailboxes_ick",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
- },
- },
-};
-
-/*
- * 'mcbsp' class
- * multi channel buffered serial port controller
- */
-
-static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
- .name = "mcbsp",
-};
-
-static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
- { .role = "pad_fck", .clk = "mcbsp_clks" },
- { .role = "prcm_fck", .clk = "func_96m_ck" },
-};
-
-/* mcbsp1 */
-static struct omap_hwmod omap2420_mcbsp1_hwmod = {
- .name = "mcbsp1",
- .class = &omap2420_mcbsp_hwmod_class,
- .main_clk = "mcbsp1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
- },
- },
- .opt_clks = mcbsp_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
-};
-
-/* mcbsp2 */
-static struct omap_hwmod omap2420_mcbsp2_hwmod = {
- .name = "mcbsp2",
- .class = &omap2420_mcbsp_hwmod_class,
- .main_clk = "mcbsp2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
- },
- },
- .opt_clks = mcbsp_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
-};
-
-static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
- .rev_offs = 0x3c,
- .sysc_offs = 0x64,
- .syss_offs = 0x68,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
- .name = "msdi",
- .sysc = &omap2420_msdi_sysc,
- .reset = &omap_msdi_reset,
-};
-
-/* msdi1 */
-static struct omap_hwmod omap2420_msdi1_hwmod = {
- .name = "msdi1",
- .class = &omap2420_msdi_hwmod_class,
- .main_clk = "mmc_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
- },
- },
- .flags = HWMOD_16BIT_REG,
-};
-
-/* HDQ1W/1-wire */
-static struct omap_hwmod omap2420_hdq1w_hwmod = {
- .name = "hdq1w",
- .main_clk = "hdq_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
- },
- },
- .class = &omap2_hdq1w_class,
-};
-
-/*
- * interfaces
- */
-
-/* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2420_i2c1_hwmod,
- .clk = "i2c1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2420_i2c2_hwmod,
- .clk = "i2c2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* IVA <- L3 interface */
-static struct omap_hwmod_ocp_if omap2420_l3__iva = {
- .master = &omap2xxx_l3_main_hwmod,
- .slave = &omap2420_iva_hwmod,
- .clk = "core_l3_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* DSP <- L3 interface */
-static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
- .master = &omap2xxx_l3_main_hwmod,
- .slave = &omap2420_dsp_hwmod,
- .clk = "dsp_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_wd_timer2_hwmod,
- .clk = "mpu_wdt_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio1 */
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_gpio1_hwmod,
- .clk = "gpios_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio2 */
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_gpio2_hwmod,
- .clk = "gpios_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio3 */
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_gpio3_hwmod,
- .clk = "gpios_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio4 */
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_gpio4_hwmod,
- .clk = "gpios_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mailbox */
-static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2420_mailbox_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mcbsp1 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2420_mcbsp1_hwmod,
- .clk = "mcbsp1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mcbsp2 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2420_mcbsp2_hwmod,
- .clk = "mcbsp2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> msdi1 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2420_msdi1_hwmod,
- .clk = "mmc_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> hdq1w interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2420_hdq1w_hwmod,
- .clk = "hdq_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
- .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
-};
-
-static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
- .master = &omap2xxx_l3_main_hwmod,
- .slave = &omap2xxx_gpmc_hwmod,
- .clk = "core_l3_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
- &omap2xxx_l3_main__l4_core,
- &omap2xxx_mpu__l3_main,
- &omap2xxx_dss__l3,
- &omap2xxx_l4_core__mcspi1,
- &omap2xxx_l4_core__mcspi2,
- &omap2xxx_l4_core__l4_wkup,
- &omap2_l4_core__uart1,
- &omap2_l4_core__uart2,
- &omap2_l4_core__uart3,
- &omap2420_l4_core__i2c1,
- &omap2420_l4_core__i2c2,
- &omap2420_l3__iva,
- &omap2420_l3__dsp,
- &omap2xxx_l4_core__timer3,
- &omap2xxx_l4_core__timer4,
- &omap2xxx_l4_core__timer5,
- &omap2xxx_l4_core__timer6,
- &omap2xxx_l4_core__timer7,
- &omap2xxx_l4_core__timer8,
- &omap2xxx_l4_core__timer9,
- &omap2xxx_l4_core__timer10,
- &omap2xxx_l4_core__timer11,
- &omap2xxx_l4_core__timer12,
- &omap2420_l4_wkup__wd_timer2,
- &omap2xxx_l4_core__dss,
- &omap2xxx_l4_core__dss_dispc,
- &omap2xxx_l4_core__dss_rfbi,
- &omap2xxx_l4_core__dss_venc,
- &omap2420_l4_wkup__gpio1,
- &omap2420_l4_wkup__gpio2,
- &omap2420_l4_wkup__gpio3,
- &omap2420_l4_wkup__gpio4,
- &omap2420_l4_core__mailbox,
- &omap2420_l4_core__mcbsp1,
- &omap2420_l4_core__mcbsp2,
- &omap2420_l4_core__msdi1,
- &omap2xxx_l4_core__rng,
- &omap2xxx_l4_core__sham,
- &omap2xxx_l4_core__aes,
- &omap2420_l4_core__hdq1w,
- &omap2420_l3__gpmc,
- NULL,
-};
-
-int __init omap2420_hwmod_init(void)
-{
- omap_hwmod_init();
- return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
-}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
deleted file mode 100644
index c93200801b34..000000000000
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ /dev/null
@@ -1,606 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
- *
- * Copyright (C) 2009-2011 Nokia Corporation
- * Copyright (C) 2012 Texas Instruments, Inc.
- * Paul Walmsley
- *
- * XXX handle crossbar/shared link difference for L3?
- * XXX these should be marked initdata for multi-OMAP kernels
- */
-
-#include <linux/platform_data/i2c-omap.h>
-#include <linux/platform_data/hsmmc-omap.h>
-
-#include "omap_hwmod.h"
-#include "l3_2xxx.h"
-
-#include "soc.h"
-#include "omap_hwmod_common_data.h"
-#include "prm-regbits-24xx.h"
-#include "cm-regbits-24xx.h"
-#include "i2c.h"
-#include "wd_timer.h"
-
-/*
- * OMAP2430 hardware module integration data
- *
- * All of the data in this section should be autogeneratable from the
- * TI hardware database or other technical documentation. Data that
- * is driver-specific or driver-kernel integration-specific belongs
- * elsewhere.
- */
-
-/*
- * IP blocks
- */
-
-/* IVA2 (IVA2) */
-static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
- { .name = "logic", .rst_shift = 0 },
- { .name = "mmu", .rst_shift = 1 },
-};
-
-static struct omap_hwmod omap2430_iva_hwmod = {
- .name = "iva",
- .class = &iva_hwmod_class,
- .clkdm_name = "dsp_clkdm",
- .rst_lines = omap2430_iva_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets),
- .main_clk = "dsp_fck",
-};
-
-/* I2C common */
-static struct omap_hwmod_class_sysconfig i2c_sysc = {
- .rev_offs = 0x00,
- .sysc_offs = 0x20,
- .syss_offs = 0x10,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class i2c_class = {
- .name = "i2c",
- .sysc = &i2c_sysc,
- .reset = &omap_i2c_reset,
-};
-
-/* I2C1 */
-static struct omap_hwmod omap2430_i2c1_hwmod = {
- .name = "i2c1",
- .flags = HWMOD_16BIT_REG,
- .main_clk = "i2chs1_fck",
- .prcm = {
- .omap2 = {
- /*
- * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
- * I2CHS IP's do not follow the usual pattern.
- * prcm_reg_id alone cannot be used to program
- * the iclk and fclk. Needs to be handled using
- * additional flags when clk handling is moved
- * to hwmod framework.
- */
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
- },
- },
- .class = &i2c_class,
-};
-
-/* I2C2 */
-static struct omap_hwmod omap2430_i2c2_hwmod = {
- .name = "i2c2",
- .flags = HWMOD_16BIT_REG,
- .main_clk = "i2chs2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
- },
- },
- .class = &i2c_class,
-};
-
-/* gpio5 */
-static struct omap_hwmod omap2430_gpio5_hwmod = {
- .name = "gpio5",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "gpio5_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
- },
- },
- .class = &omap2xxx_gpio_hwmod_class,
-};
-
-/* mailbox */
-static struct omap_hwmod omap2430_mailbox_hwmod = {
- .name = "mailbox",
- .class = &omap2xxx_mailbox_hwmod_class,
- .main_clk = "mailboxes_ick",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
- },
- },
-};
-
-/* mcspi3 */
-static struct omap_hwmod omap2430_mcspi3_hwmod = {
- .name = "mcspi3",
- .main_clk = "mcspi3_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
- },
- },
- .class = &omap2xxx_mcspi_class,
-};
-
-/* usbhsotg */
-static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
- .rev_offs = 0x0400,
- .sysc_offs = 0x0404,
- .syss_offs = 0x0408,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class usbotg_class = {
- .name = "usbotg",
- .sysc = &omap2430_usbhsotg_sysc,
-};
-
-/* usb_otg_hs */
-static struct omap_hwmod omap2430_usbhsotg_hwmod = {
- .name = "usb_otg_hs",
- .main_clk = "usbhs_ick",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
- },
- },
- .class = &usbotg_class,
- /*
- * Erratum ID: i479 idle_req / idle_ack mechanism potentially
- * broken when autoidle is enabled
- * workaround is to disable the autoidle bit at module level.
- */
- .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
- | HWMOD_SWSUP_MSTANDBY,
-};
-
-/*
- * 'mcbsp' class
- * multi channel buffered serial port controller
- */
-
-static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
- .rev_offs = 0x007C,
- .sysc_offs = 0x008C,
- .sysc_flags = (SYSC_HAS_SOFTRESET),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
- .name = "mcbsp",
- .sysc = &omap2430_mcbsp_sysc,
-};
-
-static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
- { .role = "pad_fck", .clk = "mcbsp_clks" },
- { .role = "prcm_fck", .clk = "func_96m_ck" },
-};
-
-/* mcbsp1 */
-static struct omap_hwmod omap2430_mcbsp1_hwmod = {
- .name = "mcbsp1",
- .class = &omap2430_mcbsp_hwmod_class,
- .main_clk = "mcbsp1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
- },
- },
- .opt_clks = mcbsp_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
-};
-
-/* mcbsp2 */
-static struct omap_hwmod omap2430_mcbsp2_hwmod = {
- .name = "mcbsp2",
- .class = &omap2430_mcbsp_hwmod_class,
- .main_clk = "mcbsp2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
- },
- },
- .opt_clks = mcbsp_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
-};
-
-/* mcbsp3 */
-static struct omap_hwmod omap2430_mcbsp3_hwmod = {
- .name = "mcbsp3",
- .class = &omap2430_mcbsp_hwmod_class,
- .main_clk = "mcbsp3_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
- },
- },
- .opt_clks = mcbsp_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
-};
-
-/* mcbsp4 */
-static struct omap_hwmod omap2430_mcbsp4_hwmod = {
- .name = "mcbsp4",
- .class = &omap2430_mcbsp_hwmod_class,
- .main_clk = "mcbsp4_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
- },
- },
- .opt_clks = mcbsp_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
-};
-
-/* mcbsp5 */
-static struct omap_hwmod omap2430_mcbsp5_hwmod = {
- .name = "mcbsp5",
- .class = &omap2430_mcbsp_hwmod_class,
- .main_clk = "mcbsp5_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
- },
- },
- .opt_clks = mcbsp_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
-};
-
-/* MMC/SD/SDIO common */
-static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
- .rev_offs = 0x1fc,
- .sysc_offs = 0x10,
- .syss_offs = 0x14,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_mmc_class = {
- .name = "mmc",
- .sysc = &omap2430_mmc_sysc,
-};
-
-/* MMC/SD/SDIO1 */
-static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
- { .role = "dbck", .clk = "mmchsdb1_fck" },
-};
-
-static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
- .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
-};
-
-static struct omap_hwmod omap2430_mmc1_hwmod = {
- .name = "mmc1",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .opt_clks = omap2430_mmc1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
- .main_clk = "mmchs1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
- },
- },
- .dev_attr = &mmc1_dev_attr,
- .class = &omap2430_mmc_class,
-};
-
-/* MMC/SD/SDIO2 */
-static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
- { .role = "dbck", .clk = "mmchsdb2_fck" },
-};
-
-static struct omap_hwmod omap2430_mmc2_hwmod = {
- .name = "mmc2",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .opt_clks = omap2430_mmc2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
- .main_clk = "mmchs2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
- },
- },
- .class = &omap2430_mmc_class,
-};
-
-/* HDQ1W/1-wire */
-static struct omap_hwmod omap2430_hdq1w_hwmod = {
- .name = "hdq1w",
- .main_clk = "hdq_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
- },
- },
- .class = &omap2_hdq1w_class,
-};
-
-/*
- * interfaces
- */
-
-/* L3 -> L4_CORE interface */
-/* l3_core -> usbhsotg interface */
-static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
- .master = &omap2430_usbhsotg_hwmod,
- .slave = &omap2xxx_l3_main_hwmod,
- .clk = "core_l3_ck",
- .user = OCP_USER_MPU,
-};
-
-/* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_i2c1_hwmod,
- .clk = "i2c1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_i2c2_hwmod,
- .clk = "i2c2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core ->usbhsotg interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_usbhsotg_hwmod,
- .clk = "usb_l4_ick",
- .user = OCP_USER_MPU,
-};
-
-/* L4 CORE -> MMC1 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mmc1_hwmod,
- .clk = "mmchs1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> MMC2 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mmc2_hwmod,
- .clk = "mmchs2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> mcspi3 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mcspi3_hwmod,
- .clk = "mcspi3_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* IVA2 <- L3 interface */
-static struct omap_hwmod_ocp_if omap2430_l3__iva = {
- .master = &omap2xxx_l3_main_hwmod,
- .slave = &omap2430_iva_hwmod,
- .clk = "core_l3_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_wd_timer2_hwmod,
- .clk = "mpu_wdt_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio1 */
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_gpio1_hwmod,
- .clk = "gpios_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio2 */
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_gpio2_hwmod,
- .clk = "gpios_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio3 */
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_gpio3_hwmod,
- .clk = "gpios_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio4 */
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_gpio4_hwmod,
- .clk = "gpios_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> gpio5 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_gpio5_hwmod,
- .clk = "gpio5_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mailbox */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mailbox_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mcbsp1 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mcbsp1_hwmod,
- .clk = "mcbsp1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mcbsp2 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mcbsp2_hwmod,
- .clk = "mcbsp2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mcbsp3 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mcbsp3_hwmod,
- .clk = "mcbsp3_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mcbsp4 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mcbsp4_hwmod,
- .clk = "mcbsp4_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mcbsp5 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mcbsp5_hwmod,
- .clk = "mcbsp5_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> hdq1w */
-static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_hdq1w_hwmod,
- .clk = "hdq_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
- .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
-};
-
-static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
- .master = &omap2xxx_l3_main_hwmod,
- .slave = &omap2xxx_gpmc_hwmod,
- .clk = "core_l3_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
- &omap2xxx_l3_main__l4_core,
- &omap2xxx_mpu__l3_main,
- &omap2xxx_dss__l3,
- &omap2430_usbhsotg__l3,
- &omap2430_l4_core__i2c1,
- &omap2430_l4_core__i2c2,
- &omap2xxx_l4_core__l4_wkup,
- &omap2_l4_core__uart1,
- &omap2_l4_core__uart2,
- &omap2_l4_core__uart3,
- &omap2430_l4_core__usbhsotg,
- &omap2430_l4_core__mmc1,
- &omap2430_l4_core__mmc2,
- &omap2xxx_l4_core__mcspi1,
- &omap2xxx_l4_core__mcspi2,
- &omap2430_l4_core__mcspi3,
- &omap2430_l3__iva,
- &omap2xxx_l4_core__timer3,
- &omap2xxx_l4_core__timer4,
- &omap2xxx_l4_core__timer5,
- &omap2xxx_l4_core__timer6,
- &omap2xxx_l4_core__timer7,
- &omap2xxx_l4_core__timer8,
- &omap2xxx_l4_core__timer9,
- &omap2xxx_l4_core__timer10,
- &omap2xxx_l4_core__timer11,
- &omap2xxx_l4_core__timer12,
- &omap2430_l4_wkup__wd_timer2,
- &omap2xxx_l4_core__dss,
- &omap2xxx_l4_core__dss_dispc,
- &omap2xxx_l4_core__dss_rfbi,
- &omap2xxx_l4_core__dss_venc,
- &omap2430_l4_wkup__gpio1,
- &omap2430_l4_wkup__gpio2,
- &omap2430_l4_wkup__gpio3,
- &omap2430_l4_wkup__gpio4,
- &omap2430_l4_core__gpio5,
- &omap2430_l4_core__mailbox,
- &omap2430_l4_core__mcbsp1,
- &omap2430_l4_core__mcbsp2,
- &omap2430_l4_core__mcbsp3,
- &omap2430_l4_core__mcbsp4,
- &omap2430_l4_core__mcbsp5,
- &omap2430_l4_core__hdq1w,
- &omap2xxx_l4_core__rng,
- &omap2xxx_l4_core__sham,
- &omap2xxx_l4_core__aes,
- &omap2430_l3__gpmc,
- NULL,
-};
-
-int __init omap2430_hwmod_init(void)
-{
- omap_hwmod_init();
- return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
-}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
deleted file mode 100644
index 761d34914ed9..000000000000
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ /dev/null
@@ -1,256 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
- *
- * Copyright (C) 2009-2011 Nokia Corporation
- * Paul Walmsley
- *
- * XXX handle crossbar/shared link difference for L3?
- * XXX these should be marked initdata for multi-OMAP kernels
- */
-#include <linux/sizes.h>
-
-#include "omap_hwmod.h"
-#include "l3_2xxx.h"
-#include "l4_2xxx.h"
-
-#include "omap_hwmod_common_data.h"
-
-/*
- * Common interconnect data
- */
-
-/* L3 -> L4_CORE interface */
-struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
- .master = &omap2xxx_l3_main_hwmod,
- .slave = &omap2xxx_l4_core_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* MPU -> L3 interface */
-struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
- .master = &omap2xxx_mpu_hwmod,
- .slave = &omap2xxx_l3_main_hwmod,
- .user = OCP_USER_MPU,
-};
-
-/* DSS -> l3 */
-struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
- .master = &omap2xxx_dss_core_hwmod,
- .slave = &omap2xxx_l3_main_hwmod,
- .fw = {
- .omap2 = {
- .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
- .flags = OMAP_FIREWALL_L3,
- },
- },
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4_CORE -> L4_WKUP interface */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_l4_wkup_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> UART1 interface */
-struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_uart1_hwmod,
- .clk = "uart1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> UART2 interface */
-struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_uart2_hwmod,
- .clk = "uart2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 PER -> UART3 interface */
-struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_uart3_hwmod,
- .clk = "uart3_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> mcspi1 interface */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_mcspi1_hwmod,
- .clk = "mcspi1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> mcspi2 interface */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_mcspi2_hwmod,
- .clk = "mcspi2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer3 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer3_hwmod,
- .clk = "gpt3_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer4 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer4_hwmod,
- .clk = "gpt4_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer5 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer5_hwmod,
- .clk = "gpt5_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer6 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer6_hwmod,
- .clk = "gpt6_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer7 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer7_hwmod,
- .clk = "gpt7_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer8 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer8_hwmod,
- .clk = "gpt8_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer9 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer9_hwmod,
- .clk = "gpt9_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer10 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer10_hwmod,
- .clk = "gpt10_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer11 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer11_hwmod,
- .clk = "gpt11_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer12 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer12_hwmod,
- .clk = "gpt12_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dss */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_dss_core_hwmod,
- .clk = "dss_ick",
- .fw = {
- .omap2 = {
- .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
- .flags = OMAP_FIREWALL_L4,
- },
- },
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dss_dispc */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_dss_dispc_hwmod,
- .clk = "dss_ick",
- .fw = {
- .omap2 = {
- .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
- .flags = OMAP_FIREWALL_L4,
- },
- },
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dss_rfbi */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_dss_rfbi_hwmod,
- .clk = "dss_ick",
- .fw = {
- .omap2 = {
- .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
- .flags = OMAP_FIREWALL_L4,
- },
- },
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dss_venc */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_dss_venc_hwmod,
- .clk = "dss_ick",
- .fw = {
- .omap2 = {
- .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
- .flags = OMAP_FIREWALL_L4,
- },
- },
- .flags = OCPIF_SWSUP_IDLE,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> rng */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_rng_hwmod,
- .clk = "rng_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> sham interface */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_sham_hwmod,
- .clk = "sha_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> aes interface */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_aes_hwmod,
- .clk = "aes_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
deleted file mode 100644
index 4982e04ead53..000000000000
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ /dev/null
@@ -1,668 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
- *
- * Copyright (C) 2011 Nokia Corporation
- * Paul Walmsley
- */
-
-#include <linux/types.h>
-
-#include "omap_hwmod.h"
-#include "omap_hwmod_common_data.h"
-#include "cm-regbits-24xx.h"
-#include "prm-regbits-24xx.h"
-#include "wd_timer.h"
-
-/*
- * 'dispc' class
- * display controller
- */
-
-static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2_dispc_hwmod_class = {
- .name = "dispc",
- .sysc = &omap2_dispc_sysc,
-};
-
-/* OMAP2xxx Timer Common */
-static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
- .name = "timer",
- .sysc = &omap2xxx_timer_sysc,
-};
-
-/*
- * 'wd_timer' class
- * 32-bit watchdog upward counter that generates a pulse on the reset pin on
- * overflow condition
- */
-
-static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
- .name = "wd_timer",
- .sysc = &omap2xxx_wd_timer_sysc,
- .pre_shutdown = &omap2_wd_timer_disable,
- .reset = &omap2_wd_timer_reset,
-};
-
-/*
- * 'gpio' class
- * general purpose io module
- */
-static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
- .name = "gpio",
- .sysc = &omap2xxx_gpio_sysc,
-};
-
-/*
- * 'mailbox' class
- * mailbox module allowing communication between the on-chip processors
- * using a queued mailbox-interrupt mechanism.
- */
-
-static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
- .rev_offs = 0x000,
- .sysc_offs = 0x010,
- .syss_offs = 0x014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
- .name = "mailbox",
- .sysc = &omap2xxx_mailbox_sysc,
-};
-
-/*
- * 'mcspi' class
- * multichannel serial port interface (mcspi) / master/slave synchronous serial
- * bus
- */
-
-static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-struct omap_hwmod_class omap2xxx_mcspi_class = {
- .name = "mcspi",
- .sysc = &omap2xxx_mcspi_sysc,
-};
-
-/*
- * 'gpmc' class
- * general purpose memory controller
- */
-
-static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
- .name = "gpmc",
- .sysc = &omap2xxx_gpmc_sysc,
-};
-
-/*
- * IP blocks
- */
-
-/* L3 */
-struct omap_hwmod omap2xxx_l3_main_hwmod = {
- .name = "l3_main",
- .class = &l3_hwmod_class,
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* L4 CORE */
-struct omap_hwmod omap2xxx_l4_core_hwmod = {
- .name = "l4_core",
- .class = &l4_hwmod_class,
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* L4 WKUP */
-struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
- .name = "l4_wkup",
- .class = &l4_hwmod_class,
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* MPU */
-struct omap_hwmod omap2xxx_mpu_hwmod = {
- .name = "mpu",
- .class = &mpu_hwmod_class,
- .main_clk = "mpu_ck",
-};
-
-/* timer3 */
-struct omap_hwmod omap2xxx_timer3_hwmod = {
- .name = "timer3",
- .main_clk = "gpt3_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer4 */
-struct omap_hwmod omap2xxx_timer4_hwmod = {
- .name = "timer4",
- .main_clk = "gpt4_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer5 */
-struct omap_hwmod omap2xxx_timer5_hwmod = {
- .name = "timer5",
- .main_clk = "gpt5_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer6 */
-struct omap_hwmod omap2xxx_timer6_hwmod = {
- .name = "timer6",
- .main_clk = "gpt6_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer7 */
-struct omap_hwmod omap2xxx_timer7_hwmod = {
- .name = "timer7",
- .main_clk = "gpt7_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer8 */
-struct omap_hwmod omap2xxx_timer8_hwmod = {
- .name = "timer8",
- .main_clk = "gpt8_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer9 */
-struct omap_hwmod omap2xxx_timer9_hwmod = {
- .name = "timer9",
- .main_clk = "gpt9_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer10 */
-struct omap_hwmod omap2xxx_timer10_hwmod = {
- .name = "timer10",
- .main_clk = "gpt10_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer11 */
-struct omap_hwmod omap2xxx_timer11_hwmod = {
- .name = "timer11",
- .main_clk = "gpt11_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer12 */
-struct omap_hwmod omap2xxx_timer12_hwmod = {
- .name = "timer12",
- .main_clk = "gpt12_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* wd_timer2 */
-struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
- .name = "wd_timer2",
- .class = &omap2xxx_wd_timer_hwmod_class,
- .main_clk = "mpu_wdt_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
- },
- },
-};
-
-/* UART1 */
-
-struct omap_hwmod omap2xxx_uart1_hwmod = {
- .name = "uart1",
- .main_clk = "uart1_fck",
- .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
- },
- },
- .class = &omap2_uart_class,
-};
-
-/* UART2 */
-
-struct omap_hwmod omap2xxx_uart2_hwmod = {
- .name = "uart2",
- .main_clk = "uart2_fck",
- .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
- },
- },
- .class = &omap2_uart_class,
-};
-
-/* UART3 */
-
-struct omap_hwmod omap2xxx_uart3_hwmod = {
- .name = "uart3",
- .main_clk = "uart3_fck",
- .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
- },
- },
- .class = &omap2_uart_class,
-};
-
-/* dss */
-
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
- /*
- * The DSS HW needs all DSS clocks enabled during reset. The dss_core
- * driver does not use these clocks.
- */
- { .role = "tv_clk", .clk = "dss_54m_fck" },
- { .role = "sys_clk", .clk = "dss2_fck" },
-};
-
-struct omap_hwmod omap2xxx_dss_core_hwmod = {
- .name = "dss_core",
- .class = &omap2_dss_hwmod_class,
- .main_clk = "dss1_fck", /* instead of dss_fck */
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- },
- },
- .opt_clks = dss_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
- .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-};
-
-struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
- .name = "dss_dispc",
- .class = &omap2_dispc_hwmod_class,
- .main_clk = "dss1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- },
- },
- .flags = HWMOD_NO_IDLEST,
- .dev_attr = &omap2_3_dss_dispc_dev_attr,
-};
-
-static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
- { .role = "ick", .clk = "dss_ick" },
-};
-
-struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
- .name = "dss_rfbi",
- .class = &omap2_rfbi_hwmod_class,
- .main_clk = "dss1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- },
- },
- .opt_clks = dss_rfbi_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
- .flags = HWMOD_NO_IDLEST,
-};
-
-struct omap_hwmod omap2xxx_dss_venc_hwmod = {
- .name = "dss_venc",
- .class = &omap2_venc_hwmod_class,
- .main_clk = "dss_54m_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- },
- },
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* gpio1 */
-struct omap_hwmod omap2xxx_gpio1_hwmod = {
- .name = "gpio1",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "gpios_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
- },
- },
- .class = &omap2xxx_gpio_hwmod_class,
-};
-
-/* gpio2 */
-struct omap_hwmod omap2xxx_gpio2_hwmod = {
- .name = "gpio2",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "gpios_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
- },
- },
- .class = &omap2xxx_gpio_hwmod_class,
-};
-
-/* gpio3 */
-struct omap_hwmod omap2xxx_gpio3_hwmod = {
- .name = "gpio3",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "gpios_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
- },
- },
- .class = &omap2xxx_gpio_hwmod_class,
-};
-
-/* gpio4 */
-struct omap_hwmod omap2xxx_gpio4_hwmod = {
- .name = "gpio4",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "gpios_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
- },
- },
- .class = &omap2xxx_gpio_hwmod_class,
-};
-
-/* mcspi1 */
-struct omap_hwmod omap2xxx_mcspi1_hwmod = {
- .name = "mcspi1",
- .main_clk = "mcspi1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
- },
- },
- .class = &omap2xxx_mcspi_class,
-};
-
-/* mcspi2 */
-struct omap_hwmod omap2xxx_mcspi2_hwmod = {
- .name = "mcspi2",
- .main_clk = "mcspi2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
- },
- },
- .class = &omap2xxx_mcspi_class,
-};
-
-/* gpmc */
-struct omap_hwmod omap2xxx_gpmc_hwmod = {
- .name = "gpmc",
- .class = &omap2xxx_gpmc_hwmod_class,
- .main_clk = "gpmc_fck",
- /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
- .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- },
- },
-};
-
-/* RNG */
-
-static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
- .rev_offs = 0x3c,
- .sysc_offs = 0x40,
- .syss_offs = 0x44,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2_rng_hwmod_class = {
- .name = "rng",
- .sysc = &omap2_rng_sysc,
-};
-
-struct omap_hwmod omap2xxx_rng_hwmod = {
- .name = "rng",
- .main_clk = "l4_ck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 4,
- .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
- },
- },
- /*
- * XXX The first read from the SYSSTATUS register of the RNG
- * after the SYSCONFIG SOFTRESET bit is set triggers an
- * imprecise external abort. It's unclear why this happens.
- * Until this is analyzed, skip the IP block reset.
- */
- .flags = HWMOD_INIT_NO_RESET,
- .class = &omap2_rng_hwmod_class,
-};
-
-/* SHAM */
-
-static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
- .rev_offs = 0x5c,
- .sysc_offs = 0x60,
- .syss_offs = 0x64,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2xxx_sham_class = {
- .name = "sham",
- .sysc = &omap2_sham_sysc,
-};
-
-struct omap_hwmod omap2xxx_sham_hwmod = {
- .name = "sham",
- .main_clk = "l4_ck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 4,
- .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
- },
- },
- .class = &omap2xxx_sham_class,
-};
-
-/* AES */
-
-static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
- .rev_offs = 0x44,
- .sysc_offs = 0x48,
- .syss_offs = 0x4c,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2xxx_aes_class = {
- .name = "aes",
- .sysc = &omap2_aes_sysc,
-};
-
-struct omap_hwmod omap2xxx_aes_hwmod = {
- .name = "aes",
- .main_clk = "l4_ck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 4,
- .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
- },
- },
- .class = &omap2xxx_aes_class,
-};
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 69dddc53e1d8..8b270cb3f64b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -15,68 +15,6 @@
#include "common.h"
#include "display.h"
-/* Common IP block data across OMAP2xxx */
-extern struct omap_hwmod omap2xxx_l3_main_hwmod;
-extern struct omap_hwmod omap2xxx_l4_core_hwmod;
-extern struct omap_hwmod omap2xxx_l4_wkup_hwmod;
-extern struct omap_hwmod omap2xxx_mpu_hwmod;
-extern struct omap_hwmod omap2xxx_timer3_hwmod;
-extern struct omap_hwmod omap2xxx_timer4_hwmod;
-extern struct omap_hwmod omap2xxx_timer5_hwmod;
-extern struct omap_hwmod omap2xxx_timer6_hwmod;
-extern struct omap_hwmod omap2xxx_timer7_hwmod;
-extern struct omap_hwmod omap2xxx_timer8_hwmod;
-extern struct omap_hwmod omap2xxx_timer9_hwmod;
-extern struct omap_hwmod omap2xxx_timer10_hwmod;
-extern struct omap_hwmod omap2xxx_timer11_hwmod;
-extern struct omap_hwmod omap2xxx_timer12_hwmod;
-extern struct omap_hwmod omap2xxx_wd_timer2_hwmod;
-extern struct omap_hwmod omap2xxx_uart1_hwmod;
-extern struct omap_hwmod omap2xxx_uart2_hwmod;
-extern struct omap_hwmod omap2xxx_uart3_hwmod;
-extern struct omap_hwmod omap2xxx_dss_core_hwmod;
-extern struct omap_hwmod omap2xxx_dss_dispc_hwmod;
-extern struct omap_hwmod omap2xxx_dss_rfbi_hwmod;
-extern struct omap_hwmod omap2xxx_dss_venc_hwmod;
-extern struct omap_hwmod omap2xxx_gpio1_hwmod;
-extern struct omap_hwmod omap2xxx_gpio2_hwmod;
-extern struct omap_hwmod omap2xxx_gpio3_hwmod;
-extern struct omap_hwmod omap2xxx_gpio4_hwmod;
-extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
-extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
-extern struct omap_hwmod omap2xxx_gpmc_hwmod;
-extern struct omap_hwmod omap2xxx_rng_hwmod;
-extern struct omap_hwmod omap2xxx_sham_hwmod;
-extern struct omap_hwmod omap2xxx_aes_hwmod;
-
-/* Common interface data across OMAP2xxx */
-extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
-extern struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main;
-extern struct omap_hwmod_ocp_if omap2xxx_dss__l3;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup;
-extern struct omap_hwmod_ocp_if omap2_l4_core__uart1;
-extern struct omap_hwmod_ocp_if omap2_l4_core__uart2;
-extern struct omap_hwmod_ocp_if omap2_l4_core__uart3;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__sham;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__aes;
-
/* OMAP hwmod classes - forward declarations */
extern struct omap_hwmod_class l3_hwmod_class;
extern struct omap_hwmod_class l4_hwmod_class;
@@ -88,10 +26,6 @@ extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
extern struct omap_hwmod_class omap2_venc_hwmod_class;
extern struct omap_hwmod_class omap2_hdq1w_class;
-extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
-extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
-extern struct omap_hwmod_class omap2xxx_mcspi_class;
-
extern struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr;
#endif
diff --git a/arch/arm/mach-omap2/opp2420_data.c b/arch/arm/mach-omap2/opp2420_data.c
deleted file mode 100644
index 18a448f938ea..000000000000
--- a/arch/arm/mach-omap2/opp2420_data.c
+++ /dev/null
@@ -1,131 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * opp2420_data.c - old-style "OPP" table for OMAP2420
- *
- * Copyright (C) 2005-2009 Texas Instruments, Inc.
- * Copyright (C) 2004-2009 Nokia Corporation
- *
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
- * These configurations are characterized by voltage and speed for clocks.
- * The device is only validated for certain combinations. One way to express
- * these combinations is via the 'ratios' which the clocks operate with
- * respect to each other. These ratio sets are for a given voltage/DPLL
- * setting. All configurations can be described by a DPLL setting and a ratio.
- *
- * XXX Missing voltage data.
- * XXX Missing 19.2MHz sys_clk rate sets (needed for N800/N810)
- *
- * THe format described in this file is deprecated. Once a reasonable
- * OPP API exists, the data in this file should be converted to use it.
- *
- * This is technically part of the OMAP2xxx clock code.
- *
- * Considerable work is still needed to fully support dynamic frequency
- * changes on OMAP2xxx-series chips. Readers interested in such a
- * project are encouraged to review the Maemo Diablo RX-34 and RX-44
- * kernel source at:
- * http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/
- */
-
-#include <linux/kernel.h>
-
-#include "opp2xxx.h"
-#include "sdrc.h"
-#include "clock.h"
-
-/*
- * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
- * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
- * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- *
- * Filling in table based on H4 boards available. There are quite a
- * few more rate combinations which could be defined.
- *
- * When multiple values are defined the start up will try and choose
- * the fastest one. If a 'fast' value is defined, then automatically,
- * the /2 one should be included as it can be used. Generally having
- * more than one fast set does not make sense, as static timings need
- * to be changed to change the set. The exception is the bypass
- * setting which is available for low power bypass.
- *
- * Note: This table needs to be sorted, fastest to slowest.
- **/
-const struct prcm_config omap2420_rate_table[] = {
- /* PRCM I - FAST */
- {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
- RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
- RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
- RATE_IN_242X},
-
- /* PRCM II - FAST */
- {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
- RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
- RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
- RATE_IN_242X},
-
- {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
- RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
- RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
- RATE_IN_242X},
-
- /* PRCM III - FAST */
- {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
- RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
- RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
- RATE_IN_242X},
-
- {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
- RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
- RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
- RATE_IN_242X},
-
- /* PRCM II - SLOW */
- {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
- RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
- RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
- RATE_IN_242X},
-
- {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
- RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
- RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
- RATE_IN_242X},
-
- /* PRCM III - SLOW */
- {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
- RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
- RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
- RATE_IN_242X},
-
- {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
- RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
- RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
- RATE_IN_242X},
-
- /* PRCM-VII (boot-bypass) */
- {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
- RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
- RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
- RATE_IN_242X},
-
- /* PRCM-VII (boot-bypass) */
- {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
- RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
- RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
- RATE_IN_242X},
-
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-};
diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c
deleted file mode 100644
index ded8b566a23a..000000000000
--- a/arch/arm/mach-omap2/opp2430_data.c
+++ /dev/null
@@ -1,136 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * opp2430_data.c - old-style "OPP" table for OMAP2430
- *
- * Copyright (C) 2005-2009 Texas Instruments, Inc.
- * Copyright (C) 2004-2009 Nokia Corporation
- *
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
- * These configurations are characterized by voltage and speed for clocks.
- * The device is only validated for certain combinations. One way to express
- * these combinations is via the 'ratios' which the clocks operate with
- * respect to each other. These ratio sets are for a given voltage/DPLL
- * setting. All configurations can be described by a DPLL setting and a ratio.
- *
- * 2430 differs from 2420 in that there are no more phase synchronizers used.
- * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
- * 2430 (iva2.1, NOdsp, mdm)
- *
- * XXX Missing voltage data.
- * XXX Missing 19.2MHz sys_clk rate sets.
- *
- * THe format described in this file is deprecated. Once a reasonable
- * OPP API exists, the data in this file should be converted to use it.
- *
- * This is technically part of the OMAP2xxx clock code.
- */
-
-#include <linux/kernel.h>
-
-#include "opp2xxx.h"
-#include "sdrc.h"
-#include "clock.h"
-
-/*
- * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
- * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
- * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- *
- * Filling in table based on 2430-SDPs variants available. There are
- * quite a few more rate combinations which could be defined.
- *
- * When multiple values are defined the start up will try and choose
- * the fastest one. If a 'fast' value is defined, then automatically,
- * the /2 one should be included as it can be used. Generally having
- * more than one fast set does not make sense, as static timings need
- * to be changed to change the set. The exception is the bypass
- * setting which is available for low power bypass.
- *
- * Note: This table needs to be sorted, fastest to slowest.
- */
-const struct prcm_config omap2430_rate_table[] = {
- /* PRCM #4 - ratio2 (ES2.1) - FAST */
- {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
- R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
- R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_133MHz,
- RATE_IN_243X},
-
- /* PRCM #2 - ratio1 (ES2) - FAST */
- {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
- R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
- R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_165MHz,
- RATE_IN_243X},
-
- /* PRCM #5a - ratio1 - FAST */
- {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
- R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
- R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_133MHz,
- RATE_IN_243X},
-
- /* PRCM #5b - ratio1 - FAST */
- {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
- R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
- R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_100MHz,
- RATE_IN_243X},
-
- /* PRCM #4 - ratio1 (ES2.1) - SLOW */
- {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
- R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
- R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_133MHz,
- RATE_IN_243X},
-
- /* PRCM #2 - ratio1 (ES2) - SLOW */
- {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
- R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
- R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_165MHz,
- RATE_IN_243X},
-
- /* PRCM #5a - ratio1 - SLOW */
- {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
- R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
- R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_133MHz,
- RATE_IN_243X},
-
- /* PRCM #5b - ratio1 - SLOW*/
- {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
- R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
- R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_100MHz,
- RATE_IN_243X},
-
- /* PRCM-boot/bypass */
- {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13MHz */
- RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
- RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_BYPASS,
- RATE_IN_243X},
-
- /* PRCM-boot/bypass */
- {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12MHz */
- RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
- RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_BYPASS,
- RATE_IN_243X},
-
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-};
diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
deleted file mode 100644
index a451182cdc02..000000000000
--- a/arch/arm/mach-omap2/opp2xxx.h
+++ /dev/null
@@ -1,430 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
- *
- * Copyright (C) 2005-2009 Texas Instruments, Inc.
- * Copyright (C) 2004-2009 Nokia Corporation
- *
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
- * These configurations are characterized by voltage and speed for clocks.
- * The device is only validated for certain combinations. One way to express
- * these combinations is via the 'ratio's' which the clocks operate with
- * respect to each other. These ratio sets are for a given voltage/DPLL
- * setting. All configurations can be described by a DPLL setting and a ratio
- * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
- *
- * 2430 differs from 2420 in that there are no more phase synchronizers used.
- * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
- * 2430 (iva2.1, NOdsp, mdm)
- *
- * XXX Missing voltage data.
- *
- * THe format described in this file is deprecated. Once a reasonable
- * OPP API exists, the data in this file should be converted to use it.
- *
- * This is technically part of the OMAP2xxx clock code.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
-#define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
-
-/**
- * struct prcm_config - define clock rates on a per-OPP basis (24xx)
- *
- * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
- * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- *
- * This is deprecated. As soon as we have a decent OPP API, we should
- * move all this stuff to it.
- */
-struct prcm_config {
- unsigned long xtal_speed; /* crystal rate */
- unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
- unsigned long mpu_speed; /* speed of MPU */
- unsigned long cm_clksel_mpu; /* mpu divider */
- unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
- unsigned long cm_clksel_gfx; /* gfx dividers */
- unsigned long cm_clksel1_core; /* major subsystem dividers */
- unsigned long cm_clksel1_pll; /* m,n */
- unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
- unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
- unsigned long base_sdrc_rfr; /* base refresh timing for a set */
- unsigned short flags;
-};
-
-
-/* Core fields for cm_clksel, not ratio governed */
-#define RX_CLKSEL_DSS1 (0x10 << 8)
-#define RX_CLKSEL_DSS2 (0x0 << 13)
-#define RX_CLKSEL_SSI (0x5 << 20)
-
-/*-------------------------------------------------------------------------
- * Voltage/DPLL ratios
- *-------------------------------------------------------------------------*/
-
-/* 2430 Ratio's, 2430-Ratio Config 1 */
-#define R1_CLKSEL_L3 (4 << 0)
-#define R1_CLKSEL_L4 (2 << 5)
-#define R1_CLKSEL_USB (4 << 25)
-#define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB | RX_CLKSEL_SSI | \
- RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
- R1_CLKSEL_L4 | R1_CLKSEL_L3)
-#define R1_CLKSEL_MPU (2 << 0)
-#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
-#define R1_CLKSEL_DSP (2 << 0)
-#define R1_CLKSEL_DSP_IF (2 << 5)
-#define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF)
-#define R1_CLKSEL_GFX (2 << 0)
-#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
-#define R1_CLKSEL_MDM (4 << 0)
-#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
-
-/* 2430-Ratio Config 2 */
-#define R2_CLKSEL_L3 (6 << 0)
-#define R2_CLKSEL_L4 (2 << 5)
-#define R2_CLKSEL_USB (2 << 25)
-#define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB | RX_CLKSEL_SSI | \
- RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
- R2_CLKSEL_L4 | R2_CLKSEL_L3)
-#define R2_CLKSEL_MPU (2 << 0)
-#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
-#define R2_CLKSEL_DSP (2 << 0)
-#define R2_CLKSEL_DSP_IF (3 << 5)
-#define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF)
-#define R2_CLKSEL_GFX (2 << 0)
-#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
-#define R2_CLKSEL_MDM (6 << 0)
-#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
-
-/* 2430-Ratio Bootm (BYPASS) */
-#define RB_CLKSEL_L3 (1 << 0)
-#define RB_CLKSEL_L4 (1 << 5)
-#define RB_CLKSEL_USB (1 << 25)
-#define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB | RX_CLKSEL_SSI | \
- RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
- RB_CLKSEL_L4 | RB_CLKSEL_L3)
-#define RB_CLKSEL_MPU (1 << 0)
-#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
-#define RB_CLKSEL_DSP (1 << 0)
-#define RB_CLKSEL_DSP_IF (1 << 5)
-#define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF)
-#define RB_CLKSEL_GFX (1 << 0)
-#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
-#define RB_CLKSEL_MDM (1 << 0)
-#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
-
-/* 2420 Ratio Equivalents */
-#define RXX_CLKSEL_VLYNQ (0x12 << 15)
-#define RXX_CLKSEL_SSI (0x8 << 20)
-
-/* 2420-PRCM III 532MHz core */
-#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
-#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
-#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
-#define RIII_CM_CLKSEL1_CORE_VAL (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
- RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
- RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
- RIII_CLKSEL_L3)
-#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
-#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
-#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
-#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
-#define RIII_SYNC_DSP (1 << 7) /* Enable sync */
-#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
-#define RIII_SYNC_IVA (1 << 13) /* Enable sync */
-#define RIII_CM_CLKSEL_DSP_VAL (RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
- RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
- RIII_CLKSEL_DSP)
-#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
-#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
-
-/* 2420-PRCM II 600MHz core */
-#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
-#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
-#define RII_CLKSEL_USB (2 << 25) /* 50MHz */
-#define RII_CM_CLKSEL1_CORE_VAL (RII_CLKSEL_USB | RXX_CLKSEL_SSI | \
- RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
- RX_CLKSEL_DSS1 | RII_CLKSEL_L4 | \
- RII_CLKSEL_L3)
-#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
-#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
-#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
-#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
-#define RII_SYNC_DSP (0 << 7) /* Bypass sync */
-#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
-#define RII_SYNC_IVA (0 << 13) /* Bypass sync */
-#define RII_CM_CLKSEL_DSP_VAL (RII_SYNC_IVA | RII_CLKSEL_IVA | \
- RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
- RII_CLKSEL_DSP)
-#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
-#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
-
-/* 2420-PRCM I 660MHz core */
-#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
-#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
-#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
-#define RI_CM_CLKSEL1_CORE_VAL (RI_CLKSEL_USB | \
- RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
- RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
- RI_CLKSEL_L4 | RI_CLKSEL_L3)
-#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
-#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
-#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
-#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
-#define RI_SYNC_DSP (1 << 7) /* Activate sync */
-#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
-#define RI_SYNC_IVA (0 << 13) /* Bypass sync */
-#define RI_CM_CLKSEL_DSP_VAL (RI_SYNC_IVA | RI_CLKSEL_IVA | \
- RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
- RI_CLKSEL_DSP)
-#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
-#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
-
-/* 2420-PRCM VII (boot) */
-#define RVII_CLKSEL_L3 (1 << 0)
-#define RVII_CLKSEL_L4 (1 << 5)
-#define RVII_CLKSEL_DSS1 (1 << 8)
-#define RVII_CLKSEL_DSS2 (0 << 13)
-#define RVII_CLKSEL_VLYNQ (1 << 15)
-#define RVII_CLKSEL_SSI (1 << 20)
-#define RVII_CLKSEL_USB (1 << 25)
-
-#define RVII_CM_CLKSEL1_CORE_VAL (RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
- RVII_CLKSEL_VLYNQ | \
- RVII_CLKSEL_DSS2 | RVII_CLKSEL_DSS1 | \
- RVII_CLKSEL_L4 | RVII_CLKSEL_L3)
-
-#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
-#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
-
-#define RVII_CLKSEL_DSP (1 << 0)
-#define RVII_CLKSEL_DSP_IF (1 << 5)
-#define RVII_SYNC_DSP (0 << 7)
-#define RVII_CLKSEL_IVA (1 << 8)
-#define RVII_SYNC_IVA (0 << 13)
-#define RVII_CM_CLKSEL_DSP_VAL (RVII_SYNC_IVA | RVII_CLKSEL_IVA | \
- RVII_SYNC_DSP | RVII_CLKSEL_DSP_IF | \
- RVII_CLKSEL_DSP)
-
-#define RVII_CLKSEL_GFX (1 << 0)
-#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
-
-/*-------------------------------------------------------------------------
- * 2430 Target modes: Along with each configuration the CPU has several
- * modes which goes along with them. Modes mainly are the addition of
- * describe DPLL combinations to go along with a ratio.
- *-------------------------------------------------------------------------*/
-
-/* Hardware governed */
-#define MX_48M_SRC (0 << 3)
-#define MX_54M_SRC (0 << 5)
-#define MX_APLLS_CLIKIN_12 (3 << 23)
-#define MX_APLLS_CLIKIN_13 (2 << 23)
-#define MX_APLLS_CLIKIN_19_2 (0 << 23)
-
-/*
- * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
- * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
- */
-#define M5A_DPLL_MULT_12 (133 << 12)
-#define M5A_DPLL_DIV_12 (5 << 8)
-#define M5A_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12)
-#define M5A_DPLL_MULT_13 (61 << 12)
-#define M5A_DPLL_DIV_13 (2 << 8)
-#define M5A_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
- M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
- MX_APLLS_CLIKIN_13)
-#define M5A_DPLL_MULT_19 (55 << 12)
-#define M5A_DPLL_DIV_19 (3 << 8)
-#define M5A_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
- M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
- MX_APLLS_CLIKIN_19_2)
-/* #5b (ratio1) target DPLL = 200*2 = 400MHz */
-#define M5B_DPLL_MULT_12 (50 << 12)
-#define M5B_DPLL_DIV_12 (2 << 8)
-#define M5B_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12)
-#define M5B_DPLL_MULT_13 (200 << 12)
-#define M5B_DPLL_DIV_13 (12 << 8)
-
-#define M5B_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
- M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
- MX_APLLS_CLIKIN_13)
-#define M5B_DPLL_MULT_19 (125 << 12)
-#define M5B_DPLL_DIV_19 (31 << 8)
-#define M5B_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
- M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
- MX_APLLS_CLIKIN_19_2)
-/*
- * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
- */
-#define M4_DPLL_MULT_12 (133 << 12)
-#define M4_DPLL_DIV_12 (3 << 8)
-#define M4_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12)
-
-#define M4_DPLL_MULT_13 (399 << 12)
-#define M4_DPLL_DIV_13 (12 << 8)
-#define M4_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
- M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
- MX_APLLS_CLIKIN_13)
-
-#define M4_DPLL_MULT_19 (145 << 12)
-#define M4_DPLL_DIV_19 (6 << 8)
-#define M4_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
- M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
- MX_APLLS_CLIKIN_19_2)
-
-/*
- * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
- */
-#define M3_DPLL_MULT_12 (55 << 12)
-#define M3_DPLL_DIV_12 (1 << 8)
-#define M3_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12)
-#define M3_DPLL_MULT_13 (76 << 12)
-#define M3_DPLL_DIV_13 (2 << 8)
-#define M3_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
- M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
- MX_APLLS_CLIKIN_13)
-#define M3_DPLL_MULT_19 (17 << 12)
-#define M3_DPLL_DIV_19 (0 << 8)
-#define M3_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
- M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
- MX_APLLS_CLIKIN_19_2)
-
-/*
- * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
- */
-#define M2_DPLL_MULT_12 (55 << 12)
-#define M2_DPLL_DIV_12 (1 << 8)
-#define M2_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12)
-
-/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
- * relock time issue */
-/* Core frequency changed from 330/165 to 329/164 MHz*/
-#define M2_DPLL_MULT_13 (76 << 12)
-#define M2_DPLL_DIV_13 (2 << 8)
-#define M2_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
- M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
- MX_APLLS_CLIKIN_13)
-
-#define M2_DPLL_MULT_19 (17 << 12)
-#define M2_DPLL_DIV_19 (0 << 8)
-#define M2_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
- M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
- MX_APLLS_CLIKIN_19_2)
-
-/* boot (boot) */
-#define MB_DPLL_MULT (1 << 12)
-#define MB_DPLL_DIV (0 << 8)
-#define MB_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- MB_DPLL_DIV | MB_DPLL_MULT | \
- MX_APLLS_CLIKIN_12)
-
-#define MB_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
- MB_DPLL_DIV | MB_DPLL_MULT | \
- MX_APLLS_CLIKIN_13)
-
-#define MB_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
- MB_DPLL_DIV | MB_DPLL_MULT | \
- MX_APLLS_CLIKIN_19)
-
-/*
- * 2430 - chassis (sedna)
- * 165 (ratio1) same as above #2
- * 150 (ratio1)
- * 133 (ratio2) same as above #4
- * 110 (ratio2) same as above #3
- * 104 (ratio2)
- * boot (boot)
- */
-
-/* PRCM I target DPLL = 2*330MHz = 660MHz */
-#define MI_DPLL_MULT_12 (55 << 12)
-#define MI_DPLL_DIV_12 (1 << 8)
-#define MI_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12)
-
-/*
- * 2420 Equivalent - mode registers
- * PRCM II , target DPLL = 2*300MHz = 600MHz
- */
-#define MII_DPLL_MULT_12 (50 << 12)
-#define MII_DPLL_DIV_12 (1 << 8)
-#define MII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12)
-#define MII_DPLL_MULT_13 (300 << 12)
-#define MII_DPLL_DIV_13 (12 << 8)
-#define MII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
- MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
- MX_APLLS_CLIKIN_13)
-
-/* PRCM III target DPLL = 2*266 = 532MHz*/
-#define MIII_DPLL_MULT_12 (133 << 12)
-#define MIII_DPLL_DIV_12 (5 << 8)
-#define MIII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- MIII_DPLL_DIV_12 | \
- MIII_DPLL_MULT_12 | MX_APLLS_CLIKIN_12)
-#define MIII_DPLL_MULT_13 (266 << 12)
-#define MIII_DPLL_DIV_13 (12 << 8)
-#define MIII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
- MIII_DPLL_DIV_13 | \
- MIII_DPLL_MULT_13 | MX_APLLS_CLIKIN_13)
-
-/* PRCM VII (boot bypass) */
-#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
-#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
-
-/* High and low operation value */
-#define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
-#define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
-
-/* MPU speed defines */
-#define S12M 12000000
-#define S13M 13000000
-#define S19M 19200000
-#define S26M 26000000
-#define S100M 100000000
-#define S133M 133000000
-#define S150M 150000000
-#define S164M 164000000
-#define S165M 165000000
-#define S199M 199000000
-#define S200M 200000000
-#define S266M 266000000
-#define S300M 300000000
-#define S329M 329000000
-#define S330M 330000000
-#define S399M 399000000
-#define S400M 400000000
-#define S532M 532000000
-#define S600M 600000000
-#define S658M 658000000
-#define S660M 660000000
-#define S798M 798000000
-
-
-extern const struct prcm_config omap2420_rate_table[];
-
-#ifdef CONFIG_SOC_OMAP2430
-extern const struct prcm_config omap2430_rate_table[];
-#else
-#define omap2430_rate_table NULL
-#endif
-extern const struct prcm_config *rate_table;
-extern const struct prcm_config *curr_prcm_set;
-
-#endif
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index b947bacf23a3..8b8021b297aa 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -27,7 +27,6 @@
#include "clockdomain.h"
#include "common.h"
-#include "common-board-devices.h"
#include "control.h"
#include "omap_device.h"
#include "omap-secure.h"
@@ -42,15 +41,6 @@ struct pdata_init {
static struct of_dev_auxdata omap_auxdata_lookup[];
-#ifdef CONFIG_MACH_NOKIA_N8X0
-static void __init omap2420_n8x0_legacy_init(void)
-{
- omap_auxdata_lookup[0].platform_data = n8x0_legacy_init();
-}
-#else
-#define omap2420_n8x0_legacy_init NULL
-#endif
-
#ifdef CONFIG_ARCH_OMAP3
/*
* Configures GPIOs 126, 127 and 129 to 1.8V mode instead of 3.0V
@@ -431,26 +421,9 @@ static void __init omap3_mcbsp_init(void)
static void __init omap3_mcbsp_init(void) {}
#endif
-/*
- * Few boards still need auxdata populated before we populate
- * the dev entries in of_platform_populate().
- */
-static struct pdata_init auxdata_quirks[] __initdata = {
-#ifdef CONFIG_SOC_OMAP2420
- { "nokia,n800", omap2420_n8x0_legacy_init, },
- { "nokia,n810", omap2420_n8x0_legacy_init, },
- { "nokia,n810-wimax", omap2420_n8x0_legacy_init, },
-#endif
- { /* sentinel */ },
-};
-
struct omap_sr_data __maybe_unused omap_sr_pdata[OMAP_SR_NR];
static struct of_dev_auxdata omap_auxdata_lookup[] = {
-#ifdef CONFIG_MACH_NOKIA_N8X0
- OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL),
- OF_DEV_AUXDATA("menelaus", 0x72, "1-0072", &n8x0_menelaus_platform_data),
-#endif
#ifdef CONFIG_ARCH_OMAP3
OF_DEV_AUXDATA("ti,omap2-iommu", 0x5d000000, "5d000000.mmu",
&omap3_iommu_pdata),
@@ -560,13 +533,11 @@ void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table)
* We still need this for omap2420 and omap3 PM to work, others are
* using drivers/misc/sram.c already.
*/
- if (of_machine_is_compatible("ti,omap2420") ||
- of_machine_is_compatible("ti,omap3"))
+ if (IS_ENABLED(CONFIG_ARCH_OMAP3) &&
+ of_machine_is_compatible("ti,omap3")) {
omap_sdrc_init(NULL, NULL);
-
- if (of_machine_is_compatible("ti,omap3"))
omap3_mcbsp_init();
- pdata_quirks_check(auxdata_quirks);
+ }
pdata_quirks_init_clocks(omap_dt_match_table);
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index f97ff93f2fb4..5751b85e9ffb 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -43,11 +43,6 @@ extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
#endif /* CONFIG_PM_DEBUG */
-/* 24xx */
-extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
- void __iomem *sdrc_power);
-extern unsigned int omap24xx_cpu_suspend_sz;
-
/* 3xxx */
extern void omap34xx_cpu_suspend(int save_state);
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index fbc89999460b..eaf6d1104dc2 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -244,8 +244,6 @@ int pwrdm_post_transition(struct powerdomain *pwrdm);
extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state);
-extern void omap242x_powerdomains_init(void);
-extern void omap243x_powerdomains_init(void);
extern void omap3xxx_powerdomains_init(void);
extern void am33xx_powerdomains_init(void);
extern void omap44xx_powerdomains_init(void);
@@ -253,7 +251,6 @@ extern void omap54xx_powerdomains_init(void);
extern void dra7xx_powerdomains_init(void);
void am43xx_powerdomains_init(void);
-extern struct pwrdm_ops omap2_pwrdm_operations;
extern struct pwrdm_ops omap3_pwrdm_operations;
extern struct pwrdm_ops am33xx_pwrdm_operations;
extern struct pwrdm_ops omap4_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
deleted file mode 100644
index fa259adbdc61..000000000000
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ /dev/null
@@ -1,134 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * OMAP2XXX powerdomain definitions
- *
- * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
- * Copyright (C) 2007-2011 Nokia Corporation
- *
- * Paul Walmsley, Jouni Högander
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include "soc.h"
-#include "powerdomain.h"
-#include "powerdomains2xxx_3xxx_data.h"
-
-#include "prcm-common.h"
-#include "prm2xxx_3xxx.h"
-#include "prm-regbits-24xx.h"
-
-/* 24XX powerdomains and dependencies */
-
-/* Powerdomains */
-
-static struct powerdomain dsp_pwrdm = {
- .name = "dsp_pwrdm",
- .prcm_offs = OMAP24XX_DSP_MOD,
- .pwrsts = PWRSTS_OFF_RET_ON,
- .pwrsts_logic_ret = PWRSTS_RET,
- .banks = 1,
- .pwrsts_mem_ret = {
- [0] = PWRSTS_RET,
- },
- .pwrsts_mem_on = {
- [0] = PWRSTS_ON,
- },
- .voltdm = { .name = "core" },
-};
-
-static struct powerdomain mpu_24xx_pwrdm = {
- .name = "mpu_pwrdm",
- .prcm_offs = MPU_MOD,
- .pwrsts = PWRSTS_OFF_RET_ON,
- .pwrsts_logic_ret = PWRSTS_OFF_RET,
- .banks = 1,
- .pwrsts_mem_ret = {
- [0] = PWRSTS_RET,
- },
- .pwrsts_mem_on = {
- [0] = PWRSTS_ON,
- },
- .voltdm = { .name = "core" },
-};
-
-static struct powerdomain core_24xx_pwrdm = {
- .name = "core_pwrdm",
- .prcm_offs = CORE_MOD,
- .pwrsts = PWRSTS_OFF_RET_ON,
- .pwrsts_logic_ret = PWRSTS_RET,
- .banks = 3,
- .pwrsts_mem_ret = {
- [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
- [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
- [2] = PWRSTS_OFF_RET, /* MEM3RETSTATE */
- },
- .pwrsts_mem_on = {
- [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
- [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
- [2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */
- },
- .voltdm = { .name = "core" },
-};
-
-
-/*
- * 2430-specific powerdomains
- */
-
-/* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */
-
-static struct powerdomain mdm_pwrdm = {
- .name = "mdm_pwrdm",
- .prcm_offs = OMAP2430_MDM_MOD,
- .pwrsts = PWRSTS_OFF_RET_ON,
- .pwrsts_logic_ret = PWRSTS_RET,
- .banks = 1,
- .pwrsts_mem_ret = {
- [0] = PWRSTS_RET, /* MEMRETSTATE */
- },
- .pwrsts_mem_on = {
- [0] = PWRSTS_ON, /* MEMONSTATE */
- },
- .voltdm = { .name = "core" },
-};
-
-/*
- *
- */
-
-static struct powerdomain *powerdomains_omap24xx[] __initdata = {
- &wkup_omap2_pwrdm,
- &gfx_omap2_pwrdm,
- &dsp_pwrdm,
- &mpu_24xx_pwrdm,
- &core_24xx_pwrdm,
- NULL
-};
-
-static struct powerdomain *powerdomains_omap2430[] __initdata = {
- &mdm_pwrdm,
- NULL
-};
-
-void __init omap242x_powerdomains_init(void)
-{
- if (!cpu_is_omap2420())
- return;
-
- pwrdm_register_platform_funcs(&omap2_pwrdm_operations);
- pwrdm_register_pwrdms(powerdomains_omap24xx);
- pwrdm_complete_init();
-}
-
-void __init omap243x_powerdomains_init(void)
-{
- if (!cpu_is_omap2430())
- return;
-
- pwrdm_register_platform_funcs(&omap2_pwrdm_operations);
- pwrdm_register_pwrdms(powerdomains_omap24xx);
- pwrdm_register_pwrdms(powerdomains_omap2430);
- pwrdm_complete_init();
-}
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 5e3544a63526..e326bb6a09db 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -27,12 +27,6 @@
#define PLL_MOD 0x500
-/* Chip-specific module offsets */
-#define OMAP24XX_GR_MOD OCP_MOD
-#define OMAP24XX_DSP_MOD 0x800
-
-#define OMAP2430_MDM_MOD 0xc00
-
/* IVA2 module is < base on 3430 */
#define OMAP3430_IVA2_MOD -0x800
#define OMAP3430ES2_SGX_MOD GFX_MOD
@@ -63,147 +57,6 @@
#define TI816X_PRM_SGX_MOD 0x0f00
#define TI81XX_PRM_ALWON_MOD 0x1800
-/* 24XX register bits shared between CM & PRM registers */
-
-/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
-#define OMAP2420_EN_MMC_SHIFT 26
-#define OMAP2420_EN_MMC_MASK (1 << 26)
-#define OMAP24XX_EN_UART2_SHIFT 22
-#define OMAP24XX_EN_UART2_MASK (1 << 22)
-#define OMAP24XX_EN_UART1_SHIFT 21
-#define OMAP24XX_EN_UART1_MASK (1 << 21)
-#define OMAP24XX_EN_MCSPI2_SHIFT 18
-#define OMAP24XX_EN_MCSPI2_MASK (1 << 18)
-#define OMAP24XX_EN_MCSPI1_SHIFT 17
-#define OMAP24XX_EN_MCSPI1_MASK (1 << 17)
-#define OMAP24XX_EN_MCBSP2_SHIFT 16
-#define OMAP24XX_EN_MCBSP2_MASK (1 << 16)
-#define OMAP24XX_EN_MCBSP1_SHIFT 15
-#define OMAP24XX_EN_MCBSP1_MASK (1 << 15)
-#define OMAP24XX_EN_GPT12_SHIFT 14
-#define OMAP24XX_EN_GPT12_MASK (1 << 14)
-#define OMAP24XX_EN_GPT11_SHIFT 13
-#define OMAP24XX_EN_GPT11_MASK (1 << 13)
-#define OMAP24XX_EN_GPT10_SHIFT 12
-#define OMAP24XX_EN_GPT10_MASK (1 << 12)
-#define OMAP24XX_EN_GPT9_SHIFT 11
-#define OMAP24XX_EN_GPT9_MASK (1 << 11)
-#define OMAP24XX_EN_GPT8_SHIFT 10
-#define OMAP24XX_EN_GPT8_MASK (1 << 10)
-#define OMAP24XX_EN_GPT7_SHIFT 9
-#define OMAP24XX_EN_GPT7_MASK (1 << 9)
-#define OMAP24XX_EN_GPT6_SHIFT 8
-#define OMAP24XX_EN_GPT6_MASK (1 << 8)
-#define OMAP24XX_EN_GPT5_SHIFT 7
-#define OMAP24XX_EN_GPT5_MASK (1 << 7)
-#define OMAP24XX_EN_GPT4_SHIFT 6
-#define OMAP24XX_EN_GPT4_MASK (1 << 6)
-#define OMAP24XX_EN_GPT3_SHIFT 5
-#define OMAP24XX_EN_GPT3_MASK (1 << 5)
-#define OMAP24XX_EN_GPT2_SHIFT 4
-#define OMAP24XX_EN_GPT2_MASK (1 << 4)
-#define OMAP2420_EN_VLYNQ_SHIFT 3
-#define OMAP2420_EN_VLYNQ_MASK (1 << 3)
-
-/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
-#define OMAP2430_EN_GPIO5_SHIFT 10
-#define OMAP2430_EN_GPIO5_MASK (1 << 10)
-#define OMAP2430_EN_MCSPI3_SHIFT 9
-#define OMAP2430_EN_MCSPI3_MASK (1 << 9)
-#define OMAP2430_EN_MMCHS2_SHIFT 8
-#define OMAP2430_EN_MMCHS2_MASK (1 << 8)
-#define OMAP2430_EN_MMCHS1_SHIFT 7
-#define OMAP2430_EN_MMCHS1_MASK (1 << 7)
-#define OMAP24XX_EN_UART3_SHIFT 2
-#define OMAP24XX_EN_UART3_MASK (1 << 2)
-#define OMAP24XX_EN_USB_SHIFT 0
-#define OMAP24XX_EN_USB_MASK (1 << 0)
-
-/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
-#define OMAP2430_EN_MDM_INTC_SHIFT 11
-#define OMAP2430_EN_MDM_INTC_MASK (1 << 11)
-#define OMAP2430_EN_USBHS_SHIFT 6
-#define OMAP2430_EN_USBHS_MASK (1 << 6)
-#define OMAP24XX_EN_GPMC_SHIFT 1
-#define OMAP24XX_EN_GPMC_MASK (1 << 1)
-
-/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
-#define OMAP2420_ST_MMC_SHIFT 26
-#define OMAP2420_ST_MMC_MASK (1 << 26)
-#define OMAP24XX_ST_UART2_SHIFT 22
-#define OMAP24XX_ST_UART2_MASK (1 << 22)
-#define OMAP24XX_ST_UART1_SHIFT 21
-#define OMAP24XX_ST_UART1_MASK (1 << 21)
-#define OMAP24XX_ST_MCSPI2_SHIFT 18
-#define OMAP24XX_ST_MCSPI2_MASK (1 << 18)
-#define OMAP24XX_ST_MCSPI1_SHIFT 17
-#define OMAP24XX_ST_MCSPI1_MASK (1 << 17)
-#define OMAP24XX_ST_MCBSP2_SHIFT 16
-#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
-#define OMAP24XX_ST_MCBSP1_SHIFT 15
-#define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
-#define OMAP24XX_ST_GPT12_SHIFT 14
-#define OMAP24XX_ST_GPT12_MASK (1 << 14)
-#define OMAP24XX_ST_GPT11_SHIFT 13
-#define OMAP24XX_ST_GPT11_MASK (1 << 13)
-#define OMAP24XX_ST_GPT10_SHIFT 12
-#define OMAP24XX_ST_GPT10_MASK (1 << 12)
-#define OMAP24XX_ST_GPT9_SHIFT 11
-#define OMAP24XX_ST_GPT9_MASK (1 << 11)
-#define OMAP24XX_ST_GPT8_SHIFT 10
-#define OMAP24XX_ST_GPT8_MASK (1 << 10)
-#define OMAP24XX_ST_GPT7_SHIFT 9
-#define OMAP24XX_ST_GPT7_MASK (1 << 9)
-#define OMAP24XX_ST_GPT6_SHIFT 8
-#define OMAP24XX_ST_GPT6_MASK (1 << 8)
-#define OMAP24XX_ST_GPT5_SHIFT 7
-#define OMAP24XX_ST_GPT5_MASK (1 << 7)
-#define OMAP24XX_ST_GPT4_SHIFT 6
-#define OMAP24XX_ST_GPT4_MASK (1 << 6)
-#define OMAP24XX_ST_GPT3_SHIFT 5
-#define OMAP24XX_ST_GPT3_MASK (1 << 5)
-#define OMAP24XX_ST_GPT2_SHIFT 4
-#define OMAP24XX_ST_GPT2_MASK (1 << 4)
-#define OMAP2420_ST_VLYNQ_SHIFT 3
-#define OMAP2420_ST_VLYNQ_MASK (1 << 3)
-
-/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
-#define OMAP2430_ST_MDM_INTC_SHIFT 11
-#define OMAP2430_ST_MDM_INTC_MASK (1 << 11)
-#define OMAP2430_ST_GPIO5_SHIFT 10
-#define OMAP2430_ST_GPIO5_MASK (1 << 10)
-#define OMAP2430_ST_MCSPI3_SHIFT 9
-#define OMAP2430_ST_MCSPI3_MASK (1 << 9)
-#define OMAP2430_ST_MMCHS2_SHIFT 8
-#define OMAP2430_ST_MMCHS2_MASK (1 << 8)
-#define OMAP2430_ST_MMCHS1_SHIFT 7
-#define OMAP2430_ST_MMCHS1_MASK (1 << 7)
-#define OMAP2430_ST_USBHS_SHIFT 6
-#define OMAP2430_ST_USBHS_MASK (1 << 6)
-#define OMAP24XX_ST_UART3_SHIFT 2
-#define OMAP24XX_ST_UART3_MASK (1 << 2)
-#define OMAP24XX_ST_USB_SHIFT 0
-#define OMAP24XX_ST_USB_MASK (1 << 0)
-
-/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
-#define OMAP24XX_EN_GPIOS_SHIFT 2
-#define OMAP24XX_EN_GPIOS_MASK (1 << 2)
-#define OMAP24XX_EN_GPT1_SHIFT 0
-#define OMAP24XX_EN_GPT1_MASK (1 << 0)
-
-/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
-#define OMAP24XX_ST_GPIOS_SHIFT 2
-#define OMAP24XX_ST_GPIOS_MASK (1 << 2)
-#define OMAP24XX_ST_32KSYNC_SHIFT 1
-#define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
-#define OMAP24XX_ST_GPT1_SHIFT 0
-#define OMAP24XX_ST_GPT1_MASK (1 << 0)
-
-/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
-#define OMAP2430_ST_MDM_SHIFT 0
-#define OMAP2430_ST_MDM_MASK (1 << 0)
-
-
/* 3430 register bits shared between CM & PRM registers */
/* CM_REVISION, PRM_REVISION shared bits */
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
deleted file mode 100644
index ff83801f6439..000000000000
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
-#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
-
-/*
- * OMAP24XX Power/Reset Management register bits
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
- *
- * Written by Paul Walmsley
- */
-
-#include "prm2xxx.h"
-
-#define OMAP24XX_EN_CORE_SHIFT 0
-#define OMAP24XX_FORCESTATE_MASK (1 << 18)
-#define OMAP24XX_AUTOIDLE_MASK (1 << 0)
-#define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15)
-#define OMAP24XX_SETOFF_LEVEL_SHIFT 12
-#define OMAP24XX_MEMRETCTRL_MASK (1 << 8)
-#define OMAP24XX_SETRET_LEVEL_SHIFT 6
-#define OMAP24XX_VOLT_LEVEL_SHIFT 0
-#define OMAP2420_CLKOUT2_EN_SHIFT 15
-#define OMAP2420_CLKOUT2_DIV_SHIFT 11
-#define OMAP2420_CLKOUT2_DIV_WIDTH 3
-#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
-#define OMAP24XX_CLKOUT_EN_SHIFT 7
-#define OMAP24XX_CLKOUT_DIV_SHIFT 3
-#define OMAP24XX_CLKOUT_DIV_WIDTH 3
-#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0)
-#define OMAP24XX_EMULATION_EN_SHIFT 0
-#define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5
-#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2
-#define OMAP24XX_EXTWMPU_RST_SHIFT 6
-#define OMAP24XX_SECU_WD_RST_SHIFT 5
-#define OMAP24XX_MPU_WD_RST_SHIFT 4
-#define OMAP24XX_SECU_VIOL_RST_SHIFT 3
-#endif
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
deleted file mode 100644
index 35a58f54b528..000000000000
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ /dev/null
@@ -1,229 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * OMAP2xxx PRM module functions
- *
- * Copyright (C) 2010-2012 Texas Instruments, Inc.
- * Copyright (C) 2010 Nokia Corporation
- * Benoît Cousson
- * Paul Walmsley
- * Rajendra Nayak <rnayak@ti.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-
-#include "powerdomain.h"
-#include "clockdomain.h"
-#include "prm2xxx.h"
-#include "cm2xxx_3xxx.h"
-#include "prm-regbits-24xx.h"
-
-/*
- * OMAP24xx PM_PWSTCTRL_*.POWERSTATE and PM_PWSTST_*.LASTSTATEENTERED bits -
- * these are reversed from the bits used on OMAP3+
- */
-#define OMAP24XX_PWRDM_POWER_ON 0x0
-#define OMAP24XX_PWRDM_POWER_RET 0x1
-#define OMAP24XX_PWRDM_POWER_OFF 0x3
-
-/*
- * omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP
- * hardware register (which are specific to the OMAP2xxx SoCs) to
- * reset source ID bit shifts (which is an OMAP SoC-independent
- * enumeration)
- */
-static struct prm_reset_src_map omap2xxx_prm_reset_src_map[] = {
- { OMAP_GLOBALCOLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
- { OMAP_GLOBALWARM_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
- { OMAP24XX_SECU_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
- { OMAP24XX_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
- { OMAP24XX_SECU_WD_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
- { OMAP24XX_EXTWMPU_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
- { -1, -1 },
-};
-
-/**
- * omap2xxx_prm_read_reset_sources - return the last SoC reset source
- *
- * Return a u32 representing the last reset sources of the SoC. The
- * returned reset source bits are standardized across OMAP SoCs.
- */
-static u32 omap2xxx_prm_read_reset_sources(void)
-{
- struct prm_reset_src_map *p;
- u32 r = 0;
- u32 v;
-
- v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);
-
- p = omap2xxx_prm_reset_src_map;
- while (p->reg_shift >= 0 && p->std_shift >= 0) {
- if (v & (1 << p->reg_shift))
- r |= 1 << p->std_shift;
- p++;
- }
-
- return r;
-}
-
-/**
- * omap2xxx_pwrst_to_common_pwrst - convert OMAP2xxx pwrst to common pwrst
- * @omap2xxx_pwrst: OMAP2xxx hardware power state to convert
- *
- * Return the common power state bits corresponding to the OMAP2xxx
- * hardware power state bits @omap2xxx_pwrst, or -EINVAL upon error.
- */
-static int omap2xxx_pwrst_to_common_pwrst(u8 omap2xxx_pwrst)
-{
- u8 pwrst;
-
- switch (omap2xxx_pwrst) {
- case OMAP24XX_PWRDM_POWER_OFF:
- pwrst = PWRDM_POWER_OFF;
- break;
- case OMAP24XX_PWRDM_POWER_RET:
- pwrst = PWRDM_POWER_RET;
- break;
- case OMAP24XX_PWRDM_POWER_ON:
- pwrst = PWRDM_POWER_ON;
- break;
- default:
- return -EINVAL;
- }
-
- return pwrst;
-}
-
-/**
- * omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC
- *
- * Set the DPLL reset bit, which should reboot the SoC. This is the
- * recommended way to restart the SoC. No return value.
- */
-static void omap2xxx_prm_dpll_reset(void)
-{
- omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, WKUP_MOD,
- OMAP2_RM_RSTCTRL);
- /* OCP barrier */
- omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL);
-}
-
-/**
- * omap2xxx_prm_clear_mod_irqs - clear wakeup status bits for a module
- * @module: PRM module to clear wakeups from
- * @regs: register offset to clear
- * @wkst_mask: wakeup status mask to clear
- *
- * Clears wakeup status bits for a given module, so that the device can
- * re-enter idle.
- */
-static int omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
-{
- u32 wkst;
-
- wkst = omap2_prm_read_mod_reg(module, regs);
- wkst &= wkst_mask;
- omap2_prm_write_mod_reg(wkst, module, regs);
- return 0;
-}
-
-int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
-{
- omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
- clkdm->pwrdm.ptr->prcm_offs,
- OMAP2_PM_PWSTCTRL);
- return 0;
-}
-
-int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm)
-{
- omap2_prm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
- clkdm->pwrdm.ptr->prcm_offs,
- OMAP2_PM_PWSTCTRL);
- return 0;
-}
-
-static int omap2xxx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
-{
- u8 omap24xx_pwrst;
-
- switch (pwrst) {
- case PWRDM_POWER_OFF:
- omap24xx_pwrst = OMAP24XX_PWRDM_POWER_OFF;
- break;
- case PWRDM_POWER_RET:
- omap24xx_pwrst = OMAP24XX_PWRDM_POWER_RET;
- break;
- case PWRDM_POWER_ON:
- omap24xx_pwrst = OMAP24XX_PWRDM_POWER_ON;
- break;
- default:
- return -EINVAL;
- }
-
- omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
- (omap24xx_pwrst << OMAP_POWERSTATE_SHIFT),
- pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
- return 0;
-}
-
-static int omap2xxx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
-{
- u8 omap2xxx_pwrst;
-
- omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
- OMAP2_PM_PWSTCTRL,
- OMAP_POWERSTATE_MASK);
-
- return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst);
-}
-
-static int omap2xxx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
-{
- u8 omap2xxx_pwrst;
-
- omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
- OMAP2_PM_PWSTST,
- OMAP_POWERSTATEST_MASK);
-
- return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst);
-}
-
-struct pwrdm_ops omap2_pwrdm_operations = {
- .pwrdm_set_next_pwrst = omap2xxx_pwrdm_set_next_pwrst,
- .pwrdm_read_next_pwrst = omap2xxx_pwrdm_read_next_pwrst,
- .pwrdm_read_pwrst = omap2xxx_pwrdm_read_pwrst,
- .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
- .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
- .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
- .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst,
- .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst,
- .pwrdm_wait_transition = omap2_pwrdm_wait_transition,
-};
-
-/*
- *
- */
-
-static struct prm_ll_data omap2xxx_prm_ll_data = {
- .read_reset_sources = &omap2xxx_prm_read_reset_sources,
- .assert_hardreset = &omap2_prm_assert_hardreset,
- .deassert_hardreset = &omap2_prm_deassert_hardreset,
- .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
- .reset_system = &omap2xxx_prm_dpll_reset,
- .clear_mod_irqs = &omap2xxx_prm_clear_mod_irqs,
-};
-
-int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data)
-{
- return prm_register(&omap2xxx_prm_ll_data);
-}
-
-static void __exit omap2xxx_prm_exit(void)
-{
- prm_unregister(&omap2xxx_prm_ll_data);
-}
-__exitcall(omap2xxx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
deleted file mode 100644
index 659b917348f8..000000000000
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * OMAP2xxx Power/Reset Management (PRM) register definitions
- *
- * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
- * Copyright (C) 2008-2010 Nokia Corporation
- * Paul Walmsley
- *
- * The PRM hardware modules on the OMAP2/3 are quite similar to each
- * other. The PRM on OMAP4 has a new register layout, and is handled
- * in a separate file.
- */
-#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
-#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
-
-#include "prcm-common.h"
-#include "prm.h"
-#include "prm2xxx_3xxx.h"
-
-#define OMAP2420_PRM_REGADDR(module, reg) \
- OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
-#define OMAP2430_PRM_REGADDR(module, reg) \
- OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
-
-/*
- * OMAP2-specific global PRM registers
- * Use {read,write}l_relaxed() with these registers.
- *
- * With a few exceptions, these are the register names beginning with
- * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE
- * bits.)
- *
- */
-
-#define OMAP2_PRCM_REVISION_OFFSET 0x0000
-#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
-#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
-
-#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
-#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
-#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
-
-#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
-#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
-#define OMAP2_PRCM_VOLTST_OFFSET 0x0054
-#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
-#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
-#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
-#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
-#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
-#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
-#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
-#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
-#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
-#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
-#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
-#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
-#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
-#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
-#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
-#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
-#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
-
-#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
-
-#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
-
-#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
-#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
-#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
-#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
-#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
-#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
-#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
-#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
-#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
-#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
-
-/*
- * Module specific PRM register offsets from PRM_BASE + domain offset
- *
- * Use prm_{read,write}_mod_reg() with these registers.
- *
- * With a few exceptions, these are the register names beginning with
- * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the
- * IRQSTATUS and IRQENABLE bits.)
- */
-
-/* Register offsets appearing on both OMAP2 and OMAP3 */
-
-#define OMAP2_RM_RSTCTRL 0x0050
-#define OMAP2_RM_RSTTIME 0x0054
-#define OMAP2_RM_RSTST 0x0058
-#define OMAP2_PM_PWSTCTRL 0x00e0
-#define OMAP2_PM_PWSTST 0x00e4
-
-#define PM_WKEN 0x00a0
-#define PM_WKEN1 PM_WKEN
-#define PM_WKST 0x00b0
-#define PM_WKST1 PM_WKST
-#define PM_WKDEP 0x00c8
-#define PM_EVGENCTRL 0x00d4
-#define PM_EVGENONTIM 0x00d8
-#define PM_EVGENOFFTIM 0x00dc
-
-/* OMAP2xxx specific register offsets */
-#define OMAP24XX_PM_WKEN2 0x00a4
-#define OMAP24XX_PM_WKST2 0x00b4
-
-#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
-#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
-#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
-#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
-
-#ifndef __ASSEMBLER__
-/* Function prototypes */
-extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
-extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
-
-int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data);
-
-#endif
-
-#endif
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index d983efac6f4f..afaba7153ece 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -15,7 +15,6 @@
#include "powerdomain.h"
#include "prm2xxx_3xxx.h"
-#include "prm-regbits-24xx.h"
#include "clockdomain.h"
/**
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index ee4588acda50..3546e7292bfb 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -26,7 +26,6 @@
#include "soc.h"
#include "prm2xxx_3xxx.h"
-#include "prm2xxx.h"
#include "prm3xxx.h"
#include "prm33xx.h"
#include "prm44xx.h"
@@ -582,13 +581,6 @@ int prm_unregister(struct prm_ll_data *pld)
return 0;
}
-#ifdef CONFIG_ARCH_OMAP2
-static struct omap_prcm_init_data omap2_prm_data __initdata = {
- .index = TI_CLKM_PRM,
- .init = omap2xxx_prm_init,
-};
-#endif
-
#ifdef CONFIG_ARCH_OMAP3
static struct omap_prcm_init_data omap3_prm_data __initdata = {
.index = TI_CLKM_PRM,
@@ -670,9 +662,6 @@ static const struct of_device_id omap_prcm_dt_match_table[] __initconst = {
{ .compatible = "ti,dm814-pllss", .data = &dm814_pllss_data },
{ .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
#endif
-#ifdef CONFIG_ARCH_OMAP2
- { .compatible = "ti,omap2-prcm", .data = &omap2_prm_data },
-#endif
#ifdef CONFIG_ARCH_OMAP3
{ .compatible = "ti,omap3-prm", .data = &omap3_prm_data },
#endif
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 45b35422b587..c34fba4d2f1a 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -90,17 +90,7 @@ struct memory_timings {
u32 base_cs; /* base chip select to use for calculations */
};
-extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
-
-u32 omap2xxx_sdrc_dll_is_unlocked(void);
-u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
-
-
#else
-#define OMAP242X_SDRC_REGADDR(reg) \
- OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
-#define OMAP243X_SDRC_REGADDR(reg) \
- OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
#define OMAP34XX_SDRC_REGADDR(reg) \
OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
@@ -184,17 +174,6 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
-/*
- * SMS register access
- */
-
-#define OMAP242X_SMS_REGADDR(reg) \
- (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
-#define OMAP243X_SMS_REGADDR(reg) \
- (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
-#define OMAP343X_SMS_REGADDR(reg) \
- (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
-
/* SMS register offsets - read/write with sms_{read,write}_reg() */
#define SMS_SYSCONFIG 0x010
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
deleted file mode 100644
index 5a275b4fd404..000000000000
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ /dev/null
@@ -1,164 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * SDRAM timing related functions for OMAP2xxx
- *
- * Copyright (C) 2005, 2008 Texas Instruments Inc.
- * Copyright (C) 2005, 2008 Nokia Corporation
- *
- * Tony Lindgren <tony@atomide.com>
- * Paul Walmsley
- * Richard Woodruff <r-woodruff2@ti.com>
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include "soc.h"
-#include "iomap.h"
-#include "common.h"
-#include "prm2xxx.h"
-#include "clock.h"
-#include "sdrc.h"
-#include "sram.h"
-
-/* Memory timing, DLL mode flags */
-#define M_DDR 1
-#define M_LOCK_CTRL (1 << 2)
-#define M_UNLOCK 0
-#define M_LOCK 1
-
-
-static struct memory_timings mem_timings;
-static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
-
-static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
-{
- return mem_timings.slow_dll_ctrl;
-}
-
-static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
-{
- return mem_timings.fast_dll_ctrl;
-}
-
-static u32 omap2xxx_sdrc_get_type(void)
-{
- return mem_timings.m_type;
-}
-
-/*
- * Check the DLL lock state, and return tue if running in unlock mode.
- * This is needed to compensate for the shifted DLL value in unlock mode.
- */
-u32 omap2xxx_sdrc_dll_is_unlocked(void)
-{
- /* dlla and dllb are a set */
- u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
-
- if ((dll_state & (1 << 2)) == (1 << 2))
- return 1;
- else
- return 0;
-}
-
-/*
- * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
- * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
- * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
- *
- * Used by the clock framework during CORE DPLL changes
- */
-u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
-{
- u32 dll_ctrl, m_type;
- u32 prev = curr_perf_level;
- unsigned long flags;
-
- if ((curr_perf_level == level) && !force)
- return prev;
-
- if (level == CORE_CLK_SRC_DPLL)
- dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
- else if (level == CORE_CLK_SRC_DPLL_X2)
- dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
- else
- return prev;
-
- m_type = omap2xxx_sdrc_get_type();
-
- local_irq_save(flags);
- /*
- * XXX These calls should be abstracted out through a
- * prm2xxx.c function
- */
- if (cpu_is_omap2420())
- writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP);
- else
- writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP);
- omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
- curr_perf_level = level;
- local_irq_restore(flags);
-
- return prev;
-}
-
-/* Used by the clock framework during CORE DPLL changes */
-void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
-{
- unsigned long dll_cnt;
- u32 fast_dll = 0;
-
- /* DDR = 1, SDR = 0 */
- mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
-
- /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
- * In the case of 2422, its ok to use CS1 instead of CS0.
- */
- if (cpu_is_omap2422())
- mem_timings.base_cs = 1;
- else
- mem_timings.base_cs = 0;
-
- if (mem_timings.m_type != M_DDR)
- return;
-
- /* With DDR we need to determine the low frequency DLL value */
- if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
- mem_timings.dll_mode = M_UNLOCK;
- else
- mem_timings.dll_mode = M_LOCK;
-
- if (mem_timings.base_cs == 0) {
- fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
- dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
- } else {
- fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
- dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
- }
- if (force_lock_to_unlock_mode) {
- fast_dll &= ~0xff00;
- fast_dll |= dll_cnt; /* Current lock mode */
- }
- /* set fast timings with DLL filter disabled */
- mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
-
- /* No disruptions, DDR will be offline & C-ABI not followed */
- omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
- mem_timings.fast_dll_ctrl,
- mem_timings.base_cs,
- force_lock_to_unlock_mode);
- mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
-
- /* Turn status into unlock ctrl */
- mem_timings.slow_dll_ctrl |=
- ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
-
- /* 90 degree phase for anything below 133MHz + disable DLL filter */
- mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
-}
diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S
deleted file mode 100644
index 84d8c43ad382..000000000000
--- a/arch/arm/mach-omap2/sleep24xx.S
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * linux/arch/arm/mach-omap2/sleep.S
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * (C) Copyright 2006 Nokia Corporation
- * Fixed idle loop sleep
- * Igor Stoppa <igor.stoppa@nokia.com>
- */
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-
-#include "omap24xx.h"
-#include "sdrc.h"
-
-/* First address of reserved address space? apparently valid for OMAP2 & 3 */
-#define A_SDRC0_V (0xC0000000)
-
- .text
-
-/*
- * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
- * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore
- * SDRC.
- *
- * Input:
- * R0 : DLL ctrl value pre-Sleep
- * R1 : SDRC_DLLA_CTRL
- * R2 : SDRC_POWER
- *
- * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
- * when we get called, but the DLL probably isn't. We will wait a bit more in
- * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
- * if in unlocked mode.
- *
- * For less than 242x-ES2.2 upon wake from a sleep mode where the external
- * oscillator was stopped, a timing bug exists where a non-stabilized 12MHz
- * clock can pass into the PRCM can cause problems at DSP and IVA.
- * To work around this the code will switch to the 32kHz source prior to sleep.
- * Post sleep we will shift back to using the DPLL. Apparently,
- * CM_IDLEST_CLKGEN does not reflect the full clock change so you need to wait
- * 3x12MHz + 3x32kHz clocks for a full switch.
- *
- * The DLL load value is not kept in RETENTION or OFF. It needs to be restored
- * at wake
- */
- .align 3
-ENTRY(omap24xx_cpu_suspend)
- stmfd sp!, {r0 - r12, lr} @ save registers on stack
- mov r3, #0x0 @ clear for mcr call
- mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
- nop
- nop
- ldr r4, [r2] @ read SDRC_POWER
- orr r4, r4, #0x40 @ enable self refresh on idle req
- mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
- str r4, [r2] @ make it so
- nop
- mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt
- nop
-loop:
- subs r5, r5, #0x1 @ awake, wait just a bit
- bne loop
-
- /* The DPLL has to be on before we take the DDR out of self refresh */
- bic r4, r4, #0x40 @ now clear self refresh bit.
- str r4, [r2] @ write to SDRC_POWER
- ldr r4, A_SDRC0 @ make a clock happen
- ldr r4, [r4] @ read A_SDRC0
- nop @ start auto refresh only after clk ok
- movs r0, r0 @ see if DDR or SDR
- strne r0, [r1] @ rewrite DLLA to force DLL reload
- addne r1, r1, #0x8 @ move to DLLB
- strne r0, [r1] @ rewrite DLLB to force DLL reload
-
- mov r5, #0x1000
-loop2:
- subs r5, r5, #0x1
- bne loop2
- /* resume*/
- ldmfd sp!, {r0 - r12, pc} @ restore regs and return
-
-A_SDRC0:
- .word A_SDRC0_V
-
-ENTRY(omap24xx_cpu_suspend_sz)
- .word . - omap24xx_cpu_suspend
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 9e3dbb743e5c..9c9f56ca9142 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -12,7 +12,6 @@
* Added DRA7xxx specific defines - Sricharan R<r.sricharan@ti.com>
*/
-#include "omap24xx.h"
#include "omap34xx.h"
#include "omap44xx.h"
#include "ti81xx.h"
@@ -62,9 +61,6 @@ static inline int soc_is_omap(void)
/*
* Macros to group OMAP into cpu classes.
* These can be used in most places.
- * soc_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
- * soc_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
- * soc_is_omap243x(): True for OMAP2430
* soc_is_omap343x(): True for OMAP3430
* soc_is_omap443x(): True for OMAP4430
* soc_is_omap446x(): True for OMAP4460
@@ -137,7 +133,6 @@ static inline int is_dra ##subclass ##_ ##package (void) \
return (is_dra ##subclass () && GET_DRA_PACKAGE == id) ? 1 : 0; \
}
-IS_OMAP_CLASS(24xx, 0x24)
IS_OMAP_CLASS(34xx, 0x34)
IS_OMAP_CLASS(44xx, 0x44)
IS_AM_CLASS(35xx, 0x35)
@@ -148,8 +143,6 @@ IS_AM_CLASS(43xx, 0x43)
IS_TI_CLASS(81xx, 0x81)
IS_DRA_CLASS(7xx, 0x7)
-IS_OMAP_SUBCLASS(242x, 0x242)
-IS_OMAP_SUBCLASS(243x, 0x243)
IS_OMAP_SUBCLASS(343x, 0x343)
IS_OMAP_SUBCLASS(363x, 0x363)
IS_OMAP_SUBCLASS(443x, 0x443)
@@ -186,21 +179,6 @@ IS_DRA_SUBCLASS(72x, 0x72)
#define soc_is_dra74x() 0
#define soc_is_dra72x() 0
-#if defined(CONFIG_ARCH_OMAP2)
-# define soc_is_omap24xx() is_omap24xx()
-#else
-# define soc_is_omap24xx() 0
-#endif
-#if defined(CONFIG_SOC_OMAP2420)
-# define soc_is_omap242x() is_omap242x()
-#else
-# define soc_is_omap242x() 0
-#endif
-#if defined(CONFIG_SOC_OMAP2430)
-# define soc_is_omap243x() is_omap243x()
-#else
-# define soc_is_omap243x() 0
-#endif
#if defined(CONFIG_ARCH_OMAP3)
# define soc_is_omap34xx() is_omap34xx()
# define soc_is_omap343x() is_omap343x()
@@ -212,10 +190,6 @@ IS_DRA_SUBCLASS(72x, 0x72)
/*
* Macros to detect individual cpu types.
* These are only rarely needed.
- * soc_is_omap2420(): True for OMAP2420
- * soc_is_omap2422(): True for OMAP2422
- * soc_is_omap2423(): True for OMAP2423
- * soc_is_omap2430(): True for OMAP2430
* soc_is_omap3430(): True for OMAP3430
*/
#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
@@ -226,16 +200,8 @@ static inline int is_omap ##type (void) \
return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
}
-IS_OMAP_TYPE(2420, 0x2420)
-IS_OMAP_TYPE(2422, 0x2422)
-IS_OMAP_TYPE(2423, 0x2423)
-IS_OMAP_TYPE(2430, 0x2430)
IS_OMAP_TYPE(3430, 0x3430)
-#define soc_is_omap2420() 0
-#define soc_is_omap2422() 0
-#define soc_is_omap2423() 0
-#define soc_is_omap2430() 0
#define soc_is_omap3430() 0
#define soc_is_omap3630() 0
#define soc_is_omap5430() 0
@@ -252,17 +218,6 @@ IS_OMAP_TYPE(3430, 0x3430)
#define cpu_class_is_omap1() 0
#define cpu_class_is_omap2() 1
-#if defined(CONFIG_ARCH_OMAP2)
-# undef soc_is_omap2420
-# undef soc_is_omap2422
-# undef soc_is_omap2423
-# undef soc_is_omap2430
-# define soc_is_omap2420() is_omap2420()
-# define soc_is_omap2422() is_omap2422()
-# define soc_is_omap2423() is_omap2423()
-# define soc_is_omap2430() is_omap2430()
-#endif
-
#if defined(CONFIG_ARCH_OMAP3)
# undef soc_is_omap3430
# undef soc_is_ti81xx
@@ -326,13 +281,6 @@ IS_OMAP_TYPE(3430, 0x3430)
#endif
/* Various silicon revisions for omap2 */
-#define OMAP242X_CLASS 0x24200024
-#define OMAP2420_REV_ES1_0 OMAP242X_CLASS
-#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (0x1 << 8))
-
-#define OMAP243X_CLASS 0x24300024
-#define OMAP2430_REV_ES1_0 OMAP243X_CLASS
-
#define OMAP343X_CLASS 0x34300034
#define OMAP3430_REV_ES1_0 OMAP343X_CLASS
#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (0x1 << 8))
@@ -400,7 +348,6 @@ IS_OMAP_TYPE(3430, 0x3430)
#define DRA722_REV_ES2_0 (DRA7XX_CLASS | (0x22 << 16) | (0x20 << 8))
#define DRA722_REV_ES2_1 (DRA7XX_CLASS | (0x22 << 16) | (0x21 << 8))
-void omap2xxx_check_revision(void);
void omap3xxx_check_revision(void);
void omap4xxx_check_revision(void);
void omap5xxx_check_revision(void);
@@ -484,12 +431,6 @@ level(__##fn);
#define omap_late_initcall_sync(fn) omap_initcall(late_initcall_sync, fn)
/* Legacy defines, these can be removed when users are removed */
-#define cpu_is_omap2420() soc_is_omap2420()
-#define cpu_is_omap2422() soc_is_omap2422()
-#define cpu_is_omap242x() soc_is_omap242x()
-#define cpu_is_omap2430() soc_is_omap2430()
-#define cpu_is_omap243x() soc_is_omap243x()
-#define cpu_is_omap24xx() soc_is_omap24xx()
#define cpu_is_omap3430() soc_is_omap3430()
#define cpu_is_omap343x() soc_is_omap343x()
#define cpu_is_omap34xx() soc_is_omap34xx()
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index 898b011ae8d9..8f980849f201 100644
--- a/arch/arm/mach-omap2/sram.c
+++ b/arch/arm/mach-omap2/sram.c
@@ -28,15 +28,10 @@
#include "sdrc.h"
#include "sram.h"
-#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
#define SRAM_BOOTLOADER_SZ 0x00
-#define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
-#define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
-#define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
-
#define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
#define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
#define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
@@ -120,18 +115,11 @@ static int is_sram_locked(void)
{
if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
/* RAMFW: R/W access to all initiators for all qualifier sets */
- if (cpu_is_omap242x()) {
- writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
- writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
- writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
- }
- if (cpu_is_omap34xx()) {
- writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
- writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
- writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
- writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
- writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
- }
+ writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
+ writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
+ writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
+ writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
+ writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
return 0;
} else
return 1; /* assume locked with no PPA or security driver */
@@ -147,30 +135,17 @@ static void __init omap_detect_sram(void)
{
omap_sram_skip = SRAM_BOOTLOADER_SZ;
if (is_sram_locked()) {
- if (cpu_is_omap34xx()) {
- omap_sram_start = OMAP3_SRAM_PUB_PA;
- if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
- (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
- omap_sram_size = 0x7000; /* 28K */
- omap_sram_skip += SZ_16K;
- } else {
- omap_sram_size = 0x8000; /* 32K */
- }
+ omap_sram_start = OMAP3_SRAM_PUB_PA;
+ if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
+ (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
+ omap_sram_size = 0x7000; /* 28K */
+ omap_sram_skip += SZ_16K;
} else {
- omap_sram_start = OMAP2_SRAM_PUB_PA;
- omap_sram_size = 0x800; /* 2K */
+ omap_sram_size = 0x8000; /* 32K */
}
} else {
- if (cpu_is_omap34xx()) {
- omap_sram_start = OMAP3_SRAM_PA;
- omap_sram_size = 0x10000; /* 64K */
- } else {
- omap_sram_start = OMAP2_SRAM_PA;
- if (cpu_is_omap242x())
- omap_sram_size = 0xa0000; /* 640K */
- else if (cpu_is_omap243x())
- omap_sram_size = 0x10000; /* 64K */
- }
+ omap_sram_start = OMAP3_SRAM_PA;
+ omap_sram_size = 0x10000; /* 64K */
}
}
@@ -181,24 +156,20 @@ static void __init omap2_map_sram(void)
{
unsigned long base;
int pages;
- int cached = 1;
-
- if (cpu_is_omap34xx()) {
- /*
- * SRAM must be marked as non-cached on OMAP3 since the
- * CORE DPLL M2 divider change code (in SRAM) runs with the
- * SDRAM controller disabled, and if it is marked cached,
- * the ARM may attempt to write cache lines back to SDRAM
- * which will cause the system to hang.
- */
- cached = 0;
- }
if (omap_sram_size == 0)
return;
omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
- omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size, cached);
+ /*
+ * SRAM must be marked as non-cached on OMAP3 since the
+ * CORE DPLL M2 divider change code (in SRAM) runs with the
+ * SDRAM controller disabled, and if it is marked cached,
+ * the ARM may attempt to write cache lines back to SDRAM
+ * which will cause the system to hang.
+ */
+
+ omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size, 0);
if (!omap_sram_base) {
pr_err("SRAM: Could not map\n");
return;
@@ -219,78 +190,6 @@ static void __init omap2_map_sram(void)
set_memory_rox(base, pages);
}
-static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
- u32 base_cs, u32 force_unlock);
-
-void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
- u32 base_cs, u32 force_unlock)
-{
- BUG_ON(!_omap2_sram_ddr_init);
- _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
- base_cs, force_unlock);
-}
-
-static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
- u32 mem_type);
-
-void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
-{
- BUG_ON(!_omap2_sram_reprogram_sdrc);
- _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
-}
-
-static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
-
-u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
-{
- BUG_ON(!_omap2_set_prcm);
- return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
-}
-
-#ifdef CONFIG_SOC_OMAP2420
-static int __init omap242x_sram_init(void)
-{
- _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
- omap242x_sram_ddr_init_sz);
-
- _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
- omap242x_sram_reprogram_sdrc_sz);
-
- _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
- omap242x_sram_set_prcm_sz);
-
- return 0;
-}
-#else
-static inline int omap242x_sram_init(void)
-{
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SOC_OMAP2430
-static int __init omap243x_sram_init(void)
-{
- _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
- omap243x_sram_ddr_init_sz);
-
- _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
- omap243x_sram_reprogram_sdrc_sz);
-
- _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
- omap243x_sram_set_prcm_sz);
-
- return 0;
-}
-#else
-static inline int omap243x_sram_init(void)
-{
- return 0;
-}
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-
void omap3_sram_restore_context(void)
{
omap_sram_reset();
@@ -303,24 +202,12 @@ static inline int omap34xx_sram_init(void)
omap3_sram_restore_context();
return 0;
}
-#else
-static inline int omap34xx_sram_init(void)
-{
- return 0;
-}
-#endif /* CONFIG_ARCH_OMAP3 */
int __init omap_sram_init(void)
{
omap_detect_sram();
omap2_map_sram();
-
- if (cpu_is_omap242x())
- omap242x_sram_init();
- else if (cpu_is_omap2430())
- omap243x_sram_init();
- else if (cpu_is_omap34xx())
- omap34xx_sram_init();
+ omap34xx_sram_init();
return 0;
}
diff --git a/arch/arm/mach-omap2/sram.h b/arch/arm/mach-omap2/sram.h
index 030cabc39821..2db2c4598cdb 100644
--- a/arch/arm/mach-omap2/sram.h
+++ b/arch/arm/mach-omap2/sram.h
@@ -5,43 +5,12 @@
#ifndef __ASSEMBLY__
-extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
- u32 base_cs, u32 force_unlock);
-extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
- u32 mem_type);
-extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
-
extern void omap3_sram_restore_context(void);
extern int __init omap_sram_init(void);
extern void *omap_sram_push(void *funcp, unsigned long size);
-extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
- u32 base_cs, u32 force_unlock);
-extern unsigned long omap242x_sram_ddr_init_sz;
-
-extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
- int bypass);
-extern unsigned long omap242x_sram_set_prcm_sz;
-
-extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
- u32 mem_type);
-extern unsigned long omap242x_sram_reprogram_sdrc_sz;
-
-
-extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
- u32 base_cs, u32 force_unlock);
-extern unsigned long omap243x_sram_ddr_init_sz;
-
-extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
- int bypass);
-extern unsigned long omap243x_sram_set_prcm_sz;
-
-extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
- u32 mem_type);
-extern unsigned long omap243x_sram_reprogram_sdrc_sz;
-
#ifdef CONFIG_PM
extern void omap_push_sram_idle(void);
#else
@@ -54,5 +23,4 @@ static inline void omap_push_sram_idle(void) {}
* OMAP2+: define the SRAM PA addresses.
* Used by the SRAM management code and the idle sleep code.
*/
-#define OMAP2_SRAM_PA 0x40200000
#define OMAP3_SRAM_PA 0x40200000
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
deleted file mode 100644
index 92ef21ac2ac1..000000000000
--- a/arch/arm/mach-omap2/sram242x.S
+++ /dev/null
@@ -1,317 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * linux/arch/arm/mach-omap2/sram242x.S
- *
- * Omap2 specific functions that need to be run in internal SRAM
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * Richard Woodruff notes that any changes to this code must be carefully
- * audited and tested to ensure that they don't cause a TLB miss while
- * the SDRAM is inaccessible. Such a situation will crash the system
- * since it will cause the ARM MMU to attempt to walk the page tables.
- * These crashes may be intermittent.
- */
-#include <linux/linkage.h>
-
-#include <asm/assembler.h>
-
-#include "soc.h"
-#include "iomap.h"
-#include "prm2xxx.h"
-#include "cm2xxx.h"
-#include "sdrc.h"
-
- .text
-
- .align 3
-ENTRY(omap242x_sram_ddr_init)
- stmfd sp!, {r0 - r12, lr} @ save registers on stack
-
- mov r12, r2 @ capture CS1 vs CS0
- mov r8, r3 @ capture force parameter
-
- /* frequency shift down */
- ldr r2, omap242x_sdi_cm_clksel2_pll @ get address of dpllout reg
- mov r3, #0x1 @ value for 1x operation
- str r3, [r2] @ go to L1-freq operation
-
- /* voltage shift down */
- mov r9, #0x1 @ set up for L1 voltage call
- bl voltage_shift @ go drop voltage
-
- /* dll lock mode */
- ldr r11, omap242x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
- ldr r10, [r11] @ get current val
- cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
- addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
- mvn r9, #0x4 @ mask to get clear bit2
- and r10, r10, r9 @ clear bit2 for lock mode.
- orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
- orr r10, r10, #0x2 @ 90 degree phase for all below 133MHz
- str r10, [r11] @ commit to DLLA_CTRL
- bl i_dll_wait @ wait for dll to lock
-
- /* get dll value */
- add r11, r11, #0x4 @ get addr of status reg
- ldr r10, [r11] @ get locked value
-
- /* voltage shift up */
- mov r9, #0x0 @ shift back to L0-voltage
- bl voltage_shift @ go raise voltage
-
- /* frequency shift up */
- mov r3, #0x2 @ value for 2x operation
- str r3, [r2] @ go to L0-freq operation
-
- /* reset entry mode for dllctrl */
- sub r11, r11, #0x4 @ move from status to ctrl
- cmp r12, #0x1 @ normalize if cs1 based
- subeq r11, r11, #0x8 @ possibly back to DLLA
- cmp r8, #0x1 @ if forced unlock exit
- orreq r1, r1, #0x4 @ make sure exit with unlocked value
- str r1, [r11] @ restore DLLA_CTRL high value
- add r11, r11, #0x8 @ move to DLLB_CTRL addr
- str r1, [r11] @ set value DLLB_CTRL
- bl i_dll_wait @ wait for possible lock
-
- /* set up for return, DDR should be good */
- str r10, [r0] @ write dll_status and return counter
- ldmfd sp!, {r0 - r12, pc} @ restore regs and return
-
- /* ensure the DLL has relocked */
-i_dll_wait:
- mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
-i_dll_delay:
- subs r4, r4, #0x1
- bne i_dll_delay
- ret lr
-
- /*
- * shift up or down voltage, use R9 as input to tell level.
- * wait for it to finish, use 32k sync counter, 1tick=31uS.
- */
-voltage_shift:
- ldr r4, omap242x_sdi_prcm_voltctrl @ get addr of volt ctrl.
- ldr r5, [r4] @ get value.
- ldr r6, prcm_mask_val @ get value of mask
- and r5, r5, r6 @ apply mask to clear bits
- orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
- str r5, [r4] @ set up for change.
- mov r3, #0x4000 @ get val for force
- orr r5, r5, r3 @ build value for force
- str r5, [r4] @ Force transition to L1
-
- ldr r3, omap242x_sdi_timer_32ksynct_cr @ get addr of counter
- ldr r5, [r3] @ get value
- add r5, r5, #0x3 @ give it at most 93uS
-volt_delay:
- ldr r7, [r3] @ get timer value
- cmp r5, r7 @ time up?
- bhi volt_delay @ not yet->branch
- ret lr @ back to caller.
-
-omap242x_sdi_cm_clksel2_pll:
- .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
-omap242x_sdi_sdrc_dlla_ctrl:
- .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-omap242x_sdi_prcm_voltctrl:
- .word OMAP2420_PRCM_VOLTCTRL
-prcm_mask_val:
- .word 0xFFFF3FFC
-omap242x_sdi_timer_32ksynct_cr:
- .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
-ENTRY(omap242x_sram_ddr_init_sz)
- .word . - omap242x_sram_ddr_init
-
-/*
- * Reprograms memory timings.
- * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
- * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
- */
- .align 3
-ENTRY(omap242x_sram_reprogram_sdrc)
- stmfd sp!, {r0 - r10, lr} @ save registers on stack
- mov r3, #0x0 @ clear for mrc call
- mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
- nop
- nop
- ldr r6, omap242x_srs_sdrc_rfr_ctrl @ get addr of refresh reg
- ldr r5, [r6] @ get value
- mov r5, r5, lsr #8 @ isolate rfr field and drop burst
-
- cmp r0, #0x1 @ going to half speed?
- movne r9, #0x0 @ if up set flag up for pre up, hi volt
-
- blne voltage_shift_c @ adjust voltage
-
- cmp r0, #0x1 @ going to half speed (post branch link)
- moveq r5, r5, lsr #1 @ divide by 2 if to half
- movne r5, r5, lsl #1 @ mult by 2 if to full
- mov r5, r5, lsl #8 @ put rfr field back into place
- add r5, r5, #0x1 @ turn on burst of 1
- ldr r4, omap242x_srs_cm_clksel2_pll @ get address of out reg
- ldr r3, [r4] @ get curr value
- orr r3, r3, #0x3
- bic r3, r3, #0x3 @ clear lower bits
- orr r3, r3, r0 @ new state value
- str r3, [r4] @ set new state (pll/x, x=1 or 2)
- nop
- nop
-
- moveq r9, #0x1 @ if speed down, post down, drop volt
- bleq voltage_shift_c
-
- mcr p15, 0, r3, c7, c10, 4 @ memory barrier
- str r5, [r6] @ set new RFR_1 value
- add r6, r6, #0x30 @ get RFR_2 addr
- str r5, [r6] @ set RFR_2
- nop
- cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
- bne freq_out @ leave if SDR, no DLL function
-
- /* With DDR, we need to take care of the DLL for the frequency change */
- ldr r2, omap242x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
- str r1, [r2] @ write out new SDRC_DLLA_CTRL
- add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
- str r1, [r2] @ commit to SDRC_DLLB_CTRL
- mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
-dll_wait:
- subs r1, r1, #0x1
- bne dll_wait
-freq_out:
- ldmfd sp!, {r0 - r10, pc} @ restore regs and return
-
- /*
- * shift up or down voltage, use R9 as input to tell level.
- * wait for it to finish, use 32k sync counter, 1tick=31uS.
- */
-voltage_shift_c:
- ldr r10, omap242x_srs_prcm_voltctrl @ get addr of volt ctrl
- ldr r8, [r10] @ get value
- ldr r7, ddr_prcm_mask_val @ get value of mask
- and r8, r8, r7 @ apply mask to clear bits
- orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
- str r8, [r10] @ set up for change.
- mov r7, #0x4000 @ get val for force
- orr r8, r8, r7 @ build value for force
- str r8, [r10] @ Force transition to L1
-
- ldr r10, omap242x_srs_timer_32ksynct @ get addr of counter
- ldr r8, [r10] @ get value
- add r8, r8, #0x2 @ give it at most 62uS (min 31+)
-volt_delay_c:
- ldr r7, [r10] @ get timer value
- cmp r8, r7 @ time up?
- bhi volt_delay_c @ not yet->branch
- ret lr @ back to caller
-
-omap242x_srs_cm_clksel2_pll:
- .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
-omap242x_srs_sdrc_dlla_ctrl:
- .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-omap242x_srs_sdrc_rfr_ctrl:
- .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-omap242x_srs_prcm_voltctrl:
- .word OMAP2420_PRCM_VOLTCTRL
-ddr_prcm_mask_val:
- .word 0xFFFF3FFC
-omap242x_srs_timer_32ksynct:
- .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
-
-ENTRY(omap242x_sram_reprogram_sdrc_sz)
- .word . - omap242x_sram_reprogram_sdrc
-
-/*
- * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
- */
- .align 3
-ENTRY(omap242x_sram_set_prcm)
- stmfd sp!, {r0-r12, lr} @ regs to stack
- adr r4, pbegin @ addr of preload start
- adr r8, pend @ addr of preload end
- mcrr p15, 1, r8, r4, c12 @ preload into icache
-pbegin:
- /* move into fast relock bypass */
- ldr r8, omap242x_ssp_pll_ctl @ get addr
- ldr r5, [r8] @ get val
- mvn r6, #0x3 @ clear mask
- and r5, r5, r6 @ clear field
- orr r7, r5, #0x2 @ fast relock val
- str r7, [r8] @ go to fast relock
- ldr r4, omap242x_ssp_pll_stat @ addr of stat
-block:
- /* wait for bypass */
- ldr r8, [r4] @ stat value
- and r8, r8, #0x3 @ mask for stat
- cmp r8, #0x1 @ there yet
- bne block @ loop if not
-
- /* set new dpll dividers _after_ in bypass */
- ldr r4, omap242x_ssp_pll_div @ get addr
- str r0, [r4] @ set dpll ctrl val
-
- ldr r4, omap242x_ssp_set_config @ get addr
- mov r8, #1 @ valid cfg msk
- str r8, [r4] @ make dividers take
-
- mov r4, #100 @ dead spin a bit
-wait_a_bit:
- subs r4, r4, #1 @ dec loop
- bne wait_a_bit @ delay done?
-
- /* check if staying in bypass */
- cmp r2, #0x1 @ stay in bypass?
- beq pend @ jump over dpll relock
-
- /* relock DPLL with new vals */
- ldr r5, omap242x_ssp_pll_stat @ get addr
- ldr r4, omap242x_ssp_pll_ctl @ get addr
- orr r8, r7, #0x3 @ val for lock dpll
- str r8, [r4] @ set val
- mov r0, #1000 @ dead spin a bit
-wait_more:
- subs r0, r0, #1 @ dec loop
- bne wait_more @ delay done?
-wait_lock:
- ldr r8, [r5] @ get lock val
- and r8, r8, #3 @ isolate field
- cmp r8, #2 @ locked?
- bne wait_lock @ wait if not
-pend:
- /* update memory timings & briefly lock dll */
- ldr r4, omap242x_ssp_sdrc_rfr @ get addr
- str r1, [r4] @ update refresh timing
- ldr r11, omap242x_ssp_dlla_ctrl @ get addr of DLLA ctrl
- ldr r10, [r11] @ get current val
- mvn r9, #0x4 @ mask to get clear bit2
- and r10, r10, r9 @ clear bit2 for lock mode
- orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
- str r10, [r11] @ commit to DLLA_CTRL
- add r11, r11, #0x8 @ move to dllb
- str r10, [r11] @ hit DLLB also
-
- mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
-wait_dll_lock:
- subs r4, r4, #0x1
- bne wait_dll_lock
- nop
- ldmfd sp!, {r0-r12, pc} @ restore regs and return
-
-omap242x_ssp_set_config:
- .word OMAP2420_PRCM_CLKCFG_CTRL
-omap242x_ssp_pll_ctl:
- .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
-omap242x_ssp_pll_stat:
- .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST)
-omap242x_ssp_pll_div:
- .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
-omap242x_ssp_sdrc_rfr:
- .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-omap242x_ssp_dlla_ctrl:
- .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-
-ENTRY(omap242x_sram_set_prcm_sz)
- .word . - omap242x_sram_set_prcm
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
deleted file mode 100644
index faf03b7f08f5..000000000000
--- a/arch/arm/mach-omap2/sram243x.S
+++ /dev/null
@@ -1,317 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * linux/arch/arm/mach-omap2/sram243x.S
- *
- * Omap2 specific functions that need to be run in internal SRAM
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * Richard Woodruff notes that any changes to this code must be carefully
- * audited and tested to ensure that they don't cause a TLB miss while
- * the SDRAM is inaccessible. Such a situation will crash the system
- * since it will cause the ARM MMU to attempt to walk the page tables.
- * These crashes may be intermittent.
- */
-#include <linux/linkage.h>
-
-#include <asm/assembler.h>
-
-#include "soc.h"
-#include "iomap.h"
-#include "prm2xxx.h"
-#include "cm2xxx.h"
-#include "sdrc.h"
-
- .text
-
- .align 3
-ENTRY(omap243x_sram_ddr_init)
- stmfd sp!, {r0 - r12, lr} @ save registers on stack
-
- mov r12, r2 @ capture CS1 vs CS0
- mov r8, r3 @ capture force parameter
-
- /* frequency shift down */
- ldr r2, omap243x_sdi_cm_clksel2_pll @ get address of dpllout reg
- mov r3, #0x1 @ value for 1x operation
- str r3, [r2] @ go to L1-freq operation
-
- /* voltage shift down */
- mov r9, #0x1 @ set up for L1 voltage call
- bl voltage_shift @ go drop voltage
-
- /* dll lock mode */
- ldr r11, omap243x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
- ldr r10, [r11] @ get current val
- cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
- addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
- mvn r9, #0x4 @ mask to get clear bit2
- and r10, r10, r9 @ clear bit2 for lock mode.
- orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
- orr r10, r10, #0x2 @ 90 degree phase for all below 133MHz
- str r10, [r11] @ commit to DLLA_CTRL
- bl i_dll_wait @ wait for dll to lock
-
- /* get dll value */
- add r11, r11, #0x4 @ get addr of status reg
- ldr r10, [r11] @ get locked value
-
- /* voltage shift up */
- mov r9, #0x0 @ shift back to L0-voltage
- bl voltage_shift @ go raise voltage
-
- /* frequency shift up */
- mov r3, #0x2 @ value for 2x operation
- str r3, [r2] @ go to L0-freq operation
-
- /* reset entry mode for dllctrl */
- sub r11, r11, #0x4 @ move from status to ctrl
- cmp r12, #0x1 @ normalize if cs1 based
- subeq r11, r11, #0x8 @ possibly back to DLLA
- cmp r8, #0x1 @ if forced unlock exit
- orreq r1, r1, #0x4 @ make sure exit with unlocked value
- str r1, [r11] @ restore DLLA_CTRL high value
- add r11, r11, #0x8 @ move to DLLB_CTRL addr
- str r1, [r11] @ set value DLLB_CTRL
- bl i_dll_wait @ wait for possible lock
-
- /* set up for return, DDR should be good */
- str r10, [r0] @ write dll_status and return counter
- ldmfd sp!, {r0 - r12, pc} @ restore regs and return
-
- /* ensure the DLL has relocked */
-i_dll_wait:
- mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
-i_dll_delay:
- subs r4, r4, #0x1
- bne i_dll_delay
- ret lr
-
- /*
- * shift up or down voltage, use R9 as input to tell level.
- * wait for it to finish, use 32k sync counter, 1tick=31uS.
- */
-voltage_shift:
- ldr r4, omap243x_sdi_prcm_voltctrl @ get addr of volt ctrl.
- ldr r5, [r4] @ get value.
- ldr r6, prcm_mask_val @ get value of mask
- and r5, r5, r6 @ apply mask to clear bits
- orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
- str r5, [r4] @ set up for change.
- mov r3, #0x4000 @ get val for force
- orr r5, r5, r3 @ build value for force
- str r5, [r4] @ Force transition to L1
-
- ldr r3, omap243x_sdi_timer_32ksynct_cr @ get addr of counter
- ldr r5, [r3] @ get value
- add r5, r5, #0x3 @ give it at most 93uS
-volt_delay:
- ldr r7, [r3] @ get timer value
- cmp r5, r7 @ time up?
- bhi volt_delay @ not yet->branch
- ret lr @ back to caller.
-
-omap243x_sdi_cm_clksel2_pll:
- .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
-omap243x_sdi_sdrc_dlla_ctrl:
- .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-omap243x_sdi_prcm_voltctrl:
- .word OMAP2430_PRCM_VOLTCTRL
-prcm_mask_val:
- .word 0xFFFF3FFC
-omap243x_sdi_timer_32ksynct_cr:
- .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
-ENTRY(omap243x_sram_ddr_init_sz)
- .word . - omap243x_sram_ddr_init
-
-/*
- * Reprograms memory timings.
- * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
- * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
- */
- .align 3
-ENTRY(omap243x_sram_reprogram_sdrc)
- stmfd sp!, {r0 - r10, lr} @ save registers on stack
- mov r3, #0x0 @ clear for mrc call
- mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
- nop
- nop
- ldr r6, omap243x_srs_sdrc_rfr_ctrl @ get addr of refresh reg
- ldr r5, [r6] @ get value
- mov r5, r5, lsr #8 @ isolate rfr field and drop burst
-
- cmp r0, #0x1 @ going to half speed?
- movne r9, #0x0 @ if up set flag up for pre up, hi volt
-
- blne voltage_shift_c @ adjust voltage
-
- cmp r0, #0x1 @ going to half speed (post branch link)
- moveq r5, r5, lsr #1 @ divide by 2 if to half
- movne r5, r5, lsl #1 @ mult by 2 if to full
- mov r5, r5, lsl #8 @ put rfr field back into place
- add r5, r5, #0x1 @ turn on burst of 1
- ldr r4, omap243x_srs_cm_clksel2_pll @ get address of out reg
- ldr r3, [r4] @ get curr value
- orr r3, r3, #0x3
- bic r3, r3, #0x3 @ clear lower bits
- orr r3, r3, r0 @ new state value
- str r3, [r4] @ set new state (pll/x, x=1 or 2)
- nop
- nop
-
- moveq r9, #0x1 @ if speed down, post down, drop volt
- bleq voltage_shift_c
-
- mcr p15, 0, r3, c7, c10, 4 @ memory barrier
- str r5, [r6] @ set new RFR_1 value
- add r6, r6, #0x30 @ get RFR_2 addr
- str r5, [r6] @ set RFR_2
- nop
- cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
- bne freq_out @ leave if SDR, no DLL function
-
- /* With DDR, we need to take care of the DLL for the frequency change */
- ldr r2, omap243x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
- str r1, [r2] @ write out new SDRC_DLLA_CTRL
- add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
- str r1, [r2] @ commit to SDRC_DLLB_CTRL
- mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
-dll_wait:
- subs r1, r1, #0x1
- bne dll_wait
-freq_out:
- ldmfd sp!, {r0 - r10, pc} @ restore regs and return
-
- /*
- * shift up or down voltage, use R9 as input to tell level.
- * wait for it to finish, use 32k sync counter, 1tick=31uS.
- */
-voltage_shift_c:
- ldr r10, omap243x_srs_prcm_voltctrl @ get addr of volt ctrl
- ldr r8, [r10] @ get value
- ldr r7, ddr_prcm_mask_val @ get value of mask
- and r8, r8, r7 @ apply mask to clear bits
- orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
- str r8, [r10] @ set up for change.
- mov r7, #0x4000 @ get val for force
- orr r8, r8, r7 @ build value for force
- str r8, [r10] @ Force transition to L1
-
- ldr r10, omap243x_srs_timer_32ksynct @ get addr of counter
- ldr r8, [r10] @ get value
- add r8, r8, #0x2 @ give it at most 62uS (min 31+)
-volt_delay_c:
- ldr r7, [r10] @ get timer value
- cmp r8, r7 @ time up?
- bhi volt_delay_c @ not yet->branch
- ret lr @ back to caller
-
-omap243x_srs_cm_clksel2_pll:
- .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
-omap243x_srs_sdrc_dlla_ctrl:
- .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-omap243x_srs_sdrc_rfr_ctrl:
- .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-omap243x_srs_prcm_voltctrl:
- .word OMAP2430_PRCM_VOLTCTRL
-ddr_prcm_mask_val:
- .word 0xFFFF3FFC
-omap243x_srs_timer_32ksynct:
- .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
-
-ENTRY(omap243x_sram_reprogram_sdrc_sz)
- .word . - omap243x_sram_reprogram_sdrc
-
-/*
- * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
- */
- .align 3
-ENTRY(omap243x_sram_set_prcm)
- stmfd sp!, {r0-r12, lr} @ regs to stack
- adr r4, pbegin @ addr of preload start
- adr r8, pend @ addr of preload end
- mcrr p15, 1, r8, r4, c12 @ preload into icache
-pbegin:
- /* move into fast relock bypass */
- ldr r8, omap243x_ssp_pll_ctl @ get addr
- ldr r5, [r8] @ get val
- mvn r6, #0x3 @ clear mask
- and r5, r5, r6 @ clear field
- orr r7, r5, #0x2 @ fast relock val
- str r7, [r8] @ go to fast relock
- ldr r4, omap243x_ssp_pll_stat @ addr of stat
-block:
- /* wait for bypass */
- ldr r8, [r4] @ stat value
- and r8, r8, #0x3 @ mask for stat
- cmp r8, #0x1 @ there yet
- bne block @ loop if not
-
- /* set new dpll dividers _after_ in bypass */
- ldr r4, omap243x_ssp_pll_div @ get addr
- str r0, [r4] @ set dpll ctrl val
-
- ldr r4, omap243x_ssp_set_config @ get addr
- mov r8, #1 @ valid cfg msk
- str r8, [r4] @ make dividers take
-
- mov r4, #100 @ dead spin a bit
-wait_a_bit:
- subs r4, r4, #1 @ dec loop
- bne wait_a_bit @ delay done?
-
- /* check if staying in bypass */
- cmp r2, #0x1 @ stay in bypass?
- beq pend @ jump over dpll relock
-
- /* relock DPLL with new vals */
- ldr r5, omap243x_ssp_pll_stat @ get addr
- ldr r4, omap243x_ssp_pll_ctl @ get addr
- orr r8, r7, #0x3 @ val for lock dpll
- str r8, [r4] @ set val
- mov r0, #1000 @ dead spin a bit
-wait_more:
- subs r0, r0, #1 @ dec loop
- bne wait_more @ delay done?
-wait_lock:
- ldr r8, [r5] @ get lock val
- and r8, r8, #3 @ isolate field
- cmp r8, #2 @ locked?
- bne wait_lock @ wait if not
-pend:
- /* update memory timings & briefly lock dll */
- ldr r4, omap243x_ssp_sdrc_rfr @ get addr
- str r1, [r4] @ update refresh timing
- ldr r11, omap243x_ssp_dlla_ctrl @ get addr of DLLA ctrl
- ldr r10, [r11] @ get current val
- mvn r9, #0x4 @ mask to get clear bit2
- and r10, r10, r9 @ clear bit2 for lock mode
- orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
- str r10, [r11] @ commit to DLLA_CTRL
- add r11, r11, #0x8 @ move to dllb
- str r10, [r11] @ hit DLLB also
-
- mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
-wait_dll_lock:
- subs r4, r4, #0x1
- bne wait_dll_lock
- nop
- ldmfd sp!, {r0-r12, pc} @ restore regs and return
-
-omap243x_ssp_set_config:
- .word OMAP2430_PRCM_CLKCFG_CTRL
-omap243x_ssp_pll_ctl:
- .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
-omap243x_ssp_pll_stat:
- .word OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST)
-omap243x_ssp_pll_div:
- .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
-omap243x_ssp_sdrc_rfr:
- .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-omap243x_ssp_dlla_ctrl:
- .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-
-ENTRY(omap243x_sram_set_prcm_sz)
- .word . - omap243x_sram_set_prcm
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
deleted file mode 100644
index b46c254c2bc4..000000000000
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ /dev/null
@@ -1,217 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap2/usb-tusb6010.c
- *
- * Copyright (C) 2006 Nokia Corporation
- */
-
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/export.h>
-#include <linux/platform_data/usb-omap.h>
-
-#include <linux/usb/musb.h>
-
-#include "usb-tusb6010.h"
-#include "gpmc.h"
-
-static u8 async_cs, sync_cs;
-static unsigned refclk_psec;
-
-static struct gpmc_settings tusb_async = {
- .wait_on_read = true,
- .wait_on_write = true,
- .device_width = GPMC_DEVWIDTH_16BIT,
- .mux_add_data = GPMC_MUX_AD,
-};
-
-static struct gpmc_settings tusb_sync = {
- .burst_read = true,
- .burst_write = true,
- .sync_read = true,
- .sync_write = true,
- .wait_on_read = true,
- .wait_on_write = true,
- .burst_len = GPMC_BURST_16,
- .device_width = GPMC_DEVWIDTH_16BIT,
- .mux_add_data = GPMC_MUX_AD,
-};
-
-/* NOTE: timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */
-
-static int tusb_set_async_mode(unsigned sysclk_ps)
-{
- struct gpmc_device_timings dev_t;
- struct gpmc_timings t;
- unsigned t_acsnh_advnh = sysclk_ps + 3000;
-
- memset(&dev_t, 0, sizeof(dev_t));
-
- dev_t.t_ceasu = 8 * 1000;
- dev_t.t_avdasu = t_acsnh_advnh - 7000;
- dev_t.t_ce_avd = 1000;
- dev_t.t_avdp_r = t_acsnh_advnh;
- dev_t.t_oeasu = t_acsnh_advnh + 1000;
- dev_t.t_oe = 300;
- dev_t.t_cez_r = 7000;
- dev_t.t_cez_w = dev_t.t_cez_r;
- dev_t.t_avdp_w = t_acsnh_advnh;
- dev_t.t_weasu = t_acsnh_advnh + 1000;
- dev_t.t_wpl = 300;
- dev_t.cyc_aavdh_we = 1;
-
- gpmc_calc_timings(&t, &tusb_async, &dev_t);
-
- return gpmc_cs_set_timings(async_cs, &t, &tusb_async);
-}
-
-static int tusb_set_sync_mode(unsigned sysclk_ps)
-{
- struct gpmc_device_timings dev_t;
- struct gpmc_timings t;
- unsigned t_scsnh_advnh = sysclk_ps + 3000;
-
- memset(&dev_t, 0, sizeof(dev_t));
-
- dev_t.clk = 11100;
- dev_t.t_bacc = 1000;
- dev_t.t_ces = 1000;
- dev_t.t_ceasu = 8 * 1000;
- dev_t.t_avdasu = t_scsnh_advnh - 7000;
- dev_t.t_ce_avd = 1000;
- dev_t.t_avdp_r = t_scsnh_advnh;
- dev_t.cyc_aavdh_oe = 3;
- dev_t.cyc_oe = 5;
- dev_t.t_ce_rdyz = 7000;
- dev_t.t_avdp_w = t_scsnh_advnh;
- dev_t.cyc_aavdh_we = 3;
- dev_t.cyc_wpl = 6;
-
- gpmc_calc_timings(&t, &tusb_sync, &dev_t);
-
- return gpmc_cs_set_timings(sync_cs, &t, &tusb_sync);
-}
-
-/* tusb driver calls this when it changes the chip's clocking */
-static int tusb6010_platform_retime(unsigned is_refclk)
-{
- static const char error[] =
- KERN_ERR "tusb6010 %s retime error %d\n";
-
- unsigned sysclk_ps;
- int status;
-
- if (!refclk_psec)
- return -ENODEV;
-
- sysclk_ps = is_refclk ? refclk_psec : TUSB6010_OSCCLK_60;
-
- status = tusb_set_async_mode(sysclk_ps);
- if (status < 0) {
- printk(error, "async", status);
- goto done;
- }
- status = tusb_set_sync_mode(sysclk_ps);
- if (status < 0)
- printk(error, "sync", status);
-done:
- return status;
-}
-
-static struct resource tusb_resources[] = {
- /* Order is significant! The start/end fields
- * are updated during setup..
- */
- { /* Asynchronous access */
- .flags = IORESOURCE_MEM,
- },
- { /* Synchronous access */
- .flags = IORESOURCE_MEM,
- },
-};
-
-static u64 tusb_dmamask = ~(u32)0;
-
-static struct platform_device tusb_device = {
- .name = "musb-tusb",
- .id = -1,
- .dev = {
- .dma_mask = &tusb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(tusb_resources),
- .resource = tusb_resources,
-};
-
-
-/* this may be called only from board-*.c setup code */
-int __init tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
- unsigned int ps_refclk, unsigned int waitpin,
- unsigned int async, unsigned int sync,
- unsigned int dmachan)
-{
- int status;
- static char error[] __initdata =
- KERN_ERR "tusb6010 init error %d, %d\n";
-
- /* ASYNC region, primarily for PIO */
- status = gpmc_cs_request(async, SZ_16M, (unsigned long *)
- &tusb_resources[0].start);
- if (status < 0) {
- printk(error, 1, status);
- return status;
- }
- tusb_resources[0].end = tusb_resources[0].start + 0x9ff;
- tusb_async.wait_pin = waitpin;
- async_cs = async;
-
- status = gpmc_cs_program_settings(async_cs, &tusb_async);
- if (status < 0)
- return status;
-
- /* SYNC region, primarily for DMA */
- status = gpmc_cs_request(sync, SZ_16M, (unsigned long *)
- &tusb_resources[1].start);
- if (status < 0) {
- printk(error, 2, status);
- return status;
- }
- tusb_resources[1].end = tusb_resources[1].start + 0x9ff;
- tusb_sync.wait_pin = waitpin;
- sync_cs = sync;
-
- status = gpmc_cs_program_settings(sync_cs, &tusb_sync);
- if (status < 0)
- return status;
-
- /* set up memory timings ... can speed them up later */
- if (!ps_refclk) {
- printk(error, 4, status);
- return -ENODEV;
- }
- refclk_psec = ps_refclk;
- status = tusb6010_platform_retime(1);
- if (status < 0) {
- printk(error, 5, status);
- return status;
- }
-
- /* finish device setup ... */
- if (!data) {
- printk(error, 6, status);
- return -ENODEV;
- }
- tusb_device.dev.platform_data = data;
-
- /* so far so good ... register the device */
- status = platform_device_register(&tusb_device);
- if (status < 0) {
- printk(error, 7, status);
- return status;
- }
- return 0;
-}
diff --git a/arch/arm/mach-omap2/usb-tusb6010.h b/arch/arm/mach-omap2/usb-tusb6010.h
deleted file mode 100644
index d210ff6238c2..000000000000
--- a/arch/arm/mach-omap2/usb-tusb6010.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifndef __USB_TUSB6010_H
-#define __USB_TUSB6010_H
-
-extern int __init tusb6010_setup_interface(
- struct musb_hdrc_platform_data *data,
- unsigned int ps_refclk, unsigned int waitpin,
- unsigned int async_cs, unsigned int sync_cs,
- unsigned int dmachan);
-
-#endif /* __USB_TUSB6010_H */
diff --git a/arch/arm/mach-omap2/voltagedomains2xxx_data.c b/arch/arm/mach-omap2/voltagedomains2xxx_data.c
deleted file mode 100644
index 9bc116fe3ba9..000000000000
--- a/arch/arm/mach-omap2/voltagedomains2xxx_data.c
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * OMAP3 voltage domain data
- *
- * Copyright (C) 2011 Texas Instruments, Inc.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include "voltage.h"
-
-static struct voltagedomain omap2_voltdm_core = {
- .name = "core",
-};
-
-static struct voltagedomain omap2_voltdm_wkup = {
- .name = "wakeup",
-};
-
-static struct voltagedomain *voltagedomains_omap2[] __initdata = {
- &omap2_voltdm_core,
- &omap2_voltdm_wkup,
- NULL,
-};
-
-void __init omap2xxx_voltagedomains_init(void)
-{
- voltdm_init(voltagedomains_omap2);
-}
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 0189dfdcbbe1..a383ff8f446c 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -337,7 +337,7 @@ config CRYPTO_DEV_OMAP_SHAM
config CRYPTO_DEV_OMAP_AES
tristate "Support for OMAP AES hw engine"
- depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP2PLUS
+ depends on ARCH_OMAP3 || ARCH_OMAP2PLUS
select CRYPTO_AES
select CRYPTO_SKCIPHER
select CRYPTO_ENGINE
diff --git a/drivers/media/platform/ti/omap/Kconfig b/drivers/media/platform/ti/omap/Kconfig
index a9dbe1097775..c41812b324ad 100644
--- a/drivers/media/platform/ti/omap/Kconfig
+++ b/drivers/media/platform/ti/omap/Kconfig
@@ -9,9 +9,9 @@ config VIDEO_OMAP2_VOUT
depends on V4L_PLATFORM_DRIVERS
depends on MMU
depends on FB_OMAP2 || (COMPILE_TEST && FB_OMAP2=n)
- depends on ARCH_OMAP2 || ARCH_OMAP3 || COMPILE_TEST
+ depends on ARCH_OMAP3 || COMPILE_TEST
depends on VIDEO_DEV
select VIDEOBUF2_DMA_CONTIG
- select OMAP2_VRFB if ARCH_OMAP2 || ARCH_OMAP3
+ select OMAP2_VRFB if ARCH_OMAP3
help
V4L2 Display driver support for OMAP2/3 based boards.
diff --git a/drivers/mtd/nand/onenand/Kconfig b/drivers/mtd/nand/onenand/Kconfig
index 7d57836bf32f..8a362fd5bfc4 100644
--- a/drivers/mtd/nand/onenand/Kconfig
+++ b/drivers/mtd/nand/onenand/Kconfig
@@ -23,8 +23,8 @@ config MTD_ONENAND_GENERIC
Support for OneNAND flash via platform device driver.
config MTD_ONENAND_OMAP2
- tristate "OneNAND on OMAP2/OMAP3 support"
- depends on ARCH_OMAP2 || ARCH_OMAP3 || (COMPILE_TEST && ARM)
+ tristate "OneNAND on OMAP3 support"
+ depends on ARCH_OMAP3 || (COMPILE_TEST && ARM)
depends on OF
depends on OMAP_GPMC
help
diff --git a/drivers/video/fbdev/omap2/omapfb/Kconfig b/drivers/video/fbdev/omap2/omapfb/Kconfig
index 2d20e79adefc..d8227f4326bd 100644
--- a/drivers/video/fbdev/omap2/omapfb/Kconfig
+++ b/drivers/video/fbdev/omap2/omapfb/Kconfig
@@ -8,7 +8,7 @@ menuconfig FB_OMAP2
depends on DRM_OMAP = n
depends on GPIOLIB
select FB_OMAP2_DSS
- select OMAP2_VRFB if ARCH_OMAP2 || ARCH_OMAP3
+ select OMAP2_VRFB if ARCH_OMAP3
select FB_IOMEM_HELPERS
help
Frame buffer driver for OMAP2+ based boards.
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 54a3fa370004..ca151152da19 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -265,12 +265,6 @@ int omap2_clk_disable_autoidle_all(void);
int omap2_clk_enable_autoidle_all(void);
int omap2_clk_allow_idle(struct clk *clk);
int omap2_clk_deny_idle(struct clk *clk);
-unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
- unsigned long parent_rate);
-int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
- unsigned long parent_rate);
-void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
-void omap2xxx_clkt_vps_init(void);
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
void ti_dt_clk_init_retry_clks(void);
@@ -322,8 +316,6 @@ void omap3_noncore_dpll_restore_context(struct clk_hw *hw);
int omap3_core_dpll_save_context(struct clk_hw *hw);
void omap3_core_dpll_restore_context(struct clk_hw *hw);
-extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
-
#ifdef CONFIG_ATAGS
int omap3430_clk_legacy_init(void);
int omap3430es1_clk_legacy_init(void);
--
2.53.0
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 06/13] ARM: omap2: remove omap24xx support
2026-09-08 15:27 ` [PATCH 06/13] ARM: omap2: remove omap24xx support Arnd Bergmann
@ 2026-09-08 17:18 ` Aaro Koskinen
2026-09-08 17:35 ` Linus Walleij
` (2 subsequent siblings)
3 siblings, 0 replies; 70+ messages in thread
From: Aaro Koskinen @ 2026-09-08 17:18 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Arnd Bergmann, Rob Herring,
Conor Dooley, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Andreas Kemnade, Kevin Hilman, Roger Quadros,
Tony Lindgren, Nicolas Ferre, Claudiu Beznea, Andrew Lunn,
Sebastian Hesselbarth, Gregory Clement, Robert Jarzmik,
Kristoffer Ericson, Ethan Nelson-Moore, Geert Uytterhoeven,
Alexander Sverdlin, Shawn Guo, Karl Mehltretter,
David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Paul Walmsley,
Herbert Xu, David S. Miller, Mauro Carvalho Chehab,
Kyungmin Park, Helge Deller, Tero Kristo, Stephen Boyd,
Thomas Zimmermann, linux-media, linux-mtd, linux-fbdev,
dri-devel, linux-clk
Hi,
On Tue, Sep 08, 2026 at 05:27:56PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The omap24xx SoC platform was used in the Nokia N800 and N810 tablets
> released on 2007 and was among the first ARMv6 CPUs in products that
> made it into products.
>
> Unfortunately the early ARM1136r0 CPU cores had a number of quirks that
> caused a disproportionate amount of work to keep them compatible with
> later ARMv6K/v7/v8 implementations.
>
> Drop the support for this SoC in order to allow removing ARM1136r0.
>
> Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Acked-by: Aaro Koskinen <aaro.koskinen@iki.fi>
A.
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 06/13] ARM: omap2: remove omap24xx support
2026-09-08 15:27 ` [PATCH 06/13] ARM: omap2: remove omap24xx support Arnd Bergmann
2026-09-08 17:18 ` Aaro Koskinen
@ 2026-09-08 17:35 ` Linus Walleij
2026-09-08 19:21 ` Karl Mehltretter
2026-09-09 8:06 ` Thomas Zimmermann
3 siblings, 0 replies; 70+ messages in thread
From: Linus Walleij @ 2026-09-08 17:35 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Russell King,
Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Paul Walmsley,
Herbert Xu, David S. Miller, Mauro Carvalho Chehab,
Kyungmin Park, Helge Deller, Tero Kristo, Stephen Boyd,
Thomas Zimmermann, linux-media, linux-mtd, linux-fbdev,
dri-devel, linux-clk
On Tue, Sep 8, 2026 at 5:29 PM Arnd Bergmann <arnd@kernel.org> wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The omap24xx SoC platform was used in the Nokia N800 and N810 tablets
> released on 2007 and was among the first ARMv6 CPUs in products that
> made it into products.
>
> Unfortunately the early ARM1136r0 CPU cores had a number of quirks that
> caused a disproportionate amount of work to keep them compatible with
> later ARMv6K/v7/v8 implementations.
>
> Drop the support for this SoC in order to allow removing ARM1136r0.
>
> Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
> Cc: Andreas Kemnade <andreas@kemnade.info>
> Cc: Kevin Hilman <khilman@baylibre.com>
> Cc: Roger Quadros <rogerq@kernel.org>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Paul Walmsley <paul@pwsan.com>
> Cc: Herbert Xu <herbert@gondor.apana.org.au>
> Cc: "David S. Miller" <davem@davemloft.net>
> Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
> Cc: Kyungmin Park <kyungmin.park@samsung.com>
> Cc: Helge Deller <deller@gmx.de>
> Cc: Tero Kristo <kristo@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-omap@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-media@vger.kernel.org
> Cc: linux-mtd@lists.infradead.org
> Cc: linux-fbdev@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
> Cc: linux-clk@vger.kernel.org
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Since Aaro says it can go, it can go.
If the n800 had a PostmarketOS port things would be different,
but it does not.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 06/13] ARM: omap2: remove omap24xx support
2026-09-08 15:27 ` [PATCH 06/13] ARM: omap2: remove omap24xx support Arnd Bergmann
2026-09-08 17:18 ` Aaro Koskinen
2026-09-08 17:35 ` Linus Walleij
@ 2026-09-08 19:21 ` Karl Mehltretter
2026-09-08 19:42 ` Arnd Bergmann
2026-09-09 8:06 ` Thomas Zimmermann
3 siblings, 1 reply; 70+ messages in thread
From: Karl Mehltretter @ 2026-09-08 19:21 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Arnd Bergmann, Rob Herring,
Conor Dooley, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Paul Walmsley,
Herbert Xu, David S. Miller, Mauro Carvalho Chehab,
Kyungmin Park, Helge Deller, Tero Kristo, Stephen Boyd,
Thomas Zimmermann, linux-media, linux-mtd, linux-fbdev,
dri-devel, linux-clk
On Tue, Sep 08, 2026 at 05:27:56PM +0100, Arnd Bergmann wrote:
> 86 files changed, 60 insertions(+), 10696 deletions(-)
Note that Sashiko skipped reviewing this patch, because it exceeded
its current 10000 line limit.
> -CONFIG_ARCH_MULTI_V6=y
> CONFIG_OMAP_RESET_CLOCKS=y
> -CONFIG_ARCH_OMAP2=y
With CONFIG_ARCH_MULTI_V6 gone, CONFIG_ARM_ERRATA_411920=y a few lines
down can be deleted (savedefconfig drops it)
> diff --git a/arch/arm/mach-omap2/gpmc.h b/arch/arm/mach-omap2/gpmc.h
> deleted file mode 100644
perl scripts/get_maintainer.pl --self-test=patterns now warns:
./MAINTAINERS:19896: warning: no file matches F: arch/arm/mach-omap2/*gpmc*
> @@ -560,13 +533,11 @@ void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table)
> * We still need this for omap2420 and omap3 PM to work, others are
Stale comment about omap2420
> diff --git a/arch/arm/mach-omap2/voltagedomains2xxx_data.c b/arch/arm/mach-omap2/voltagedomains2xxx_data.c
> deleted file mode 100644
> [...]
> -void __init omap2xxx_voltagedomains_init(void)
The declaration for this is still in voltage.h.
Thanks,
Karl
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 06/13] ARM: omap2: remove omap24xx support
2026-09-08 19:21 ` Karl Mehltretter
@ 2026-09-08 19:42 ` Arnd Bergmann
0 siblings, 0 replies; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 19:42 UTC (permalink / raw)
To: Karl Mehltretter, Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, A. Sverdlin, Shawn Guo,
David Hildenbrand (Red Hat),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, Linux-OMAP, Paul Walmsley,
Herbert Xu, David S . Miller, Mauro Carvalho Chehab,
Kyungmin Park, Helge Deller, Tero Kristo, Stephen Boyd,
Thomas Zimmermann, linux-media, linux-mtd, linux-fbdev,
dri-devel, linux-clk
On Tue, Sep 8, 2026, at 21:21, Karl Mehltretter wrote:
> On Tue, Sep 08, 2026 at 05:27:56PM +0100, Arnd Bergmann wrote:
>> 86 files changed, 60 insertions(+), 10696 deletions(-)
>
>> -CONFIG_ARCH_MULTI_V6=y
>> CONFIG_OMAP_RESET_CLOCKS=y
>> -CONFIG_ARCH_OMAP2=y
>
> With CONFIG_ARCH_MULTI_V6 gone, CONFIG_ARM_ERRATA_411920=y a few lines
> down can be deleted (savedefconfig drops it)
fixed now
>> diff --git a/arch/arm/mach-omap2/gpmc.h b/arch/arm/mach-omap2/gpmc.h
>> deleted file mode 100644
>
> perl scripts/get_maintainer.pl --self-test=patterns now warns:
> ./MAINTAINERS:19896: warning: no file matches F: arch/arm/mach-omap2/*gpmc*
Ah perfect, I was looking for that command, and will check
the rest of my series now.
>> @@ -560,13 +533,11 @@ void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table)
>> * We still need this for omap2420 and omap3 PM to work, others are
>
> Stale comment about omap2420
fixed.
>> diff --git a/arch/arm/mach-omap2/voltagedomains2xxx_data.c b/arch/arm/mach-omap2/voltagedomains2xxx_data.c
>> deleted file mode 100644
>> [...]
>> -void __init omap2xxx_voltagedomains_init(void)
>
> The declaration for this is still in voltage.h.
fixed.
Thanks a lot for taking a look here.
Arnd
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 06/13] ARM: omap2: remove omap24xx support
2026-09-08 15:27 ` [PATCH 06/13] ARM: omap2: remove omap24xx support Arnd Bergmann
` (2 preceding siblings ...)
2026-09-08 19:21 ` Karl Mehltretter
@ 2026-09-09 8:06 ` Thomas Zimmermann
3 siblings, 0 replies; 70+ messages in thread
From: Thomas Zimmermann @ 2026-09-09 8:06 UTC (permalink / raw)
To: Arnd Bergmann, Krzysztof Kozlowski, Alexandre Belloni,
Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Paul Walmsley,
Herbert Xu, David S. Miller, Mauro Carvalho Chehab,
Kyungmin Park, Helge Deller, Tero Kristo, Stephen Boyd,
linux-media, linux-mtd, linux-fbdev, dri-devel, linux-clk
Am 08.09.26 um 17:27 schrieb Arnd Bergmann:
> drivers/video/fbdev/omap2/omapfb/Kconfig | 2 +-
Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> # omapfb
> include/linux/clk/ti.h | 8 -
> 86 files changed, 60 insertions(+), 10696 deletions(-)
> delete mode 100644 arch/arm/boot/dts/ti/omap/omap2.dtsi
> delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi
> delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-h4.dts
> delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-n800.dts
> delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts
> delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-n810.dts
> delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi
> delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420.dtsi
> delete mode 100644 arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi
> delete mode 100644 arch/arm/boot/dts/ti/omap/omap2430-sdp.dts
> delete mode 100644 arch/arm/boot/dts/ti/omap/omap2430.dtsi
> delete mode 100644 arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi
> delete mode 100644 arch/arm/mach-omap2/board-n8x0.c
> delete mode 100644 arch/arm/mach-omap2/clkt2xxx_dpll.c
> delete mode 100644 arch/arm/mach-omap2/clkt2xxx_dpllcore.c
> delete mode 100644 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
> delete mode 100644 arch/arm/mach-omap2/clock2xxx.h
> delete mode 100644 arch/arm/mach-omap2/clockdomains2420_data.c
> delete mode 100644 arch/arm/mach-omap2/clockdomains2430_data.c
> delete mode 100644 arch/arm/mach-omap2/cm-regbits-24xx.h
> delete mode 100644 arch/arm/mach-omap2/cm2xxx.c
> delete mode 100644 arch/arm/mach-omap2/cm2xxx.h
> delete mode 100644 arch/arm/mach-omap2/common-board-devices.h
> delete mode 100644 arch/arm/mach-omap2/gpmc.h
> delete mode 100644 arch/arm/mach-omap2/l3_2xxx.h
> delete mode 100644 arch/arm/mach-omap2/l4_2xxx.h
> delete mode 100644 arch/arm/mach-omap2/mmc.h
> delete mode 100644 arch/arm/mach-omap2/msdi.c
> delete mode 100644 arch/arm/mach-omap2/omap2-restart.c
> delete mode 100644 arch/arm/mach-omap2/omap24xx.h
> delete mode 100644 arch/arm/mach-omap2/omap_hwmod_2420_data.c
> delete mode 100644 arch/arm/mach-omap2/omap_hwmod_2430_data.c
> delete mode 100644 arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
> delete mode 100644 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
> delete mode 100644 arch/arm/mach-omap2/opp2420_data.c
> delete mode 100644 arch/arm/mach-omap2/opp2430_data.c
> delete mode 100644 arch/arm/mach-omap2/opp2xxx.h
> delete mode 100644 arch/arm/mach-omap2/powerdomains2xxx_data.c
> delete mode 100644 arch/arm/mach-omap2/prm-regbits-24xx.h
> delete mode 100644 arch/arm/mach-omap2/prm2xxx.c
> delete mode 100644 arch/arm/mach-omap2/prm2xxx.h
> delete mode 100644 arch/arm/mach-omap2/sdrc2xxx.c
> delete mode 100644 arch/arm/mach-omap2/sleep24xx.S
> delete mode 100644 arch/arm/mach-omap2/sram242x.S
> delete mode 100644 arch/arm/mach-omap2/sram243x.S
> delete mode 100644 arch/arm/mach-omap2/usb-tusb6010.c
> delete mode 100644 arch/arm/mach-omap2/usb-tusb6010.h
> delete mode 100644 arch/arm/mach-omap2/voltagedomains2xxx_data.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 028db7ad15ad..0d10f778800d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -19874,7 +19874,6 @@ M: Jarkko Nikula <jarkko.nikula@bitmer.com>
> L: linux-sound@vger.kernel.org
> L: linux-omap@vger.kernel.org
> S: Maintained
> -F: sound/soc/ti/n810.c
> F: sound/soc/ti/omap*
> F: sound/soc/ti/rx51.c
> F: sound/soc/ti/sdma-pcm.*
> @@ -20027,7 +20026,6 @@ F: drivers/gpio/gpio-tps65219.c
> F: drivers/i2c/busses/i2c-omap.c
> F: drivers/irqchip/irq-omap-intc.c
> F: drivers/mfd/*omap*.c
> -F: drivers/mfd/menelaus.c
> F: drivers/mfd/palmas.c
> F: drivers/mfd/tps65217.c
> F: drivers/mfd/tps65218.c
> diff --git a/arch/arm/boot/dts/ti/omap/Makefile b/arch/arm/boot/dts/ti/omap/Makefile
> index 498c36ccb5ea..3c5d378df6b9 100644
> --- a/arch/arm/boot/dts/ti/omap/Makefile
> +++ b/arch/arm/boot/dts/ti/omap/Makefile
> @@ -1,10 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0
> -dtb-$(CONFIG_ARCH_OMAP2) += \
> - omap2420-h4.dtb \
> - omap2420-n800.dtb \
> - omap2420-n810.dtb \
> - omap2420-n810-wimax.dtb \
> - omap2430-sdp.dtb
> dtb-$(CONFIG_ARCH_OMAP3) += \
> am3517-craneboard.dtb \
> am3517-evm.dtb \
> diff --git a/arch/arm/boot/dts/ti/omap/omap2.dtsi b/arch/arm/boot/dts/ti/omap/omap2.dtsi
> deleted file mode 100644
> index fdc1790adf43..000000000000
> --- a/arch/arm/boot/dts/ti/omap/omap2.dtsi
> +++ /dev/null
> @@ -1,338 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Device Tree Source for OMAP2 SoC
> - *
> - * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
> - */
> -
> -#include <dt-bindings/bus/ti-sysc.h>
> -#include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/interrupt-controller/irq.h>
> -#include <dt-bindings/pinctrl/omap.h>
> -
> -/ {
> - compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
> - interrupt-parent = <&intc>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - chosen { };
> -
> - aliases {
> - serial0 = &uart1;
> - serial1 = &uart2;
> - serial2 = &uart3;
> - i2c0 = &i2c1;
> - i2c1 = &i2c2;
> - };
> -
> - cpus {
> - #address-cells = <0>;
> - #size-cells = <0>;
> -
> - cpu {
> - compatible = "arm,arm1136jf-s";
> - device_type = "cpu";
> - };
> - };
> -
> - pmu {
> - compatible = "arm,arm1136-pmu";
> - interrupts = <3>;
> - };
> -
> - soc {
> - compatible = "ti,omap-infra";
> - mpu {
> - compatible = "ti,omap2-mpu";
> - ti,hwmods = "mpu";
> - };
> - };
> -
> - ocp {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges;
> - ti,hwmods = "l3_main";
> -
> - aes: aes@480a6000 {
> - compatible = "ti,omap2-aes";
> - ti,hwmods = "aes";
> - reg = <0x480a6000 0x50>;
> - dmas = <&sdma 9 &sdma 10>;
> - dma-names = "tx", "rx";
> - };
> -
> - hdq1w: 1w@480b2000 {
> - compatible = "ti,omap2420-1w";
> - ti,hwmods = "hdq1w";
> - reg = <0x480b2000 0x1000>;
> - interrupts = <58>;
> - };
> -
> - intc: interrupt-controller@1 {
> - compatible = "ti,omap2-intc";
> - interrupt-controller;
> - #interrupt-cells = <1>;
> - reg = <0x480FE000 0x1000>;
> - };
> -
> - target-module@48056000 {
> - compatible = "ti,sysc-omap2", "ti,sysc";
> - reg = <0x48056000 0x4>,
> - <0x4805602c 0x4>,
> - <0x48056028 0x4>;
> - reg-names = "rev", "sysc", "syss";
> - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
> - SYSC_OMAP2_EMUFREE |
> - SYSC_OMAP2_SOFTRESET |
> - SYSC_OMAP2_AUTOIDLE)>;
> - ti,sysc-midle = <SYSC_IDLE_FORCE>,
> - <SYSC_IDLE_NO>,
> - <SYSC_IDLE_SMART>;
> - ti,syss-mask = <1>;
> - clocks = <&core_l3_ck>;
> - clock-names = "fck";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0 0x48056000 0x1000>;
> -
> - sdma: dma-controller@0 {
> - compatible = "ti,omap2420-sdma", "ti,omap-sdma";
> - reg = <0 0x1000>;
> - interrupts = <12>,
> - <13>,
> - <14>,
> - <15>;
> - #dma-cells = <1>;
> - dma-channels = <32>;
> - dma-requests = <64>;
> - };
> - };
> -
> - i2c1: i2c@48070000 {
> - compatible = "ti,omap2-i2c";
> - ti,hwmods = "i2c1";
> - reg = <0x48070000 0x80>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - interrupts = <56>;
> - };
> -
> - i2c2: i2c@48072000 {
> - compatible = "ti,omap2-i2c";
> - ti,hwmods = "i2c2";
> - reg = <0x48072000 0x80>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - interrupts = <57>;
> - };
> -
> - mcspi1: spi@48098000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "ti,omap2-mcspi";
> - ti,hwmods = "mcspi1";
> - reg = <0x48098000 0x100>;
> - interrupts = <65>;
> - dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
> - &sdma 39 &sdma 40 &sdma 41 &sdma 42>;
> - dma-names = "tx0", "rx0", "tx1", "rx1",
> - "tx2", "rx2", "tx3", "rx3";
> - };
> -
> - mcspi2: spi@4809a000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "ti,omap2-mcspi";
> - ti,hwmods = "mcspi2";
> - reg = <0x4809a000 0x100>;
> - interrupts = <66>;
> - dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
> - dma-names = "tx0", "rx0", "tx1", "rx1";
> - };
> -
> - rng: rng@480a0000 {
> - compatible = "ti,omap2-rng";
> - ti,hwmods = "rng";
> - reg = <0x480a0000 0x50>;
> - interrupts = <52>;
> - };
> -
> - sham: sham@480a4000 {
> - compatible = "ti,omap2-sham";
> - ti,hwmods = "sham";
> - reg = <0x480a4000 0x64>;
> - interrupts = <51>;
> - dmas = <&sdma 13>;
> - dma-names = "rx";
> - };
> -
> - uart1: serial@4806a000 {
> - compatible = "ti,omap2-uart";
> - ti,hwmods = "uart1";
> - reg = <0x4806a000 0x2000>;
> - interrupts = <72>;
> - dmas = <&sdma 49 &sdma 50>;
> - dma-names = "tx", "rx";
> - clock-frequency = <48000000>;
> - };
> -
> - uart2: serial@4806c000 {
> - compatible = "ti,omap2-uart";
> - ti,hwmods = "uart2";
> - reg = <0x4806c000 0x400>;
> - interrupts = <73>;
> - dmas = <&sdma 51 &sdma 52>;
> - dma-names = "tx", "rx";
> - clock-frequency = <48000000>;
> - };
> -
> - uart3: serial@4806e000 {
> - compatible = "ti,omap2-uart";
> - ti,hwmods = "uart3";
> - reg = <0x4806e000 0x400>;
> - interrupts = <74>;
> - dmas = <&sdma 53 &sdma 54>;
> - dma-names = "tx", "rx";
> - clock-frequency = <48000000>;
> - };
> -
> - timer2_target: target-module@4802a000 {
> - compatible = "ti,sysc-omap2-timer", "ti,sysc";
> - reg = <0x4802a000 0x4>,
> - <0x4802a010 0x4>,
> - <0x4802a014 0x4>;
> - reg-names = "rev", "sysc", "syss";
> - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
> - SYSC_OMAP2_EMUFREE |
> - SYSC_OMAP2_ENAWAKEUP |
> - SYSC_OMAP2_SOFTRESET |
> - SYSC_OMAP2_AUTOIDLE)>;
> - ti,sysc-sidle = <SYSC_IDLE_FORCE>,
> - <SYSC_IDLE_NO>,
> - <SYSC_IDLE_SMART>;
> - ti,syss-mask = <1>;
> - clocks = <&gpt2_fck>, <&gpt2_ick>;
> - clock-names = "fck", "ick";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0x0 0x4802a000 0x1000>;
> -
> - timer2: timer@0 {
> - compatible = "ti,omap2420-timer";
> - reg = <0 0x400>;
> - interrupts = <38>;
> - };
> - };
> -
> - timer3: timer@48078000 {
> - compatible = "ti,omap2420-timer";
> - reg = <0x48078000 0x400>;
> - interrupts = <39>;
> - ti,hwmods = "timer3";
> - };
> -
> - timer4: timer@4807a000 {
> - compatible = "ti,omap2420-timer";
> - reg = <0x4807a000 0x400>;
> - interrupts = <40>;
> - ti,hwmods = "timer4";
> - };
> -
> - timer5: timer@4807c000 {
> - compatible = "ti,omap2420-timer";
> - reg = <0x4807c000 0x400>;
> - interrupts = <41>;
> - ti,hwmods = "timer5";
> - ti,timer-dsp;
> - };
> -
> - timer6: timer@4807e000 {
> - compatible = "ti,omap2420-timer";
> - reg = <0x4807e000 0x400>;
> - interrupts = <42>;
> - ti,hwmods = "timer6";
> - ti,timer-dsp;
> - };
> -
> - timer7: timer@48080000 {
> - compatible = "ti,omap2420-timer";
> - reg = <0x48080000 0x400>;
> - interrupts = <43>;
> - ti,hwmods = "timer7";
> - ti,timer-dsp;
> - };
> -
> - timer8: timer@48082000 {
> - compatible = "ti,omap2420-timer";
> - reg = <0x48082000 0x400>;
> - interrupts = <44>;
> - ti,hwmods = "timer8";
> - ti,timer-dsp;
> - };
> -
> - timer9: timer@48084000 {
> - compatible = "ti,omap2420-timer";
> - reg = <0x48084000 0x400>;
> - interrupts = <45>;
> - ti,hwmods = "timer9";
> - ti,timer-pwm;
> - };
> -
> - timer10: timer@48086000 {
> - compatible = "ti,omap2420-timer";
> - reg = <0x48086000 0x400>;
> - interrupts = <46>;
> - ti,hwmods = "timer10";
> - ti,timer-pwm;
> - };
> -
> - timer11: timer@48088000 {
> - compatible = "ti,omap2420-timer";
> - reg = <0x48088000 0x400>;
> - interrupts = <47>;
> - ti,hwmods = "timer11";
> - ti,timer-pwm;
> - };
> -
> - timer12: timer@4808a000 {
> - compatible = "ti,omap2420-timer";
> - reg = <0x4808a000 0x400>;
> - interrupts = <48>;
> - ti,hwmods = "timer12";
> - ti,timer-pwm;
> - };
> -
> - dss: dss@48050000 {
> - compatible = "ti,omap2-dss";
> - reg = <0x48050000 0x400>;
> - status = "disabled";
> - ti,hwmods = "dss_core";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges;
> -
> - dispc@48050400 {
> - compatible = "ti,omap2-dispc";
> - reg = <0x48050400 0x400>;
> - interrupts = <25>;
> - ti,hwmods = "dss_dispc";
> - };
> -
> - rfbi: encoder@48050800 {
> - compatible = "ti,omap2-rfbi";
> - reg = <0x48050800 0x400>;
> - status = "disabled";
> - ti,hwmods = "dss_rfbi";
> - };
> -
> - venc: encoder@48050c00 {
> - compatible = "ti,omap2-venc";
> - reg = <0x48050c00 0x400>;
> - status = "disabled";
> - ti,hwmods = "dss_venc";
> - };
> - };
> - };
> -};
> diff --git a/arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi
> deleted file mode 100644
> index 00a7a199a91c..000000000000
> --- a/arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi
> +++ /dev/null
> @@ -1,267 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Device Tree Source for OMAP2420 clock data
> - *
> - * Copyright (C) 2014 Texas Instruments, Inc.
> - */
> -
> -&prcm_clocks {
> - sys_clkout2_src_gate: sys_clkout2_src_gate@70 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-no-wait-gate-clock";
> - clocks = <&core_ck>;
> - ti,bit-shift = <15>;
> - reg = <0x0070>;
> - };
> -
> - sys_clkout2_src_mux: sys_clkout2_src_mux@70 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
> - ti,bit-shift = <8>;
> - reg = <0x0070>;
> - };
> -
> - sys_clkout2_src: sys_clkout2_src {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
> - };
> -
> - sys_clkout2: sys_clkout2@70 {
> - #clock-cells = <0>;
> - compatible = "ti,divider-clock";
> - clocks = <&sys_clkout2_src>;
> - ti,bit-shift = <11>;
> - ti,max-div = <64>;
> - reg = <0x0070>;
> - ti,index-power-of-two;
> - };
> -
> - dsp_gate_ick: dsp_gate_ick@810 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-interface-clock";
> - clocks = <&dsp_fck>;
> - ti,bit-shift = <1>;
> - reg = <0x0810>;
> - };
> -
> - dsp_div_ick: dsp_div_ick@840 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-divider-clock";
> - clocks = <&dsp_fck>;
> - ti,bit-shift = <5>;
> - ti,max-div = <3>;
> - reg = <0x0840>;
> - ti,index-starts-at-one;
> - };
> -
> - dsp_ick: dsp_ick {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
> - };
> -
> - iva1_gate_ifck: iva1_gate_ifck@800 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&core_ck>;
> - ti,bit-shift = <10>;
> - reg = <0x0800>;
> - };
> -
> - iva1_div_ifck: iva1_div_ifck@840 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-divider-clock";
> - clocks = <&core_ck>;
> - ti,bit-shift = <8>;
> - reg = <0x0840>;
> - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
> - };
> -
> - iva1_ifck: iva1_ifck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
> - };
> -
> - iva1_ifck_div: iva1_ifck_div {
> - #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&iva1_ifck>;
> - clock-mult = <1>;
> - clock-div = <2>;
> - };
> -
> - iva1_mpu_int_ifck: iva1_mpu_int_ifck@800 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&iva1_ifck_div>;
> - ti,bit-shift = <8>;
> - reg = <0x0800>;
> - };
> -
> - wdt3_ick: wdt3_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <28>;
> - reg = <0x0210>;
> - };
> -
> - wdt3_fck: wdt3_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <28>;
> - reg = <0x0200>;
> - };
> -
> - mmc_ick: mmc_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <26>;
> - reg = <0x0210>;
> - };
> -
> - mmc_fck: mmc_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_96m_ck>;
> - ti,bit-shift = <26>;
> - reg = <0x0200>;
> - };
> -
> - eac_ick: eac_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <24>;
> - reg = <0x0210>;
> - };
> -
> - eac_fck: eac_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_96m_ck>;
> - ti,bit-shift = <24>;
> - reg = <0x0200>;
> - };
> -
> - i2c1_fck: i2c1_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_12m_ck>;
> - ti,bit-shift = <19>;
> - reg = <0x0200>;
> - };
> -
> - i2c2_fck: i2c2_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_12m_ck>;
> - ti,bit-shift = <20>;
> - reg = <0x0200>;
> - };
> -
> - vlynq_ick: vlynq_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&core_l3_ck>;
> - ti,bit-shift = <3>;
> - reg = <0x0210>;
> - };
> -
> - vlynq_gate_fck: vlynq_gate_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&core_ck>;
> - ti,bit-shift = <3>;
> - reg = <0x0200>;
> - };
> -
> - core_d18_ck: core_d18_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&core_ck>;
> - clock-mult = <1>;
> - clock-div = <18>;
> - };
> -
> - vlynq_mux_fck: vlynq_mux_fck@240 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;
> - ti,bit-shift = <15>;
> - reg = <0x0240>;
> - };
> -
> - vlynq_fck: vlynq_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>;
> - };
> -};
> -
> -&prcm_clockdomains {
> - gfx_clkdm: gfx_clkdm {
> - compatible = "ti,clockdomain";
> - clocks = <&gfx_ick>;
> - };
> -
> - core_l3_clkdm: core_l3_clkdm {
> - compatible = "ti,clockdomain";
> - clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>;
> - };
> -
> - wkup_clkdm: wkup_clkdm {
> - compatible = "ti,clockdomain";
> - clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
> - <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
> - <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>;
> - };
> -
> - iva1_clkdm: iva1_clkdm {
> - compatible = "ti,clockdomain";
> - clocks = <&iva1_mpu_int_ifck>;
> - };
> -
> - dss_clkdm: dss_clkdm {
> - compatible = "ti,clockdomain";
> - clocks = <&dss_ick>, <&dss_54m_fck>;
> - };
> -
> - core_l4_clkdm: core_l4_clkdm {
> - compatible = "ti,clockdomain";
> - clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
> - <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
> - <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
> - <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>,
> - <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
> - <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>,
> - <&uart3_ick>, <&uart3_fck>, <&cam_ick>,
> - <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>,
> - <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>,
> - <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>,
> - <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>,
> - <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>,
> - <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
> - <&pka_ick>;
> - };
> -};
> -
> -&func_96m_ck {
> - compatible = "fixed-factor-clock";
> - clocks = <&apll96_ck>;
> - clock-mult = <1>;
> - clock-div = <1>;
> -};
> -
> -&dsp_div_fck {
> - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
> -};
> -
> -&ssi_ssr_sst_div_fck {
> - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
> -};
> diff --git a/arch/arm/boot/dts/ti/omap/omap2420-h4.dts b/arch/arm/boot/dts/ti/omap/omap2420-h4.dts
> deleted file mode 100644
> index 5acf5dd87c59..000000000000
> --- a/arch/arm/boot/dts/ti/omap/omap2420-h4.dts
> +++ /dev/null
> @@ -1,63 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
> - */
> -/dts-v1/;
> -
> -#include "omap2420.dtsi"
> -
> -/ {
> - model = "TI OMAP2420 H4 board";
> - compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2";
> -
> - memory@80000000 {
> - device_type = "memory";
> - reg = <0x80000000 0x4000000>; /* 64 MB */
> - };
> -};
> -
> -&gpmc {
> - ranges = <0 0 0x08000000 0x04000000>;
> -
> - nor@0,0 {
> - compatible = "cfi-flash";
> - linux,mtd-name = "intel,ge28f256l18b85";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0 0 0x04000000>;
> - bank-width = <2>;
> -
> - gpmc,mux-add-data = <2>;
> - gpmc,cs-on-ns = <10>;
> - gpmc,cs-rd-off-ns = <160>;
> - gpmc,cs-wr-off-ns = <160>;
> - gpmc,adv-on-ns = <20>;
> - gpmc,adv-rd-off-ns = <50>;
> - gpmc,adv-wr-off-ns = <50>;
> - gpmc,oe-on-ns = <60>;
> - gpmc,oe-off-ns = <120>;
> - gpmc,we-on-ns = <60>;
> - gpmc,we-off-ns = <120>;
> - gpmc,rd-cycle-ns = <170>;
> - gpmc,wr-cycle-ns = <170>;
> - gpmc,access-ns = <150>;
> - gpmc,page-burst-access-ns = <10>;
> -
> - partition@0 {
> - label = "bootloader";
> - reg = <0 0x20000>;
> - };
> - partition@20000 {
> - label = "params";
> - reg = <0x20000 0x20000>;
> - };
> - partition@40000 {
> - label = "kernel";
> - reg = <0x40000 0x200000>;
> - };
> - partition@240000 {
> - label = "file-system";
> - reg = <0x240000 0x3dc0000>;
> - };
> - };
> -};
> diff --git a/arch/arm/boot/dts/ti/omap/omap2420-n800.dts b/arch/arm/boot/dts/ti/omap/omap2420-n800.dts
> deleted file mode 100644
> index f06d767e818b..000000000000
> --- a/arch/arm/boot/dts/ti/omap/omap2420-n800.dts
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/dts-v1/;
> -
> -#include "omap2420-n8x0-common.dtsi"
> -
> -/ {
> - model = "Nokia N800";
> - compatible = "nokia,n800", "nokia,n8x0", "ti,omap2420", "ti,omap2";
> -};
> diff --git a/arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts b/arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts
> deleted file mode 100644
> index ac9acbd609b6..000000000000
> --- a/arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/dts-v1/;
> -
> -#include "omap2420-n8x0-common.dtsi"
> -
> -/ {
> - model = "Nokia N810 WiMax";
> - compatible = "nokia,n810-wimax", "nokia,n8x0", "ti,omap2420", "ti,omap2";
> -};
> diff --git a/arch/arm/boot/dts/ti/omap/omap2420-n810.dts b/arch/arm/boot/dts/ti/omap/omap2420-n810.dts
> deleted file mode 100644
> index 3bf8175d85a8..000000000000
> --- a/arch/arm/boot/dts/ti/omap/omap2420-n810.dts
> +++ /dev/null
> @@ -1,75 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/dts-v1/;
> -
> -#include "omap2420-n8x0-common.dtsi"
> -
> -/ {
> - model = "Nokia N810";
> - compatible = "nokia,n810", "nokia,n8x0", "ti,omap2420", "ti,omap2";
> -
> - vio_ape: vio_ape {
> - compatible = "regulator-fixed";
> - regulator-name = "vio_ape";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - v28_aic: v28_aic {
> - compatible = "regulator-fixed";
> - regulator-name = "v28_aic";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - };
> -};
> -
> -&omap2420_pmx {
> - mcbsp2_pins: mcbsp2-pins {
> - pinctrl-single,pins = <
> - OMAP2420_CORE_IOPAD(0x0124, PIN_INPUT | MUX_MODE1) /* eac_ac_sclk.mcbsp2_clkx */
> - OMAP2420_CORE_IOPAD(0x0125, PIN_INPUT | MUX_MODE1) /* eac_ac_fs.mcbsp2_fsx */
> - OMAP2420_CORE_IOPAD(0x0126, PIN_INPUT | MUX_MODE1) /* eac_ac_din.mcbsp2_dr */
> - OMAP2420_CORE_IOPAD(0x0127, PIN_OUTPUT | MUX_MODE1) /* eac_ac_dout.mcbsp2_dx */
> - >;
> - };
> -
> - aic33_pins: aic33-pins {
> - pinctrl-single,pins = <
> - OMAP2420_CORE_IOPAD(0x0129, PIN_OUTPUT | MUX_MODE3) /* eac_ac_rst.gpio118 */
> - OMAP2420_CORE_IOPAD(0x00e8, PIN_OUTPUT | MUX_MODE2) /* vlynq_tx1.sys_clkout2 */
> - >;
> - };
> -};
> -
> -&i2c2 {
> - aic33@18 {
> - compatible = "ti,tlv320aic33";
> - reg = <0x18>;
> -
> - pinctrl-names = "default";
> - pinctrl-0 = <&aic33_pins>;
> -
> - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; /* gpio118 */
> -
> - ai3x-gpio-func = <
> - 10 /* AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK */
> - 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */
> - >;
> - ai3x-micbias-vg = <1>; /* 2V */
> -
> - AVDD-supply = <&v28_aic>;
> - DRVDD-supply = <&v28_aic>;
> - IOVDD-supply = <&vio_ape>;
> - DVDD-supply = <&vio_ape>;
> -
> - assigned-clocks = <&sys_clkout2_src>, <&sys_clkout2>;
> - assigned-clock-parents = <&func_96m_ck>;
> - assigned-clock-rates = <0>, <12000000>;
> - };
> -};
> -
> -&mcbsp2 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&mcbsp2_pins>;
> -
> - status = "okay";
> -};
> diff --git a/arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi
> deleted file mode 100644
> index fe9dd8bbfc85..000000000000
> --- a/arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi
> +++ /dev/null
> @@ -1,123 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -#include "omap2420.dtsi"
> -
> -/ {
> - memory@80000000 {
> - device_type = "memory";
> - reg = <0x80000000 0x8000000>; /* 128 MB */
> - };
> -
> - chosen {
> - stdout-path = &uart3;
> - };
> -
> - ocp {
> - i2c0 {
> - compatible = "i2c-cbus-gpio";
> - gpios = <&gpio3 2 GPIO_ACTIVE_HIGH /* gpio66 clk */
> - &gpio3 1 GPIO_ACTIVE_HIGH /* gpio65 dat */
> - &gpio3 0 GPIO_ACTIVE_HIGH /* gpio64 sel */
> - >;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - retu: retu@1 {
> - compatible = "nokia,retu";
> - interrupt-parent = <&gpio4>;
> - interrupts = <12 IRQ_TYPE_EDGE_RISING>;
> - reg = <0x1>;
> - };
> - };
> - };
> -};
> -
> -&i2c1 {
> - clock-frequency = <400000>;
> -
> - pmic@72 {
> - compatible = "menelaus";
> - reg = <0x72>;
> - interrupts = <7 IRQ_TYPE_EDGE_RISING>;
> - };
> -};
> -
> -&i2c2 {
> - clock-frequency = <400000>;
> -};
> -
> -&gpmc {
> - ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
> -
> - /* gpio-irq for dma: 26 */
> -
> - onenand@0,0 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "ti,omap2-onenand";
> - reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
> -
> - gpmc,sync-read;
> - gpmc,burst-length = <16>;
> - gpmc,burst-read;
> - gpmc,burst-wrap;
> - gpmc,device-width = <2>;
> - gpmc,mux-add-data = <2>;
> - gpmc,cs-on-ns = <0>;
> - gpmc,cs-rd-off-ns = <127>;
> - gpmc,cs-wr-off-ns = <109>;
> - gpmc,adv-on-ns = <0>;
> - gpmc,adv-rd-off-ns = <18>;
> - gpmc,adv-wr-off-ns = <18>;
> - gpmc,oe-on-ns = <27>;
> - gpmc,oe-off-ns = <127>;
> - gpmc,we-on-ns = <27>;
> - gpmc,we-off-ns = <72>;
> - gpmc,rd-cycle-ns = <145>;
> - gpmc,wr-cycle-ns = <136>;
> - gpmc,access-ns = <118>;
> - gpmc,page-burst-access-ns = <27>;
> - gpmc,bus-turnaround-ns = <0>;
> - gpmc,cycle2cycle-delay-ns = <0>;
> - gpmc,wait-monitoring-ns = <0>;
> - gpmc,clk-activation-ns = <9>;
> - gpmc,sync-clk-ps = <27000>;
> -
> - /* MTD partition table corresponding to old board-n8x0 file. */
> - partition@0 {
> - label = "bootloader";
> - reg = <0x00000000 0x00020000>;
> - read-only;
> - };
> - partition@1 {
> - label = "config";
> - reg = <0x00020000 0x00060000>;
> - };
> - partition@2 {
> - label = "kernel";
> - reg = <0x00080000 0x00200000>;
> - };
> - partition@3 {
> - label = "initfs";
> - reg = <0x00280000 0x00400000>;
> - };
> - partition@4 {
> - label = "rootfs";
> - reg = <0x00680000 0x0f980000>;
> - };
> - partition@5 {
> - label = "omap2-onenand";
> - reg = <0x00000000 0x10000000>;
> - };
> - };
> -};
> -
> -&mcspi2 {
> - status = "okay";
> -
> - wifi@0 {
> - reg = <0>;
> - compatible = "st,stlc4560";
> - spi-max-frequency = <48000000>;
> - interrupts-extended = <&gpio3 23 IRQ_TYPE_EDGE_RISING>;
> - powerdown-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; /* gpio 97 */
> - };
> -};
> diff --git a/arch/arm/boot/dts/ti/omap/omap2420.dtsi b/arch/arm/boot/dts/ti/omap/omap2420.dtsi
> deleted file mode 100644
> index 821da51cb870..000000000000
> --- a/arch/arm/boot/dts/ti/omap/omap2420.dtsi
> +++ /dev/null
> @@ -1,262 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Device Tree Source for OMAP2420 SoC
> - *
> - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
> - */
> -
> -#include "omap2.dtsi"
> -
> -/ {
> - compatible = "ti,omap2420", "ti,omap2";
> -
> - ocp {
> - l4: l4@48000000 {
> - compatible = "ti,omap2-l4", "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0 0x48000000 0x100000>;
> -
> - prcm: prcm@8000 {
> - compatible = "ti,omap2-prcm";
> - reg = <0x8000 0x1000>;
> -
> - prcm_clocks: clocks {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - prcm_clockdomains: clockdomains {
> - };
> - };
> -
> - scm: scm@0 {
> - compatible = "ti,omap2-scm", "simple-bus";
> - reg = <0x0 0x1000>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - #pinctrl-cells = <1>;
> - ranges = <0 0x0 0x1000>;
> -
> - omap2420_pmx: pinmux@30 {
> - compatible = "ti,omap2420-padconf",
> - "pinctrl-single";
> - reg = <0x30 0x0113>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - #pinctrl-cells = <1>;
> - pinctrl-single,register-width = <8>;
> - pinctrl-single,function-mask = <0x3f>;
> - };
> -
> - scm_conf: scm_conf@270 {
> - compatible = "syscon";
> - reg = <0x270 0x100>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> -
> - scm_clocks: clocks {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> - };
> -
> - scm_clockdomains: clockdomains {
> - };
> - };
> -
> - target-module@4000 {
> - compatible = "ti,sysc-omap2", "ti,sysc";
> - reg = <0x4000 0x4>,
> - <0x4004 0x4>;
> - reg-names = "rev", "sysc";
> - ti,sysc-sidle = <SYSC_IDLE_FORCE>,
> - <SYSC_IDLE_NO>;
> - clocks = <&func_32k_ck>;
> - clock-names = "fck";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0x0 0x4000 0x1000>;
> -
> - counter32k: counter@0 {
> - compatible = "ti,omap-counter32k";
> - reg = <0 0x20>;
> - };
> - };
> - };
> -
> - gpio1: gpio@48018000 {
> - compatible = "ti,omap2-gpio";
> - reg = <0x48018000 0x200>;
> - interrupts = <29>;
> - ti,hwmods = "gpio1";
> - ti,gpio-always-on;
> - #gpio-cells = <2>;
> - gpio-controller;
> - #interrupt-cells = <2>;
> - interrupt-controller;
> - };
> -
> - gpio2: gpio@4801a000 {
> - compatible = "ti,omap2-gpio";
> - reg = <0x4801a000 0x200>;
> - interrupts = <30>;
> - ti,hwmods = "gpio2";
> - ti,gpio-always-on;
> - #gpio-cells = <2>;
> - gpio-controller;
> - #interrupt-cells = <2>;
> - interrupt-controller;
> - };
> -
> - gpio3: gpio@4801c000 {
> - compatible = "ti,omap2-gpio";
> - reg = <0x4801c000 0x200>;
> - interrupts = <31>;
> - ti,hwmods = "gpio3";
> - ti,gpio-always-on;
> - #gpio-cells = <2>;
> - gpio-controller;
> - #interrupt-cells = <2>;
> - interrupt-controller;
> - };
> -
> - gpio4: gpio@4801e000 {
> - compatible = "ti,omap2-gpio";
> - reg = <0x4801e000 0x200>;
> - interrupts = <32>;
> - ti,hwmods = "gpio4";
> - ti,gpio-always-on;
> - #gpio-cells = <2>;
> - gpio-controller;
> - #interrupt-cells = <2>;
> - interrupt-controller;
> - };
> -
> - gpmc: gpmc@6800a000 {
> - compatible = "ti,omap2420-gpmc";
> - reg = <0x6800a000 0x1000>;
> - #address-cells = <2>;
> - #size-cells = <1>;
> - interrupts = <20>;
> - gpmc,num-cs = <8>;
> - gpmc,num-waitpins = <4>;
> - ti,hwmods = "gpmc";
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - };
> -
> - mcbsp1: mcbsp@48074000 {
> - compatible = "ti,omap2420-mcbsp";
> - reg = <0x48074000 0xff>;
> - reg-names = "mpu";
> - interrupts = <59>, /* TX interrupt */
> - <60>; /* RX interrupt */
> - interrupt-names = "tx", "rx";
> - ti,hwmods = "mcbsp1";
> - dmas = <&sdma 31>,
> - <&sdma 32>;
> - dma-names = "tx", "rx";
> - status = "disabled";
> - };
> -
> - mcbsp2: mcbsp@48076000 {
> - compatible = "ti,omap2420-mcbsp";
> - reg = <0x48076000 0xff>;
> - reg-names = "mpu";
> - interrupts = <62>, /* TX interrupt */
> - <63>; /* RX interrupt */
> - interrupt-names = "tx", "rx";
> - ti,hwmods = "mcbsp2";
> - dmas = <&sdma 33>,
> - <&sdma 34>;
> - dma-names = "tx", "rx";
> - status = "disabled";
> - };
> -
> - msdi1: mmc@4809c000 {
> - compatible = "ti,omap2420-mmc";
> - ti,hwmods = "msdi1";
> - reg = <0x4809c000 0x80>;
> - interrupts = <83>;
> - dmas = <&sdma 61 &sdma 62>;
> - dma-names = "tx", "rx";
> - };
> -
> - mailbox: mailbox@48094000 {
> - compatible = "ti,omap2-mailbox";
> - reg = <0x48094000 0x200>;
> - interrupts = <26>, <34>;
> - ti,hwmods = "mailbox";
> - #mbox-cells = <1>;
> - ti,mbox-num-users = <4>;
> - ti,mbox-num-fifos = <6>;
> - mbox_dsp: mbox-dsp {
> - ti,mbox-tx = <0 0 0>;
> - ti,mbox-rx = <1 0 0>;
> - };
> - mbox_iva: mbox-iva {
> - ti,mbox-tx = <2 1 3>;
> - ti,mbox-rx = <3 1 3>;
> - };
> - };
> -
> - timer1_target: target-module@48028000 {
> - compatible = "ti,sysc-omap2-timer", "ti,sysc";
> - reg = <0x48028000 0x4>,
> - <0x48028010 0x4>,
> - <0x48028014 0x4>;
> - reg-names = "rev", "sysc", "syss";
> - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
> - SYSC_OMAP2_EMUFREE |
> - SYSC_OMAP2_ENAWAKEUP |
> - SYSC_OMAP2_SOFTRESET |
> - SYSC_OMAP2_AUTOIDLE)>;
> - ti,sysc-sidle = <SYSC_IDLE_FORCE>,
> - <SYSC_IDLE_NO>,
> - <SYSC_IDLE_SMART>;
> - ti,syss-mask = <1>;
> - clocks = <&gpt1_fck>, <&gpt1_ick>;
> - clock-names = "fck", "ick";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0x0 0x48028000 0x1000>;
> -
> - timer1: timer@0 {
> - compatible = "ti,omap2420-timer";
> - reg = <0 0x400>;
> - interrupts = <37>;
> - ti,timer-alwon;
> - };
> - };
> -
> - wd_timer2: wdt@48022000 {
> - compatible = "ti,omap2-wdt";
> - ti,hwmods = "wd_timer2";
> - reg = <0x48022000 0x80>;
> - };
> - };
> -};
> -
> -&i2c1 {
> - compatible = "ti,omap2420-i2c";
> -};
> -
> -&i2c2 {
> - compatible = "ti,omap2420-i2c";
> -};
> -
> -#include "omap24xx-clocks.dtsi"
> -#include "omap2420-clocks.dtsi"
> -
> -/* Preferred always-on timer for clockevent */
> -&timer1_target {
> - ti,no-reset-on-init;
> - ti,no-idle;
> - timer@0 {
> - assigned-clocks = <&gpt1_fck>;
> - assigned-clock-parents = <&func_32k_ck>;
> - };
> -};
> diff --git a/arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi
> deleted file mode 100644
> index 4e5ab5189476..000000000000
> --- a/arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi
> +++ /dev/null
> @@ -1,341 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Device Tree Source for OMAP2430 clock data
> - *
> - * Copyright (C) 2014 Texas Instruments, Inc.
> - */
> -
> -&scm_clocks {
> - mcbsp3_mux_fck: mcbsp3_mux_fck@78 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_96m_ck>, <&mcbsp_clks>;
> - reg = <0x78>;
> - };
> -
> - mcbsp3_fck: mcbsp3_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
> - };
> -
> - mcbsp4_mux_fck: mcbsp4_mux_fck@78 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_96m_ck>, <&mcbsp_clks>;
> - ti,bit-shift = <2>;
> - reg = <0x78>;
> - };
> -
> - mcbsp4_fck: mcbsp4_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
> - };
> -
> - mcbsp5_mux_fck: mcbsp5_mux_fck@78 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_96m_ck>, <&mcbsp_clks>;
> - ti,bit-shift = <4>;
> - reg = <0x78>;
> - };
> -
> - mcbsp5_fck: mcbsp5_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
> - };
> -};
> -
> -&prcm_clocks {
> - iva2_1_gate_ick: iva2_1_gate_ick@800 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&dsp_fck>;
> - ti,bit-shift = <0>;
> - reg = <0x0800>;
> - };
> -
> - iva2_1_div_ick: iva2_1_div_ick@840 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-divider-clock";
> - clocks = <&dsp_fck>;
> - ti,bit-shift = <5>;
> - ti,max-div = <3>;
> - reg = <0x0840>;
> - ti,index-starts-at-one;
> - };
> -
> - iva2_1_ick: iva2_1_ick {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
> - };
> -
> - mdm_gate_ick: mdm_gate_ick@c10 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-interface-clock";
> - clocks = <&core_ck>;
> - ti,bit-shift = <0>;
> - reg = <0x0c10>;
> - };
> -
> - mdm_div_ick: mdm_div_ick@c40 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-divider-clock";
> - clocks = <&core_ck>;
> - reg = <0x0c40>;
> - ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>;
> - };
> -
> - mdm_ick: mdm_ick {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&mdm_gate_ick>, <&mdm_div_ick>;
> - };
> -
> - mdm_osc_ck: mdm_osc_ck@c00 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&osc_ck>;
> - ti,bit-shift = <1>;
> - reg = <0x0c00>;
> - };
> -
> - mcbsp3_ick: mcbsp3_ick@214 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <3>;
> - reg = <0x0214>;
> - };
> -
> - mcbsp3_gate_fck: mcbsp3_gate_fck@204 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&mcbsp_clks>;
> - ti,bit-shift = <3>;
> - reg = <0x0204>;
> - };
> -
> - mcbsp4_ick: mcbsp4_ick@214 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <4>;
> - reg = <0x0214>;
> - };
> -
> - mcbsp4_gate_fck: mcbsp4_gate_fck@204 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&mcbsp_clks>;
> - ti,bit-shift = <4>;
> - reg = <0x0204>;
> - };
> -
> - mcbsp5_ick: mcbsp5_ick@214 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <5>;
> - reg = <0x0214>;
> - };
> -
> - mcbsp5_gate_fck: mcbsp5_gate_fck@204 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&mcbsp_clks>;
> - ti,bit-shift = <5>;
> - reg = <0x0204>;
> - };
> -
> - mcspi3_ick: mcspi3_ick@214 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <9>;
> - reg = <0x0214>;
> - };
> -
> - mcspi3_fck: mcspi3_fck@204 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_48m_ck>;
> - ti,bit-shift = <9>;
> - reg = <0x0204>;
> - };
> -
> - icr_ick: icr_ick@410 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&sys_ck>;
> - ti,bit-shift = <6>;
> - reg = <0x0410>;
> - };
> -
> - i2chs1_fck: i2chs1_fck@204 {
> - #clock-cells = <0>;
> - compatible = "ti,omap2430-interface-clock";
> - clocks = <&func_96m_ck>;
> - ti,bit-shift = <19>;
> - reg = <0x0204>;
> - };
> -
> - i2chs2_fck: i2chs2_fck@204 {
> - #clock-cells = <0>;
> - compatible = "ti,omap2430-interface-clock";
> - clocks = <&func_96m_ck>;
> - ti,bit-shift = <20>;
> - reg = <0x0204>;
> - };
> -
> - usbhs_ick: usbhs_ick@214 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&core_l3_ck>;
> - ti,bit-shift = <6>;
> - reg = <0x0214>;
> - };
> -
> - mmchs1_ick: mmchs1_ick@214 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <7>;
> - reg = <0x0214>;
> - };
> -
> - mmchs1_fck: mmchs1_fck@204 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_96m_ck>;
> - ti,bit-shift = <7>;
> - reg = <0x0204>;
> - };
> -
> - mmchs2_ick: mmchs2_ick@214 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <8>;
> - reg = <0x0214>;
> - };
> -
> - mmchs2_fck: mmchs2_fck@204 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_96m_ck>;
> - ti,bit-shift = <8>;
> - reg = <0x0204>;
> - };
> -
> - gpio5_ick: gpio5_ick@214 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <10>;
> - reg = <0x0214>;
> - };
> -
> - gpio5_fck: gpio5_fck@204 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <10>;
> - reg = <0x0204>;
> - };
> -
> - mdm_intc_ick: mdm_intc_ick@214 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <11>;
> - reg = <0x0214>;
> - };
> -
> - mmchsdb1_fck: mmchsdb1_fck@204 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <16>;
> - reg = <0x0204>;
> - };
> -
> - mmchsdb2_fck: mmchsdb2_fck@204 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <17>;
> - reg = <0x0204>;
> - };
> -};
> -
> -&prcm_clockdomains {
> - gfx_clkdm: gfx_clkdm {
> - compatible = "ti,clockdomain";
> - clocks = <&gfx_ick>;
> - };
> -
> - core_l3_clkdm: core_l3_clkdm {
> - compatible = "ti,clockdomain";
> - clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>;
> - };
> -
> - wkup_clkdm: wkup_clkdm {
> - compatible = "ti,clockdomain";
> - clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
> - <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
> - <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>,
> - <&icr_ick>;
> - };
> -
> - dss_clkdm: dss_clkdm {
> - compatible = "ti,clockdomain";
> - clocks = <&dss_ick>, <&dss_54m_fck>;
> - };
> -
> - core_l4_clkdm: core_l4_clkdm {
> - compatible = "ti,clockdomain";
> - clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
> - <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
> - <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
> - <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
> - <&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>,
> - <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
> - <&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>,
> - <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>,
> - <&uart3_fck>, <&cam_ick>, <&mailboxes_ick>,
> - <&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>,
> - <&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>,
> - <&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>,
> - <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
> - <&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>,
> - <&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>,
> - <&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>,
> - <&mmchsdb2_fck>;
> - };
> -
> - mdm_clkdm: mdm_clkdm {
> - compatible = "ti,clockdomain";
> - clocks = <&mdm_osc_ck>;
> - };
> -};
> -
> -&func_96m_ck {
> - compatible = "ti,mux-clock";
> - clocks = <&apll96_ck>, <&alt_ck>;
> - ti,bit-shift = <4>;
> - reg = <0x0540>;
> -};
> -
> -&dsp_div_fck {
> - ti,max-div = <4>;
> - ti,index-starts-at-one;
> -};
> -
> -&ssi_ssr_sst_div_fck {
> - ti,max-div = <5>;
> - ti,index-starts-at-one;
> -};
> diff --git a/arch/arm/boot/dts/ti/omap/omap2430-sdp.dts b/arch/arm/boot/dts/ti/omap/omap2430-sdp.dts
> deleted file mode 100644
> index 207070677e3a..000000000000
> --- a/arch/arm/boot/dts/ti/omap/omap2430-sdp.dts
> +++ /dev/null
> @@ -1,70 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
> - */
> -/dts-v1/;
> -
> -#include "omap2430.dtsi"
> -
> -/ {
> - model = "TI OMAP2430 SDP";
> - compatible = "ti,omap2430-sdp", "ti,omap2430", "ti,omap2";
> -
> - memory@80000000 {
> - device_type = "memory";
> - reg = <0x80000000 0x8000000>; /* 128 MB */
> - };
> -};
> -
> -&i2c2 {
> - clock-frequency = <100000>;
> -
> - twl: twl@48 {
> - reg = <0x48>;
> - interrupts = <7>; /* SYS_NIRQ cascaded to intc */
> - };
> -};
> -
> -#include "twl4030.dtsi"
> -
> -&mmc1 {
> - vmmc-supply = <&vmmc1>;
> - bus-width = <4>;
> -};
> -
> -&gpmc {
> - ranges = <5 0 0x08000000 0x01000000>;
> - ethernet@gpmc {
> - compatible = "smsc,lan91c94";
> - interrupt-parent = <&gpio5>;
> - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */
> - reg = <5 0x300 0xf>;
> - bank-width = <2>;
> - gpmc,sync-clk-ps = <0>;
> - gpmc,mux-add-data = <2>;
> - gpmc,device-width = <1>;
> - gpmc,cycle2cycle-samecsen;
> - gpmc,cycle2cycle-diffcsen;
> - gpmc,cs-on-ns = <6>;
> - gpmc,cs-rd-off-ns = <187>;
> - gpmc,cs-wr-off-ns = <187>;
> - gpmc,adv-on-ns = <18>;
> - gpmc,adv-rd-off-ns = <48>;
> - gpmc,adv-wr-off-ns = <48>;
> - gpmc,oe-on-ns = <60>;
> - gpmc,oe-off-ns = <169>;
> - gpmc,we-on-ns = <66>;
> - gpmc,we-off-ns = <169>;
> - gpmc,rd-cycle-ns = <187>;
> - gpmc,wr-cycle-ns = <187>;
> - gpmc,access-ns = <187>;
> - gpmc,page-burst-access-ns = <24>;
> - gpmc,bus-turnaround-ns = <24>;
> - gpmc,cycle2cycle-delay-ns = <24>;
> - gpmc,wait-monitoring-ns = <0>;
> - gpmc,clk-activation-ns = <0>;
> - gpmc,wr-data-mux-bus-ns = <0>;
> - gpmc,wr-access-ns = <0>;
> - };
> -};
> -
> diff --git a/arch/arm/boot/dts/ti/omap/omap2430.dtsi b/arch/arm/boot/dts/ti/omap/omap2430.dtsi
> deleted file mode 100644
> index 01bd471f9223..000000000000
> --- a/arch/arm/boot/dts/ti/omap/omap2430.dtsi
> +++ /dev/null
> @@ -1,366 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Device Tree Source for OMAP243x SoC
> - *
> - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
> - */
> -
> -#include "omap2.dtsi"
> -
> -/ {
> - compatible = "ti,omap2430", "ti,omap2";
> -
> - ocp {
> - l4_wkup: l4_wkup@49000000 {
> - compatible = "ti,omap2-l4-wkup", "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0 0x49000000 0x31000>;
> -
> - prcm: prcm@6000 {
> - compatible = "ti,omap2-prcm";
> - reg = <0x6000 0x1000>;
> -
> - prcm_clocks: clocks {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - prcm_clockdomains: clockdomains {
> - };
> - };
> -
> - scm: scm@2000 {
> - compatible = "ti,omap2-scm", "simple-bus";
> - reg = <0x2000 0x1000>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - #pinctrl-cells = <1>;
> - ranges = <0 0x2000 0x1000>;
> -
> - omap2430_pmx: pinmux@30 {
> - compatible = "ti,omap2430-padconf",
> - "pinctrl-single";
> - reg = <0x30 0x0154>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - #pinctrl-cells = <1>;
> - pinctrl-single,register-width = <8>;
> - pinctrl-single,function-mask = <0x3f>;
> - };
> -
> - scm_conf: scm_conf@270 {
> - compatible = "ti,omap2-scm-conf", "syscon",
> - "simple-bus";
> - reg = <0x270 0x240>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0 0x270 0x240>;
> -
> - scm_clocks: clocks {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - pbias_regulator: pbias_regulator@230 {
> - compatible = "ti,pbias-omap2", "ti,pbias-omap";
> - reg = <0x230 0x4>;
> - syscon = <&scm_conf>;
> - pbias_mmc_reg: pbias_mmc_omap2430 {
> - regulator-name = "pbias_mmc_omap2430";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <3000000>;
> - };
> - };
> - };
> -
> - scm_clockdomains: clockdomains {
> - };
> - };
> -
> - target-module@20000 {
> - compatible = "ti,sysc-omap2", "ti,sysc";
> - reg = <0x20000 0x4>,
> - <0x20004 0x4>;
> - reg-names = "rev", "sysc";
> - ti,sysc-sidle = <SYSC_IDLE_FORCE>,
> - <SYSC_IDLE_NO>;
> - clocks = <&func_32k_ck>;
> - clock-names = "fck";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0x0 0x20000 0x1000>;
> -
> - counter32k: counter@0 {
> - compatible = "ti,omap-counter32k";
> - reg = <0 0x20>;
> - };
> - };
> - };
> -
> - gpio1: gpio@4900c000 {
> - compatible = "ti,omap2-gpio";
> - reg = <0x4900c000 0x200>;
> - interrupts = <29>;
> - ti,hwmods = "gpio1";
> - ti,gpio-always-on;
> - #gpio-cells = <2>;
> - gpio-controller;
> - #interrupt-cells = <2>;
> - interrupt-controller;
> - };
> -
> - gpio2: gpio@4900e000 {
> - compatible = "ti,omap2-gpio";
> - reg = <0x4900e000 0x200>;
> - interrupts = <30>;
> - ti,hwmods = "gpio2";
> - ti,gpio-always-on;
> - #gpio-cells = <2>;
> - gpio-controller;
> - #interrupt-cells = <2>;
> - interrupt-controller;
> - };
> -
> - gpio3: gpio@49010000 {
> - compatible = "ti,omap2-gpio";
> - reg = <0x49010000 0x200>;
> - interrupts = <31>;
> - ti,hwmods = "gpio3";
> - ti,gpio-always-on;
> - #gpio-cells = <2>;
> - gpio-controller;
> - #interrupt-cells = <2>;
> - interrupt-controller;
> - };
> -
> - gpio4: gpio@49012000 {
> - compatible = "ti,omap2-gpio";
> - reg = <0x49012000 0x200>;
> - interrupts = <32>;
> - ti,hwmods = "gpio4";
> - ti,gpio-always-on;
> - #gpio-cells = <2>;
> - gpio-controller;
> - #interrupt-cells = <2>;
> - interrupt-controller;
> - };
> -
> - gpio5: gpio@480b6000 {
> - compatible = "ti,omap2-gpio";
> - reg = <0x480b6000 0x200>;
> - interrupts = <33>;
> - ti,hwmods = "gpio5";
> - #gpio-cells = <2>;
> - gpio-controller;
> - #interrupt-cells = <2>;
> - interrupt-controller;
> - };
> -
> - gpmc: gpmc@6e000000 {
> - compatible = "ti,omap2430-gpmc";
> - reg = <0x6e000000 0x1000>;
> - #address-cells = <2>;
> - #size-cells = <1>;
> - interrupts = <20>;
> - gpmc,num-cs = <8>;
> - gpmc,num-waitpins = <4>;
> - ti,hwmods = "gpmc";
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - };
> -
> - mcbsp1: mcbsp@48074000 {
> - compatible = "ti,omap2430-mcbsp";
> - reg = <0x48074000 0xff>;
> - reg-names = "mpu";
> - interrupts = <64>, /* OCP compliant interrupt */
> - <59>, /* TX interrupt */
> - <60>, /* RX interrupt */
> - <61>; /* RX overflow interrupt */
> - interrupt-names = "common", "tx", "rx", "rx_overflow";
> - ti,buffer-size = <128>;
> - ti,hwmods = "mcbsp1";
> - dmas = <&sdma 31>,
> - <&sdma 32>;
> - dma-names = "tx", "rx";
> - status = "disabled";
> - };
> -
> - mcbsp2: mcbsp@48076000 {
> - compatible = "ti,omap2430-mcbsp";
> - reg = <0x48076000 0xff>;
> - reg-names = "mpu";
> - interrupts = <16>, /* OCP compliant interrupt */
> - <62>, /* TX interrupt */
> - <63>; /* RX interrupt */
> - interrupt-names = "common", "tx", "rx";
> - ti,buffer-size = <128>;
> - ti,hwmods = "mcbsp2";
> - dmas = <&sdma 33>,
> - <&sdma 34>;
> - dma-names = "tx", "rx";
> - status = "disabled";
> - };
> -
> - mcbsp3: mcbsp@4808c000 {
> - compatible = "ti,omap2430-mcbsp";
> - reg = <0x4808c000 0xff>;
> - reg-names = "mpu";
> - interrupts = <17>, /* OCP compliant interrupt */
> - <89>, /* TX interrupt */
> - <90>; /* RX interrupt */
> - interrupt-names = "common", "tx", "rx";
> - ti,buffer-size = <128>;
> - ti,hwmods = "mcbsp3";
> - dmas = <&sdma 17>,
> - <&sdma 18>;
> - dma-names = "tx", "rx";
> - status = "disabled";
> - };
> -
> - mcbsp4: mcbsp@4808e000 {
> - compatible = "ti,omap2430-mcbsp";
> - reg = <0x4808e000 0xff>;
> - reg-names = "mpu";
> - interrupts = <18>, /* OCP compliant interrupt */
> - <54>, /* TX interrupt */
> - <55>; /* RX interrupt */
> - interrupt-names = "common", "tx", "rx";
> - ti,buffer-size = <128>;
> - ti,hwmods = "mcbsp4";
> - dmas = <&sdma 19>,
> - <&sdma 20>;
> - dma-names = "tx", "rx";
> - status = "disabled";
> - };
> -
> - mcbsp5: mcbsp@48096000 {
> - compatible = "ti,omap2430-mcbsp";
> - reg = <0x48096000 0xff>;
> - reg-names = "mpu";
> - interrupts = <19>, /* OCP compliant interrupt */
> - <81>, /* TX interrupt */
> - <82>; /* RX interrupt */
> - interrupt-names = "common", "tx", "rx";
> - ti,buffer-size = <128>;
> - ti,hwmods = "mcbsp5";
> - dmas = <&sdma 21>,
> - <&sdma 22>;
> - dma-names = "tx", "rx";
> - status = "disabled";
> - };
> -
> - mmc1: mmc@4809c000 {
> - compatible = "ti,omap2-hsmmc";
> - reg = <0x4809c000 0x200>;
> - interrupts = <83>;
> - ti,hwmods = "mmc1";
> - ti,dual-volt;
> - dmas = <&sdma 61>, <&sdma 62>;
> - dma-names = "tx", "rx";
> - pbias-supply = <&pbias_mmc_reg>;
> - };
> -
> - mmc2: mmc@480b4000 {
> - compatible = "ti,omap2-hsmmc";
> - reg = <0x480b4000 0x200>;
> - interrupts = <86>;
> - ti,hwmods = "mmc2";
> - dmas = <&sdma 47>, <&sdma 48>;
> - dma-names = "tx", "rx";
> - };
> -
> - mailbox: mailbox@48094000 {
> - compatible = "ti,omap2-mailbox";
> - reg = <0x48094000 0x200>;
> - interrupts = <26>;
> - ti,hwmods = "mailbox";
> - #mbox-cells = <1>;
> - ti,mbox-num-users = <4>;
> - ti,mbox-num-fifos = <6>;
> - mbox_dsp: mbox-dsp {
> - ti,mbox-tx = <0 0 0>;
> - ti,mbox-rx = <1 0 0>;
> - };
> - };
> -
> - timer1_target: target-module@49018000 {
> - compatible = "ti,sysc-omap2-timer", "ti,sysc";
> - reg = <0x49018000 0x4>,
> - <0x49018010 0x4>,
> - <0x49018014 0x4>;
> - reg-names = "rev", "sysc", "syss";
> - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
> - SYSC_OMAP2_EMUFREE |
> - SYSC_OMAP2_ENAWAKEUP |
> - SYSC_OMAP2_SOFTRESET |
> - SYSC_OMAP2_AUTOIDLE)>;
> - ti,sysc-sidle = <SYSC_IDLE_FORCE>,
> - <SYSC_IDLE_NO>,
> - <SYSC_IDLE_SMART>;
> - ti,syss-mask = <1>;
> - clocks = <&gpt1_fck>, <&gpt1_ick>;
> - clock-names = "fck", "ick";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0x0 0x49018000 0x1000>;
> -
> - timer1: timer@0 {
> - compatible = "ti,omap2420-timer";
> - reg = <0 0x400>;
> - interrupts = <37>;
> - ti,timer-alwon;
> - };
> - };
> -
> - mcspi3: spi@480b8000 {
> - compatible = "ti,omap2-mcspi";
> - ti,hwmods = "mcspi3";
> - reg = <0x480b8000 0x100>;
> - interrupts = <91>;
> - dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>;
> - dma-names = "tx0", "rx0", "tx1", "rx1";
> - };
> -
> - usb_otg_hs: usb_otg_hs@480ac000 {
> - compatible = "ti,omap2-musb";
> - ti,hwmods = "usb_otg_hs";
> - reg = <0x480ac000 0x1000>;
> - interrupts = <93>;
> - };
> -
> - wd_timer2: watchdog@49016000 {
> - compatible = "ti,omap2-wdt";
> - ti,hwmods = "wd_timer2";
> - reg = <0x49016000 0x80>;
> - };
> - };
> -};
> -
> -&sdma {
> - compatible = "ti,omap2430-sdma", "ti,omap-sdma";
> -};
> -
> -&i2c1 {
> - compatible = "ti,omap2430-i2c";
> -};
> -
> -&i2c2 {
> - compatible = "ti,omap2430-i2c";
> -};
> -
> -#include "omap24xx-clocks.dtsi"
> -#include "omap2430-clocks.dtsi"
> -
> -/* Preferred always-on timer for clockevent */
> -&timer1_target {
> - ti,no-reset-on-init;
> - ti,no-idle;
> - timer@0 {
> - assigned-clocks = <&gpt1_fck>;
> - assigned-clock-parents = <&func_32k_ck>;
> - };
> -};
> diff --git a/arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi
> deleted file mode 100644
> index 07af87edf0e2..000000000000
> --- a/arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi
> +++ /dev/null
> @@ -1,1241 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Device Tree Source for OMAP24xx clock data
> - *
> - * Copyright (C) 2014 Texas Instruments, Inc.
> - */
> -&scm_clocks {
> - mcbsp1_mux_fck: mcbsp1_mux_fck@4 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_96m_ck>, <&mcbsp_clks>;
> - ti,bit-shift = <2>;
> - reg = <0x4>;
> - };
> -
> - mcbsp1_fck: mcbsp1_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
> - };
> -
> - mcbsp2_mux_fck: mcbsp2_mux_fck@4 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_96m_ck>, <&mcbsp_clks>;
> - ti,bit-shift = <6>;
> - reg = <0x4>;
> - };
> -
> - mcbsp2_fck: mcbsp2_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
> - };
> -};
> -
> -&prcm_clocks {
> - func_32k_ck: func_32k_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <32768>;
> - };
> -
> - secure_32k_ck: secure_32k_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <32768>;
> - };
> -
> - virt_12m_ck: virt_12m_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <12000000>;
> - };
> -
> - virt_13m_ck: virt_13m_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <13000000>;
> - };
> -
> - virt_19200000_ck: virt_19200000_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <19200000>;
> - };
> -
> - virt_26m_ck: virt_26m_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <26000000>;
> - };
> -
> - aplls_clkin_ck: aplls_clkin_ck@540 {
> - #clock-cells = <0>;
> - compatible = "ti,mux-clock";
> - clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
> - ti,bit-shift = <23>;
> - reg = <0x0540>;
> - };
> -
> - aplls_clkin_x2_ck: aplls_clkin_x2_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&aplls_clkin_ck>;
> - clock-mult = <2>;
> - clock-div = <1>;
> - };
> -
> - osc_ck: osc_ck@60 {
> - #clock-cells = <0>;
> - compatible = "ti,mux-clock";
> - clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
> - ti,bit-shift = <6>;
> - reg = <0x0060>;
> - ti,index-starts-at-one;
> - };
> -
> - sys_ck: sys_ck@60 {
> - #clock-cells = <0>;
> - compatible = "ti,divider-clock";
> - clocks = <&osc_ck>;
> - ti,bit-shift = <6>;
> - ti,max-div = <3>;
> - reg = <0x0060>;
> - ti,index-starts-at-one;
> - };
> -
> - alt_ck: alt_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <54000000>;
> - };
> -
> - mcbsp_clks: mcbsp_clks {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <0x0>;
> - };
> -
> - dpll_ck: dpll_ck@500 {
> - #clock-cells = <0>;
> - compatible = "ti,omap2-dpll-core-clock";
> - clocks = <&sys_ck>, <&sys_ck>;
> - reg = <0x0500>, <0x0540>;
> - };
> -
> - apll96_ck: apll96_ck@500 {
> - #clock-cells = <0>;
> - compatible = "ti,omap2-apll-clock";
> - clocks = <&sys_ck>;
> - ti,bit-shift = <2>;
> - ti,idlest-shift = <8>;
> - ti,clock-frequency = <96000000>;
> - reg = <0x0500>, <0x0530>, <0x0520>;
> - };
> -
> - apll54_ck: apll54_ck@500 {
> - #clock-cells = <0>;
> - compatible = "ti,omap2-apll-clock";
> - clocks = <&sys_ck>;
> - ti,bit-shift = <6>;
> - ti,idlest-shift = <9>;
> - ti,clock-frequency = <54000000>;
> - reg = <0x0500>, <0x0530>, <0x0520>;
> - };
> -
> - func_54m_ck: func_54m_ck@540 {
> - #clock-cells = <0>;
> - compatible = "ti,mux-clock";
> - clocks = <&apll54_ck>, <&alt_ck>;
> - ti,bit-shift = <5>;
> - reg = <0x0540>;
> - };
> -
> - core_ck: core_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&dpll_ck>;
> - clock-mult = <1>;
> - clock-div = <1>;
> - };
> -
> - func_96m_ck: func_96m_ck@540 {
> - #clock-cells = <0>;
> - };
> -
> - apll96_d2_ck: apll96_d2_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&apll96_ck>;
> - clock-mult = <1>;
> - clock-div = <2>;
> - };
> -
> - func_48m_ck: func_48m_ck@540 {
> - #clock-cells = <0>;
> - compatible = "ti,mux-clock";
> - clocks = <&apll96_d2_ck>, <&alt_ck>;
> - ti,bit-shift = <3>;
> - reg = <0x0540>;
> - };
> -
> - func_12m_ck: func_12m_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&func_48m_ck>;
> - clock-mult = <1>;
> - clock-div = <4>;
> - };
> -
> - sys_clkout_src_gate: sys_clkout_src_gate@70 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-no-wait-gate-clock";
> - clocks = <&core_ck>;
> - ti,bit-shift = <7>;
> - reg = <0x0070>;
> - };
> -
> - sys_clkout_src_mux: sys_clkout_src_mux@70 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
> - reg = <0x0070>;
> - };
> -
> - sys_clkout_src: sys_clkout_src {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>;
> - };
> -
> - sys_clkout: sys_clkout@70 {
> - #clock-cells = <0>;
> - compatible = "ti,divider-clock";
> - clocks = <&sys_clkout_src>;
> - ti,bit-shift = <3>;
> - ti,max-div = <64>;
> - reg = <0x0070>;
> - ti,index-power-of-two;
> - };
> -
> - emul_ck: emul_ck@78 {
> - #clock-cells = <0>;
> - compatible = "ti,gate-clock";
> - clocks = <&func_54m_ck>;
> - ti,bit-shift = <0>;
> - reg = <0x0078>;
> - };
> -
> - mpu_ck: mpu_ck@140 {
> - #clock-cells = <0>;
> - compatible = "ti,divider-clock";
> - clocks = <&core_ck>;
> - ti,max-div = <31>;
> - reg = <0x0140>;
> - ti,index-starts-at-one;
> - };
> -
> - dsp_gate_fck: dsp_gate_fck@800 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&core_ck>;
> - ti,bit-shift = <0>;
> - reg = <0x0800>;
> - };
> -
> - dsp_div_fck: dsp_div_fck@840 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-divider-clock";
> - clocks = <&core_ck>;
> - reg = <0x0840>;
> - };
> -
> - dsp_fck: dsp_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&dsp_gate_fck>, <&dsp_div_fck>;
> - };
> -
> - core_l3_ck: core_l3_ck@240 {
> - #clock-cells = <0>;
> - compatible = "ti,divider-clock";
> - clocks = <&core_ck>;
> - ti,max-div = <31>;
> - reg = <0x0240>;
> - ti,index-starts-at-one;
> - };
> -
> - gfx_3d_gate_fck: gfx_3d_gate_fck@300 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&core_l3_ck>;
> - ti,bit-shift = <2>;
> - reg = <0x0300>;
> - };
> -
> - gfx_3d_div_fck: gfx_3d_div_fck@340 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-divider-clock";
> - clocks = <&core_l3_ck>;
> - ti,max-div = <4>;
> - reg = <0x0340>;
> - ti,index-starts-at-one;
> - };
> -
> - gfx_3d_fck: gfx_3d_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>;
> - };
> -
> - gfx_2d_gate_fck: gfx_2d_gate_fck@300 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&core_l3_ck>;
> - ti,bit-shift = <1>;
> - reg = <0x0300>;
> - };
> -
> - gfx_2d_div_fck: gfx_2d_div_fck@340 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-divider-clock";
> - clocks = <&core_l3_ck>;
> - ti,max-div = <4>;
> - reg = <0x0340>;
> - ti,index-starts-at-one;
> - };
> -
> - gfx_2d_fck: gfx_2d_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>;
> - };
> -
> - gfx_ick: gfx_ick@310 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&core_l3_ck>;
> - ti,bit-shift = <0>;
> - reg = <0x0310>;
> - };
> -
> - l4_ck: l4_ck@240 {
> - #clock-cells = <0>;
> - compatible = "ti,divider-clock";
> - clocks = <&core_l3_ck>;
> - ti,bit-shift = <5>;
> - ti,max-div = <3>;
> - reg = <0x0240>;
> - ti,index-starts-at-one;
> - };
> -
> - dss_ick: dss_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-no-wait-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <0>;
> - reg = <0x0210>;
> - };
> -
> - dss1_gate_fck: dss1_gate_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-no-wait-gate-clock";
> - clocks = <&core_ck>;
> - ti,bit-shift = <0>;
> - reg = <0x0200>;
> - };
> -
> - core_d2_ck: core_d2_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&core_ck>;
> - clock-mult = <1>;
> - clock-div = <2>;
> - };
> -
> - core_d3_ck: core_d3_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&core_ck>;
> - clock-mult = <1>;
> - clock-div = <3>;
> - };
> -
> - core_d4_ck: core_d4_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&core_ck>;
> - clock-mult = <1>;
> - clock-div = <4>;
> - };
> -
> - core_d5_ck: core_d5_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&core_ck>;
> - clock-mult = <1>;
> - clock-div = <5>;
> - };
> -
> - core_d6_ck: core_d6_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&core_ck>;
> - clock-mult = <1>;
> - clock-div = <6>;
> - };
> -
> - dummy_ck: dummy_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <0>;
> - };
> -
> - core_d8_ck: core_d8_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&core_ck>;
> - clock-mult = <1>;
> - clock-div = <8>;
> - };
> -
> - core_d9_ck: core_d9_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&core_ck>;
> - clock-mult = <1>;
> - clock-div = <9>;
> - };
> -
> - core_d12_ck: core_d12_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&core_ck>;
> - clock-mult = <1>;
> - clock-div = <12>;
> - };
> -
> - core_d16_ck: core_d16_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&core_ck>;
> - clock-mult = <1>;
> - clock-div = <16>;
> - };
> -
> - dss1_mux_fck: dss1_mux_fck@240 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>;
> - ti,bit-shift = <8>;
> - reg = <0x0240>;
> - };
> -
> - dss1_fck: dss1_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&dss1_gate_fck>, <&dss1_mux_fck>;
> - };
> -
> - dss2_gate_fck: dss2_gate_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-no-wait-gate-clock";
> - clocks = <&func_48m_ck>;
> - ti,bit-shift = <1>;
> - reg = <0x0200>;
> - };
> -
> - dss2_mux_fck: dss2_mux_fck@240 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&sys_ck>, <&func_48m_ck>;
> - ti,bit-shift = <13>;
> - reg = <0x0240>;
> - };
> -
> - dss2_fck: dss2_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&dss2_gate_fck>, <&dss2_mux_fck>;
> - };
> -
> - dss_54m_fck: dss_54m_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_54m_ck>;
> - ti,bit-shift = <2>;
> - reg = <0x0200>;
> - };
> -
> - ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck@204 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&core_ck>;
> - ti,bit-shift = <1>;
> - reg = <0x0204>;
> - };
> -
> - ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck@240 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-divider-clock";
> - clocks = <&core_ck>;
> - ti,bit-shift = <20>;
> - reg = <0x0240>;
> - };
> -
> - ssi_ssr_sst_fck: ssi_ssr_sst_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>;
> - };
> -
> - usb_l4_gate_ick: usb_l4_gate_ick@214 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-interface-clock";
> - clocks = <&core_l3_ck>;
> - ti,bit-shift = <0>;
> - reg = <0x0214>;
> - };
> -
> - usb_l4_div_ick: usb_l4_div_ick@240 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-divider-clock";
> - clocks = <&core_l3_ck>;
> - ti,bit-shift = <25>;
> - reg = <0x0240>;
> - ti,dividers = <0>, <1>, <2>, <0>, <4>;
> - };
> -
> - usb_l4_ick: usb_l4_ick {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
> - };
> -
> - ssi_l4_ick: ssi_l4_ick@214 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <1>;
> - reg = <0x0214>;
> - };
> -
> - gpt1_ick: gpt1_ick@410 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&sys_ck>;
> - ti,bit-shift = <0>;
> - reg = <0x0410>;
> - };
> -
> - gpt1_gate_fck: gpt1_gate_fck@400 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <0>;
> - reg = <0x0400>;
> - };
> -
> - gpt1_mux_fck: gpt1_mux_fck@440 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
> - reg = <0x0440>;
> - };
> -
> - gpt1_fck: gpt1_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
> - };
> -
> - gpt2_ick: gpt2_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <4>;
> - reg = <0x0210>;
> - };
> -
> - gpt2_gate_fck: gpt2_gate_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <4>;
> - reg = <0x0200>;
> - };
> -
> - gpt2_mux_fck: gpt2_mux_fck@244 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
> - ti,bit-shift = <2>;
> - reg = <0x0244>;
> - };
> -
> - gpt2_fck: gpt2_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
> - };
> -
> - gpt3_ick: gpt3_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <5>;
> - reg = <0x0210>;
> - };
> -
> - gpt3_gate_fck: gpt3_gate_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <5>;
> - reg = <0x0200>;
> - };
> -
> - gpt3_mux_fck: gpt3_mux_fck@244 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
> - ti,bit-shift = <4>;
> - reg = <0x0244>;
> - };
> -
> - gpt3_fck: gpt3_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
> - };
> -
> - gpt4_ick: gpt4_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <6>;
> - reg = <0x0210>;
> - };
> -
> - gpt4_gate_fck: gpt4_gate_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <6>;
> - reg = <0x0200>;
> - };
> -
> - gpt4_mux_fck: gpt4_mux_fck@244 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
> - ti,bit-shift = <6>;
> - reg = <0x0244>;
> - };
> -
> - gpt4_fck: gpt4_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
> - };
> -
> - gpt5_ick: gpt5_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <7>;
> - reg = <0x0210>;
> - };
> -
> - gpt5_gate_fck: gpt5_gate_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <7>;
> - reg = <0x0200>;
> - };
> -
> - gpt5_mux_fck: gpt5_mux_fck@244 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
> - ti,bit-shift = <8>;
> - reg = <0x0244>;
> - };
> -
> - gpt5_fck: gpt5_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
> - };
> -
> - gpt6_ick: gpt6_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <8>;
> - reg = <0x0210>;
> - };
> -
> - gpt6_gate_fck: gpt6_gate_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <8>;
> - reg = <0x0200>;
> - };
> -
> - gpt6_mux_fck: gpt6_mux_fck@244 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
> - ti,bit-shift = <10>;
> - reg = <0x0244>;
> - };
> -
> - gpt6_fck: gpt6_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
> - };
> -
> - gpt7_ick: gpt7_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <9>;
> - reg = <0x0210>;
> - };
> -
> - gpt7_gate_fck: gpt7_gate_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <9>;
> - reg = <0x0200>;
> - };
> -
> - gpt7_mux_fck: gpt7_mux_fck@244 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
> - ti,bit-shift = <12>;
> - reg = <0x0244>;
> - };
> -
> - gpt7_fck: gpt7_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
> - };
> -
> - gpt8_ick: gpt8_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <10>;
> - reg = <0x0210>;
> - };
> -
> - gpt8_gate_fck: gpt8_gate_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <10>;
> - reg = <0x0200>;
> - };
> -
> - gpt8_mux_fck: gpt8_mux_fck@244 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
> - ti,bit-shift = <14>;
> - reg = <0x0244>;
> - };
> -
> - gpt8_fck: gpt8_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
> - };
> -
> - gpt9_ick: gpt9_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <11>;
> - reg = <0x0210>;
> - };
> -
> - gpt9_gate_fck: gpt9_gate_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <11>;
> - reg = <0x0200>;
> - };
> -
> - gpt9_mux_fck: gpt9_mux_fck@244 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
> - ti,bit-shift = <16>;
> - reg = <0x0244>;
> - };
> -
> - gpt9_fck: gpt9_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
> - };
> -
> - gpt10_ick: gpt10_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <12>;
> - reg = <0x0210>;
> - };
> -
> - gpt10_gate_fck: gpt10_gate_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <12>;
> - reg = <0x0200>;
> - };
> -
> - gpt10_mux_fck: gpt10_mux_fck@244 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
> - ti,bit-shift = <18>;
> - reg = <0x0244>;
> - };
> -
> - gpt10_fck: gpt10_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
> - };
> -
> - gpt11_ick: gpt11_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <13>;
> - reg = <0x0210>;
> - };
> -
> - gpt11_gate_fck: gpt11_gate_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <13>;
> - reg = <0x0200>;
> - };
> -
> - gpt11_mux_fck: gpt11_mux_fck@244 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
> - ti,bit-shift = <20>;
> - reg = <0x0244>;
> - };
> -
> - gpt11_fck: gpt11_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
> - };
> -
> - gpt12_ick: gpt12_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <14>;
> - reg = <0x0210>;
> - };
> -
> - gpt12_gate_fck: gpt12_gate_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <14>;
> - reg = <0x0200>;
> - };
> -
> - gpt12_mux_fck: gpt12_mux_fck@244 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-mux-clock";
> - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
> - ti,bit-shift = <22>;
> - reg = <0x0244>;
> - };
> -
> - gpt12_fck: gpt12_fck {
> - #clock-cells = <0>;
> - compatible = "ti,composite-clock";
> - clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>;
> - };
> -
> - mcbsp1_ick: mcbsp1_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <15>;
> - reg = <0x0210>;
> - };
> -
> - mcbsp1_gate_fck: mcbsp1_gate_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&mcbsp_clks>;
> - ti,bit-shift = <15>;
> - reg = <0x0200>;
> - };
> -
> - mcbsp2_ick: mcbsp2_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <16>;
> - reg = <0x0210>;
> - };
> -
> - mcbsp2_gate_fck: mcbsp2_gate_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,composite-gate-clock";
> - clocks = <&mcbsp_clks>;
> - ti,bit-shift = <16>;
> - reg = <0x0200>;
> - };
> -
> - mcspi1_ick: mcspi1_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <17>;
> - reg = <0x0210>;
> - };
> -
> - mcspi1_fck: mcspi1_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_48m_ck>;
> - ti,bit-shift = <17>;
> - reg = <0x0200>;
> - };
> -
> - mcspi2_ick: mcspi2_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <18>;
> - reg = <0x0210>;
> - };
> -
> - mcspi2_fck: mcspi2_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_48m_ck>;
> - ti,bit-shift = <18>;
> - reg = <0x0200>;
> - };
> -
> - uart1_ick: uart1_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <21>;
> - reg = <0x0210>;
> - };
> -
> - uart1_fck: uart1_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_48m_ck>;
> - ti,bit-shift = <21>;
> - reg = <0x0200>;
> - };
> -
> - uart2_ick: uart2_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <22>;
> - reg = <0x0210>;
> - };
> -
> - uart2_fck: uart2_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_48m_ck>;
> - ti,bit-shift = <22>;
> - reg = <0x0200>;
> - };
> -
> - uart3_ick: uart3_ick@214 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <2>;
> - reg = <0x0214>;
> - };
> -
> - uart3_fck: uart3_fck@204 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_48m_ck>;
> - ti,bit-shift = <2>;
> - reg = <0x0204>;
> - };
> -
> - gpios_ick: gpios_ick@410 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&sys_ck>;
> - ti,bit-shift = <2>;
> - reg = <0x0410>;
> - };
> -
> - gpios_fck: gpios_fck@400 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <2>;
> - reg = <0x0400>;
> - };
> -
> - mpu_wdt_ick: mpu_wdt_ick@410 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&sys_ck>;
> - ti,bit-shift = <3>;
> - reg = <0x0410>;
> - };
> -
> - mpu_wdt_fck: mpu_wdt_fck@400 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <3>;
> - reg = <0x0400>;
> - };
> -
> - sync_32k_ick: sync_32k_ick@410 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&sys_ck>;
> - ti,bit-shift = <1>;
> - reg = <0x0410>;
> - };
> -
> - wdt1_ick: wdt1_ick@410 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&sys_ck>;
> - ti,bit-shift = <4>;
> - reg = <0x0410>;
> - };
> -
> - omapctrl_ick: omapctrl_ick@410 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&sys_ck>;
> - ti,bit-shift = <5>;
> - reg = <0x0410>;
> - };
> -
> - cam_fck: cam_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,gate-clock";
> - clocks = <&func_96m_ck>;
> - ti,bit-shift = <31>;
> - reg = <0x0200>;
> - };
> -
> - cam_ick: cam_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-no-wait-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <31>;
> - reg = <0x0210>;
> - };
> -
> - mailboxes_ick: mailboxes_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <30>;
> - reg = <0x0210>;
> - };
> -
> - wdt4_ick: wdt4_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <29>;
> - reg = <0x0210>;
> - };
> -
> - wdt4_fck: wdt4_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_32k_ck>;
> - ti,bit-shift = <29>;
> - reg = <0x0200>;
> - };
> -
> - mspro_ick: mspro_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <27>;
> - reg = <0x0210>;
> - };
> -
> - mspro_fck: mspro_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_96m_ck>;
> - ti,bit-shift = <27>;
> - reg = <0x0200>;
> - };
> -
> - fac_ick: fac_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <25>;
> - reg = <0x0210>;
> - };
> -
> - fac_fck: fac_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_12m_ck>;
> - ti,bit-shift = <25>;
> - reg = <0x0200>;
> - };
> -
> - hdq_ick: hdq_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <23>;
> - reg = <0x0210>;
> - };
> -
> - hdq_fck: hdq_fck@200 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_12m_ck>;
> - ti,bit-shift = <23>;
> - reg = <0x0200>;
> - };
> -
> - i2c1_ick: i2c1_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <19>;
> - reg = <0x0210>;
> - };
> -
> - i2c2_ick: i2c2_ick@210 {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <20>;
> - reg = <0x0210>;
> - };
> -
> - gpmc_fck: gpmc_fck@238 {
> - #clock-cells = <0>;
> - compatible = "ti,fixed-factor-clock";
> - clocks = <&core_l3_ck>;
> - ti,clock-div = <1>;
> - ti,autoidle-shift = <1>;
> - reg = <0x0238>;
> - ti,clock-mult = <1>;
> - };
> -
> - sdma_fck: sdma_fck {
> - #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&core_l3_ck>;
> - clock-mult = <1>;
> - clock-div = <1>;
> - };
> -
> - sdma_ick: sdma_ick@238 {
> - #clock-cells = <0>;
> - compatible = "ti,fixed-factor-clock";
> - clocks = <&core_l3_ck>;
> - ti,clock-div = <1>;
> - ti,autoidle-shift = <0>;
> - reg = <0x0238>;
> - ti,clock-mult = <1>;
> - };
> -
> - sdrc_ick: sdrc_ick@238 {
> - #clock-cells = <0>;
> - compatible = "ti,fixed-factor-clock";
> - clocks = <&core_l3_ck>;
> - ti,clock-div = <1>;
> - ti,autoidle-shift = <2>;
> - reg = <0x0238>;
> - ti,clock-mult = <1>;
> - };
> -
> - des_ick: des_ick@21c {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <0>;
> - reg = <0x021c>;
> - };
> -
> - sha_ick: sha_ick@21c {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <1>;
> - reg = <0x021c>;
> - };
> -
> - rng_ick: rng_ick@21c {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <2>;
> - reg = <0x021c>;
> - };
> -
> - aes_ick: aes_ick@21c {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <3>;
> - reg = <0x021c>;
> - };
> -
> - pka_ick: pka_ick@21c {
> - #clock-cells = <0>;
> - compatible = "ti,omap3-interface-clock";
> - clocks = <&l4_ck>;
> - ti,bit-shift = <4>;
> - reg = <0x021c>;
> - };
> -
> - usb_fck: usb_fck@204 {
> - #clock-cells = <0>;
> - compatible = "ti,wait-gate-clock";
> - clocks = <&func_48m_ck>;
> - ti,bit-shift = <0>;
> - reg = <0x0204>;
> - };
> -};
> diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
> index f827f89567fd..2e9597f50c58 100644
> --- a/arch/arm/configs/omap2plus_defconfig
> +++ b/arch/arm/configs/omap2plus_defconfig
> @@ -22,9 +22,7 @@ CONFIG_NAMESPACES=y
> CONFIG_BLK_DEV_INITRD=y
> CONFIG_EXPERT=y
> CONFIG_PROFILING=y
> -CONFIG_ARCH_MULTI_V6=y
> CONFIG_OMAP_RESET_CLOCKS=y
> -CONFIG_ARCH_OMAP2=y
> CONFIG_ARCH_OMAP3=y
> CONFIG_ARCH_OMAP4=y
> CONFIG_SOC_OMAP5=y
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index 79f8afe3a6bf..37ecbfc0a19f 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -5,15 +5,6 @@ menu "TI OMAP/AM/DM/DRA Family"
> config OMAP_HWMOD
> bool
>
> -config ARCH_OMAP2
> - bool "TI OMAP2"
> - depends on ARCH_MULTI_V6
> - depends on !SMP
> - select ARCH_OMAP2PLUS
> - select CPU_ARM1136R0
> - select OMAP_HWMOD
> - select SOC_HAS_OMAP2_SDRC
> -
> config ARCH_OMAP3
> bool "TI OMAP3"
> depends on ARCH_MULTI_V7
> @@ -118,7 +109,7 @@ config ARCH_OMAP2PLUS
> select OMAP_IRQCHIP
> select CLKSRC_TI_32K
> help
> - Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
> + Systems based on OMAP3, OMAP4 or OMAP5
>
> config OMAP_INTERCONNECT_BARRIER
> bool
> @@ -129,7 +120,7 @@ config ARCH_OMAP
>
> if ARCH_OMAP2PLUS
>
> -menu "TI OMAP2/3/4 Specific Features"
> +menu "TI OMAP3/4 Specific Features"
>
> config ARCH_OMAP2PLUS_TYPICAL
> bool "Typical OMAP configuration"
> @@ -138,8 +129,7 @@ config ARCH_OMAP2PLUS_TYPICAL
> select HIGHMEM
> select I2C
> select I2C_OMAP
> - select MENELAUS if ARCH_OMAP2
> - select NEON if CPU_V7
> + select NEON
> select REGULATOR
> select REGULATOR_FIXED_VOLTAGE
> select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
> @@ -204,27 +194,7 @@ config OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
> PPA routine service ID for setting L2 auxiliary control register.
>
> comment "OMAP Core Type"
> - depends on ARCH_OMAP2
> -
> -config SOC_OMAP2420
> - bool "OMAP2420 support (DEPRECATED)"
> - depends on ARCH_OMAP2
> - default y
> - select OMAP_DM_SYSTIMER
> - select OMAP_DM_TIMER
> - select SOC_HAS_OMAP2_SDRC
> - help
> - This SoC is scheduled for removal in early 2027,
> - since it uses the ARM1136r0 CPU revision.
> -
> -config SOC_OMAP2430
> - bool "OMAP2430 support (DEPRECATED)"
> - depends on ARCH_OMAP2
> - default y
> - select SOC_HAS_OMAP2_SDRC
> - help
> - This SoC is scheduled for removal in early 2027,
> - since it uses the ARM1136r0 CPU revision.
> + depends on ARCH_OMAP3
>
> config SOC_OMAP3430
> bool "OMAP3430 support"
> @@ -237,33 +207,9 @@ config SOC_TI81XX
> depends on ARCH_OMAP3
> default y
>
> -comment "OMAP Legacy Platform Data Board Type"
> - depends on ARCH_OMAP2PLUS
> -
> config MACH_OMAP_GENERIC
> bool
>
> -config MACH_OMAP2_TUSB6010
> - bool
> - depends on ARCH_OMAP2 && SOC_OMAP2420
> - default y if MACH_NOKIA_N8X0
> -
> -config MACH_NOKIA_N810
> - bool
> -
> -config MACH_NOKIA_N810_WIMAX
> - bool
> -
> -config MACH_NOKIA_N8X0
> - bool "Nokia N800/N810 (DEPRECATED)"
> - depends on SOC_OMAP2420
> - default y
> - select MACH_NOKIA_N810
> - select MACH_NOKIA_N810_WIMAX
> - help
> - This machine is scheduled for removal in early 2027,
> - since it uses the ARM1136r0 CPU revision.
> -
> endmenu
>
> endif
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index daf21127c82f..6c741442dc0d 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -5,23 +5,17 @@
>
> # Common support
> obj-y := id.o io.o control.o devices.o fb.o pm.o \
> - common.o dma.o omap-headsmp.o sram.o
> + common.o dma.o omap-headsmp.o
>
> -hwmod-common = omap_hwmod.o \
> +# OMAP3 hwmod specific
> +obj-$(CONFIG_ARCH_OMAP3) += sram.o omap_hwmod.o \
> omap_hwmod_common_data.o \
> omap_hwmod_common_ipblock_data.o \
> omap_device.o display.o hdq1w.o \
> i2c.o wd_timer.o
> -clock-common = clock.o
> -secure-common = omap-smc.o omap-secure.o
>
> -obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
> -obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
> -obj-$(CONFIG_ARCH_OMAP4) += $(secure-common)
> -obj-$(CONFIG_SOC_AM33XX) += $(secure-common)
> -obj-$(CONFIG_SOC_OMAP5) += $(secure-common)
> -obj-$(CONFIG_SOC_AM43XX) += $(secure-common)
> -obj-$(CONFIG_SOC_DRA7XX) += $(secure-common)
> +# secure world
> +obj-y += omap-smc.o omap-secure.o
>
> ifneq ($(CONFIG_SND_SOC_OMAP_MCBSP),)
> obj-$(CONFIG_OMAP_HWMOD) += mcbsp.o
> @@ -49,13 +43,7 @@ omap5-dra7-common-$(CONFIG_SOC_HAS_REALTIME_COUNTER) = timer.o
> obj-$(CONFIG_SOC_OMAP5) += $(omap5-dra7-common-y)
> obj-$(CONFIG_SOC_DRA7XX) += $(omap5-dra7-common-y)
>
> -# Functions loaded to SRAM
> -obj-$(CONFIG_SOC_OMAP2420) += sram242x.o
> -obj-$(CONFIG_SOC_OMAP2430) += sram243x.o
> -
> # Restart code (OMAP4/5 currently in omap4-common.c)
> -obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o
> -obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o
> obj-$(CONFIG_SOC_TI81XX) += ti81xx-restart.o
> obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o
> obj-$(CONFIG_SOC_AM43XX) += omap4-restart.o
> @@ -65,7 +53,6 @@ obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
> obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
>
> # SMS/SDRC
> -obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
> # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
>
> # OPP table initialization
> @@ -80,7 +67,6 @@ obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common)
> obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-pm-common)
>
> ifeq ($(CONFIG_PM),y)
> -obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
> obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
> omap-4-5-pm-common += pm44xx.o
> obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common)
> @@ -105,7 +91,6 @@ endif
>
> # PRCM
> obj-y += prm_common.o cm_common.o
> -obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
> omap-prcm-4-5-common = cminst44xx.o prm44xx.o \
> @@ -122,8 +107,6 @@ obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common) \
>
> # OMAP voltage domains
> voltagedomain-common := voltage.o vc.o vp.o
> -obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common)
> -obj-$(CONFIG_ARCH_OMAP2) += voltagedomains2xxx_data.o
> obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
> obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
> @@ -136,9 +119,6 @@ obj-$(CONFIG_SOC_DRA7XX) += $(voltagedomain-common)
>
> # OMAP powerdomain framework
> powerdomain-common += powerdomain.o powerdomain-common.o
> -obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common)
> -obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_data.o
> -obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common)
> obj-$(CONFIG_ARCH_OMAP3) += powerdomains3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
> @@ -155,10 +135,6 @@ obj-$(CONFIG_SOC_DRA7XX) += powerdomains7xx_data.o
>
> # PRCM clockdomain control
> clockdomain-common += clockdomain.o
> -obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common)
> -obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o
> -obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o
> -obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o
> obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common)
> obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
> @@ -176,47 +152,20 @@ obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common)
> obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
>
> # Clock framework
> -obj-$(CONFIG_ARCH_OMAP2) += $(clock-common)
> -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
> -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
> -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o
> -obj-$(CONFIG_ARCH_OMAP3) += $(clock-common)
> -obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
> -obj-$(CONFIG_SOC_AM33XX) += $(clock-common)
> -obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
> -obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
> -obj-$(CONFIG_SOC_AM43XX) += $(clock-common)
> -
> -# OMAP2 clock rate set data (old "OPP" data)
> -obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
> -obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
> +obj-y += clock.o
>
> # hwmod data
> -obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o
> -obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o
> -obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o
> -obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o
> -obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o
> -obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_3xxx_ipblock_data.o
> -obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o
> -obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
> obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
> obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
> obj-$(CONFIG_SOC_TI81XX) += omap_hwmod_81xx_data.o
>
> -# OMAP2420 MSDI controller integration support ("MMC")
> -obj-$(CONFIG_SOC_OMAP2420) += msdi.o
> -
> # Specific board support
> obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o
> -obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
>
> # Platform specific device init code
>
> obj-y += omap_phy_internal.o
>
> -obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
> -
> $(obj)/pm-asm-offsets.h: $(obj)/pm-asm-offsets.s FORCE
> $(call filechk,offsets,__TI_PM_ASM_OFFSETS_H__)
>
> diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
> index bff673e932fe..972b8cf0547f 100644
> --- a/arch/arm/mach-omap2/board-generic.c
> +++ b/arch/arm/mach-omap2/board-generic.c
> @@ -45,40 +45,6 @@ void tick_broadcast(const struct cpumask *mask)
> }
> #endif
>
> -#ifdef CONFIG_SOC_OMAP2420
> -static const char *const omap242x_boards_compat[] __initconst = {
> - "ti,omap2420",
> - NULL,
> -};
> -
> -DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
> - .reserve = omap_reserve,
> - .map_io = omap242x_map_io,
> - .init_early = omap2420_init_early,
> - .init_machine = omap_generic_init,
> - .init_time = omap_init_time_of,
> - .dt_compat = omap242x_boards_compat,
> - .restart = omap2xxx_restart,
> -MACHINE_END
> -#endif
> -
> -#ifdef CONFIG_SOC_OMAP2430
> -static const char *const omap243x_boards_compat[] __initconst = {
> - "ti,omap2430",
> - NULL,
> -};
> -
> -DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
> - .reserve = omap_reserve,
> - .map_io = omap243x_map_io,
> - .init_early = omap2430_init_early,
> - .init_machine = omap_generic_init,
> - .init_time = omap_init_time_of,
> - .dt_compat = omap243x_boards_compat,
> - .restart = omap2xxx_restart,
> -MACHINE_END
> -#endif
> -
> #ifdef CONFIG_ARCH_OMAP3
> /* Some boards need board name for legacy userspace in /proc/cpuinfo */
> static const char *const n900_boards_compat[] __initconst = {
> diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
> deleted file mode 100644
> index d9acd32c5457..000000000000
> --- a/arch/arm/mach-omap2/board-n8x0.c
> +++ /dev/null
> @@ -1,512 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * linux/arch/arm/mach-omap2/board-n8x0.c
> - *
> - * Copyright (C) 2005-2009 Nokia Corporation
> - * Author: Juha Yrjola <juha.yrjola@nokia.com>
> - *
> - * Modified from mach-omap2/board-generic.c
> - */
> -
> -#include <linux/clk.h>
> -#include <linux/delay.h>
> -#include <linux/gpio/machine.h>
> -#include <linux/gpio/consumer.h>
> -#include <linux/init.h>
> -#include <linux/io.h>
> -#include <linux/irq.h>
> -#include <linux/stddef.h>
> -#include <linux/i2c.h>
> -#include <linux/spi/spi.h>
> -#include <linux/usb/musb.h>
> -#include <linux/mmc/host.h>
> -#include <linux/platform_data/mmc-omap.h>
> -#include <linux/mfd/menelaus.h>
> -
> -#include <asm/mach/arch.h>
> -#include <asm/mach-types.h>
> -
> -#include "common.h"
> -#include "mmc.h"
> -#include "usb-tusb6010.h"
> -#include "soc.h"
> -#include "common-board-devices.h"
> -
> -#define TUSB6010_ASYNC_CS 1
> -#define TUSB6010_SYNC_CS 4
> -#define TUSB6010_DMACHAN 0x3f
> -
> -#define NOKIA_N810_WIMAX (1 << 2)
> -#define NOKIA_N810 (1 << 1)
> -#define NOKIA_N800 (1 << 0)
> -
> -static u32 board_caps;
> -
> -#define board_is_n800() (board_caps & NOKIA_N800)
> -#define board_is_n810() (board_caps & NOKIA_N810)
> -#define board_is_n810_wimax() (board_caps & NOKIA_N810_WIMAX)
> -
> -static void board_check_revision(void)
> -{
> - if (of_machine_is_compatible("nokia,n800"))
> - board_caps = NOKIA_N800;
> - else if (of_machine_is_compatible("nokia,n810"))
> - board_caps = NOKIA_N810;
> - else if (of_machine_is_compatible("nokia,n810-wimax"))
> - board_caps = NOKIA_N810_WIMAX;
> -
> - if (!board_caps)
> - pr_err("Unknown board\n");
> -}
> -
> -#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
> -
> -static struct musb_hdrc_config musb_config = {
> - .multipoint = 1,
> - .dyn_fifo = 1,
> - .num_eps = 16,
> - .ram_bits = 12,
> -};
> -
> -static struct musb_hdrc_platform_data tusb_data = {
> - .mode = MUSB_OTG,
> - .min_power = 25, /* x2 = 50 mA drawn from VBUS as peripheral */
> - .power = 100, /* Max 100 mA VBUS for host mode */
> - .config = &musb_config,
> -};
> -
> -static struct gpiod_lookup_table tusb_gpio_table = {
> - .dev_id = "musb-tusb",
> - .table = {
> - GPIO_LOOKUP("gpio-0-31", 0, "enable", GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP("gpio-32-63", 26, "int", GPIO_ACTIVE_HIGH),
> - { }
> - },
> -};
> -
> -static void __init n8x0_usb_init(void)
> -{
> - int ret = 0;
> -
> - gpiod_add_lookup_table(&tusb_gpio_table);
> - ret = tusb6010_setup_interface(&tusb_data, TUSB6010_REFCLK_19, 2,
> - TUSB6010_ASYNC_CS, TUSB6010_SYNC_CS,
> - TUSB6010_DMACHAN);
> - if (ret != 0)
> - return;
> -
> - pr_info("TUSB 6010\n");
> -
> - return;
> -}
> -#else
> -
> -static void __init n8x0_usb_init(void) {}
> -
> -#endif /*CONFIG_USB_MUSB_TUSB6010 */
> -
> -#if defined(CONFIG_MENELAUS) && IS_ENABLED(CONFIG_MMC_OMAP)
> -
> -/*
> - * On both N800 and N810, only the first of the two MMC controllers is in use.
> - * The two MMC slots are multiplexed via Menelaus companion chip over I2C.
> - * On N800, both slots are powered via Menelaus. On N810, only one of the
> - * slots is powered via Menelaus. The N810 EMMC is powered via GPIO.
> - *
> - * VMMC slot 1 on both N800 and N810
> - * VDCDC3_APE and VMCS2_APE slot 2 on N800
> - * GPIO23 and GPIO9 slot 2 EMMC on N810
> - *
> - */
> -static int slot1_cover_open;
> -static int slot2_cover_open;
> -static struct device *mmc_device;
> -
> -static struct gpiod_lookup_table nokia800_mmc_gpio_table = {
> - .dev_id = "mmci-omap.0",
> - .table = {
> - /* Slot switch, GPIO 96 */
> - GPIO_LOOKUP("gpio-96-127", 0, "switch", GPIO_ACTIVE_HIGH),
> - { }
> - },
> -};
> -
> -static struct gpiod_lookup_table nokia810_mmc_gpio_table = {
> - .dev_id = "mmci-omap.0",
> - .table = {
> - /* Slot switch, GPIO 96 */
> - GPIO_LOOKUP("gpio-96-127", 0, "switch", GPIO_ACTIVE_HIGH),
> - /* Slot index 1, VSD power, GPIO 23 */
> - GPIO_LOOKUP_IDX("gpio-0-31", 23, "vsd", 1, GPIO_ACTIVE_HIGH),
> - /* Slot index 1, VIO power, GPIO 9 */
> - GPIO_LOOKUP_IDX("gpio-0-31", 9, "vio", 1, GPIO_ACTIVE_HIGH),
> - { }
> - },
> -};
> -
> -static int n8x0_mmc_set_power_menelaus(struct device *dev, int slot,
> - int power_on, int vdd)
> -{
> - int mV;
> -
> -#ifdef CONFIG_MMC_DEBUG
> - dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1,
> - str_on_off(power_on), vdd);
> -#endif
> - if (slot == 0) {
> - if (!power_on)
> - return menelaus_set_vmmc(0);
> - switch (1 << vdd) {
> - case MMC_VDD_33_34:
> - case MMC_VDD_32_33:
> - case MMC_VDD_31_32:
> - mV = 3100;
> - break;
> - case MMC_VDD_30_31:
> - mV = 3000;
> - break;
> - case MMC_VDD_28_29:
> - mV = 2800;
> - break;
> - case MMC_VDD_165_195:
> - mV = 1850;
> - break;
> - default:
> - BUG();
> - }
> - return menelaus_set_vmmc(mV);
> - } else {
> - if (!power_on)
> - return menelaus_set_vdcdc(3, 0);
> - switch (1 << vdd) {
> - case MMC_VDD_33_34:
> - case MMC_VDD_32_33:
> - mV = 3300;
> - break;
> - case MMC_VDD_30_31:
> - case MMC_VDD_29_30:
> - mV = 3000;
> - break;
> - case MMC_VDD_28_29:
> - case MMC_VDD_27_28:
> - mV = 2800;
> - break;
> - case MMC_VDD_24_25:
> - case MMC_VDD_23_24:
> - mV = 2400;
> - break;
> - case MMC_VDD_22_23:
> - case MMC_VDD_21_22:
> - mV = 2200;
> - break;
> - case MMC_VDD_20_21:
> - mV = 2000;
> - break;
> - case MMC_VDD_165_195:
> - mV = 1800;
> - break;
> - default:
> - BUG();
> - }
> - return menelaus_set_vdcdc(3, mV);
> - }
> - return 0;
> -}
> -
> -static int n8x0_mmc_set_power(struct device *dev, int slot, int power_on,
> - int vdd)
> -{
> - if (board_is_n800() || slot == 0)
> - return n8x0_mmc_set_power_menelaus(dev, slot, power_on, vdd);
> -
> - /* The n810 power will be handled by GPIO code in the driver */
> -
> - return 0;
> -}
> -
> -static int n8x0_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode)
> -{
> - int r;
> -
> - dev_dbg(dev, "Set slot %d bus mode %s\n", slot + 1,
> - bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull");
> - BUG_ON(slot != 0 && slot != 1);
> - slot++;
> - switch (bus_mode) {
> - case MMC_BUSMODE_OPENDRAIN:
> - r = menelaus_set_mmc_opendrain(slot, 1);
> - break;
> - case MMC_BUSMODE_PUSHPULL:
> - r = menelaus_set_mmc_opendrain(slot, 0);
> - break;
> - default:
> - BUG();
> - }
> - if (r != 0 && printk_ratelimit())
> - dev_err(dev, "MMC: unable to set bus mode for slot %d\n",
> - slot);
> - return r;
> -}
> -
> -static int n8x0_mmc_get_cover_state(struct device *dev, int slot)
> -{
> - slot++;
> - BUG_ON(slot != 1 && slot != 2);
> - if (slot == 1)
> - return slot1_cover_open;
> - else
> - return slot2_cover_open;
> -}
> -
> -static void n8x0_mmc_callback(void *data, u8 card_mask)
> -{
> -#ifdef CONFIG_MMC_OMAP
> - int bit, *openp, index;
> -
> - if (board_is_n800()) {
> - bit = 1 << 1;
> - openp = &slot2_cover_open;
> - index = 1;
> - } else {
> - bit = 1;
> - openp = &slot1_cover_open;
> - index = 0;
> - }
> -
> - if (card_mask & bit)
> - *openp = 1;
> - else
> - *openp = 0;
> -
> - omap_mmc_notify_cover_event(mmc_device, index, *openp);
> -#else
> - pr_warn("MMC: notify cover event not available\n");
> -#endif
> -}
> -
> -static int n8x0_mmc_late_init(struct device *dev)
> -{
> - int r, bit, *openp;
> - int vs2sel;
> -
> - mmc_device = dev;
> -
> - r = menelaus_set_slot_sel(1);
> - if (r < 0)
> - return r;
> -
> - if (board_is_n800())
> - vs2sel = 0;
> - else
> - vs2sel = 2;
> -
> - r = menelaus_set_mmc_slot(2, 0, vs2sel, 1);
> - if (r < 0)
> - return r;
> -
> - n8x0_mmc_set_power(dev, 0, MMC_POWER_ON, 16); /* MMC_VDD_28_29 */
> - n8x0_mmc_set_power(dev, 1, MMC_POWER_ON, 16);
> -
> - r = menelaus_set_mmc_slot(1, 1, 0, 1);
> - if (r < 0)
> - return r;
> - r = menelaus_set_mmc_slot(2, 1, vs2sel, 1);
> - if (r < 0)
> - return r;
> -
> - r = menelaus_get_slot_pin_states();
> - if (r < 0)
> - return r;
> -
> - if (board_is_n800()) {
> - bit = 1 << 1;
> - openp = &slot2_cover_open;
> - } else {
> - bit = 1;
> - openp = &slot1_cover_open;
> - slot2_cover_open = 0;
> - }
> -
> - /* All slot pin bits seem to be inversed until first switch change */
> - if (r == 0xf || r == (0xf & ~bit))
> - r = ~r;
> -
> - if (r & bit)
> - *openp = 1;
> - else
> - *openp = 0;
> -
> - r = menelaus_register_mmc_callback(n8x0_mmc_callback, NULL);
> -
> - return r;
> -}
> -
> -static void n8x0_mmc_shutdown(struct device *dev)
> -{
> - int vs2sel;
> -
> - if (board_is_n800())
> - vs2sel = 0;
> - else
> - vs2sel = 2;
> -
> - menelaus_set_mmc_slot(1, 0, 0, 0);
> - menelaus_set_mmc_slot(2, 0, vs2sel, 0);
> -}
> -
> -static void n8x0_mmc_cleanup(struct device *dev)
> -{
> - menelaus_unregister_mmc_callback();
> -}
> -
> -/*
> - * MMC controller1 has two slots that are multiplexed via I2C.
> - * MMC controller2 is not in use.
> - */
> -static struct omap_mmc_platform_data mmc1_data = {
> - .nr_slots = 0,
> - .init = n8x0_mmc_late_init,
> - .cleanup = n8x0_mmc_cleanup,
> - .shutdown = n8x0_mmc_shutdown,
> - .max_freq = 24000000,
> - .slots[0] = {
> - .wires = 4,
> - .set_power = n8x0_mmc_set_power,
> - .set_bus_mode = n8x0_mmc_set_bus_mode,
> - .get_cover_state = n8x0_mmc_get_cover_state,
> - .ocr_mask = MMC_VDD_165_195 | MMC_VDD_30_31 |
> - MMC_VDD_32_33 | MMC_VDD_33_34,
> - .name = "internal",
> - },
> - .slots[1] = {
> - .set_power = n8x0_mmc_set_power,
> - .set_bus_mode = n8x0_mmc_set_bus_mode,
> - .get_cover_state = n8x0_mmc_get_cover_state,
> - .ocr_mask = MMC_VDD_165_195 | MMC_VDD_20_21 |
> - MMC_VDD_21_22 | MMC_VDD_22_23 |
> - MMC_VDD_23_24 | MMC_VDD_24_25 |
> - MMC_VDD_27_28 | MMC_VDD_28_29 |
> - MMC_VDD_29_30 | MMC_VDD_30_31 |
> - MMC_VDD_32_33 | MMC_VDD_33_34,
> - .name = "external",
> - },
> -};
> -
> -static struct omap_mmc_platform_data *mmc_data[OMAP24XX_NR_MMC];
> -
> -static void __init n8x0_mmc_init(void)
> -{
> - if (board_is_n810()) {
> - mmc1_data.slots[0].name = "external";
> -
> - /*
> - * Some Samsung Movinand chips do not like open-ended
> - * multi-block reads and fall to braind-dead state
> - * while doing so. Reducing the number of blocks in
> - * the transfer or delays in clock disable do not help
> - */
> - mmc1_data.slots[1].name = "internal";
> - mmc1_data.slots[1].ban_openended = 1;
> - gpiod_add_lookup_table(&nokia810_mmc_gpio_table);
> - } else {
> - gpiod_add_lookup_table(&nokia800_mmc_gpio_table);
> - }
> -
> - mmc1_data.nr_slots = 2;
> - mmc_data[0] = &mmc1_data;
> -}
> -#else
> -static struct omap_mmc_platform_data mmc1_data;
> -static void __init n8x0_mmc_init(void)
> -{
> -}
> -#endif /* CONFIG_MMC_OMAP */
> -
> -#ifdef CONFIG_MENELAUS
> -
> -static int n8x0_auto_sleep_regulators(void)
> -{
> - u32 val;
> - int ret;
> -
> - val = EN_VPLL_SLEEP | EN_VMMC_SLEEP \
> - | EN_VAUX_SLEEP | EN_VIO_SLEEP \
> - | EN_VMEM_SLEEP | EN_DC3_SLEEP \
> - | EN_VC_SLEEP | EN_DC2_SLEEP;
> -
> - ret = menelaus_set_regulator_sleep(1, val);
> - if (ret < 0) {
> - pr_err("Could not set regulators to sleep on menelaus: %u\n",
> - ret);
> - return ret;
> - }
> - return 0;
> -}
> -
> -static int n8x0_auto_voltage_scale(void)
> -{
> - int ret;
> -
> - ret = menelaus_set_vcore_hw(1400, 1050);
> - if (ret < 0) {
> - pr_err("Could not set VCORE voltage on menelaus: %u\n", ret);
> - return ret;
> - }
> - return 0;
> -}
> -
> -static int n8x0_menelaus_late_init(struct device *dev)
> -{
> - int ret;
> -
> - ret = n8x0_auto_voltage_scale();
> - if (ret < 0)
> - return ret;
> - ret = n8x0_auto_sleep_regulators();
> - if (ret < 0)
> - return ret;
> - return 0;
> -}
> -
> -#else
> -static int n8x0_menelaus_late_init(struct device *dev)
> -{
> - return 0;
> -}
> -#endif
> -
> -struct menelaus_platform_data n8x0_menelaus_platform_data = {
> - .late_init = n8x0_menelaus_late_init,
> -};
> -
> -static struct gpiod_lookup_table nokia810_asoc_gpio_table = {
> - .dev_id = "soc-audio",
> - .table = {
> - GPIO_LOOKUP("gpio-0-15", 10, "headset", GPIO_ACTIVE_HIGH),
> - GPIO_LOOKUP("gpio-80-111", 21, "speaker", GPIO_ACTIVE_HIGH),
> - { }
> - },
> -};
> -
> -static int __init n8x0_late_initcall(void)
> -{
> - if (!board_caps)
> - return -ENODEV;
> -
> - n8x0_mmc_init();
> - n8x0_usb_init();
> - gpiod_add_lookup_table(&nokia810_asoc_gpio_table);
> -
> - return 0;
> -}
> -omap_late_initcall(n8x0_late_initcall);
> -
> -/*
> - * Legacy init pdata init for n8x0. Note that we want to follow the
> - * I2C bus numbering starting at 0 for device tree like other omaps.
> - */
> -void * __init n8x0_legacy_init(void)
> -{
> - board_check_revision();
> - return &mmc1_data;
> -}
> diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c
> deleted file mode 100644
> index 0edebf3355fa..000000000000
> --- a/arch/arm/mach-omap2/clkt2xxx_dpll.c
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * OMAP2-specific DPLL control functions
> - *
> - * Copyright (C) 2011 Nokia Corporation
> - * Paul Walmsley
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/errno.h>
> -#include <linux/clk.h>
> -#include <linux/io.h>
> -
> -#include "clock.h"
> -#include "cm2xxx.h"
> -#include "cm-regbits-24xx.h"
> -
> -/* Private functions */
> -
> -/**
> - * _allow_idle - enable DPLL autoidle bits
> - * @clk: struct clk * of the DPLL to operate on
> - *
> - * Enable DPLL automatic idle control. The DPLL will enter low-power
> - * stop when its downstream clocks are gated. No return value.
> - * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
> - * instead. Add some mechanism to optionally enter this mode.
> - */
> -static void _allow_idle(struct clk_hw_omap *clk)
> -{
> - if (!clk || !clk->dpll_data)
> - return;
> -
> - omap2xxx_cm_set_dpll_auto_low_power_stop();
> -}
> -
> -/**
> - * _deny_idle - prevent DPLL from automatically idling
> - * @clk: struct clk * of the DPLL to operate on
> - *
> - * Disable DPLL automatic idle control. No return value.
> - */
> -static void _deny_idle(struct clk_hw_omap *clk)
> -{
> - if (!clk || !clk->dpll_data)
> - return;
> -
> - omap2xxx_cm_set_dpll_disable_autoidle();
> -}
> -
> -
> -/* Public data */
> -const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = {
> - .allow_idle = _allow_idle,
> - .deny_idle = _deny_idle,
> -};
> diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
> deleted file mode 100644
> index 93f6d3cd9525..000000000000
> --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
> +++ /dev/null
> @@ -1,194 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * DPLL + CORE_CLK composite clock functions
> - *
> - * Copyright (C) 2005-2008 Texas Instruments, Inc.
> - * Copyright (C) 2004-2010 Nokia Corporation
> - *
> - * Contacts:
> - * Richard Woodruff <r-woodruff2@ti.com>
> - * Paul Walmsley
> - *
> - * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
> - * Gordon McNutt and RidgeRun, Inc.
> - *
> - * XXX The DPLL and CORE clocks should be split into two separate clock
> - * types.
> - */
> -#undef DEBUG
> -
> -#include <linux/kernel.h>
> -#include <linux/errno.h>
> -#include <linux/clk.h>
> -#include <linux/clk/ti.h>
> -#include <linux/io.h>
> -
> -#include "clock.h"
> -#include "clock2xxx.h"
> -#include "opp2xxx.h"
> -#include "cm2xxx.h"
> -#include "cm-regbits-24xx.h"
> -#include "sdrc.h"
> -#include "sram.h"
> -
> -/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
> -
> -/*
> - * dpll_core_ck: pointer to the combined dpll_ck + core_ck on OMAP2xxx
> - * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set
> - * during dpll_ck init and used later by omap2xxx_clk_get_core_rate().
> - */
> -static struct clk_hw_omap *dpll_core_ck;
> -
> -/**
> - * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
> - *
> - * Returns the CORE_CLK rate. CORE_CLK can have one of three rate
> - * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
> - * (the latter is unusual). This currently should be called with
> - * struct clk *dpll_ck, which is a composite clock of dpll_ck and
> - * core_ck.
> - */
> -unsigned long omap2xxx_clk_get_core_rate(void)
> -{
> - long long core_clk;
> - u32 v;
> -
> - WARN_ON(!dpll_core_ck);
> -
> - core_clk = omap2_get_dpll_rate(dpll_core_ck);
> -
> - v = omap2xxx_cm_get_core_clk_src();
> -
> - if (v == CORE_CLK_SRC_32K)
> - core_clk = 32768;
> - else
> - core_clk *= v;
> -
> - return core_clk;
> -}
> -
> -/*
> - * Uses the current prcm set to tell if a rate is valid.
> - * You can go slower, but not faster within a given rate set.
> - */
> -static long omap2_dpllcore_round_rate(unsigned long target_rate)
> -{
> - u32 high, low, core_clk_src;
> -
> - core_clk_src = omap2xxx_cm_get_core_clk_src();
> -
> - if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
> - high = curr_prcm_set->dpll_speed * 2;
> - low = curr_prcm_set->dpll_speed;
> - } else { /* DPLL clockout x 2 */
> - high = curr_prcm_set->dpll_speed;
> - low = curr_prcm_set->dpll_speed / 2;
> - }
> -
> -#ifdef DOWN_VARIABLE_DPLL
> - if (target_rate > high)
> - return high;
> - else
> - return target_rate;
> -#else
> - if (target_rate > low)
> - return high;
> - else
> - return low;
> -#endif
> -
> -}
> -
> -unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
> - unsigned long parent_rate)
> -{
> - return omap2xxx_clk_get_core_rate();
> -}
> -
> -int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
> - unsigned long parent_rate)
> -{
> - struct clk_hw_omap *clk = to_clk_hw_omap(hw);
> - u32 cur_rate, low, mult, div, valid_rate, done_rate;
> - u32 bypass = 0;
> - struct prcm_config tmpset;
> - const struct dpll_data *dd;
> -
> - cur_rate = omap2xxx_clk_get_core_rate();
> - mult = omap2xxx_cm_get_core_clk_src();
> -
> - if ((rate == (cur_rate / 2)) && (mult == 2)) {
> - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
> - } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
> - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
> - } else if (rate != cur_rate) {
> - valid_rate = omap2_dpllcore_round_rate(rate);
> - if (valid_rate != rate)
> - return -EINVAL;
> -
> - if (mult == 1)
> - low = curr_prcm_set->dpll_speed;
> - else
> - low = curr_prcm_set->dpll_speed / 2;
> -
> - dd = clk->dpll_data;
> - if (!dd)
> - return -EINVAL;
> -
> - tmpset.cm_clksel1_pll =
> - omap_clk_ll_ops.clk_readl(&dd->mult_div1_reg);
> - tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
> - dd->div1_mask);
> - div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
> - tmpset.cm_clksel2_pll = omap2xxx_cm_get_core_pll_config();
> - tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
> - if (rate > low) {
> - tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
> - mult = ((rate / 2) / 1000000);
> - done_rate = CORE_CLK_SRC_DPLL_X2;
> - } else {
> - tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
> - mult = (rate / 1000000);
> - done_rate = CORE_CLK_SRC_DPLL;
> - }
> - tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
> - tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
> -
> - /* Worst case */
> - tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
> -
> - if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
> - bypass = 1;
> -
> - /* For omap2xxx_sdrc_init_params() */
> - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
> -
> - /* Force dll lock mode */
> - omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
> - bypass);
> -
> - /* Errata: ret dll entry state */
> - omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
> - omap2xxx_sdrc_reprogram(done_rate, 0);
> - }
> -
> - return 0;
> -}
> -
> -/**
> - * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck
> - * @clk: struct clk *dpll_ck
> - *
> - * Store a local copy of @clk in dpll_core_ck so other code can query
> - * the core rate without having to clk_get(), which can sleep. Must
> - * only be called once. No return value. XXX If the clock
> - * registration process is ever changed such that dpll_ck is no longer
> - * statically defined, this code may need to change to increment some
> - * kind of use count on dpll_ck.
> - */
> -void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw)
> -{
> - WARN(dpll_core_ck, "dpll_core_ck already set - should never happen");
> - dpll_core_ck = to_clk_hw_omap(hw);
> -}
> diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
> deleted file mode 100644
> index 2b04e422b46c..000000000000
> --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
> +++ /dev/null
> @@ -1,259 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * OMAP2xxx DVFS virtual clock functions
> - *
> - * Copyright (C) 2005-2008, 2012 Texas Instruments, Inc.
> - * Copyright (C) 2004-2010 Nokia Corporation
> - *
> - * Contacts:
> - * Richard Woodruff <r-woodruff2@ti.com>
> - * Paul Walmsley
> - *
> - * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
> - * Gordon McNutt and RidgeRun, Inc.
> - *
> - * XXX Some of this code should be replaceable by the upcoming OPP layer
> - * code. However, some notion of "rate set" is probably still necessary
> - * for OMAP2xxx at least. Rate sets should be generalized so they can be
> - * used for any OMAP chip, not just OMAP2xxx. In particular, Richard Woodruff
> - * has in the past expressed a preference to use rate sets for OPP changes,
> - * rather than dynamically recalculating the clock tree, so if someone wants
> - * this badly enough to write the code to handle it, we should support it
> - * as an option.
> - */
> -#undef DEBUG
> -
> -#include <linux/kernel.h>
> -#include <linux/errno.h>
> -#include <linux/clk.h>
> -#include <linux/io.h>
> -#include <linux/cpufreq.h>
> -#include <linux/slab.h>
> -
> -#include "soc.h"
> -#include "clock.h"
> -#include "clock2xxx.h"
> -#include "opp2xxx.h"
> -#include "cm2xxx.h"
> -#include "cm-regbits-24xx.h"
> -#include "sdrc.h"
> -#include "sram.h"
> -
> -static u16 cpu_mask;
> -
> -const struct prcm_config *curr_prcm_set;
> -const struct prcm_config *rate_table;
> -
> -/*
> - * sys_ck_rate: the rate of the external high-frequency clock
> - * oscillator on the board. Set by the SoC-specific clock init code.
> - * Once set during a boot, will not change.
> - */
> -static unsigned long sys_ck_rate;
> -
> -/**
> - * omap2_table_mpu_recalc - just return the MPU speed
> - * @clk: virt_prcm_set struct clk
> - *
> - * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
> - */
> -static unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
> - unsigned long parent_rate)
> -{
> - return curr_prcm_set->mpu_speed;
> -}
> -
> -/*
> - * Look for a rate equal or less than the target rate given a configuration set.
> - *
> - * What's not entirely clear is "which" field represents the key field.
> - * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
> - * just uses the ARM rates.
> - */
> -static int omap2_determine_rate_to_table(struct clk_hw *hw,
> - struct clk_rate_request *req)
> -{
> - const struct prcm_config *ptr;
> - long highest_rate;
> -
> - highest_rate = -EINVAL;
> -
> - for (ptr = rate_table; ptr->mpu_speed; ptr++) {
> - if (!(ptr->flags & cpu_mask))
> - continue;
> - if (ptr->xtal_speed != sys_ck_rate)
> - continue;
> -
> - highest_rate = ptr->mpu_speed;
> -
> - /* Can check only after xtal frequency check */
> - if (ptr->mpu_speed <= req->rate)
> - break;
> - }
> - req->rate = highest_rate;
> -
> - return 0;
> -}
> -
> -/* Sets basic clocks based on the specified rate */
> -static int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
> - unsigned long parent_rate)
> -{
> - u32 cur_rate, done_rate, bypass = 0;
> - const struct prcm_config *prcm;
> - unsigned long found_speed = 0;
> - unsigned long flags;
> -
> - for (prcm = rate_table; prcm->mpu_speed; prcm++) {
> - if (!(prcm->flags & cpu_mask))
> - continue;
> -
> - if (prcm->xtal_speed != sys_ck_rate)
> - continue;
> -
> - if (prcm->mpu_speed <= rate) {
> - found_speed = prcm->mpu_speed;
> - break;
> - }
> - }
> -
> - if (!found_speed) {
> - printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
> - rate / 1000000);
> - return -EINVAL;
> - }
> -
> - curr_prcm_set = prcm;
> - cur_rate = omap2xxx_clk_get_core_rate();
> -
> - if (prcm->dpll_speed == cur_rate / 2) {
> - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
> - } else if (prcm->dpll_speed == cur_rate * 2) {
> - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
> - } else if (prcm->dpll_speed != cur_rate) {
> - local_irq_save(flags);
> -
> - if (prcm->dpll_speed == prcm->xtal_speed)
> - bypass = 1;
> -
> - if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
> - CORE_CLK_SRC_DPLL_X2)
> - done_rate = CORE_CLK_SRC_DPLL_X2;
> - else
> - done_rate = CORE_CLK_SRC_DPLL;
> -
> - omap2xxx_cm_set_mod_dividers(prcm->cm_clksel_mpu,
> - prcm->cm_clksel_dsp,
> - prcm->cm_clksel_gfx,
> - prcm->cm_clksel1_core,
> - prcm->cm_clksel_mdm);
> -
> - /* x2 to enter omap2xxx_sdrc_init_params() */
> - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
> -
> - omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
> - bypass);
> -
> - omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
> - omap2xxx_sdrc_reprogram(done_rate, 0);
> -
> - local_irq_restore(flags);
> - }
> -
> - return 0;
> -}
> -
> -/**
> - * omap2xxx_clkt_vps_check_bootloader_rates - determine which of the rate
> - * table sets matches the current CORE DPLL hardware rate
> - *
> - * Check the MPU rate set by bootloader. Sets the 'curr_prcm_set'
> - * global to point to the active rate set when found; otherwise, sets
> - * it to NULL. No return value;
> - */
> -static void omap2xxx_clkt_vps_check_bootloader_rates(void)
> -{
> - const struct prcm_config *prcm = NULL;
> - unsigned long rate;
> -
> - rate = omap2xxx_clk_get_core_rate();
> - for (prcm = rate_table; prcm->mpu_speed; prcm++) {
> - if (!(prcm->flags & cpu_mask))
> - continue;
> - if (prcm->xtal_speed != sys_ck_rate)
> - continue;
> - if (prcm->dpll_speed <= rate)
> - break;
> - }
> - curr_prcm_set = prcm;
> -}
> -
> -/**
> - * omap2xxx_clkt_vps_late_init - store a copy of the sys_ck rate
> - *
> - * Store a copy of the sys_ck rate for later use by the OMAP2xxx DVFS
> - * code. (The sys_ck rate does not -- or rather, must not -- change
> - * during kernel runtime.) Must be called after we have a valid
> - * sys_ck rate, but before the virt_prcm_set clock rate is
> - * recalculated. No return value.
> - */
> -static void omap2xxx_clkt_vps_late_init(void)
> -{
> - struct clk *c;
> -
> - c = clk_get(NULL, "sys_ck");
> - if (IS_ERR(c)) {
> - WARN(1, "could not locate sys_ck\n");
> - } else {
> - sys_ck_rate = clk_get_rate(c);
> - clk_put(c);
> - }
> -}
> -
> -#ifdef CONFIG_OF
> -#include <linux/clk-provider.h>
> -#include <linux/clkdev.h>
> -
> -static const struct clk_ops virt_prcm_set_ops = {
> - .recalc_rate = &omap2_table_mpu_recalc,
> - .set_rate = &omap2_select_table_rate,
> - .determine_rate = &omap2_determine_rate_to_table,
> -};
> -
> -/**
> - * omap2xxx_clkt_vps_init - initialize virt_prcm_set clock
> - *
> - * Does a manual init for the virtual prcm DVFS clock for OMAP2. This
> - * function is called only from omap2 DT clock init, as the virtual
> - * node is not modelled in the DT clock data.
> - */
> -void omap2xxx_clkt_vps_init(void)
> -{
> - struct clk_init_data init = { NULL };
> - struct clk_hw_omap *hw = NULL;
> - struct clk *clk;
> - const char *parent_name = "mpu_ck";
> -
> - omap2xxx_clkt_vps_late_init();
> - omap2xxx_clkt_vps_check_bootloader_rates();
> -
> - hw = kzalloc_obj(*hw);
> - if (!hw)
> - return;
> - init.name = "virt_prcm_set";
> - init.ops = &virt_prcm_set_ops;
> - init.parent_names = &parent_name;
> - init.num_parents = 1;
> -
> - hw->hw.init = &init;
> -
> - clk = clk_register(NULL, &hw->hw);
> - if (IS_ERR(clk)) {
> - printk(KERN_ERR "Failed to register clock\n");
> - kfree(hw);
> - return;
> - }
> -
> - clkdev_create(clk, "cpufreq_ck", NULL);
> -}
> -#endif
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index 83fae51722a9..b73a80503da8 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
> @@ -30,9 +30,7 @@
> #include "clockdomain.h"
> #include "clock.h"
> #include "cm.h"
> -#include "cm2xxx.h"
> #include "cm3xxx.h"
> -#include "cm-regbits-24xx.h"
> #include "cm-regbits-34xx.h"
> #include "common.h"
>
> @@ -94,11 +92,7 @@ void __init ti_clk_init_features(void)
> }
>
> /* Bypass value setup for DPLLs */
> - if (cpu_is_omap24xx()) {
> - features.dpll_bypass_vals |=
> - (1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
> - (1 << OMAP2XXX_EN_DPLL_FRBYPASS);
> - } else if (cpu_is_omap34xx()) {
> + if (cpu_is_omap34xx()) {
> features.dpll_bypass_vals |=
> (1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
> (1 << OMAP3XXX_EN_DPLL_FRBYPASS);
> @@ -122,9 +116,7 @@ void __init ti_clk_init_features(void)
> * 34xx reverses this, just to keep us on our toes
> * AM35xx uses both, depending on the module.
> */
> - if (cpu_is_omap24xx())
> - features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
> - else if (cpu_is_omap34xx())
> + if (cpu_is_omap34xx())
> features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
>
> /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
> diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
> deleted file mode 100644
> index 73c011dadfd2..000000000000
> --- a/arch/arm/mach-omap2/clock2xxx.h
> +++ /dev/null
> @@ -1,17 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * OMAP2 clock function prototypes and macros
> - *
> - * Copyright (C) 2005-2010 Texas Instruments, Inc.
> - * Copyright (C) 2004-2010 Nokia Corporation
> - */
> -
> -#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
> -#define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
> -
> -#include <linux/clk-provider.h>
> -#include "clock.h"
> -
> -unsigned long omap2xxx_clk_get_core_rate(void);
> -
> -#endif
> diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
> index 69dc5b839335..4b5ae1f40d50 100644
> --- a/arch/arm/mach-omap2/clockdomain.c
> +++ b/arch/arm/mach-omap2/clockdomain.c
> @@ -1213,7 +1213,7 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
> int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
> {
> /* The clkdm attribute does not exist yet prior OMAP4 */
> - if (cpu_is_omap24xx() || cpu_is_omap34xx())
> + if (cpu_is_omap34xx())
> return 0;
>
> /*
> @@ -1244,7 +1244,7 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
> int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
> {
> /* The clkdm attribute does not exist yet prior OMAP4 */
> - if (cpu_is_omap24xx() || cpu_is_omap34xx())
> + if (cpu_is_omap34xx())
> return 0;
>
> if (!oh)
> diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
> index 86a2f9e5d0ef..2d422b5f121f 100644
> --- a/arch/arm/mach-omap2/clockdomain.h
> +++ b/arch/arm/mach-omap2/clockdomain.h
> @@ -216,8 +216,6 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
> void clkdm_save_context(void);
> void clkdm_restore_context(void);
>
> -extern void __init omap242x_clockdomains_init(void);
> -extern void __init omap243x_clockdomains_init(void);
> extern void __init omap3xxx_clockdomains_init(void);
> extern void __init am33xx_clockdomains_init(void);
> extern void __init ti814x_clockdomains_init(void);
> @@ -230,14 +228,11 @@ void am43xx_clockdomains_init(void);
> extern void clkdm_add_autodeps(struct clockdomain *clkdm);
> extern void clkdm_del_autodeps(struct clockdomain *clkdm);
>
> -extern struct clkdm_ops omap2_clkdm_operations;
> extern struct clkdm_ops omap3_clkdm_operations;
> extern struct clkdm_ops omap4_clkdm_operations;
> extern struct clkdm_ops am33xx_clkdm_operations;
> extern struct clkdm_ops am43xx_clkdm_operations;
>
> -extern struct clkdm_dep gfx_24xx_wkdeps[];
> -extern struct clkdm_dep dsp_24xx_wkdeps[];
> extern struct clockdomain wkup_common_clkdm;
>
> #endif
> diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c
> deleted file mode 100644
> index ac4ffb5d2ffc..000000000000
> --- a/arch/arm/mach-omap2/clockdomains2420_data.c
> +++ /dev/null
> @@ -1,154 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * OMAP2420 clockdomains
> - *
> - * Copyright (C) 2008-2011 Texas Instruments, Inc.
> - * Copyright (C) 2008-2010 Nokia Corporation
> - *
> - * Paul Walmsley, Jouni Högander
> - *
> - * This file contains clockdomains and clockdomain wakeup dependencies
> - * for OMAP2420 chips. Some notes:
> - *
> - * A useful validation rule for struct clockdomain: Any clockdomain
> - * referenced by a wkdep_srcs must have a dep_bit assigned. So
> - * wkdep_srcs are really just software-controllable dependencies.
> - * Non-software-controllable dependencies do exist, but they are not
> - * encoded below (yet).
> - *
> - * 24xx does not support programmable sleep dependencies (SLEEPDEP)
> - *
> - * The overly-specific dep_bit names are due to a bit name collision
> - * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
> - * value are the same for all powerdomains: 2
> - *
> - * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
> - * sanity check?
> - * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
> - */
> -
> -/*
> - * To-Do List
> - * -> Port the Sleep/Wakeup dependencies for the domains
> - * from the Power domain framework
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/io.h>
> -
> -#include "soc.h"
> -#include "clockdomain.h"
> -#include "prm2xxx_3xxx.h"
> -#include "cm2xxx_3xxx.h"
> -#include "cm-regbits-24xx.h"
> -#include "prm-regbits-24xx.h"
> -
> -/*
> - * Clockdomain dependencies for wkdeps
> - *
> - * XXX Hardware dependencies (e.g., dependencies that cannot be
> - * changed in software) are not included here yet, but should be.
> - */
> -
> -/* Wakeup dependency source arrays */
> -
> -/* 2420-specific possible wakeup dependencies */
> -
> -/* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP */
> -static struct clkdm_dep mpu_2420_wkdeps[] = {
> - { .clkdm_name = "core_l3_clkdm" },
> - { .clkdm_name = "core_l4_clkdm" },
> - { .clkdm_name = "dsp_clkdm" },
> - { .clkdm_name = "wkup_clkdm" },
> - { NULL },
> -};
> -
> -/* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP */
> -static struct clkdm_dep core_2420_wkdeps[] = {
> - { .clkdm_name = "dsp_clkdm" },
> - { .clkdm_name = "gfx_clkdm" },
> - { .clkdm_name = "mpu_clkdm" },
> - { .clkdm_name = "wkup_clkdm" },
> - { NULL },
> -};
> -
> -/*
> - * 2420-only clockdomains
> - */
> -
> -static struct clockdomain mpu_2420_clkdm = {
> - .name = "mpu_clkdm",
> - .pwrdm = { .name = "mpu_pwrdm" },
> - .flags = CLKDM_CAN_HWSUP,
> - .wkdep_srcs = mpu_2420_wkdeps,
> - .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
> -};
> -
> -static struct clockdomain iva1_2420_clkdm = {
> - .name = "iva1_clkdm",
> - .pwrdm = { .name = "dsp_pwrdm" },
> - .flags = CLKDM_CAN_HWSUP_SWSUP,
> - .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
> - .wkdep_srcs = dsp_24xx_wkdeps,
> - .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
> -};
> -
> -static struct clockdomain dsp_2420_clkdm = {
> - .name = "dsp_clkdm",
> - .pwrdm = { .name = "dsp_pwrdm" },
> - .flags = CLKDM_CAN_HWSUP_SWSUP,
> - .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
> -};
> -
> -static struct clockdomain gfx_2420_clkdm = {
> - .name = "gfx_clkdm",
> - .pwrdm = { .name = "gfx_pwrdm" },
> - .flags = CLKDM_CAN_HWSUP_SWSUP,
> - .wkdep_srcs = gfx_24xx_wkdeps,
> - .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
> -};
> -
> -static struct clockdomain core_l3_2420_clkdm = {
> - .name = "core_l3_clkdm",
> - .pwrdm = { .name = "core_pwrdm" },
> - .flags = CLKDM_CAN_HWSUP,
> - .wkdep_srcs = core_2420_wkdeps,
> - .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
> -};
> -
> -static struct clockdomain core_l4_2420_clkdm = {
> - .name = "core_l4_clkdm",
> - .pwrdm = { .name = "core_pwrdm" },
> - .flags = CLKDM_CAN_HWSUP,
> - .wkdep_srcs = core_2420_wkdeps,
> - .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
> -};
> -
> -static struct clockdomain dss_2420_clkdm = {
> - .name = "dss_clkdm",
> - .pwrdm = { .name = "core_pwrdm" },
> - .flags = CLKDM_CAN_HWSUP,
> - .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
> -};
> -
> -static struct clockdomain *clockdomains_omap242x[] __initdata = {
> - &wkup_common_clkdm,
> - &mpu_2420_clkdm,
> - &iva1_2420_clkdm,
> - &dsp_2420_clkdm,
> - &gfx_2420_clkdm,
> - &core_l3_2420_clkdm,
> - &core_l4_2420_clkdm,
> - &dss_2420_clkdm,
> - NULL,
> -};
> -
> -void __init omap242x_clockdomains_init(void)
> -{
> - if (!cpu_is_omap242x())
> - return;
> -
> - clkdm_register_platform_funcs(&omap2_clkdm_operations);
> - clkdm_register_clkdms(clockdomains_omap242x);
> - clkdm_complete_init();
> -}
> diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c
> deleted file mode 100644
> index 0e97e178abaa..000000000000
> --- a/arch/arm/mach-omap2/clockdomains2430_data.c
> +++ /dev/null
> @@ -1,181 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * OMAP2xxx clockdomains
> - *
> - * Copyright (C) 2008-2009 Texas Instruments, Inc.
> - * Copyright (C) 2008-2010 Nokia Corporation
> - *
> - * Paul Walmsley, Jouni Högander
> - *
> - * This file contains clockdomains and clockdomain wakeup dependencies
> - * for OMAP2xxx chips. Some notes:
> - *
> - * A useful validation rule for struct clockdomain: Any clockdomain
> - * referenced by a wkdep_srcs must have a dep_bit assigned. So
> - * wkdep_srcs are really just software-controllable dependencies.
> - * Non-software-controllable dependencies do exist, but they are not
> - * encoded below (yet).
> - *
> - * 24xx does not support programmable sleep dependencies (SLEEPDEP)
> - *
> - * The overly-specific dep_bit names are due to a bit name collision
> - * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
> - * value are the same for all powerdomains: 2
> - *
> - * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
> - * sanity check?
> - * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
> - */
> -
> -/*
> - * To-Do List
> - * -> Port the Sleep/Wakeup dependencies for the domains
> - * from the Power domain framework
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/io.h>
> -
> -#include "soc.h"
> -#include "clockdomain.h"
> -#include "prm2xxx_3xxx.h"
> -#include "cm2xxx_3xxx.h"
> -#include "cm-regbits-24xx.h"
> -#include "prm-regbits-24xx.h"
> -
> -/*
> - * Clockdomain dependencies for wkdeps
> - *
> - * XXX Hardware dependencies (e.g., dependencies that cannot be
> - * changed in software) are not included here yet, but should be.
> - */
> -
> -/* Wakeup dependency source arrays */
> -
> -/* 2430-specific possible wakeup dependencies */
> -
> -/* 2430 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP, MDM */
> -static struct clkdm_dep core_2430_wkdeps[] = {
> - { .clkdm_name = "dsp_clkdm" },
> - { .clkdm_name = "gfx_clkdm" },
> - { .clkdm_name = "mpu_clkdm" },
> - { .clkdm_name = "wkup_clkdm" },
> - { .clkdm_name = "mdm_clkdm" },
> - { NULL },
> -};
> -
> -/* 2430 PM_WKDEP_MPU: CORE, DSP, WKUP, MDM */
> -static struct clkdm_dep mpu_2430_wkdeps[] = {
> - { .clkdm_name = "core_l3_clkdm" },
> - { .clkdm_name = "core_l4_clkdm" },
> - { .clkdm_name = "dsp_clkdm" },
> - { .clkdm_name = "wkup_clkdm" },
> - { .clkdm_name = "mdm_clkdm" },
> - { NULL },
> -};
> -
> -/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
> -static struct clkdm_dep mdm_2430_wkdeps[] = {
> - { .clkdm_name = "core_l3_clkdm" },
> - { .clkdm_name = "core_l4_clkdm" },
> - { .clkdm_name = "mpu_clkdm" },
> - { .clkdm_name = "wkup_clkdm" },
> - { NULL },
> -};
> -
> -/*
> - * 2430-only clockdomains
> - */
> -
> -static struct clockdomain mpu_2430_clkdm = {
> - .name = "mpu_clkdm",
> - .pwrdm = { .name = "mpu_pwrdm" },
> - .flags = CLKDM_CAN_HWSUP_SWSUP,
> - .wkdep_srcs = mpu_2430_wkdeps,
> - .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
> -};
> -
> -/* Another case of bit name collisions between several registers: EN_MDM */
> -static struct clockdomain mdm_clkdm = {
> - .name = "mdm_clkdm",
> - .pwrdm = { .name = "mdm_pwrdm" },
> - .flags = CLKDM_CAN_HWSUP_SWSUP,
> - .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
> - .wkdep_srcs = mdm_2430_wkdeps,
> - .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
> -};
> -
> -static struct clockdomain dsp_2430_clkdm = {
> - .name = "dsp_clkdm",
> - .pwrdm = { .name = "dsp_pwrdm" },
> - .flags = CLKDM_CAN_HWSUP_SWSUP,
> - .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
> - .wkdep_srcs = dsp_24xx_wkdeps,
> - .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
> -};
> -
> -static struct clockdomain gfx_2430_clkdm = {
> - .name = "gfx_clkdm",
> - .pwrdm = { .name = "gfx_pwrdm" },
> - .flags = CLKDM_CAN_HWSUP_SWSUP,
> - .wkdep_srcs = gfx_24xx_wkdeps,
> - .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
> -};
> -
> -/*
> - * XXX add usecounting for clkdm dependencies, otherwise the presence
> - * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
> - * could cause trouble
> - */
> -static struct clockdomain core_l3_2430_clkdm = {
> - .name = "core_l3_clkdm",
> - .pwrdm = { .name = "core_pwrdm" },
> - .flags = CLKDM_CAN_HWSUP,
> - .dep_bit = OMAP24XX_EN_CORE_SHIFT,
> - .wkdep_srcs = core_2430_wkdeps,
> - .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
> -};
> -
> -/*
> - * XXX add usecounting for clkdm dependencies, otherwise the presence
> - * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
> - * could cause trouble
> - */
> -static struct clockdomain core_l4_2430_clkdm = {
> - .name = "core_l4_clkdm",
> - .pwrdm = { .name = "core_pwrdm" },
> - .flags = CLKDM_CAN_HWSUP,
> - .dep_bit = OMAP24XX_EN_CORE_SHIFT,
> - .wkdep_srcs = core_2430_wkdeps,
> - .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
> -};
> -
> -static struct clockdomain dss_2430_clkdm = {
> - .name = "dss_clkdm",
> - .pwrdm = { .name = "core_pwrdm" },
> - .flags = CLKDM_CAN_HWSUP,
> - .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
> -};
> -
> -static struct clockdomain *clockdomains_omap243x[] __initdata = {
> - &wkup_common_clkdm,
> - &mpu_2430_clkdm,
> - &mdm_clkdm,
> - &dsp_2430_clkdm,
> - &gfx_2430_clkdm,
> - &core_l3_2430_clkdm,
> - &core_l4_2430_clkdm,
> - &dss_2430_clkdm,
> - NULL,
> -};
> -
> -void __init omap243x_clockdomains_init(void)
> -{
> - if (!cpu_is_omap243x())
> - return;
> -
> - clkdm_register_platform_funcs(&omap2_clkdm_operations);
> - clkdm_register_clkdms(clockdomains_omap243x);
> - clkdm_complete_init();
> -}
> -
> diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
> index 220c22f5e0f5..4d20c2720660 100644
> --- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
> +++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
> @@ -8,7 +8,7 @@
> * Paul Walmsley, Jouni Högander
> *
> * This file contains clockdomains and clockdomain wakeup/sleep
> - * dependencies for the OMAP2/3 chips. Some notes:
> + * dependencies for the OMAP3 chips. Some notes:
> *
> * A useful validation rule for struct clockdomain: Any clockdomain
> * referenced by a wkdep_srcs or sleepdep_srcs array must have a
> @@ -16,8 +16,6 @@
> * software-controllable dependencies. Non-software-controllable
> * dependencies do exist, but they are not encoded below (yet).
> *
> - * 24xx does not support programmable sleep dependencies (SLEEPDEP)
> - *
> * The overly-specific dep_bit names are due to a bit name collision
> * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
> * value are the same for all powerdomains: 2
> @@ -39,10 +37,8 @@
> #include "clockdomain.h"
> #include "prm2xxx_3xxx.h"
> #include "cm2xxx_3xxx.h"
> -#include "cm-regbits-24xx.h"
> #include "cm-regbits-34xx.h"
> #include "cm-regbits-44xx.h"
> -#include "prm-regbits-24xx.h"
> #include "prm-regbits-34xx.h"
>
> /*
> @@ -54,29 +50,8 @@
>
> /* Wakeup dependency source arrays */
>
> -/* 2xxx-specific possible dependencies */
> -
> -/* 2xxx PM_WKDEP_GFX: CORE, MPU, WKUP */
> -struct clkdm_dep gfx_24xx_wkdeps[] = {
> - { .clkdm_name = "core_l3_clkdm" },
> - { .clkdm_name = "core_l4_clkdm" },
> - { .clkdm_name = "mpu_clkdm" },
> - { .clkdm_name = "wkup_clkdm" },
> - { NULL },
> -};
> -
> -/* 2xxx PM_WKDEP_DSP: CORE, MPU, WKUP */
> -struct clkdm_dep dsp_24xx_wkdeps[] = {
> - { .clkdm_name = "core_l3_clkdm" },
> - { .clkdm_name = "core_l4_clkdm" },
> - { .clkdm_name = "mpu_clkdm" },
> - { .clkdm_name = "wkup_clkdm" },
> - { NULL },
> -};
> -
> -
> /*
> - * OMAP2/3-common clockdomains
> + * OMAP3-common clockdomains
> *
> * Even though the 2420 has a single PRCM module from the
> * interconnect's perspective, internally it does appear to have
> diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
> deleted file mode 100644
> index 59c14dbb6f87..000000000000
> --- a/arch/arm/mach-omap2/cm-regbits-24xx.h
> +++ /dev/null
> @@ -1,51 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
> -#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
> -
> -/*
> - * OMAP24XX Clock Management register bits
> - *
> - * Copyright (C) 2007 Texas Instruments, Inc.
> - * Copyright (C) 2007 Nokia Corporation
> - *
> - * Written by Paul Walmsley
> - */
> -
> -#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
> -#define OMAP24XX_EN_DSS1_MASK (1 << 0)
> -#define OMAP24XX_ST_MAILBOXES_SHIFT 30
> -#define OMAP24XX_ST_HDQ_SHIFT 23
> -#define OMAP2420_ST_I2C2_SHIFT 20
> -#define OMAP2430_ST_I2CHS1_SHIFT 19
> -#define OMAP2420_ST_I2C1_SHIFT 19
> -#define OMAP2430_ST_I2CHS2_SHIFT 20
> -#define OMAP24XX_ST_MCBSP2_SHIFT 16
> -#define OMAP24XX_ST_MCBSP1_SHIFT 15
> -#define OMAP2430_ST_MCBSP5_SHIFT 5
> -#define OMAP2430_ST_MCBSP4_SHIFT 4
> -#define OMAP2430_ST_MCBSP3_SHIFT 3
> -#define OMAP24XX_ST_AES_SHIFT 3
> -#define OMAP24XX_ST_RNG_SHIFT 2
> -#define OMAP24XX_ST_SHA_SHIFT 1
> -#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
> -#define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
> -#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
> -#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
> -#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
> -#define OMAP24XX_ST_MPU_WDT_SHIFT 3
> -#define OMAP24XX_ST_32KSYNC_SHIFT 1
> -#define OMAP24XX_EN_54M_PLL_SHIFT 6
> -#define OMAP24XX_EN_96M_PLL_SHIFT 2
> -#define OMAP24XX_ST_54M_APLL_SHIFT 9
> -#define OMAP24XX_ST_96M_APLL_SHIFT 8
> -#define OMAP24XX_AUTO_54M_MASK (0x3 << 6)
> -#define OMAP24XX_AUTO_96M_MASK (0x3 << 2)
> -#define OMAP24XX_AUTO_DPLL_SHIFT 0
> -#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
> -#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0)
> -#define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
> -#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
> -#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
> -#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
> -#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
> -#endif
> diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
> deleted file mode 100644
> index 1c6d69f4bf49..000000000000
> --- a/arch/arm/mach-omap2/cm2xxx.c
> +++ /dev/null
> @@ -1,302 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * OMAP2xxx CM module functions
> - *
> - * Copyright (C) 2009 Nokia Corporation
> - * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
> - * Paul Walmsley
> - * Rajendra Nayak <rnayak@ti.com>
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/types.h>
> -#include <linux/delay.h>
> -#include <linux/errno.h>
> -#include <linux/err.h>
> -#include <linux/io.h>
> -
> -#include "prm2xxx.h"
> -#include "cm.h"
> -#include "cm2xxx.h"
> -#include "cm-regbits-24xx.h"
> -#include "clockdomain.h"
> -
> -/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
> -#define DPLL_AUTOIDLE_DISABLE 0x0
> -#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
> -
> -/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
> -#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0
> -#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
> -
> -/* CM_IDLEST_PLL bit value offset for APLLs (OMAP2xxx only) */
> -#define EN_APLL_LOCKED 3
> -
> -static const u8 omap2xxx_cm_idlest_offs[] = {
> - CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
> -};
> -
> -/*
> - *
> - */
> -
> -static void _write_clktrctrl(u8 c, s16 module, u32 mask)
> -{
> - u32 v;
> -
> - v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
> - v &= ~mask;
> - v |= c << __ffs(mask);
> - omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
> -}
> -
> -static bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
> -{
> - u32 v;
> -
> - v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
> - v &= mask;
> - v >>= __ffs(mask);
> -
> - return (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
> -}
> -
> -static void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
> -{
> - _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
> -}
> -
> -static void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
> -{
> - _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
> -}
> -
> -/*
> - * DPLL autoidle control
> - */
> -
> -static void _omap2xxx_set_dpll_autoidle(u8 m)
> -{
> - u32 v;
> -
> - v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
> - v &= ~OMAP24XX_AUTO_DPLL_MASK;
> - v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
> - omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
> -}
> -
> -void omap2xxx_cm_set_dpll_disable_autoidle(void)
> -{
> - _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
> -}
> -
> -void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
> -{
> - _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
> -}
> -
> -/**
> - * omap2xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
> - * @idlest_reg: CM_IDLEST* virtual address
> - * @prcm_inst: pointer to an s16 to return the PRCM instance offset
> - * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
> - *
> - * XXX This function is only needed until absolute register addresses are
> - * removed from the OMAP struct clk records.
> - */
> -static int omap2xxx_cm_split_idlest_reg(struct clk_omap_reg *idlest_reg,
> - s16 *prcm_inst,
> - u8 *idlest_reg_id)
> -{
> - unsigned long offs;
> - u8 idlest_offs;
> - int i;
> -
> - idlest_offs = idlest_reg->offset & 0xff;
> - for (i = 0; i < ARRAY_SIZE(omap2xxx_cm_idlest_offs); i++) {
> - if (idlest_offs == omap2xxx_cm_idlest_offs[i]) {
> - *idlest_reg_id = i + 1;
> - break;
> - }
> - }
> -
> - if (i == ARRAY_SIZE(omap2xxx_cm_idlest_offs))
> - return -EINVAL;
> -
> - offs = idlest_reg->offset;
> - offs &= 0xff00;
> - *prcm_inst = offs;
> -
> - return 0;
> -}
> -
> -/*
> - *
> - */
> -
> -/**
> - * omap2xxx_cm_wait_module_ready - wait for a module to leave idle or standby
> - * @part: PRCM partition, ignored for OMAP2
> - * @prcm_mod: PRCM module offset
> - * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
> - * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
> - *
> - * Wait for the PRCM to indicate that the module identified by
> - * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon
> - * success or -EBUSY if the module doesn't enable in time.
> - */
> -static int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
> - u8 idlest_shift)
> -{
> - int ena = 0, i = 0;
> - u8 cm_idlest_reg;
> - u32 mask;
> -
> - if (!idlest_id || (idlest_id > ARRAY_SIZE(omap2xxx_cm_idlest_offs)))
> - return -EINVAL;
> -
> - cm_idlest_reg = omap2xxx_cm_idlest_offs[idlest_id - 1];
> -
> - mask = 1 << idlest_shift;
> - ena = mask;
> -
> - omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
> - mask) == ena), MAX_MODULE_READY_TIME, i);
> -
> - return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
> -}
> -
> -/* Clockdomain low-level functions */
> -
> -static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm)
> -{
> - omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> -}
> -
> -static void omap2xxx_clkdm_deny_idle(struct clockdomain *clkdm)
> -{
> - omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> -}
> -
> -static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
> -{
> - bool hwsup = false;
> -
> - if (!clkdm->clktrctrl_mask)
> - return 0;
> -
> - hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> - if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
> - omap2xxx_clkdm_wakeup(clkdm);
> -
> - return 0;
> -}
> -
> -static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm)
> -{
> - bool hwsup = false;
> -
> - if (!clkdm->clktrctrl_mask)
> - return 0;
> -
> - hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> -
> - if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
> - omap2xxx_clkdm_sleep(clkdm);
> -
> - return 0;
> -}
> -
> -struct clkdm_ops omap2_clkdm_operations = {
> - .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
> - .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
> - .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
> - .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
> - .clkdm_sleep = omap2xxx_clkdm_sleep,
> - .clkdm_wakeup = omap2xxx_clkdm_wakeup,
> - .clkdm_allow_idle = omap2xxx_clkdm_allow_idle,
> - .clkdm_deny_idle = omap2xxx_clkdm_deny_idle,
> - .clkdm_clk_enable = omap2xxx_clkdm_clk_enable,
> - .clkdm_clk_disable = omap2xxx_clkdm_clk_disable,
> -};
> -
> -int omap2xxx_cm_fclks_active(void)
> -{
> - u32 f1, f2;
> -
> - f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
> - f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
> -
> - return (f1 | f2) ? 1 : 0;
> -}
> -
> -int omap2xxx_cm_mpu_retention_allowed(void)
> -{
> - u32 l;
> -
> - /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
> - l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
> - if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
> - OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
> - OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
> - return 0;
> - /* Check for UART3. */
> - l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
> - if (l & OMAP24XX_EN_UART3_MASK)
> - return 0;
> -
> - return 1;
> -}
> -
> -u32 omap2xxx_cm_get_core_clk_src(void)
> -{
> - u32 v;
> -
> - v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
> - v &= OMAP24XX_CORE_CLK_SRC_MASK;
> -
> - return v;
> -}
> -
> -u32 omap2xxx_cm_get_core_pll_config(void)
> -{
> - return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
> -}
> -
> -void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
> -{
> - u32 tmp;
> -
> - omap2_cm_write_mod_reg(mpu, MPU_MOD, CM_CLKSEL);
> - omap2_cm_write_mod_reg(dsp, OMAP24XX_DSP_MOD, CM_CLKSEL);
> - omap2_cm_write_mod_reg(gfx, GFX_MOD, CM_CLKSEL);
> - tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) &
> - OMAP24XX_CLKSEL_DSS2_MASK;
> - omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1);
> - if (mdm)
> - omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL);
> -}
> -
> -/*
> - *
> - */
> -
> -static const struct cm_ll_data omap2xxx_cm_ll_data = {
> - .split_idlest_reg = &omap2xxx_cm_split_idlest_reg,
> - .wait_module_ready = &omap2xxx_cm_wait_module_ready,
> -};
> -
> -int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data)
> -{
> - return cm_register(&omap2xxx_cm_ll_data);
> -}
> -
> -static void __exit omap2xxx_cm_exit(void)
> -{
> - cm_unregister(&omap2xxx_cm_ll_data);
> -}
> -__exitcall(omap2xxx_cm_exit);
> diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
> deleted file mode 100644
> index 7cbeff15ffb0..000000000000
> --- a/arch/arm/mach-omap2/cm2xxx.h
> +++ /dev/null
> @@ -1,60 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * OMAP2xxx Clock Management (CM) register definitions
> - *
> - * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
> - * Copyright (C) 2007-2010 Nokia Corporation
> - * Paul Walmsley
> - *
> - * The CM hardware modules on the OMAP2/3 are quite similar to each
> - * other. The CM modules/instances on OMAP4 are quite different, so
> - * they are handled in a separate file.
> - */
> -#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_H
> -#define __ARCH_ASM_MACH_OMAP2_CM2XXX_H
> -
> -#include "prcm-common.h"
> -#include "cm2xxx_3xxx.h"
> -
> -#define OMAP2420_CM_REGADDR(module, reg) \
> - OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
> -#define OMAP2430_CM_REGADDR(module, reg) \
> - OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
> -
> -/*
> - * Module specific CM register offsets from CM_BASE + domain offset
> - * Use cm_{read,write}_mod_reg() with these registers.
> - * These register offsets generally appear in more than one PRCM submodule.
> - */
> -
> -/* OMAP2-specific register offsets */
> -
> -#define OMAP24XX_CM_FCLKEN2 0x0004
> -#define OMAP24XX_CM_ICLKEN4 0x001c
> -#define OMAP24XX_CM_AUTOIDLE4 0x003c
> -#define OMAP24XX_CM_IDLEST4 0x002c
> -
> -/* CM_IDLEST bit field values to indicate deasserted IdleReq */
> -
> -#define OMAP24XX_CM_IDLEST_VAL 0
> -
> -
> -/* Clock management domain register get/set */
> -
> -#ifndef __ASSEMBLER__
> -
> -extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
> -extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
> -
> -extern int omap2xxx_cm_fclks_active(void);
> -extern int omap2xxx_cm_mpu_retention_allowed(void);
> -extern u32 omap2xxx_cm_get_core_clk_src(void);
> -extern u32 omap2xxx_cm_get_core_pll_config(void);
> -extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
> - u32 mdm);
> -
> -int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data);
> -
> -#endif
> -
> -#endif
> diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
> index 87f2c2d2d754..fc16cd1fd2d5 100644
> --- a/arch/arm/mach-omap2/cm_common.c
> +++ b/arch/arm/mach-omap2/cm_common.c
> @@ -15,7 +15,6 @@
> #include <linux/of.h>
> #include <linux/of_address.h>
>
> -#include "cm2xxx.h"
> #include "cm3xxx.h"
> #include "cm33xx.h"
> #include "cm44xx.h"
> @@ -230,14 +229,6 @@ static struct omap_prcm_init_data cm2_data __initdata = {
> };
> #endif
>
> -#ifdef CONFIG_ARCH_OMAP2
> -static struct omap_prcm_init_data omap2_prcm_data __initdata = {
> - .index = TI_CLKM_CM,
> - .init = omap2xxx_cm_init,
> - .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
> -};
> -#endif
> -
> #ifdef CONFIG_ARCH_OMAP3
> static struct omap_prcm_init_data omap3_cm_data __initdata = {
> .index = TI_CLKM_CM,
> @@ -269,9 +260,6 @@ static struct omap_prcm_init_data am4_prcm_data __initdata = {
> #endif
>
> static const struct of_device_id omap_cm_dt_match_table[] __initconst = {
> -#ifdef CONFIG_ARCH_OMAP2
> - { .compatible = "ti,omap2-prcm", .data = &omap2_prcm_data },
> -#endif
> #ifdef CONFIG_ARCH_OMAP3
> { .compatible = "ti,omap3-cm", .data = &omap3_cm_data },
> #endif
> diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
> deleted file mode 100644
> index 69694af71475..000000000000
> --- a/arch/arm/mach-omap2/common-board-devices.h
> +++ /dev/null
> @@ -1,11 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -#ifndef __OMAP_COMMON_BOARD_DEVICES__
> -#define __OMAP_COMMON_BOARD_DEVICES__
> -
> -#include <linux/mfd/menelaus.h>
> -
> -void *n8x0_legacy_init(void);
> -
> -extern struct menelaus_platform_data n8x0_menelaus_platform_data;
> -
> -#endif /* __OMAP_COMMON_BOARD_DEVICES__ */
> diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
> index 9d60799e9752..f8ed97044ade 100644
> --- a/arch/arm/mach-omap2/common.h
> +++ b/arch/arm/mach-omap2/common.h
> @@ -102,8 +102,6 @@ static inline void omap5_realtime_timer_init(void)
> }
> #endif
>
> -void omap2420_init_early(void);
> -void omap2430_init_early(void);
> void omap3430_init_early(void);
> void omap3630_init_early(void);
> void am33xx_init_early(void);
> @@ -130,14 +128,6 @@ static inline void omap_soc_device_init(void)
> }
> #endif
>
> -#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
> -void omap2xxx_restart(enum reboot_mode mode, const char *cmd);
> -#else
> -static inline void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
> -{
> -}
> -#endif
> -
> #ifdef CONFIG_SOC_AM33XX
> void am33xx_restart(enum reboot_mode mode, const char *cmd);
> #else
> @@ -183,8 +173,6 @@ static inline void omap_barrier_reserve_memblock(void)
> /* This gets called from mach-omap2/io.c, do not call this */
> void __init omap2_set_globals_tap(u32 class, void __iomem *tap);
>
> -void __init omap242x_map_io(void);
> -void __init omap243x_map_io(void);
> void __init omap3_map_io(void);
> void __init am33xx_map_io(void);
> void __init omap4_map_io(void);
> diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
> index 7e7440533bf9..3ab1c6e6dde6 100644
> --- a/arch/arm/mach-omap2/control.h
> +++ b/arch/arm/mach-omap2/control.h
> @@ -19,19 +19,11 @@
> #include "am33xx.h"
>
> #ifndef __ASSEMBLY__
> -#define OMAP242X_CTRL_REGADDR(reg) \
> - OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
> -#define OMAP243X_CTRL_REGADDR(reg) \
> - OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
> #define OMAP343X_CTRL_REGADDR(reg) \
> OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
> #define AM33XX_CTRL_REGADDR(reg) \
> AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
> #else
> -#define OMAP242X_CTRL_REGADDR(reg) \
> - OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
> -#define OMAP243X_CTRL_REGADDR(reg) \
> - OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
> #define OMAP343X_CTRL_REGADDR(reg) \
> OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
> #define AM33XX_CTRL_REGADDR(reg) \
> @@ -74,52 +66,6 @@
> #define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
> #define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
>
> -/* 242x-only CONTROL_GENERAL register offsets */
> -#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
> -#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
> -
> -/* 243x-only CONTROL_GENERAL register offsets */
> -/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
> -#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
> -#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
> -#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
> -#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
> -#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
> -#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
> -
> -/* 24xx-only CONTROL_GENERAL register offsets */
> -#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
> -#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
> -#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
> -#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
> -#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
> -#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
> -#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
> -#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
> -#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
> -#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
> -#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
> -#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
> -#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
> -#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
> -#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
> -#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
> -#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
> -#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
> -#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
> -#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
> -#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
> -#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
> -#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
> -#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
> -#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
> -#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
> -#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
> -#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
> -#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
> -#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
> -#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
> -
> #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
>
> /* 34xx-only CONTROL_GENERAL register offsets */
> @@ -311,14 +257,12 @@
> */
> /* CONTROL_DEVCONF0 bits */
> #define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
> -#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
> #define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
> #define OMAP2_MCBSP1_FSR_MASK (1 << 4)
> #define OMAP2_MCBSP1_CLKR_MASK (1 << 3)
> #define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
>
> /* CONTROL_DEVCONF1 bits */
> -#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
> #define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
> #define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
> #define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
> diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
> index dbec3bb9fbf4..addc14898bd5 100644
> --- a/arch/arm/mach-omap2/display.c
> +++ b/arch/arm/mach-omap2/display.c
> @@ -124,9 +124,7 @@ static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
>
> static enum omapdss_version __init omap_display_get_version(void)
> {
> - if (cpu_is_omap24xx())
> - return OMAPDSS_VER_OMAP24xx;
> - else if (cpu_is_omap3630())
> + if (cpu_is_omap3630())
> return OMAPDSS_VER_OMAP3630;
> else if (cpu_is_omap34xx()) {
> if (soc_is_am35xx()) {
> diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
> index 830cd4e7eb44..3a6b7b4620ca 100644
> --- a/arch/arm/mach-omap2/dma.c
> +++ b/arch/arm/mach-omap2/dma.c
> @@ -82,39 +82,6 @@ static unsigned configure_dma_errata(void)
> {
> unsigned errata = 0;
>
> - /*
> - * Errata applicable for OMAP2430ES1.0 and all omap2420
> - *
> - * I.
> - * Erratum ID: Not Available
> - * Inter Frame DMA buffering issue DMA will wrongly
> - * buffer elements if packing and bursting is enabled. This might
> - * result in data gets stalled in FIFO at the end of the block.
> - * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
> - * guarantee no data will stay in the DMA FIFO in case inter frame
> - * buffering occurs
> - *
> - * II.
> - * Erratum ID: Not Available
> - * DMA may hang when several channels are used in parallel
> - * In the following configuration, DMA channel hanging can occur:
> - * a. Channel i, hardware synchronized, is enabled
> - * b. Another channel (Channel x), software synchronized, is enabled.
> - * c. Channel i is disabled before end of transfer
> - * d. Channel i is reenabled.
> - * e. Steps 1 to 4 are repeated a certain number of times.
> - * f. A third channel (Channel y), software synchronized, is enabled.
> - * Channel x and Channel y may hang immediately after step 'f'.
> - * Workaround:
> - * For any channel used - make sure NextLCH_ID is set to the value j.
> - */
> - if (cpu_is_omap2420() || (cpu_is_omap2430() &&
> - (omap_type() == OMAP2430_REV_ES1_0))) {
> -
> - SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
> - SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
> - }
> -
> /*
> * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
> * after a transaction error.
> @@ -162,16 +129,6 @@ static unsigned configure_dma_errata(void)
> return errata;
> }
>
> -static const struct dma_slave_map omap24xx_sdma_dt_map[] = {
> - /* external DMA requests when tusb6010 is used */
> - { "musb-hdrc.1.auto", "dmareq0", SDMA_FILTER_PARAM(2) },
> - { "musb-hdrc.1.auto", "dmareq1", SDMA_FILTER_PARAM(3) },
> - { "musb-hdrc.1.auto", "dmareq2", SDMA_FILTER_PARAM(14) }, /* OMAP2420 only */
> - { "musb-hdrc.1.auto", "dmareq3", SDMA_FILTER_PARAM(15) }, /* OMAP2420 only */
> - { "musb-hdrc.1.auto", "dmareq4", SDMA_FILTER_PARAM(16) }, /* OMAP2420 only */
> - { "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */
> -};
> -
> static struct omap_dma_dev_attr dma_attr = {
> .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
> IS_CSSA_32 | IS_CDSA_32,
> @@ -188,15 +145,7 @@ struct omap_system_dma_plat_info dma_plat_info = {
> static int __init omap2_system_dma_init(void)
> {
> dma_plat_info.errata = configure_dma_errata();
> -
> - if (soc_is_omap24xx()) {
> - /* DMA slave map for drivers not yet converted to DT */
> - dma_plat_info.slave_map = omap24xx_sdma_dt_map;
> - dma_plat_info.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
> - }
> -
> - if (!soc_is_omap242x())
> - dma_attr.dev_caps |= IS_RW_PRIORITY;
> + dma_attr.dev_caps |= IS_RW_PRIORITY;
>
> if (soc_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
> dma_attr.dev_caps |= HS_CHANNELS_RESERVED;
> diff --git a/arch/arm/mach-omap2/fb.c b/arch/arm/mach-omap2/fb.c
> index 0f8c8efe3ae8..9a425c36f996 100644
> --- a/arch/arm/mach-omap2/fb.c
> +++ b/arch/arm/mach-omap2/fb.c
> @@ -27,15 +27,6 @@
> * The first memory resource is the register region for VRFB,
> * the rest are VRFB virtual memory areas for each VRFB context.
> */
> -
> -static const struct resource omap2_vrfb_resources[] = {
> - DEFINE_RES_MEM_NAMED(0x68008000u, 0x40, "vrfb-regs"),
> - DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
> - DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
> - DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
> - DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
> -};
> -
> static const struct resource omap3_vrfb_resources[] = {
> DEFINE_RES_MEM_NAMED(0x6C000180u, 0xc0, "vrfb-regs"),
> DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
> @@ -58,10 +49,7 @@ int __init omap_init_vrfb(void)
> const struct resource *res;
> unsigned int num_res;
>
> - if (cpu_is_omap24xx()) {
> - res = omap2_vrfb_resources;
> - num_res = ARRAY_SIZE(omap2_vrfb_resources);
> - } else if (cpu_is_omap34xx()) {
> + if (cpu_is_omap34xx()) {
> res = omap3_vrfb_resources;
> num_res = ARRAY_SIZE(omap3_vrfb_resources);
> } else {
> diff --git a/arch/arm/mach-omap2/gpmc.h b/arch/arm/mach-omap2/gpmc.h
> deleted file mode 100644
> index e060f1b5c27d..000000000000
> --- a/arch/arm/mach-omap2/gpmc.h
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * General-Purpose Memory Controller for OMAP2
> - *
> - * Copyright (C) 2005-2006 Nokia Corporation
> - *
> - * Do not include this file in any new code, this will get removed
> - * once omap3 boots in device tree only mode.
> - */
> -#include <linux/omap-gpmc.h>
> diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
> index 3b4b9514f4fa..d956c70f8899 100644
> --- a/arch/arm/mach-omap2/i2c.c
> +++ b/arch/arm/mach-omap2/i2c.c
> @@ -39,7 +39,7 @@ int omap_i2c_reset(struct omap_hwmod *oh)
> u16 i2c_con;
> int c = 0;
>
> - if (soc_is_omap24xx() || soc_is_omap34xx() || soc_is_am35xx())
> + if (soc_is_omap34xx() || soc_is_am35xx())
> i2c_con = OMAP2_I2C_CON_OFFSET;
> else
> i2c_con = OMAP4_I2C_CON_OFFSET;
> diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
> index cf2bfb447ee2..3e731dd21311 100644
> --- a/arch/arm/mach-omap2/id.c
> +++ b/arch/arm/mach-omap2/id.c
> @@ -55,9 +55,7 @@ int omap_type(void)
> if (val < OMAP2_DEVICETYPE_MASK)
> return val;
>
> - if (soc_is_omap24xx()) {
> - val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
> - } else if (soc_is_ti81xx()) {
> + if (soc_is_ti81xx()) {
> val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
> } else if (soc_is_am33xx() || soc_is_am43xx()) {
> val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
> @@ -99,22 +97,6 @@ EXPORT_SYMBOL(omap_type);
>
> #define read_tap_reg(reg) readl_relaxed(tap_base + (reg))
>
> -struct omap_id {
> - u16 hawkeye; /* Silicon type (Hawkeye id) */
> - u8 dev; /* Device type from production_id reg */
> - u32 type; /* Combined type id copied to omap_revision */
> -};
> -
> -/* Register values to detect the OMAP version */
> -static struct omap_id omap_ids[] __initdata = {
> - { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
> - { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
> - { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
> - { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
> - { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
> - { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
> -};
> -
> static void __iomem *tap_base;
> static u16 tap_prod_id;
>
> @@ -145,62 +127,6 @@ static int __init omap_feed_randpool(void)
> }
> omap_device_initcall(omap_feed_randpool);
>
> -void __init omap2xxx_check_revision(void)
> -{
> - int i, j;
> - u32 idcode, prod_id;
> - u16 hawkeye;
> - u8 dev_type, rev;
> - struct omap_die_id odi;
> -
> - idcode = read_tap_reg(OMAP_TAP_IDCODE);
> - prod_id = read_tap_reg(tap_prod_id);
> - hawkeye = (idcode >> 12) & 0xffff;
> - rev = (idcode >> 28) & 0x0f;
> - dev_type = (prod_id >> 16) & 0x0f;
> - omap_get_die_id(&odi);
> -
> - pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
> - idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
> - pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
> - pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
> - odi.id_1, (odi.id_1 >> 28) & 0xf);
> - pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
> - pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
> - pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
> - prod_id, dev_type);
> -
> - /* Check hawkeye ids */
> - for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
> - if (hawkeye == omap_ids[i].hawkeye)
> - break;
> - }
> -
> - if (i == ARRAY_SIZE(omap_ids)) {
> - printk(KERN_ERR "Unknown OMAP CPU id\n");
> - return;
> - }
> -
> - for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
> - if (dev_type == omap_ids[j].dev)
> - break;
> - }
> -
> - if (j == ARRAY_SIZE(omap_ids)) {
> - pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
> - omap_ids[i].type >> 16);
> - j = i;
> - }
> -
> - sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
> - sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
> -
> - pr_info("%s", soc_name);
> - if ((omap_rev() >> 8) & 0x0f)
> - pr_cont("%s", soc_rev);
> - pr_cont("\n");
> -}
> -
> #define OMAP3_SHOW_FEATURE(feat) \
> if (omap3_has_ ##feat()) \
> n += scnprintf(buf + n, sizeof(buf) - n, #feat " ");
> @@ -750,9 +676,7 @@ static const char * const omap_types[] = {
>
> static const char * __init omap_get_family(void)
> {
> - if (soc_is_omap24xx())
> - return kasprintf(GFP_KERNEL, "OMAP2");
> - else if (soc_is_omap34xx())
> + if (soc_is_omap34xx())
> return kasprintf(GFP_KERNEL, "OMAP3");
> else if (soc_is_omap44xx())
> return kasprintf(GFP_KERNEL, "OMAP4");
> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
> index 14ec3f78000b..1c945be5e7cc 100644
> --- a/arch/arm/mach-omap2/io.c
> +++ b/arch/arm/mach-omap2/io.c
> @@ -35,7 +35,6 @@
> #include "sdrc.h"
> #include "control.h"
> #include "sram.h"
> -#include "cm2xxx.h"
> #include "cm3xxx.h"
> #include "cm33xx.h"
> #include "cm44xx.h"
> @@ -43,11 +42,9 @@
> #include "cm.h"
> #include "prcm_mpu44xx.h"
> #include "prminst44xx.h"
> -#include "prm2xxx.h"
> #include "prm3xxx.h"
> #include "prm33xx.h"
> #include "prm44xx.h"
> -#include "opp2xxx.h"
> #include "omap-secure.h"
>
> /*
> @@ -61,76 +58,6 @@ static int (*omap_clk_soc_init)(void);
> * default mapping provided here.
> */
>
> -#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
> -static struct map_desc omap24xx_io_desc[] __initdata = {
> - {
> - .virtual = L3_24XX_VIRT,
> - .pfn = __phys_to_pfn(L3_24XX_PHYS),
> - .length = L3_24XX_SIZE,
> - .type = MT_DEVICE
> - },
> - {
> - .virtual = L4_24XX_VIRT,
> - .pfn = __phys_to_pfn(L4_24XX_PHYS),
> - .length = L4_24XX_SIZE,
> - .type = MT_DEVICE
> - },
> -};
> -
> -#ifdef CONFIG_SOC_OMAP2420
> -static struct map_desc omap242x_io_desc[] __initdata = {
> - {
> - .virtual = DSP_MEM_2420_VIRT,
> - .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
> - .length = DSP_MEM_2420_SIZE,
> - .type = MT_DEVICE
> - },
> - {
> - .virtual = DSP_IPI_2420_VIRT,
> - .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
> - .length = DSP_IPI_2420_SIZE,
> - .type = MT_DEVICE
> - },
> - {
> - .virtual = DSP_MMU_2420_VIRT,
> - .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
> - .length = DSP_MMU_2420_SIZE,
> - .type = MT_DEVICE
> - },
> -};
> -
> -#endif
> -
> -#ifdef CONFIG_SOC_OMAP2430
> -static struct map_desc omap243x_io_desc[] __initdata = {
> - {
> - .virtual = L4_WK_243X_VIRT,
> - .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
> - .length = L4_WK_243X_SIZE,
> - .type = MT_DEVICE
> - },
> - {
> - .virtual = OMAP243X_GPMC_VIRT,
> - .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
> - .length = OMAP243X_GPMC_SIZE,
> - .type = MT_DEVICE
> - },
> - {
> - .virtual = OMAP243X_SDRC_VIRT,
> - .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
> - .length = OMAP243X_SDRC_SIZE,
> - .type = MT_DEVICE
> - },
> - {
> - .virtual = OMAP243X_SMS_VIRT,
> - .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
> - .length = OMAP243X_SMS_SIZE,
> - .type = MT_DEVICE
> - },
> -};
> -#endif
> -#endif
> -
> #ifdef CONFIG_ARCH_OMAP3
> static struct map_desc omap34xx_io_desc[] __initdata = {
> {
> @@ -305,22 +232,6 @@ static struct map_desc dra7xx_io_desc[] __initdata = {
> };
> #endif
>
> -#ifdef CONFIG_SOC_OMAP2420
> -void __init omap242x_map_io(void)
> -{
> - iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
> - iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
> -}
> -#endif
> -
> -#ifdef CONFIG_SOC_OMAP2430
> -void __init omap243x_map_io(void)
> -{
> - iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
> - iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
> -}
> -#endif
> -
> #ifdef CONFIG_ARCH_OMAP3
> void __init omap3_map_io(void)
> {
> @@ -365,6 +276,8 @@ void __init dra7xx_map_io(void)
> omap_barriers_init();
> }
> #endif
> +
> +#ifdef CONFIG_ARCH_OMAP3
> /*
> * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
> *
> @@ -399,7 +312,6 @@ static int __init _omap2_init_reprogram_sdrc(void)
> return v;
> }
>
> -#ifdef CONFIG_OMAP_HWMOD
> static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
> {
> return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
> @@ -412,55 +324,11 @@ static void __init __maybe_unused omap_hwmod_init_postsetup(void)
> /* Set the default postsetup state for all hwmods */
> omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
> }
> -#else
> -static inline void omap_hwmod_init_postsetup(void)
> -{
> -}
> -#endif
> -
> -#ifdef CONFIG_SOC_OMAP2420
> -void __init omap2420_init_early(void)
> -{
> - omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
> - omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
> - OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
> - omap2_control_base_init();
> - omap2xxx_check_revision();
> - omap2_prcm_base_init();
> - omap2xxx_voltagedomains_init();
> - omap242x_powerdomains_init();
> - omap242x_clockdomains_init();
> - omap2420_hwmod_init();
> - omap_hwmod_init_postsetup();
> - omap_clk_soc_init = omap2420_dt_clk_init;
> - rate_table = omap2420_rate_table;
> -}
> -#endif
> -
> -#ifdef CONFIG_SOC_OMAP2430
> -void __init omap2430_init_early(void)
> -{
> - omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
> - omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
> - OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
> - omap2_control_base_init();
> - omap2xxx_check_revision();
> - omap2_prcm_base_init();
> - omap2xxx_voltagedomains_init();
> - omap243x_powerdomains_init();
> - omap243x_clockdomains_init();
> - omap2430_hwmod_init();
> - omap_hwmod_init_postsetup();
> - omap_clk_soc_init = omap2430_dt_clk_init;
> - rate_table = omap2430_rate_table;
> -}
> -#endif
>
> /*
> * Currently only board-omap3beagle.c should call this because of the
> * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
> */
> -#ifdef CONFIG_ARCH_OMAP3
> static void __init omap3_init_early(void)
> {
> omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
> @@ -661,16 +529,18 @@ void __init dra7xx_init_late(void)
> #endif
>
>
> +#ifdef CONFIG_ARCH_OMAP3
> void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
> struct omap_sdrc_params *sdrc_cs1)
> {
> omap_sram_init();
>
> - if (cpu_is_omap24xx() || omap3_has_sdrc()) {
> + if (omap3_has_sdrc()) {
> omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
> _omap2_init_reprogram_sdrc();
> }
> }
> +#endif
>
> int __init omap_clk_init(void)
> {
> diff --git a/arch/arm/mach-omap2/iomap.h b/arch/arm/mach-omap2/iomap.h
> index 6191d244438a..403444bb6924 100644
> --- a/arch/arm/mach-omap2/iomap.h
> +++ b/arch/arm/mach-omap2/iomap.h
> @@ -48,52 +48,6 @@
> #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
> #define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
>
> -/*
> - * ----------------------------------------------------------------------------
> - * Omap2 specific IO mapping
> - * ----------------------------------------------------------------------------
> - */
> -
> -/* We map both L3 and L4 on OMAP2 */
> -#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
> -#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
> -#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
> -#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
> -#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
> -#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
> -
> -#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
> -#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
> -#define L4_WK_243X_SIZE SZ_1M
> -#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
> -#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
> - /* 0x6e000000 --> 0xfe000000 */
> -#define OMAP243X_GPMC_SIZE SZ_1M
> -#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
> - /* 0x6D000000 --> 0xfd000000 */
> -#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
> -#define OMAP243X_SDRC_SIZE SZ_1M
> -#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
> - /* 0x6c000000 --> 0xfc000000 */
> -#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
> -#define OMAP243X_SMS_SIZE SZ_1M
> -
> -/* 2420 IVA */
> -#define DSP_MEM_2420_PHYS OMAP2420_DSP_MEM_BASE
> - /* 0x58000000 --> 0xfc100000 */
> -#define DSP_MEM_2420_VIRT 0xfc100000
> -#define DSP_MEM_2420_SIZE 0x28000
> -#define DSP_IPI_2420_PHYS OMAP2420_DSP_IPI_BASE
> - /* 0x59000000 --> 0xfc128000 */
> -#define DSP_IPI_2420_VIRT 0xfc128000
> -#define DSP_IPI_2420_SIZE SZ_4K
> -#define DSP_MMU_2420_PHYS OMAP2420_DSP_MMU_BASE
> - /* 0x5a000000 --> 0xfc129000 */
> -#define DSP_MMU_2420_VIRT 0xfc129000
> -#define DSP_MMU_2420_SIZE SZ_4K
> -
> -/* 2430 IVA2.1 - currently unmapped */
> -
> /*
> * ----------------------------------------------------------------------------
> * Omap3 specific IO mapping
> diff --git a/arch/arm/mach-omap2/l3_2xxx.h b/arch/arm/mach-omap2/l3_2xxx.h
> deleted file mode 100644
> index 6297c62428ac..000000000000
> --- a/arch/arm/mach-omap2/l3_2xxx.h
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-or-later */
> -/*
> - * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
> - *
> - * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
> - * Sumit Semwal
> - */
> -#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
> -#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
> -
> -/* L3 CONNIDs */
> -/* Display Sub system (DSS) */
> -#define OMAP2_L3_CORE_FW_CONNID_DSS 8
> -
> -#endif
> diff --git a/arch/arm/mach-omap2/l4_2xxx.h b/arch/arm/mach-omap2/l4_2xxx.h
> deleted file mode 100644
> index 418e1072d730..000000000000
> --- a/arch/arm/mach-omap2/l4_2xxx.h
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-or-later */
> -/*
> - * arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions
> - *
> - * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
> - * Sumit Semwal
> - */
> -#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
> -#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
> -
> -/* L4 CORE */
> -/* Display Sub system (DSS) */
> -#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION 28
> -#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION 29
> -#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION 30
> -#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION 31
> -#define OMAP2420_L4_CORE_FW_DSS_TA_REGION 32
> -
> -#endif
> diff --git a/arch/arm/mach-omap2/mmc.h b/arch/arm/mach-omap2/mmc.h
> deleted file mode 100644
> index b5533e93cb63..000000000000
> --- a/arch/arm/mach-omap2/mmc.h
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -
> -#define OMAP24XX_NR_MMC 2
> -#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE
> -#define OMAP2_MMC1_BASE 0x4809c000
> -
> -#define OMAP4_MMC_REG_OFFSET 0x100
> -
> -struct omap_hwmod;
> -
> -#ifdef CONFIG_SOC_OMAP2420
> -int omap_msdi_reset(struct omap_hwmod *oh);
> -#else
> -static inline int omap_msdi_reset(struct omap_hwmod *oh)
> -{
> - return 0;
> -}
> -#endif
> diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
> deleted file mode 100644
> index 552b2fa4e4f1..000000000000
> --- a/arch/arm/mach-omap2/msdi.c
> +++ /dev/null
> @@ -1,75 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * MSDI IP block reset
> - *
> - * Copyright (C) 2012 Texas Instruments, Inc.
> - * Paul Walmsley
> - *
> - * XXX What about pad muxing?
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/err.h>
> -
> -#include "prm.h"
> -#include "common.h"
> -#include "control.h"
> -#include "omap_hwmod.h"
> -#include "omap_device.h"
> -#include "mmc.h"
> -
> -/*
> - * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register
> - * from the IP block's base address
> - */
> -#define MSDI_CON_OFFSET 0x0c
> -
> -/* Register bitfields in the CON register */
> -#define MSDI_CON_POW_MASK BIT(11)
> -#define MSDI_CON_CLKD_MASK (0x3f << 0)
> -#define MSDI_CON_CLKD_SHIFT 0
> -
> -/* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
> -#define MSDI_TARGET_RESET_CLKD 0x3ff
> -
> -/**
> - * omap_msdi_reset - reset the MSDI IP block
> - * @oh: struct omap_hwmod *
> - *
> - * The MSDI IP block on OMAP2420 has to have both the POW and CLKD
> - * fields set inside its CON register for a reset to complete
> - * successfully. This is not documented in the TRM. For CLKD, we use
> - * the value that results in the lowest possible clock rate, to attempt
> - * to avoid disturbing any cards.
> - */
> -int omap_msdi_reset(struct omap_hwmod *oh)
> -{
> - u16 v = 0;
> - int c = 0;
> -
> - /* Write to the SOFTRESET bit */
> - omap_hwmod_softreset(oh);
> -
> - /* Enable the MSDI core and internal clock */
> - v |= MSDI_CON_POW_MASK;
> - v |= MSDI_TARGET_RESET_CLKD << MSDI_CON_CLKD_SHIFT;
> - omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
> -
> - /* Poll on RESETDONE bit */
> - omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
> - & SYSS_RESETDONE_MASK),
> - MAX_MODULE_SOFTRESET_WAIT, c);
> -
> - if (c == MAX_MODULE_SOFTRESET_WAIT)
> - pr_warn("%s: %s: softreset failed (waited %d usec)\n",
> - __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
> - else
> - pr_debug("%s: %s: softreset in %d usec\n", __func__,
> - oh->name, c);
> -
> - /* Disable the MSDI internal clock */
> - v &= ~MSDI_CON_CLKD_MASK;
> - omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
> -
> - return 0;
> -}
> diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
> deleted file mode 100644
> index fdcc75c97d70..000000000000
> --- a/arch/arm/mach-omap2/omap2-restart.c
> +++ /dev/null
> @@ -1,62 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * omap2-restart.c - code common to all OMAP2xxx machines.
> - *
> - * Copyright (C) 2012 Texas Instruments
> - * Paul Walmsley
> - */
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/clk.h>
> -#include <linux/io.h>
> -
> -#include "soc.h"
> -#include "common.h"
> -#include "prm.h"
> -
> -/*
> - * reset_virt_prcm_set_ck, reset_sys_ck: pointers to the virt_prcm_set
> - * clock and the sys_ck. Used during the reset process
> - */
> -static struct clk *reset_virt_prcm_set_ck, *reset_sys_ck;
> -
> -/* Reboot handling */
> -
> -/**
> - * omap2xxx_restart - Set DPLL to bypass mode for reboot to work
> - *
> - * Set the DPLL to bypass so that reboot completes successfully. No
> - * return value.
> - */
> -void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
> -{
> - u32 rate;
> -
> - rate = clk_get_rate(reset_sys_ck);
> - clk_set_rate(reset_virt_prcm_set_ck, rate);
> -
> - /* XXX Should save the cmd argument for use after the reboot */
> -
> - omap_prm_reset_system();
> -}
> -
> -/**
> - * omap2xxx_common_look_up_clks_for_reset - look up clocks needed for restart
> - *
> - * Some clocks need to be looked up in advance for the SoC restart
> - * operation to work - see omap2xxx_restart(). Returns -EINVAL upon
> - * error or 0 upon success.
> - */
> -static int __init omap2xxx_common_look_up_clks_for_reset(void)
> -{
> - reset_virt_prcm_set_ck = clk_get(NULL, "virt_prcm_set");
> - if (IS_ERR(reset_virt_prcm_set_ck))
> - return -EINVAL;
> -
> - reset_sys_ck = clk_get(NULL, "sys_ck");
> - if (IS_ERR(reset_sys_ck))
> - return -EINVAL;
> -
> - return 0;
> -}
> -omap_postcore_initcall(omap2xxx_common_look_up_clks_for_reset);
> diff --git a/arch/arm/mach-omap2/omap24xx.h b/arch/arm/mach-omap2/omap24xx.h
> deleted file mode 100644
> index d9ecc0578292..000000000000
> --- a/arch/arm/mach-omap2/omap24xx.h
> +++ /dev/null
> @@ -1,73 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-or-later */
> -/*
> - * This file contains the processor specific definitions
> - * of the TI OMAP24XX.
> - *
> - * Copyright (C) 2007 Texas Instruments.
> - * Copyright (C) 2007 Nokia Corporation.
> - */
> -
> -#ifndef __ASM_ARCH_OMAP2_H
> -#define __ASM_ARCH_OMAP2_H
> -
> -/*
> - * Please place only base defines here and put the rest in device
> - * specific headers. Note also that some of these defines are needed
> - * for omap1 to compile without adding ifdefs.
> - */
> -
> -#define L4_24XX_BASE 0x48000000
> -#define L4_WK_243X_BASE 0x49000000
> -#define L3_24XX_BASE 0x68000000
> -
> -/* interrupt controller */
> -#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
> -#define OMAP24XX_IVA_INTC_BASE 0x40000000
> -
> -#define OMAP242X_CTRL_BASE L4_24XX_BASE
> -#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
> -#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
> -#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
> -#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
> -#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
> -#define OMAP2420_SMS_BASE 0x68008000
> -#define OMAP2420_GPMC_BASE 0x6800a000
> -
> -#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
> -#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
> -#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000)
> -#define OMAP2430_PRM_BASE OMAP2430_CM_BASE
> -
> -#define OMAP243X_SMS_BASE 0x6C000000
> -#define OMAP243X_SDRC_BASE 0x6D000000
> -#define OMAP243X_GPMC_BASE 0x6E000000
> -#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000)
> -#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE
> -#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000)
> -
> -/* DSP SS */
> -#define OMAP2420_DSP_BASE 0x58000000
> -#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0)
> -#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000)
> -#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000)
> -
> -#define OMAP243X_DSP_BASE 0x5C000000
> -#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0)
> -#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000)
> -
> -/* Mailbox */
> -#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000)
> -
> -/* Camera */
> -#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000)
> -
> -/* Security */
> -#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000)
> -#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000)
> -#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000)
> -#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
> -#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
> -#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
> -
> -#endif /* __ASM_ARCH_OMAP2_H */
> -
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index 03cd523dff87..c918399ea735 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -153,9 +153,7 @@
> #include "common.h"
> #include "clockdomain.h"
> #include "hdq1w.h"
> -#include "mmc.h"
> #include "powerdomain.h"
> -#include "cm2xxx.h"
> #include "cm3xxx.h"
> #include "cm33xx.h"
> #include "prm.h"
> @@ -3469,10 +3467,6 @@ static int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh,
> return -ENOMEM;
> }
>
> -static const struct omap_hwmod_reset omap24xx_reset_quirks[] = {
> - { .match = "msdi", .len = 4, .reset = omap_msdi_reset, },
> -};
> -
> static const struct omap_hwmod_reset omap_reset_quirks[] = {
> { .match = "dss_core", .len = 8, .reset = omap_dss_reset, },
> { .match = "hdq1w", .len = 5, .reset = omap_hdq1w_reset, },
> @@ -3503,11 +3497,6 @@ static void
> omap_hwmod_init_reset_quirks(struct device *dev, struct omap_hwmod *oh,
> const struct ti_sysc_module_data *data)
> {
> - if (soc_is_omap24xx())
> - omap_hwmod_init_reset_quirk(dev, oh, data,
> - omap24xx_reset_quirks,
> - ARRAY_SIZE(omap24xx_reset_quirks));
> -
> omap_hwmod_init_reset_quirk(dev, oh, data, omap_reset_quirks,
> ARRAY_SIZE(omap_reset_quirks));
> }
> @@ -3914,12 +3903,7 @@ int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
> */
> void __init omap_hwmod_init(void)
> {
> - if (cpu_is_omap24xx()) {
> - soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready;
> - soc_ops.assert_hardreset = _omap2_assert_hardreset;
> - soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
> - soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
> - } else if (cpu_is_omap34xx()) {
> + if (cpu_is_omap34xx()) {
> soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready;
> soc_ops.assert_hardreset = _omap2_assert_hardreset;
> soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
> diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
> index dcab7a01c10e..b60cd09c1997 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.h
> +++ b/arch/arm/mach-omap2/omap_hwmod.h
> @@ -663,8 +663,6 @@ omap_hwmod_for_each_by_class(const char *classname,
> * Chip variant-specific hwmod init routines - XXX should be converted
> * to use initcalls once the initial boot ordering is straightened out
> */
> -extern int omap2420_hwmod_init(void);
> -extern int omap2430_hwmod_init(void);
> extern int omap3xxx_hwmod_init(void);
> extern int dm814x_hwmod_init(void);
> extern int dm816x_hwmod_init(void);
> diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
> deleted file mode 100644
> index dbd9dc9f0962..000000000000
> --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
> +++ /dev/null
> @@ -1,402 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
> - *
> - * Copyright (C) 2009-2011 Nokia Corporation
> - * Copyright (C) 2012 Texas Instruments, Inc.
> - * Paul Walmsley
> - *
> - * XXX handle crossbar/shared link difference for L3?
> - * XXX these should be marked initdata for multi-OMAP kernels
> - */
> -
> -#include <linux/platform_data/i2c-omap.h>
> -
> -#include "omap_hwmod.h"
> -#include "l3_2xxx.h"
> -#include "l4_2xxx.h"
> -
> -#include "omap_hwmod_common_data.h"
> -
> -#include "cm-regbits-24xx.h"
> -#include "prm-regbits-24xx.h"
> -#include "i2c.h"
> -#include "mmc.h"
> -#include "wd_timer.h"
> -
> -/*
> - * OMAP2420 hardware module integration data
> - *
> - * All of the data in this section should be autogeneratable from the
> - * TI hardware database or other technical documentation. Data that
> - * is driver-specific or driver-kernel integration-specific belongs
> - * elsewhere.
> - */
> -
> -/*
> - * IP blocks
> - */
> -
> -/* IVA1 (IVA1) */
> -static struct omap_hwmod_class iva1_hwmod_class = {
> - .name = "iva1",
> -};
> -
> -static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
> - { .name = "iva", .rst_shift = 8 },
> -};
> -
> -static struct omap_hwmod omap2420_iva_hwmod = {
> - .name = "iva",
> - .class = &iva1_hwmod_class,
> - .clkdm_name = "iva1_clkdm",
> - .rst_lines = omap2420_iva_resets,
> - .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
> - .main_clk = "iva1_ifck",
> -};
> -
> -/* DSP */
> -static struct omap_hwmod_class dsp_hwmod_class = {
> - .name = "dsp",
> -};
> -
> -static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
> - { .name = "logic", .rst_shift = 0 },
> - { .name = "mmu", .rst_shift = 1 },
> -};
> -
> -static struct omap_hwmod omap2420_dsp_hwmod = {
> - .name = "dsp",
> - .class = &dsp_hwmod_class,
> - .clkdm_name = "dsp_clkdm",
> - .rst_lines = omap2420_dsp_resets,
> - .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
> - .main_clk = "dsp_fck",
> -};
> -
> -/* I2C common */
> -static struct omap_hwmod_class_sysconfig i2c_sysc = {
> - .rev_offs = 0x00,
> - .sysc_offs = 0x20,
> - .syss_offs = 0x10,
> - .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
> - .sysc_fields = &omap_hwmod_sysc_type1,
> -};
> -
> -static struct omap_hwmod_class i2c_class = {
> - .name = "i2c",
> - .sysc = &i2c_sysc,
> - .reset = &omap_i2c_reset,
> -};
> -
> -/* I2C1 */
> -static struct omap_hwmod omap2420_i2c1_hwmod = {
> - .name = "i2c1",
> - .main_clk = "i2c1_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
> - },
> - },
> - .class = &i2c_class,
> - /*
> - * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
> - * while a transfer is active seems to cause the I2C block to
> - * timeout. Why? Good question."
> - */
> - .flags = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
> -};
> -
> -/* I2C2 */
> -static struct omap_hwmod omap2420_i2c2_hwmod = {
> - .name = "i2c2",
> - .main_clk = "i2c2_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
> - },
> - },
> - .class = &i2c_class,
> - .flags = HWMOD_16BIT_REG,
> -};
> -
> -/* mailbox */
> -static struct omap_hwmod omap2420_mailbox_hwmod = {
> - .name = "mailbox",
> - .class = &omap2xxx_mailbox_hwmod_class,
> - .main_clk = "mailboxes_ick",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
> - },
> - },
> -};
> -
> -/*
> - * 'mcbsp' class
> - * multi channel buffered serial port controller
> - */
> -
> -static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
> - .name = "mcbsp",
> -};
> -
> -static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
> - { .role = "pad_fck", .clk = "mcbsp_clks" },
> - { .role = "prcm_fck", .clk = "func_96m_ck" },
> -};
> -
> -/* mcbsp1 */
> -static struct omap_hwmod omap2420_mcbsp1_hwmod = {
> - .name = "mcbsp1",
> - .class = &omap2420_mcbsp_hwmod_class,
> - .main_clk = "mcbsp1_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
> - },
> - },
> - .opt_clks = mcbsp_opt_clks,
> - .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
> -};
> -
> -/* mcbsp2 */
> -static struct omap_hwmod omap2420_mcbsp2_hwmod = {
> - .name = "mcbsp2",
> - .class = &omap2420_mcbsp_hwmod_class,
> - .main_clk = "mcbsp2_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
> - },
> - },
> - .opt_clks = mcbsp_opt_clks,
> - .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
> -};
> -
> -static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
> - .rev_offs = 0x3c,
> - .sysc_offs = 0x64,
> - .syss_offs = 0x68,
> - .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
> - .sysc_fields = &omap_hwmod_sysc_type1,
> -};
> -
> -static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
> - .name = "msdi",
> - .sysc = &omap2420_msdi_sysc,
> - .reset = &omap_msdi_reset,
> -};
> -
> -/* msdi1 */
> -static struct omap_hwmod omap2420_msdi1_hwmod = {
> - .name = "msdi1",
> - .class = &omap2420_msdi_hwmod_class,
> - .main_clk = "mmc_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
> - },
> - },
> - .flags = HWMOD_16BIT_REG,
> -};
> -
> -/* HDQ1W/1-wire */
> -static struct omap_hwmod omap2420_hdq1w_hwmod = {
> - .name = "hdq1w",
> - .main_clk = "hdq_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
> - },
> - },
> - .class = &omap2_hdq1w_class,
> -};
> -
> -/*
> - * interfaces
> - */
> -
> -/* L4 CORE -> I2C1 interface */
> -static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2420_i2c1_hwmod,
> - .clk = "i2c1_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* L4 CORE -> I2C2 interface */
> -static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2420_i2c2_hwmod,
> - .clk = "i2c2_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* IVA <- L3 interface */
> -static struct omap_hwmod_ocp_if omap2420_l3__iva = {
> - .master = &omap2xxx_l3_main_hwmod,
> - .slave = &omap2420_iva_hwmod,
> - .clk = "core_l3_ck",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* DSP <- L3 interface */
> -static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
> - .master = &omap2xxx_l3_main_hwmod,
> - .slave = &omap2420_dsp_hwmod,
> - .clk = "dsp_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_wkup -> wd_timer2 */
> -static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
> - .master = &omap2xxx_l4_wkup_hwmod,
> - .slave = &omap2xxx_wd_timer2_hwmod,
> - .clk = "mpu_wdt_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_wkup -> gpio1 */
> -static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
> - .master = &omap2xxx_l4_wkup_hwmod,
> - .slave = &omap2xxx_gpio1_hwmod,
> - .clk = "gpios_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_wkup -> gpio2 */
> -static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
> - .master = &omap2xxx_l4_wkup_hwmod,
> - .slave = &omap2xxx_gpio2_hwmod,
> - .clk = "gpios_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_wkup -> gpio3 */
> -static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
> - .master = &omap2xxx_l4_wkup_hwmod,
> - .slave = &omap2xxx_gpio3_hwmod,
> - .clk = "gpios_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_wkup -> gpio4 */
> -static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
> - .master = &omap2xxx_l4_wkup_hwmod,
> - .slave = &omap2xxx_gpio4_hwmod,
> - .clk = "gpios_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> mailbox */
> -static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2420_mailbox_hwmod,
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> mcbsp1 */
> -static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2420_mcbsp1_hwmod,
> - .clk = "mcbsp1_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> mcbsp2 */
> -static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2420_mcbsp2_hwmod,
> - .clk = "mcbsp2_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> msdi1 */
> -static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2420_msdi1_hwmod,
> - .clk = "mmc_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> hdq1w interface */
> -static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2420_hdq1w_hwmod,
> - .clk = "hdq_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> - .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
> -};
> -
> -static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
> - .master = &omap2xxx_l3_main_hwmod,
> - .slave = &omap2xxx_gpmc_hwmod,
> - .clk = "core_l3_ck",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
> - &omap2xxx_l3_main__l4_core,
> - &omap2xxx_mpu__l3_main,
> - &omap2xxx_dss__l3,
> - &omap2xxx_l4_core__mcspi1,
> - &omap2xxx_l4_core__mcspi2,
> - &omap2xxx_l4_core__l4_wkup,
> - &omap2_l4_core__uart1,
> - &omap2_l4_core__uart2,
> - &omap2_l4_core__uart3,
> - &omap2420_l4_core__i2c1,
> - &omap2420_l4_core__i2c2,
> - &omap2420_l3__iva,
> - &omap2420_l3__dsp,
> - &omap2xxx_l4_core__timer3,
> - &omap2xxx_l4_core__timer4,
> - &omap2xxx_l4_core__timer5,
> - &omap2xxx_l4_core__timer6,
> - &omap2xxx_l4_core__timer7,
> - &omap2xxx_l4_core__timer8,
> - &omap2xxx_l4_core__timer9,
> - &omap2xxx_l4_core__timer10,
> - &omap2xxx_l4_core__timer11,
> - &omap2xxx_l4_core__timer12,
> - &omap2420_l4_wkup__wd_timer2,
> - &omap2xxx_l4_core__dss,
> - &omap2xxx_l4_core__dss_dispc,
> - &omap2xxx_l4_core__dss_rfbi,
> - &omap2xxx_l4_core__dss_venc,
> - &omap2420_l4_wkup__gpio1,
> - &omap2420_l4_wkup__gpio2,
> - &omap2420_l4_wkup__gpio3,
> - &omap2420_l4_wkup__gpio4,
> - &omap2420_l4_core__mailbox,
> - &omap2420_l4_core__mcbsp1,
> - &omap2420_l4_core__mcbsp2,
> - &omap2420_l4_core__msdi1,
> - &omap2xxx_l4_core__rng,
> - &omap2xxx_l4_core__sham,
> - &omap2xxx_l4_core__aes,
> - &omap2420_l4_core__hdq1w,
> - &omap2420_l3__gpmc,
> - NULL,
> -};
> -
> -int __init omap2420_hwmod_init(void)
> -{
> - omap_hwmod_init();
> - return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
> -}
> diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
> deleted file mode 100644
> index c93200801b34..000000000000
> --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
> +++ /dev/null
> @@ -1,606 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
> - *
> - * Copyright (C) 2009-2011 Nokia Corporation
> - * Copyright (C) 2012 Texas Instruments, Inc.
> - * Paul Walmsley
> - *
> - * XXX handle crossbar/shared link difference for L3?
> - * XXX these should be marked initdata for multi-OMAP kernels
> - */
> -
> -#include <linux/platform_data/i2c-omap.h>
> -#include <linux/platform_data/hsmmc-omap.h>
> -
> -#include "omap_hwmod.h"
> -#include "l3_2xxx.h"
> -
> -#include "soc.h"
> -#include "omap_hwmod_common_data.h"
> -#include "prm-regbits-24xx.h"
> -#include "cm-regbits-24xx.h"
> -#include "i2c.h"
> -#include "wd_timer.h"
> -
> -/*
> - * OMAP2430 hardware module integration data
> - *
> - * All of the data in this section should be autogeneratable from the
> - * TI hardware database or other technical documentation. Data that
> - * is driver-specific or driver-kernel integration-specific belongs
> - * elsewhere.
> - */
> -
> -/*
> - * IP blocks
> - */
> -
> -/* IVA2 (IVA2) */
> -static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
> - { .name = "logic", .rst_shift = 0 },
> - { .name = "mmu", .rst_shift = 1 },
> -};
> -
> -static struct omap_hwmod omap2430_iva_hwmod = {
> - .name = "iva",
> - .class = &iva_hwmod_class,
> - .clkdm_name = "dsp_clkdm",
> - .rst_lines = omap2430_iva_resets,
> - .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets),
> - .main_clk = "dsp_fck",
> -};
> -
> -/* I2C common */
> -static struct omap_hwmod_class_sysconfig i2c_sysc = {
> - .rev_offs = 0x00,
> - .sysc_offs = 0x20,
> - .syss_offs = 0x10,
> - .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
> - SYSS_HAS_RESET_STATUS),
> - .sysc_fields = &omap_hwmod_sysc_type1,
> -};
> -
> -static struct omap_hwmod_class i2c_class = {
> - .name = "i2c",
> - .sysc = &i2c_sysc,
> - .reset = &omap_i2c_reset,
> -};
> -
> -/* I2C1 */
> -static struct omap_hwmod omap2430_i2c1_hwmod = {
> - .name = "i2c1",
> - .flags = HWMOD_16BIT_REG,
> - .main_clk = "i2chs1_fck",
> - .prcm = {
> - .omap2 = {
> - /*
> - * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
> - * I2CHS IP's do not follow the usual pattern.
> - * prcm_reg_id alone cannot be used to program
> - * the iclk and fclk. Needs to be handled using
> - * additional flags when clk handling is moved
> - * to hwmod framework.
> - */
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
> - },
> - },
> - .class = &i2c_class,
> -};
> -
> -/* I2C2 */
> -static struct omap_hwmod omap2430_i2c2_hwmod = {
> - .name = "i2c2",
> - .flags = HWMOD_16BIT_REG,
> - .main_clk = "i2chs2_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
> - },
> - },
> - .class = &i2c_class,
> -};
> -
> -/* gpio5 */
> -static struct omap_hwmod omap2430_gpio5_hwmod = {
> - .name = "gpio5",
> - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> - .main_clk = "gpio5_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 2,
> - .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
> - },
> - },
> - .class = &omap2xxx_gpio_hwmod_class,
> -};
> -
> -/* mailbox */
> -static struct omap_hwmod omap2430_mailbox_hwmod = {
> - .name = "mailbox",
> - .class = &omap2xxx_mailbox_hwmod_class,
> - .main_clk = "mailboxes_ick",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
> - },
> - },
> -};
> -
> -/* mcspi3 */
> -static struct omap_hwmod omap2430_mcspi3_hwmod = {
> - .name = "mcspi3",
> - .main_clk = "mcspi3_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 2,
> - .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
> - },
> - },
> - .class = &omap2xxx_mcspi_class,
> -};
> -
> -/* usbhsotg */
> -static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
> - .rev_offs = 0x0400,
> - .sysc_offs = 0x0404,
> - .syss_offs = 0x0408,
> - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
> - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
> - SYSC_HAS_AUTOIDLE),
> - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
> - .sysc_fields = &omap_hwmod_sysc_type1,
> -};
> -
> -static struct omap_hwmod_class usbotg_class = {
> - .name = "usbotg",
> - .sysc = &omap2430_usbhsotg_sysc,
> -};
> -
> -/* usb_otg_hs */
> -static struct omap_hwmod omap2430_usbhsotg_hwmod = {
> - .name = "usb_otg_hs",
> - .main_clk = "usbhs_ick",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
> - },
> - },
> - .class = &usbotg_class,
> - /*
> - * Erratum ID: i479 idle_req / idle_ack mechanism potentially
> - * broken when autoidle is enabled
> - * workaround is to disable the autoidle bit at module level.
> - */
> - .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
> - | HWMOD_SWSUP_MSTANDBY,
> -};
> -
> -/*
> - * 'mcbsp' class
> - * multi channel buffered serial port controller
> - */
> -
> -static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
> - .rev_offs = 0x007C,
> - .sysc_offs = 0x008C,
> - .sysc_flags = (SYSC_HAS_SOFTRESET),
> - .sysc_fields = &omap_hwmod_sysc_type1,
> -};
> -
> -static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
> - .name = "mcbsp",
> - .sysc = &omap2430_mcbsp_sysc,
> -};
> -
> -static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
> - { .role = "pad_fck", .clk = "mcbsp_clks" },
> - { .role = "prcm_fck", .clk = "func_96m_ck" },
> -};
> -
> -/* mcbsp1 */
> -static struct omap_hwmod omap2430_mcbsp1_hwmod = {
> - .name = "mcbsp1",
> - .class = &omap2430_mcbsp_hwmod_class,
> - .main_clk = "mcbsp1_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
> - },
> - },
> - .opt_clks = mcbsp_opt_clks,
> - .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
> -};
> -
> -/* mcbsp2 */
> -static struct omap_hwmod omap2430_mcbsp2_hwmod = {
> - .name = "mcbsp2",
> - .class = &omap2430_mcbsp_hwmod_class,
> - .main_clk = "mcbsp2_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
> - },
> - },
> - .opt_clks = mcbsp_opt_clks,
> - .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
> -};
> -
> -/* mcbsp3 */
> -static struct omap_hwmod omap2430_mcbsp3_hwmod = {
> - .name = "mcbsp3",
> - .class = &omap2430_mcbsp_hwmod_class,
> - .main_clk = "mcbsp3_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 2,
> - .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
> - },
> - },
> - .opt_clks = mcbsp_opt_clks,
> - .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
> -};
> -
> -/* mcbsp4 */
> -static struct omap_hwmod omap2430_mcbsp4_hwmod = {
> - .name = "mcbsp4",
> - .class = &omap2430_mcbsp_hwmod_class,
> - .main_clk = "mcbsp4_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 2,
> - .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
> - },
> - },
> - .opt_clks = mcbsp_opt_clks,
> - .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
> -};
> -
> -/* mcbsp5 */
> -static struct omap_hwmod omap2430_mcbsp5_hwmod = {
> - .name = "mcbsp5",
> - .class = &omap2430_mcbsp_hwmod_class,
> - .main_clk = "mcbsp5_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 2,
> - .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
> - },
> - },
> - .opt_clks = mcbsp_opt_clks,
> - .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
> -};
> -
> -/* MMC/SD/SDIO common */
> -static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
> - .rev_offs = 0x1fc,
> - .sysc_offs = 0x10,
> - .syss_offs = 0x14,
> - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
> - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
> - SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
> - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> - .sysc_fields = &omap_hwmod_sysc_type1,
> -};
> -
> -static struct omap_hwmod_class omap2430_mmc_class = {
> - .name = "mmc",
> - .sysc = &omap2430_mmc_sysc,
> -};
> -
> -/* MMC/SD/SDIO1 */
> -static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
> - { .role = "dbck", .clk = "mmchsdb1_fck" },
> -};
> -
> -static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
> - .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
> -};
> -
> -static struct omap_hwmod omap2430_mmc1_hwmod = {
> - .name = "mmc1",
> - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> - .opt_clks = omap2430_mmc1_opt_clks,
> - .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
> - .main_clk = "mmchs1_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 2,
> - .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
> - },
> - },
> - .dev_attr = &mmc1_dev_attr,
> - .class = &omap2430_mmc_class,
> -};
> -
> -/* MMC/SD/SDIO2 */
> -static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
> - { .role = "dbck", .clk = "mmchsdb2_fck" },
> -};
> -
> -static struct omap_hwmod omap2430_mmc2_hwmod = {
> - .name = "mmc2",
> - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> - .opt_clks = omap2430_mmc2_opt_clks,
> - .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
> - .main_clk = "mmchs2_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 2,
> - .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
> - },
> - },
> - .class = &omap2430_mmc_class,
> -};
> -
> -/* HDQ1W/1-wire */
> -static struct omap_hwmod omap2430_hdq1w_hwmod = {
> - .name = "hdq1w",
> - .main_clk = "hdq_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
> - },
> - },
> - .class = &omap2_hdq1w_class,
> -};
> -
> -/*
> - * interfaces
> - */
> -
> -/* L3 -> L4_CORE interface */
> -/* l3_core -> usbhsotg interface */
> -static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
> - .master = &omap2430_usbhsotg_hwmod,
> - .slave = &omap2xxx_l3_main_hwmod,
> - .clk = "core_l3_ck",
> - .user = OCP_USER_MPU,
> -};
> -
> -/* L4 CORE -> I2C1 interface */
> -static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2430_i2c1_hwmod,
> - .clk = "i2c1_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* L4 CORE -> I2C2 interface */
> -static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2430_i2c2_hwmod,
> - .clk = "i2c2_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core ->usbhsotg interface */
> -static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2430_usbhsotg_hwmod,
> - .clk = "usb_l4_ick",
> - .user = OCP_USER_MPU,
> -};
> -
> -/* L4 CORE -> MMC1 interface */
> -static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2430_mmc1_hwmod,
> - .clk = "mmchs1_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* L4 CORE -> MMC2 interface */
> -static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2430_mmc2_hwmod,
> - .clk = "mmchs2_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4 core -> mcspi3 interface */
> -static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2430_mcspi3_hwmod,
> - .clk = "mcspi3_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* IVA2 <- L3 interface */
> -static struct omap_hwmod_ocp_if omap2430_l3__iva = {
> - .master = &omap2xxx_l3_main_hwmod,
> - .slave = &omap2430_iva_hwmod,
> - .clk = "core_l3_ck",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_wkup -> wd_timer2 */
> -static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
> - .master = &omap2xxx_l4_wkup_hwmod,
> - .slave = &omap2xxx_wd_timer2_hwmod,
> - .clk = "mpu_wdt_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_wkup -> gpio1 */
> -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
> - .master = &omap2xxx_l4_wkup_hwmod,
> - .slave = &omap2xxx_gpio1_hwmod,
> - .clk = "gpios_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_wkup -> gpio2 */
> -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
> - .master = &omap2xxx_l4_wkup_hwmod,
> - .slave = &omap2xxx_gpio2_hwmod,
> - .clk = "gpios_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_wkup -> gpio3 */
> -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
> - .master = &omap2xxx_l4_wkup_hwmod,
> - .slave = &omap2xxx_gpio3_hwmod,
> - .clk = "gpios_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_wkup -> gpio4 */
> -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
> - .master = &omap2xxx_l4_wkup_hwmod,
> - .slave = &omap2xxx_gpio4_hwmod,
> - .clk = "gpios_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> gpio5 */
> -static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2430_gpio5_hwmod,
> - .clk = "gpio5_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> mailbox */
> -static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2430_mailbox_hwmod,
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> mcbsp1 */
> -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2430_mcbsp1_hwmod,
> - .clk = "mcbsp1_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> mcbsp2 */
> -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2430_mcbsp2_hwmod,
> - .clk = "mcbsp2_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> mcbsp3 */
> -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2430_mcbsp3_hwmod,
> - .clk = "mcbsp3_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> mcbsp4 */
> -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2430_mcbsp4_hwmod,
> - .clk = "mcbsp4_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> mcbsp5 */
> -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2430_mcbsp5_hwmod,
> - .clk = "mcbsp5_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> hdq1w */
> -static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2430_hdq1w_hwmod,
> - .clk = "hdq_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> - .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
> -};
> -
> -static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
> - .master = &omap2xxx_l3_main_hwmod,
> - .slave = &omap2xxx_gpmc_hwmod,
> - .clk = "core_l3_ck",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
> - &omap2xxx_l3_main__l4_core,
> - &omap2xxx_mpu__l3_main,
> - &omap2xxx_dss__l3,
> - &omap2430_usbhsotg__l3,
> - &omap2430_l4_core__i2c1,
> - &omap2430_l4_core__i2c2,
> - &omap2xxx_l4_core__l4_wkup,
> - &omap2_l4_core__uart1,
> - &omap2_l4_core__uart2,
> - &omap2_l4_core__uart3,
> - &omap2430_l4_core__usbhsotg,
> - &omap2430_l4_core__mmc1,
> - &omap2430_l4_core__mmc2,
> - &omap2xxx_l4_core__mcspi1,
> - &omap2xxx_l4_core__mcspi2,
> - &omap2430_l4_core__mcspi3,
> - &omap2430_l3__iva,
> - &omap2xxx_l4_core__timer3,
> - &omap2xxx_l4_core__timer4,
> - &omap2xxx_l4_core__timer5,
> - &omap2xxx_l4_core__timer6,
> - &omap2xxx_l4_core__timer7,
> - &omap2xxx_l4_core__timer8,
> - &omap2xxx_l4_core__timer9,
> - &omap2xxx_l4_core__timer10,
> - &omap2xxx_l4_core__timer11,
> - &omap2xxx_l4_core__timer12,
> - &omap2430_l4_wkup__wd_timer2,
> - &omap2xxx_l4_core__dss,
> - &omap2xxx_l4_core__dss_dispc,
> - &omap2xxx_l4_core__dss_rfbi,
> - &omap2xxx_l4_core__dss_venc,
> - &omap2430_l4_wkup__gpio1,
> - &omap2430_l4_wkup__gpio2,
> - &omap2430_l4_wkup__gpio3,
> - &omap2430_l4_wkup__gpio4,
> - &omap2430_l4_core__gpio5,
> - &omap2430_l4_core__mailbox,
> - &omap2430_l4_core__mcbsp1,
> - &omap2430_l4_core__mcbsp2,
> - &omap2430_l4_core__mcbsp3,
> - &omap2430_l4_core__mcbsp4,
> - &omap2430_l4_core__mcbsp5,
> - &omap2430_l4_core__hdq1w,
> - &omap2xxx_l4_core__rng,
> - &omap2xxx_l4_core__sham,
> - &omap2xxx_l4_core__aes,
> - &omap2430_l3__gpmc,
> - NULL,
> -};
> -
> -int __init omap2430_hwmod_init(void)
> -{
> - omap_hwmod_init();
> - return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
> -}
> diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
> deleted file mode 100644
> index 761d34914ed9..000000000000
> --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
> +++ /dev/null
> @@ -1,256 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
> - *
> - * Copyright (C) 2009-2011 Nokia Corporation
> - * Paul Walmsley
> - *
> - * XXX handle crossbar/shared link difference for L3?
> - * XXX these should be marked initdata for multi-OMAP kernels
> - */
> -#include <linux/sizes.h>
> -
> -#include "omap_hwmod.h"
> -#include "l3_2xxx.h"
> -#include "l4_2xxx.h"
> -
> -#include "omap_hwmod_common_data.h"
> -
> -/*
> - * Common interconnect data
> - */
> -
> -/* L3 -> L4_CORE interface */
> -struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
> - .master = &omap2xxx_l3_main_hwmod,
> - .slave = &omap2xxx_l4_core_hwmod,
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* MPU -> L3 interface */
> -struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
> - .master = &omap2xxx_mpu_hwmod,
> - .slave = &omap2xxx_l3_main_hwmod,
> - .user = OCP_USER_MPU,
> -};
> -
> -/* DSS -> l3 */
> -struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
> - .master = &omap2xxx_dss_core_hwmod,
> - .slave = &omap2xxx_l3_main_hwmod,
> - .fw = {
> - .omap2 = {
> - .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
> - .flags = OMAP_FIREWALL_L3,
> - },
> - },
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* L4_CORE -> L4_WKUP interface */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_l4_wkup_hwmod,
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* L4 CORE -> UART1 interface */
> -struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_uart1_hwmod,
> - .clk = "uart1_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* L4 CORE -> UART2 interface */
> -struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_uart2_hwmod,
> - .clk = "uart2_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* L4 PER -> UART3 interface */
> -struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_uart3_hwmod,
> - .clk = "uart3_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4 core -> mcspi1 interface */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_mcspi1_hwmod,
> - .clk = "mcspi1_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4 core -> mcspi2 interface */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_mcspi2_hwmod,
> - .clk = "mcspi2_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> timer3 */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_timer3_hwmod,
> - .clk = "gpt3_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> timer4 */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_timer4_hwmod,
> - .clk = "gpt4_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> timer5 */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_timer5_hwmod,
> - .clk = "gpt5_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> timer6 */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_timer6_hwmod,
> - .clk = "gpt6_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> timer7 */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_timer7_hwmod,
> - .clk = "gpt7_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> timer8 */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_timer8_hwmod,
> - .clk = "gpt8_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> timer9 */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_timer9_hwmod,
> - .clk = "gpt9_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> timer10 */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_timer10_hwmod,
> - .clk = "gpt10_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> timer11 */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_timer11_hwmod,
> - .clk = "gpt11_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> timer12 */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_timer12_hwmod,
> - .clk = "gpt12_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> dss */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_dss_core_hwmod,
> - .clk = "dss_ick",
> - .fw = {
> - .omap2 = {
> - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
> - .flags = OMAP_FIREWALL_L4,
> - },
> - },
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> dss_dispc */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_dss_dispc_hwmod,
> - .clk = "dss_ick",
> - .fw = {
> - .omap2 = {
> - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
> - .flags = OMAP_FIREWALL_L4,
> - },
> - },
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> dss_rfbi */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_dss_rfbi_hwmod,
> - .clk = "dss_ick",
> - .fw = {
> - .omap2 = {
> - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
> - .flags = OMAP_FIREWALL_L4,
> - },
> - },
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> dss_venc */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_dss_venc_hwmod,
> - .clk = "dss_ick",
> - .fw = {
> - .omap2 = {
> - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
> - .flags = OMAP_FIREWALL_L4,
> - },
> - },
> - .flags = OCPIF_SWSUP_IDLE,
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4_core -> rng */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_rng_hwmod,
> - .clk = "rng_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4 core -> sham interface */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_sham_hwmod,
> - .clk = "sha_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> -
> -/* l4 core -> aes interface */
> -struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
> - .master = &omap2xxx_l4_core_hwmod,
> - .slave = &omap2xxx_aes_hwmod,
> - .clk = "aes_ick",
> - .user = OCP_USER_MPU | OCP_USER_SDMA,
> -};
> diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
> deleted file mode 100644
> index 4982e04ead53..000000000000
> --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
> +++ /dev/null
> @@ -1,668 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
> - *
> - * Copyright (C) 2011 Nokia Corporation
> - * Paul Walmsley
> - */
> -
> -#include <linux/types.h>
> -
> -#include "omap_hwmod.h"
> -#include "omap_hwmod_common_data.h"
> -#include "cm-regbits-24xx.h"
> -#include "prm-regbits-24xx.h"
> -#include "wd_timer.h"
> -
> -/*
> - * 'dispc' class
> - * display controller
> - */
> -
> -static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
> - .rev_offs = 0x0000,
> - .sysc_offs = 0x0010,
> - .syss_offs = 0x0014,
> - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
> - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
> - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
> - .sysc_fields = &omap_hwmod_sysc_type1,
> -};
> -
> -static struct omap_hwmod_class omap2_dispc_hwmod_class = {
> - .name = "dispc",
> - .sysc = &omap2_dispc_sysc,
> -};
> -
> -/* OMAP2xxx Timer Common */
> -static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
> - .rev_offs = 0x0000,
> - .sysc_offs = 0x0010,
> - .syss_offs = 0x0014,
> - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
> - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
> - SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
> - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> - .sysc_fields = &omap_hwmod_sysc_type1,
> -};
> -
> -static struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
> - .name = "timer",
> - .sysc = &omap2xxx_timer_sysc,
> -};
> -
> -/*
> - * 'wd_timer' class
> - * 32-bit watchdog upward counter that generates a pulse on the reset pin on
> - * overflow condition
> - */
> -
> -static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
> - .rev_offs = 0x0000,
> - .sysc_offs = 0x0010,
> - .syss_offs = 0x0014,
> - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
> - SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
> - .sysc_fields = &omap_hwmod_sysc_type1,
> -};
> -
> -static struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
> - .name = "wd_timer",
> - .sysc = &omap2xxx_wd_timer_sysc,
> - .pre_shutdown = &omap2_wd_timer_disable,
> - .reset = &omap2_wd_timer_reset,
> -};
> -
> -/*
> - * 'gpio' class
> - * general purpose io module
> - */
> -static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
> - .rev_offs = 0x0000,
> - .sysc_offs = 0x0010,
> - .syss_offs = 0x0014,
> - .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
> - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
> - SYSS_HAS_RESET_STATUS),
> - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> - .sysc_fields = &omap_hwmod_sysc_type1,
> -};
> -
> -struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
> - .name = "gpio",
> - .sysc = &omap2xxx_gpio_sysc,
> -};
> -
> -/*
> - * 'mailbox' class
> - * mailbox module allowing communication between the on-chip processors
> - * using a queued mailbox-interrupt mechanism.
> - */
> -
> -static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
> - .rev_offs = 0x000,
> - .sysc_offs = 0x010,
> - .syss_offs = 0x014,
> - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
> - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
> - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> - .sysc_fields = &omap_hwmod_sysc_type1,
> -};
> -
> -struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
> - .name = "mailbox",
> - .sysc = &omap2xxx_mailbox_sysc,
> -};
> -
> -/*
> - * 'mcspi' class
> - * multichannel serial port interface (mcspi) / master/slave synchronous serial
> - * bus
> - */
> -
> -static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
> - .rev_offs = 0x0000,
> - .sysc_offs = 0x0010,
> - .syss_offs = 0x0014,
> - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
> - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
> - SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
> - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> - .sysc_fields = &omap_hwmod_sysc_type1,
> -};
> -
> -struct omap_hwmod_class omap2xxx_mcspi_class = {
> - .name = "mcspi",
> - .sysc = &omap2xxx_mcspi_sysc,
> -};
> -
> -/*
> - * 'gpmc' class
> - * general purpose memory controller
> - */
> -
> -static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
> - .rev_offs = 0x0000,
> - .sysc_offs = 0x0010,
> - .syss_offs = 0x0014,
> - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
> - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
> - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> - .sysc_fields = &omap_hwmod_sysc_type1,
> -};
> -
> -static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
> - .name = "gpmc",
> - .sysc = &omap2xxx_gpmc_sysc,
> -};
> -
> -/*
> - * IP blocks
> - */
> -
> -/* L3 */
> -struct omap_hwmod omap2xxx_l3_main_hwmod = {
> - .name = "l3_main",
> - .class = &l3_hwmod_class,
> - .flags = HWMOD_NO_IDLEST,
> -};
> -
> -/* L4 CORE */
> -struct omap_hwmod omap2xxx_l4_core_hwmod = {
> - .name = "l4_core",
> - .class = &l4_hwmod_class,
> - .flags = HWMOD_NO_IDLEST,
> -};
> -
> -/* L4 WKUP */
> -struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
> - .name = "l4_wkup",
> - .class = &l4_hwmod_class,
> - .flags = HWMOD_NO_IDLEST,
> -};
> -
> -/* MPU */
> -struct omap_hwmod omap2xxx_mpu_hwmod = {
> - .name = "mpu",
> - .class = &mpu_hwmod_class,
> - .main_clk = "mpu_ck",
> -};
> -
> -/* timer3 */
> -struct omap_hwmod omap2xxx_timer3_hwmod = {
> - .name = "timer3",
> - .main_clk = "gpt3_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
> - },
> - },
> - .class = &omap2xxx_timer_hwmod_class,
> - .flags = HWMOD_SET_DEFAULT_CLOCKACT,
> -};
> -
> -/* timer4 */
> -struct omap_hwmod omap2xxx_timer4_hwmod = {
> - .name = "timer4",
> - .main_clk = "gpt4_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
> - },
> - },
> - .class = &omap2xxx_timer_hwmod_class,
> - .flags = HWMOD_SET_DEFAULT_CLOCKACT,
> -};
> -
> -/* timer5 */
> -struct omap_hwmod omap2xxx_timer5_hwmod = {
> - .name = "timer5",
> - .main_clk = "gpt5_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
> - },
> - },
> - .class = &omap2xxx_timer_hwmod_class,
> - .flags = HWMOD_SET_DEFAULT_CLOCKACT,
> -};
> -
> -/* timer6 */
> -struct omap_hwmod omap2xxx_timer6_hwmod = {
> - .name = "timer6",
> - .main_clk = "gpt6_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
> - },
> - },
> - .class = &omap2xxx_timer_hwmod_class,
> - .flags = HWMOD_SET_DEFAULT_CLOCKACT,
> -};
> -
> -/* timer7 */
> -struct omap_hwmod omap2xxx_timer7_hwmod = {
> - .name = "timer7",
> - .main_clk = "gpt7_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
> - },
> - },
> - .class = &omap2xxx_timer_hwmod_class,
> - .flags = HWMOD_SET_DEFAULT_CLOCKACT,
> -};
> -
> -/* timer8 */
> -struct omap_hwmod omap2xxx_timer8_hwmod = {
> - .name = "timer8",
> - .main_clk = "gpt8_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
> - },
> - },
> - .class = &omap2xxx_timer_hwmod_class,
> - .flags = HWMOD_SET_DEFAULT_CLOCKACT,
> -};
> -
> -/* timer9 */
> -struct omap_hwmod omap2xxx_timer9_hwmod = {
> - .name = "timer9",
> - .main_clk = "gpt9_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
> - },
> - },
> - .class = &omap2xxx_timer_hwmod_class,
> - .flags = HWMOD_SET_DEFAULT_CLOCKACT,
> -};
> -
> -/* timer10 */
> -struct omap_hwmod omap2xxx_timer10_hwmod = {
> - .name = "timer10",
> - .main_clk = "gpt10_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
> - },
> - },
> - .class = &omap2xxx_timer_hwmod_class,
> - .flags = HWMOD_SET_DEFAULT_CLOCKACT,
> -};
> -
> -/* timer11 */
> -struct omap_hwmod omap2xxx_timer11_hwmod = {
> - .name = "timer11",
> - .main_clk = "gpt11_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
> - },
> - },
> - .class = &omap2xxx_timer_hwmod_class,
> - .flags = HWMOD_SET_DEFAULT_CLOCKACT,
> -};
> -
> -/* timer12 */
> -struct omap_hwmod omap2xxx_timer12_hwmod = {
> - .name = "timer12",
> - .main_clk = "gpt12_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
> - },
> - },
> - .class = &omap2xxx_timer_hwmod_class,
> - .flags = HWMOD_SET_DEFAULT_CLOCKACT,
> -};
> -
> -/* wd_timer2 */
> -struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
> - .name = "wd_timer2",
> - .class = &omap2xxx_wd_timer_hwmod_class,
> - .main_clk = "mpu_wdt_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = WKUP_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
> - },
> - },
> -};
> -
> -/* UART1 */
> -
> -struct omap_hwmod omap2xxx_uart1_hwmod = {
> - .name = "uart1",
> - .main_clk = "uart1_fck",
> - .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
> - },
> - },
> - .class = &omap2_uart_class,
> -};
> -
> -/* UART2 */
> -
> -struct omap_hwmod omap2xxx_uart2_hwmod = {
> - .name = "uart2",
> - .main_clk = "uart2_fck",
> - .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
> - },
> - },
> - .class = &omap2_uart_class,
> -};
> -
> -/* UART3 */
> -
> -struct omap_hwmod omap2xxx_uart3_hwmod = {
> - .name = "uart3",
> - .main_clk = "uart3_fck",
> - .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 2,
> - .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
> - },
> - },
> - .class = &omap2_uart_class,
> -};
> -
> -/* dss */
> -
> -static struct omap_hwmod_opt_clk dss_opt_clks[] = {
> - /*
> - * The DSS HW needs all DSS clocks enabled during reset. The dss_core
> - * driver does not use these clocks.
> - */
> - { .role = "tv_clk", .clk = "dss_54m_fck" },
> - { .role = "sys_clk", .clk = "dss2_fck" },
> -};
> -
> -struct omap_hwmod omap2xxx_dss_core_hwmod = {
> - .name = "dss_core",
> - .class = &omap2_dss_hwmod_class,
> - .main_clk = "dss1_fck", /* instead of dss_fck */
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - },
> - },
> - .opt_clks = dss_opt_clks,
> - .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
> - .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> -};
> -
> -struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
> - .name = "dss_dispc",
> - .class = &omap2_dispc_hwmod_class,
> - .main_clk = "dss1_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - },
> - },
> - .flags = HWMOD_NO_IDLEST,
> - .dev_attr = &omap2_3_dss_dispc_dev_attr,
> -};
> -
> -static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
> - { .role = "ick", .clk = "dss_ick" },
> -};
> -
> -struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
> - .name = "dss_rfbi",
> - .class = &omap2_rfbi_hwmod_class,
> - .main_clk = "dss1_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - },
> - },
> - .opt_clks = dss_rfbi_opt_clks,
> - .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
> - .flags = HWMOD_NO_IDLEST,
> -};
> -
> -struct omap_hwmod omap2xxx_dss_venc_hwmod = {
> - .name = "dss_venc",
> - .class = &omap2_venc_hwmod_class,
> - .main_clk = "dss_54m_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - },
> - },
> - .flags = HWMOD_NO_IDLEST,
> -};
> -
> -/* gpio1 */
> -struct omap_hwmod omap2xxx_gpio1_hwmod = {
> - .name = "gpio1",
> - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> - .main_clk = "gpios_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = WKUP_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
> - },
> - },
> - .class = &omap2xxx_gpio_hwmod_class,
> -};
> -
> -/* gpio2 */
> -struct omap_hwmod omap2xxx_gpio2_hwmod = {
> - .name = "gpio2",
> - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> - .main_clk = "gpios_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = WKUP_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
> - },
> - },
> - .class = &omap2xxx_gpio_hwmod_class,
> -};
> -
> -/* gpio3 */
> -struct omap_hwmod omap2xxx_gpio3_hwmod = {
> - .name = "gpio3",
> - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> - .main_clk = "gpios_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = WKUP_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
> - },
> - },
> - .class = &omap2xxx_gpio_hwmod_class,
> -};
> -
> -/* gpio4 */
> -struct omap_hwmod omap2xxx_gpio4_hwmod = {
> - .name = "gpio4",
> - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> - .main_clk = "gpios_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = WKUP_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
> - },
> - },
> - .class = &omap2xxx_gpio_hwmod_class,
> -};
> -
> -/* mcspi1 */
> -struct omap_hwmod omap2xxx_mcspi1_hwmod = {
> - .name = "mcspi1",
> - .main_clk = "mcspi1_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
> - },
> - },
> - .class = &omap2xxx_mcspi_class,
> -};
> -
> -/* mcspi2 */
> -struct omap_hwmod omap2xxx_mcspi2_hwmod = {
> - .name = "mcspi2",
> - .main_clk = "mcspi2_fck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 1,
> - .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
> - },
> - },
> - .class = &omap2xxx_mcspi_class,
> -};
> -
> -/* gpmc */
> -struct omap_hwmod omap2xxx_gpmc_hwmod = {
> - .name = "gpmc",
> - .class = &omap2xxx_gpmc_hwmod_class,
> - .main_clk = "gpmc_fck",
> - /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
> - .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - },
> - },
> -};
> -
> -/* RNG */
> -
> -static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
> - .rev_offs = 0x3c,
> - .sysc_offs = 0x40,
> - .syss_offs = 0x44,
> - .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
> - SYSS_HAS_RESET_STATUS),
> - .sysc_fields = &omap_hwmod_sysc_type1,
> -};
> -
> -static struct omap_hwmod_class omap2_rng_hwmod_class = {
> - .name = "rng",
> - .sysc = &omap2_rng_sysc,
> -};
> -
> -struct omap_hwmod omap2xxx_rng_hwmod = {
> - .name = "rng",
> - .main_clk = "l4_ck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 4,
> - .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
> - },
> - },
> - /*
> - * XXX The first read from the SYSSTATUS register of the RNG
> - * after the SYSCONFIG SOFTRESET bit is set triggers an
> - * imprecise external abort. It's unclear why this happens.
> - * Until this is analyzed, skip the IP block reset.
> - */
> - .flags = HWMOD_INIT_NO_RESET,
> - .class = &omap2_rng_hwmod_class,
> -};
> -
> -/* SHAM */
> -
> -static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
> - .rev_offs = 0x5c,
> - .sysc_offs = 0x60,
> - .syss_offs = 0x64,
> - .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
> - SYSS_HAS_RESET_STATUS),
> - .sysc_fields = &omap_hwmod_sysc_type1,
> -};
> -
> -static struct omap_hwmod_class omap2xxx_sham_class = {
> - .name = "sham",
> - .sysc = &omap2_sham_sysc,
> -};
> -
> -struct omap_hwmod omap2xxx_sham_hwmod = {
> - .name = "sham",
> - .main_clk = "l4_ck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 4,
> - .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
> - },
> - },
> - .class = &omap2xxx_sham_class,
> -};
> -
> -/* AES */
> -
> -static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
> - .rev_offs = 0x44,
> - .sysc_offs = 0x48,
> - .syss_offs = 0x4c,
> - .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
> - SYSS_HAS_RESET_STATUS),
> - .sysc_fields = &omap_hwmod_sysc_type1,
> -};
> -
> -static struct omap_hwmod_class omap2xxx_aes_class = {
> - .name = "aes",
> - .sysc = &omap2_aes_sysc,
> -};
> -
> -struct omap_hwmod omap2xxx_aes_hwmod = {
> - .name = "aes",
> - .main_clk = "l4_ck",
> - .prcm = {
> - .omap2 = {
> - .module_offs = CORE_MOD,
> - .idlest_reg_id = 4,
> - .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
> - },
> - },
> - .class = &omap2xxx_aes_class,
> -};
> diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
> index 69dddc53e1d8..8b270cb3f64b 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
> +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
> @@ -15,68 +15,6 @@
> #include "common.h"
> #include "display.h"
>
> -/* Common IP block data across OMAP2xxx */
> -extern struct omap_hwmod omap2xxx_l3_main_hwmod;
> -extern struct omap_hwmod omap2xxx_l4_core_hwmod;
> -extern struct omap_hwmod omap2xxx_l4_wkup_hwmod;
> -extern struct omap_hwmod omap2xxx_mpu_hwmod;
> -extern struct omap_hwmod omap2xxx_timer3_hwmod;
> -extern struct omap_hwmod omap2xxx_timer4_hwmod;
> -extern struct omap_hwmod omap2xxx_timer5_hwmod;
> -extern struct omap_hwmod omap2xxx_timer6_hwmod;
> -extern struct omap_hwmod omap2xxx_timer7_hwmod;
> -extern struct omap_hwmod omap2xxx_timer8_hwmod;
> -extern struct omap_hwmod omap2xxx_timer9_hwmod;
> -extern struct omap_hwmod omap2xxx_timer10_hwmod;
> -extern struct omap_hwmod omap2xxx_timer11_hwmod;
> -extern struct omap_hwmod omap2xxx_timer12_hwmod;
> -extern struct omap_hwmod omap2xxx_wd_timer2_hwmod;
> -extern struct omap_hwmod omap2xxx_uart1_hwmod;
> -extern struct omap_hwmod omap2xxx_uart2_hwmod;
> -extern struct omap_hwmod omap2xxx_uart3_hwmod;
> -extern struct omap_hwmod omap2xxx_dss_core_hwmod;
> -extern struct omap_hwmod omap2xxx_dss_dispc_hwmod;
> -extern struct omap_hwmod omap2xxx_dss_rfbi_hwmod;
> -extern struct omap_hwmod omap2xxx_dss_venc_hwmod;
> -extern struct omap_hwmod omap2xxx_gpio1_hwmod;
> -extern struct omap_hwmod omap2xxx_gpio2_hwmod;
> -extern struct omap_hwmod omap2xxx_gpio3_hwmod;
> -extern struct omap_hwmod omap2xxx_gpio4_hwmod;
> -extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
> -extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
> -extern struct omap_hwmod omap2xxx_gpmc_hwmod;
> -extern struct omap_hwmod omap2xxx_rng_hwmod;
> -extern struct omap_hwmod omap2xxx_sham_hwmod;
> -extern struct omap_hwmod omap2xxx_aes_hwmod;
> -
> -/* Common interface data across OMAP2xxx */
> -extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
> -extern struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main;
> -extern struct omap_hwmod_ocp_if omap2xxx_dss__l3;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup;
> -extern struct omap_hwmod_ocp_if omap2_l4_core__uart1;
> -extern struct omap_hwmod_ocp_if omap2_l4_core__uart2;
> -extern struct omap_hwmod_ocp_if omap2_l4_core__uart3;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__sham;
> -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__aes;
> -
> /* OMAP hwmod classes - forward declarations */
> extern struct omap_hwmod_class l3_hwmod_class;
> extern struct omap_hwmod_class l4_hwmod_class;
> @@ -88,10 +26,6 @@ extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
> extern struct omap_hwmod_class omap2_venc_hwmod_class;
> extern struct omap_hwmod_class omap2_hdq1w_class;
>
> -extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
> -extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
> -extern struct omap_hwmod_class omap2xxx_mcspi_class;
> -
> extern struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr;
>
> #endif
> diff --git a/arch/arm/mach-omap2/opp2420_data.c b/arch/arm/mach-omap2/opp2420_data.c
> deleted file mode 100644
> index 18a448f938ea..000000000000
> --- a/arch/arm/mach-omap2/opp2420_data.c
> +++ /dev/null
> @@ -1,131 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * opp2420_data.c - old-style "OPP" table for OMAP2420
> - *
> - * Copyright (C) 2005-2009 Texas Instruments, Inc.
> - * Copyright (C) 2004-2009 Nokia Corporation
> - *
> - * Richard Woodruff <r-woodruff2@ti.com>
> - *
> - * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
> - * These configurations are characterized by voltage and speed for clocks.
> - * The device is only validated for certain combinations. One way to express
> - * these combinations is via the 'ratios' which the clocks operate with
> - * respect to each other. These ratio sets are for a given voltage/DPLL
> - * setting. All configurations can be described by a DPLL setting and a ratio.
> - *
> - * XXX Missing voltage data.
> - * XXX Missing 19.2MHz sys_clk rate sets (needed for N800/N810)
> - *
> - * THe format described in this file is deprecated. Once a reasonable
> - * OPP API exists, the data in this file should be converted to use it.
> - *
> - * This is technically part of the OMAP2xxx clock code.
> - *
> - * Considerable work is still needed to fully support dynamic frequency
> - * changes on OMAP2xxx-series chips. Readers interested in such a
> - * project are encouraged to review the Maemo Diablo RX-34 and RX-44
> - * kernel source at:
> - * http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/
> - */
> -
> -#include <linux/kernel.h>
> -
> -#include "opp2xxx.h"
> -#include "sdrc.h"
> -#include "clock.h"
> -
> -/*
> - * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
> - * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
> - * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
> - * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
> - *
> - * Filling in table based on H4 boards available. There are quite a
> - * few more rate combinations which could be defined.
> - *
> - * When multiple values are defined the start up will try and choose
> - * the fastest one. If a 'fast' value is defined, then automatically,
> - * the /2 one should be included as it can be used. Generally having
> - * more than one fast set does not make sense, as static timings need
> - * to be changed to change the set. The exception is the bypass
> - * setting which is available for low power bypass.
> - *
> - * Note: This table needs to be sorted, fastest to slowest.
> - **/
> -const struct prcm_config omap2420_rate_table[] = {
> - /* PRCM I - FAST */
> - {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
> - RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
> - RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
> - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
> - RATE_IN_242X},
> -
> - /* PRCM II - FAST */
> - {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
> - RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
> - RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
> - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
> - RATE_IN_242X},
> -
> - {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
> - RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
> - RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
> - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
> - RATE_IN_242X},
> -
> - /* PRCM III - FAST */
> - {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
> - RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
> - RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
> - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
> - RATE_IN_242X},
> -
> - {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
> - RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
> - RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
> - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
> - RATE_IN_242X},
> -
> - /* PRCM II - SLOW */
> - {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
> - RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
> - RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
> - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
> - RATE_IN_242X},
> -
> - {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
> - RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
> - RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
> - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
> - RATE_IN_242X},
> -
> - /* PRCM III - SLOW */
> - {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
> - RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
> - RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
> - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
> - RATE_IN_242X},
> -
> - {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
> - RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
> - RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
> - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
> - RATE_IN_242X},
> -
> - /* PRCM-VII (boot-bypass) */
> - {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
> - RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
> - RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
> - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
> - RATE_IN_242X},
> -
> - /* PRCM-VII (boot-bypass) */
> - {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
> - RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
> - RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
> - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
> - RATE_IN_242X},
> -
> - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
> -};
> diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c
> deleted file mode 100644
> index ded8b566a23a..000000000000
> --- a/arch/arm/mach-omap2/opp2430_data.c
> +++ /dev/null
> @@ -1,136 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * opp2430_data.c - old-style "OPP" table for OMAP2430
> - *
> - * Copyright (C) 2005-2009 Texas Instruments, Inc.
> - * Copyright (C) 2004-2009 Nokia Corporation
> - *
> - * Richard Woodruff <r-woodruff2@ti.com>
> - *
> - * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
> - * These configurations are characterized by voltage and speed for clocks.
> - * The device is only validated for certain combinations. One way to express
> - * these combinations is via the 'ratios' which the clocks operate with
> - * respect to each other. These ratio sets are for a given voltage/DPLL
> - * setting. All configurations can be described by a DPLL setting and a ratio.
> - *
> - * 2430 differs from 2420 in that there are no more phase synchronizers used.
> - * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
> - * 2430 (iva2.1, NOdsp, mdm)
> - *
> - * XXX Missing voltage data.
> - * XXX Missing 19.2MHz sys_clk rate sets.
> - *
> - * THe format described in this file is deprecated. Once a reasonable
> - * OPP API exists, the data in this file should be converted to use it.
> - *
> - * This is technically part of the OMAP2xxx clock code.
> - */
> -
> -#include <linux/kernel.h>
> -
> -#include "opp2xxx.h"
> -#include "sdrc.h"
> -#include "clock.h"
> -
> -/*
> - * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
> - * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
> - * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
> - * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
> - *
> - * Filling in table based on 2430-SDPs variants available. There are
> - * quite a few more rate combinations which could be defined.
> - *
> - * When multiple values are defined the start up will try and choose
> - * the fastest one. If a 'fast' value is defined, then automatically,
> - * the /2 one should be included as it can be used. Generally having
> - * more than one fast set does not make sense, as static timings need
> - * to be changed to change the set. The exception is the bypass
> - * setting which is available for low power bypass.
> - *
> - * Note: This table needs to be sorted, fastest to slowest.
> - */
> -const struct prcm_config omap2430_rate_table[] = {
> - /* PRCM #4 - ratio2 (ES2.1) - FAST */
> - {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
> - R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
> - R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
> - MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
> - SDRC_RFR_CTRL_133MHz,
> - RATE_IN_243X},
> -
> - /* PRCM #2 - ratio1 (ES2) - FAST */
> - {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
> - R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
> - R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
> - MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
> - SDRC_RFR_CTRL_165MHz,
> - RATE_IN_243X},
> -
> - /* PRCM #5a - ratio1 - FAST */
> - {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
> - R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
> - R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
> - MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
> - SDRC_RFR_CTRL_133MHz,
> - RATE_IN_243X},
> -
> - /* PRCM #5b - ratio1 - FAST */
> - {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
> - R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
> - R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
> - MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
> - SDRC_RFR_CTRL_100MHz,
> - RATE_IN_243X},
> -
> - /* PRCM #4 - ratio1 (ES2.1) - SLOW */
> - {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
> - R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
> - R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
> - MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
> - SDRC_RFR_CTRL_133MHz,
> - RATE_IN_243X},
> -
> - /* PRCM #2 - ratio1 (ES2) - SLOW */
> - {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
> - R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
> - R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
> - MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
> - SDRC_RFR_CTRL_165MHz,
> - RATE_IN_243X},
> -
> - /* PRCM #5a - ratio1 - SLOW */
> - {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
> - R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
> - R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
> - MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
> - SDRC_RFR_CTRL_133MHz,
> - RATE_IN_243X},
> -
> - /* PRCM #5b - ratio1 - SLOW*/
> - {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
> - R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
> - R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
> - MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
> - SDRC_RFR_CTRL_100MHz,
> - RATE_IN_243X},
> -
> - /* PRCM-boot/bypass */
> - {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13MHz */
> - RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
> - RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
> - MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
> - SDRC_RFR_CTRL_BYPASS,
> - RATE_IN_243X},
> -
> - /* PRCM-boot/bypass */
> - {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12MHz */
> - RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
> - RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
> - MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
> - SDRC_RFR_CTRL_BYPASS,
> - RATE_IN_243X},
> -
> - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
> -};
> diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
> deleted file mode 100644
> index a451182cdc02..000000000000
> --- a/arch/arm/mach-omap2/opp2xxx.h
> +++ /dev/null
> @@ -1,430 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
> - *
> - * Copyright (C) 2005-2009 Texas Instruments, Inc.
> - * Copyright (C) 2004-2009 Nokia Corporation
> - *
> - * Richard Woodruff <r-woodruff2@ti.com>
> - *
> - * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
> - * These configurations are characterized by voltage and speed for clocks.
> - * The device is only validated for certain combinations. One way to express
> - * these combinations is via the 'ratio's' which the clocks operate with
> - * respect to each other. These ratio sets are for a given voltage/DPLL
> - * setting. All configurations can be described by a DPLL setting and a ratio
> - * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
> - *
> - * 2430 differs from 2420 in that there are no more phase synchronizers used.
> - * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
> - * 2430 (iva2.1, NOdsp, mdm)
> - *
> - * XXX Missing voltage data.
> - *
> - * THe format described in this file is deprecated. Once a reasonable
> - * OPP API exists, the data in this file should be converted to use it.
> - *
> - * This is technically part of the OMAP2xxx clock code.
> - */
> -
> -#ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
> -#define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
> -
> -/**
> - * struct prcm_config - define clock rates on a per-OPP basis (24xx)
> - *
> - * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
> - * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
> - * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
> - *
> - * This is deprecated. As soon as we have a decent OPP API, we should
> - * move all this stuff to it.
> - */
> -struct prcm_config {
> - unsigned long xtal_speed; /* crystal rate */
> - unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
> - unsigned long mpu_speed; /* speed of MPU */
> - unsigned long cm_clksel_mpu; /* mpu divider */
> - unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
> - unsigned long cm_clksel_gfx; /* gfx dividers */
> - unsigned long cm_clksel1_core; /* major subsystem dividers */
> - unsigned long cm_clksel1_pll; /* m,n */
> - unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
> - unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
> - unsigned long base_sdrc_rfr; /* base refresh timing for a set */
> - unsigned short flags;
> -};
> -
> -
> -/* Core fields for cm_clksel, not ratio governed */
> -#define RX_CLKSEL_DSS1 (0x10 << 8)
> -#define RX_CLKSEL_DSS2 (0x0 << 13)
> -#define RX_CLKSEL_SSI (0x5 << 20)
> -
> -/*-------------------------------------------------------------------------
> - * Voltage/DPLL ratios
> - *-------------------------------------------------------------------------*/
> -
> -/* 2430 Ratio's, 2430-Ratio Config 1 */
> -#define R1_CLKSEL_L3 (4 << 0)
> -#define R1_CLKSEL_L4 (2 << 5)
> -#define R1_CLKSEL_USB (4 << 25)
> -#define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB | RX_CLKSEL_SSI | \
> - RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
> - R1_CLKSEL_L4 | R1_CLKSEL_L3)
> -#define R1_CLKSEL_MPU (2 << 0)
> -#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
> -#define R1_CLKSEL_DSP (2 << 0)
> -#define R1_CLKSEL_DSP_IF (2 << 5)
> -#define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF)
> -#define R1_CLKSEL_GFX (2 << 0)
> -#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
> -#define R1_CLKSEL_MDM (4 << 0)
> -#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
> -
> -/* 2430-Ratio Config 2 */
> -#define R2_CLKSEL_L3 (6 << 0)
> -#define R2_CLKSEL_L4 (2 << 5)
> -#define R2_CLKSEL_USB (2 << 25)
> -#define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB | RX_CLKSEL_SSI | \
> - RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
> - R2_CLKSEL_L4 | R2_CLKSEL_L3)
> -#define R2_CLKSEL_MPU (2 << 0)
> -#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
> -#define R2_CLKSEL_DSP (2 << 0)
> -#define R2_CLKSEL_DSP_IF (3 << 5)
> -#define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF)
> -#define R2_CLKSEL_GFX (2 << 0)
> -#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
> -#define R2_CLKSEL_MDM (6 << 0)
> -#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
> -
> -/* 2430-Ratio Bootm (BYPASS) */
> -#define RB_CLKSEL_L3 (1 << 0)
> -#define RB_CLKSEL_L4 (1 << 5)
> -#define RB_CLKSEL_USB (1 << 25)
> -#define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB | RX_CLKSEL_SSI | \
> - RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
> - RB_CLKSEL_L4 | RB_CLKSEL_L3)
> -#define RB_CLKSEL_MPU (1 << 0)
> -#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
> -#define RB_CLKSEL_DSP (1 << 0)
> -#define RB_CLKSEL_DSP_IF (1 << 5)
> -#define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF)
> -#define RB_CLKSEL_GFX (1 << 0)
> -#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
> -#define RB_CLKSEL_MDM (1 << 0)
> -#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
> -
> -/* 2420 Ratio Equivalents */
> -#define RXX_CLKSEL_VLYNQ (0x12 << 15)
> -#define RXX_CLKSEL_SSI (0x8 << 20)
> -
> -/* 2420-PRCM III 532MHz core */
> -#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
> -#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
> -#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
> -#define RIII_CM_CLKSEL1_CORE_VAL (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
> - RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
> - RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
> - RIII_CLKSEL_L3)
> -#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
> -#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
> -#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
> -#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
> -#define RIII_SYNC_DSP (1 << 7) /* Enable sync */
> -#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
> -#define RIII_SYNC_IVA (1 << 13) /* Enable sync */
> -#define RIII_CM_CLKSEL_DSP_VAL (RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
> - RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
> - RIII_CLKSEL_DSP)
> -#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
> -#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
> -
> -/* 2420-PRCM II 600MHz core */
> -#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
> -#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
> -#define RII_CLKSEL_USB (2 << 25) /* 50MHz */
> -#define RII_CM_CLKSEL1_CORE_VAL (RII_CLKSEL_USB | RXX_CLKSEL_SSI | \
> - RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
> - RX_CLKSEL_DSS1 | RII_CLKSEL_L4 | \
> - RII_CLKSEL_L3)
> -#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
> -#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
> -#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
> -#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
> -#define RII_SYNC_DSP (0 << 7) /* Bypass sync */
> -#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
> -#define RII_SYNC_IVA (0 << 13) /* Bypass sync */
> -#define RII_CM_CLKSEL_DSP_VAL (RII_SYNC_IVA | RII_CLKSEL_IVA | \
> - RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
> - RII_CLKSEL_DSP)
> -#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
> -#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
> -
> -/* 2420-PRCM I 660MHz core */
> -#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
> -#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
> -#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
> -#define RI_CM_CLKSEL1_CORE_VAL (RI_CLKSEL_USB | \
> - RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
> - RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
> - RI_CLKSEL_L4 | RI_CLKSEL_L3)
> -#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
> -#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
> -#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
> -#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
> -#define RI_SYNC_DSP (1 << 7) /* Activate sync */
> -#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
> -#define RI_SYNC_IVA (0 << 13) /* Bypass sync */
> -#define RI_CM_CLKSEL_DSP_VAL (RI_SYNC_IVA | RI_CLKSEL_IVA | \
> - RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
> - RI_CLKSEL_DSP)
> -#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
> -#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
> -
> -/* 2420-PRCM VII (boot) */
> -#define RVII_CLKSEL_L3 (1 << 0)
> -#define RVII_CLKSEL_L4 (1 << 5)
> -#define RVII_CLKSEL_DSS1 (1 << 8)
> -#define RVII_CLKSEL_DSS2 (0 << 13)
> -#define RVII_CLKSEL_VLYNQ (1 << 15)
> -#define RVII_CLKSEL_SSI (1 << 20)
> -#define RVII_CLKSEL_USB (1 << 25)
> -
> -#define RVII_CM_CLKSEL1_CORE_VAL (RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
> - RVII_CLKSEL_VLYNQ | \
> - RVII_CLKSEL_DSS2 | RVII_CLKSEL_DSS1 | \
> - RVII_CLKSEL_L4 | RVII_CLKSEL_L3)
> -
> -#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
> -#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
> -
> -#define RVII_CLKSEL_DSP (1 << 0)
> -#define RVII_CLKSEL_DSP_IF (1 << 5)
> -#define RVII_SYNC_DSP (0 << 7)
> -#define RVII_CLKSEL_IVA (1 << 8)
> -#define RVII_SYNC_IVA (0 << 13)
> -#define RVII_CM_CLKSEL_DSP_VAL (RVII_SYNC_IVA | RVII_CLKSEL_IVA | \
> - RVII_SYNC_DSP | RVII_CLKSEL_DSP_IF | \
> - RVII_CLKSEL_DSP)
> -
> -#define RVII_CLKSEL_GFX (1 << 0)
> -#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
> -
> -/*-------------------------------------------------------------------------
> - * 2430 Target modes: Along with each configuration the CPU has several
> - * modes which goes along with them. Modes mainly are the addition of
> - * describe DPLL combinations to go along with a ratio.
> - *-------------------------------------------------------------------------*/
> -
> -/* Hardware governed */
> -#define MX_48M_SRC (0 << 3)
> -#define MX_54M_SRC (0 << 5)
> -#define MX_APLLS_CLIKIN_12 (3 << 23)
> -#define MX_APLLS_CLIKIN_13 (2 << 23)
> -#define MX_APLLS_CLIKIN_19_2 (0 << 23)
> -
> -/*
> - * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
> - * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
> - */
> -#define M5A_DPLL_MULT_12 (133 << 12)
> -#define M5A_DPLL_DIV_12 (5 << 8)
> -#define M5A_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
> - M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
> - MX_APLLS_CLIKIN_12)
> -#define M5A_DPLL_MULT_13 (61 << 12)
> -#define M5A_DPLL_DIV_13 (2 << 8)
> -#define M5A_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
> - M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
> - MX_APLLS_CLIKIN_13)
> -#define M5A_DPLL_MULT_19 (55 << 12)
> -#define M5A_DPLL_DIV_19 (3 << 8)
> -#define M5A_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
> - M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
> - MX_APLLS_CLIKIN_19_2)
> -/* #5b (ratio1) target DPLL = 200*2 = 400MHz */
> -#define M5B_DPLL_MULT_12 (50 << 12)
> -#define M5B_DPLL_DIV_12 (2 << 8)
> -#define M5B_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
> - M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
> - MX_APLLS_CLIKIN_12)
> -#define M5B_DPLL_MULT_13 (200 << 12)
> -#define M5B_DPLL_DIV_13 (12 << 8)
> -
> -#define M5B_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
> - M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
> - MX_APLLS_CLIKIN_13)
> -#define M5B_DPLL_MULT_19 (125 << 12)
> -#define M5B_DPLL_DIV_19 (31 << 8)
> -#define M5B_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
> - M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
> - MX_APLLS_CLIKIN_19_2)
> -/*
> - * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
> - */
> -#define M4_DPLL_MULT_12 (133 << 12)
> -#define M4_DPLL_DIV_12 (3 << 8)
> -#define M4_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
> - M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
> - MX_APLLS_CLIKIN_12)
> -
> -#define M4_DPLL_MULT_13 (399 << 12)
> -#define M4_DPLL_DIV_13 (12 << 8)
> -#define M4_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
> - M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
> - MX_APLLS_CLIKIN_13)
> -
> -#define M4_DPLL_MULT_19 (145 << 12)
> -#define M4_DPLL_DIV_19 (6 << 8)
> -#define M4_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
> - M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
> - MX_APLLS_CLIKIN_19_2)
> -
> -/*
> - * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
> - */
> -#define M3_DPLL_MULT_12 (55 << 12)
> -#define M3_DPLL_DIV_12 (1 << 8)
> -#define M3_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
> - M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
> - MX_APLLS_CLIKIN_12)
> -#define M3_DPLL_MULT_13 (76 << 12)
> -#define M3_DPLL_DIV_13 (2 << 8)
> -#define M3_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
> - M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
> - MX_APLLS_CLIKIN_13)
> -#define M3_DPLL_MULT_19 (17 << 12)
> -#define M3_DPLL_DIV_19 (0 << 8)
> -#define M3_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
> - M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
> - MX_APLLS_CLIKIN_19_2)
> -
> -/*
> - * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
> - */
> -#define M2_DPLL_MULT_12 (55 << 12)
> -#define M2_DPLL_DIV_12 (1 << 8)
> -#define M2_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
> - M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
> - MX_APLLS_CLIKIN_12)
> -
> -/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
> - * relock time issue */
> -/* Core frequency changed from 330/165 to 329/164 MHz*/
> -#define M2_DPLL_MULT_13 (76 << 12)
> -#define M2_DPLL_DIV_13 (2 << 8)
> -#define M2_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
> - M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
> - MX_APLLS_CLIKIN_13)
> -
> -#define M2_DPLL_MULT_19 (17 << 12)
> -#define M2_DPLL_DIV_19 (0 << 8)
> -#define M2_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
> - M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
> - MX_APLLS_CLIKIN_19_2)
> -
> -/* boot (boot) */
> -#define MB_DPLL_MULT (1 << 12)
> -#define MB_DPLL_DIV (0 << 8)
> -#define MB_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
> - MB_DPLL_DIV | MB_DPLL_MULT | \
> - MX_APLLS_CLIKIN_12)
> -
> -#define MB_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
> - MB_DPLL_DIV | MB_DPLL_MULT | \
> - MX_APLLS_CLIKIN_13)
> -
> -#define MB_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
> - MB_DPLL_DIV | MB_DPLL_MULT | \
> - MX_APLLS_CLIKIN_19)
> -
> -/*
> - * 2430 - chassis (sedna)
> - * 165 (ratio1) same as above #2
> - * 150 (ratio1)
> - * 133 (ratio2) same as above #4
> - * 110 (ratio2) same as above #3
> - * 104 (ratio2)
> - * boot (boot)
> - */
> -
> -/* PRCM I target DPLL = 2*330MHz = 660MHz */
> -#define MI_DPLL_MULT_12 (55 << 12)
> -#define MI_DPLL_DIV_12 (1 << 8)
> -#define MI_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
> - MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
> - MX_APLLS_CLIKIN_12)
> -
> -/*
> - * 2420 Equivalent - mode registers
> - * PRCM II , target DPLL = 2*300MHz = 600MHz
> - */
> -#define MII_DPLL_MULT_12 (50 << 12)
> -#define MII_DPLL_DIV_12 (1 << 8)
> -#define MII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
> - MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
> - MX_APLLS_CLIKIN_12)
> -#define MII_DPLL_MULT_13 (300 << 12)
> -#define MII_DPLL_DIV_13 (12 << 8)
> -#define MII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
> - MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
> - MX_APLLS_CLIKIN_13)
> -
> -/* PRCM III target DPLL = 2*266 = 532MHz*/
> -#define MIII_DPLL_MULT_12 (133 << 12)
> -#define MIII_DPLL_DIV_12 (5 << 8)
> -#define MIII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
> - MIII_DPLL_DIV_12 | \
> - MIII_DPLL_MULT_12 | MX_APLLS_CLIKIN_12)
> -#define MIII_DPLL_MULT_13 (266 << 12)
> -#define MIII_DPLL_DIV_13 (12 << 8)
> -#define MIII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
> - MIII_DPLL_DIV_13 | \
> - MIII_DPLL_MULT_13 | MX_APLLS_CLIKIN_13)
> -
> -/* PRCM VII (boot bypass) */
> -#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
> -#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
> -
> -/* High and low operation value */
> -#define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
> -#define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
> -
> -/* MPU speed defines */
> -#define S12M 12000000
> -#define S13M 13000000
> -#define S19M 19200000
> -#define S26M 26000000
> -#define S100M 100000000
> -#define S133M 133000000
> -#define S150M 150000000
> -#define S164M 164000000
> -#define S165M 165000000
> -#define S199M 199000000
> -#define S200M 200000000
> -#define S266M 266000000
> -#define S300M 300000000
> -#define S329M 329000000
> -#define S330M 330000000
> -#define S399M 399000000
> -#define S400M 400000000
> -#define S532M 532000000
> -#define S600M 600000000
> -#define S658M 658000000
> -#define S660M 660000000
> -#define S798M 798000000
> -
> -
> -extern const struct prcm_config omap2420_rate_table[];
> -
> -#ifdef CONFIG_SOC_OMAP2430
> -extern const struct prcm_config omap2430_rate_table[];
> -#else
> -#define omap2430_rate_table NULL
> -#endif
> -extern const struct prcm_config *rate_table;
> -extern const struct prcm_config *curr_prcm_set;
> -
> -#endif
> diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
> index b947bacf23a3..8b8021b297aa 100644
> --- a/arch/arm/mach-omap2/pdata-quirks.c
> +++ b/arch/arm/mach-omap2/pdata-quirks.c
> @@ -27,7 +27,6 @@
>
> #include "clockdomain.h"
> #include "common.h"
> -#include "common-board-devices.h"
> #include "control.h"
> #include "omap_device.h"
> #include "omap-secure.h"
> @@ -42,15 +41,6 @@ struct pdata_init {
>
> static struct of_dev_auxdata omap_auxdata_lookup[];
>
> -#ifdef CONFIG_MACH_NOKIA_N8X0
> -static void __init omap2420_n8x0_legacy_init(void)
> -{
> - omap_auxdata_lookup[0].platform_data = n8x0_legacy_init();
> -}
> -#else
> -#define omap2420_n8x0_legacy_init NULL
> -#endif
> -
> #ifdef CONFIG_ARCH_OMAP3
> /*
> * Configures GPIOs 126, 127 and 129 to 1.8V mode instead of 3.0V
> @@ -431,26 +421,9 @@ static void __init omap3_mcbsp_init(void)
> static void __init omap3_mcbsp_init(void) {}
> #endif
>
> -/*
> - * Few boards still need auxdata populated before we populate
> - * the dev entries in of_platform_populate().
> - */
> -static struct pdata_init auxdata_quirks[] __initdata = {
> -#ifdef CONFIG_SOC_OMAP2420
> - { "nokia,n800", omap2420_n8x0_legacy_init, },
> - { "nokia,n810", omap2420_n8x0_legacy_init, },
> - { "nokia,n810-wimax", omap2420_n8x0_legacy_init, },
> -#endif
> - { /* sentinel */ },
> -};
> -
> struct omap_sr_data __maybe_unused omap_sr_pdata[OMAP_SR_NR];
>
> static struct of_dev_auxdata omap_auxdata_lookup[] = {
> -#ifdef CONFIG_MACH_NOKIA_N8X0
> - OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL),
> - OF_DEV_AUXDATA("menelaus", 0x72, "1-0072", &n8x0_menelaus_platform_data),
> -#endif
> #ifdef CONFIG_ARCH_OMAP3
> OF_DEV_AUXDATA("ti,omap2-iommu", 0x5d000000, "5d000000.mmu",
> &omap3_iommu_pdata),
> @@ -560,13 +533,11 @@ void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table)
> * We still need this for omap2420 and omap3 PM to work, others are
> * using drivers/misc/sram.c already.
> */
> - if (of_machine_is_compatible("ti,omap2420") ||
> - of_machine_is_compatible("ti,omap3"))
> + if (IS_ENABLED(CONFIG_ARCH_OMAP3) &&
> + of_machine_is_compatible("ti,omap3")) {
> omap_sdrc_init(NULL, NULL);
> -
> - if (of_machine_is_compatible("ti,omap3"))
> omap3_mcbsp_init();
> - pdata_quirks_check(auxdata_quirks);
> + }
>
> pdata_quirks_init_clocks(omap_dt_match_table);
>
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index f97ff93f2fb4..5751b85e9ffb 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -43,11 +43,6 @@ extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
> #define pm_dbg_update_time(pwrdm, prev) do {} while (0);
> #endif /* CONFIG_PM_DEBUG */
>
> -/* 24xx */
> -extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
> - void __iomem *sdrc_power);
> -extern unsigned int omap24xx_cpu_suspend_sz;
> -
> /* 3xxx */
> extern void omap34xx_cpu_suspend(int save_state);
>
> diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
> index fbc89999460b..eaf6d1104dc2 100644
> --- a/arch/arm/mach-omap2/powerdomain.h
> +++ b/arch/arm/mach-omap2/powerdomain.h
> @@ -244,8 +244,6 @@ int pwrdm_post_transition(struct powerdomain *pwrdm);
>
> extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state);
>
> -extern void omap242x_powerdomains_init(void);
> -extern void omap243x_powerdomains_init(void);
> extern void omap3xxx_powerdomains_init(void);
> extern void am33xx_powerdomains_init(void);
> extern void omap44xx_powerdomains_init(void);
> @@ -253,7 +251,6 @@ extern void omap54xx_powerdomains_init(void);
> extern void dra7xx_powerdomains_init(void);
> void am43xx_powerdomains_init(void);
>
> -extern struct pwrdm_ops omap2_pwrdm_operations;
> extern struct pwrdm_ops omap3_pwrdm_operations;
> extern struct pwrdm_ops am33xx_pwrdm_operations;
> extern struct pwrdm_ops omap4_pwrdm_operations;
> diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
> deleted file mode 100644
> index fa259adbdc61..000000000000
> --- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
> +++ /dev/null
> @@ -1,134 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * OMAP2XXX powerdomain definitions
> - *
> - * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
> - * Copyright (C) 2007-2011 Nokia Corporation
> - *
> - * Paul Walmsley, Jouni Högander
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -
> -#include "soc.h"
> -#include "powerdomain.h"
> -#include "powerdomains2xxx_3xxx_data.h"
> -
> -#include "prcm-common.h"
> -#include "prm2xxx_3xxx.h"
> -#include "prm-regbits-24xx.h"
> -
> -/* 24XX powerdomains and dependencies */
> -
> -/* Powerdomains */
> -
> -static struct powerdomain dsp_pwrdm = {
> - .name = "dsp_pwrdm",
> - .prcm_offs = OMAP24XX_DSP_MOD,
> - .pwrsts = PWRSTS_OFF_RET_ON,
> - .pwrsts_logic_ret = PWRSTS_RET,
> - .banks = 1,
> - .pwrsts_mem_ret = {
> - [0] = PWRSTS_RET,
> - },
> - .pwrsts_mem_on = {
> - [0] = PWRSTS_ON,
> - },
> - .voltdm = { .name = "core" },
> -};
> -
> -static struct powerdomain mpu_24xx_pwrdm = {
> - .name = "mpu_pwrdm",
> - .prcm_offs = MPU_MOD,
> - .pwrsts = PWRSTS_OFF_RET_ON,
> - .pwrsts_logic_ret = PWRSTS_OFF_RET,
> - .banks = 1,
> - .pwrsts_mem_ret = {
> - [0] = PWRSTS_RET,
> - },
> - .pwrsts_mem_on = {
> - [0] = PWRSTS_ON,
> - },
> - .voltdm = { .name = "core" },
> -};
> -
> -static struct powerdomain core_24xx_pwrdm = {
> - .name = "core_pwrdm",
> - .prcm_offs = CORE_MOD,
> - .pwrsts = PWRSTS_OFF_RET_ON,
> - .pwrsts_logic_ret = PWRSTS_RET,
> - .banks = 3,
> - .pwrsts_mem_ret = {
> - [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
> - [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
> - [2] = PWRSTS_OFF_RET, /* MEM3RETSTATE */
> - },
> - .pwrsts_mem_on = {
> - [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
> - [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
> - [2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */
> - },
> - .voltdm = { .name = "core" },
> -};
> -
> -
> -/*
> - * 2430-specific powerdomains
> - */
> -
> -/* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */
> -
> -static struct powerdomain mdm_pwrdm = {
> - .name = "mdm_pwrdm",
> - .prcm_offs = OMAP2430_MDM_MOD,
> - .pwrsts = PWRSTS_OFF_RET_ON,
> - .pwrsts_logic_ret = PWRSTS_RET,
> - .banks = 1,
> - .pwrsts_mem_ret = {
> - [0] = PWRSTS_RET, /* MEMRETSTATE */
> - },
> - .pwrsts_mem_on = {
> - [0] = PWRSTS_ON, /* MEMONSTATE */
> - },
> - .voltdm = { .name = "core" },
> -};
> -
> -/*
> - *
> - */
> -
> -static struct powerdomain *powerdomains_omap24xx[] __initdata = {
> - &wkup_omap2_pwrdm,
> - &gfx_omap2_pwrdm,
> - &dsp_pwrdm,
> - &mpu_24xx_pwrdm,
> - &core_24xx_pwrdm,
> - NULL
> -};
> -
> -static struct powerdomain *powerdomains_omap2430[] __initdata = {
> - &mdm_pwrdm,
> - NULL
> -};
> -
> -void __init omap242x_powerdomains_init(void)
> -{
> - if (!cpu_is_omap2420())
> - return;
> -
> - pwrdm_register_platform_funcs(&omap2_pwrdm_operations);
> - pwrdm_register_pwrdms(powerdomains_omap24xx);
> - pwrdm_complete_init();
> -}
> -
> -void __init omap243x_powerdomains_init(void)
> -{
> - if (!cpu_is_omap2430())
> - return;
> -
> - pwrdm_register_platform_funcs(&omap2_pwrdm_operations);
> - pwrdm_register_pwrdms(powerdomains_omap24xx);
> - pwrdm_register_pwrdms(powerdomains_omap2430);
> - pwrdm_complete_init();
> -}
> diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
> index 5e3544a63526..e326bb6a09db 100644
> --- a/arch/arm/mach-omap2/prcm-common.h
> +++ b/arch/arm/mach-omap2/prcm-common.h
> @@ -27,12 +27,6 @@
> #define PLL_MOD 0x500
>
>
> -/* Chip-specific module offsets */
> -#define OMAP24XX_GR_MOD OCP_MOD
> -#define OMAP24XX_DSP_MOD 0x800
> -
> -#define OMAP2430_MDM_MOD 0xc00
> -
> /* IVA2 module is < base on 3430 */
> #define OMAP3430_IVA2_MOD -0x800
> #define OMAP3430ES2_SGX_MOD GFX_MOD
> @@ -63,147 +57,6 @@
> #define TI816X_PRM_SGX_MOD 0x0f00
> #define TI81XX_PRM_ALWON_MOD 0x1800
>
> -/* 24XX register bits shared between CM & PRM registers */
> -
> -/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
> -#define OMAP2420_EN_MMC_SHIFT 26
> -#define OMAP2420_EN_MMC_MASK (1 << 26)
> -#define OMAP24XX_EN_UART2_SHIFT 22
> -#define OMAP24XX_EN_UART2_MASK (1 << 22)
> -#define OMAP24XX_EN_UART1_SHIFT 21
> -#define OMAP24XX_EN_UART1_MASK (1 << 21)
> -#define OMAP24XX_EN_MCSPI2_SHIFT 18
> -#define OMAP24XX_EN_MCSPI2_MASK (1 << 18)
> -#define OMAP24XX_EN_MCSPI1_SHIFT 17
> -#define OMAP24XX_EN_MCSPI1_MASK (1 << 17)
> -#define OMAP24XX_EN_MCBSP2_SHIFT 16
> -#define OMAP24XX_EN_MCBSP2_MASK (1 << 16)
> -#define OMAP24XX_EN_MCBSP1_SHIFT 15
> -#define OMAP24XX_EN_MCBSP1_MASK (1 << 15)
> -#define OMAP24XX_EN_GPT12_SHIFT 14
> -#define OMAP24XX_EN_GPT12_MASK (1 << 14)
> -#define OMAP24XX_EN_GPT11_SHIFT 13
> -#define OMAP24XX_EN_GPT11_MASK (1 << 13)
> -#define OMAP24XX_EN_GPT10_SHIFT 12
> -#define OMAP24XX_EN_GPT10_MASK (1 << 12)
> -#define OMAP24XX_EN_GPT9_SHIFT 11
> -#define OMAP24XX_EN_GPT9_MASK (1 << 11)
> -#define OMAP24XX_EN_GPT8_SHIFT 10
> -#define OMAP24XX_EN_GPT8_MASK (1 << 10)
> -#define OMAP24XX_EN_GPT7_SHIFT 9
> -#define OMAP24XX_EN_GPT7_MASK (1 << 9)
> -#define OMAP24XX_EN_GPT6_SHIFT 8
> -#define OMAP24XX_EN_GPT6_MASK (1 << 8)
> -#define OMAP24XX_EN_GPT5_SHIFT 7
> -#define OMAP24XX_EN_GPT5_MASK (1 << 7)
> -#define OMAP24XX_EN_GPT4_SHIFT 6
> -#define OMAP24XX_EN_GPT4_MASK (1 << 6)
> -#define OMAP24XX_EN_GPT3_SHIFT 5
> -#define OMAP24XX_EN_GPT3_MASK (1 << 5)
> -#define OMAP24XX_EN_GPT2_SHIFT 4
> -#define OMAP24XX_EN_GPT2_MASK (1 << 4)
> -#define OMAP2420_EN_VLYNQ_SHIFT 3
> -#define OMAP2420_EN_VLYNQ_MASK (1 << 3)
> -
> -/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
> -#define OMAP2430_EN_GPIO5_SHIFT 10
> -#define OMAP2430_EN_GPIO5_MASK (1 << 10)
> -#define OMAP2430_EN_MCSPI3_SHIFT 9
> -#define OMAP2430_EN_MCSPI3_MASK (1 << 9)
> -#define OMAP2430_EN_MMCHS2_SHIFT 8
> -#define OMAP2430_EN_MMCHS2_MASK (1 << 8)
> -#define OMAP2430_EN_MMCHS1_SHIFT 7
> -#define OMAP2430_EN_MMCHS1_MASK (1 << 7)
> -#define OMAP24XX_EN_UART3_SHIFT 2
> -#define OMAP24XX_EN_UART3_MASK (1 << 2)
> -#define OMAP24XX_EN_USB_SHIFT 0
> -#define OMAP24XX_EN_USB_MASK (1 << 0)
> -
> -/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
> -#define OMAP2430_EN_MDM_INTC_SHIFT 11
> -#define OMAP2430_EN_MDM_INTC_MASK (1 << 11)
> -#define OMAP2430_EN_USBHS_SHIFT 6
> -#define OMAP2430_EN_USBHS_MASK (1 << 6)
> -#define OMAP24XX_EN_GPMC_SHIFT 1
> -#define OMAP24XX_EN_GPMC_MASK (1 << 1)
> -
> -/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
> -#define OMAP2420_ST_MMC_SHIFT 26
> -#define OMAP2420_ST_MMC_MASK (1 << 26)
> -#define OMAP24XX_ST_UART2_SHIFT 22
> -#define OMAP24XX_ST_UART2_MASK (1 << 22)
> -#define OMAP24XX_ST_UART1_SHIFT 21
> -#define OMAP24XX_ST_UART1_MASK (1 << 21)
> -#define OMAP24XX_ST_MCSPI2_SHIFT 18
> -#define OMAP24XX_ST_MCSPI2_MASK (1 << 18)
> -#define OMAP24XX_ST_MCSPI1_SHIFT 17
> -#define OMAP24XX_ST_MCSPI1_MASK (1 << 17)
> -#define OMAP24XX_ST_MCBSP2_SHIFT 16
> -#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
> -#define OMAP24XX_ST_MCBSP1_SHIFT 15
> -#define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
> -#define OMAP24XX_ST_GPT12_SHIFT 14
> -#define OMAP24XX_ST_GPT12_MASK (1 << 14)
> -#define OMAP24XX_ST_GPT11_SHIFT 13
> -#define OMAP24XX_ST_GPT11_MASK (1 << 13)
> -#define OMAP24XX_ST_GPT10_SHIFT 12
> -#define OMAP24XX_ST_GPT10_MASK (1 << 12)
> -#define OMAP24XX_ST_GPT9_SHIFT 11
> -#define OMAP24XX_ST_GPT9_MASK (1 << 11)
> -#define OMAP24XX_ST_GPT8_SHIFT 10
> -#define OMAP24XX_ST_GPT8_MASK (1 << 10)
> -#define OMAP24XX_ST_GPT7_SHIFT 9
> -#define OMAP24XX_ST_GPT7_MASK (1 << 9)
> -#define OMAP24XX_ST_GPT6_SHIFT 8
> -#define OMAP24XX_ST_GPT6_MASK (1 << 8)
> -#define OMAP24XX_ST_GPT5_SHIFT 7
> -#define OMAP24XX_ST_GPT5_MASK (1 << 7)
> -#define OMAP24XX_ST_GPT4_SHIFT 6
> -#define OMAP24XX_ST_GPT4_MASK (1 << 6)
> -#define OMAP24XX_ST_GPT3_SHIFT 5
> -#define OMAP24XX_ST_GPT3_MASK (1 << 5)
> -#define OMAP24XX_ST_GPT2_SHIFT 4
> -#define OMAP24XX_ST_GPT2_MASK (1 << 4)
> -#define OMAP2420_ST_VLYNQ_SHIFT 3
> -#define OMAP2420_ST_VLYNQ_MASK (1 << 3)
> -
> -/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
> -#define OMAP2430_ST_MDM_INTC_SHIFT 11
> -#define OMAP2430_ST_MDM_INTC_MASK (1 << 11)
> -#define OMAP2430_ST_GPIO5_SHIFT 10
> -#define OMAP2430_ST_GPIO5_MASK (1 << 10)
> -#define OMAP2430_ST_MCSPI3_SHIFT 9
> -#define OMAP2430_ST_MCSPI3_MASK (1 << 9)
> -#define OMAP2430_ST_MMCHS2_SHIFT 8
> -#define OMAP2430_ST_MMCHS2_MASK (1 << 8)
> -#define OMAP2430_ST_MMCHS1_SHIFT 7
> -#define OMAP2430_ST_MMCHS1_MASK (1 << 7)
> -#define OMAP2430_ST_USBHS_SHIFT 6
> -#define OMAP2430_ST_USBHS_MASK (1 << 6)
> -#define OMAP24XX_ST_UART3_SHIFT 2
> -#define OMAP24XX_ST_UART3_MASK (1 << 2)
> -#define OMAP24XX_ST_USB_SHIFT 0
> -#define OMAP24XX_ST_USB_MASK (1 << 0)
> -
> -/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
> -#define OMAP24XX_EN_GPIOS_SHIFT 2
> -#define OMAP24XX_EN_GPIOS_MASK (1 << 2)
> -#define OMAP24XX_EN_GPT1_SHIFT 0
> -#define OMAP24XX_EN_GPT1_MASK (1 << 0)
> -
> -/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
> -#define OMAP24XX_ST_GPIOS_SHIFT 2
> -#define OMAP24XX_ST_GPIOS_MASK (1 << 2)
> -#define OMAP24XX_ST_32KSYNC_SHIFT 1
> -#define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
> -#define OMAP24XX_ST_GPT1_SHIFT 0
> -#define OMAP24XX_ST_GPT1_MASK (1 << 0)
> -
> -/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
> -#define OMAP2430_ST_MDM_SHIFT 0
> -#define OMAP2430_ST_MDM_MASK (1 << 0)
> -
> -
> /* 3430 register bits shared between CM & PRM registers */
>
> /* CM_REVISION, PRM_REVISION shared bits */
> diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
> deleted file mode 100644
> index ff83801f6439..000000000000
> --- a/arch/arm/mach-omap2/prm-regbits-24xx.h
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
> -#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
> -
> -/*
> - * OMAP24XX Power/Reset Management register bits
> - *
> - * Copyright (C) 2007 Texas Instruments, Inc.
> - * Copyright (C) 2007 Nokia Corporation
> - *
> - * Written by Paul Walmsley
> - */
> -
> -#include "prm2xxx.h"
> -
> -#define OMAP24XX_EN_CORE_SHIFT 0
> -#define OMAP24XX_FORCESTATE_MASK (1 << 18)
> -#define OMAP24XX_AUTOIDLE_MASK (1 << 0)
> -#define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15)
> -#define OMAP24XX_SETOFF_LEVEL_SHIFT 12
> -#define OMAP24XX_MEMRETCTRL_MASK (1 << 8)
> -#define OMAP24XX_SETRET_LEVEL_SHIFT 6
> -#define OMAP24XX_VOLT_LEVEL_SHIFT 0
> -#define OMAP2420_CLKOUT2_EN_SHIFT 15
> -#define OMAP2420_CLKOUT2_DIV_SHIFT 11
> -#define OMAP2420_CLKOUT2_DIV_WIDTH 3
> -#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
> -#define OMAP24XX_CLKOUT_EN_SHIFT 7
> -#define OMAP24XX_CLKOUT_DIV_SHIFT 3
> -#define OMAP24XX_CLKOUT_DIV_WIDTH 3
> -#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0)
> -#define OMAP24XX_EMULATION_EN_SHIFT 0
> -#define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5
> -#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2
> -#define OMAP24XX_EXTWMPU_RST_SHIFT 6
> -#define OMAP24XX_SECU_WD_RST_SHIFT 5
> -#define OMAP24XX_MPU_WD_RST_SHIFT 4
> -#define OMAP24XX_SECU_VIOL_RST_SHIFT 3
> -#endif
> diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
> deleted file mode 100644
> index 35a58f54b528..000000000000
> --- a/arch/arm/mach-omap2/prm2xxx.c
> +++ /dev/null
> @@ -1,229 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * OMAP2xxx PRM module functions
> - *
> - * Copyright (C) 2010-2012 Texas Instruments, Inc.
> - * Copyright (C) 2010 Nokia Corporation
> - * Benoît Cousson
> - * Paul Walmsley
> - * Rajendra Nayak <rnayak@ti.com>
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/errno.h>
> -#include <linux/err.h>
> -#include <linux/io.h>
> -#include <linux/irq.h>
> -
> -#include "powerdomain.h"
> -#include "clockdomain.h"
> -#include "prm2xxx.h"
> -#include "cm2xxx_3xxx.h"
> -#include "prm-regbits-24xx.h"
> -
> -/*
> - * OMAP24xx PM_PWSTCTRL_*.POWERSTATE and PM_PWSTST_*.LASTSTATEENTERED bits -
> - * these are reversed from the bits used on OMAP3+
> - */
> -#define OMAP24XX_PWRDM_POWER_ON 0x0
> -#define OMAP24XX_PWRDM_POWER_RET 0x1
> -#define OMAP24XX_PWRDM_POWER_OFF 0x3
> -
> -/*
> - * omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP
> - * hardware register (which are specific to the OMAP2xxx SoCs) to
> - * reset source ID bit shifts (which is an OMAP SoC-independent
> - * enumeration)
> - */
> -static struct prm_reset_src_map omap2xxx_prm_reset_src_map[] = {
> - { OMAP_GLOBALCOLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
> - { OMAP_GLOBALWARM_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
> - { OMAP24XX_SECU_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
> - { OMAP24XX_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
> - { OMAP24XX_SECU_WD_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
> - { OMAP24XX_EXTWMPU_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
> - { -1, -1 },
> -};
> -
> -/**
> - * omap2xxx_prm_read_reset_sources - return the last SoC reset source
> - *
> - * Return a u32 representing the last reset sources of the SoC. The
> - * returned reset source bits are standardized across OMAP SoCs.
> - */
> -static u32 omap2xxx_prm_read_reset_sources(void)
> -{
> - struct prm_reset_src_map *p;
> - u32 r = 0;
> - u32 v;
> -
> - v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);
> -
> - p = omap2xxx_prm_reset_src_map;
> - while (p->reg_shift >= 0 && p->std_shift >= 0) {
> - if (v & (1 << p->reg_shift))
> - r |= 1 << p->std_shift;
> - p++;
> - }
> -
> - return r;
> -}
> -
> -/**
> - * omap2xxx_pwrst_to_common_pwrst - convert OMAP2xxx pwrst to common pwrst
> - * @omap2xxx_pwrst: OMAP2xxx hardware power state to convert
> - *
> - * Return the common power state bits corresponding to the OMAP2xxx
> - * hardware power state bits @omap2xxx_pwrst, or -EINVAL upon error.
> - */
> -static int omap2xxx_pwrst_to_common_pwrst(u8 omap2xxx_pwrst)
> -{
> - u8 pwrst;
> -
> - switch (omap2xxx_pwrst) {
> - case OMAP24XX_PWRDM_POWER_OFF:
> - pwrst = PWRDM_POWER_OFF;
> - break;
> - case OMAP24XX_PWRDM_POWER_RET:
> - pwrst = PWRDM_POWER_RET;
> - break;
> - case OMAP24XX_PWRDM_POWER_ON:
> - pwrst = PWRDM_POWER_ON;
> - break;
> - default:
> - return -EINVAL;
> - }
> -
> - return pwrst;
> -}
> -
> -/**
> - * omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC
> - *
> - * Set the DPLL reset bit, which should reboot the SoC. This is the
> - * recommended way to restart the SoC. No return value.
> - */
> -static void omap2xxx_prm_dpll_reset(void)
> -{
> - omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, WKUP_MOD,
> - OMAP2_RM_RSTCTRL);
> - /* OCP barrier */
> - omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL);
> -}
> -
> -/**
> - * omap2xxx_prm_clear_mod_irqs - clear wakeup status bits for a module
> - * @module: PRM module to clear wakeups from
> - * @regs: register offset to clear
> - * @wkst_mask: wakeup status mask to clear
> - *
> - * Clears wakeup status bits for a given module, so that the device can
> - * re-enter idle.
> - */
> -static int omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
> -{
> - u32 wkst;
> -
> - wkst = omap2_prm_read_mod_reg(module, regs);
> - wkst &= wkst_mask;
> - omap2_prm_write_mod_reg(wkst, module, regs);
> - return 0;
> -}
> -
> -int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
> -{
> - omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
> - clkdm->pwrdm.ptr->prcm_offs,
> - OMAP2_PM_PWSTCTRL);
> - return 0;
> -}
> -
> -int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm)
> -{
> - omap2_prm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
> - clkdm->pwrdm.ptr->prcm_offs,
> - OMAP2_PM_PWSTCTRL);
> - return 0;
> -}
> -
> -static int omap2xxx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
> -{
> - u8 omap24xx_pwrst;
> -
> - switch (pwrst) {
> - case PWRDM_POWER_OFF:
> - omap24xx_pwrst = OMAP24XX_PWRDM_POWER_OFF;
> - break;
> - case PWRDM_POWER_RET:
> - omap24xx_pwrst = OMAP24XX_PWRDM_POWER_RET;
> - break;
> - case PWRDM_POWER_ON:
> - omap24xx_pwrst = OMAP24XX_PWRDM_POWER_ON;
> - break;
> - default:
> - return -EINVAL;
> - }
> -
> - omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
> - (omap24xx_pwrst << OMAP_POWERSTATE_SHIFT),
> - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
> - return 0;
> -}
> -
> -static int omap2xxx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
> -{
> - u8 omap2xxx_pwrst;
> -
> - omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> - OMAP2_PM_PWSTCTRL,
> - OMAP_POWERSTATE_MASK);
> -
> - return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst);
> -}
> -
> -static int omap2xxx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
> -{
> - u8 omap2xxx_pwrst;
> -
> - omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> - OMAP2_PM_PWSTST,
> - OMAP_POWERSTATEST_MASK);
> -
> - return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst);
> -}
> -
> -struct pwrdm_ops omap2_pwrdm_operations = {
> - .pwrdm_set_next_pwrst = omap2xxx_pwrdm_set_next_pwrst,
> - .pwrdm_read_next_pwrst = omap2xxx_pwrdm_read_next_pwrst,
> - .pwrdm_read_pwrst = omap2xxx_pwrdm_read_pwrst,
> - .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
> - .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
> - .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
> - .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst,
> - .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst,
> - .pwrdm_wait_transition = omap2_pwrdm_wait_transition,
> -};
> -
> -/*
> - *
> - */
> -
> -static struct prm_ll_data omap2xxx_prm_ll_data = {
> - .read_reset_sources = &omap2xxx_prm_read_reset_sources,
> - .assert_hardreset = &omap2_prm_assert_hardreset,
> - .deassert_hardreset = &omap2_prm_deassert_hardreset,
> - .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
> - .reset_system = &omap2xxx_prm_dpll_reset,
> - .clear_mod_irqs = &omap2xxx_prm_clear_mod_irqs,
> -};
> -
> -int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data)
> -{
> - return prm_register(&omap2xxx_prm_ll_data);
> -}
> -
> -static void __exit omap2xxx_prm_exit(void)
> -{
> - prm_unregister(&omap2xxx_prm_ll_data);
> -}
> -__exitcall(omap2xxx_prm_exit);
> diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
> deleted file mode 100644
> index 659b917348f8..000000000000
> --- a/arch/arm/mach-omap2/prm2xxx.h
> +++ /dev/null
> @@ -1,128 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * OMAP2xxx Power/Reset Management (PRM) register definitions
> - *
> - * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
> - * Copyright (C) 2008-2010 Nokia Corporation
> - * Paul Walmsley
> - *
> - * The PRM hardware modules on the OMAP2/3 are quite similar to each
> - * other. The PRM on OMAP4 has a new register layout, and is handled
> - * in a separate file.
> - */
> -#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
> -#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
> -
> -#include "prcm-common.h"
> -#include "prm.h"
> -#include "prm2xxx_3xxx.h"
> -
> -#define OMAP2420_PRM_REGADDR(module, reg) \
> - OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
> -#define OMAP2430_PRM_REGADDR(module, reg) \
> - OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
> -
> -/*
> - * OMAP2-specific global PRM registers
> - * Use {read,write}l_relaxed() with these registers.
> - *
> - * With a few exceptions, these are the register names beginning with
> - * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE
> - * bits.)
> - *
> - */
> -
> -#define OMAP2_PRCM_REVISION_OFFSET 0x0000
> -#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
> -#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
> -#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
> -
> -#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
> -#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
> -#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
> -#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
> -
> -#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
> -#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
> -#define OMAP2_PRCM_VOLTST_OFFSET 0x0054
> -#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
> -#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
> -#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
> -#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
> -#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
> -#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
> -#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
> -#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
> -#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
> -#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
> -#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
> -#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
> -#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
> -#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
> -#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
> -#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
> -#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
> -
> -#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
> -#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
> -
> -#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
> -#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
> -
> -#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
> -#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
> -#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
> -#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
> -#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
> -#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
> -#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
> -#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
> -#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
> -#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
> -
> -/*
> - * Module specific PRM register offsets from PRM_BASE + domain offset
> - *
> - * Use prm_{read,write}_mod_reg() with these registers.
> - *
> - * With a few exceptions, these are the register names beginning with
> - * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the
> - * IRQSTATUS and IRQENABLE bits.)
> - */
> -
> -/* Register offsets appearing on both OMAP2 and OMAP3 */
> -
> -#define OMAP2_RM_RSTCTRL 0x0050
> -#define OMAP2_RM_RSTTIME 0x0054
> -#define OMAP2_RM_RSTST 0x0058
> -#define OMAP2_PM_PWSTCTRL 0x00e0
> -#define OMAP2_PM_PWSTST 0x00e4
> -
> -#define PM_WKEN 0x00a0
> -#define PM_WKEN1 PM_WKEN
> -#define PM_WKST 0x00b0
> -#define PM_WKST1 PM_WKST
> -#define PM_WKDEP 0x00c8
> -#define PM_EVGENCTRL 0x00d4
> -#define PM_EVGENONTIM 0x00d8
> -#define PM_EVGENOFFTIM 0x00dc
> -
> -/* OMAP2xxx specific register offsets */
> -#define OMAP24XX_PM_WKEN2 0x00a4
> -#define OMAP24XX_PM_WKST2 0x00b4
> -
> -#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
> -#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
> -#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
> -#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
> -
> -#ifndef __ASSEMBLER__
> -/* Function prototypes */
> -extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
> -extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
> -
> -int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data);
> -
> -#endif
> -
> -#endif
> diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
> index d983efac6f4f..afaba7153ece 100644
> --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
> +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
> @@ -15,7 +15,6 @@
>
> #include "powerdomain.h"
> #include "prm2xxx_3xxx.h"
> -#include "prm-regbits-24xx.h"
> #include "clockdomain.h"
>
> /**
> diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
> index ee4588acda50..3546e7292bfb 100644
> --- a/arch/arm/mach-omap2/prm_common.c
> +++ b/arch/arm/mach-omap2/prm_common.c
> @@ -26,7 +26,6 @@
>
> #include "soc.h"
> #include "prm2xxx_3xxx.h"
> -#include "prm2xxx.h"
> #include "prm3xxx.h"
> #include "prm33xx.h"
> #include "prm44xx.h"
> @@ -582,13 +581,6 @@ int prm_unregister(struct prm_ll_data *pld)
> return 0;
> }
>
> -#ifdef CONFIG_ARCH_OMAP2
> -static struct omap_prcm_init_data omap2_prm_data __initdata = {
> - .index = TI_CLKM_PRM,
> - .init = omap2xxx_prm_init,
> -};
> -#endif
> -
> #ifdef CONFIG_ARCH_OMAP3
> static struct omap_prcm_init_data omap3_prm_data __initdata = {
> .index = TI_CLKM_PRM,
> @@ -670,9 +662,6 @@ static const struct of_device_id omap_prcm_dt_match_table[] __initconst = {
> { .compatible = "ti,dm814-pllss", .data = &dm814_pllss_data },
> { .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
> #endif
> -#ifdef CONFIG_ARCH_OMAP2
> - { .compatible = "ti,omap2-prcm", .data = &omap2_prm_data },
> -#endif
> #ifdef CONFIG_ARCH_OMAP3
> { .compatible = "ti,omap3-prm", .data = &omap3_prm_data },
> #endif
> diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
> index 45b35422b587..c34fba4d2f1a 100644
> --- a/arch/arm/mach-omap2/sdrc.h
> +++ b/arch/arm/mach-omap2/sdrc.h
> @@ -90,17 +90,7 @@ struct memory_timings {
> u32 base_cs; /* base chip select to use for calculations */
> };
>
> -extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
> -
> -u32 omap2xxx_sdrc_dll_is_unlocked(void);
> -u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
> -
> -
> #else
> -#define OMAP242X_SDRC_REGADDR(reg) \
> - OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
> -#define OMAP243X_SDRC_REGADDR(reg) \
> - OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
> #define OMAP34XX_SDRC_REGADDR(reg) \
> OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
>
> @@ -184,17 +174,6 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
> #define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
>
>
> -/*
> - * SMS register access
> - */
> -
> -#define OMAP242X_SMS_REGADDR(reg) \
> - (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
> -#define OMAP243X_SMS_REGADDR(reg) \
> - (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
> -#define OMAP343X_SMS_REGADDR(reg) \
> - (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
> -
> /* SMS register offsets - read/write with sms_{read,write}_reg() */
>
> #define SMS_SYSCONFIG 0x010
> diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
> deleted file mode 100644
> index 5a275b4fd404..000000000000
> --- a/arch/arm/mach-omap2/sdrc2xxx.c
> +++ /dev/null
> @@ -1,164 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * SDRAM timing related functions for OMAP2xxx
> - *
> - * Copyright (C) 2005, 2008 Texas Instruments Inc.
> - * Copyright (C) 2005, 2008 Nokia Corporation
> - *
> - * Tony Lindgren <tony@atomide.com>
> - * Paul Walmsley
> - * Richard Woodruff <r-woodruff2@ti.com>
> - */
> -
> -#include <linux/module.h>
> -#include <linux/kernel.h>
> -#include <linux/device.h>
> -#include <linux/list.h>
> -#include <linux/errno.h>
> -#include <linux/delay.h>
> -#include <linux/clk.h>
> -#include <linux/io.h>
> -
> -#include "soc.h"
> -#include "iomap.h"
> -#include "common.h"
> -#include "prm2xxx.h"
> -#include "clock.h"
> -#include "sdrc.h"
> -#include "sram.h"
> -
> -/* Memory timing, DLL mode flags */
> -#define M_DDR 1
> -#define M_LOCK_CTRL (1 << 2)
> -#define M_UNLOCK 0
> -#define M_LOCK 1
> -
> -
> -static struct memory_timings mem_timings;
> -static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
> -
> -static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
> -{
> - return mem_timings.slow_dll_ctrl;
> -}
> -
> -static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
> -{
> - return mem_timings.fast_dll_ctrl;
> -}
> -
> -static u32 omap2xxx_sdrc_get_type(void)
> -{
> - return mem_timings.m_type;
> -}
> -
> -/*
> - * Check the DLL lock state, and return tue if running in unlock mode.
> - * This is needed to compensate for the shifted DLL value in unlock mode.
> - */
> -u32 omap2xxx_sdrc_dll_is_unlocked(void)
> -{
> - /* dlla and dllb are a set */
> - u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
> -
> - if ((dll_state & (1 << 2)) == (1 << 2))
> - return 1;
> - else
> - return 0;
> -}
> -
> -/*
> - * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
> - * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
> - * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
> - *
> - * Used by the clock framework during CORE DPLL changes
> - */
> -u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
> -{
> - u32 dll_ctrl, m_type;
> - u32 prev = curr_perf_level;
> - unsigned long flags;
> -
> - if ((curr_perf_level == level) && !force)
> - return prev;
> -
> - if (level == CORE_CLK_SRC_DPLL)
> - dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
> - else if (level == CORE_CLK_SRC_DPLL_X2)
> - dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
> - else
> - return prev;
> -
> - m_type = omap2xxx_sdrc_get_type();
> -
> - local_irq_save(flags);
> - /*
> - * XXX These calls should be abstracted out through a
> - * prm2xxx.c function
> - */
> - if (cpu_is_omap2420())
> - writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP);
> - else
> - writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP);
> - omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
> - curr_perf_level = level;
> - local_irq_restore(flags);
> -
> - return prev;
> -}
> -
> -/* Used by the clock framework during CORE DPLL changes */
> -void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
> -{
> - unsigned long dll_cnt;
> - u32 fast_dll = 0;
> -
> - /* DDR = 1, SDR = 0 */
> - mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
> -
> - /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
> - * In the case of 2422, its ok to use CS1 instead of CS0.
> - */
> - if (cpu_is_omap2422())
> - mem_timings.base_cs = 1;
> - else
> - mem_timings.base_cs = 0;
> -
> - if (mem_timings.m_type != M_DDR)
> - return;
> -
> - /* With DDR we need to determine the low frequency DLL value */
> - if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
> - mem_timings.dll_mode = M_UNLOCK;
> - else
> - mem_timings.dll_mode = M_LOCK;
> -
> - if (mem_timings.base_cs == 0) {
> - fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
> - dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
> - } else {
> - fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
> - dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
> - }
> - if (force_lock_to_unlock_mode) {
> - fast_dll &= ~0xff00;
> - fast_dll |= dll_cnt; /* Current lock mode */
> - }
> - /* set fast timings with DLL filter disabled */
> - mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
> -
> - /* No disruptions, DDR will be offline & C-ABI not followed */
> - omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
> - mem_timings.fast_dll_ctrl,
> - mem_timings.base_cs,
> - force_lock_to_unlock_mode);
> - mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
> -
> - /* Turn status into unlock ctrl */
> - mem_timings.slow_dll_ctrl |=
> - ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
> -
> - /* 90 degree phase for anything below 133MHz + disable DLL filter */
> - mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
> -}
> diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S
> deleted file mode 100644
> index 84d8c43ad382..000000000000
> --- a/arch/arm/mach-omap2/sleep24xx.S
> +++ /dev/null
> @@ -1,91 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-or-later */
> -/*
> - * linux/arch/arm/mach-omap2/sleep.S
> - *
> - * (C) Copyright 2004
> - * Texas Instruments, <www.ti.com>
> - * Richard Woodruff <r-woodruff2@ti.com>
> - *
> - * (C) Copyright 2006 Nokia Corporation
> - * Fixed idle loop sleep
> - * Igor Stoppa <igor.stoppa@nokia.com>
> - */
> -
> -#include <linux/linkage.h>
> -#include <asm/assembler.h>
> -
> -#include "omap24xx.h"
> -#include "sdrc.h"
> -
> -/* First address of reserved address space? apparently valid for OMAP2 & 3 */
> -#define A_SDRC0_V (0xC0000000)
> -
> - .text
> -
> -/*
> - * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
> - * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore
> - * SDRC.
> - *
> - * Input:
> - * R0 : DLL ctrl value pre-Sleep
> - * R1 : SDRC_DLLA_CTRL
> - * R2 : SDRC_POWER
> - *
> - * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
> - * when we get called, but the DLL probably isn't. We will wait a bit more in
> - * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
> - * if in unlocked mode.
> - *
> - * For less than 242x-ES2.2 upon wake from a sleep mode where the external
> - * oscillator was stopped, a timing bug exists where a non-stabilized 12MHz
> - * clock can pass into the PRCM can cause problems at DSP and IVA.
> - * To work around this the code will switch to the 32kHz source prior to sleep.
> - * Post sleep we will shift back to using the DPLL. Apparently,
> - * CM_IDLEST_CLKGEN does not reflect the full clock change so you need to wait
> - * 3x12MHz + 3x32kHz clocks for a full switch.
> - *
> - * The DLL load value is not kept in RETENTION or OFF. It needs to be restored
> - * at wake
> - */
> - .align 3
> -ENTRY(omap24xx_cpu_suspend)
> - stmfd sp!, {r0 - r12, lr} @ save registers on stack
> - mov r3, #0x0 @ clear for mcr call
> - mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
> - nop
> - nop
> - ldr r4, [r2] @ read SDRC_POWER
> - orr r4, r4, #0x40 @ enable self refresh on idle req
> - mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
> - str r4, [r2] @ make it so
> - nop
> - mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt
> - nop
> -loop:
> - subs r5, r5, #0x1 @ awake, wait just a bit
> - bne loop
> -
> - /* The DPLL has to be on before we take the DDR out of self refresh */
> - bic r4, r4, #0x40 @ now clear self refresh bit.
> - str r4, [r2] @ write to SDRC_POWER
> - ldr r4, A_SDRC0 @ make a clock happen
> - ldr r4, [r4] @ read A_SDRC0
> - nop @ start auto refresh only after clk ok
> - movs r0, r0 @ see if DDR or SDR
> - strne r0, [r1] @ rewrite DLLA to force DLL reload
> - addne r1, r1, #0x8 @ move to DLLB
> - strne r0, [r1] @ rewrite DLLB to force DLL reload
> -
> - mov r5, #0x1000
> -loop2:
> - subs r5, r5, #0x1
> - bne loop2
> - /* resume*/
> - ldmfd sp!, {r0 - r12, pc} @ restore regs and return
> -
> -A_SDRC0:
> - .word A_SDRC0_V
> -
> -ENTRY(omap24xx_cpu_suspend_sz)
> - .word . - omap24xx_cpu_suspend
> diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
> index 9e3dbb743e5c..9c9f56ca9142 100644
> --- a/arch/arm/mach-omap2/soc.h
> +++ b/arch/arm/mach-omap2/soc.h
> @@ -12,7 +12,6 @@
> * Added DRA7xxx specific defines - Sricharan R<r.sricharan@ti.com>
> */
>
> -#include "omap24xx.h"
> #include "omap34xx.h"
> #include "omap44xx.h"
> #include "ti81xx.h"
> @@ -62,9 +61,6 @@ static inline int soc_is_omap(void)
> /*
> * Macros to group OMAP into cpu classes.
> * These can be used in most places.
> - * soc_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
> - * soc_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
> - * soc_is_omap243x(): True for OMAP2430
> * soc_is_omap343x(): True for OMAP3430
> * soc_is_omap443x(): True for OMAP4430
> * soc_is_omap446x(): True for OMAP4460
> @@ -137,7 +133,6 @@ static inline int is_dra ##subclass ##_ ##package (void) \
> return (is_dra ##subclass () && GET_DRA_PACKAGE == id) ? 1 : 0; \
> }
>
> -IS_OMAP_CLASS(24xx, 0x24)
> IS_OMAP_CLASS(34xx, 0x34)
> IS_OMAP_CLASS(44xx, 0x44)
> IS_AM_CLASS(35xx, 0x35)
> @@ -148,8 +143,6 @@ IS_AM_CLASS(43xx, 0x43)
> IS_TI_CLASS(81xx, 0x81)
> IS_DRA_CLASS(7xx, 0x7)
>
> -IS_OMAP_SUBCLASS(242x, 0x242)
> -IS_OMAP_SUBCLASS(243x, 0x243)
> IS_OMAP_SUBCLASS(343x, 0x343)
> IS_OMAP_SUBCLASS(363x, 0x363)
> IS_OMAP_SUBCLASS(443x, 0x443)
> @@ -186,21 +179,6 @@ IS_DRA_SUBCLASS(72x, 0x72)
> #define soc_is_dra74x() 0
> #define soc_is_dra72x() 0
>
> -#if defined(CONFIG_ARCH_OMAP2)
> -# define soc_is_omap24xx() is_omap24xx()
> -#else
> -# define soc_is_omap24xx() 0
> -#endif
> -#if defined(CONFIG_SOC_OMAP2420)
> -# define soc_is_omap242x() is_omap242x()
> -#else
> -# define soc_is_omap242x() 0
> -#endif
> -#if defined(CONFIG_SOC_OMAP2430)
> -# define soc_is_omap243x() is_omap243x()
> -#else
> -# define soc_is_omap243x() 0
> -#endif
> #if defined(CONFIG_ARCH_OMAP3)
> # define soc_is_omap34xx() is_omap34xx()
> # define soc_is_omap343x() is_omap343x()
> @@ -212,10 +190,6 @@ IS_DRA_SUBCLASS(72x, 0x72)
> /*
> * Macros to detect individual cpu types.
> * These are only rarely needed.
> - * soc_is_omap2420(): True for OMAP2420
> - * soc_is_omap2422(): True for OMAP2422
> - * soc_is_omap2423(): True for OMAP2423
> - * soc_is_omap2430(): True for OMAP2430
> * soc_is_omap3430(): True for OMAP3430
> */
> #define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
> @@ -226,16 +200,8 @@ static inline int is_omap ##type (void) \
> return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
> }
>
> -IS_OMAP_TYPE(2420, 0x2420)
> -IS_OMAP_TYPE(2422, 0x2422)
> -IS_OMAP_TYPE(2423, 0x2423)
> -IS_OMAP_TYPE(2430, 0x2430)
> IS_OMAP_TYPE(3430, 0x3430)
>
> -#define soc_is_omap2420() 0
> -#define soc_is_omap2422() 0
> -#define soc_is_omap2423() 0
> -#define soc_is_omap2430() 0
> #define soc_is_omap3430() 0
> #define soc_is_omap3630() 0
> #define soc_is_omap5430() 0
> @@ -252,17 +218,6 @@ IS_OMAP_TYPE(3430, 0x3430)
> #define cpu_class_is_omap1() 0
> #define cpu_class_is_omap2() 1
>
> -#if defined(CONFIG_ARCH_OMAP2)
> -# undef soc_is_omap2420
> -# undef soc_is_omap2422
> -# undef soc_is_omap2423
> -# undef soc_is_omap2430
> -# define soc_is_omap2420() is_omap2420()
> -# define soc_is_omap2422() is_omap2422()
> -# define soc_is_omap2423() is_omap2423()
> -# define soc_is_omap2430() is_omap2430()
> -#endif
> -
> #if defined(CONFIG_ARCH_OMAP3)
> # undef soc_is_omap3430
> # undef soc_is_ti81xx
> @@ -326,13 +281,6 @@ IS_OMAP_TYPE(3430, 0x3430)
> #endif
>
> /* Various silicon revisions for omap2 */
> -#define OMAP242X_CLASS 0x24200024
> -#define OMAP2420_REV_ES1_0 OMAP242X_CLASS
> -#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (0x1 << 8))
> -
> -#define OMAP243X_CLASS 0x24300024
> -#define OMAP2430_REV_ES1_0 OMAP243X_CLASS
> -
> #define OMAP343X_CLASS 0x34300034
> #define OMAP3430_REV_ES1_0 OMAP343X_CLASS
> #define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (0x1 << 8))
> @@ -400,7 +348,6 @@ IS_OMAP_TYPE(3430, 0x3430)
> #define DRA722_REV_ES2_0 (DRA7XX_CLASS | (0x22 << 16) | (0x20 << 8))
> #define DRA722_REV_ES2_1 (DRA7XX_CLASS | (0x22 << 16) | (0x21 << 8))
>
> -void omap2xxx_check_revision(void);
> void omap3xxx_check_revision(void);
> void omap4xxx_check_revision(void);
> void omap5xxx_check_revision(void);
> @@ -484,12 +431,6 @@ level(__##fn);
> #define omap_late_initcall_sync(fn) omap_initcall(late_initcall_sync, fn)
>
> /* Legacy defines, these can be removed when users are removed */
> -#define cpu_is_omap2420() soc_is_omap2420()
> -#define cpu_is_omap2422() soc_is_omap2422()
> -#define cpu_is_omap242x() soc_is_omap242x()
> -#define cpu_is_omap2430() soc_is_omap2430()
> -#define cpu_is_omap243x() soc_is_omap243x()
> -#define cpu_is_omap24xx() soc_is_omap24xx()
> #define cpu_is_omap3430() soc_is_omap3430()
> #define cpu_is_omap343x() soc_is_omap343x()
> #define cpu_is_omap34xx() soc_is_omap34xx()
> diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
> index 898b011ae8d9..8f980849f201 100644
> --- a/arch/arm/mach-omap2/sram.c
> +++ b/arch/arm/mach-omap2/sram.c
> @@ -28,15 +28,10 @@
> #include "sdrc.h"
> #include "sram.h"
>
> -#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
> #define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
>
> #define SRAM_BOOTLOADER_SZ 0x00
>
> -#define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
> -#define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
> -#define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
> -
> #define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
> #define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
> #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
> @@ -120,18 +115,11 @@ static int is_sram_locked(void)
> {
> if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
> /* RAMFW: R/W access to all initiators for all qualifier sets */
> - if (cpu_is_omap242x()) {
> - writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
> - writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
> - writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
> - }
> - if (cpu_is_omap34xx()) {
> - writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
> - writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
> - writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
> - writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
> - writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
> - }
> + writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
> + writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
> + writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
> + writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
> + writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
> return 0;
> } else
> return 1; /* assume locked with no PPA or security driver */
> @@ -147,30 +135,17 @@ static void __init omap_detect_sram(void)
> {
> omap_sram_skip = SRAM_BOOTLOADER_SZ;
> if (is_sram_locked()) {
> - if (cpu_is_omap34xx()) {
> - omap_sram_start = OMAP3_SRAM_PUB_PA;
> - if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
> - (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
> - omap_sram_size = 0x7000; /* 28K */
> - omap_sram_skip += SZ_16K;
> - } else {
> - omap_sram_size = 0x8000; /* 32K */
> - }
> + omap_sram_start = OMAP3_SRAM_PUB_PA;
> + if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
> + (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
> + omap_sram_size = 0x7000; /* 28K */
> + omap_sram_skip += SZ_16K;
> } else {
> - omap_sram_start = OMAP2_SRAM_PUB_PA;
> - omap_sram_size = 0x800; /* 2K */
> + omap_sram_size = 0x8000; /* 32K */
> }
> } else {
> - if (cpu_is_omap34xx()) {
> - omap_sram_start = OMAP3_SRAM_PA;
> - omap_sram_size = 0x10000; /* 64K */
> - } else {
> - omap_sram_start = OMAP2_SRAM_PA;
> - if (cpu_is_omap242x())
> - omap_sram_size = 0xa0000; /* 640K */
> - else if (cpu_is_omap243x())
> - omap_sram_size = 0x10000; /* 64K */
> - }
> + omap_sram_start = OMAP3_SRAM_PA;
> + omap_sram_size = 0x10000; /* 64K */
> }
> }
>
> @@ -181,24 +156,20 @@ static void __init omap2_map_sram(void)
> {
> unsigned long base;
> int pages;
> - int cached = 1;
> -
> - if (cpu_is_omap34xx()) {
> - /*
> - * SRAM must be marked as non-cached on OMAP3 since the
> - * CORE DPLL M2 divider change code (in SRAM) runs with the
> - * SDRAM controller disabled, and if it is marked cached,
> - * the ARM may attempt to write cache lines back to SDRAM
> - * which will cause the system to hang.
> - */
> - cached = 0;
> - }
>
> if (omap_sram_size == 0)
> return;
>
> omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
> - omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size, cached);
> + /*
> + * SRAM must be marked as non-cached on OMAP3 since the
> + * CORE DPLL M2 divider change code (in SRAM) runs with the
> + * SDRAM controller disabled, and if it is marked cached,
> + * the ARM may attempt to write cache lines back to SDRAM
> + * which will cause the system to hang.
> + */
> +
> + omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size, 0);
> if (!omap_sram_base) {
> pr_err("SRAM: Could not map\n");
> return;
> @@ -219,78 +190,6 @@ static void __init omap2_map_sram(void)
> set_memory_rox(base, pages);
> }
>
> -static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
> - u32 base_cs, u32 force_unlock);
> -
> -void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
> - u32 base_cs, u32 force_unlock)
> -{
> - BUG_ON(!_omap2_sram_ddr_init);
> - _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
> - base_cs, force_unlock);
> -}
> -
> -static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
> - u32 mem_type);
> -
> -void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
> -{
> - BUG_ON(!_omap2_sram_reprogram_sdrc);
> - _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
> -}
> -
> -static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
> -
> -u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
> -{
> - BUG_ON(!_omap2_set_prcm);
> - return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
> -}
> -
> -#ifdef CONFIG_SOC_OMAP2420
> -static int __init omap242x_sram_init(void)
> -{
> - _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
> - omap242x_sram_ddr_init_sz);
> -
> - _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
> - omap242x_sram_reprogram_sdrc_sz);
> -
> - _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
> - omap242x_sram_set_prcm_sz);
> -
> - return 0;
> -}
> -#else
> -static inline int omap242x_sram_init(void)
> -{
> - return 0;
> -}
> -#endif
> -
> -#ifdef CONFIG_SOC_OMAP2430
> -static int __init omap243x_sram_init(void)
> -{
> - _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
> - omap243x_sram_ddr_init_sz);
> -
> - _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
> - omap243x_sram_reprogram_sdrc_sz);
> -
> - _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
> - omap243x_sram_set_prcm_sz);
> -
> - return 0;
> -}
> -#else
> -static inline int omap243x_sram_init(void)
> -{
> - return 0;
> -}
> -#endif
> -
> -#ifdef CONFIG_ARCH_OMAP3
> -
> void omap3_sram_restore_context(void)
> {
> omap_sram_reset();
> @@ -303,24 +202,12 @@ static inline int omap34xx_sram_init(void)
> omap3_sram_restore_context();
> return 0;
> }
> -#else
> -static inline int omap34xx_sram_init(void)
> -{
> - return 0;
> -}
> -#endif /* CONFIG_ARCH_OMAP3 */
>
> int __init omap_sram_init(void)
> {
> omap_detect_sram();
> omap2_map_sram();
> -
> - if (cpu_is_omap242x())
> - omap242x_sram_init();
> - else if (cpu_is_omap2430())
> - omap243x_sram_init();
> - else if (cpu_is_omap34xx())
> - omap34xx_sram_init();
> + omap34xx_sram_init();
>
> return 0;
> }
> diff --git a/arch/arm/mach-omap2/sram.h b/arch/arm/mach-omap2/sram.h
> index 030cabc39821..2db2c4598cdb 100644
> --- a/arch/arm/mach-omap2/sram.h
> +++ b/arch/arm/mach-omap2/sram.h
> @@ -5,43 +5,12 @@
>
> #ifndef __ASSEMBLY__
>
> -extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
> - u32 base_cs, u32 force_unlock);
> -extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
> - u32 mem_type);
> -extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
> -
> extern void omap3_sram_restore_context(void);
>
> extern int __init omap_sram_init(void);
>
> extern void *omap_sram_push(void *funcp, unsigned long size);
>
> -extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
> - u32 base_cs, u32 force_unlock);
> -extern unsigned long omap242x_sram_ddr_init_sz;
> -
> -extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
> - int bypass);
> -extern unsigned long omap242x_sram_set_prcm_sz;
> -
> -extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
> - u32 mem_type);
> -extern unsigned long omap242x_sram_reprogram_sdrc_sz;
> -
> -
> -extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
> - u32 base_cs, u32 force_unlock);
> -extern unsigned long omap243x_sram_ddr_init_sz;
> -
> -extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
> - int bypass);
> -extern unsigned long omap243x_sram_set_prcm_sz;
> -
> -extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
> - u32 mem_type);
> -extern unsigned long omap243x_sram_reprogram_sdrc_sz;
> -
> #ifdef CONFIG_PM
> extern void omap_push_sram_idle(void);
> #else
> @@ -54,5 +23,4 @@ static inline void omap_push_sram_idle(void) {}
> * OMAP2+: define the SRAM PA addresses.
> * Used by the SRAM management code and the idle sleep code.
> */
> -#define OMAP2_SRAM_PA 0x40200000
> #define OMAP3_SRAM_PA 0x40200000
> diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
> deleted file mode 100644
> index 92ef21ac2ac1..000000000000
> --- a/arch/arm/mach-omap2/sram242x.S
> +++ /dev/null
> @@ -1,317 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-or-later */
> -/*
> - * linux/arch/arm/mach-omap2/sram242x.S
> - *
> - * Omap2 specific functions that need to be run in internal SRAM
> - *
> - * (C) Copyright 2004
> - * Texas Instruments, <www.ti.com>
> - * Richard Woodruff <r-woodruff2@ti.com>
> - *
> - * Richard Woodruff notes that any changes to this code must be carefully
> - * audited and tested to ensure that they don't cause a TLB miss while
> - * the SDRAM is inaccessible. Such a situation will crash the system
> - * since it will cause the ARM MMU to attempt to walk the page tables.
> - * These crashes may be intermittent.
> - */
> -#include <linux/linkage.h>
> -
> -#include <asm/assembler.h>
> -
> -#include "soc.h"
> -#include "iomap.h"
> -#include "prm2xxx.h"
> -#include "cm2xxx.h"
> -#include "sdrc.h"
> -
> - .text
> -
> - .align 3
> -ENTRY(omap242x_sram_ddr_init)
> - stmfd sp!, {r0 - r12, lr} @ save registers on stack
> -
> - mov r12, r2 @ capture CS1 vs CS0
> - mov r8, r3 @ capture force parameter
> -
> - /* frequency shift down */
> - ldr r2, omap242x_sdi_cm_clksel2_pll @ get address of dpllout reg
> - mov r3, #0x1 @ value for 1x operation
> - str r3, [r2] @ go to L1-freq operation
> -
> - /* voltage shift down */
> - mov r9, #0x1 @ set up for L1 voltage call
> - bl voltage_shift @ go drop voltage
> -
> - /* dll lock mode */
> - ldr r11, omap242x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
> - ldr r10, [r11] @ get current val
> - cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
> - addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
> - mvn r9, #0x4 @ mask to get clear bit2
> - and r10, r10, r9 @ clear bit2 for lock mode.
> - orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
> - orr r10, r10, #0x2 @ 90 degree phase for all below 133MHz
> - str r10, [r11] @ commit to DLLA_CTRL
> - bl i_dll_wait @ wait for dll to lock
> -
> - /* get dll value */
> - add r11, r11, #0x4 @ get addr of status reg
> - ldr r10, [r11] @ get locked value
> -
> - /* voltage shift up */
> - mov r9, #0x0 @ shift back to L0-voltage
> - bl voltage_shift @ go raise voltage
> -
> - /* frequency shift up */
> - mov r3, #0x2 @ value for 2x operation
> - str r3, [r2] @ go to L0-freq operation
> -
> - /* reset entry mode for dllctrl */
> - sub r11, r11, #0x4 @ move from status to ctrl
> - cmp r12, #0x1 @ normalize if cs1 based
> - subeq r11, r11, #0x8 @ possibly back to DLLA
> - cmp r8, #0x1 @ if forced unlock exit
> - orreq r1, r1, #0x4 @ make sure exit with unlocked value
> - str r1, [r11] @ restore DLLA_CTRL high value
> - add r11, r11, #0x8 @ move to DLLB_CTRL addr
> - str r1, [r11] @ set value DLLB_CTRL
> - bl i_dll_wait @ wait for possible lock
> -
> - /* set up for return, DDR should be good */
> - str r10, [r0] @ write dll_status and return counter
> - ldmfd sp!, {r0 - r12, pc} @ restore regs and return
> -
> - /* ensure the DLL has relocked */
> -i_dll_wait:
> - mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
> -i_dll_delay:
> - subs r4, r4, #0x1
> - bne i_dll_delay
> - ret lr
> -
> - /*
> - * shift up or down voltage, use R9 as input to tell level.
> - * wait for it to finish, use 32k sync counter, 1tick=31uS.
> - */
> -voltage_shift:
> - ldr r4, omap242x_sdi_prcm_voltctrl @ get addr of volt ctrl.
> - ldr r5, [r4] @ get value.
> - ldr r6, prcm_mask_val @ get value of mask
> - and r5, r5, r6 @ apply mask to clear bits
> - orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
> - str r5, [r4] @ set up for change.
> - mov r3, #0x4000 @ get val for force
> - orr r5, r5, r3 @ build value for force
> - str r5, [r4] @ Force transition to L1
> -
> - ldr r3, omap242x_sdi_timer_32ksynct_cr @ get addr of counter
> - ldr r5, [r3] @ get value
> - add r5, r5, #0x3 @ give it at most 93uS
> -volt_delay:
> - ldr r7, [r3] @ get timer value
> - cmp r5, r7 @ time up?
> - bhi volt_delay @ not yet->branch
> - ret lr @ back to caller.
> -
> -omap242x_sdi_cm_clksel2_pll:
> - .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
> -omap242x_sdi_sdrc_dlla_ctrl:
> - .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
> -omap242x_sdi_prcm_voltctrl:
> - .word OMAP2420_PRCM_VOLTCTRL
> -prcm_mask_val:
> - .word 0xFFFF3FFC
> -omap242x_sdi_timer_32ksynct_cr:
> - .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
> -ENTRY(omap242x_sram_ddr_init_sz)
> - .word . - omap242x_sram_ddr_init
> -
> -/*
> - * Reprograms memory timings.
> - * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
> - * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
> - */
> - .align 3
> -ENTRY(omap242x_sram_reprogram_sdrc)
> - stmfd sp!, {r0 - r10, lr} @ save registers on stack
> - mov r3, #0x0 @ clear for mrc call
> - mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
> - nop
> - nop
> - ldr r6, omap242x_srs_sdrc_rfr_ctrl @ get addr of refresh reg
> - ldr r5, [r6] @ get value
> - mov r5, r5, lsr #8 @ isolate rfr field and drop burst
> -
> - cmp r0, #0x1 @ going to half speed?
> - movne r9, #0x0 @ if up set flag up for pre up, hi volt
> -
> - blne voltage_shift_c @ adjust voltage
> -
> - cmp r0, #0x1 @ going to half speed (post branch link)
> - moveq r5, r5, lsr #1 @ divide by 2 if to half
> - movne r5, r5, lsl #1 @ mult by 2 if to full
> - mov r5, r5, lsl #8 @ put rfr field back into place
> - add r5, r5, #0x1 @ turn on burst of 1
> - ldr r4, omap242x_srs_cm_clksel2_pll @ get address of out reg
> - ldr r3, [r4] @ get curr value
> - orr r3, r3, #0x3
> - bic r3, r3, #0x3 @ clear lower bits
> - orr r3, r3, r0 @ new state value
> - str r3, [r4] @ set new state (pll/x, x=1 or 2)
> - nop
> - nop
> -
> - moveq r9, #0x1 @ if speed down, post down, drop volt
> - bleq voltage_shift_c
> -
> - mcr p15, 0, r3, c7, c10, 4 @ memory barrier
> - str r5, [r6] @ set new RFR_1 value
> - add r6, r6, #0x30 @ get RFR_2 addr
> - str r5, [r6] @ set RFR_2
> - nop
> - cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
> - bne freq_out @ leave if SDR, no DLL function
> -
> - /* With DDR, we need to take care of the DLL for the frequency change */
> - ldr r2, omap242x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
> - str r1, [r2] @ write out new SDRC_DLLA_CTRL
> - add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
> - str r1, [r2] @ commit to SDRC_DLLB_CTRL
> - mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
> -dll_wait:
> - subs r1, r1, #0x1
> - bne dll_wait
> -freq_out:
> - ldmfd sp!, {r0 - r10, pc} @ restore regs and return
> -
> - /*
> - * shift up or down voltage, use R9 as input to tell level.
> - * wait for it to finish, use 32k sync counter, 1tick=31uS.
> - */
> -voltage_shift_c:
> - ldr r10, omap242x_srs_prcm_voltctrl @ get addr of volt ctrl
> - ldr r8, [r10] @ get value
> - ldr r7, ddr_prcm_mask_val @ get value of mask
> - and r8, r8, r7 @ apply mask to clear bits
> - orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
> - str r8, [r10] @ set up for change.
> - mov r7, #0x4000 @ get val for force
> - orr r8, r8, r7 @ build value for force
> - str r8, [r10] @ Force transition to L1
> -
> - ldr r10, omap242x_srs_timer_32ksynct @ get addr of counter
> - ldr r8, [r10] @ get value
> - add r8, r8, #0x2 @ give it at most 62uS (min 31+)
> -volt_delay_c:
> - ldr r7, [r10] @ get timer value
> - cmp r8, r7 @ time up?
> - bhi volt_delay_c @ not yet->branch
> - ret lr @ back to caller
> -
> -omap242x_srs_cm_clksel2_pll:
> - .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
> -omap242x_srs_sdrc_dlla_ctrl:
> - .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
> -omap242x_srs_sdrc_rfr_ctrl:
> - .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
> -omap242x_srs_prcm_voltctrl:
> - .word OMAP2420_PRCM_VOLTCTRL
> -ddr_prcm_mask_val:
> - .word 0xFFFF3FFC
> -omap242x_srs_timer_32ksynct:
> - .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
> -
> -ENTRY(omap242x_sram_reprogram_sdrc_sz)
> - .word . - omap242x_sram_reprogram_sdrc
> -
> -/*
> - * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
> - */
> - .align 3
> -ENTRY(omap242x_sram_set_prcm)
> - stmfd sp!, {r0-r12, lr} @ regs to stack
> - adr r4, pbegin @ addr of preload start
> - adr r8, pend @ addr of preload end
> - mcrr p15, 1, r8, r4, c12 @ preload into icache
> -pbegin:
> - /* move into fast relock bypass */
> - ldr r8, omap242x_ssp_pll_ctl @ get addr
> - ldr r5, [r8] @ get val
> - mvn r6, #0x3 @ clear mask
> - and r5, r5, r6 @ clear field
> - orr r7, r5, #0x2 @ fast relock val
> - str r7, [r8] @ go to fast relock
> - ldr r4, omap242x_ssp_pll_stat @ addr of stat
> -block:
> - /* wait for bypass */
> - ldr r8, [r4] @ stat value
> - and r8, r8, #0x3 @ mask for stat
> - cmp r8, #0x1 @ there yet
> - bne block @ loop if not
> -
> - /* set new dpll dividers _after_ in bypass */
> - ldr r4, omap242x_ssp_pll_div @ get addr
> - str r0, [r4] @ set dpll ctrl val
> -
> - ldr r4, omap242x_ssp_set_config @ get addr
> - mov r8, #1 @ valid cfg msk
> - str r8, [r4] @ make dividers take
> -
> - mov r4, #100 @ dead spin a bit
> -wait_a_bit:
> - subs r4, r4, #1 @ dec loop
> - bne wait_a_bit @ delay done?
> -
> - /* check if staying in bypass */
> - cmp r2, #0x1 @ stay in bypass?
> - beq pend @ jump over dpll relock
> -
> - /* relock DPLL with new vals */
> - ldr r5, omap242x_ssp_pll_stat @ get addr
> - ldr r4, omap242x_ssp_pll_ctl @ get addr
> - orr r8, r7, #0x3 @ val for lock dpll
> - str r8, [r4] @ set val
> - mov r0, #1000 @ dead spin a bit
> -wait_more:
> - subs r0, r0, #1 @ dec loop
> - bne wait_more @ delay done?
> -wait_lock:
> - ldr r8, [r5] @ get lock val
> - and r8, r8, #3 @ isolate field
> - cmp r8, #2 @ locked?
> - bne wait_lock @ wait if not
> -pend:
> - /* update memory timings & briefly lock dll */
> - ldr r4, omap242x_ssp_sdrc_rfr @ get addr
> - str r1, [r4] @ update refresh timing
> - ldr r11, omap242x_ssp_dlla_ctrl @ get addr of DLLA ctrl
> - ldr r10, [r11] @ get current val
> - mvn r9, #0x4 @ mask to get clear bit2
> - and r10, r10, r9 @ clear bit2 for lock mode
> - orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
> - str r10, [r11] @ commit to DLLA_CTRL
> - add r11, r11, #0x8 @ move to dllb
> - str r10, [r11] @ hit DLLB also
> -
> - mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
> -wait_dll_lock:
> - subs r4, r4, #0x1
> - bne wait_dll_lock
> - nop
> - ldmfd sp!, {r0-r12, pc} @ restore regs and return
> -
> -omap242x_ssp_set_config:
> - .word OMAP2420_PRCM_CLKCFG_CTRL
> -omap242x_ssp_pll_ctl:
> - .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
> -omap242x_ssp_pll_stat:
> - .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST)
> -omap242x_ssp_pll_div:
> - .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
> -omap242x_ssp_sdrc_rfr:
> - .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
> -omap242x_ssp_dlla_ctrl:
> - .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
> -
> -ENTRY(omap242x_sram_set_prcm_sz)
> - .word . - omap242x_sram_set_prcm
> diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
> deleted file mode 100644
> index faf03b7f08f5..000000000000
> --- a/arch/arm/mach-omap2/sram243x.S
> +++ /dev/null
> @@ -1,317 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-or-later */
> -/*
> - * linux/arch/arm/mach-omap2/sram243x.S
> - *
> - * Omap2 specific functions that need to be run in internal SRAM
> - *
> - * (C) Copyright 2004
> - * Texas Instruments, <www.ti.com>
> - * Richard Woodruff <r-woodruff2@ti.com>
> - *
> - * Richard Woodruff notes that any changes to this code must be carefully
> - * audited and tested to ensure that they don't cause a TLB miss while
> - * the SDRAM is inaccessible. Such a situation will crash the system
> - * since it will cause the ARM MMU to attempt to walk the page tables.
> - * These crashes may be intermittent.
> - */
> -#include <linux/linkage.h>
> -
> -#include <asm/assembler.h>
> -
> -#include "soc.h"
> -#include "iomap.h"
> -#include "prm2xxx.h"
> -#include "cm2xxx.h"
> -#include "sdrc.h"
> -
> - .text
> -
> - .align 3
> -ENTRY(omap243x_sram_ddr_init)
> - stmfd sp!, {r0 - r12, lr} @ save registers on stack
> -
> - mov r12, r2 @ capture CS1 vs CS0
> - mov r8, r3 @ capture force parameter
> -
> - /* frequency shift down */
> - ldr r2, omap243x_sdi_cm_clksel2_pll @ get address of dpllout reg
> - mov r3, #0x1 @ value for 1x operation
> - str r3, [r2] @ go to L1-freq operation
> -
> - /* voltage shift down */
> - mov r9, #0x1 @ set up for L1 voltage call
> - bl voltage_shift @ go drop voltage
> -
> - /* dll lock mode */
> - ldr r11, omap243x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
> - ldr r10, [r11] @ get current val
> - cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
> - addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
> - mvn r9, #0x4 @ mask to get clear bit2
> - and r10, r10, r9 @ clear bit2 for lock mode.
> - orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
> - orr r10, r10, #0x2 @ 90 degree phase for all below 133MHz
> - str r10, [r11] @ commit to DLLA_CTRL
> - bl i_dll_wait @ wait for dll to lock
> -
> - /* get dll value */
> - add r11, r11, #0x4 @ get addr of status reg
> - ldr r10, [r11] @ get locked value
> -
> - /* voltage shift up */
> - mov r9, #0x0 @ shift back to L0-voltage
> - bl voltage_shift @ go raise voltage
> -
> - /* frequency shift up */
> - mov r3, #0x2 @ value for 2x operation
> - str r3, [r2] @ go to L0-freq operation
> -
> - /* reset entry mode for dllctrl */
> - sub r11, r11, #0x4 @ move from status to ctrl
> - cmp r12, #0x1 @ normalize if cs1 based
> - subeq r11, r11, #0x8 @ possibly back to DLLA
> - cmp r8, #0x1 @ if forced unlock exit
> - orreq r1, r1, #0x4 @ make sure exit with unlocked value
> - str r1, [r11] @ restore DLLA_CTRL high value
> - add r11, r11, #0x8 @ move to DLLB_CTRL addr
> - str r1, [r11] @ set value DLLB_CTRL
> - bl i_dll_wait @ wait for possible lock
> -
> - /* set up for return, DDR should be good */
> - str r10, [r0] @ write dll_status and return counter
> - ldmfd sp!, {r0 - r12, pc} @ restore regs and return
> -
> - /* ensure the DLL has relocked */
> -i_dll_wait:
> - mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
> -i_dll_delay:
> - subs r4, r4, #0x1
> - bne i_dll_delay
> - ret lr
> -
> - /*
> - * shift up or down voltage, use R9 as input to tell level.
> - * wait for it to finish, use 32k sync counter, 1tick=31uS.
> - */
> -voltage_shift:
> - ldr r4, omap243x_sdi_prcm_voltctrl @ get addr of volt ctrl.
> - ldr r5, [r4] @ get value.
> - ldr r6, prcm_mask_val @ get value of mask
> - and r5, r5, r6 @ apply mask to clear bits
> - orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
> - str r5, [r4] @ set up for change.
> - mov r3, #0x4000 @ get val for force
> - orr r5, r5, r3 @ build value for force
> - str r5, [r4] @ Force transition to L1
> -
> - ldr r3, omap243x_sdi_timer_32ksynct_cr @ get addr of counter
> - ldr r5, [r3] @ get value
> - add r5, r5, #0x3 @ give it at most 93uS
> -volt_delay:
> - ldr r7, [r3] @ get timer value
> - cmp r5, r7 @ time up?
> - bhi volt_delay @ not yet->branch
> - ret lr @ back to caller.
> -
> -omap243x_sdi_cm_clksel2_pll:
> - .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
> -omap243x_sdi_sdrc_dlla_ctrl:
> - .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
> -omap243x_sdi_prcm_voltctrl:
> - .word OMAP2430_PRCM_VOLTCTRL
> -prcm_mask_val:
> - .word 0xFFFF3FFC
> -omap243x_sdi_timer_32ksynct_cr:
> - .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
> -ENTRY(omap243x_sram_ddr_init_sz)
> - .word . - omap243x_sram_ddr_init
> -
> -/*
> - * Reprograms memory timings.
> - * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
> - * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
> - */
> - .align 3
> -ENTRY(omap243x_sram_reprogram_sdrc)
> - stmfd sp!, {r0 - r10, lr} @ save registers on stack
> - mov r3, #0x0 @ clear for mrc call
> - mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
> - nop
> - nop
> - ldr r6, omap243x_srs_sdrc_rfr_ctrl @ get addr of refresh reg
> - ldr r5, [r6] @ get value
> - mov r5, r5, lsr #8 @ isolate rfr field and drop burst
> -
> - cmp r0, #0x1 @ going to half speed?
> - movne r9, #0x0 @ if up set flag up for pre up, hi volt
> -
> - blne voltage_shift_c @ adjust voltage
> -
> - cmp r0, #0x1 @ going to half speed (post branch link)
> - moveq r5, r5, lsr #1 @ divide by 2 if to half
> - movne r5, r5, lsl #1 @ mult by 2 if to full
> - mov r5, r5, lsl #8 @ put rfr field back into place
> - add r5, r5, #0x1 @ turn on burst of 1
> - ldr r4, omap243x_srs_cm_clksel2_pll @ get address of out reg
> - ldr r3, [r4] @ get curr value
> - orr r3, r3, #0x3
> - bic r3, r3, #0x3 @ clear lower bits
> - orr r3, r3, r0 @ new state value
> - str r3, [r4] @ set new state (pll/x, x=1 or 2)
> - nop
> - nop
> -
> - moveq r9, #0x1 @ if speed down, post down, drop volt
> - bleq voltage_shift_c
> -
> - mcr p15, 0, r3, c7, c10, 4 @ memory barrier
> - str r5, [r6] @ set new RFR_1 value
> - add r6, r6, #0x30 @ get RFR_2 addr
> - str r5, [r6] @ set RFR_2
> - nop
> - cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
> - bne freq_out @ leave if SDR, no DLL function
> -
> - /* With DDR, we need to take care of the DLL for the frequency change */
> - ldr r2, omap243x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
> - str r1, [r2] @ write out new SDRC_DLLA_CTRL
> - add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
> - str r1, [r2] @ commit to SDRC_DLLB_CTRL
> - mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
> -dll_wait:
> - subs r1, r1, #0x1
> - bne dll_wait
> -freq_out:
> - ldmfd sp!, {r0 - r10, pc} @ restore regs and return
> -
> - /*
> - * shift up or down voltage, use R9 as input to tell level.
> - * wait for it to finish, use 32k sync counter, 1tick=31uS.
> - */
> -voltage_shift_c:
> - ldr r10, omap243x_srs_prcm_voltctrl @ get addr of volt ctrl
> - ldr r8, [r10] @ get value
> - ldr r7, ddr_prcm_mask_val @ get value of mask
> - and r8, r8, r7 @ apply mask to clear bits
> - orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
> - str r8, [r10] @ set up for change.
> - mov r7, #0x4000 @ get val for force
> - orr r8, r8, r7 @ build value for force
> - str r8, [r10] @ Force transition to L1
> -
> - ldr r10, omap243x_srs_timer_32ksynct @ get addr of counter
> - ldr r8, [r10] @ get value
> - add r8, r8, #0x2 @ give it at most 62uS (min 31+)
> -volt_delay_c:
> - ldr r7, [r10] @ get timer value
> - cmp r8, r7 @ time up?
> - bhi volt_delay_c @ not yet->branch
> - ret lr @ back to caller
> -
> -omap243x_srs_cm_clksel2_pll:
> - .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
> -omap243x_srs_sdrc_dlla_ctrl:
> - .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
> -omap243x_srs_sdrc_rfr_ctrl:
> - .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
> -omap243x_srs_prcm_voltctrl:
> - .word OMAP2430_PRCM_VOLTCTRL
> -ddr_prcm_mask_val:
> - .word 0xFFFF3FFC
> -omap243x_srs_timer_32ksynct:
> - .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
> -
> -ENTRY(omap243x_sram_reprogram_sdrc_sz)
> - .word . - omap243x_sram_reprogram_sdrc
> -
> -/*
> - * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
> - */
> - .align 3
> -ENTRY(omap243x_sram_set_prcm)
> - stmfd sp!, {r0-r12, lr} @ regs to stack
> - adr r4, pbegin @ addr of preload start
> - adr r8, pend @ addr of preload end
> - mcrr p15, 1, r8, r4, c12 @ preload into icache
> -pbegin:
> - /* move into fast relock bypass */
> - ldr r8, omap243x_ssp_pll_ctl @ get addr
> - ldr r5, [r8] @ get val
> - mvn r6, #0x3 @ clear mask
> - and r5, r5, r6 @ clear field
> - orr r7, r5, #0x2 @ fast relock val
> - str r7, [r8] @ go to fast relock
> - ldr r4, omap243x_ssp_pll_stat @ addr of stat
> -block:
> - /* wait for bypass */
> - ldr r8, [r4] @ stat value
> - and r8, r8, #0x3 @ mask for stat
> - cmp r8, #0x1 @ there yet
> - bne block @ loop if not
> -
> - /* set new dpll dividers _after_ in bypass */
> - ldr r4, omap243x_ssp_pll_div @ get addr
> - str r0, [r4] @ set dpll ctrl val
> -
> - ldr r4, omap243x_ssp_set_config @ get addr
> - mov r8, #1 @ valid cfg msk
> - str r8, [r4] @ make dividers take
> -
> - mov r4, #100 @ dead spin a bit
> -wait_a_bit:
> - subs r4, r4, #1 @ dec loop
> - bne wait_a_bit @ delay done?
> -
> - /* check if staying in bypass */
> - cmp r2, #0x1 @ stay in bypass?
> - beq pend @ jump over dpll relock
> -
> - /* relock DPLL with new vals */
> - ldr r5, omap243x_ssp_pll_stat @ get addr
> - ldr r4, omap243x_ssp_pll_ctl @ get addr
> - orr r8, r7, #0x3 @ val for lock dpll
> - str r8, [r4] @ set val
> - mov r0, #1000 @ dead spin a bit
> -wait_more:
> - subs r0, r0, #1 @ dec loop
> - bne wait_more @ delay done?
> -wait_lock:
> - ldr r8, [r5] @ get lock val
> - and r8, r8, #3 @ isolate field
> - cmp r8, #2 @ locked?
> - bne wait_lock @ wait if not
> -pend:
> - /* update memory timings & briefly lock dll */
> - ldr r4, omap243x_ssp_sdrc_rfr @ get addr
> - str r1, [r4] @ update refresh timing
> - ldr r11, omap243x_ssp_dlla_ctrl @ get addr of DLLA ctrl
> - ldr r10, [r11] @ get current val
> - mvn r9, #0x4 @ mask to get clear bit2
> - and r10, r10, r9 @ clear bit2 for lock mode
> - orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
> - str r10, [r11] @ commit to DLLA_CTRL
> - add r11, r11, #0x8 @ move to dllb
> - str r10, [r11] @ hit DLLB also
> -
> - mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
> -wait_dll_lock:
> - subs r4, r4, #0x1
> - bne wait_dll_lock
> - nop
> - ldmfd sp!, {r0-r12, pc} @ restore regs and return
> -
> -omap243x_ssp_set_config:
> - .word OMAP2430_PRCM_CLKCFG_CTRL
> -omap243x_ssp_pll_ctl:
> - .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
> -omap243x_ssp_pll_stat:
> - .word OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST)
> -omap243x_ssp_pll_div:
> - .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
> -omap243x_ssp_sdrc_rfr:
> - .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
> -omap243x_ssp_dlla_ctrl:
> - .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
> -
> -ENTRY(omap243x_sram_set_prcm_sz)
> - .word . - omap243x_sram_set_prcm
> diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
> deleted file mode 100644
> index b46c254c2bc4..000000000000
> --- a/arch/arm/mach-omap2/usb-tusb6010.c
> +++ /dev/null
> @@ -1,217 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * linux/arch/arm/mach-omap2/usb-tusb6010.c
> - *
> - * Copyright (C) 2006 Nokia Corporation
> - */
> -
> -#include <linux/err.h>
> -#include <linux/string.h>
> -#include <linux/types.h>
> -#include <linux/errno.h>
> -#include <linux/delay.h>
> -#include <linux/platform_device.h>
> -#include <linux/export.h>
> -#include <linux/platform_data/usb-omap.h>
> -
> -#include <linux/usb/musb.h>
> -
> -#include "usb-tusb6010.h"
> -#include "gpmc.h"
> -
> -static u8 async_cs, sync_cs;
> -static unsigned refclk_psec;
> -
> -static struct gpmc_settings tusb_async = {
> - .wait_on_read = true,
> - .wait_on_write = true,
> - .device_width = GPMC_DEVWIDTH_16BIT,
> - .mux_add_data = GPMC_MUX_AD,
> -};
> -
> -static struct gpmc_settings tusb_sync = {
> - .burst_read = true,
> - .burst_write = true,
> - .sync_read = true,
> - .sync_write = true,
> - .wait_on_read = true,
> - .wait_on_write = true,
> - .burst_len = GPMC_BURST_16,
> - .device_width = GPMC_DEVWIDTH_16BIT,
> - .mux_add_data = GPMC_MUX_AD,
> -};
> -
> -/* NOTE: timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */
> -
> -static int tusb_set_async_mode(unsigned sysclk_ps)
> -{
> - struct gpmc_device_timings dev_t;
> - struct gpmc_timings t;
> - unsigned t_acsnh_advnh = sysclk_ps + 3000;
> -
> - memset(&dev_t, 0, sizeof(dev_t));
> -
> - dev_t.t_ceasu = 8 * 1000;
> - dev_t.t_avdasu = t_acsnh_advnh - 7000;
> - dev_t.t_ce_avd = 1000;
> - dev_t.t_avdp_r = t_acsnh_advnh;
> - dev_t.t_oeasu = t_acsnh_advnh + 1000;
> - dev_t.t_oe = 300;
> - dev_t.t_cez_r = 7000;
> - dev_t.t_cez_w = dev_t.t_cez_r;
> - dev_t.t_avdp_w = t_acsnh_advnh;
> - dev_t.t_weasu = t_acsnh_advnh + 1000;
> - dev_t.t_wpl = 300;
> - dev_t.cyc_aavdh_we = 1;
> -
> - gpmc_calc_timings(&t, &tusb_async, &dev_t);
> -
> - return gpmc_cs_set_timings(async_cs, &t, &tusb_async);
> -}
> -
> -static int tusb_set_sync_mode(unsigned sysclk_ps)
> -{
> - struct gpmc_device_timings dev_t;
> - struct gpmc_timings t;
> - unsigned t_scsnh_advnh = sysclk_ps + 3000;
> -
> - memset(&dev_t, 0, sizeof(dev_t));
> -
> - dev_t.clk = 11100;
> - dev_t.t_bacc = 1000;
> - dev_t.t_ces = 1000;
> - dev_t.t_ceasu = 8 * 1000;
> - dev_t.t_avdasu = t_scsnh_advnh - 7000;
> - dev_t.t_ce_avd = 1000;
> - dev_t.t_avdp_r = t_scsnh_advnh;
> - dev_t.cyc_aavdh_oe = 3;
> - dev_t.cyc_oe = 5;
> - dev_t.t_ce_rdyz = 7000;
> - dev_t.t_avdp_w = t_scsnh_advnh;
> - dev_t.cyc_aavdh_we = 3;
> - dev_t.cyc_wpl = 6;
> -
> - gpmc_calc_timings(&t, &tusb_sync, &dev_t);
> -
> - return gpmc_cs_set_timings(sync_cs, &t, &tusb_sync);
> -}
> -
> -/* tusb driver calls this when it changes the chip's clocking */
> -static int tusb6010_platform_retime(unsigned is_refclk)
> -{
> - static const char error[] =
> - KERN_ERR "tusb6010 %s retime error %d\n";
> -
> - unsigned sysclk_ps;
> - int status;
> -
> - if (!refclk_psec)
> - return -ENODEV;
> -
> - sysclk_ps = is_refclk ? refclk_psec : TUSB6010_OSCCLK_60;
> -
> - status = tusb_set_async_mode(sysclk_ps);
> - if (status < 0) {
> - printk(error, "async", status);
> - goto done;
> - }
> - status = tusb_set_sync_mode(sysclk_ps);
> - if (status < 0)
> - printk(error, "sync", status);
> -done:
> - return status;
> -}
> -
> -static struct resource tusb_resources[] = {
> - /* Order is significant! The start/end fields
> - * are updated during setup..
> - */
> - { /* Asynchronous access */
> - .flags = IORESOURCE_MEM,
> - },
> - { /* Synchronous access */
> - .flags = IORESOURCE_MEM,
> - },
> -};
> -
> -static u64 tusb_dmamask = ~(u32)0;
> -
> -static struct platform_device tusb_device = {
> - .name = "musb-tusb",
> - .id = -1,
> - .dev = {
> - .dma_mask = &tusb_dmamask,
> - .coherent_dma_mask = 0xffffffff,
> - },
> - .num_resources = ARRAY_SIZE(tusb_resources),
> - .resource = tusb_resources,
> -};
> -
> -
> -/* this may be called only from board-*.c setup code */
> -int __init tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
> - unsigned int ps_refclk, unsigned int waitpin,
> - unsigned int async, unsigned int sync,
> - unsigned int dmachan)
> -{
> - int status;
> - static char error[] __initdata =
> - KERN_ERR "tusb6010 init error %d, %d\n";
> -
> - /* ASYNC region, primarily for PIO */
> - status = gpmc_cs_request(async, SZ_16M, (unsigned long *)
> - &tusb_resources[0].start);
> - if (status < 0) {
> - printk(error, 1, status);
> - return status;
> - }
> - tusb_resources[0].end = tusb_resources[0].start + 0x9ff;
> - tusb_async.wait_pin = waitpin;
> - async_cs = async;
> -
> - status = gpmc_cs_program_settings(async_cs, &tusb_async);
> - if (status < 0)
> - return status;
> -
> - /* SYNC region, primarily for DMA */
> - status = gpmc_cs_request(sync, SZ_16M, (unsigned long *)
> - &tusb_resources[1].start);
> - if (status < 0) {
> - printk(error, 2, status);
> - return status;
> - }
> - tusb_resources[1].end = tusb_resources[1].start + 0x9ff;
> - tusb_sync.wait_pin = waitpin;
> - sync_cs = sync;
> -
> - status = gpmc_cs_program_settings(sync_cs, &tusb_sync);
> - if (status < 0)
> - return status;
> -
> - /* set up memory timings ... can speed them up later */
> - if (!ps_refclk) {
> - printk(error, 4, status);
> - return -ENODEV;
> - }
> - refclk_psec = ps_refclk;
> - status = tusb6010_platform_retime(1);
> - if (status < 0) {
> - printk(error, 5, status);
> - return status;
> - }
> -
> - /* finish device setup ... */
> - if (!data) {
> - printk(error, 6, status);
> - return -ENODEV;
> - }
> - tusb_device.dev.platform_data = data;
> -
> - /* so far so good ... register the device */
> - status = platform_device_register(&tusb_device);
> - if (status < 0) {
> - printk(error, 7, status);
> - return status;
> - }
> - return 0;
> -}
> diff --git a/arch/arm/mach-omap2/usb-tusb6010.h b/arch/arm/mach-omap2/usb-tusb6010.h
> deleted file mode 100644
> index d210ff6238c2..000000000000
> --- a/arch/arm/mach-omap2/usb-tusb6010.h
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -
> -#ifndef __USB_TUSB6010_H
> -#define __USB_TUSB6010_H
> -
> -extern int __init tusb6010_setup_interface(
> - struct musb_hdrc_platform_data *data,
> - unsigned int ps_refclk, unsigned int waitpin,
> - unsigned int async_cs, unsigned int sync_cs,
> - unsigned int dmachan);
> -
> -#endif /* __USB_TUSB6010_H */
> diff --git a/arch/arm/mach-omap2/voltagedomains2xxx_data.c b/arch/arm/mach-omap2/voltagedomains2xxx_data.c
> deleted file mode 100644
> index 9bc116fe3ba9..000000000000
> --- a/arch/arm/mach-omap2/voltagedomains2xxx_data.c
> +++ /dev/null
> @@ -1,29 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * OMAP3 voltage domain data
> - *
> - * Copyright (C) 2011 Texas Instruments, Inc.
> - */
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -
> -#include "voltage.h"
> -
> -static struct voltagedomain omap2_voltdm_core = {
> - .name = "core",
> -};
> -
> -static struct voltagedomain omap2_voltdm_wkup = {
> - .name = "wakeup",
> -};
> -
> -static struct voltagedomain *voltagedomains_omap2[] __initdata = {
> - &omap2_voltdm_core,
> - &omap2_voltdm_wkup,
> - NULL,
> -};
> -
> -void __init omap2xxx_voltagedomains_init(void)
> -{
> - voltdm_init(voltagedomains_omap2);
> -}
> diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
> index 0189dfdcbbe1..a383ff8f446c 100644
> --- a/drivers/crypto/Kconfig
> +++ b/drivers/crypto/Kconfig
> @@ -337,7 +337,7 @@ config CRYPTO_DEV_OMAP_SHAM
>
> config CRYPTO_DEV_OMAP_AES
> tristate "Support for OMAP AES hw engine"
> - depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP2PLUS
> + depends on ARCH_OMAP3 || ARCH_OMAP2PLUS
> select CRYPTO_AES
> select CRYPTO_SKCIPHER
> select CRYPTO_ENGINE
> diff --git a/drivers/media/platform/ti/omap/Kconfig b/drivers/media/platform/ti/omap/Kconfig
> index a9dbe1097775..c41812b324ad 100644
> --- a/drivers/media/platform/ti/omap/Kconfig
> +++ b/drivers/media/platform/ti/omap/Kconfig
> @@ -9,9 +9,9 @@ config VIDEO_OMAP2_VOUT
> depends on V4L_PLATFORM_DRIVERS
> depends on MMU
> depends on FB_OMAP2 || (COMPILE_TEST && FB_OMAP2=n)
> - depends on ARCH_OMAP2 || ARCH_OMAP3 || COMPILE_TEST
> + depends on ARCH_OMAP3 || COMPILE_TEST
> depends on VIDEO_DEV
> select VIDEOBUF2_DMA_CONTIG
> - select OMAP2_VRFB if ARCH_OMAP2 || ARCH_OMAP3
> + select OMAP2_VRFB if ARCH_OMAP3
> help
> V4L2 Display driver support for OMAP2/3 based boards.
> diff --git a/drivers/mtd/nand/onenand/Kconfig b/drivers/mtd/nand/onenand/Kconfig
> index 7d57836bf32f..8a362fd5bfc4 100644
> --- a/drivers/mtd/nand/onenand/Kconfig
> +++ b/drivers/mtd/nand/onenand/Kconfig
> @@ -23,8 +23,8 @@ config MTD_ONENAND_GENERIC
> Support for OneNAND flash via platform device driver.
>
> config MTD_ONENAND_OMAP2
> - tristate "OneNAND on OMAP2/OMAP3 support"
> - depends on ARCH_OMAP2 || ARCH_OMAP3 || (COMPILE_TEST && ARM)
> + tristate "OneNAND on OMAP3 support"
> + depends on ARCH_OMAP3 || (COMPILE_TEST && ARM)
> depends on OF
> depends on OMAP_GPMC
> help
> diff --git a/drivers/video/fbdev/omap2/omapfb/Kconfig b/drivers/video/fbdev/omap2/omapfb/Kconfig
> index 2d20e79adefc..d8227f4326bd 100644
> --- a/drivers/video/fbdev/omap2/omapfb/Kconfig
> +++ b/drivers/video/fbdev/omap2/omapfb/Kconfig
> @@ -8,7 +8,7 @@ menuconfig FB_OMAP2
> depends on DRM_OMAP = n
> depends on GPIOLIB
> select FB_OMAP2_DSS
> - select OMAP2_VRFB if ARCH_OMAP2 || ARCH_OMAP3
> + select OMAP2_VRFB if ARCH_OMAP3
> select FB_IOMEM_HELPERS
> help
> Frame buffer driver for OMAP2+ based boards.
> diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
> index 54a3fa370004..ca151152da19 100644
> --- a/include/linux/clk/ti.h
> +++ b/include/linux/clk/ti.h
> @@ -265,12 +265,6 @@ int omap2_clk_disable_autoidle_all(void);
> int omap2_clk_enable_autoidle_all(void);
> int omap2_clk_allow_idle(struct clk *clk);
> int omap2_clk_deny_idle(struct clk *clk);
> -unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
> - unsigned long parent_rate);
> -int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
> - unsigned long parent_rate);
> -void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
> -void omap2xxx_clkt_vps_init(void);
> unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
>
> void ti_dt_clk_init_retry_clks(void);
> @@ -322,8 +316,6 @@ void omap3_noncore_dpll_restore_context(struct clk_hw *hw);
> int omap3_core_dpll_save_context(struct clk_hw *hw);
> void omap3_core_dpll_restore_context(struct clk_hw *hw);
>
> -extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
> -
> #ifdef CONFIG_ATAGS
> int omap3430_clk_legacy_init(void);
> int omap3430es1_clk_legacy_init(void);
--
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstr. 146, 90461 Nürnberg, Germany, www.suse.com
GF: Jochen Jaser, Andrew McDonald, (HRB 36809, AG Nürnberg)
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH 07/13] ARM: imx: remove i.MX31 SoC support
2026-09-08 15:27 [PATCH 00/13] ARM: deprecated platform removal Arnd Bergmann
` (5 preceding siblings ...)
2026-09-08 15:27 ` [PATCH 06/13] ARM: omap2: remove omap24xx support Arnd Bergmann
@ 2026-09-08 15:27 ` Arnd Bergmann
2026-09-09 8:24 ` Vladimir Zapolskiy
` (2 more replies)
2026-09-08 15:27 ` [PATCH 08/13] ARM: imx: remove nommu support Arnd Bergmann
` (6 subsequent siblings)
13 siblings, 3 replies; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 15:27 UTC (permalink / raw)
To: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski
From: Arnd Bergmann <arnd@arndb.de>
The Freescale i.MX31 was an early SoC based on the ARM1136r0 CPU core. It
was used in the Bug Labs modular computer but ultimately much less
popular than most other i.MX SoCs.
As the ARM1136r0 support is causing a lot of extra maintenance effort
to keep alive and there are no known users, remove i.MX31 in order to
allow removing support for that CPU core altogether.
The related i.MX35 is based on a slightly newer ARM1136r1 CPU core that
does not have this problem, so there is no reason to remove that.
Cc: Russell King <linux@armlinux.org.uk>
Cc: Frank Li <Frank.Li@nxp.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: imx@lists.linux.dev
Cc: devicetree@vger.kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/Kconfig.debug | 9 -
arch/arm/boot/dts/nxp/imx/Makefile | 3 -
arch/arm/boot/dts/nxp/imx/imx31-bug.dts | 22 --
arch/arm/boot/dts/nxp/imx/imx31-lite.dts | 178 -----------
arch/arm/boot/dts/nxp/imx/imx31.dtsi | 371 -----------------------
arch/arm/configs/imx_v6_v7_defconfig | 1 -
arch/arm/mach-imx/Kconfig | 11 -
arch/arm/mach-imx/Makefile | 1 -
arch/arm/mach-imx/cpu-imx31.c | 72 -----
arch/arm/mach-imx/mach-imx31.c | 18 --
arch/arm/mach-imx/mm-imx3.c | 44 ---
11 files changed, 730 deletions(-)
delete mode 100644 arch/arm/boot/dts/nxp/imx/imx31-bug.dts
delete mode 100644 arch/arm/boot/dts/nxp/imx/imx31-lite.dts
delete mode 100644 arch/arm/boot/dts/nxp/imx/imx31.dtsi
delete mode 100644 arch/arm/mach-imx/cpu-imx31.c
delete mode 100644 arch/arm/mach-imx/mach-imx31.c
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index e2fc89055463..52387fe2a057 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -424,13 +424,6 @@ choice
Say Y here if you want kernel low-level debugging support
on i.MX28.
- config DEBUG_IMX31_UART
- bool "i.MX31 Debug UART"
- depends on SOC_IMX31
- help
- Say Y here if you want kernel low-level debugging support
- on i.MX31.
-
config DEBUG_IMX35_UART
bool "i.MX35 Debug UART"
depends on SOC_IMX35
@@ -1411,7 +1404,6 @@ config DEBUG_IMX_UART_PORT
depends on DEBUG_IMX1_UART || \
DEBUG_IMX25_UART || \
DEBUG_IMX27_UART || \
- DEBUG_IMX31_UART || \
DEBUG_IMX35_UART || \
DEBUG_IMX50_UART || \
DEBUG_IMX51_UART || \
@@ -1468,7 +1460,6 @@ config DEBUG_LL_INCLUDE
default "debug/imx.S" if DEBUG_IMX1_UART || \
DEBUG_IMX25_UART || \
DEBUG_IMX27_UART || \
- DEBUG_IMX31_UART || \
DEBUG_IMX35_UART || \
DEBUG_IMX50_UART || \
DEBUG_IMX51_UART || \
diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
index 1a2539fa19b4..e0747cb6e772 100644
--- a/arch/arm/boot/dts/nxp/imx/Makefile
+++ b/arch/arm/boot/dts/nxp/imx/Makefile
@@ -16,9 +16,6 @@ dtb-$(CONFIG_SOC_IMX27) += \
imx27-pdk.dtb \
imx27-phytec-phycore-rdk.dtb \
imx27-phytec-phycard-s-rdk.dtb
-dtb-$(CONFIG_SOC_IMX31) += \
- imx31-bug.dtb \
- imx31-lite.dtb
dtb-$(CONFIG_SOC_IMX35) += \
imx35-eukrea-mbimxsd35-baseboard.dtb \
imx35-pdk.dtb
diff --git a/arch/arm/boot/dts/nxp/imx/imx31-bug.dts b/arch/arm/boot/dts/nxp/imx/imx31-bug.dts
deleted file mode 100644
index d87eee3f9b3c..000000000000
--- a/arch/arm/boot/dts/nxp/imx/imx31-bug.dts
+++ /dev/null
@@ -1,22 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
- */
-
-/dts-v1/;
-#include "imx31.dtsi"
-
-/ {
- model = "Buglabs i.MX31 Bug 1.x";
- compatible = "buglabs,imx31-bug", "fsl,imx31";
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x8000000>; /* 128M */
- };
-};
-
-&uart5 {
- uart-has-rtscts;
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/nxp/imx/imx31-lite.dts b/arch/arm/boot/dts/nxp/imx/imx31-lite.dts
deleted file mode 100644
index 630f8fa69ba8..000000000000
--- a/arch/arm/boot/dts/nxp/imx/imx31-lite.dts
+++ /dev/null
@@ -1,178 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-//
-// Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
-
-/dts-v1/;
-
-#include "imx31.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- model = "LogicPD i.MX31 Lite";
- compatible = "logicpd,imx31-lite", "fsl,imx31";
-
- chosen {
- stdout-path = &uart1;
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x8000000>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led0 {
- gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
- };
-
- led1 {
- gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&ata {
- status = "okay";
-};
-
-&nfc {
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- nand-on-flash-bbt;
- status = "okay";
-};
-
-&sdhci1 {
- bus-width = <4>;
- cd-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
- wp-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&spi2 {
- status = "okay";
-
- pmic@0 {
- compatible = "fsl,mc13783";
- reg = <0>;
- spi-cs-high;
- spi-max-frequency = <1000000>;
- interrupt-parent = <&gpio1>;
- interrupts = <3 IRQ_TYPE_EDGE_RISING>;
-
- fsl,mc13xxx-uses-adc;
- fsl,mc13xxx-uses-rtc;
-
- regulators {
- sw1a { /* QVCC */
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- sw1b { /* QVCC */
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- sw2a { /* 1.8V_DDR, NVCC2, NVCC21 and NVCC22 */
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- sw2b { /* NVCC10 */
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- violo { /* NVCC1 and NVCC7 */
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- viohi { /* VIOHI */
- regulator-min-microvolt = <2775000>;
- regulator-max-microvolt = <2775000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vaudio { /* VAUDIO */
- regulator-min-microvolt = <2775000>;
- regulator-max-microvolt = <2775000>;
- };
-
- vcam { /* NVCC4 */
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- vgen { /* NVCC5 / NVCC8 and NVCC6 / NVCC9 */
- regulator-min-microvolt = <2775000>;
- regulator-max-microvolt = <2775000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vmmc2 { /* NVCC3 */
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
- };
- };
- };
-};
-
-&uart1 {
- uart-has-rtscts;
- status = "okay";
-};
-
-/* Routed to the extension board */
-&uart2 {
- uart-has-rtscts;
- status = "okay";
-};
-
-/* Routed to the extension board */
-&uart3 {
- uart-has-rtscts;
- status = "okay";
-};
-
-&weim {
- status = "okay";
-
- flash@0,0 {
- compatible = "cfi-flash";
- reg = <0 0x0 0x200000>;
- bank-width = <2>;
- linux,mtd-name = "physmap-flash.0";
- fsl,weim-cs-timing = <0x0000cf03 0xa0330d01 0x00220800>;
- };
-
- ethernet@4,0 {
- compatible = "smsc,lan9117", "smsc,lan9115";
- reg = <4 0x0 0x100>;
- interrupt-parent = <&gpio1>;
- interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
- phy-mode = "mii";
- reg-io-width = <2>;
- smsc,irq-push-pull;
- fsl,weim-cs-timing = <0x00008701 0x04000541 0x00010000>;
- };
-};
diff --git a/arch/arm/boot/dts/nxp/imx/imx31.dtsi b/arch/arm/boot/dts/nxp/imx/imx31.dtsi
deleted file mode 100644
index c58f855ea851..000000000000
--- a/arch/arm/boot/dts/nxp/imx/imx31.dtsi
+++ /dev/null
@@ -1,371 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-//
-// Copyright 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
-// Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- /*
- * The decompressor and also some bootloaders rely on a
- * pre-existing /chosen node to be available to insert the
- * command line and merge other ATAGS info.
- */
- chosen {};
-
- aliases {
- gpio0 = &gpio1;
- gpio1 = &gpio2;
- gpio2 = &gpio3;
- i2c0 = &i2c1;
- i2c1 = &i2c2;
- i2c2 = &i2c3;
- serial0 = &uart1;
- serial1 = &uart2;
- serial2 = &uart3;
- serial3 = &uart4;
- serial4 = &uart5;
- spi0 = &spi1;
- spi1 = &spi2;
- spi2 = &spi3;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- compatible = "arm,arm1136jf-s";
- device_type = "cpu";
- reg = <0>;
- };
- };
-
- avic: interrupt-controller@68000000 {
- compatible = "fsl,imx31-avic", "fsl,avic";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x68000000 0x100000>;
- };
-
- soc: soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&avic>;
- ranges;
-
- iram: sram@1fffc000 {
- compatible = "mmio-sram";
- reg = <0x1fffc000 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1fffc000 0x4000>;
- };
-
- aips1: bus@43f00000 { /* AIPS1 */
- compatible = "fsl,aips-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x43f00000 0x100000>;
- ranges;
-
- i2c1: i2c@43f80000 {
- compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
- reg = <0x43f80000 0x4000>;
- interrupts = <10>;
- clocks = <&clks 33>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@43f84000 {
- compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
- reg = <0x43f84000 0x4000>;
- interrupts = <3>;
- clocks = <&clks 35>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- ata: ata@43f8c000 {
- compatible = "fsl,imx31-pata", "fsl,imx27-pata";
- reg = <0x43f8c000 0x4000>;
- interrupts = <15>;
- clocks = <&clks 26>;
- status = "disabled";
- };
-
- uart1: serial@43f90000 {
- compatible = "fsl,imx31-uart", "fsl,imx21-uart";
- reg = <0x43f90000 0x4000>;
- interrupts = <45>;
- clocks = <&clks 10>, <&clks 30>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- uart2: serial@43f94000 {
- compatible = "fsl,imx31-uart", "fsl,imx21-uart";
- reg = <0x43f94000 0x4000>;
- interrupts = <32>;
- clocks = <&clks 10>, <&clks 31>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- i2c2: i2c@43f98000 {
- compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
- reg = <0x43f98000 0x4000>;
- interrupts = <4>;
- clocks = <&clks 34>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi1: spi@43fa4000 {
- compatible = "fsl,imx31-cspi";
- reg = <0x43fa4000 0x4000>;
- interrupts = <14>;
- clocks = <&clks 10>, <&clks 53>;
- clock-names = "ipg", "per";
- dmas = <&sdma 8 8 0>, <&sdma 9 8 0>;
- dma-names = "rx", "tx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- kpp: kpp@43fa8000 {
- compatible = "fsl,imx31-kpp", "fsl,imx21-kpp";
- reg = <0x43fa8000 0x4000>;
- interrupts = <24>;
- clocks = <&clks 46>;
- status = "disabled";
- };
-
- uart4: serial@43fb0000 {
- compatible = "fsl,imx31-uart", "fsl,imx21-uart";
- reg = <0x43fb0000 0x4000>;
- clocks = <&clks 10>, <&clks 49>;
- clock-names = "ipg", "per";
- interrupts = <46>;
- status = "disabled";
- };
-
- uart5: serial@43fb4000 {
- compatible = "fsl,imx31-uart", "fsl,imx21-uart";
- reg = <0x43fb4000 0x4000>;
- interrupts = <47>;
- clocks = <&clks 10>, <&clks 50>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
- };
-
- spba-bus@50000000 {
- compatible = "fsl,spba-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x50000000 0x100000>;
- ranges;
-
- sdhci1: mmc@50004000 {
- compatible = "fsl,imx31-mmc";
- reg = <0x50004000 0x4000>;
- interrupts = <9>;
- clocks = <&clks 10>, <&clks 20>;
- clock-names = "ipg", "per";
- dmas = <&sdma 20 3 0>;
- dma-names = "rx-tx";
- status = "disabled";
- };
-
- sdhci2: mmc@50008000 {
- compatible = "fsl,imx31-mmc";
- reg = <0x50008000 0x4000>;
- interrupts = <8>;
- clocks = <&clks 10>, <&clks 21>;
- clock-names = "ipg", "per";
- dmas = <&sdma 21 3 0>;
- dma-names = "rx-tx";
- status = "disabled";
- };
-
- uart3: serial@5000c000 {
- compatible = "fsl,imx31-uart", "fsl,imx21-uart";
- reg = <0x5000c000 0x4000>;
- interrupts = <18>;
- clocks = <&clks 10>, <&clks 48>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- spi2: spi@50010000 {
- compatible = "fsl,imx31-cspi";
- reg = <0x50010000 0x4000>;
- interrupts = <13>;
- clocks = <&clks 10>, <&clks 54>;
- clock-names = "ipg", "per";
- dmas = <&sdma 6 8 0>, <&sdma 7 8 0>;
- dma-names = "rx", "tx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- iim: efuse@5001c000 {
- compatible = "fsl,imx31-iim";
- reg = <0x5001c000 0x1000>;
- interrupts = <19>;
- clocks = <&clks 25>;
- };
- };
-
- bus@53f00000 { /* AIPS2 */
- compatible = "fsl,aips-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x53f00000 0x100000>;
- ranges;
-
- clks: ccm@53f80000 {
- compatible = "fsl,imx31-ccm";
- reg = <0x53f80000 0x4000>;
- interrupts = <31>, <53>;
- #clock-cells = <1>;
- };
-
- spi3: spi@53f84000 {
- compatible = "fsl,imx31-cspi";
- reg = <0x53f84000 0x4000>;
- interrupts = <17>;
- clocks = <&clks 10>, <&clks 28>;
- clock-names = "ipg", "per";
- dmas = <&sdma 10 8 0>, <&sdma 11 8 0>;
- dma-names = "rx", "tx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- gpt: timer@53f90000 {
- compatible = "fsl,imx31-gpt";
- reg = <0x53f90000 0x4000>;
- interrupts = <29>;
- clocks = <&clks 10>, <&clks 22>;
- clock-names = "ipg", "per";
- };
-
- gpio3: gpio@53fa4000 {
- compatible = "fsl,imx31-gpio";
- reg = <0x53fa4000 0x4000>;
- interrupts = <56>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- rng@53fb0000 {
- compatible = "fsl,imx31-rnga";
- reg = <0x53fb0000 0x4000>;
- interrupts = <22>;
- clocks = <&clks 29>;
- };
-
- gpio1: gpio@53fcc000 {
- compatible = "fsl,imx31-gpio";
- reg = <0x53fcc000 0x4000>;
- interrupts = <52>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@53fd0000 {
- compatible = "fsl,imx31-gpio";
- reg = <0x53fd0000 0x4000>;
- interrupts = <51>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- sdma: dma-controller@53fd4000 {
- compatible = "fsl,imx31-sdma";
- reg = <0x53fd4000 0x4000>;
- interrupts = <34>;
- clocks = <&clks 10>, <&clks 27>;
- clock-names = "ipg", "ahb";
- #dma-cells = <3>;
- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin";
- };
-
- rtc: rtc@53fd8000 {
- compatible = "fsl,imx31-rtc", "fsl,imx21-rtc";
- reg = <0x53fd8000 0x4000>;
- interrupts = <25>;
- clocks = <&clks 2>, <&clks 40>;
- clock-names = "ref", "ipg";
- };
-
- wdog: watchdog@53fdc000 {
- compatible = "fsl,imx31-wdt", "fsl,imx21-wdt";
- reg = <0x53fdc000 0x4000>;
- clocks = <&clks 41>;
- interrupts = <55>;
- };
-
- pwm: pwm@53fe0000 {
- compatible = "fsl,imx31-pwm", "fsl,imx27-pwm";
- reg = <0x53fe0000 0x4000>;
- interrupts = <26>;
- clocks = <&clks 10>, <&clks 42>;
- clock-names = "ipg", "per";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- emi-bus@b8000000 { /* External Memory Interface */
- compatible = "simple-bus";
- reg = <0xb8000000 0x5000>;
- ranges;
- #address-cells = <1>;
- #size-cells = <1>;
-
- nfc: nand-controller@b8000000 {
- compatible = "fsl,imx31-nand", "fsl,imx27-nand";
- reg = <0xb8000000 0x1000>;
- interrupts = <33>;
- clocks = <&clks 9>;
- dmas = <&sdma 30 17 0>;
- dma-names = "rx-tx";
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
- };
-
- weim: memory-controller@b8002000 {
- compatible = "fsl,imx31-weim", "fsl,imx27-weim";
- reg = <0xb8002000 0x1000>;
- clocks = <&clks 56>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0xa0000000 0x08000000
- 1 0 0xa8000000 0x08000000
- 2 0 0xb0000000 0x02000000
- 3 0 0xb2000000 0x02000000
- 4 0 0xb4000000 0x02000000
- 5 0 0xb6000000 0x02000000>;
- status = "disabled";
- };
- };
- };
-};
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index ed588add8d31..6ac42c06c1e9 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -15,7 +15,6 @@ CONFIG_PERF_EVENTS=y
CONFIG_KEXEC=y
CONFIG_ARCH_MULTI_V6=y
CONFIG_ARCH_MXC=y
-CONFIG_SOC_IMX31=y
CONFIG_SOC_IMX35=y
CONFIG_SOC_IMX50=y
CONFIG_SOC_IMX51=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3f0521c652cb..77704c6a70ba 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -39,17 +39,6 @@ if ARCH_MULTI_V6
comment "ARM1136 platforms"
-config SOC_IMX31
- bool "i.MX31 support (DEPRECATED)"
- depends on !SMP
- select CPU_ARM1136R0
- select MXC_AVIC
- help
- This enables support for Freescale i.MX31 processor
-
- This SoC is scheduled for removal in early 2027,
- since it uses the ARM1136r0 CPU revision.
-
config SOC_IMX35
bool "i.MX35 support"
select CPU_ARM1136R1
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 5c650bf40e02..fa0144f0882d 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -5,7 +5,6 @@ obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o
obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o mach-imx27.o
-obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o mach-imx31.o
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o mach-imx35.o
imx5-pm-$(CONFIG_PM) += pm-imx5.o
diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c
deleted file mode 100644
index e81ef9e36a1f..000000000000
--- a/arch/arm/mach-imx/cpu-imx31.c
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * MX31 CPU type detection
- *
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- */
-
-#include <linux/module.h>
-#include <linux/of_address.h>
-#include <linux/io.h>
-
-#include "common.h"
-#include "hardware.h"
-#include "iim.h"
-
-static int mx31_cpu_rev = -1;
-
-static struct {
- u8 srev;
- const char *name;
- unsigned int rev;
-} mx31_cpu_type[] = {
- { .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 },
- { .srev = 0x10, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 },
- { .srev = 0x11, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 },
- { .srev = 0x12, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 },
- { .srev = 0x13, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 },
- { .srev = 0x14, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_2 },
- { .srev = 0x15, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_2 },
- { .srev = 0x28, .name = "i.MX31", .rev = IMX_CHIP_REVISION_2_0 },
- { .srev = 0x29, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_2_0 },
-};
-
-static int mx31_read_cpu_rev(void)
-{
- void __iomem *iim_base;
- struct device_node *np;
- u32 i, srev;
- int rev = IMX_CHIP_REVISION_UNKNOWN;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,imx31-iim");
- iim_base = of_iomap(np, 0);
- of_node_put(np);
- BUG_ON(!iim_base);
-
- /* read SREV register from IIM module */
- srev = imx_readl(iim_base + MXC_IIMSREV);
- srev &= 0xff;
-
- for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
- if (srev == mx31_cpu_type[i].srev) {
- rev = mx31_cpu_type[i].rev;
- imx_print_silicon_rev(mx31_cpu_type[i].name,
- mx31_cpu_type[i].rev);
- goto out;
- }
-
- imx_print_silicon_rev("i.MX31", IMX_CHIP_REVISION_UNKNOWN);
-
-out:
- iounmap(iim_base);
- return rev;
-}
-
-int mx31_revision(void)
-{
- if (mx31_cpu_rev == -1)
- mx31_cpu_rev = mx31_read_cpu_rev();
-
- return mx31_cpu_rev;
-}
-EXPORT_SYMBOL(mx31_revision);
diff --git a/arch/arm/mach-imx/mach-imx31.c b/arch/arm/mach-imx/mach-imx31.c
deleted file mode 100644
index e9a1092b6093..000000000000
--- a/arch/arm/mach-imx/mach-imx31.c
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2012 Sascha Hauer, Pengutronix
- */
-
-#include <asm/mach/arch.h>
-#include "common.h"
-
-static const char * const imx31_dt_board_compat[] __initconst = {
- "fsl,imx31",
- NULL
-};
-
-DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
- .map_io = mx31_map_io,
- .init_early = imx31_init_early,
- .dt_compat = imx31_dt_board_compat,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 9b0b014d7fe2..42e73518004a 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -69,49 +69,6 @@ static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
return __arm_ioremap_caller(phys_addr, size, mtype, caller);
}
-#ifdef CONFIG_SOC_IMX31
-static struct map_desc mx31_io_desc[] __initdata = {
- imx_map_entry(MX31, X_MEMC, MT_DEVICE),
- imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
- imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
- imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
- imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
-};
-
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx31_map_io(void)
-{
- iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
-}
-
-static void imx31_idle(void)
-{
- int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
- reg &= ~MXC_CCM_CCMR_LPM_MASK;
- imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
-
- imx3_idle();
-}
-
-void __init imx31_init_early(void)
-{
- struct device_node *np;
-
- mxc_set_cpu_type(MXC_CPU_MX31);
- arch_ioremap_caller = imx3_ioremap_caller;
- arm_pm_idle = imx31_idle;
- np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
- mx3_ccm_base = of_iomap(np, 0);
- of_node_put(np);
- BUG_ON(!mx3_ccm_base);
-}
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
static struct map_desc mx35_io_desc[] __initdata = {
imx_map_entry(MX35, X_MEMC, MT_DEVICE),
imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
@@ -147,4 +104,3 @@ void __init imx35_init_early(void)
of_node_put(np);
BUG_ON(!mx3_ccm_base);
}
-#endif /* ifdef CONFIG_SOC_IMX35 */
--
2.53.0
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 07/13] ARM: imx: remove i.MX31 SoC support
2026-09-08 15:27 ` [PATCH 07/13] ARM: imx: remove i.MX31 SoC support Arnd Bergmann
@ 2026-09-09 8:24 ` Vladimir Zapolskiy
2026-09-09 8:26 ` Daniel Baluta
2026-09-10 15:11 ` Frank Li
2 siblings, 0 replies; 70+ messages in thread
From: Vladimir Zapolskiy @ 2026-09-09 8:24 UTC (permalink / raw)
To: Arnd Bergmann, Krzysztof Kozlowski, Alexandre Belloni,
Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Stefan Agner, Maxime Coquelin, Alexandre Torgue, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Nicolas Ferre, Claudiu Beznea, Andrew Lunn,
Sebastian Hesselbarth, Gregory Clement, Robert Jarzmik,
Kristoffer Ericson, Ethan Nelson-Moore, Geert Uytterhoeven,
Alexander Sverdlin, Shawn Guo, Karl Mehltretter,
David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski
On 9/8/26 18:27, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The Freescale i.MX31 was an early SoC based on the ARM1136r0 CPU core. It
> was used in the Bug Labs modular computer but ultimately much less
> popular than most other i.MX SoCs.
>
> As the ARM1136r0 support is causing a lot of extra maintenance effort
> to keep alive and there are no known users, remove i.MX31 in order to
> allow removing support for that CPU core altogether.
>
> The related i.MX35 is based on a slightly newer ARM1136r1 CPU core that
> does not have this problem, so there is no reason to remove that.
>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Frank Li <Frank.Li@nxp.com>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: imx@lists.linux.dev
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
I still do possess a LogicPD i.MX31 Lite board, which boots the upstream
kernel, but there is no plan to maintain it further.
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 07/13] ARM: imx: remove i.MX31 SoC support
2026-09-08 15:27 ` [PATCH 07/13] ARM: imx: remove i.MX31 SoC support Arnd Bergmann
2026-09-09 8:24 ` Vladimir Zapolskiy
@ 2026-09-09 8:26 ` Daniel Baluta
2026-09-10 15:11 ` Frank Li
2 siblings, 0 replies; 70+ messages in thread
From: Daniel Baluta @ 2026-09-09 8:26 UTC (permalink / raw)
To: Arnd Bergmann, Krzysztof Kozlowski, Alexandre Belloni,
Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski
On 9/8/26 18:27, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The Freescale i.MX31 was an early SoC based on the ARM1136r0 CPU core. It
> was used in the Bug Labs modular computer but ultimately much less
> popular than most other i.MX SoCs.
>
> As the ARM1136r0 support is causing a lot of extra maintenance effort
> to keep alive and there are no known users, remove i.MX31 in order to
> allow removing support for that CPU core altogether.
>
> The related i.MX35 is based on a slightly newer ARM1136r1 CPU core that
> does not have this problem, so there is no reason to remove that.
>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Frank Li <Frank.Li@nxp.com>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: imx@lists.linux.dev
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Daniel Baluta <daniel.baluta@nxp.com>
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 07/13] ARM: imx: remove i.MX31 SoC support
2026-09-08 15:27 ` [PATCH 07/13] ARM: imx: remove i.MX31 SoC support Arnd Bergmann
2026-09-09 8:24 ` Vladimir Zapolskiy
2026-09-09 8:26 ` Daniel Baluta
@ 2026-09-10 15:11 ` Frank Li
2 siblings, 0 replies; 70+ messages in thread
From: Frank Li @ 2026-09-10 15:11 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Arnd Bergmann, Rob Herring,
Conor Dooley, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski
On Tue, Sep 08, 2026 at 05:27:57PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The Freescale i.MX31 was an early SoC based on the ARM1136r0 CPU core. It
> was used in the Bug Labs modular computer but ultimately much less
> popular than most other i.MX SoCs.
>
> As the ARM1136r0 support is causing a lot of extra maintenance effort
> to keep alive and there are no known users, remove i.MX31 in order to
> allow removing support for that CPU core altogether.
>
> The related i.MX35 is based on a slightly newer ARM1136r1 CPU core that
> does not have this problem, so there is no reason to remove that.
>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Frank Li <Frank.Li@nxp.com>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: imx@lists.linux.dev
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
Acked-by: Frank Li <Frank.Li@nxp.com>
> arch/arm/Kconfig.debug | 9 -
> arch/arm/boot/dts/nxp/imx/Makefile | 3 -
> arch/arm/boot/dts/nxp/imx/imx31-bug.dts | 22 --
> arch/arm/boot/dts/nxp/imx/imx31-lite.dts | 178 -----------
> arch/arm/boot/dts/nxp/imx/imx31.dtsi | 371 -----------------------
> arch/arm/configs/imx_v6_v7_defconfig | 1 -
> arch/arm/mach-imx/Kconfig | 11 -
> arch/arm/mach-imx/Makefile | 1 -
> arch/arm/mach-imx/cpu-imx31.c | 72 -----
> arch/arm/mach-imx/mach-imx31.c | 18 --
> arch/arm/mach-imx/mm-imx3.c | 44 ---
> 11 files changed, 730 deletions(-)
> delete mode 100644 arch/arm/boot/dts/nxp/imx/imx31-bug.dts
> delete mode 100644 arch/arm/boot/dts/nxp/imx/imx31-lite.dts
> delete mode 100644 arch/arm/boot/dts/nxp/imx/imx31.dtsi
> delete mode 100644 arch/arm/mach-imx/cpu-imx31.c
> delete mode 100644 arch/arm/mach-imx/mach-imx31.c
>
> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index e2fc89055463..52387fe2a057 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -424,13 +424,6 @@ choice
> Say Y here if you want kernel low-level debugging support
> on i.MX28.
>
> - config DEBUG_IMX31_UART
> - bool "i.MX31 Debug UART"
> - depends on SOC_IMX31
> - help
> - Say Y here if you want kernel low-level debugging support
> - on i.MX31.
> -
> config DEBUG_IMX35_UART
> bool "i.MX35 Debug UART"
> depends on SOC_IMX35
> @@ -1411,7 +1404,6 @@ config DEBUG_IMX_UART_PORT
> depends on DEBUG_IMX1_UART || \
> DEBUG_IMX25_UART || \
> DEBUG_IMX27_UART || \
> - DEBUG_IMX31_UART || \
> DEBUG_IMX35_UART || \
> DEBUG_IMX50_UART || \
> DEBUG_IMX51_UART || \
> @@ -1468,7 +1460,6 @@ config DEBUG_LL_INCLUDE
> default "debug/imx.S" if DEBUG_IMX1_UART || \
> DEBUG_IMX25_UART || \
> DEBUG_IMX27_UART || \
> - DEBUG_IMX31_UART || \
> DEBUG_IMX35_UART || \
> DEBUG_IMX50_UART || \
> DEBUG_IMX51_UART || \
> diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
> index 1a2539fa19b4..e0747cb6e772 100644
> --- a/arch/arm/boot/dts/nxp/imx/Makefile
> +++ b/arch/arm/boot/dts/nxp/imx/Makefile
> @@ -16,9 +16,6 @@ dtb-$(CONFIG_SOC_IMX27) += \
> imx27-pdk.dtb \
> imx27-phytec-phycore-rdk.dtb \
> imx27-phytec-phycard-s-rdk.dtb
> -dtb-$(CONFIG_SOC_IMX31) += \
> - imx31-bug.dtb \
> - imx31-lite.dtb
> dtb-$(CONFIG_SOC_IMX35) += \
> imx35-eukrea-mbimxsd35-baseboard.dtb \
> imx35-pdk.dtb
> diff --git a/arch/arm/boot/dts/nxp/imx/imx31-bug.dts b/arch/arm/boot/dts/nxp/imx/imx31-bug.dts
> deleted file mode 100644
> index d87eee3f9b3c..000000000000
> --- a/arch/arm/boot/dts/nxp/imx/imx31-bug.dts
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later
> -/*
> - * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
> - */
> -
> -/dts-v1/;
> -#include "imx31.dtsi"
> -
> -/ {
> - model = "Buglabs i.MX31 Bug 1.x";
> - compatible = "buglabs,imx31-bug", "fsl,imx31";
> -
> - memory@80000000 {
> - device_type = "memory";
> - reg = <0x80000000 0x8000000>; /* 128M */
> - };
> -};
> -
> -&uart5 {
> - uart-has-rtscts;
> - status = "okay";
> -};
> diff --git a/arch/arm/boot/dts/nxp/imx/imx31-lite.dts b/arch/arm/boot/dts/nxp/imx/imx31-lite.dts
> deleted file mode 100644
> index 630f8fa69ba8..000000000000
> --- a/arch/arm/boot/dts/nxp/imx/imx31-lite.dts
> +++ /dev/null
> @@ -1,178 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -//
> -// Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
> -
> -/dts-v1/;
> -
> -#include "imx31.dtsi"
> -
> -#include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/interrupt-controller/irq.h>
> -
> -/ {
> - model = "LogicPD i.MX31 Lite";
> - compatible = "logicpd,imx31-lite", "fsl,imx31";
> -
> - chosen {
> - stdout-path = &uart1;
> - };
> -
> - memory@80000000 {
> - device_type = "memory";
> - reg = <0x80000000 0x8000000>;
> - };
> -
> - leds {
> - compatible = "gpio-leds";
> -
> - led0 {
> - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
> - };
> -
> - led1 {
> - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
> - };
> - };
> -};
> -
> -&ata {
> - status = "okay";
> -};
> -
> -&nfc {
> - nand-bus-width = <8>;
> - nand-ecc-mode = "hw";
> - nand-on-flash-bbt;
> - status = "okay";
> -};
> -
> -&sdhci1 {
> - bus-width = <4>;
> - cd-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
> - wp-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
> - status = "okay";
> -};
> -
> -&spi2 {
> - status = "okay";
> -
> - pmic@0 {
> - compatible = "fsl,mc13783";
> - reg = <0>;
> - spi-cs-high;
> - spi-max-frequency = <1000000>;
> - interrupt-parent = <&gpio1>;
> - interrupts = <3 IRQ_TYPE_EDGE_RISING>;
> -
> - fsl,mc13xxx-uses-adc;
> - fsl,mc13xxx-uses-rtc;
> -
> - regulators {
> - sw1a { /* QVCC */
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - regulator-boot-on;
> - };
> -
> - sw1b { /* QVCC */
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - regulator-boot-on;
> - };
> -
> - sw2a { /* 1.8V_DDR, NVCC2, NVCC21 and NVCC22 */
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - regulator-boot-on;
> - };
> -
> - sw2b { /* NVCC10 */
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - regulator-boot-on;
> - };
> -
> - violo { /* NVCC1 and NVCC7 */
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - regulator-boot-on;
> - };
> -
> - viohi { /* VIOHI */
> - regulator-min-microvolt = <2775000>;
> - regulator-max-microvolt = <2775000>;
> - regulator-always-on;
> - regulator-boot-on;
> - };
> -
> - vaudio { /* VAUDIO */
> - regulator-min-microvolt = <2775000>;
> - regulator-max-microvolt = <2775000>;
> - };
> -
> - vcam { /* NVCC4 */
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - };
> -
> - vgen { /* NVCC5 / NVCC8 and NVCC6 / NVCC9 */
> - regulator-min-microvolt = <2775000>;
> - regulator-max-microvolt = <2775000>;
> - regulator-always-on;
> - regulator-boot-on;
> - };
> -
> - vmmc2 { /* NVCC3 */
> - regulator-min-microvolt = <1600000>;
> - regulator-max-microvolt = <3000000>;
> - regulator-always-on;
> - regulator-boot-on;
> - };
> - };
> - };
> -};
> -
> -&uart1 {
> - uart-has-rtscts;
> - status = "okay";
> -};
> -
> -/* Routed to the extension board */
> -&uart2 {
> - uart-has-rtscts;
> - status = "okay";
> -};
> -
> -/* Routed to the extension board */
> -&uart3 {
> - uart-has-rtscts;
> - status = "okay";
> -};
> -
> -&weim {
> - status = "okay";
> -
> - flash@0,0 {
> - compatible = "cfi-flash";
> - reg = <0 0x0 0x200000>;
> - bank-width = <2>;
> - linux,mtd-name = "physmap-flash.0";
> - fsl,weim-cs-timing = <0x0000cf03 0xa0330d01 0x00220800>;
> - };
> -
> - ethernet@4,0 {
> - compatible = "smsc,lan9117", "smsc,lan9115";
> - reg = <4 0x0 0x100>;
> - interrupt-parent = <&gpio1>;
> - interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
> - phy-mode = "mii";
> - reg-io-width = <2>;
> - smsc,irq-push-pull;
> - fsl,weim-cs-timing = <0x00008701 0x04000541 0x00010000>;
> - };
> -};
> diff --git a/arch/arm/boot/dts/nxp/imx/imx31.dtsi b/arch/arm/boot/dts/nxp/imx/imx31.dtsi
> deleted file mode 100644
> index c58f855ea851..000000000000
> --- a/arch/arm/boot/dts/nxp/imx/imx31.dtsi
> +++ /dev/null
> @@ -1,371 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -//
> -// Copyright 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
> -// Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
> -
> -/ {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - /*
> - * The decompressor and also some bootloaders rely on a
> - * pre-existing /chosen node to be available to insert the
> - * command line and merge other ATAGS info.
> - */
> - chosen {};
> -
> - aliases {
> - gpio0 = &gpio1;
> - gpio1 = &gpio2;
> - gpio2 = &gpio3;
> - i2c0 = &i2c1;
> - i2c1 = &i2c2;
> - i2c2 = &i2c3;
> - serial0 = &uart1;
> - serial1 = &uart2;
> - serial2 = &uart3;
> - serial3 = &uart4;
> - serial4 = &uart5;
> - spi0 = &spi1;
> - spi1 = &spi2;
> - spi2 = &spi3;
> - };
> -
> - cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - cpu@0 {
> - compatible = "arm,arm1136jf-s";
> - device_type = "cpu";
> - reg = <0>;
> - };
> - };
> -
> - avic: interrupt-controller@68000000 {
> - compatible = "fsl,imx31-avic", "fsl,avic";
> - interrupt-controller;
> - #interrupt-cells = <1>;
> - reg = <0x68000000 0x100000>;
> - };
> -
> - soc: soc {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "simple-bus";
> - interrupt-parent = <&avic>;
> - ranges;
> -
> - iram: sram@1fffc000 {
> - compatible = "mmio-sram";
> - reg = <0x1fffc000 0x4000>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0 0x1fffc000 0x4000>;
> - };
> -
> - aips1: bus@43f00000 { /* AIPS1 */
> - compatible = "fsl,aips-bus", "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0x43f00000 0x100000>;
> - ranges;
> -
> - i2c1: i2c@43f80000 {
> - compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
> - reg = <0x43f80000 0x4000>;
> - interrupts = <10>;
> - clocks = <&clks 33>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "disabled";
> - };
> -
> - i2c3: i2c@43f84000 {
> - compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
> - reg = <0x43f84000 0x4000>;
> - interrupts = <3>;
> - clocks = <&clks 35>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "disabled";
> - };
> -
> - ata: ata@43f8c000 {
> - compatible = "fsl,imx31-pata", "fsl,imx27-pata";
> - reg = <0x43f8c000 0x4000>;
> - interrupts = <15>;
> - clocks = <&clks 26>;
> - status = "disabled";
> - };
> -
> - uart1: serial@43f90000 {
> - compatible = "fsl,imx31-uart", "fsl,imx21-uart";
> - reg = <0x43f90000 0x4000>;
> - interrupts = <45>;
> - clocks = <&clks 10>, <&clks 30>;
> - clock-names = "ipg", "per";
> - status = "disabled";
> - };
> -
> - uart2: serial@43f94000 {
> - compatible = "fsl,imx31-uart", "fsl,imx21-uart";
> - reg = <0x43f94000 0x4000>;
> - interrupts = <32>;
> - clocks = <&clks 10>, <&clks 31>;
> - clock-names = "ipg", "per";
> - status = "disabled";
> - };
> -
> - i2c2: i2c@43f98000 {
> - compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
> - reg = <0x43f98000 0x4000>;
> - interrupts = <4>;
> - clocks = <&clks 34>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "disabled";
> - };
> -
> - spi1: spi@43fa4000 {
> - compatible = "fsl,imx31-cspi";
> - reg = <0x43fa4000 0x4000>;
> - interrupts = <14>;
> - clocks = <&clks 10>, <&clks 53>;
> - clock-names = "ipg", "per";
> - dmas = <&sdma 8 8 0>, <&sdma 9 8 0>;
> - dma-names = "rx", "tx";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "disabled";
> - };
> -
> - kpp: kpp@43fa8000 {
> - compatible = "fsl,imx31-kpp", "fsl,imx21-kpp";
> - reg = <0x43fa8000 0x4000>;
> - interrupts = <24>;
> - clocks = <&clks 46>;
> - status = "disabled";
> - };
> -
> - uart4: serial@43fb0000 {
> - compatible = "fsl,imx31-uart", "fsl,imx21-uart";
> - reg = <0x43fb0000 0x4000>;
> - clocks = <&clks 10>, <&clks 49>;
> - clock-names = "ipg", "per";
> - interrupts = <46>;
> - status = "disabled";
> - };
> -
> - uart5: serial@43fb4000 {
> - compatible = "fsl,imx31-uart", "fsl,imx21-uart";
> - reg = <0x43fb4000 0x4000>;
> - interrupts = <47>;
> - clocks = <&clks 10>, <&clks 50>;
> - clock-names = "ipg", "per";
> - status = "disabled";
> - };
> - };
> -
> - spba-bus@50000000 {
> - compatible = "fsl,spba-bus", "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0x50000000 0x100000>;
> - ranges;
> -
> - sdhci1: mmc@50004000 {
> - compatible = "fsl,imx31-mmc";
> - reg = <0x50004000 0x4000>;
> - interrupts = <9>;
> - clocks = <&clks 10>, <&clks 20>;
> - clock-names = "ipg", "per";
> - dmas = <&sdma 20 3 0>;
> - dma-names = "rx-tx";
> - status = "disabled";
> - };
> -
> - sdhci2: mmc@50008000 {
> - compatible = "fsl,imx31-mmc";
> - reg = <0x50008000 0x4000>;
> - interrupts = <8>;
> - clocks = <&clks 10>, <&clks 21>;
> - clock-names = "ipg", "per";
> - dmas = <&sdma 21 3 0>;
> - dma-names = "rx-tx";
> - status = "disabled";
> - };
> -
> - uart3: serial@5000c000 {
> - compatible = "fsl,imx31-uart", "fsl,imx21-uart";
> - reg = <0x5000c000 0x4000>;
> - interrupts = <18>;
> - clocks = <&clks 10>, <&clks 48>;
> - clock-names = "ipg", "per";
> - status = "disabled";
> - };
> -
> - spi2: spi@50010000 {
> - compatible = "fsl,imx31-cspi";
> - reg = <0x50010000 0x4000>;
> - interrupts = <13>;
> - clocks = <&clks 10>, <&clks 54>;
> - clock-names = "ipg", "per";
> - dmas = <&sdma 6 8 0>, <&sdma 7 8 0>;
> - dma-names = "rx", "tx";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "disabled";
> - };
> -
> - iim: efuse@5001c000 {
> - compatible = "fsl,imx31-iim";
> - reg = <0x5001c000 0x1000>;
> - interrupts = <19>;
> - clocks = <&clks 25>;
> - };
> - };
> -
> - bus@53f00000 { /* AIPS2 */
> - compatible = "fsl,aips-bus", "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0x53f00000 0x100000>;
> - ranges;
> -
> - clks: ccm@53f80000 {
> - compatible = "fsl,imx31-ccm";
> - reg = <0x53f80000 0x4000>;
> - interrupts = <31>, <53>;
> - #clock-cells = <1>;
> - };
> -
> - spi3: spi@53f84000 {
> - compatible = "fsl,imx31-cspi";
> - reg = <0x53f84000 0x4000>;
> - interrupts = <17>;
> - clocks = <&clks 10>, <&clks 28>;
> - clock-names = "ipg", "per";
> - dmas = <&sdma 10 8 0>, <&sdma 11 8 0>;
> - dma-names = "rx", "tx";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "disabled";
> - };
> -
> - gpt: timer@53f90000 {
> - compatible = "fsl,imx31-gpt";
> - reg = <0x53f90000 0x4000>;
> - interrupts = <29>;
> - clocks = <&clks 10>, <&clks 22>;
> - clock-names = "ipg", "per";
> - };
> -
> - gpio3: gpio@53fa4000 {
> - compatible = "fsl,imx31-gpio";
> - reg = <0x53fa4000 0x4000>;
> - interrupts = <56>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - };
> -
> - rng@53fb0000 {
> - compatible = "fsl,imx31-rnga";
> - reg = <0x53fb0000 0x4000>;
> - interrupts = <22>;
> - clocks = <&clks 29>;
> - };
> -
> - gpio1: gpio@53fcc000 {
> - compatible = "fsl,imx31-gpio";
> - reg = <0x53fcc000 0x4000>;
> - interrupts = <52>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - };
> -
> - gpio2: gpio@53fd0000 {
> - compatible = "fsl,imx31-gpio";
> - reg = <0x53fd0000 0x4000>;
> - interrupts = <51>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - };
> -
> - sdma: dma-controller@53fd4000 {
> - compatible = "fsl,imx31-sdma";
> - reg = <0x53fd4000 0x4000>;
> - interrupts = <34>;
> - clocks = <&clks 10>, <&clks 27>;
> - clock-names = "ipg", "ahb";
> - #dma-cells = <3>;
> - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin";
> - };
> -
> - rtc: rtc@53fd8000 {
> - compatible = "fsl,imx31-rtc", "fsl,imx21-rtc";
> - reg = <0x53fd8000 0x4000>;
> - interrupts = <25>;
> - clocks = <&clks 2>, <&clks 40>;
> - clock-names = "ref", "ipg";
> - };
> -
> - wdog: watchdog@53fdc000 {
> - compatible = "fsl,imx31-wdt", "fsl,imx21-wdt";
> - reg = <0x53fdc000 0x4000>;
> - clocks = <&clks 41>;
> - interrupts = <55>;
> - };
> -
> - pwm: pwm@53fe0000 {
> - compatible = "fsl,imx31-pwm", "fsl,imx27-pwm";
> - reg = <0x53fe0000 0x4000>;
> - interrupts = <26>;
> - clocks = <&clks 10>, <&clks 42>;
> - clock-names = "ipg", "per";
> - #pwm-cells = <3>;
> - status = "disabled";
> - };
> - };
> -
> - emi-bus@b8000000 { /* External Memory Interface */
> - compatible = "simple-bus";
> - reg = <0xb8000000 0x5000>;
> - ranges;
> - #address-cells = <1>;
> - #size-cells = <1>;
> -
> - nfc: nand-controller@b8000000 {
> - compatible = "fsl,imx31-nand", "fsl,imx27-nand";
> - reg = <0xb8000000 0x1000>;
> - interrupts = <33>;
> - clocks = <&clks 9>;
> - dmas = <&sdma 30 17 0>;
> - dma-names = "rx-tx";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - status = "disabled";
> - };
> -
> - weim: memory-controller@b8002000 {
> - compatible = "fsl,imx31-weim", "fsl,imx27-weim";
> - reg = <0xb8002000 0x1000>;
> - clocks = <&clks 56>;
> - #address-cells = <2>;
> - #size-cells = <1>;
> - ranges = <0 0 0xa0000000 0x08000000
> - 1 0 0xa8000000 0x08000000
> - 2 0 0xb0000000 0x02000000
> - 3 0 0xb2000000 0x02000000
> - 4 0 0xb4000000 0x02000000
> - 5 0 0xb6000000 0x02000000>;
> - status = "disabled";
> - };
> - };
> - };
> -};
> diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
> index ed588add8d31..6ac42c06c1e9 100644
> --- a/arch/arm/configs/imx_v6_v7_defconfig
> +++ b/arch/arm/configs/imx_v6_v7_defconfig
> @@ -15,7 +15,6 @@ CONFIG_PERF_EVENTS=y
> CONFIG_KEXEC=y
> CONFIG_ARCH_MULTI_V6=y
> CONFIG_ARCH_MXC=y
> -CONFIG_SOC_IMX31=y
> CONFIG_SOC_IMX35=y
> CONFIG_SOC_IMX50=y
> CONFIG_SOC_IMX51=y
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 3f0521c652cb..77704c6a70ba 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -39,17 +39,6 @@ if ARCH_MULTI_V6
>
> comment "ARM1136 platforms"
>
> -config SOC_IMX31
> - bool "i.MX31 support (DEPRECATED)"
> - depends on !SMP
> - select CPU_ARM1136R0
> - select MXC_AVIC
> - help
> - This enables support for Freescale i.MX31 processor
> -
> - This SoC is scheduled for removal in early 2027,
> - since it uses the ARM1136r0 CPU revision.
> -
> config SOC_IMX35
> bool "i.MX35 support"
> select CPU_ARM1136R1
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index 5c650bf40e02..fa0144f0882d 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -5,7 +5,6 @@ obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o
>
> obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o mach-imx27.o
>
> -obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o mach-imx31.o
> obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o mach-imx35.o
>
> imx5-pm-$(CONFIG_PM) += pm-imx5.o
> diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c
> deleted file mode 100644
> index e81ef9e36a1f..000000000000
> --- a/arch/arm/mach-imx/cpu-imx31.c
> +++ /dev/null
> @@ -1,72 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later
> -/*
> - * MX31 CPU type detection
> - *
> - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
> - */
> -
> -#include <linux/module.h>
> -#include <linux/of_address.h>
> -#include <linux/io.h>
> -
> -#include "common.h"
> -#include "hardware.h"
> -#include "iim.h"
> -
> -static int mx31_cpu_rev = -1;
> -
> -static struct {
> - u8 srev;
> - const char *name;
> - unsigned int rev;
> -} mx31_cpu_type[] = {
> - { .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 },
> - { .srev = 0x10, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 },
> - { .srev = 0x11, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 },
> - { .srev = 0x12, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 },
> - { .srev = 0x13, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 },
> - { .srev = 0x14, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_2 },
> - { .srev = 0x15, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_2 },
> - { .srev = 0x28, .name = "i.MX31", .rev = IMX_CHIP_REVISION_2_0 },
> - { .srev = 0x29, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_2_0 },
> -};
> -
> -static int mx31_read_cpu_rev(void)
> -{
> - void __iomem *iim_base;
> - struct device_node *np;
> - u32 i, srev;
> - int rev = IMX_CHIP_REVISION_UNKNOWN;
> -
> - np = of_find_compatible_node(NULL, NULL, "fsl,imx31-iim");
> - iim_base = of_iomap(np, 0);
> - of_node_put(np);
> - BUG_ON(!iim_base);
> -
> - /* read SREV register from IIM module */
> - srev = imx_readl(iim_base + MXC_IIMSREV);
> - srev &= 0xff;
> -
> - for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
> - if (srev == mx31_cpu_type[i].srev) {
> - rev = mx31_cpu_type[i].rev;
> - imx_print_silicon_rev(mx31_cpu_type[i].name,
> - mx31_cpu_type[i].rev);
> - goto out;
> - }
> -
> - imx_print_silicon_rev("i.MX31", IMX_CHIP_REVISION_UNKNOWN);
> -
> -out:
> - iounmap(iim_base);
> - return rev;
> -}
> -
> -int mx31_revision(void)
> -{
> - if (mx31_cpu_rev == -1)
> - mx31_cpu_rev = mx31_read_cpu_rev();
> -
> - return mx31_cpu_rev;
> -}
> -EXPORT_SYMBOL(mx31_revision);
> diff --git a/arch/arm/mach-imx/mach-imx31.c b/arch/arm/mach-imx/mach-imx31.c
> deleted file mode 100644
> index e9a1092b6093..000000000000
> --- a/arch/arm/mach-imx/mach-imx31.c
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later
> -/*
> - * Copyright 2012 Sascha Hauer, Pengutronix
> - */
> -
> -#include <asm/mach/arch.h>
> -#include "common.h"
> -
> -static const char * const imx31_dt_board_compat[] __initconst = {
> - "fsl,imx31",
> - NULL
> -};
> -
> -DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
> - .map_io = mx31_map_io,
> - .init_early = imx31_init_early,
> - .dt_compat = imx31_dt_board_compat,
> -MACHINE_END
> diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
> index 9b0b014d7fe2..42e73518004a 100644
> --- a/arch/arm/mach-imx/mm-imx3.c
> +++ b/arch/arm/mach-imx/mm-imx3.c
> @@ -69,49 +69,6 @@ static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
> return __arm_ioremap_caller(phys_addr, size, mtype, caller);
> }
>
> -#ifdef CONFIG_SOC_IMX31
> -static struct map_desc mx31_io_desc[] __initdata = {
> - imx_map_entry(MX31, X_MEMC, MT_DEVICE),
> - imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
> - imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
> - imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
> - imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
> -};
> -
> -/*
> - * This function initializes the memory map. It is called during the
> - * system startup to create static physical to virtual memory mappings
> - * for the IO modules.
> - */
> -void __init mx31_map_io(void)
> -{
> - iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
> -}
> -
> -static void imx31_idle(void)
> -{
> - int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
> - reg &= ~MXC_CCM_CCMR_LPM_MASK;
> - imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
> -
> - imx3_idle();
> -}
> -
> -void __init imx31_init_early(void)
> -{
> - struct device_node *np;
> -
> - mxc_set_cpu_type(MXC_CPU_MX31);
> - arch_ioremap_caller = imx3_ioremap_caller;
> - arm_pm_idle = imx31_idle;
> - np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
> - mx3_ccm_base = of_iomap(np, 0);
> - of_node_put(np);
> - BUG_ON(!mx3_ccm_base);
> -}
> -#endif /* ifdef CONFIG_SOC_IMX31 */
> -
> -#ifdef CONFIG_SOC_IMX35
> static struct map_desc mx35_io_desc[] __initdata = {
> imx_map_entry(MX35, X_MEMC, MT_DEVICE),
> imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
> @@ -147,4 +104,3 @@ void __init imx35_init_early(void)
> of_node_put(np);
> BUG_ON(!mx3_ccm_base);
> }
> -#endif /* ifdef CONFIG_SOC_IMX35 */
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH 08/13] ARM: imx: remove nommu support
2026-09-08 15:27 [PATCH 00/13] ARM: deprecated platform removal Arnd Bergmann
` (6 preceding siblings ...)
2026-09-08 15:27 ` [PATCH 07/13] ARM: imx: remove i.MX31 SoC support Arnd Bergmann
@ 2026-09-08 15:27 ` Arnd Bergmann
2026-09-09 20:17 ` Fabio Estevam
` (2 more replies)
2026-09-08 15:27 ` [PATCH 09/13] ARM: lpc18xx: remove entire platform Arnd Bergmann
` (5 subsequent siblings)
13 siblings, 3 replies; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 15:27 UTC (permalink / raw)
To: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski,
Giulio Benetti
From: Arnd Bergmann <arnd@arndb.de>
The i.MX platform has grown support for three separate product
lines using Cortex-M based microcontrollers over the years:
- i.MX RT1050, a high-end microcontroller
- Vybrid vf610 suppors running Linux on either the Cortex-A5
CPU or the Cortex-M4 MCU
- i.MX7D similarly can run Linux on the Cortex-A7 or the
Cortex-M4
There are no known upstream users of any of those three, so
drop support and simplify the platform to assume that an MMU
is present.
Cc: Frank Li <Frank.Li@nxp.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Rob Herring <robh@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Giulio Benetti <giulio.benetti@benettiengineering.com>
Cc: devicetree@vger.kernel.org
Cc: imx@lists.linux.dev
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/boot/dts/nxp/imx/Makefile | 2 -
arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts | 72 -
arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h | 993 -----------
arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi | 160 --
arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h | 1561 -----------------
arch/arm/boot/dts/nxp/vf/Makefile | 2 -
arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts | 61 -
arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts | 88 -
arch/arm/boot/dts/nxp/vf/vf610m4.dtsi | 61 -
arch/arm/configs/imxrt_defconfig | 35 -
arch/arm/configs/vf610m4_defconfig | 39 -
arch/arm/mach-imx/Kconfig | 27 +-
arch/arm/mach-imx/Makefile | 3 -
arch/arm/mach-imx/mach-imx7d-cm4.c | 18 -
arch/arm/mach-imx/mach-imxrt.c | 19 -
arch/arm/mach-imx/mach-vf610.c | 1 -
16 files changed, 6 insertions(+), 3136 deletions(-)
delete mode 100644 arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts
delete mode 100644 arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h
delete mode 100644 arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi
delete mode 100644 arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h
delete mode 100644 arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts
delete mode 100644 arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts
delete mode 100644 arch/arm/boot/dts/nxp/vf/vf610m4.dtsi
delete mode 100644 arch/arm/configs/imxrt_defconfig
delete mode 100644 arch/arm/configs/vf610m4_defconfig
delete mode 100644 arch/arm/mach-imx/mach-imx7d-cm4.c
delete mode 100644 arch/arm/mach-imx/mach-imxrt.c
diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
index e0747cb6e772..288d16d9315d 100644
--- a/arch/arm/boot/dts/nxp/imx/Makefile
+++ b/arch/arm/boot/dts/nxp/imx/Makefile
@@ -452,5 +452,3 @@ dtb-$(CONFIG_SOC_IMX7D) += \
dtb-$(CONFIG_SOC_IMX7ULP) += \
imx7ulp-com.dtb \
imx7ulp-evk.dtb
-dtb-$(CONFIG_SOC_IMXRT) += \
- imxrt1050-evk.dtb
diff --git a/arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts b/arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts
deleted file mode 100644
index 6a9c10decf52..000000000000
--- a/arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-/dts-v1/;
-#include "imxrt1050.dtsi"
-#include "imxrt1050-pinfunc.h"
-
-/ {
- model = "NXP IMXRT1050-evk board";
- compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
-
- chosen {
- stdout-path = &lpuart1;
- };
-
- aliases {
- gpio0 = &gpio1;
- gpio1 = &gpio2;
- gpio2 = &gpio3;
- gpio3 = &gpio4;
- gpio4 = &gpio5;
- mmc0 = &usdhc1;
- serial0 = &lpuart1;
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x2000000>;
- };
-};
-
-&lpuart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpuart1>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl_lpuart1: lpuart1grp {
- fsl,pins = <
- MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1
- MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1
- >;
- };
-
- pinctrl_usdhc0: usdhc0grp {
- fsl,pins = <
- MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000
- MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069
- MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061
- >;
- };
-};
-
-&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
- pinctrl-0 = <&pinctrl_usdhc0>;
- pinctrl-1 = <&pinctrl_usdhc0>;
- pinctrl-2 = <&pinctrl_usdhc0>;
- pinctrl-3 = <&pinctrl_usdhc0>;
- cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h
deleted file mode 100644
index 22c14a3262ad..000000000000
--- a/arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h
+++ /dev/null
@@ -1,993 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
-#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
-
-#define IMX_PAD_SION 0x40000000
-
-/*
- * The pin function ID is a tuple of
- * <mux_reg conf_reg input_reg mux_mode input_val>
- */
-
-#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x018 0x208 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x20C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x01C 0x20C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x210 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x020 0x210 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x214 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024 0x214 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x024 0x214 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x5C4 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x21C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x02C 0x21C 0x478 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C 0x21C 0x5C0 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x02C 0x21C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x220 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x030 0x220 0x488 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x030 0x220 0x5B0 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x030 0x220 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x224 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x034 0x224 0x47C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x224 0x5B8 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x034 0x224 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x228 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x038 0x228 0x48C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038 0x228 0x5BC 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x038 0x228 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x03C 0x22C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x03C 0x22C 0x480 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C 0x22C 0x5B4 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x03C 0x22C 0x450 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x03C 0x22C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x03C 0x22C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x040 0x230 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x040 0x230 0x490 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x040 0x230 0x4E8 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x040 0x230 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x040 0x230 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x040 0x230 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x044 0x234 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044 0x234 0x640 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x044 0x234 0x4E4 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 0x044 0x234 0x5D8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x044 0x234 0x454 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x044 0x234 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x650 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x53C 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x464 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x04C 0x23C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C 0x23C 0x654 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x04C 0x23C 0x538 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 0x04C 0x23C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x23C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x04C 0x23C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x634 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x534 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x57C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x054 0x244 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054 0x244 0x658 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x054 0x244 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 0x054 0x244 0x5C8 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x054 0x244 0x580 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x054 0x244 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x058 0x248 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x058 0x248 0x4A0 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x058 0x248 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x058 0x248 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x058 0x248 0x584 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x058 0x248 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x05C 0x24C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x05C 0x24C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x05C 0x24C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x05C 0x24C 0x44C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x05C 0x24C 0x588 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x05C 0x24C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x05C 0x24C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x060 0x250 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x060 0x250 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x060 0x250 0x544 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x060 0x250 0x438 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x060 0x250 0x56C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x060 0x250 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x060 0x250 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x484 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x540 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x570 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0x068 0x258 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x068 0x258 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x068 0x258 0x4E0 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x068 0x258 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x068 0x258 0x574 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x068 0x258 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0x06C 0x25C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x06C 0x25C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x06C 0x25C 0x4DC 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x06C 0x25C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x06C 0x25C 0x578 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x06C 0x25C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x070 0x260 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x070 0x260 0x458 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x070 0x260 0x54C 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x070 0x260 0x43C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x070 0x260 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x070 0x260 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0x074 0x264 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x074 0x264 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x074 0x264 0x548 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x074 0x264 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x074 0x264 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x074 0x264 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0x078 0x268 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x078 0x268 0x45C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x078 0x268 0x554 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x078 0x268 0x448 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078 0x268 0x42C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x078 0x268 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0x07C 0x26C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x07C 0x26C 0x46C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x07C 0x26C 0x550 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x07C 0x26C 0x440 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x07C 0x26C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x07C 0x26C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0x080 0x270 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x080 0x270 0x460 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x080 0x270 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x080 0x270 0x4F0 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x080 0x270 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x080 0x270 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0x084 0x274 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x084 0x274 0x470 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x084 0x274 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x084 0x274 0x4F8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x084 0x274 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x084 0x274 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0x088 0x278 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x088 0x278 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x088 0x278 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x088 0x278 0x4F4 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x088 0x278 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x088 0x278 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0x08C 0x27C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x08C 0x27C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x08C 0x27C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x08C 0x27C 0x4EC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 0x08C 0x27C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x08C 0x27C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0x090 0x280 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x090 0x280 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x090 0x280 0x55C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x090 0x280 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 0x090 0x280 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x090 0x280 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0x094 0x284 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x094 0x284 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x094 0x284 0x558 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x094 0x284 0x3FC 0x3 0x4
-#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 0x094 0x284 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x094 0x284 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0x098 0x288 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x098 0x288 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x098 0x288 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098 0x288 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 0x098 0x288 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x098 0x288 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0x09C 0x28C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x09C 0x28C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x09C 0x28C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C 0x28C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 0x09C 0x28C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x09C 0x28C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0x0A0 0x290 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0 0x290 0x630 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x0A0 0x290 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0 0x290 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 0x0A0 0x290 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x0A0 0x290 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x0A0 0x290 0x5D4 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0x0A4 0x294 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4 0x294 0x638 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x0A4 0x294 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4 0x294 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 0x0A4 0x294 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x0A4 0x294 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x294 0x5D8 0x6 0x1
-
-#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0x0A8 0x298 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8 0x298 0x63C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x0A8 0x298 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x0A8 0x298 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 0x0A8 0x298 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x0A8 0x298 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 0x0A8 0x298 0x608 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0x0AC 0x29C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x0AC 0x29C 0x454 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x0AC 0x29C 0x564 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC 0x29C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 0x0AC 0x29C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x0AC 0x29C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x0AC 0x29C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 0x0B0 0x2A0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x0B0 0x2A0 0x464 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x0B0 0x2A0 0x560 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0 0x2A0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x2A0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x0B0 0x2A0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x0B0 0x2A0 0x5E0 0x6 0x1
-
-#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 0x0B4 0x2A4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x0B4 0x2A4 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x0B4 0x2A4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x0B4 0x2A4 0x5CC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 0x0B4 0x2A4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x0B4 0x2A4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x0B4 0x2A4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x0B8 0x2A8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x0B8 0x2A8 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x0B8 0x2A8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8 0x2A8 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 0x0B8 0x2A8 0x430 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x0B8 0x2A8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT 0x0B8 0x2A8 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x0BC 0x2AC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14 0x0BC 0x2AC 0x644 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x0BC 0x2AC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x0BC 0x2AC 0x3F8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x0BC 0x2AC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x2AC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x0BC 0x2AC 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC 0x2AC 0x510 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x0C0 0x2B0 0x484 0x0 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15 0x0C0 0x2B0 0x648 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x0C0 0x2B0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x0C0 0x2B0 0x3F4 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x0C0 0x2B0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x2B0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x0C0 0x2B0 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0 0x2B0 0x518 0x7 0x1
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x0C4 0x2B4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16 0x0C4 0x2B4 0x64C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x0C4 0x2B4 0x554 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x0C4 0x2B4 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x0C4 0x2B4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x2B4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x0C4 0x2B4 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4 0x2B4 0x514 0x7 0x1
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x0C8 0x2B8 0x450 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17 0x0C8 0x2B8 0x62C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x0C8 0x2B8 0x550 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x2B8 0x5D0 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x0C8 0x2B8 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x2B8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x0C8 0x2B8 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x0C8 0x2B8 0x50C 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x0CC 0x2BC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x0CC 0x2BC 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x0CC 0x2BC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x0CC 0x2BC 0x5C4 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC 0x2BC 0x41C 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x2BC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x0CC 0x2BC 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x0CC 0x2BC 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x0D0 0x2C0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x0D0 0x2C0 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x0D0 0x2C0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x0D0 0x2C0 0x5C0 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0 0x2C0 0x418 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x2C0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17 0x0D0 0x2C0 0x62C 0x6 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x0D0 0x2C0 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x0D4 0x2C4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x0D4 0x2C4 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x0D4 0x2C4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x0D4 0x2C4 0x5B4 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4 0x2C4 0x414 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x2C4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18 0x0D4 0x2C4 0x630 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x0D4 0x2C4 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x0D8 0x2C8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x0D8 0x2C8 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8 0x2C8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x0D8 0x2C8 0x5BC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8 0x2C8 0x410 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x2C8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19 0x0D8 0x2C8 0x654 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x0D8 0x2C8 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x0DC 0x2CC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x0DC 0x2CC 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x0DC 0x2CC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x0DC 0x2CC 0x5B8 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC 0x2CC 0x40C 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x2CC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20 0x0DC 0x2CC 0x634 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x0DC 0x2CC 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x0E0 0x2D0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x0E0 0x2D0 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x0E0 0x2D0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x0E0 0x2D0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0 0x2D0 0x408 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x2D0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21 0x0E0 0x2D0 0x658 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x0E0 0x2D0 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x0E4 0x2D4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x0E4 0x2D4 0x454 0x1 0x3
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x0E4 0x2D4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x0E4 0x2D4 0x5B0 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4 0x2D4 0x404 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x2D4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22 0x0E4 0x2D4 0x638 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x0E4 0x2D4 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8 0x2D8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x0E8 0x2D8 0x464 0x1 0x3
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 0x0E8 0x2D8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x0E8 0x2D8 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8 0x2D8 0x400 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x2D8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23 0x0E8 0x2D8 0x63C 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x0E8 0x2D8 0x444 0x7 0x1
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC 0x2DC 0x4E4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x0EC 0x2DC 0x3FC 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x0EC 0x2DC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x0EC 0x2DC 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x0EC 0x2DC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x2DC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x0EC 0x2DC 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 0x0EC 0x2DC 0x568 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0 0x2E0 0x4E8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x0F0 0x2E0 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x0F0 0x2E0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x0F0 0x2E0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x0F0 0x2E0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x2E0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x0F0 0x2E0 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x0F0 0x2E0 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x0F4 0x2E4 0x5CC 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24 0x0F4 0x2E4 0x640 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x0F4 0x2E4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x0F4 0x2E4 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x0F4 0x2E4 0x428 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x2E4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x2E4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x0F8 0x2E8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25 0x0F8 0x2E8 0x650 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x0F8 0x2E8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x0F8 0x2E8 0x444 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x0F8 0x2E8 0x420 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x2E8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x2E8 0x450 0x6 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x0F8 0x2E8 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x0FC 0x2EC 0x3F8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x0FC 0x2EC 0x57C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x0FC 0x2EC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC 0x2EC 0x4CC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x0FC 0x2EC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x2EC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x0FC 0x2EC 0x5D8 0x6 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x0FC 0x2EC 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x100 0x2F0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x100 0x2F0 0x580 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x100 0x2F0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100 0x2F0 0x4D0 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x100 0x2F0 0x3FC 0x4 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x2F0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x100 0x2F0 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x100 0x2F0 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x104 0x2F4 0x3F4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x104 0x2F4 0x584 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x104 0x2F4 0x530 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x104 0x2F4 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x104 0x2F4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x2F4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x104 0x2F4 0x5D4 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x104 0x2F4 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x108 0x2F8 0x5D0 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x108 0x2F8 0x588 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x108 0x2F8 0x52C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x108 0x2F8 0x5C8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x108 0x2F8 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x2F8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x108 0x2F8 0x5E0 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x108 0x2F8 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x10C 0x2FC 0x4C4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x10C 0x2FC 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x10C 0x2FC 0x534 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x10C 0x2FC 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C 0x2FC 0x424 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x2FC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x10C 0x2FC 0x5E8 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x10C 0x2FC 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x110 0x300 0x4C0 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x110 0x300 0x430 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x110 0x300 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x110 0x300 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x110 0x300 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x300 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x110 0x300 0x5EC 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x110 0x300 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x4BC 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x4E0 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x53C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x5F0 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x4B8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x4DC 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x538 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x5F4 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x11C 0x30C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x11C 0x30C 0x494 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x11C 0x30C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x11C 0x30C 0x3FC 0x3 0x3
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C 0x30C 0x41C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x30C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C 0x30C 0x5E4 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x11C 0x30C 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x120 0x310 0x4A4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x120 0x310 0x498 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x120 0x310 0x44C 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x120 0x310 0x58C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120 0x310 0x418 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x310 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120 0x310 0x5DC 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x120 0x310 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x124 0x314 0x4B4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x124 0x314 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x124 0x314 0x564 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x124 0x314 0x5A4 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124 0x314 0x414 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x314 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x124 0x314 0x608 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x124 0x314 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x128 0x318 0x4B0 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x128 0x318 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x128 0x318 0x560 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x128 0x318 0x590 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128 0x318 0x410 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x318 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x128 0x318 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x128 0x318 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x12C 0x31C 0x4AC 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x31C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x12C 0x31C 0x50C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x12C 0x31C 0x594 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C 0x31C 0x40C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x31C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x12C 0x31C 0x5F8 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x12C 0x31C 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 0x130 0x320 0x4A8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x320 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130 0x320 0x514 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x130 0x320 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130 0x320 0x408 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x320 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x130 0x320 0x5FC 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x130 0x320 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x134 0x324 0x4C8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x324 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x324 0x518 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x134 0x324 0x5A8 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134 0x324 0x404 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x324 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x134 0x324 0x600 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x134 0x324 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x138 0x328 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x328 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138 0x328 0x510 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x138 0x328 0x5AC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138 0x328 0x400 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x328 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x138 0x328 0x604 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x138 0x328 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x13C 0x32C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x13C 0x32C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 0x13C 0x32C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x13C 0x32C 0x51C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x13C 0x32C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 0x13C 0x32C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 0x13C 0x32C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x140 0x330 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x140 0x330 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 0x140 0x330 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x140 0x330 0x524 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x140 0x330 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 0x140 0x330 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 0x140 0x330 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x144 0x334 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x144 0x334 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x144 0x334 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x144 0x334 0x528 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x144 0x334 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 0x144 0x334 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 0x144 0x334 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x148 0x338 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x148 0x338 0x56C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x148 0x338 0x44C 0x2 0x3
-#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x148 0x338 0x520 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x148 0x338 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 0x148 0x338 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x148 0x338 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x14C 0x33C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x14C 0x33C 0x570 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x14C 0x33C 0x4D4 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 0x14C 0x33C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x14C 0x33C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 0x14C 0x33C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x14C 0x33C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x150 0x340 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x150 0x340 0x574 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x150 0x340 0x4D8 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 0x150 0x340 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x150 0x340 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 0x150 0x340 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x150 0x340 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x154 0x344 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x154 0x344 0x57C 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x154 0x344 0x478 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 0x154 0x344 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x154 0x344 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 0x154 0x344 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x154 0x344 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x158 0x348 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x158 0x348 0x580 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x158 0x348 0x488 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 0x158 0x348 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x158 0x348 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 0x158 0x348 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x158 0x348 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x15C 0x34C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x15C 0x34C 0x584 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x15C 0x34C 0x47C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 0x15C 0x34C 0x53C 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x15C 0x34C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 0x15C 0x34C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x15C 0x34C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x160 0x350 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x160 0x350 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x160 0x350 0x48C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 0x160 0x350 0x538 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x160 0x350 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 0x160 0x350 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x160 0x350 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x164 0x354 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x164 0x354 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x164 0x354 0x480 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x164 0x354 0x598 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x164 0x354 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 0x164 0x354 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x164 0x354 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x490 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x59C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x16C 0x35C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10 0x16C 0x35C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C 0x35C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x16C 0x35C 0x5A0 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x16C 0x35C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 0x16C 0x35C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x16C 0x35C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x170 0x360 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11 0x170 0x360 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170 0x360 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 0x170 0x360 0x58C 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x170 0x360 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 0x170 0x360 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x170 0x360 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x174 0x364 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12 0x174 0x364 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x174 0x364 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x174 0x364 0x5A4 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x174 0x364 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 0x174 0x364 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x174 0x364 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x590 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 0x17C 0x36C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14 0x17C 0x36C 0x644 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 0x17C 0x36C 0x544 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x17C 0x36C 0x594 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x17C 0x36C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 0x17C 0x36C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x17C 0x36C 0x454 0x6 0x4
-
-#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x180 0x370 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15 0x180 0x370 0x648 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 0x180 0x370 0x540 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x180 0x370 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x180 0x370 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 0x180 0x370 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x180 0x370 0x464 0x6 0x4
-
-#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x184 0x374 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16 0x184 0x374 0x64C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x184 0x374 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x184 0x374 0x5A8 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x184 0x374 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 0x184 0x374 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x184 0x374 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x188 0x378 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17 0x188 0x378 0x62C 0x1 0x3
-#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x188 0x378 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x188 0x378 0x5AC 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x188 0x378 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 0x188 0x378 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x188 0x378 0x484 0x6 0x3
-
-#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 0x18C 0x37C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x18C 0x37C 0x51C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 0x18C 0x37C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x18C 0x37C 0x434 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x18C 0x37C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 0x18C 0x37C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 0x190 0x380 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x190 0x380 0x524 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 0x190 0x380 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x190 0x380 0x438 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x190 0x380 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 0x190 0x380 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0x194 0x384 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x194 0x384 0x528 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0x194 0x384 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0x194 0x384 0x43C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x194 0x384 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0x194 0x384 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 0x198 0x388 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x198 0x388 0x520 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 0x198 0x388 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x198 0x388 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x198 0x388 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 0x198 0x388 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 0x19C 0x38C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x19C 0x38C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 0x19C 0x38C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x19C 0x38C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x19C 0x38C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 0x19C 0x38C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x19C 0x38C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 0x1A0 0x390 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x1A0 0x390 0x578 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 0x1A0 0x390 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 0x1A0 0x390 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x1A0 0x390 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 0x1A0 0x390 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x1A0 0x390 0x450 0x6 0x3
-
-#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 0x1A4 0x394 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x1A4 0x394 0x588 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 0x1A4 0x394 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x1A4 0x394 0x448 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x1A4 0x394 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 0x1A4 0x394 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x1A4 0x394 0x42C 0x6 0x1
-
-#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 0x1A8 0x398 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x1A8 0x398 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 0x1A8 0x398 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 0x1A8 0x398 0x440 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x1A8 0x398 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 0x1A8 0x398 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x1A8 0x398 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 0x1AC 0x39C 0x54C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x1AC 0x39C 0x424 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x1AC 0x39C 0x444 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x1AC 0x39C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 0x1AC 0x39C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1AC 0x39C 0x5D4 0x6 0x2
-
-#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 0x1B0 0x3A0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 0x1B0 0x3A0 0x548 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 0x1B0 0x3A0 0x428 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x1B0 0x3A0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x1B0 0x3A0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 0x1B0 0x3A0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 0x1B0 0x3A0 0x5D8 0x6 0x3
-
-#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 0x1B4 0x3A4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x1B4 0x3A4 0x49C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 0x1B4 0x3A4 0x420 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02 0x1B4 0x3A4 0x60C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x1B4 0x3A4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 0x1B4 0x3A4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x1B4 0x3A4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 0x1B8 0x3A8 0x430 0x0 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x1B8 0x3A8 0x4A0 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 0x1B8 0x3A8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03 0x1B8 0x3A8 0x610 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x1B8 0x3A8 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x1B8 0x3A8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x1B8 0x3A8 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC 0x3AC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x1BC 0x3AC 0x458 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC 0x3AC 0x4DC 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04 0x1BC 0x3AC 0x614 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC 0x3AC 0x4F0 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC 0x3AC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x1BC 0x3AC 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0 0x3B0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x1C0 0x3B0 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0 0x3B0 0x4E0 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05 0x1C0 0x3B0 0x618 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x1C0 0x3B0 0x4EC 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0 0x3B0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x1C0 0x3B0 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x1C4 0x3B4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x1C4 0x3B4 0x45C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x1C4 0x3B4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06 0x1C4 0x3B4 0x61C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4 0x3B4 0x4F8 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4 0x3B4 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x1C8 0x3B8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x1C8 0x3B8 0x46C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x1C8 0x3B8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07 0x1C8 0x3B8 0x620 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8 0x3B8 0x4F4 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8 0x3B8 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x1CC 0x3BC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x1CC 0x3BC 0x460 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x1CC 0x3BC 0x564 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08 0x1CC 0x3BC 0x624 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x1CC 0x3BC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC 0x3BC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x1CC 0x3BC 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x1D0 0x3C0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x1D0 0x3C0 0x470 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x1D0 0x3C0 0x560 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09 0x1D0 0x3C0 0x628 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x1D0 0x3C0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0 0x3C0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x1D0 0x3C0 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x1D4 0x3C4 0x5F4 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x1D4 0x3C4 0x4C4 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x1D4 0x3C4 0x454 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x1D4 0x3C4 0x598 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x1D4 0x3C4 0x544 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4 0x3C4 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x1D8 0x3C8 0x5F0 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x1D8 0x3C8 0x4C0 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x1D8 0x3C8 0x464 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x1D8 0x3C8 0x59C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x1D8 0x3C8 0x540 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8 0x3C8 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x1DC 0x3CC 0x5EC 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x1DC 0x3CC 0x4BC 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x1DC 0x3CC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x1DC 0x3CC 0x5A0 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x1DC 0x3CC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC 0x3CC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x1DC 0x3CC 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x1E0 0x3D0 0x5E8 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x1E0 0x3D0 0x4B8 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x1E0 0x3D0 0x484 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x1E0 0x3D0 0x58C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x1E0 0x3D0 0x44C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0 0x3D0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x1E0 0x3D0 0x3FC 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4 0x3D4 0x5DC 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x1E4 0x3D4 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4 0x3D4 0x4CC 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x1E4 0x3D4 0x5A4 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B 0x1E4 0x3D4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4 0x3D4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x1E4 0x3D4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8 0x3D8 0x5E4 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x1E8 0x3D8 0x4A4 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8 0x3D8 0x4D0 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x1E8 0x3D8 0x590 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B 0x1E8 0x3D8 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8 0x3D8 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x1EC 0x3DC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x1EC 0x3DC 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x1EC 0x3DC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x1EC 0x3DC 0x594 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x1EC 0x3DC 0x4FC 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC 0x3DC 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x1F0 0x3E0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x1F0 0x3E0 0x4C8 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x1F0 0x3E0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x1F0 0x3E0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0 0x3E0 0x500 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0 0x3E0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x1F0 0x3E0 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x1F4 0x3E4 0x5F8 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 0x1F4 0x3E4 0x4A8 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x1F4 0x3E4 0x55C 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK 0x1F4 0x3E4 0x5A8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4 0x3E4 0x508 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4 0x3E4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x1F4 0x3E4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x1F8 0x3E8 0x5FC 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x1F8 0x3E8 0x4AC 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x1F8 0x3E8 0x558 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x1F8 0x3E8 0x5AC 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8 0x3E8 0x504 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8 0x3E8 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x1FC 0x3EC 0x600 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x1FC 0x3EC 0x4B0 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x1FC 0x3EC 0x52C 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC 0x3EC 0x4D8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x1FC 0x3EC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC 0x3EC 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x200 0x3F0 0x604 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x200 0x3F0 0x4B4 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x200 0x3F0 0x530 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200 0x3F0 0x4D4 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x200 0x3F0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200 0x3F0 0x000 0x5 0x0
-
-#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */
diff --git a/arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi b/arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi
deleted file mode 100644
index b0bad0d1ba36..000000000000
--- a/arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi
+++ /dev/null
@@ -1,160 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#include "../../armv7-m.dtsi"
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/imxrt1050-clock.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- clocks {
- osc: osc {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- };
-
- osc3M: osc3M {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <3000000>;
- };
- };
-
- soc {
- lpuart1: serial@40184000 {
- compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x40184000 0x4000>;
- interrupts = <20>;
- clocks = <&clks IMXRT1050_CLK_LPUART1>;
- clock-names = "ipg";
- status = "disabled";
- };
-
- iomuxc: pinctrl@401f8000 {
- compatible = "fsl,imxrt1050-iomuxc";
- reg = <0x401f8000 0x4000>;
- fsl,mux_mask = <0x7>;
- };
-
- anatop: anatop@400d8000 {
- compatible = "fsl,imxrt-anatop";
- reg = <0x400d8000 0x4000>;
- };
-
- clks: clock-controller@400fc000 {
- compatible = "fsl,imxrt1050-ccm";
- reg = <0x400fc000 0x4000>;
- interrupts = <95>, <96>;
- clocks = <&osc>;
- clock-names = "osc";
- #clock-cells = <1>;
- assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
- <&clks IMXRT1050_CLK_PLL1_BYPASS>,
- <&clks IMXRT1050_CLK_PLL2_BYPASS>,
- <&clks IMXRT1050_CLK_PLL3_BYPASS>,
- <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
- <&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
- assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
- <&clks IMXRT1050_CLK_PLL1_ARM>,
- <&clks IMXRT1050_CLK_PLL2_SYS>,
- <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
- <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
- <&clks IMXRT1050_CLK_PLL2_SYS>;
- };
-
- edma1: dma-controller@400e8000 {
- #dma-cells = <2>;
- compatible = "fsl,imx7ulp-edma";
- reg = <0x400e8000 0x4000>,
- <0x400ec000 0x4000>;
- dma-channels = <32>;
- interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
- <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
- clock-names = "dma", "dmamux0";
- clocks = <&clks IMXRT1050_CLK_DMA>,
- <&clks IMXRT1050_CLK_DMA_MUX>;
- };
-
- usdhc1: mmc@402c0000 {
- compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
- reg = <0x402c0000 0x4000>;
- interrupts = <110>;
- clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
- <&clks IMXRT1050_CLK_AHB_PODF>,
- <&clks IMXRT1050_CLK_USDHC1>;
- clock-names = "ipg", "ahb", "per";
- bus-width = <4>;
- fsl,wp-controller;
- no-1-8-v;
- max-frequency = <200000000>;
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step = <2>;
- status = "disabled";
- };
-
- gpio1: gpio@401b8000 {
- compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
- reg = <0x401b8000 0x4000>;
- interrupts = <80>, <81>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@401bc000 {
- compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
- reg = <0x401bc000 0x4000>;
- interrupts = <82>, <83>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@401c0000 {
- compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
- reg = <0x401c0000 0x4000>;
- interrupts = <84>, <85>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@401c4000 {
- compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
- reg = <0x401c4000 0x4000>;
- interrupts = <86>, <87>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio5: gpio@400c0000 {
- compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
- reg = <0x400c0000 0x4000>;
- interrupts = <88>, <89>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpt: timer@401ec000 {
- compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
- reg = <0x401ec000 0x4000>;
- interrupts = <100>;
- clocks = <&osc3M>;
- clock-names = "per";
- };
- };
-};
diff --git a/arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h
deleted file mode 100644
index 3b9fff2f08e1..000000000000
--- a/arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h
+++ /dev/null
@@ -1,1561 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (C) 2021
- * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H
-#define _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H
-
-#define IMX_PAD_SION 0x40000000
-
-/*
- * The pin function ID is a tuple of
- * <mux_reg conf_reg input_reg mux_mode input_val>
- */
-
-#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
-#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
-#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
-#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
-#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
-#define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
-#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x004 0x044 0x0B4 0x1 0x0
-#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x004 0x044 0x0 0x2 0x0
-#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x004 0x044 0x0 0x3 0x0
-#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x004 0x044 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x004 0x044 0x0AC 0x6 0x0
-#define IOMUXC_GPIO_LPSR_01_GPIO12_IO01 0x004 0x044 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_LPSR_02_GPIO12_IO02 0x008 0x048 0x0 0xA 0x0
-#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE00 0x008 0x048 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x008 0x048 0x098 0x1 0x0
-#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x008 0x048 0x0 0x2 0x0
-#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x008 0x048 0x0 0x3 0x0
-#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x008 0x048 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE01 0x00C 0x04C 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS0 0x00C 0x04C 0x094 0x1 0x0
-#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x00C 0x04C 0x0DC 0x2 0x0
-#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x00C 0x04C 0x0 0x3 0x0
-#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x00C 0x04C 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_03_GPIO12_IO03 0x00C 0x04C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x010 0x050 0x088 0x0 0x0
-#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT 0x010 0x050 0x0A0 0x1 0x0
-#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x010 0x050 0x0D8 0x2 0x0
-#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x010 0x050 0x0 0x3 0x0
-#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x010 0x050 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x010 0x050 0x0A8 0x6 0x0
-#define IOMUXC_GPIO_LPSR_04_GPIO12_IO04 0x010 0x050 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_LPSR_05_GPIO12_IO05 0x014 0x054 0x0 0xA 0x0
-#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x014 0x054 0x084 0x0 0x0
-#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x014 0x054 0x09C 0x1 0x0
-#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x014 0x054 0x0C8 0x2 0x1
-#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x014 0x054 0x0 0x3 0x0
-#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x014 0x054 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x014 0x054 0x0A4 0x6 0x0
-#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x014 0x054 0x0C4 0x7 0x0
-
-#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x018 0x058 0x090 0x0 0x0
-#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x018 0x058 0x0D0 0x2 0x0
-#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x018 0x058 0x0B0 0x3 0x1
-#define IOMUXC_GPIO_LPSR_06_LPSPI6_PCS3 0x018 0x058 0x0 0x4 0x0
-#define IOMUXC_GPIO_LPSR_06_GPIO_MUX6_IO06 0x018 0x058 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_06_FLEXCAN3_TX 0x018 0x058 0x0 0x6 0x0
-#define IOMUXC_GPIO_LPSR_06_PIT2_TRIGGER3 0x018 0x058 0x0 0x7 0x0
-#define IOMUXC_GPIO_LPSR_06_LPSPI5_PCS1 0x018 0x058 0x0 0x8 0x0
-#define IOMUXC_GPIO_LPSR_06_GPIO12_IO06 0x018 0x058 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_LPSR_07_LPI2C6_SCL 0x01C 0x05C 0x08C 0x0 0x0
-#define IOMUXC_GPIO_LPSR_07_SAI4_RX_BCLK 0x01C 0x05C 0x0CC 0x2 0x0
-#define IOMUXC_GPIO_LPSR_07_LPUART12_RXD 0x01C 0x05C 0x0AC 0x3 0x1
-#define IOMUXC_GPIO_LPSR_07_LPSPI6_PCS2 0x01C 0x05C 0x0 0x4 0x0
-#define IOMUXC_GPIO_LPSR_07_GPIO_MUX6_IO07 0x01C 0x05C 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_07_FLEXCAN3_RX 0x01C 0x05C 0x080 0x6 0x1
-#define IOMUXC_GPIO_LPSR_07_PIT2_TRIGGER2 0x01C 0x05C 0x0 0x7 0x0
-#define IOMUXC_GPIO_LPSR_07_LPSPI5_PCS2 0x01C 0x05C 0x0 0x8 0x0
-#define IOMUXC_GPIO_LPSR_07_GPIO12_IO07 0x01C 0x05C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_LPSR_08_GPIO12_IO08 0x020 0x060 0x0 0xA 0x0
-#define IOMUXC_GPIO_LPSR_08_LPUART11_TXD 0x020 0x060 0x0A8 0x0 0x1
-#define IOMUXC_GPIO_LPSR_08_FLEXCAN3_TX 0x020 0x060 0x0 0x1 0x0
-#define IOMUXC_GPIO_LPSR_08_SAI4_RX_SYNC 0x020 0x060 0x0D4 0x2 0x0
-#define IOMUXC_GPIO_LPSR_08_MIC_CLK 0x020 0x060 0x0 0x3 0x0
-#define IOMUXC_GPIO_LPSR_08_LPSPI6_PCS1 0x020 0x060 0x0 0x4 0x0
-#define IOMUXC_GPIO_LPSR_08_GPIO_MUX6_IO08 0x020 0x060 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_08_LPI2C5_SDA 0x020 0x060 0x088 0x6 0x1
-#define IOMUXC_GPIO_LPSR_08_PIT2_TRIGGER1 0x020 0x060 0x0 0x7 0x0
-#define IOMUXC_GPIO_LPSR_08_LPSPI5_PCS3 0x020 0x060 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_LPSR_09_GPIO12_IO09 0x024 0x064 0x0 0xA 0x0
-#define IOMUXC_GPIO_LPSR_09_LPUART11_RXD 0x024 0x064 0x0A4 0x0 0x1
-#define IOMUXC_GPIO_LPSR_09_FLEXCAN3_RX 0x024 0x064 0x080 0x1 0x2
-#define IOMUXC_GPIO_LPSR_09_PIT2_TRIGGER0 0x024 0x064 0x0 0x2 0x0
-#define IOMUXC_GPIO_LPSR_09_MIC_BITSTREAM0 0x024 0x064 0x0B4 0x3 0x1
-#define IOMUXC_GPIO_LPSR_09_LPSPI6_PCS0 0x024 0x064 0x0 0x4 0x0
-#define IOMUXC_GPIO_LPSR_09_GPIO_MUX6_IO09 0x024 0x064 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_09_LPI2C5_SCL 0x024 0x064 0x084 0x6 0x1
-#define IOMUXC_GPIO_LPSR_09_SAI4_TX_DATA 0x024 0x064 0x0 0x7 0x0
-
-#define IOMUXC_GPIO_LPSR_10_GPIO12_IO10 0x028 0x068 0x0 0xA 0x0
-#define IOMUXC_GPIO_LPSR_10_JTAG_MUX_TRSTB 0x028 0x068 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_10_LPUART11_CTS_B 0x028 0x068 0x0 0x1 0x0
-#define IOMUXC_GPIO_LPSR_10_LPI2C6_SDA 0x028 0x068 0x090 0x2 0x1
-#define IOMUXC_GPIO_LPSR_10_MIC_BITSTREAM1 0x028 0x068 0x0B8 0x3 0x0
-#define IOMUXC_GPIO_LPSR_10_LPSPI6_SCK 0x028 0x068 0x0 0x4 0x0
-#define IOMUXC_GPIO_LPSR_10_GPIO_MUX6_IO10 0x028 0x068 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_10_LPI2C5_SCLS 0x028 0x068 0x0 0x6 0x0
-#define IOMUXC_GPIO_LPSR_10_SAI4_TX_SYNC 0x028 0x068 0x0DC 0x7 0x1
-#define IOMUXC_GPIO_LPSR_10_LPUART12_TXD 0x028 0x068 0x0B0 0x8 0x2
-
-#define IOMUXC_GPIO_LPSR_11_JTAG_MUX_TDO 0x02C 0x06C 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_11_LPUART11_RTS_B 0x02C 0x06C 0x0 0x1 0x0
-#define IOMUXC_GPIO_LPSR_11_LPI2C6_SCL 0x02C 0x06C 0x08C 0x2 0x1
-#define IOMUXC_GPIO_LPSR_11_MIC_BITSTREAM2 0x02C 0x06C 0x0BC 0x3 0x0
-#define IOMUXC_GPIO_LPSR_11_LPSPI6_SOUT 0x02C 0x06C 0x0 0x4 0x0
-#define IOMUXC_GPIO_LPSR_11_GPIO_MUX6_IO11 0x02C 0x06C 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_11_LPI2C5_SDAS 0x02C 0x06C 0x0 0x6 0x0
-#define IOMUXC_GPIO_LPSR_11_ARM_TRACE_SWO 0x02C 0x06C 0x0 0x7 0x0
-#define IOMUXC_GPIO_LPSR_11_LPUART12_RXD 0x02C 0x06C 0x0AC 0x8 0x2
-#define IOMUXC_GPIO_LPSR_11_GPIO12_IO11 0x02C 0x06C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_LPSR_12_GPIO12_IO12 0x030 0x070 0x0 0xA 0x0
-#define IOMUXC_GPIO_LPSR_12_JTAG_MUX_TDI 0x030 0x070 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_12_PIT2_TRIGGER0 0x030 0x070 0x0 0x1 0x0
-#define IOMUXC_GPIO_LPSR_12_MIC_BITSTREAM3 0x030 0x070 0x0C0 0x3 0x0
-#define IOMUXC_GPIO_LPSR_12_LPSPI6_SIN 0x030 0x070 0x0 0x4 0x0
-#define IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12 0x030 0x070 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_12_LPI2C5_HREQ 0x030 0x070 0x0 0x6 0x0
-#define IOMUXC_GPIO_LPSR_12_SAI4_TX_BCLK 0x030 0x070 0x0D8 0x7 0x1
-#define IOMUXC_GPIO_LPSR_12_LPSPI5_SCK 0x030 0x070 0x098 0x8 0x1
-
-#define IOMUXC_GPIO_LPSR_13_GPIO12_IO13 0x034 0x074 0x0 0xA 0x0
-#define IOMUXC_GPIO_LPSR_13_JTAG_MUX_MOD 0x034 0x074 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_13_MIC_BITSTREAM1 0x034 0x074 0x0B8 0x1 0x1
-#define IOMUXC_GPIO_LPSR_13_PIT2_TRIGGER1 0x034 0x074 0x0 0x2 0x0
-#define IOMUXC_GPIO_LPSR_13_GPIO_MUX6_IO13 0x034 0x074 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_13_SAI4_RX_DATA 0x034 0x074 0x0D0 0x7 0x1
-#define IOMUXC_GPIO_LPSR_13_LPSPI5_PCS0 0x034 0x074 0x094 0x8 0x1
-
-#define IOMUXC_GPIO_LPSR_14_JTAG_MUX_TCK 0x038 0x078 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_14_MIC_BITSTREAM2 0x038 0x078 0x0BC 0x1 0x1
-#define IOMUXC_GPIO_LPSR_14_PIT2_TRIGGER2 0x038 0x078 0x0 0x2 0x0
-#define IOMUXC_GPIO_LPSR_14_GPIO_MUX6_IO14 0x038 0x078 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_14_SAI4_RX_BCLK 0x038 0x078 0x0CC 0x7 0x1
-#define IOMUXC_GPIO_LPSR_14_LPSPI5_SOUT 0x038 0x078 0x0A0 0x8 0x1
-#define IOMUXC_GPIO_LPSR_14_GPIO12_IO14 0x038 0x078 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_LPSR_15_GPIO12_IO15 0x03C 0x07C 0x0 0xA 0x0
-#define IOMUXC_GPIO_LPSR_15_JTAG_MUX_TMS 0x03C 0x07C 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_15_MIC_BITSTREAM3 0x03C 0x07C 0x0C0 0x1 0x1
-#define IOMUXC_GPIO_LPSR_15_PIT2_TRIGGER3 0x03C 0x07C 0x0 0x2 0x0
-#define IOMUXC_GPIO_LPSR_15_GPIO_MUX6_IO15 0x03C 0x07C 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_15_SAI4_RX_SYNC 0x03C 0x07C 0x0D4 0x7 0x1
-#define IOMUXC_GPIO_LPSR_15_LPSPI5_SIN 0x03C 0x07C 0x09C 0x8 0x1
-
-#define IOMUXC_WAKEUP_DIG_GPIO13_IO00 0x40C94000 0x40C94040 0x0 0x5 0x0
-#define IOMUXC_WAKEUP_DIG_NMI_GLUE_NMI 0x40C94000 0x40C94040 0x0C4 0x7 0x1
-
-#define IOMUXC_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ 0x40C94004 0x40C94044 0x0 0x0 0x0
-#define IOMUXC_PMIC_ON_REQ_DIG_GPIO13_IO01 0x40C94004 0x40C94044 0x0 0x5 0x0
-
-#define IOMUXC_PMIC_STBY_REQ_DIG_CCM_PMIC_VSTBY_REQ 0x40C94008 0x40C94048 0x0 0x0 0x0
-#define IOMUXC_PMIC_STBY_REQ_DIG_GPIO13_IO02 0x40C94008 0x40C94048 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_00_DIG_SNVS_TAMPER0 0x40C9400C 0x40C9404C 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_00_DIG_GPIO13_IO03 0x40C9400C 0x40C9404C 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_01_DIG_SNVS_TAMPER1 0x40C94010 0x40C94050 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_01_DIG_GPIO13_IO04 0x40C94010 0x40C94050 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_02_DIG_SNVS_TAMPER2 0x40C94014 0x40C94054 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_02_DIG_GPIO13_IO05 0x40C94014 0x40C94054 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_03_DIG_SNVS_TAMPER3 0x40C94018 0x40C94058 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_03_DIG_GPIO13_IO06 0x40C94018 0x40C94058 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_04_DIG_SNVS_TAMPER4 0x40C9401C 0x40C9405C 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_04_DIG_GPIO13_IO07 0x40C9401C 0x40C9405C 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_05_DIG_SNVS_TAMPER5 0x40C94020 0x40C94060 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_05_DIG_GPIO13_IO08 0x40C94020 0x40C94060 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_06_DIG_SNVS_TAMPER6 0x40C94024 0x40C94064 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_06_DIG_GPIO13_IO09 0x40C94024 0x40C94064 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_07_DIG_SNVS_TAMPER7 0x40C94028 0x40C94068 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_07_DIG_GPIO13_IO10 0x40C94028 0x40C94068 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_08_DIG_SNVS_TAMPER8 0x40C9402C 0x40C9406C 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_08_DIG_GPIO13_IO11 0x40C9402C 0x40C9406C 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_09_DIG_SNVS_TAMPER9 0x40C94030 0x40C94070 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_09_DIG_GPIO13_IO12 0x40C94030 0x40C94070 0x0 0x5 0x0
-
-#define IOMUXC_TEST_MODE_DIG 0x0 0x40C94034 0x0 0x0 0x0
-
-#define IOMUXC_POR_B_DIG 0x0 0x40C94038 0x0 0x0 0x0
-
-#define IOMUXC_ONOFF_DIG 0x0 0x40C9403C 0x0 0x0 0x0
-
-#define IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 0x010 0x254 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A 0x010 0x254 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 0x010 0x254 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_00_FLEXIO1_D00 0x010 0x254 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 0x010 0x254 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01 0x014 0x258 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 0x014 0x258 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B 0x014 0x258 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01 0x014 0x258 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_01_FLEXIO1_D01 0x014 0x258 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 0x018 0x25C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A 0x018 0x25C 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02 0x018 0x25C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_02_FLEXIO1_D02 0x018 0x25C 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02 0x018 0x25C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 0x01C 0x260 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B 0x01C 0x260 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03 0x01C 0x260 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_03_FLEXIO1_D03 0x01C 0x260 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03 0x01C 0x260 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04 0x020 0x264 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 0x020 0x264 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A 0x020 0x264 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04 0x020 0x264 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_04_FLEXIO1_D04 0x020 0x264 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 0x024 0x268 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B 0x024 0x268 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05 0x024 0x268 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_05_FLEXIO1_D05 0x024 0x268 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05 0x024 0x268 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 0x028 0x26C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A 0x028 0x26C 0x518 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06 0x028 0x26C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_06_FLEXIO1_D06 0x028 0x26C 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06 0x028 0x26C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07 0x02C 0x270 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 0x02C 0x270 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B 0x02C 0x270 0x524 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07 0x02C 0x270 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_07_FLEXIO1_D07 0x02C 0x270 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 0x030 0x274 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A 0x030 0x274 0x51C 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08 0x030 0x274 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_08_FLEXIO1_D08 0x030 0x274 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08 0x030 0x274 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 0x034 0x278 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B 0x034 0x278 0x528 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1 0x034 0x278 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09 0x034 0x278 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_09_FLEXIO1_D09 0x034 0x278 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09 0x034 0x278 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 0x038 0x27C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A 0x038 0x27C 0x520 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2 0x038 0x27C 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10 0x038 0x27C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_10_FLEXIO1_D10 0x038 0x27C 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10 0x038 0x27C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11 0x03C 0x280 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 0x03C 0x280 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B 0x03C 0x280 0x52C 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1 0x03C 0x280 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11 0x03C 0x280 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_11_FLEXIO1_D11 0x03C 0x280 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 0x040 0x284 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_12_XBAR1_INOUT04 0x040 0x284 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2 0x040 0x284 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12 0x040 0x284 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_12_FLEXIO1_D12 0x040 0x284 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12 0x040 0x284 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 0x044 0x288 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_13_XBAR1_INOUT05 0x044 0x288 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3 0x044 0x288 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13 0x044 0x288 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_13_FLEXIO1_D13 0x044 0x288 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13 0x044 0x288 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14 0x048 0x28C 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 0x048 0x28C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_14_XBAR1_INOUT06 0x048 0x28C 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_14_GPT5_CLK 0x048 0x28C 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14 0x048 0x28C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_14_FLEXIO1_D14 0x048 0x28C 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 0x04C 0x290 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_15_XBAR1_INOUT07 0x04C 0x290 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15 0x04C 0x290 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_15_FLEXIO1_D15 0x04C 0x290 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15 0x04C 0x290 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 0x050 0x294 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_16_XBAR1_INOUT08 0x050 0x294 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16 0x050 0x294 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_16_FLEXIO1_D16 0x050 0x294 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16 0x050 0x294 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17 0x054 0x298 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 0x054 0x298 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A 0x054 0x298 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_17_TMR1_TIMER0 0x054 0x298 0x63C 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17 0x054 0x298 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_17_FLEXIO1_D17 0x054 0x298 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 0x058 0x29C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B 0x058 0x29C 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_18_TMR2_TIMER0 0x058 0x29C 0x648 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18 0x058 0x29C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_18_FLEXIO1_D18 0x058 0x29C 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18 0x058 0x29C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 0x05C 0x2A0 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A 0x05C 0x2A0 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_19_TMR3_TIMER0 0x05C 0x2A0 0x654 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19 0x05C 0x2A0 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_19_FLEXIO1_D19 0x05C 0x2A0 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19 0x05C 0x2A0 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 0x060 0x2A4 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B 0x060 0x2A4 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_20_TMR4_TIMER0 0x060 0x2A4 0x660 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20 0x060 0x2A4 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_20_FLEXIO1_D20 0x060 0x2A4 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20 0x060 0x2A4 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21 0x064 0x2A8 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 0x064 0x2A8 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A 0x064 0x2A8 0x53C 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21 0x064 0x2A8 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_21_FLEXIO1_D21 0x064 0x2A8 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22 0x068 0x2AC 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 0x068 0x2AC 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B 0x068 0x2AC 0x54C 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22 0x068 0x2AC 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_22_FLEXIO1_D22 0x068 0x2AC 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 0x06C 0x2B0 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A 0x06C 0x2B0 0x500 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23 0x06C 0x2B0 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_23_FLEXIO1_D23 0x06C 0x2B0 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23 0x06C 0x2B0 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24 0x070 0x2B4 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_24_SEMC_CAS 0x070 0x2B4 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B 0x070 0x2B4 0x50C 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24 0x070 0x2B4 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_24_FLEXIO1_D24 0x070 0x2B4 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25 0x074 0x2B8 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_25_SEMC_RAS 0x074 0x2B8 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A 0x074 0x2B8 0x504 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25 0x074 0x2B8 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_25_FLEXIO1_D25 0x074 0x2B8 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_26_SEMC_CLK 0x078 0x2BC 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B 0x078 0x2BC 0x510 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26 0x078 0x2BC 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_26_FLEXIO1_D26 0x078 0x2BC 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26 0x078 0x2BC 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27 0x07C 0x2C0 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_27_SEMC_CKE 0x07C 0x2C0 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A 0x07C 0x2C0 0x508 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27 0x07C 0x2C0 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_27_FLEXIO1_D27 0x07C 0x2C0 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28 0x080 0x2C4 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_28_SEMC_WE 0x080 0x2C4 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B 0x080 0x2C4 0x514 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28 0x080 0x2C4 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_28_FLEXIO1_D28 0x080 0x2C4 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 0x084 0x2C8 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A 0x084 0x2C8 0x530 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29 0x084 0x2C8 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_29_FLEXIO1_D29 0x084 0x2C8 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29 0x084 0x2C8 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 0x088 0x2CC 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B 0x088 0x2CC 0x540 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30 0x088 0x2CC 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_30_FLEXIO1_D30 0x088 0x2CC 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30 0x088 0x2CC 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31 0x08C 0x2D0 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 0x08C 0x2D0 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A 0x08C 0x2D0 0x534 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31 0x08C 0x2D0 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_31_FLEXIO1_D31 0x08C 0x2D0 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00 0x090 0x2D4 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 0x090 0x2D4 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B 0x090 0x2D4 0x544 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00 0x090 0x2D4 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 0x094 0x2D8 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A 0x094 0x2D8 0x538 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01 0x094 0x2D8 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01 0x094 0x2D8 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02 0x098 0x2DC 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 0x098 0x2DC 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B 0x098 0x2DC 0x548 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02 0x098 0x2DC 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03 0x09C 0x2E0 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 0x09C 0x2E0 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_35_XBAR1_INOUT09 0x09C 0x2E0 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03 0x09C 0x2E0 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 0x0A0 0x2E4 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_36_XBAR1_INOUT10 0x0A0 0x2E4 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04 0x0A0 0x2E4 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04 0x0A0 0x2E4 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05 0x0A4 0x2E8 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 0x0A4 0x2E8 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_37_XBAR1_INOUT11 0x0A4 0x2E8 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05 0x0A4 0x2E8 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06 0x0A8 0x2EC 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 0x0A8 0x2EC 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A 0x0A8 0x2EC 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_38_TMR1_TIMER1 0x0A8 0x2EC 0x640 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06 0x0A8 0x2EC 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_EMC_B1_39_SEMC_DQS 0x0AC 0x2F0 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B 0x0AC 0x2F0 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_39_TMR2_TIMER1 0x0AC 0x2F0 0x64C 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07 0x0AC 0x2F0 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07 0x0AC 0x2F0 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_40_SEMC_RDY 0x0B0 0x2F4 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_40_XBAR1_INOUT12 0x0B0 0x2F4 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT 0x0B0 0x2F4 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_40_LPUART6_TXD 0x0B0 0x2F4 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08 0x0B0 0x2F4 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC 0x0B0 0x2F4 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1 0x0B0 0x2F4 0x0 0x9 0x0
-#define IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08 0x0B0 0x2F4 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09 0x0B4 0x2F8 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00 0x0B4 0x2F8 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_41_XBAR1_INOUT13 0x0B4 0x2F8 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_41_MQS_LEFT 0x0B4 0x2F8 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_41_LPUART6_RXD 0x0B4 0x2F8 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 0x0B4 0x2F8 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09 0x0B4 0x2F8 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO 0x0B4 0x2F8 0x4C8 0x7 0x0
-#define IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2 0x0B4 0x2F8 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 0x0B8 0x2FC 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M 0x0B8 0x2FC 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_00_TMR3_TIMER1 0x0B8 0x2FC 0x658 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B 0x0B8 0x2FC 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 0x0B8 0x2FC 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10 0x0B8 0x2FC 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_00_XBAR1_INOUT20 0x0B8 0x2FC 0x6D8 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_00_ENET_QOS_1588_EVENT1_OUT 0x0B8 0x2FC 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK 0x0B8 0x2FC 0x5D0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL 0x0B8 0x2FC 0x5B4 0x9 0x0
-#define IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10 0x0B8 0x2FC 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A 0x0B8 0x2FC 0x530 0xB 0x1
-
-#define IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 0x0BC 0x300 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B 0x0BC 0x300 0x6D0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_01_TMR4_TIMER1 0x0BC 0x300 0x664 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B 0x0BC 0x300 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 0x0BC 0x300 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11 0x0BC 0x300 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_01_XBAR1_INOUT21 0x0BC 0x300 0x6DC 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_01_ENET_QOS_1588_EVENT1_IN 0x0BC 0x300 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0 0x0BC 0x300 0x5CC 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA 0x0BC 0x300 0x5B8 0x9 0x0
-#define IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11 0x0BC 0x300 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B 0x0BC 0x300 0x540 0xB 0x1
-
-#define IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 0x0C0 0x304 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_02_USDHC2_WP 0x0C0 0x304 0x6D4 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_02_VIDEO_MUX_CSI_DATA23 0x0C0 0x304 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 0x0C0 0x304 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12 0x0C0 0x304 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_02_XBAR1_INOUT22 0x0C0 0x304 0x6E0 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_02_ENET_QOS_1588_EVENT1_AUX_IN 0x0C0 0x304 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_02_LPSPI1_SOUT 0x0C0 0x304 0x5D8 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12 0x0C0 0x304 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A 0x0C0 0x304 0x534 0xB 0x1
-
-#define IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 0x0C4 0x308 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT 0x0C4 0x308 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_03_VIDEO_MUX_CSI_DATA22 0x0C4 0x308 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 0x0C4 0x308 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13 0x0C4 0x308 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_03_XBAR1_INOUT23 0x0C4 0x308 0x6E4 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_03_ENET_1G_TX_DATA03 0x0C4 0x308 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_03_LPSPI1_SIN 0x0C4 0x308 0x5D4 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13 0x0C4 0x308 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B 0x0C4 0x308 0x544 0xB 0x1
-
-#define IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 0x0C8 0x30C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B 0x0C8 0x30C 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK 0x0C8 0x30C 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_04_VIDEO_MUX_CSI_DATA21 0x0C8 0x30C 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 0x0C8 0x30C 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14 0x0C8 0x30C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_04_XBAR1_INOUT24 0x0C8 0x30C 0x6E8 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_04_ENET_1G_TX_DATA02 0x0C8 0x30C 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK 0x0C8 0x30C 0x600 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14 0x0C8 0x30C 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A 0x0C8 0x30C 0x538 0xB 0x1
-
-#define IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 0x0CC 0x310 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_05_GPT3_CLK 0x0CC 0x310 0x598 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC 0x0CC 0x310 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_05_VIDEO_MUX_CSI_DATA20 0x0CC 0x310 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 0x0CC 0x310 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15 0x0CC 0x310 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_05_XBAR1_INOUT25 0x0CC 0x310 0x6EC 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK 0x0CC 0x310 0x4CC 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0 0x0CC 0x310 0x5F0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER0 0x0CC 0x310 0x0 0x9 0x0
-#define IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15 0x0CC 0x310 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B 0x0CC 0x310 0x548 0xB 0x1
-
-#define IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 0x0D0 0x314 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1 0x0D0 0x314 0x590 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16 0x0D0 0x314 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK 0x0D0 0x314 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A 0x0D0 0x314 0x53C 0xB 0x1
-#define IOMUXC_GPIO_EMC_B2_06_VIDEO_MUX_CSI_DATA19 0x0D0 0x314 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 0x0D0 0x314 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16 0x0D0 0x314 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_06_XBAR1_INOUT26 0x0D0 0x314 0x6F0 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER 0x0D0 0x314 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_06_LPSPI3_SOUT 0x0D0 0x314 0x608 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER1 0x0D0 0x314 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 0x0D4 0x318 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2 0x0D4 0x318 0x594 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA 0x0D4 0x318 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_07_VIDEO_MUX_CSI_DATA18 0x0D4 0x318 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS 0x0D4 0x318 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17 0x0D4 0x318 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_07_XBAR1_INOUT27 0x0D4 0x318 0x6F4 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_07_ENET_1G_RX_DATA03 0x0D4 0x318 0x4DC 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_07_LPSPI3_SIN 0x0D4 0x318 0x604 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER2 0x0D4 0x318 0x0 0x9 0x0
-#define IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17 0x0D4 0x318 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B 0x0D4 0x318 0x54C 0xB 0x1
-
-#define IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 0x0D8 0x31C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1 0x0D8 0x31C 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA 0x0D8 0x31C 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_08_VIDEO_MUX_CSI_DATA17 0x0D8 0x31C 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B 0x0D8 0x31C 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18 0x0D8 0x31C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_08_XBAR1_INOUT28 0x0D8 0x31C 0x6F8 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_08_ENET_1G_RX_DATA02 0x0D8 0x31C 0x4D8 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1 0x0D8 0x31C 0x5F4 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER3 0x0D8 0x31C 0x0 0x9 0x0
-#define IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18 0x0D8 0x31C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19 0x0DC 0x320 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 0x0DC 0x320 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2 0x0DC 0x320 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK 0x0DC 0x320 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_09_VIDEO_MUX_CSI_DATA16 0x0DC 0x320 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK 0x0DC 0x320 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19 0x0DC 0x320 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_09_XBAR1_INOUT29 0x0DC 0x320 0x6FC 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS 0x0DC 0x320 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2 0x0DC 0x320 0x5F8 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_09_TMR1_TIMER0 0x0DC 0x320 0x63C 0x9 0x1
-
-#define IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20 0x0E0 0x324 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 0x0E0 0x324 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3 0x0E0 0x324 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC 0x0E0 0x324 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_10_VIDEO_MUX_CSI_FIELD 0x0E0 0x324 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK 0x0E0 0x324 0x58C 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20 0x0E0 0x324 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_10_XBAR1_INOUT30 0x0E0 0x324 0x700 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL 0x0E0 0x324 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3 0x0E0 0x324 0x5FC 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_10_TMR1_TIMER1 0x0E0 0x324 0x640 0x9 0x1
-
-#define IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 0x0E4 0x328 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_11_SPDIF_IN 0x0E4 0x328 0x6B4 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_11_ENET_1G_TX_DATA00 0x0E4 0x328 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC 0x0E4 0x328 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B 0x0E4 0x328 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21 0x0E4 0x328 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_11_XBAR1_INOUT31 0x0E4 0x328 0x704 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_11_EMVSIM1_IO 0x0E4 0x328 0x69C 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_11_TMR1_TIMER2 0x0E4 0x328 0x644 0x9 0x0
-#define IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21 0x0E4 0x328 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 0x0E8 0x32C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT 0x0E8 0x32C 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_12_ENET_1G_TX_DATA01 0x0E8 0x32C 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK 0x0E8 0x32C 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS 0x0E8 0x32C 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22 0x0E8 0x32C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_12_XBAR1_INOUT32 0x0E8 0x32C 0x708 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_12_EMVSIM1_CLK 0x0E8 0x32C 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_12_TMR1_TIMER3 0x0E8 0x32C 0x0 0x9 0x0
-#define IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22 0x0E8 0x32C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23 0x0EC 0x330 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 0x0EC 0x330 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN 0x0EC 0x330 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA 0x0EC 0x330 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 0x0EC 0x330 0x57C 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23 0x0EC 0x330 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_13_XBAR1_INOUT33 0x0EC 0x330 0x70C 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_13_EMVSIM1_RST 0x0EC 0x330 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_13_TMR2_TIMER0 0x0EC 0x330 0x648 0x9 0x1
-
-#define IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 0x0F0 0x334 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO 0x0F0 0x334 0x4E8 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA 0x0F0 0x334 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 0x0F0 0x334 0x580 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24 0x0F0 0x334 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_14_XBAR1_INOUT34 0x0F0 0x334 0x710 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_14_SFA_ipp_do_atx_clk_under_test 0x0F0 0x334 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_14_EMVSIM1_SVEN 0x0F0 0x334 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_14_TMR2_TIMER1 0x0F0 0x334 0x64C 0x9 0x1
-#define IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24 0x0F0 0x334 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 0x0F4 0x338 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_15_ENET_1G_RX_DATA00 0x0F4 0x338 0x4D0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK 0x0F4 0x338 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 0x0F4 0x338 0x584 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25 0x0F4 0x338 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_15_XBAR1_INOUT35 0x0F4 0x338 0x714 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_15_EMVSIM1_PD 0x0F4 0x338 0x6A0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_15_TMR2_TIMER2 0x0F4 0x338 0x650 0x9 0x0
-#define IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25 0x0F4 0x338 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26 0x0F8 0x33C 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 0x0F8 0x33C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_16_XBAR1_INOUT14 0x0F8 0x33C 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_16_ENET_1G_RX_DATA01 0x0F8 0x33C 0x4D4 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC 0x0F8 0x33C 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 0x0F8 0x33C 0x588 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26 0x0F8 0x33C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_16_EMVSIM1_POWER_FAIL 0x0F8 0x33C 0x6A4 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_16_TMR2_TIMER3 0x0F8 0x33C 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 0x0FC 0x340 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_17_XBAR1_INOUT15 0x0FC 0x340 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN 0x0FC 0x340 0x4E0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK 0x0FC 0x340 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 0x0FC 0x340 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27 0x0FC 0x340 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_17_WDOG1_ANY 0x0FC 0x340 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_17_TMR3_TIMER0 0x0FC 0x340 0x654 0x9 0x1
-#define IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27 0x0FC 0x340 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 0x100 0x344 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_18_XBAR1_INOUT16 0x100 0x344 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER 0x100 0x344 0x4E4 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_18_EWM_OUT_B 0x100 0x344 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 0x100 0x344 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28 0x100 0x344 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS 0x100 0x344 0x550 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_18_WDOG1_B 0x100 0x344 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_18_TMR3_TIMER1 0x100 0x344 0x658 0x9 0x1
-#define IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28 0x100 0x344 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29 0x104 0x348 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 0x104 0x348 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_19_ENET_MDC 0x104 0x348 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC 0x104 0x348 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK 0x104 0x348 0x4C4 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 0x104 0x348 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 0x104 0x348 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_19_ENET_QOS_MDC 0x104 0x348 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_19_TMR3_TIMER2 0x104 0x348 0x65C 0x9 0x0
-
-#define IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30 0x108 0x34C 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 0x108 0x34C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_20_ENET_MDIO 0x108 0x34C 0x4AC 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO 0x108 0x34C 0x4C8 0x2 0x1
-#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_REF_CLK 0x108 0x34C 0x4A0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 0x108 0x34C 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 0x108 0x34C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_MDIO 0x108 0x34C 0x4EC 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_20_TMR3_TIMER3 0x108 0x34C 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_AD_00_GPIO8_IO31 0x10C 0x350 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_00_EMVSIM1_IO 0x10C 0x350 0x69C 0x0 0x1
-#define IOMUXC_GPIO_AD_00_FLEXCAN2_TX 0x10C 0x350 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN 0x10C 0x350 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_00_GPT2_CAPTURE1 0x10C 0x350 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A 0x10C 0x350 0x500 0x4 0x1
-#define IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31 0x10C 0x350 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_00_LPUART7_TXD 0x10C 0x350 0x630 0x6 0x0
-#define IOMUXC_GPIO_AD_00_FLEXIO2_D00 0x10C 0x350 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B 0x10C 0x350 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_AD_01_GPIO9_IO00 0x110 0x354 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_01_EMVSIM1_CLK 0x110 0x354 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_01_FLEXCAN2_RX 0x110 0x354 0x49C 0x1 0x0
-#define IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT 0x110 0x354 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_01_GPT2_CAPTURE2 0x110 0x354 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B 0x110 0x354 0x50C 0x4 0x1
-#define IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00 0x110 0x354 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_01_LPUART7_RXD 0x110 0x354 0x62C 0x6 0x0
-#define IOMUXC_GPIO_AD_01_FLEXIO2_D01 0x110 0x354 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B 0x110 0x354 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_AD_02_GPIO9_IO01 0x114 0x358 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_02_EMVSIM1_RST 0x114 0x358 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_02_LPUART7_CTS_B 0x114 0x358 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN 0x114 0x358 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_02_GPT2_COMPARE1 0x114 0x358 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A 0x114 0x358 0x504 0x4 0x1
-#define IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01 0x114 0x358 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_02_LPUART8_TXD 0x114 0x358 0x638 0x6 0x0
-#define IOMUXC_GPIO_AD_02_FLEXIO2_D02 0x114 0x358 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 0x114 0x358 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_AD_03_GPIO9_IO02 0x118 0x35C 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_03_EMVSIM1_SVEN 0x118 0x35C 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_03_LPUART7_RTS_B 0x118 0x35C 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT 0x118 0x35C 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_03_GPT2_COMPARE2 0x118 0x35C 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B 0x118 0x35C 0x510 0x4 0x1
-#define IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02 0x118 0x35C 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_03_LPUART8_RXD 0x118 0x35C 0x634 0x6 0x0
-#define IOMUXC_GPIO_AD_03_FLEXIO2_D03 0x118 0x35C 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 0x118 0x35C 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_AD_04_EMVSIM1_PD 0x11C 0x360 0x6A0 0x0 0x1
-#define IOMUXC_GPIO_AD_04_LPUART8_CTS_B 0x11C 0x360 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN 0x11C 0x360 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_04_GPT2_COMPARE3 0x11C 0x360 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A 0x11C 0x360 0x508 0x4 0x1
-#define IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03 0x11C 0x360 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_04_WDOG1_B 0x11C 0x360 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_04_FLEXIO2_D04 0x11C 0x360 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_04_TMR4_TIMER0 0x11C 0x360 0x660 0x9 0x1
-#define IOMUXC_GPIO_AD_04_GPIO9_IO03 0x11C 0x360 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_AD_05_EMVSIM1_POWER_FAIL 0x120 0x364 0x6A4 0x0 0x1
-#define IOMUXC_GPIO_AD_05_LPUART8_RTS_B 0x120 0x364 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT 0x120 0x364 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_05_GPT2_CLK 0x120 0x364 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B 0x120 0x364 0x514 0x4 0x1
-#define IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04 0x120 0x364 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_05_WDOG2_B 0x120 0x364 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_05_FLEXIO2_D05 0x120 0x364 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_05_TMR4_TIMER1 0x120 0x364 0x664 0x9 0x1
-#define IOMUXC_GPIO_AD_05_GPIO9_IO04 0x120 0x364 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_AD_06_USB_OTG2_OC 0x124 0x368 0x6B8 0x0 0x0
-#define IOMUXC_GPIO_AD_06_FLEXCAN1_TX 0x124 0x368 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_06_EMVSIM2_IO 0x124 0x368 0x6A8 0x2 0x0
-#define IOMUXC_GPIO_AD_06_GPT3_CAPTURE1 0x124 0x368 0x590 0x3 0x1
-#define IOMUXC_GPIO_AD_06_VIDEO_MUX_CSI_DATA15 0x124 0x368 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05 0x124 0x368 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN 0x124 0x368 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_06_FLEXIO2_D06 0x124 0x368 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_06_TMR4_TIMER2 0x124 0x368 0x668 0x9 0x0
-#define IOMUXC_GPIO_AD_06_GPIO9_IO05 0x124 0x368 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X 0x124 0x368 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_07_USB_OTG2_PWR 0x128 0x36C 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_07_FLEXCAN1_RX 0x128 0x36C 0x498 0x1 0x0
-#define IOMUXC_GPIO_AD_07_EMVSIM2_CLK 0x128 0x36C 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_07_GPT3_CAPTURE2 0x128 0x36C 0x594 0x3 0x1
-#define IOMUXC_GPIO_AD_07_VIDEO_MUX_CSI_DATA14 0x128 0x36C 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06 0x128 0x36C 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT 0x128 0x36C 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_07_FLEXIO2_D07 0x128 0x36C 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_07_TMR4_TIMER3 0x128 0x36C 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_07_GPIO9_IO06 0x128 0x36C 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X 0x128 0x36C 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID 0x12C 0x370 0x6C4 0x0 0x0
-#define IOMUXC_GPIO_AD_08_LPI2C1_SCL 0x12C 0x370 0x5AC 0x1 0x0
-#define IOMUXC_GPIO_AD_08_EMVSIM2_RST 0x12C 0x370 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_08_GPT3_COMPARE1 0x12C 0x370 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_08_VIDEO_MUX_CSI_DATA13 0x12C 0x370 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07 0x12C 0x370 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN 0x12C 0x370 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_08_FLEXIO2_D08 0x12C 0x370 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_08_GPIO9_IO07 0x12C 0x370 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X 0x12C 0x370 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID 0x130 0x374 0x6C0 0x0 0x0
-#define IOMUXC_GPIO_AD_09_LPI2C1_SDA 0x130 0x374 0x5B0 0x1 0x0
-#define IOMUXC_GPIO_AD_09_EMVSIM2_SVEN 0x130 0x374 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_09_GPT3_COMPARE2 0x130 0x374 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_09_VIDEO_MUX_CSI_DATA12 0x130 0x374 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08 0x130 0x374 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT 0x130 0x374 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_09_FLEXIO2_D09 0x130 0x374 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_09_GPIO9_IO08 0x130 0x374 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X 0x130 0x374 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_10_USB_OTG1_PWR 0x134 0x378 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_10_LPI2C1_SCLS 0x134 0x378 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_10_EMVSIM2_PD 0x134 0x378 0x6AC 0x2 0x0
-#define IOMUXC_GPIO_AD_10_GPT3_COMPARE3 0x134 0x378 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_10_VIDEO_MUX_CSI_DATA11 0x134 0x378 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09 0x134 0x378 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN 0x134 0x378 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_10_FLEXIO2_D10 0x134 0x378 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_10_GPIO9_IO09 0x134 0x378 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X 0x134 0x378 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_11_USB_OTG1_OC 0x138 0x37C 0x6BC 0x0 0x0
-#define IOMUXC_GPIO_AD_11_LPI2C1_SDAS 0x138 0x37C 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_11_EMVSIM2_POWER_FAIL 0x138 0x37C 0x6B0 0x2 0x0
-#define IOMUXC_GPIO_AD_11_GPT3_CLK 0x138 0x37C 0x598 0x3 0x1
-#define IOMUXC_GPIO_AD_11_VIDEO_MUX_CSI_DATA10 0x138 0x37C 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10 0x138 0x37C 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT 0x138 0x37C 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_11_FLEXIO2_D11 0x138 0x37C 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_11_GPIO9_IO10 0x138 0x37C 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X 0x138 0x37C 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_12_SPDIF_LOCK 0x13C 0x380 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_12_LPI2C1_HREQ 0x13C 0x380 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_12_GPT1_CAPTURE1 0x13C 0x380 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03 0x13C 0x380 0x570 0x3 0x0
-#define IOMUXC_GPIO_AD_12_VIDEO_MUX_CSI_PIXCLK 0x13C 0x380 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11 0x13C 0x380 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_12_ENET_TX_DATA03 0x13C 0x380 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_12_FLEXIO2_D12 0x13C 0x380 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_12_EWM_OUT_B 0x13C 0x380 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_12_GPIO9_IO11 0x13C 0x380 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X 0x13C 0x380 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_13_SPDIF_SR_CLK 0x140 0x384 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_13_PIT1_TRIGGER0 0x140 0x384 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_13_GPT1_CAPTURE2 0x140 0x384 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02 0x140 0x384 0x56C 0x3 0x0
-#define IOMUXC_GPIO_AD_13_VIDEO_MUX_CSI_MCLK 0x140 0x384 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12 0x140 0x384 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_13_ENET_TX_DATA02 0x140 0x384 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_13_FLEXIO2_D13 0x140 0x384 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_13_REF_CLK_32K 0x140 0x384 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_13_GPIO9_IO12 0x140 0x384 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X 0x140 0x384 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK 0x144 0x388 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_14_REF_CLK_24M 0x144 0x388 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_14_GPT1_COMPARE1 0x144 0x388 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01 0x144 0x388 0x568 0x3 0x0
-#define IOMUXC_GPIO_AD_14_VIDEO_MUX_CSI_VSYNC 0x144 0x388 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13 0x144 0x388 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_14_ENET_RX_CLK 0x144 0x388 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_14_FLEXIO2_D14 0x144 0x388 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M 0x144 0x388 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_14_GPIO9_IO13 0x144 0x388 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X 0x144 0x388 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_15_GPIO9_IO14 0x148 0x38C 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X 0x148 0x38C 0x0 0xB 0x0
-#define IOMUXC_GPIO_AD_15_SPDIF_IN 0x148 0x38C 0x6B4 0x0 0x1
-#define IOMUXC_GPIO_AD_15_LPUART10_TXD 0x148 0x38C 0x628 0x1 0x0
-#define IOMUXC_GPIO_AD_15_GPT1_COMPARE2 0x148 0x38C 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00 0x148 0x38C 0x564 0x3 0x0
-#define IOMUXC_GPIO_AD_15_VIDEO_MUX_CSI_HSYNC 0x148 0x38C 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14 0x148 0x38C 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_15_ENET_TX_ER 0x148 0x38C 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_15_FLEXIO2_D15 0x148 0x38C 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_AD_16_SPDIF_OUT 0x14C 0x390 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_16_LPUART10_RXD 0x14C 0x390 0x624 0x1 0x0
-#define IOMUXC_GPIO_AD_16_GPT1_COMPARE3 0x14C 0x390 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK 0x14C 0x390 0x578 0x3 0x0
-#define IOMUXC_GPIO_AD_16_VIDEO_MUX_CSI_DATA09 0x14C 0x390 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15 0x14C 0x390 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_16_ENET_RX_DATA03 0x14C 0x390 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_16_FLEXIO2_D16 0x14C 0x390 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_16_ENET_1G_MDC 0x14C 0x390 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_16_GPIO9_IO15 0x14C 0x390 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X 0x14C 0x390 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_17_SAI1_MCLK 0x150 0x394 0x66C 0x0 0x0
-#define IOMUXC_GPIO_AD_17_ACMP1_OUT 0x150 0x394 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_17_GPT1_CLK 0x150 0x394 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS 0x150 0x394 0x550 0x3 0x1
-#define IOMUXC_GPIO_AD_17_VIDEO_MUX_CSI_DATA08 0x150 0x394 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16 0x150 0x394 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_17_ENET_RX_DATA02 0x150 0x394 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_17_FLEXIO2_D17 0x150 0x394 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_17_ENET_1G_MDIO 0x150 0x394 0x4C8 0x9 0x2
-#define IOMUXC_GPIO_AD_17_GPIO9_IO16 0x150 0x394 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X 0x150 0x394 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_18_GPIO9_IO17 0x154 0x398 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X 0x154 0x398 0x0 0xB 0x0
-#define IOMUXC_GPIO_AD_18_SAI1_RX_SYNC 0x154 0x398 0x678 0x0 0x0
-#define IOMUXC_GPIO_AD_18_ACMP2_OUT 0x154 0x398 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_18_LPSPI1_PCS1 0x154 0x398 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B 0x154 0x398 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_18_VIDEO_MUX_CSI_DATA07 0x154 0x398 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17 0x154 0x398 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_18_ENET_CRS 0x154 0x398 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_18_FLEXIO2_D18 0x154 0x398 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_18_LPI2C2_SCL 0x154 0x398 0x5B4 0x9 0x1
-
-#define IOMUXC_GPIO_AD_19_SAI1_RX_BCLK 0x158 0x39C 0x670 0x0 0x0
-#define IOMUXC_GPIO_AD_19_ACMP3_OUT 0x158 0x39C 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_19_LPSPI1_PCS2 0x158 0x39C 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK 0x158 0x39C 0x574 0x3 0x0
-#define IOMUXC_GPIO_AD_19_VIDEO_MUX_CSI_DATA06 0x158 0x39C 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18 0x158 0x39C 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_19_ENET_COL 0x158 0x39C 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_19_FLEXIO2_D19 0x158 0x39C 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_19_LPI2C2_SDA 0x158 0x39C 0x5B8 0x9 0x1
-#define IOMUXC_GPIO_AD_19_GPIO9_IO18 0x158 0x39C 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X 0x158 0x39C 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 0x15C 0x3A0 0x674 0x0 0x0
-#define IOMUXC_GPIO_AD_20_ACMP4_OUT 0x15C 0x3A0 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_20_LPSPI1_PCS3 0x15C 0x3A0 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00 0x15C 0x3A0 0x554 0x3 0x0
-#define IOMUXC_GPIO_AD_20_VIDEO_MUX_CSI_DATA05 0x15C 0x3A0 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19 0x15C 0x3A0 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_20_KPP_ROW07 0x15C 0x3A0 0x5A8 0x6 0x0
-#define IOMUXC_GPIO_AD_20_FLEXIO2_D20 0x15C 0x3A0 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_20_ENET_QOS_1588_EVENT2_OUT 0x15C 0x3A0 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_20_GPIO9_IO19 0x15C 0x3A0 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X 0x15C 0x3A0 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 0x160 0x3A4 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_21_LPSPI2_PCS1 0x160 0x3A4 0x5E0 0x2 0x0
-#define IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01 0x160 0x3A4 0x558 0x3 0x0
-#define IOMUXC_GPIO_AD_21_VIDEO_MUX_CSI_DATA04 0x160 0x3A4 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20 0x160 0x3A4 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_21_KPP_COL07 0x160 0x3A4 0x5A0 0x6 0x0
-#define IOMUXC_GPIO_AD_21_FLEXIO2_D21 0x160 0x3A4 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_21_ENET_QOS_1588_EVENT2_IN 0x160 0x3A4 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_21_GPIO9_IO20 0x160 0x3A4 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X 0x160 0x3A4 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_22_GPIO9_IO21 0x164 0x3A8 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_22_SAI1_TX_BCLK 0x164 0x3A8 0x67C 0x0 0x0
-#define IOMUXC_GPIO_AD_22_LPSPI2_PCS2 0x164 0x3A8 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02 0x164 0x3A8 0x55C 0x3 0x0
-#define IOMUXC_GPIO_AD_22_VIDEO_MUX_CSI_DATA03 0x164 0x3A8 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21 0x164 0x3A8 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_22_KPP_ROW06 0x164 0x3A8 0x5A4 0x6 0x0
-#define IOMUXC_GPIO_AD_22_FLEXIO2_D22 0x164 0x3A8 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_22_ENET_QOS_1588_EVENT3_OUT 0x164 0x3A8 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_AD_23_SAI1_TX_SYNC 0x168 0x3AC 0x680 0x0 0x0
-#define IOMUXC_GPIO_AD_23_LPSPI2_PCS3 0x168 0x3AC 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03 0x168 0x3AC 0x560 0x3 0x0
-#define IOMUXC_GPIO_AD_23_VIDEO_MUX_CSI_DATA02 0x168 0x3AC 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22 0x168 0x3AC 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_23_KPP_COL06 0x168 0x3AC 0x59C 0x6 0x0
-#define IOMUXC_GPIO_AD_23_FLEXIO2_D23 0x168 0x3AC 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_23_ENET_QOS_1588_EVENT3_IN 0x168 0x3AC 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_23_GPIO9_IO22 0x168 0x3AC 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_AD_24_LPUART1_TXD 0x16C 0x3B0 0x620 0x0 0x0
-#define IOMUXC_GPIO_AD_24_LPSPI2_SCK 0x16C 0x3B0 0x5E4 0x1 0x0
-#define IOMUXC_GPIO_AD_24_VIDEO_MUX_CSI_DATA00 0x16C 0x3B0 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_24_ENET_RX_EN 0x16C 0x3B0 0x4B8 0x3 0x0
-#define IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A 0x16C 0x3B0 0x518 0x4 0x1
-#define IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23 0x16C 0x3B0 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_24_KPP_ROW05 0x16C 0x3B0 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_24_FLEXIO2_D24 0x16C 0x3B0 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_24_LPI2C4_SCL 0x16C 0x3B0 0x5C4 0x9 0x0
-#define IOMUXC_GPIO_AD_24_GPIO9_IO23 0x16C 0x3B0 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_AD_25_GPIO9_IO24 0x170 0x3B4 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_25_LPUART1_RXD 0x170 0x3B4 0x61C 0x0 0x0
-#define IOMUXC_GPIO_AD_25_LPSPI2_PCS0 0x170 0x3B4 0x5DC 0x1 0x0
-#define IOMUXC_GPIO_AD_25_VIDEO_MUX_CSI_DATA01 0x170 0x3B4 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_25_ENET_RX_ER 0x170 0x3B4 0x4BC 0x3 0x0
-#define IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B 0x170 0x3B4 0x524 0x4 0x1
-#define IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 0x170 0x3B4 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_25_KPP_COL05 0x170 0x3B4 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_25_FLEXIO2_D25 0x170 0x3B4 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_25_LPI2C4_SDA 0x170 0x3B4 0x5C8 0x9 0x0
-
-#define IOMUXC_GPIO_AD_26_LPUART1_CTS_B 0x174 0x3B8 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_26_LPSPI2_SOUT 0x174 0x3B8 0x5EC 0x1 0x0
-#define IOMUXC_GPIO_AD_26_SEMC_CSX01 0x174 0x3B8 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_26_ENET_RX_DATA00 0x174 0x3B8 0x4B0 0x3 0x0
-#define IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A 0x174 0x3B8 0x51C 0x4 0x1
-#define IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25 0x174 0x3B8 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_26_KPP_ROW04 0x174 0x3B8 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_26_FLEXIO2_D26 0x174 0x3B8 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_26_ENET_QOS_MDC 0x174 0x3B8 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_26_GPIO9_IO25 0x174 0x3B8 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_26_USDHC2_CD_B 0x174 0x3B8 0x6D0 0xB 0x1
-
-#define IOMUXC_GPIO_AD_27_LPUART1_RTS_B 0x178 0x3BC 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_27_LPSPI2_SIN 0x178 0x3BC 0x5E8 0x1 0x0
-#define IOMUXC_GPIO_AD_27_SEMC_CSX02 0x178 0x3BC 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_27_ENET_RX_DATA01 0x178 0x3BC 0x4B4 0x3 0x0
-#define IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B 0x178 0x3BC 0x528 0x4 0x1
-#define IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 0x178 0x3BC 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_27_KPP_COL04 0x178 0x3BC 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_27_FLEXIO2_D27 0x178 0x3BC 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_27_ENET_QOS_MDIO 0x178 0x3BC 0x4EC 0x9 0x1
-#define IOMUXC_GPIO_AD_27_GPIO9_IO26 0x178 0x3BC 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_27_USDHC2_WP 0x178 0x3BC 0x6D4 0xB 0x1
-
-#define IOMUXC_GPIO_AD_28_GPIO9_IO27 0x17C 0x3C0 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_28_USDHC2_VSELECT 0x17C 0x3C0 0x0 0xB 0x0
-#define IOMUXC_GPIO_AD_28_LPSPI1_SCK 0x17C 0x3C0 0x5D0 0x0 0x1
-#define IOMUXC_GPIO_AD_28_LPUART5_TXD 0x17C 0x3C0 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_28_SEMC_CSX03 0x17C 0x3C0 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_28_ENET_TX_EN 0x17C 0x3C0 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A 0x17C 0x3C0 0x520 0x4 0x1
-#define IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27 0x17C 0x3C0 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_28_KPP_ROW03 0x17C 0x3C0 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_28_FLEXIO2_D28 0x17C 0x3C0 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 0x17C 0x3C0 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_AD_29_LPSPI1_PCS0 0x180 0x3C4 0x5CC 0x0 0x1
-#define IOMUXC_GPIO_AD_29_LPUART5_RXD 0x180 0x3C4 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_29_ENET_REF_CLK 0x180 0x3C4 0x4A8 0x2 0x0
-#define IOMUXC_GPIO_AD_29_ENET_TX_CLK 0x180 0x3C4 0x4C0 0x3 0x0
-#define IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B 0x180 0x3C4 0x52C 0x4 0x1
-#define IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 0x180 0x3C4 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_29_KPP_COL03 0x180 0x3C4 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_29_FLEXIO2_D29 0x180 0x3C4 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 0x180 0x3C4 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_29_GPIO9_IO28 0x180 0x3C4 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_29_USDHC2_RESET_B 0x180 0x3C4 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_30_LPSPI1_SOUT 0x184 0x3C8 0x5D8 0x0 0x1
-#define IOMUXC_GPIO_AD_30_USB_OTG2_OC 0x184 0x3C8 0x6B8 0x1 0x1
-#define IOMUXC_GPIO_AD_30_FLEXCAN2_TX 0x184 0x3C8 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_30_ENET_TX_DATA00 0x184 0x3C8 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_30_LPUART3_TXD 0x184 0x3C8 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 0x184 0x3C8 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_30_KPP_ROW02 0x184 0x3C8 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_30_FLEXIO2_D30 0x184 0x3C8 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_30_WDOG2_RESET_B_DEB 0x184 0x3C8 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_30_GPIO9_IO29 0x184 0x3C8 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_AD_31_LPSPI1_SIN 0x188 0x3CC 0x5D4 0x0 0x1
-#define IOMUXC_GPIO_AD_31_USB_OTG2_PWR 0x188 0x3CC 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_31_FLEXCAN2_RX 0x188 0x3CC 0x49C 0x2 0x1
-#define IOMUXC_GPIO_AD_31_ENET_TX_DATA01 0x188 0x3CC 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_31_LPUART3_RXD 0x188 0x3CC 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 0x188 0x3CC 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_31_KPP_COL02 0x188 0x3CC 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_31_FLEXIO2_D31 0x188 0x3CC 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_31_WDOG1_RESET_B_DEB 0x188 0x3CC 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_31_GPIO9_IO30 0x188 0x3CC 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_AD_32_GPIO9_IO31 0x18C 0x3D0 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_32_LPI2C1_SCL 0x18C 0x3D0 0x5AC 0x0 0x1
-#define IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID 0x18C 0x3D0 0x6C4 0x1 0x1
-#define IOMUXC_GPIO_AD_32_PGMC_PMIC_RDY 0x18C 0x3D0 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_32_ENET_MDC 0x18C 0x3D0 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_32_USDHC1_CD_B 0x18C 0x3D0 0x6C8 0x4 0x0
-#define IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31 0x18C 0x3D0 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_32_KPP_ROW01 0x18C 0x3D0 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_32_LPUART10_TXD 0x18C 0x3D0 0x628 0x8 0x1
-#define IOMUXC_GPIO_AD_32_ENET_1G_MDC 0x18C 0x3D0 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_AD_33_LPI2C1_SDA 0x190 0x3D4 0x5B0 0x0 0x1
-#define IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID 0x190 0x3D4 0x6C0 0x1 0x1
-#define IOMUXC_GPIO_AD_33_XBAR1_INOUT17 0x190 0x3D4 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_33_ENET_MDIO 0x190 0x3D4 0x4AC 0x3 0x1
-#define IOMUXC_GPIO_AD_33_USDHC1_WP 0x190 0x3D4 0x6CC 0x4 0x0
-#define IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00 0x190 0x3D4 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_33_KPP_COL01 0x190 0x3D4 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_33_LPUART10_RXD 0x190 0x3D4 0x624 0x8 0x1
-#define IOMUXC_GPIO_AD_33_ENET_1G_MDIO 0x190 0x3D4 0x4C8 0x9 0x3
-#define IOMUXC_GPIO_AD_33_GPIO10_IO00 0x190 0x3D4 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN 0x194 0x3D8 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_34_USB_OTG1_PWR 0x194 0x3D8 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_34_XBAR1_INOUT18 0x194 0x3D8 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN 0x194 0x3D8 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_34_USDHC1_VSELECT 0x194 0x3D8 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01 0x194 0x3D8 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_34_KPP_ROW00 0x194 0x3D8 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_34_LPUART10_CTS_B 0x194 0x3D8 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_34_WDOG1_ANY 0x194 0x3D8 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_34_GPIO10_IO01 0x194 0x3D8 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_AD_35_GPIO10_IO02 0x198 0x3DC 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_35_USB_OTG1_OC 0x198 0x3DC 0x6BC 0x1 0x1
-#define IOMUXC_GPIO_AD_35_XBAR1_INOUT19 0x198 0x3DC 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_35_USDHC1_RESET_B 0x198 0x3DC 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02 0x198 0x3DC 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_35_KPP_COL00 0x198 0x3DC 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_35_LPUART10_RTS_B 0x198 0x3DC 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B 0x198 0x3DC 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_SD_B1_00_USDHC1_CMD 0x19C 0x3E0 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT20 0x19C 0x3E0 0x6D8 0x2 0x1
-#define IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 0x19C 0x3E0 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 0x19C 0x3E0 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B 0x19C 0x3E0 0x0 0x6 0x0
-#define IOMUXC_GPIO_SD_B1_00_KPP_ROW07 0x19C 0x3E0 0x5A8 0x8 0x1
-#define IOMUXC_GPIO_SD_B1_00_GPIO10_IO03 0x19C 0x3E0 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_SD_B1_01_USDHC1_CLK 0x1A0 0x3E4 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B1_01_XBAR1_INOUT21 0x1A0 0x3E4 0x6DC 0x2 0x1
-#define IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 0x1A0 0x3E4 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 0x1A0 0x3E4 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK 0x1A0 0x3E4 0x58C 0x6 0x1
-#define IOMUXC_GPIO_SD_B1_01_KPP_COL07 0x1A0 0x3E4 0x5A0 0x8 0x1
-#define IOMUXC_GPIO_SD_B1_01_GPIO10_IO04 0x1A0 0x3E4 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_SD_B1_02_GPIO10_IO05 0x1A4 0x3E8 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 0x1A4 0x3E8 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B1_02_XBAR1_INOUT22 0x1A4 0x3E8 0x6E0 0x2 0x1
-#define IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 0x1A4 0x3E8 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 0x1A4 0x3E8 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 0x1A4 0x3E8 0x57C 0x6 0x1
-#define IOMUXC_GPIO_SD_B1_02_KPP_ROW06 0x1A4 0x3E8 0x5A4 0x8 0x1
-#define IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B 0x1A4 0x3E8 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 0x1A8 0x3EC 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B1_03_XBAR1_INOUT23 0x1A8 0x3EC 0x6E4 0x2 0x1
-#define IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 0x1A8 0x3EC 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 0x1A8 0x3EC 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 0x1A8 0x3EC 0x580 0x6 0x1
-#define IOMUXC_GPIO_SD_B1_03_KPP_COL06 0x1A8 0x3EC 0x59C 0x8 0x1
-#define IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B 0x1A8 0x3EC 0x0 0x9 0x0
-#define IOMUXC_GPIO_SD_B1_03_GPIO10_IO06 0x1A8 0x3EC 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 0x1AC 0x3F0 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B1_04_XBAR1_INOUT24 0x1AC 0x3F0 0x6E8 0x2 0x1
-#define IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 0x1AC 0x3F0 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 0x1AC 0x3F0 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 0x1AC 0x3F0 0x584 0x6 0x1
-#define IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B 0x1AC 0x3F0 0x0 0x8 0x0
-#define IOMUXC_GPIO_SD_B1_04_ENET_QOS_1588_EVENT2_AUX_IN 0x1AC 0x3F0 0x0 0x9 0x0
-#define IOMUXC_GPIO_SD_B1_04_GPIO10_IO07 0x1AC 0x3F0 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_SD_B1_05_GPIO10_IO08 0x1B0 0x3F4 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 0x1B0 0x3F4 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B1_05_XBAR1_INOUT25 0x1B0 0x3F4 0x6EC 0x2 0x1
-#define IOMUXC_GPIO_SD_B1_05_GPT4_CLK 0x1B0 0x3F4 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 0x1B0 0x3F4 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 0x1B0 0x3F4 0x588 0x6 0x1
-#define IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS 0x1B0 0x3F4 0x0 0x8 0x0
-#define IOMUXC_GPIO_SD_B1_05_ENET_QOS_1588_EVENT3_AUX_IN 0x1B0 0x3F4 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_SD_B2_00_GPIO10_IO09 0x1B4 0x3F8 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3 0x1B4 0x3F8 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 0x1B4 0x3F8 0x570 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN 0x1B4 0x3F8 0x4E0 0x2 0x1
-#define IOMUXC_GPIO_SD_B2_00_LPUART9_TXD 0x1B4 0x3F8 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK 0x1B4 0x3F8 0x610 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09 0x1B4 0x3F8 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2 0x1B8 0x3FC 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 0x1B8 0x3FC 0x56C 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK 0x1B8 0x3FC 0x4CC 0x2 0x1
-#define IOMUXC_GPIO_SD_B2_01_LPUART9_RXD 0x1B8 0x3FC 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0 0x1B8 0x3FC 0x60C 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10 0x1B8 0x3FC 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B2_01_GPIO10_IO10 0x1B8 0x3FC 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_SD_B2_02_GPIO10_IO11 0x1BC 0x400 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1 0x1BC 0x400 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 0x1BC 0x400 0x568 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_02_ENET_1G_RX_DATA00 0x1BC 0x400 0x4D0 0x2 0x1
-#define IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B 0x1BC 0x400 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_02_LPSPI4_SOUT 0x1BC 0x400 0x618 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11 0x1BC 0x400 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SD_B2_03_GPIO10_IO12 0x1C0 0x404 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0 0x1C0 0x404 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 0x1C0 0x404 0x564 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_03_ENET_1G_RX_DATA01 0x1C0 0x404 0x4D4 0x2 0x1
-#define IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B 0x1C0 0x404 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_03_LPSPI4_SIN 0x1C0 0x404 0x614 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12 0x1C0 0x404 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SD_B2_04_USDHC2_CLK 0x1C4 0x408 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK 0x1C4 0x408 0x578 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_04_ENET_1G_RX_DATA02 0x1C4 0x408 0x4D8 0x2 0x1
-#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B 0x1C4 0x408 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1 0x1C4 0x408 0x0 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13 0x1C4 0x408 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B2_04_GPIO10_IO13 0x1C4 0x408 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_SD_B2_05_GPIO10_IO14 0x1C8 0x40C 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B2_05_USDHC2_CMD 0x1C8 0x40C 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS 0x1C8 0x40C 0x550 0x1 0x2
-#define IOMUXC_GPIO_SD_B2_05_ENET_1G_RX_DATA03 0x1C8 0x40C 0x4DC 0x2 0x1
-#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B 0x1C8 0x40C 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2 0x1C8 0x40C 0x0 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14 0x1C8 0x40C 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SD_B2_06_GPIO10_IO15 0x1CC 0x410 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B 0x1CC 0x410 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B 0x1CC 0x410 0x0 0x1 0x0
-#define IOMUXC_GPIO_SD_B2_06_ENET_1G_TX_DATA03 0x1CC 0x410 0x0 0x2 0x0
-#define IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3 0x1CC 0x410 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1 0x1CC 0x410 0x0 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15 0x1CC 0x410 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE 0x1D0 0x414 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK 0x1D0 0x414 0x574 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_07_ENET_1G_TX_DATA02 0x1D0 0x414 0x0 0x2 0x0
-#define IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B 0x1D0 0x414 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2 0x1D0 0x414 0x0 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 0x1D0 0x414 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK 0x1D0 0x414 0x5E4 0x6 0x1
-#define IOMUXC_GPIO_SD_B2_07_ENET_TX_ER 0x1D0 0x414 0x0 0x8 0x0
-#define IOMUXC_GPIO_SD_B2_07_ENET_QOS_REF_CLK 0x1D0 0x414 0x4A0 0x9 0x1
-#define IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 0x1D0 0x414 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 0x1D4 0x418 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4 0x1D4 0x418 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 0x1D4 0x418 0x554 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_08_ENET_1G_TX_DATA01 0x1D4 0x418 0x0 0x2 0x0
-#define IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B 0x1D4 0x418 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1 0x1D4 0x418 0x0 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17 0x1D4 0x418 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0 0x1D4 0x418 0x5DC 0x6 0x1
-
-#define IOMUXC_GPIO_SD_B2_09_GPIO10_IO18 0x1D8 0x41C 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5 0x1D8 0x41C 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 0x1D8 0x41C 0x558 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_09_ENET_1G_TX_DATA00 0x1D8 0x41C 0x0 0x2 0x0
-#define IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B 0x1D8 0x41C 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2 0x1D8 0x41C 0x0 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18 0x1D8 0x41C 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B2_09_LPSPI2_SOUT 0x1D8 0x41C 0x5EC 0x6 0x1
-
-#define IOMUXC_GPIO_SD_B2_10_GPIO10_IO19 0x1DC 0x420 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6 0x1DC 0x420 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 0x1DC 0x420 0x55C 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN 0x1DC 0x420 0x0 0x2 0x0
-#define IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B 0x1DC 0x420 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3 0x1DC 0x420 0x0 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19 0x1DC 0x420 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B2_10_LPSPI2_SIN 0x1DC 0x420 0x5E8 0x6 0x1
-
-#define IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 0x1E0 0x424 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0x1E0 0x424 0x560 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO 0x1E0 0x424 0x4E8 0x2 0x1
-#define IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK 0x1E0 0x424 0x4C4 0x3 0x1
-#define IOMUXC_GPIO_SD_B2_11_GPT6_CLK 0x1E0 0x424 0x0 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 0x1E0 0x424 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 0x1E0 0x424 0x5E0 0x6 0x1
-#define IOMUXC_GPIO_SD_B2_11_GPIO10_IO20 0x1E0 0x424 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK 0x1E4 0x428 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN 0x1E4 0x428 0x4E0 0x1 0x2
-#define IOMUXC_GPIO_DISP_B1_00_TMR1_TIMER0 0x1E4 0x428 0x63C 0x3 0x2
-#define IOMUXC_GPIO_DISP_B1_00_XBAR1_INOUT26 0x1E4 0x428 0x6F0 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 0x1E4 0x428 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_00_ENET_QOS_RX_EN 0x1E4 0x428 0x4F8 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 0x1E4 0x428 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE 0x1E8 0x42C 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK 0x1E8 0x42C 0x4CC 0x1 0x2
-#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER 0x1E8 0x42C 0x4E4 0x2 0x1
-#define IOMUXC_GPIO_DISP_B1_01_TMR1_TIMER1 0x1E8 0x42C 0x640 0x3 0x2
-#define IOMUXC_GPIO_DISP_B1_01_XBAR1_INOUT27 0x1E8 0x42C 0x6F4 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 0x1E8 0x42C 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_CLK 0x1E8 0x42C 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_ER 0x1E8 0x42C 0x4FC 0x9 0x0
-#define IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 0x1E8 0x42C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23 0x1EC 0x430 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC 0x1EC 0x430 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00 0x1EC 0x430 0x4D0 0x1 0x2
-#define IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL 0x1EC 0x430 0x5BC 0x2 0x0
-#define IOMUXC_GPIO_DISP_B1_02_TMR1_TIMER2 0x1EC 0x430 0x644 0x3 0x1
-#define IOMUXC_GPIO_DISP_B1_02_XBAR1_INOUT28 0x1EC 0x430 0x6F8 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 0x1EC 0x430 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_02_ENET_QOS_RX_DATA00 0x1EC 0x430 0x4F0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_02_LPUART1_TXD 0x1EC 0x430 0x620 0x9 0x1
-
-#define IOMUXC_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC 0x1F0 0x434 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01 0x1F0 0x434 0x4D4 0x1 0x2
-#define IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA 0x1F0 0x434 0x5C0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B1_03_TMR2_TIMER0 0x1F0 0x434 0x648 0x3 0x2
-#define IOMUXC_GPIO_DISP_B1_03_XBAR1_INOUT29 0x1F0 0x434 0x6FC 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 0x1F0 0x434 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_03_ENET_QOS_RX_DATA01 0x1F0 0x434 0x4F4 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_03_LPUART1_RXD 0x1F0 0x434 0x61C 0x9 0x1
-#define IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 0x1F0 0x434 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00 0x1F4 0x438 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02 0x1F4 0x438 0x4D8 0x1 0x2
-#define IOMUXC_GPIO_DISP_B1_04_LPUART4_RXD 0x1F4 0x438 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B1_04_TMR2_TIMER1 0x1F4 0x438 0x64C 0x3 0x2
-#define IOMUXC_GPIO_DISP_B1_04_XBAR1_INOUT30 0x1F4 0x438 0x700 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 0x1F4 0x438 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_04_ENET_QOS_RX_DATA02 0x1F4 0x438 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK 0x1F4 0x438 0x600 0x9 0x1
-#define IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 0x1F4 0x438 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26 0x1F8 0x43C 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01 0x1F8 0x43C 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03 0x1F8 0x43C 0x4DC 0x1 0x2
-#define IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B 0x1F8 0x43C 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B1_05_TMR2_TIMER2 0x1F8 0x43C 0x650 0x3 0x1
-#define IOMUXC_GPIO_DISP_B1_05_XBAR1_INOUT31 0x1F8 0x43C 0x704 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 0x1F8 0x43C 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_05_ENET_QOS_RX_DATA03 0x1F8 0x43C 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_05_LPSPI3_SIN 0x1F8 0x43C 0x604 0x9 0x1
-
-#define IOMUXC_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02 0x1FC 0x440 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03 0x1FC 0x440 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B1_06_LPUART4_TXD 0x1FC 0x440 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B1_06_TMR3_TIMER0 0x1FC 0x440 0x654 0x3 0x2
-#define IOMUXC_GPIO_DISP_B1_06_XBAR1_INOUT32 0x1FC 0x440 0x708 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27 0x1FC 0x440 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00 0x1FC 0x440 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B1_06_ENET_QOS_TX_DATA03 0x1FC 0x440 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_06_LPSPI3_SOUT 0x1FC 0x440 0x608 0x9 0x1
-#define IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27 0x1FC 0x440 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03 0x200 0x444 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02 0x200 0x444 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B 0x200 0x444 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B1_07_TMR3_TIMER1 0x200 0x444 0x658 0x3 0x2
-#define IOMUXC_GPIO_DISP_B1_07_XBAR1_INOUT33 0x200 0x444 0x70C 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28 0x200 0x444 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01 0x200 0x444 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B1_07_ENET_QOS_TX_DATA02 0x200 0x444 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0 0x200 0x444 0x5F0 0x9 0x1
-#define IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28 0x200 0x444 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29 0x204 0x448 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04 0x204 0x448 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01 0x204 0x448 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B 0x204 0x448 0x6C8 0x2 0x1
-#define IOMUXC_GPIO_DISP_B1_08_TMR3_TIMER2 0x204 0x448 0x65C 0x3 0x1
-#define IOMUXC_GPIO_DISP_B1_08_XBAR1_INOUT34 0x204 0x448 0x710 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29 0x204 0x448 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02 0x204 0x448 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B1_08_ENET_QOS_TX_DATA01 0x204 0x448 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1 0x204 0x448 0x5F4 0x9 0x1
-
-#define IOMUXC_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05 0x208 0x44C 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00 0x208 0x44C 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B1_09_USDHC1_WP 0x208 0x44C 0x6CC 0x2 0x1
-#define IOMUXC_GPIO_DISP_B1_09_TMR4_TIMER0 0x208 0x44C 0x660 0x3 0x2
-#define IOMUXC_GPIO_DISP_B1_09_XBAR1_INOUT35 0x208 0x44C 0x714 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30 0x208 0x44C 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03 0x208 0x44C 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B1_09_ENET_QOS_TX_DATA00 0x208 0x44C 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2 0x208 0x44C 0x5F8 0x9 0x1
-#define IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30 0x208 0x44C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06 0x20C 0x450 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN 0x20C 0x450 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B 0x20C 0x450 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B1_10_TMR4_TIMER1 0x20C 0x450 0x664 0x3 0x2
-#define IOMUXC_GPIO_DISP_B1_10_XBAR1_INOUT36 0x20C 0x450 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31 0x20C 0x450 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04 0x20C 0x450 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B1_10_ENET_QOS_TX_EN 0x20C 0x450 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3 0x20C 0x450 0x5FC 0x9 0x1
-#define IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31 0x20C 0x450 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 0x210 0x454 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO 0x210 0x454 0x4E8 0x1 0x2
-#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK 0x210 0x454 0x4C4 0x2 0x2
-#define IOMUXC_GPIO_DISP_B1_11_TMR4_TIMER2 0x210 0x454 0x668 0x3 0x1
-#define IOMUXC_GPIO_DISP_B1_11_XBAR1_INOUT37 0x210 0x454 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 0x210 0x454 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 0x210 0x454 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_TX_CLK 0x210 0x454 0x4A4 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_REF_CLK 0x210 0x454 0x4A0 0x9 0x2
-#define IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 0x210 0x454 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 0x214 0x458 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08 0x214 0x458 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_00_WDOG1_B 0x214 0x458 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT 0x214 0x458 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER 0x214 0x458 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03 0x214 0x458 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01 0x214 0x458 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06 0x214 0x458 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B2_00_ENET_QOS_TX_ER 0x214 0x458 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09 0x218 0x45C 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT 0x218 0x45C 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B2_01_MQS_LEFT 0x218 0x45C 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_01_WDOG2_B 0x218 0x45C 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02 0x218 0x45C 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02 0x218 0x45C 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07 0x218 0x45C 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B2_01_EWM_OUT_B 0x218 0x45C 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M 0x218 0x45C 0x0 0x9 0x0
-#define IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02 0x218 0x45C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03 0x21C 0x460 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 0x21C 0x460 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00 0x21C 0x460 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER3 0x21C 0x460 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 0x21C 0x460 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 0x21C 0x460 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 0x21C 0x460 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 0x21C 0x460 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B2_02_ENET_QOS_TX_DATA00 0x21C 0x460 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04 0x220 0x464 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 0x220 0x464 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01 0x220 0x464 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER2 0x220 0x464 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 0x220 0x464 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK 0x220 0x464 0x66C 0x4 0x1
-#define IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 0x220 0x464 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 0x220 0x464 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B2_03_ENET_QOS_TX_DATA01 0x220 0x464 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 0x224 0x468 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN 0x224 0x468 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER1 0x224 0x468 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 0x224 0x468 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC 0x224 0x468 0x678 0x4 0x1
-#define IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 0x224 0x468 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 0x224 0x468 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B2_04_ENET_QOS_TX_EN 0x224 0x468 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05 0x224 0x468 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 0x228 0x46C 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 0x228 0x46C 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK 0x228 0x46C 0x4C0 0x1 0x1
-#define IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK 0x228 0x46C 0x4A8 0x2 0x1
-#define IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 0x228 0x46C 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK 0x228 0x46C 0x670 0x4 0x1
-#define IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 0x228 0x46C 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 0x228 0x46C 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B2_05_ENET_QOS_TX_CLK 0x228 0x46C 0x4A4 0x8 0x1
-
-#define IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07 0x22C 0x470 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 0x22C 0x470 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00 0x22C 0x470 0x4B0 0x1 0x1
-#define IOMUXC_GPIO_DISP_B2_06_LPUART7_TXD 0x22C 0x470 0x630 0x2 0x1
-#define IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK 0x22C 0x470 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 0x22C 0x470 0x674 0x4 0x1
-#define IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 0x22C 0x470 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_06_ENET_QOS_RX_DATA00 0x22C 0x470 0x4F0 0x8 0x1
-
-#define IOMUXC_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 0x230 0x474 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01 0x230 0x474 0x4B4 0x1 0x1
-#define IOMUXC_GPIO_DISP_B2_07_LPUART7_RXD 0x230 0x474 0x62C 0x2 0x1
-#define IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO 0x230 0x474 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 0x230 0x474 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 0x230 0x474 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_07_ENET_QOS_RX_DATA01 0x230 0x474 0x4F4 0x8 0x1
-#define IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 0x230 0x474 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 0x234 0x478 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 0x234 0x478 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN 0x234 0x478 0x4B8 0x1 0x1
-#define IOMUXC_GPIO_DISP_B2_08_LPUART8_TXD 0x234 0x478 0x638 0x2 0x1
-#define IOMUXC_GPIO_DISP_B2_08_ARM_CM7_EVENTO 0x234 0x478 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK 0x234 0x478 0x67C 0x4 0x1
-#define IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09 0x234 0x478 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_08_ENET_QOS_RX_EN 0x234 0x478 0x4F8 0x8 0x1
-#define IOMUXC_GPIO_DISP_B2_08_LPUART1_TXD 0x234 0x478 0x620 0x9 0x2
-
-#define IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 0x238 0x47C 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 0x238 0x47C 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER 0x238 0x47C 0x4BC 0x1 0x1
-#define IOMUXC_GPIO_DISP_B2_09_LPUART8_RXD 0x238 0x47C 0x634 0x2 0x1
-#define IOMUXC_GPIO_DISP_B2_09_ARM_CM7_EVENTI 0x238 0x47C 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC 0x238 0x47C 0x680 0x4 0x1
-#define IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 0x238 0x47C 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_09_ENET_QOS_RX_ER 0x238 0x47C 0x4FC 0x8 0x1
-#define IOMUXC_GPIO_DISP_B2_09_LPUART1_RXD 0x238 0x47C 0x61C 0x9 0x2
-
-#define IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 0x23C 0x480 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 0x23C 0x480 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_10_EMVSIM2_IO 0x23C 0x480 0x6A8 0x1 0x1
-#define IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD 0x23C 0x480 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_10_WDOG2_RESET_B_DEB 0x23C 0x480 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_10_XBAR1_INOUT38 0x23C 0x480 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 0x23C 0x480 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL 0x23C 0x480 0x5BC 0x6 0x1
-#define IOMUXC_GPIO_DISP_B2_10_ENET_QOS_RX_ER 0x23C 0x480 0x4FC 0x8 0x2
-#define IOMUXC_GPIO_DISP_B2_10_SPDIF_IN 0x23C 0x480 0x6B4 0x9 0x2
-
-#define IOMUXC_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 0x240 0x484 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_11_EMVSIM2_CLK 0x240 0x484 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD 0x240 0x484 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_11_WDOG1_RESET_B_DEB 0x240 0x484 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_11_XBAR1_INOUT39 0x240 0x484 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 0x240 0x484 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA 0x240 0x484 0x5C0 0x6 0x1
-#define IOMUXC_GPIO_DISP_B2_11_ENET_QOS_CRS 0x240 0x484 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT 0x240 0x484 0x0 0x9 0x0
-#define IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 0x240 0x484 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 0x244 0x488 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 0x244 0x488 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_12_EMVSIM2_RST 0x244 0x488 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B2_12_FLEXCAN1_TX 0x244 0x488 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B 0x244 0x488 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_12_XBAR1_INOUT40 0x244 0x488 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13 0x244 0x488 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL 0x244 0x488 0x5C4 0x6 0x1
-#define IOMUXC_GPIO_DISP_B2_12_ENET_QOS_COL 0x244 0x488 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK 0x244 0x488 0x610 0x9 0x1
-
-#define IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 0x248 0x48C 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 0x248 0x48C 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_13_EMVSIM2_SVEN 0x248 0x48C 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B2_13_FLEXCAN1_RX 0x248 0x48C 0x498 0x2 0x1
-#define IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B 0x248 0x48C 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK 0x248 0x48C 0x4A8 0x4 0x2
-#define IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 0x248 0x48C 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA 0x248 0x48C 0x5C8 0x6 0x1
-#define IOMUXC_GPIO_DISP_B2_13_ENET_QOS_1588_EVENT0_OUT 0x248 0x48C 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B2_13_LPSPI4_SIN 0x248 0x48C 0x614 0x9 0x1
-
-#define IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15 0x24C 0x490 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_14_FLEXCAN1_TX 0x24C 0x490 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B2_14_ENET_QOS_1588_EVENT0_IN 0x24C 0x490 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B2_14_LPSPI4_SOUT 0x24C 0x490 0x618 0x9 0x1
-#define IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15 0x24C 0x490 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22 0x24C 0x490 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_14_EMVSIM2_PD 0x24C 0x490 0x6AC 0x1 0x1
-#define IOMUXC_GPIO_DISP_B2_14_WDOG2_B 0x24C 0x490 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 0x24C 0x490 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK 0x24C 0x490 0x4C4 0x4 0x3
-
-#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 0x250 0x494 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_15_EMVSIM2_POWER_FAIL 0x250 0x494 0x6B0 0x1 0x1
-#define IOMUXC_GPIO_DISP_B2_15_WDOG1_B 0x250 0x494 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 0x250 0x494 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER0 0x250 0x494 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16 0x250 0x494 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_15_FLEXCAN1_RX 0x250 0x494 0x498 0x6 0x2
-#define IOMUXC_GPIO_DISP_B2_15_ENET_QOS_1588_EVENT0_AUX_IN 0x250 0x494 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 0x250 0x494 0x60C 0x9 0x1
-#define IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 0x250 0x494 0x0 0xA 0x0
-
-#endif /* _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H */
diff --git a/arch/arm/boot/dts/nxp/vf/Makefile b/arch/arm/boot/dts/nxp/vf/Makefile
index 0a4a7f9dd43e..1733506c0c72 100644
--- a/arch/arm/boot/dts/nxp/vf/Makefile
+++ b/arch/arm/boot/dts/nxp/vf/Makefile
@@ -3,9 +3,7 @@ dtb-$(CONFIG_SOC_VF610) += \
vf500-colibri-eval-v3.dtb \
vf610-bk4.dtb \
vf610-colibri-eval-v3.dtb \
- vf610m4-colibri.dtb \
vf610-cosmic.dtb \
- vf610m4-cosmic.dtb \
vf610-twr.dtb \
vf610-zii-cfu1.dtb \
vf610-zii-dev-rev-b.dtb \
diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts b/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts
deleted file mode 100644
index 86d32f54c250..000000000000
--- a/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Device tree for Colibri VF61 Cortex-M4 support
- *
- * Copyright (C) 2015 Stefan Agner
- */
-
-/dts-v1/;
-#include "vf610m4.dtsi"
-
-/ {
- model = "VF610 Cortex-M4";
- compatible = "fsl,vf610m4";
-
- chosen {
- bootargs = "clk_ignore_unused init=/linuxrc rw";
- stdout-path = "serial2:115200";
- };
-
- memory@8c000000 {
- device_type = "memory";
- reg = <0x8c000000 0x3000000>;
- };
-};
-
-&gpio0 {
- status = "disabled";
-};
-
-&gpio1 {
- status = "disabled";
-};
-
-&gpio2 {
- status = "disabled";
-};
-
-&gpio3 {
- status = "disabled";
-};
-
-&gpio4 {
- status = "disabled";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- VF610_PAD_PTD0__UART2_TX 0x21a2
- VF610_PAD_PTD1__UART2_RX 0x21a1
- VF610_PAD_PTD2__UART2_RTS 0x21a2
- VF610_PAD_PTD3__UART2_CTS 0x21a1
- >;
- };
-};
diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts b/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts
deleted file mode 100644
index 454b484368cb..000000000000
--- a/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Device tree for Cosmic+ VF6xx Cortex-M4 support
- *
- * Copyright (C) 2015
- *
- * Based on vf610m4 Colibri
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "vf610m4.dtsi"
-
-/ {
- model = "VF610 Cortex-M4";
- compatible = "fsl,vf610m4";
-};
-
-&gpio0 {
- status = "disabled";
-};
-
-&gpio1 {
- status = "disabled";
-};
-
-&gpio2 {
- status = "disabled";
-};
-
-&gpio3 {
- status = "disabled";
-};
-
-&gpio4 {
- status = "disabled";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- VF610_PAD_PTA20__UART3_TX 0x21a2
- VF610_PAD_PTA21__UART3_RX 0x21a1
- >;
- };
-};
diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi b/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi
deleted file mode 100644
index 648d219e1d0e..000000000000
--- a/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Device tree for VF6xx Cortex-M4 support
- *
- * Copyright (C) 2015 Stefan Agner
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "../../armv7-m.dtsi"
-#include "vfxxx.dtsi"
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- chosen { };
- aliases { };
-};
-
-&mscm_ir {
- interrupt-parent = <&nvic>;
-};
-
-&nvic {
- arm,num-irq-priority-bits = <4>;
-};
diff --git a/arch/arm/configs/imxrt_defconfig b/arch/arm/configs/imxrt_defconfig
deleted file mode 100644
index 52dba3762996..000000000000
--- a/arch/arm/configs/imxrt_defconfig
+++ /dev/null
@@ -1,35 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_BPF_SYSCALL=y
-CONFIG_SCHED_AUTOGROUP=y
-# CONFIG_MMU is not set
-CONFIG_ARCH_MXC=y
-CONFIG_SOC_IMXRT=y
-CONFIG_SET_MEM_PARAM=y
-CONFIG_DRAM_BASE=0x80000000
-CONFIG_DRAM_SIZE=0x02000000
-CONFIG_BINFMT_FLAT=y
-CONFIG_UEVENT_HELPER=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_IMX_WEIM=y
-CONFIG_LEGACY_PTY_COUNT=2
-CONFIG_SERIAL_FSL_LPUART=y
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_PINCTRL_IMXRT1050=y
-CONFIG_GPIO_MXC=y
-CONFIG_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_ESDHC_IMX=y
-CONFIG_DMADEVICES=y
-CONFIG_FSL_EDMA=y
-CONFIG_CLK_IMXRT1050=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_UTF8=y
-CONFIG_EXFAT_FS=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_UTF8=y
diff --git a/arch/arm/configs/vf610m4_defconfig b/arch/arm/configs/vf610m4_defconfig
deleted file mode 100644
index a5609cbfdfb3..000000000000
--- a/arch/arm/configs/vf610m4_defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-CONFIG_NAMESPACES=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-# CONFIG_RD_XZ is not set
-# CONFIG_RD_LZ4 is not set
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_MMU is not set
-CONFIG_ARCH_MXC=y
-CONFIG_SOC_VF610=y
-CONFIG_SET_MEM_PARAM=y
-CONFIG_DRAM_BASE=0x8c000000
-CONFIG_FLASH_MEM_BASE=0x8f000000
-CONFIG_FLASH_SIZE=0x01000000
-CONFIG_CMDLINE="console=/dev/ttyLP2"
-CONFIG_XIP_KERNEL=y
-CONFIG_XIP_PHYS_ADDR=0x0f000080
-# CONFIG_SUSPEND is not set
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-# CONFIG_UEVENT_HELPER is not set
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_ALLOW_DEV_COREDUMP is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=4
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_FSL_LPUART=y
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_MFD_SYSCON=y
-# CONFIG_HID is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT4_FS=y
-# CONFIG_MISC_FILESYSTEMS is not set
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 77704c6a70ba..cdc1b31fe573 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -2,7 +2,7 @@
menuconfig ARCH_MXC
bool "Freescale i.MX family"
depends on ((ARCH_MULTI_V4T || ARCH_MULTI_V5) && CPU_LITTLE_ENDIAN) || \
- ARCH_MULTI_V6_V7 || ARM_SINGLE_ARMV7M
+ ARCH_MULTI_V6_V7
select CLKSRC_IMX_GPT
select GENERIC_IRQ_CHIP
select GPIOLIB
@@ -174,7 +174,7 @@ config SOC_LS1021A
endif
-if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
+if ARCH_MULTI_V7
comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
@@ -187,38 +187,23 @@ config SOC_IMX7D_CA7
select HAVE_IMX_SRC
select IMX_GPCV2
-config SOC_IMX7D_CM4
- bool
- select ARMV7M_SYSTICK
-
config SOC_IMX7D
bool "i.MX7 Dual support"
- select SOC_IMX7D_CA7 if ARCH_MULTI_V7
- select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
- select ARM_ERRATA_814220 if ARCH_MULTI_V7
+ select SOC_IMX7D_CA7
+ select ARM_ERRATA_814220
help
This enables support for Freescale i.MX7 Dual processor.
config SOC_IMX7ULP
bool "i.MX7ULP support"
select CLKSRC_IMX_TPM
- select SOC_IMX7D_CA7 if ARCH_MULTI_V7
- select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
+ select SOC_IMX7D_CA7
help
This enables support for Freescale i.MX7 Ultra Low Power processor.
-config SOC_IMXRT
- bool "i.MXRT support (DEPRECATED)"
- depends on ARM_SINGLE_ARMV7M
- select ARMV7M_SYSTICK if ARM_SINGLE_ARMV7M
- help
- This enables support for Freescale i.MXRT Crossover processor.
-
- This platform is scheduled for removal in early 2027
-
config SOC_VF610
bool "Vybrid Family VF610 support"
- select ARM_GIC if ARCH_MULTI_V7
+ select ARM_GIC
help
This enables support for Freescale Vybrid VF610 processor.
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index fa0144f0882d..135079340428 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -42,7 +42,6 @@ obj-$(CONFIG_SOC_IMX6SLL) += mach-imx6sl.o
obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
obj-$(CONFIG_SOC_IMX7D_CA7) += mach-imx7d.o
-obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o
obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o
ifeq ($(CONFIG_SUSPEND),y)
@@ -59,8 +58,6 @@ obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
obj-$(CONFIG_SOC_IMX51) += mach-imx51.o
obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
-obj-$(CONFIG_SOC_IMXRT) += mach-imxrt.o
-
obj-$(CONFIG_SOC_VF610) += mach-vf610.o
obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
diff --git a/arch/arm/mach-imx/mach-imx7d-cm4.c b/arch/arm/mach-imx/mach-imx7d-cm4.c
deleted file mode 100644
index 0800b5891d2a..000000000000
--- a/arch/arm/mach-imx/mach-imx7d-cm4.c
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
- */
-
-#include <linux/kernel.h>
-#include <asm/v7m.h>
-#include <asm/mach/arch.h>
-
-static const char * const imx7d_cm4_dt_compat[] __initconst = {
- "fsl,imx7d-cm4",
- NULL,
-};
-
-DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual Cortex-M4 (Device Tree)")
- .dt_compat = imx7d_cm4_dt_compat,
- .restart = armv7m_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imxrt.c b/arch/arm/mach-imx/mach-imxrt.c
deleted file mode 100644
index 2063a3059c84..000000000000
--- a/arch/arm/mach-imx/mach-imxrt.c
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#include <linux/kernel.h>
-#include <asm/mach/arch.h>
-#include <asm/v7m.h>
-
-static const char *const imxrt_compat[] __initconst = {
- "fsl,imxrt1050",
- NULL
-};
-
-DT_MACHINE_START(IMXRTDT, "IMXRT (Device Tree Support)")
- .dt_compat = imxrt_compat,
- .restart = armv7m_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
index 208ff640698d..f77565381097 100644
--- a/arch/arm/mach-imx/mach-vf610.c
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -59,7 +59,6 @@ static const char * const vf610_dt_compat[] __initconst = {
"fsl,vf510",
"fsl,vf600",
"fsl,vf610",
- "fsl,vf610m4",
NULL,
};
--
2.53.0
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 08/13] ARM: imx: remove nommu support
2026-09-08 15:27 ` [PATCH 08/13] ARM: imx: remove nommu support Arnd Bergmann
@ 2026-09-09 20:17 ` Fabio Estevam
2026-09-09 20:21 ` Fabio Estevam
2026-09-10 15:14 ` Frank Li
2 siblings, 0 replies; 70+ messages in thread
From: Fabio Estevam @ 2026-09-09 20:17 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Arnd Bergmann, Rob Herring,
Conor Dooley, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski,
Giulio Benetti
On Tue, Sep 8, 2026 at 12:29 PM Arnd Bergmann <arnd@kernel.org> wrote:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> The i.MX platform has grown support for three separate product
> lines using Cortex-M based microcontrollers over the years:
>
> - i.MX RT1050, a high-end microcontroller
> - Vybrid vf610 suppors running Linux on either the Cortex-A5
> CPU or the Cortex-M4 MCU
> - i.MX7D similarly can run Linux on the Cortex-A7 or the
> Cortex-M4
>
> There are no known upstream users of any of those three, so
> drop support and simplify the platform to assume that an MMU
> is present.
>
> Cc: Frank Li <Frank.Li@nxp.com>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Vladimir Zapolskiy <vz@mleia.com>
> Cc: Giulio Benetti <giulio.benetti@benettiengineering.com>
> Cc: devicetree@vger.kernel.org
> Cc: imx@lists.linux.dev
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> arch/arm/boot/dts/nxp/imx/Makefile | 2 -
> arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts | 72 -
> arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h | 993 -----------
> arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi | 160 --
> arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h | 1561 -----------------
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 08/13] ARM: imx: remove nommu support
2026-09-08 15:27 ` [PATCH 08/13] ARM: imx: remove nommu support Arnd Bergmann
2026-09-09 20:17 ` Fabio Estevam
@ 2026-09-09 20:21 ` Fabio Estevam
2026-09-10 13:08 ` Jesse T
2026-09-10 16:08 ` Giulio Benetti
2026-09-10 15:14 ` Frank Li
2 siblings, 2 replies; 70+ messages in thread
From: Fabio Estevam @ 2026-09-09 20:21 UTC (permalink / raw)
To: Arnd Bergmann, Jesse Taube, Giulio Benetti
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Arnd Bergmann, Rob Herring,
Conor Dooley, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski
On Tue, Sep 8, 2026 at 12:29 PM Arnd Bergmann <arnd@kernel.org> wrote:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> The i.MX platform has grown support for three separate product
> lines using Cortex-M based microcontrollers over the years:
>
> - i.MX RT1050, a high-end microcontroller
> - Vybrid vf610 suppors running Linux on either the Cortex-A5
> CPU or the Cortex-M4 MCU
> - i.MX7D similarly can run Linux on the Cortex-A7 or the
> Cortex-M4
>
> There are no known upstream users of any of those three, so
> drop support and simplify the platform to assume that an MMU
> is present.
>
> Cc: Frank Li <Frank.Li@nxp.com>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Vladimir Zapolskiy <vz@mleia.com>
> Cc: Giulio Benetti <giulio.benetti@benettiengineering.com>
> Cc: devicetree@vger.kernel.org
> Cc: imx@lists.linux.dev
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> arch/arm/boot/dts/nxp/imx/Makefile | 2 -
> arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts | 72 -
> arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h | 993 -----------
> arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi | 160 --
> arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h | 1561 -----------------
> arch/arm/boot/dts/nxp/vf/Makefile | 2 -
> arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts | 61 -
> arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts | 88 -
> arch/arm/boot/dts/nxp/vf/vf610m4.dtsi | 61 -
> arch/arm/configs/imxrt_defconfig | 35 -
> arch/arm/configs/vf610m4_defconfig | 39 -
> arch/arm/mach-imx/Kconfig | 27 +-
> arch/arm/mach-imx/Makefile | 3 -
> arch/arm/mach-imx/mach-imx7d-cm4.c | 18 -
> arch/arm/mach-imx/mach-imxrt.c | 19 -
The imxrt1050-evk dts is used in U-Boot.
Adding Jesse and Giulio, who use this platform in U-Boot.
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 08/13] ARM: imx: remove nommu support
2026-09-09 20:21 ` Fabio Estevam
@ 2026-09-10 13:08 ` Jesse T
2026-09-10 16:08 ` Giulio Benetti
1 sibling, 0 replies; 70+ messages in thread
From: Jesse T @ 2026-09-10 13:08 UTC (permalink / raw)
To: Fabio Estevam
Cc: Arnd Bergmann, Giulio Benetti, Krzysztof Kozlowski,
Alexandre Belloni, Linus Walleij, Russell King, Drew Fustini,
Arnd Bergmann, Rob Herring, Conor Dooley, Liviu Dudau,
Sudeep Holla, Lorenzo Pieralisi, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Vladimir Zapolskiy, Stefan Agner,
Maxime Coquelin, Alexandre Torgue, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Nicolas Ferre, Claudiu Beznea, Andrew Lunn,
Sebastian Hesselbarth, Gregory Clement, Robert Jarzmik,
Kristoffer Ericson, Ethan Nelson-Moore, Geert Uytterhoeven,
Alexander Sverdlin, Shawn Guo, Karl Mehltretter,
David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski
On Wed, Sep 9, 2026 at 4:21 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> On Tue, Sep 8, 2026 at 12:29 PM Arnd Bergmann <arnd@kernel.org> wrote:
> >
> > From: Arnd Bergmann <arnd@arndb.de>
> >
> > The i.MX platform has grown support for three separate product
> > lines using Cortex-M based microcontrollers over the years:
> >
> > - i.MX RT1050, a high-end microcontroller
> > - Vybrid vf610 suppors running Linux on either the Cortex-A5
> > CPU or the Cortex-M4 MCU
> > - i.MX7D similarly can run Linux on the Cortex-A7 or the
> > Cortex-M4
> >
> > There are no known upstream users of any of those three,
There is both a u-boot and buildroot config for i.MX RT1050,
I also do basic regression testing on this platform. I understand the
need to depreciate no-MMU, but it's sad to see them go.
If it helps at all to remove i.MX RT1050 there are only 11 commits
adding it that are from Giulio Benetti and I.
For i.MX RT1170 only 3 commits by me which only got partially
added. See
Commit: fff65226b229 ("pinctrl: freescale: Add i.MXRT1170 pinctrl
driver support")
I also occasionally test the stm32f429-disco as I have one.
> > so
> > drop support and simplify the platform to assume that an MMU
> > is present.
> >
> > Cc: Frank Li <Frank.Li@nxp.com>
> > Cc: Sascha Hauer <s.hauer@pengutronix.de>
> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> > Cc: Fabio Estevam <festevam@gmail.com>
> > Cc: Stefan Agner <stefan@agner.ch>
> > Cc: Rob Herring <robh@kernel.org>
> > Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> > Cc: Conor Dooley <conor+dt@kernel.org>
> > Cc: Vladimir Zapolskiy <vz@mleia.com>
> > Cc: Giulio Benetti <giulio.benetti@benettiengineering.com>
> > Cc: devicetree@vger.kernel.org
> > Cc: imx@lists.linux.dev
> > Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> > ---
> > arch/arm/boot/dts/nxp/imx/Makefile | 2 -
> > arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts | 72 -
> > arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h | 993 -----------
> > arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi | 160 --
> > arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h | 1561 -----------------
> > arch/arm/boot/dts/nxp/vf/Makefile | 2 -
> > arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts | 61 -
> > arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts | 88 -
> > arch/arm/boot/dts/nxp/vf/vf610m4.dtsi | 61 -
> > arch/arm/configs/imxrt_defconfig | 35 -
> > arch/arm/configs/vf610m4_defconfig | 39 -
> > arch/arm/mach-imx/Kconfig | 27 +-
> > arch/arm/mach-imx/Makefile | 3 -
> > arch/arm/mach-imx/mach-imx7d-cm4.c | 18 -
> > arch/arm/mach-imx/mach-imxrt.c | 19 -
>
> The imxrt1050-evk dts is used in U-Boot.
>
> Adding Jesse and Giulio, who use this platform in U-Boot.
Thanks for the CC,
Jesse Taube
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 08/13] ARM: imx: remove nommu support
2026-09-09 20:21 ` Fabio Estevam
2026-09-10 13:08 ` Jesse T
@ 2026-09-10 16:08 ` Giulio Benetti
1 sibling, 0 replies; 70+ messages in thread
From: Giulio Benetti @ 2026-09-10 16:08 UTC (permalink / raw)
To: Fabio Estevam, Arnd Bergmann, Jesse Taube
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Arnd Bergmann, Rob Herring,
Conor Dooley, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski
Hi Fabio, Arnd and Jesse,
On 9/9/26 10:21 PM, Fabio Estevam wrote:
> On Tue, Sep 8, 2026 at 12:29 PM Arnd Bergmann <arnd@kernel.org> wrote:
>>
>> From: Arnd Bergmann <arnd@arndb.de>
>>
>> The i.MX platform has grown support for three separate product
>> lines using Cortex-M based microcontrollers over the years:
>>
>> - i.MX RT1050, a high-end microcontroller
>> - Vybrid vf610 suppors running Linux on either the Cortex-A5
>> CPU or the Cortex-M4 MCU
>> - i.MX7D similarly can run Linux on the Cortex-A7 or the
>> Cortex-M4
>>
>> There are no known upstream users of any of those three, so
>> drop support and simplify the platform to assume that an MMU
>> is present.
>>
>> Cc: Frank Li <Frank.Li@nxp.com>
>> Cc: Sascha Hauer <s.hauer@pengutronix.de>
>> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
>> Cc: Fabio Estevam <festevam@gmail.com>
>> Cc: Stefan Agner <stefan@agner.ch>
>> Cc: Rob Herring <robh@kernel.org>
>> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
>> Cc: Conor Dooley <conor+dt@kernel.org>
>> Cc: Vladimir Zapolskiy <vz@mleia.com>
>> Cc: Giulio Benetti <giulio.benetti@benettiengineering.com>
>> Cc: devicetree@vger.kernel.org
>> Cc: imx@lists.linux.dev
>> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>> ---
>> arch/arm/boot/dts/nxp/imx/Makefile | 2 -
>> arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts | 72 -
>> arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h | 993 -----------
>> arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi | 160 --
>> arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h | 1561 -----------------
>> arch/arm/boot/dts/nxp/vf/Makefile | 2 -
>> arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts | 61 -
>> arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts | 88 -
>> arch/arm/boot/dts/nxp/vf/vf610m4.dtsi | 61 -
>> arch/arm/configs/imxrt_defconfig | 35 -
>> arch/arm/configs/vf610m4_defconfig | 39 -
>> arch/arm/mach-imx/Kconfig | 27 +-
>> arch/arm/mach-imx/Makefile | 3 -
>> arch/arm/mach-imx/mach-imx7d-cm4.c | 18 -
>> arch/arm/mach-imx/mach-imxrt.c | 19 -
>
> The imxrt1050-evk dts is used in U-Boot.
>
> Adding Jesse and Giulio, who use this platform in U-Boot.
MMU-less architecture never had a complete support, I agree that it's
time to drop it so:
Acked-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Best regards
Giulio Benetti
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 08/13] ARM: imx: remove nommu support
2026-09-08 15:27 ` [PATCH 08/13] ARM: imx: remove nommu support Arnd Bergmann
2026-09-09 20:17 ` Fabio Estevam
2026-09-09 20:21 ` Fabio Estevam
@ 2026-09-10 15:14 ` Frank Li
2 siblings, 0 replies; 70+ messages in thread
From: Frank Li @ 2026-09-10 15:14 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Arnd Bergmann, Rob Herring,
Conor Dooley, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski,
Giulio Benetti
On Tue, Sep 08, 2026 at 05:27:58PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The i.MX platform has grown support for three separate product
> lines using Cortex-M based microcontrollers over the years:
>
> - i.MX RT1050, a high-end microcontroller
> - Vybrid vf610 suppors running Linux on either the Cortex-A5
> CPU or the Cortex-M4 MCU
> - i.MX7D similarly can run Linux on the Cortex-A7 or the
> Cortex-M4
>
> There are no known upstream users of any of those three, so
> drop support and simplify the platform to assume that an MMU
> is present.
>
> Cc: Frank Li <Frank.Li@nxp.com>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Vladimir Zapolskiy <vz@mleia.com>
> Cc: Giulio Benetti <giulio.benetti@benettiengineering.com>
> Cc: devicetree@vger.kernel.org
> Cc: imx@lists.linux.dev
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
Acked-by: Frank Li <Frank.Li@nxp.com>
> arch/arm/boot/dts/nxp/imx/Makefile | 2 -
> arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts | 72 -
> arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h | 993 -----------
> arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi | 160 --
> arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h | 1561 -----------------
> arch/arm/boot/dts/nxp/vf/Makefile | 2 -
> arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts | 61 -
> arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts | 88 -
> arch/arm/boot/dts/nxp/vf/vf610m4.dtsi | 61 -
> arch/arm/configs/imxrt_defconfig | 35 -
> arch/arm/configs/vf610m4_defconfig | 39 -
> arch/arm/mach-imx/Kconfig | 27 +-
> arch/arm/mach-imx/Makefile | 3 -
> arch/arm/mach-imx/mach-imx7d-cm4.c | 18 -
> arch/arm/mach-imx/mach-imxrt.c | 19 -
> arch/arm/mach-imx/mach-vf610.c | 1 -
> 16 files changed, 6 insertions(+), 3136 deletions(-)
> delete mode 100644 arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts
> delete mode 100644 arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h
> delete mode 100644 arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi
> delete mode 100644 arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h
> delete mode 100644 arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts
> delete mode 100644 arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts
> delete mode 100644 arch/arm/boot/dts/nxp/vf/vf610m4.dtsi
> delete mode 100644 arch/arm/configs/imxrt_defconfig
> delete mode 100644 arch/arm/configs/vf610m4_defconfig
> delete mode 100644 arch/arm/mach-imx/mach-imx7d-cm4.c
> delete mode 100644 arch/arm/mach-imx/mach-imxrt.c
>
> diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
> index e0747cb6e772..288d16d9315d 100644
> --- a/arch/arm/boot/dts/nxp/imx/Makefile
> +++ b/arch/arm/boot/dts/nxp/imx/Makefile
> @@ -452,5 +452,3 @@ dtb-$(CONFIG_SOC_IMX7D) += \
> dtb-$(CONFIG_SOC_IMX7ULP) += \
> imx7ulp-com.dtb \
> imx7ulp-evk.dtb
> -dtb-$(CONFIG_SOC_IMXRT) += \
> - imxrt1050-evk.dtb
> diff --git a/arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts b/arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts
> deleted file mode 100644
> index 6a9c10decf52..000000000000
> --- a/arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts
> +++ /dev/null
> @@ -1,72 +0,0 @@
> -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> -/*
> - * Copyright (C) 2019
> - * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> - */
> -
> -/dts-v1/;
> -#include "imxrt1050.dtsi"
> -#include "imxrt1050-pinfunc.h"
> -
> -/ {
> - model = "NXP IMXRT1050-evk board";
> - compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
> -
> - chosen {
> - stdout-path = &lpuart1;
> - };
> -
> - aliases {
> - gpio0 = &gpio1;
> - gpio1 = &gpio2;
> - gpio2 = &gpio3;
> - gpio3 = &gpio4;
> - gpio4 = &gpio5;
> - mmc0 = &usdhc1;
> - serial0 = &lpuart1;
> - };
> -
> - memory@80000000 {
> - device_type = "memory";
> - reg = <0x80000000 0x2000000>;
> - };
> -};
> -
> -&lpuart1 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_lpuart1>;
> - status = "okay";
> -};
> -
> -&iomuxc {
> - pinctrl-names = "default";
> - pinctrl_lpuart1: lpuart1grp {
> - fsl,pins = <
> - MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1
> - MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1
> - >;
> - };
> -
> - pinctrl_usdhc0: usdhc0grp {
> - fsl,pins = <
> - MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000
> - MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069
> - MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061
> - MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061
> - MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061
> - MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061
> - MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061
> - MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061
> - >;
> - };
> -};
> -
> -&usdhc1 {
> - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> - pinctrl-0 = <&pinctrl_usdhc0>;
> - pinctrl-1 = <&pinctrl_usdhc0>;
> - pinctrl-2 = <&pinctrl_usdhc0>;
> - pinctrl-3 = <&pinctrl_usdhc0>;
> - cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
> - status = "okay";
> -};
> diff --git a/arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h
> deleted file mode 100644
> index 22c14a3262ad..000000000000
> --- a/arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h
> +++ /dev/null
> @@ -1,993 +0,0 @@
> -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> -/*
> - * Copyright (C) 2019
> - * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> - */
> -
> -#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
> -#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
> -
> -#define IMX_PAD_SION 0x40000000
> -
> -/*
> - * The pin function ID is a tuple of
> - * <mux_reg conf_reg input_reg mux_mode input_val>
> - */
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x018 0x208 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x20C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x01C 0x20C 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x210 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x020 0x210 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x214 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024 0x214 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x024 0x214 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x5C4 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x21C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x02C 0x21C 0x478 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C 0x21C 0x5C0 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x02C 0x21C 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x220 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x030 0x220 0x488 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x030 0x220 0x5B0 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x030 0x220 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x224 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x034 0x224 0x47C 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x224 0x5B8 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x034 0x224 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x228 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x038 0x228 0x48C 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038 0x228 0x5BC 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x038 0x228 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x03C 0x22C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x03C 0x22C 0x480 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C 0x22C 0x5B4 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x03C 0x22C 0x450 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x03C 0x22C 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x03C 0x22C 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x040 0x230 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x040 0x230 0x490 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x040 0x230 0x4E8 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x040 0x230 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x040 0x230 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x040 0x230 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x044 0x234 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044 0x234 0x640 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x044 0x234 0x4E4 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 0x044 0x234 0x5D8 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x044 0x234 0x454 0x4 0x1
> -#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x044 0x234 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x650 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x53C 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x464 0x4 0x1
> -#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x04C 0x23C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C 0x23C 0x654 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x04C 0x23C 0x538 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 0x04C 0x23C 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x23C 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x04C 0x23C 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x634 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x534 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x57C 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x054 0x244 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054 0x244 0x658 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x054 0x244 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 0x054 0x244 0x5C8 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x054 0x244 0x580 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x054 0x244 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x058 0x248 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x058 0x248 0x4A0 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x058 0x248 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x058 0x248 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x058 0x248 0x584 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x058 0x248 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x05C 0x24C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x05C 0x24C 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x05C 0x24C 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x05C 0x24C 0x44C 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x05C 0x24C 0x588 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x05C 0x24C 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x05C 0x24C 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x060 0x250 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x060 0x250 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x060 0x250 0x544 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x060 0x250 0x438 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x060 0x250 0x56C 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x060 0x250 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x060 0x250 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x484 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x540 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x570 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0x068 0x258 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x068 0x258 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x068 0x258 0x4E0 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x068 0x258 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x068 0x258 0x574 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x068 0x258 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0x06C 0x25C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x06C 0x25C 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x06C 0x25C 0x4DC 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x06C 0x25C 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x06C 0x25C 0x578 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x06C 0x25C 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x070 0x260 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x070 0x260 0x458 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x070 0x260 0x54C 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x070 0x260 0x43C 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x070 0x260 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x070 0x260 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0x074 0x264 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x074 0x264 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x074 0x264 0x548 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x074 0x264 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x074 0x264 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x074 0x264 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0x078 0x268 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x078 0x268 0x45C 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x078 0x268 0x554 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x078 0x268 0x448 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078 0x268 0x42C 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x078 0x268 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0x07C 0x26C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x07C 0x26C 0x46C 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x07C 0x26C 0x550 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x07C 0x26C 0x440 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x07C 0x26C 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x07C 0x26C 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0x080 0x270 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x080 0x270 0x460 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x080 0x270 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x080 0x270 0x4F0 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x080 0x270 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x080 0x270 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0x084 0x274 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x084 0x274 0x470 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x084 0x274 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x084 0x274 0x4F8 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x084 0x274 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x084 0x274 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0x088 0x278 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x088 0x278 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x088 0x278 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x088 0x278 0x4F4 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x088 0x278 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x088 0x278 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0x08C 0x27C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x08C 0x27C 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x08C 0x27C 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x08C 0x27C 0x4EC 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 0x08C 0x27C 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x08C 0x27C 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0x090 0x280 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x090 0x280 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x090 0x280 0x55C 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x090 0x280 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 0x090 0x280 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x090 0x280 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0x094 0x284 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x094 0x284 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x094 0x284 0x558 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x094 0x284 0x3FC 0x3 0x4
> -#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 0x094 0x284 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x094 0x284 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0x098 0x288 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x098 0x288 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x098 0x288 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098 0x288 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 0x098 0x288 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x098 0x288 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0x09C 0x28C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x09C 0x28C 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x09C 0x28C 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C 0x28C 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 0x09C 0x28C 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x09C 0x28C 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0x0A0 0x290 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0 0x290 0x630 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x0A0 0x290 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0 0x290 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 0x0A0 0x290 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x0A0 0x290 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x0A0 0x290 0x5D4 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0x0A4 0x294 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4 0x294 0x638 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x0A4 0x294 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4 0x294 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 0x0A4 0x294 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x0A4 0x294 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x294 0x5D8 0x6 0x1
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0x0A8 0x298 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8 0x298 0x63C 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x0A8 0x298 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x0A8 0x298 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 0x0A8 0x298 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x0A8 0x298 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 0x0A8 0x298 0x608 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0x0AC 0x29C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x0AC 0x29C 0x454 0x1 0x2
> -#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x0AC 0x29C 0x564 0x2 0x2
> -#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC 0x29C 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 0x0AC 0x29C 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x0AC 0x29C 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x0AC 0x29C 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 0x0B0 0x2A0 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x0B0 0x2A0 0x464 0x1 0x2
> -#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x0B0 0x2A0 0x560 0x2 0x2
> -#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0 0x2A0 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x2A0 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x0B0 0x2A0 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x0B0 0x2A0 0x5E0 0x6 0x1
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 0x0B4 0x2A4 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x0B4 0x2A4 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x0B4 0x2A4 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x0B4 0x2A4 0x5CC 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 0x0B4 0x2A4 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x0B4 0x2A4 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x0B4 0x2A4 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x0B8 0x2A8 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x0B8 0x2A8 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x0B8 0x2A8 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8 0x2A8 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 0x0B8 0x2A8 0x430 0x4 0x1
> -#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x0B8 0x2A8 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT 0x0B8 0x2A8 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x0BC 0x2AC 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14 0x0BC 0x2AC 0x644 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x0BC 0x2AC 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x0BC 0x2AC 0x3F8 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x0BC 0x2AC 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x2AC 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x0BC 0x2AC 0x000 0x6 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC 0x2AC 0x510 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x0C0 0x2B0 0x484 0x0 0x2
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15 0x0C0 0x2B0 0x648 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x0C0 0x2B0 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x0C0 0x2B0 0x3F4 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x0C0 0x2B0 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x2B0 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x0C0 0x2B0 0x000 0x6 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0 0x2B0 0x518 0x7 0x1
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x0C4 0x2B4 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16 0x0C4 0x2B4 0x64C 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x0C4 0x2B4 0x554 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x0C4 0x2B4 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x0C4 0x2B4 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x2B4 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x0C4 0x2B4 0x000 0x6 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4 0x2B4 0x514 0x7 0x1
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x0C8 0x2B8 0x450 0x0 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17 0x0C8 0x2B8 0x62C 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x0C8 0x2B8 0x550 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x2B8 0x5D0 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x0C8 0x2B8 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x2B8 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x0C8 0x2B8 0x000 0x6 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x0C8 0x2B8 0x50C 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x0CC 0x2BC 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x0CC 0x2BC 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x0CC 0x2BC 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x0CC 0x2BC 0x5C4 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC 0x2BC 0x41C 0x4 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x2BC 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x0CC 0x2BC 0x000 0x6 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x0CC 0x2BC 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x0D0 0x2C0 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x0D0 0x2C0 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x0D0 0x2C0 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x0D0 0x2C0 0x5C0 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0 0x2C0 0x418 0x4 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x2C0 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17 0x0D0 0x2C0 0x62C 0x6 0x2
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x0D0 0x2C0 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x0D4 0x2C4 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x0D4 0x2C4 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x0D4 0x2C4 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x0D4 0x2C4 0x5B4 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4 0x2C4 0x414 0x4 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x2C4 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18 0x0D4 0x2C4 0x630 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x0D4 0x2C4 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x0D8 0x2C8 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x0D8 0x2C8 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8 0x2C8 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x0D8 0x2C8 0x5BC 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8 0x2C8 0x410 0x4 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x2C8 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19 0x0D8 0x2C8 0x654 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x0D8 0x2C8 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x0DC 0x2CC 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x0DC 0x2CC 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x0DC 0x2CC 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x0DC 0x2CC 0x5B8 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC 0x2CC 0x40C 0x4 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x2CC 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20 0x0DC 0x2CC 0x634 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x0DC 0x2CC 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x0E0 0x2D0 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x0E0 0x2D0 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x0E0 0x2D0 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x0E0 0x2D0 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0 0x2D0 0x408 0x4 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x2D0 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21 0x0E0 0x2D0 0x658 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x0E0 0x2D0 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x0E4 0x2D4 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x0E4 0x2D4 0x454 0x1 0x3
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x0E4 0x2D4 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x0E4 0x2D4 0x5B0 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4 0x2D4 0x404 0x4 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x2D4 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22 0x0E4 0x2D4 0x638 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x0E4 0x2D4 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8 0x2D8 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x0E8 0x2D8 0x464 0x1 0x3
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 0x0E8 0x2D8 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x0E8 0x2D8 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8 0x2D8 0x400 0x4 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x2D8 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23 0x0E8 0x2D8 0x63C 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x0E8 0x2D8 0x444 0x7 0x1
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC 0x2DC 0x4E4 0x0 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x0EC 0x2DC 0x3FC 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x0EC 0x2DC 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x0EC 0x2DC 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x0EC 0x2DC 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x2DC 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x0EC 0x2DC 0x000 0x6 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 0x0EC 0x2DC 0x568 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0 0x2E0 0x4E8 0x0 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x0F0 0x2E0 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x0F0 0x2E0 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x0F0 0x2E0 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x0F0 0x2E0 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x2E0 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x0F0 0x2E0 0x000 0x6 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x0F0 0x2E0 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x0F4 0x2E4 0x5CC 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24 0x0F4 0x2E4 0x640 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x0F4 0x2E4 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x0F4 0x2E4 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x0F4 0x2E4 0x428 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x2E4 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x2E4 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x0F8 0x2E8 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25 0x0F8 0x2E8 0x650 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x0F8 0x2E8 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x0F8 0x2E8 0x444 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x0F8 0x2E8 0x420 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x2E8 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x2E8 0x450 0x6 0x2
> -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x0F8 0x2E8 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x0FC 0x2EC 0x3F8 0x0 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x0FC 0x2EC 0x57C 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x0FC 0x2EC 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC 0x2EC 0x4CC 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x0FC 0x2EC 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x2EC 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x0FC 0x2EC 0x5D8 0x6 0x2
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x0FC 0x2EC 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x100 0x2F0 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x100 0x2F0 0x580 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x100 0x2F0 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100 0x2F0 0x4D0 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x100 0x2F0 0x3FC 0x4 0x2
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x2F0 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x100 0x2F0 0x000 0x6 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x100 0x2F0 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x104 0x2F4 0x3F4 0x0 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x104 0x2F4 0x584 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x104 0x2F4 0x530 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x104 0x2F4 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x104 0x2F4 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x2F4 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x104 0x2F4 0x5D4 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x104 0x2F4 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x108 0x2F8 0x5D0 0x0 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x108 0x2F8 0x588 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x108 0x2F8 0x52C 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x108 0x2F8 0x5C8 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x108 0x2F8 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x2F8 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x108 0x2F8 0x5E0 0x6 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x108 0x2F8 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x10C 0x2FC 0x4C4 0x0 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x10C 0x2FC 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x10C 0x2FC 0x534 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x10C 0x2FC 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C 0x2FC 0x424 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x2FC 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x10C 0x2FC 0x5E8 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x10C 0x2FC 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x110 0x300 0x4C0 0x0 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x110 0x300 0x430 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x110 0x300 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x110 0x300 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x110 0x300 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x300 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x110 0x300 0x5EC 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x110 0x300 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x4BC 0x0 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x4E0 0x1 0x2
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x53C 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x5F0 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x4B8 0x0 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x4DC 0x1 0x2
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x538 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x5F4 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x11C 0x30C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x11C 0x30C 0x494 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x11C 0x30C 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x11C 0x30C 0x3FC 0x3 0x3
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C 0x30C 0x41C 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x30C 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C 0x30C 0x5E4 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x11C 0x30C 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x120 0x310 0x4A4 0x0 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x120 0x310 0x498 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x120 0x310 0x44C 0x2 0x2
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x120 0x310 0x58C 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120 0x310 0x418 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x310 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120 0x310 0x5DC 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x120 0x310 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x124 0x314 0x4B4 0x0 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x124 0x314 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x124 0x314 0x564 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x124 0x314 0x5A4 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124 0x314 0x414 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x314 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x124 0x314 0x608 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x124 0x314 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x128 0x318 0x4B0 0x0 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x128 0x318 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x128 0x318 0x560 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x128 0x318 0x590 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128 0x318 0x410 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x318 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x128 0x318 0x000 0x6 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x128 0x318 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x12C 0x31C 0x4AC 0x0 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x31C 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x12C 0x31C 0x50C 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x12C 0x31C 0x594 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C 0x31C 0x40C 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x31C 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x12C 0x31C 0x5F8 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x12C 0x31C 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 0x130 0x320 0x4A8 0x0 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x320 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130 0x320 0x514 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x130 0x320 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130 0x320 0x408 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x320 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x130 0x320 0x5FC 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x130 0x320 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x134 0x324 0x4C8 0x0 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x324 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x324 0x518 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x134 0x324 0x5A8 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134 0x324 0x404 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x324 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x134 0x324 0x600 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x134 0x324 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x138 0x328 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x328 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138 0x328 0x510 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x138 0x328 0x5AC 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138 0x328 0x400 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x328 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x138 0x328 0x604 0x6 0x1
> -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x138 0x328 0x000 0x7 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x13C 0x32C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x13C 0x32C 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 0x13C 0x32C 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x13C 0x32C 0x51C 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x13C 0x32C 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 0x13C 0x32C 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 0x13C 0x32C 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x140 0x330 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x140 0x330 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 0x140 0x330 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x140 0x330 0x524 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x140 0x330 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 0x140 0x330 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 0x140 0x330 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x144 0x334 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x144 0x334 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x144 0x334 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x144 0x334 0x528 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x144 0x334 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 0x144 0x334 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 0x144 0x334 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x148 0x338 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x148 0x338 0x56C 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x148 0x338 0x44C 0x2 0x3
> -#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x148 0x338 0x520 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x148 0x338 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 0x148 0x338 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x148 0x338 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x14C 0x33C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x14C 0x33C 0x570 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x14C 0x33C 0x4D4 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 0x14C 0x33C 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x14C 0x33C 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 0x14C 0x33C 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x14C 0x33C 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x150 0x340 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x150 0x340 0x574 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x150 0x340 0x4D8 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 0x150 0x340 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x150 0x340 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 0x150 0x340 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x150 0x340 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x154 0x344 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x154 0x344 0x57C 0x1 0x2
> -#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x154 0x344 0x478 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 0x154 0x344 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x154 0x344 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 0x154 0x344 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x154 0x344 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x158 0x348 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x158 0x348 0x580 0x1 0x2
> -#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x158 0x348 0x488 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 0x158 0x348 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x158 0x348 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 0x158 0x348 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x158 0x348 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x15C 0x34C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x15C 0x34C 0x584 0x1 0x2
> -#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x15C 0x34C 0x47C 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 0x15C 0x34C 0x53C 0x3 0x2
> -#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x15C 0x34C 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 0x15C 0x34C 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x15C 0x34C 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x160 0x350 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x160 0x350 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x160 0x350 0x48C 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 0x160 0x350 0x538 0x3 0x2
> -#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x160 0x350 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 0x160 0x350 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x160 0x350 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x164 0x354 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x164 0x354 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x164 0x354 0x480 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x164 0x354 0x598 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x164 0x354 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 0x164 0x354 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x164 0x354 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x490 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x59C 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x16C 0x35C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10 0x16C 0x35C 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C 0x35C 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x16C 0x35C 0x5A0 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x16C 0x35C 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 0x16C 0x35C 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x16C 0x35C 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x170 0x360 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11 0x170 0x360 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170 0x360 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 0x170 0x360 0x58C 0x3 0x2
> -#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x170 0x360 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 0x170 0x360 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x170 0x360 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x174 0x364 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12 0x174 0x364 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x174 0x364 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x174 0x364 0x5A4 0x3 0x2
> -#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x174 0x364 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 0x174 0x364 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x174 0x364 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x590 0x3 0x2
> -#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 0x17C 0x36C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14 0x17C 0x36C 0x644 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 0x17C 0x36C 0x544 0x2 0x2
> -#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x17C 0x36C 0x594 0x3 0x2
> -#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x17C 0x36C 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 0x17C 0x36C 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x17C 0x36C 0x454 0x6 0x4
> -
> -#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x180 0x370 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15 0x180 0x370 0x648 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 0x180 0x370 0x540 0x2 0x2
> -#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x180 0x370 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x180 0x370 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 0x180 0x370 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x180 0x370 0x464 0x6 0x4
> -
> -#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x184 0x374 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16 0x184 0x374 0x64C 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x184 0x374 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x184 0x374 0x5A8 0x3 0x2
> -#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x184 0x374 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 0x184 0x374 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x184 0x374 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x188 0x378 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17 0x188 0x378 0x62C 0x1 0x3
> -#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x188 0x378 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x188 0x378 0x5AC 0x3 0x2
> -#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x188 0x378 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 0x188 0x378 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x188 0x378 0x484 0x6 0x3
> -
> -#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 0x18C 0x37C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x18C 0x37C 0x51C 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 0x18C 0x37C 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x18C 0x37C 0x434 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x18C 0x37C 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 0x18C 0x37C 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 0x190 0x380 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x190 0x380 0x524 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 0x190 0x380 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x190 0x380 0x438 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x190 0x380 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 0x190 0x380 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0x194 0x384 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x194 0x384 0x528 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0x194 0x384 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0x194 0x384 0x43C 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x194 0x384 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0x194 0x384 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 0x198 0x388 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x198 0x388 0x520 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 0x198 0x388 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x198 0x388 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x198 0x388 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 0x198 0x388 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 0x19C 0x38C 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x19C 0x38C 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 0x19C 0x38C 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x19C 0x38C 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x19C 0x38C 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 0x19C 0x38C 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x19C 0x38C 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 0x1A0 0x390 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x1A0 0x390 0x578 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 0x1A0 0x390 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 0x1A0 0x390 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x1A0 0x390 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 0x1A0 0x390 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x1A0 0x390 0x450 0x6 0x3
> -
> -#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 0x1A4 0x394 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x1A4 0x394 0x588 0x1 0x2
> -#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 0x1A4 0x394 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x1A4 0x394 0x448 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x1A4 0x394 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 0x1A4 0x394 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x1A4 0x394 0x42C 0x6 0x1
> -
> -#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 0x1A8 0x398 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x1A8 0x398 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 0x1A8 0x398 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 0x1A8 0x398 0x440 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x1A8 0x398 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 0x1A8 0x398 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x1A8 0x398 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 0x1AC 0x39C 0x54C 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x1AC 0x39C 0x424 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x1AC 0x39C 0x444 0x3 0x2
> -#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x1AC 0x39C 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 0x1AC 0x39C 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1AC 0x39C 0x5D4 0x6 0x2
> -
> -#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 0x1B0 0x3A0 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 0x1B0 0x3A0 0x548 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 0x1B0 0x3A0 0x428 0x2 0x2
> -#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x1B0 0x3A0 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x1B0 0x3A0 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 0x1B0 0x3A0 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 0x1B0 0x3A0 0x5D8 0x6 0x3
> -
> -#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 0x1B4 0x3A4 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x1B4 0x3A4 0x49C 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 0x1B4 0x3A4 0x420 0x2 0x2
> -#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02 0x1B4 0x3A4 0x60C 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x1B4 0x3A4 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 0x1B4 0x3A4 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x1B4 0x3A4 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 0x1B8 0x3A8 0x430 0x0 0x2
> -#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x1B8 0x3A8 0x4A0 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 0x1B8 0x3A8 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03 0x1B8 0x3A8 0x610 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x1B8 0x3A8 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x1B8 0x3A8 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x1B8 0x3A8 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC 0x3AC 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x1BC 0x3AC 0x458 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC 0x3AC 0x4DC 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04 0x1BC 0x3AC 0x614 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC 0x3AC 0x4F0 0x4 0x1
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC 0x3AC 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x1BC 0x3AC 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0 0x3B0 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x1C0 0x3B0 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0 0x3B0 0x4E0 0x2 0x1
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05 0x1C0 0x3B0 0x618 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x1C0 0x3B0 0x4EC 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0 0x3B0 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x1C0 0x3B0 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x1C4 0x3B4 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x1C4 0x3B4 0x45C 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x1C4 0x3B4 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06 0x1C4 0x3B4 0x61C 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4 0x3B4 0x4F8 0x4 0x1
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4 0x3B4 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x1C8 0x3B8 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x1C8 0x3B8 0x46C 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x1C8 0x3B8 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07 0x1C8 0x3B8 0x620 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8 0x3B8 0x4F4 0x4 0x1
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8 0x3B8 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x1CC 0x3BC 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x1CC 0x3BC 0x460 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x1CC 0x3BC 0x564 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08 0x1CC 0x3BC 0x624 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x1CC 0x3BC 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC 0x3BC 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x1CC 0x3BC 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x1D0 0x3C0 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x1D0 0x3C0 0x470 0x1 0x1
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x1D0 0x3C0 0x560 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09 0x1D0 0x3C0 0x628 0x3 0x1
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x1D0 0x3C0 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0 0x3C0 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x1D0 0x3C0 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x1D4 0x3C4 0x5F4 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x1D4 0x3C4 0x4C4 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x1D4 0x3C4 0x454 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x1D4 0x3C4 0x598 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x1D4 0x3C4 0x544 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4 0x3C4 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x1D8 0x3C8 0x5F0 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x1D8 0x3C8 0x4C0 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x1D8 0x3C8 0x464 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x1D8 0x3C8 0x59C 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x1D8 0x3C8 0x540 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8 0x3C8 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x1DC 0x3CC 0x5EC 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x1DC 0x3CC 0x4BC 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x1DC 0x3CC 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x1DC 0x3CC 0x5A0 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x1DC 0x3CC 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC 0x3CC 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x1DC 0x3CC 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x1E0 0x3D0 0x5E8 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x1E0 0x3D0 0x4B8 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x1E0 0x3D0 0x484 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x1E0 0x3D0 0x58C 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x1E0 0x3D0 0x44C 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0 0x3D0 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x1E0 0x3D0 0x3FC 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4 0x3D4 0x5DC 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x1E4 0x3D4 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4 0x3D4 0x4CC 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x1E4 0x3D4 0x5A4 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B 0x1E4 0x3D4 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4 0x3D4 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x1E4 0x3D4 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8 0x3D8 0x5E4 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x1E8 0x3D8 0x4A4 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8 0x3D8 0x4D0 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x1E8 0x3D8 0x590 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B 0x1E8 0x3D8 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8 0x3D8 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x1EC 0x3DC 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x1EC 0x3DC 0x000 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x1EC 0x3DC 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x1EC 0x3DC 0x594 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x1EC 0x3DC 0x4FC 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC 0x3DC 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x1F0 0x3E0 0x000 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x1F0 0x3E0 0x4C8 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x1F0 0x3E0 0x000 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x1F0 0x3E0 0x000 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0 0x3E0 0x500 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0 0x3E0 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x1F0 0x3E0 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x1F4 0x3E4 0x5F8 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 0x1F4 0x3E4 0x4A8 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x1F4 0x3E4 0x55C 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK 0x1F4 0x3E4 0x5A8 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4 0x3E4 0x508 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4 0x3E4 0x000 0x5 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x1F4 0x3E4 0x000 0x6 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x1F8 0x3E8 0x5FC 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x1F8 0x3E8 0x4AC 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x1F8 0x3E8 0x558 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x1F8 0x3E8 0x5AC 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8 0x3E8 0x504 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8 0x3E8 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x1FC 0x3EC 0x600 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x1FC 0x3EC 0x4B0 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x1FC 0x3EC 0x52C 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC 0x3EC 0x4D8 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x1FC 0x3EC 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC 0x3EC 0x000 0x5 0x0
> -
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x200 0x3F0 0x604 0x0 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x200 0x3F0 0x4B4 0x1 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x200 0x3F0 0x530 0x2 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200 0x3F0 0x4D4 0x3 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x200 0x3F0 0x000 0x4 0x0
> -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200 0x3F0 0x000 0x5 0x0
> -
> -#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */
> diff --git a/arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi b/arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi
> deleted file mode 100644
> index b0bad0d1ba36..000000000000
> --- a/arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi
> +++ /dev/null
> @@ -1,160 +0,0 @@
> -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> -/*
> - * Copyright (C) 2019
> - * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> - */
> -
> -#include "../../armv7-m.dtsi"
> -#include <dt-bindings/interrupt-controller/arm-gic.h>
> -#include <dt-bindings/clock/imxrt1050-clock.h>
> -#include <dt-bindings/gpio/gpio.h>
> -
> -/ {
> - #address-cells = <1>;
> - #size-cells = <1>;
> -
> - clocks {
> - osc: osc {
> - compatible = "fixed-clock";
> - #clock-cells = <0>;
> - clock-frequency = <24000000>;
> - };
> -
> - osc3M: osc3M {
> - compatible = "fixed-clock";
> - #clock-cells = <0>;
> - clock-frequency = <3000000>;
> - };
> - };
> -
> - soc {
> - lpuart1: serial@40184000 {
> - compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
> - reg = <0x40184000 0x4000>;
> - interrupts = <20>;
> - clocks = <&clks IMXRT1050_CLK_LPUART1>;
> - clock-names = "ipg";
> - status = "disabled";
> - };
> -
> - iomuxc: pinctrl@401f8000 {
> - compatible = "fsl,imxrt1050-iomuxc";
> - reg = <0x401f8000 0x4000>;
> - fsl,mux_mask = <0x7>;
> - };
> -
> - anatop: anatop@400d8000 {
> - compatible = "fsl,imxrt-anatop";
> - reg = <0x400d8000 0x4000>;
> - };
> -
> - clks: clock-controller@400fc000 {
> - compatible = "fsl,imxrt1050-ccm";
> - reg = <0x400fc000 0x4000>;
> - interrupts = <95>, <96>;
> - clocks = <&osc>;
> - clock-names = "osc";
> - #clock-cells = <1>;
> - assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
> - <&clks IMXRT1050_CLK_PLL1_BYPASS>,
> - <&clks IMXRT1050_CLK_PLL2_BYPASS>,
> - <&clks IMXRT1050_CLK_PLL3_BYPASS>,
> - <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
> - <&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
> - assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
> - <&clks IMXRT1050_CLK_PLL1_ARM>,
> - <&clks IMXRT1050_CLK_PLL2_SYS>,
> - <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
> - <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
> - <&clks IMXRT1050_CLK_PLL2_SYS>;
> - };
> -
> - edma1: dma-controller@400e8000 {
> - #dma-cells = <2>;
> - compatible = "fsl,imx7ulp-edma";
> - reg = <0x400e8000 0x4000>,
> - <0x400ec000 0x4000>;
> - dma-channels = <32>;
> - interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
> - <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
> - clock-names = "dma", "dmamux0";
> - clocks = <&clks IMXRT1050_CLK_DMA>,
> - <&clks IMXRT1050_CLK_DMA_MUX>;
> - };
> -
> - usdhc1: mmc@402c0000 {
> - compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
> - reg = <0x402c0000 0x4000>;
> - interrupts = <110>;
> - clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
> - <&clks IMXRT1050_CLK_AHB_PODF>,
> - <&clks IMXRT1050_CLK_USDHC1>;
> - clock-names = "ipg", "ahb", "per";
> - bus-width = <4>;
> - fsl,wp-controller;
> - no-1-8-v;
> - max-frequency = <200000000>;
> - fsl,tuning-start-tap = <20>;
> - fsl,tuning-step = <2>;
> - status = "disabled";
> - };
> -
> - gpio1: gpio@401b8000 {
> - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
> - reg = <0x401b8000 0x4000>;
> - interrupts = <80>, <81>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - };
> -
> - gpio2: gpio@401bc000 {
> - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
> - reg = <0x401bc000 0x4000>;
> - interrupts = <82>, <83>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - };
> -
> - gpio3: gpio@401c0000 {
> - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
> - reg = <0x401c0000 0x4000>;
> - interrupts = <84>, <85>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - };
> -
> - gpio4: gpio@401c4000 {
> - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
> - reg = <0x401c4000 0x4000>;
> - interrupts = <86>, <87>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - };
> -
> - gpio5: gpio@400c0000 {
> - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
> - reg = <0x400c0000 0x4000>;
> - interrupts = <88>, <89>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - };
> -
> - gpt: timer@401ec000 {
> - compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
> - reg = <0x401ec000 0x4000>;
> - interrupts = <100>;
> - clocks = <&osc3M>;
> - clock-names = "per";
> - };
> - };
> -};
> diff --git a/arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h
> deleted file mode 100644
> index 3b9fff2f08e1..000000000000
> --- a/arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h
> +++ /dev/null
> @@ -1,1561 +0,0 @@
> -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> -/*
> - * Copyright (C) 2021
> - * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
> - */
> -
> -#ifndef _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H
> -#define _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H
> -
> -#define IMX_PAD_SION 0x40000000
> -
> -/*
> - * The pin function ID is a tuple of
> - * <mux_reg conf_reg input_reg mux_mode input_val>
> - */
> -
> -#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
> -#define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
> -#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
> -#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
> -#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
> -#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
> -#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
> -#define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
> -#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x004 0x044 0x0B4 0x1 0x0
> -#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x004 0x044 0x0 0x2 0x0
> -#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x004 0x044 0x0 0x3 0x0
> -#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x004 0x044 0x0 0x5 0x0
> -#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x004 0x044 0x0AC 0x6 0x0
> -#define IOMUXC_GPIO_LPSR_01_GPIO12_IO01 0x004 0x044 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_LPSR_02_GPIO12_IO02 0x008 0x048 0x0 0xA 0x0
> -#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE00 0x008 0x048 0x0 0x0 0x0
> -#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x008 0x048 0x098 0x1 0x0
> -#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x008 0x048 0x0 0x2 0x0
> -#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x008 0x048 0x0 0x3 0x0
> -#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x008 0x048 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE01 0x00C 0x04C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS0 0x00C 0x04C 0x094 0x1 0x0
> -#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x00C 0x04C 0x0DC 0x2 0x0
> -#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x00C 0x04C 0x0 0x3 0x0
> -#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x00C 0x04C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_LPSR_03_GPIO12_IO03 0x00C 0x04C 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x010 0x050 0x088 0x0 0x0
> -#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT 0x010 0x050 0x0A0 0x1 0x0
> -#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x010 0x050 0x0D8 0x2 0x0
> -#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x010 0x050 0x0 0x3 0x0
> -#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x010 0x050 0x0 0x5 0x0
> -#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x010 0x050 0x0A8 0x6 0x0
> -#define IOMUXC_GPIO_LPSR_04_GPIO12_IO04 0x010 0x050 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_LPSR_05_GPIO12_IO05 0x014 0x054 0x0 0xA 0x0
> -#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x014 0x054 0x084 0x0 0x0
> -#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x014 0x054 0x09C 0x1 0x0
> -#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x014 0x054 0x0C8 0x2 0x1
> -#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x014 0x054 0x0 0x3 0x0
> -#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x014 0x054 0x0 0x5 0x0
> -#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x014 0x054 0x0A4 0x6 0x0
> -#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x014 0x054 0x0C4 0x7 0x0
> -
> -#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x018 0x058 0x090 0x0 0x0
> -#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x018 0x058 0x0D0 0x2 0x0
> -#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x018 0x058 0x0B0 0x3 0x1
> -#define IOMUXC_GPIO_LPSR_06_LPSPI6_PCS3 0x018 0x058 0x0 0x4 0x0
> -#define IOMUXC_GPIO_LPSR_06_GPIO_MUX6_IO06 0x018 0x058 0x0 0x5 0x0
> -#define IOMUXC_GPIO_LPSR_06_FLEXCAN3_TX 0x018 0x058 0x0 0x6 0x0
> -#define IOMUXC_GPIO_LPSR_06_PIT2_TRIGGER3 0x018 0x058 0x0 0x7 0x0
> -#define IOMUXC_GPIO_LPSR_06_LPSPI5_PCS1 0x018 0x058 0x0 0x8 0x0
> -#define IOMUXC_GPIO_LPSR_06_GPIO12_IO06 0x018 0x058 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_LPSR_07_LPI2C6_SCL 0x01C 0x05C 0x08C 0x0 0x0
> -#define IOMUXC_GPIO_LPSR_07_SAI4_RX_BCLK 0x01C 0x05C 0x0CC 0x2 0x0
> -#define IOMUXC_GPIO_LPSR_07_LPUART12_RXD 0x01C 0x05C 0x0AC 0x3 0x1
> -#define IOMUXC_GPIO_LPSR_07_LPSPI6_PCS2 0x01C 0x05C 0x0 0x4 0x0
> -#define IOMUXC_GPIO_LPSR_07_GPIO_MUX6_IO07 0x01C 0x05C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_LPSR_07_FLEXCAN3_RX 0x01C 0x05C 0x080 0x6 0x1
> -#define IOMUXC_GPIO_LPSR_07_PIT2_TRIGGER2 0x01C 0x05C 0x0 0x7 0x0
> -#define IOMUXC_GPIO_LPSR_07_LPSPI5_PCS2 0x01C 0x05C 0x0 0x8 0x0
> -#define IOMUXC_GPIO_LPSR_07_GPIO12_IO07 0x01C 0x05C 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_LPSR_08_GPIO12_IO08 0x020 0x060 0x0 0xA 0x0
> -#define IOMUXC_GPIO_LPSR_08_LPUART11_TXD 0x020 0x060 0x0A8 0x0 0x1
> -#define IOMUXC_GPIO_LPSR_08_FLEXCAN3_TX 0x020 0x060 0x0 0x1 0x0
> -#define IOMUXC_GPIO_LPSR_08_SAI4_RX_SYNC 0x020 0x060 0x0D4 0x2 0x0
> -#define IOMUXC_GPIO_LPSR_08_MIC_CLK 0x020 0x060 0x0 0x3 0x0
> -#define IOMUXC_GPIO_LPSR_08_LPSPI6_PCS1 0x020 0x060 0x0 0x4 0x0
> -#define IOMUXC_GPIO_LPSR_08_GPIO_MUX6_IO08 0x020 0x060 0x0 0x5 0x0
> -#define IOMUXC_GPIO_LPSR_08_LPI2C5_SDA 0x020 0x060 0x088 0x6 0x1
> -#define IOMUXC_GPIO_LPSR_08_PIT2_TRIGGER1 0x020 0x060 0x0 0x7 0x0
> -#define IOMUXC_GPIO_LPSR_08_LPSPI5_PCS3 0x020 0x060 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_LPSR_09_GPIO12_IO09 0x024 0x064 0x0 0xA 0x0
> -#define IOMUXC_GPIO_LPSR_09_LPUART11_RXD 0x024 0x064 0x0A4 0x0 0x1
> -#define IOMUXC_GPIO_LPSR_09_FLEXCAN3_RX 0x024 0x064 0x080 0x1 0x2
> -#define IOMUXC_GPIO_LPSR_09_PIT2_TRIGGER0 0x024 0x064 0x0 0x2 0x0
> -#define IOMUXC_GPIO_LPSR_09_MIC_BITSTREAM0 0x024 0x064 0x0B4 0x3 0x1
> -#define IOMUXC_GPIO_LPSR_09_LPSPI6_PCS0 0x024 0x064 0x0 0x4 0x0
> -#define IOMUXC_GPIO_LPSR_09_GPIO_MUX6_IO09 0x024 0x064 0x0 0x5 0x0
> -#define IOMUXC_GPIO_LPSR_09_LPI2C5_SCL 0x024 0x064 0x084 0x6 0x1
> -#define IOMUXC_GPIO_LPSR_09_SAI4_TX_DATA 0x024 0x064 0x0 0x7 0x0
> -
> -#define IOMUXC_GPIO_LPSR_10_GPIO12_IO10 0x028 0x068 0x0 0xA 0x0
> -#define IOMUXC_GPIO_LPSR_10_JTAG_MUX_TRSTB 0x028 0x068 0x0 0x0 0x0
> -#define IOMUXC_GPIO_LPSR_10_LPUART11_CTS_B 0x028 0x068 0x0 0x1 0x0
> -#define IOMUXC_GPIO_LPSR_10_LPI2C6_SDA 0x028 0x068 0x090 0x2 0x1
> -#define IOMUXC_GPIO_LPSR_10_MIC_BITSTREAM1 0x028 0x068 0x0B8 0x3 0x0
> -#define IOMUXC_GPIO_LPSR_10_LPSPI6_SCK 0x028 0x068 0x0 0x4 0x0
> -#define IOMUXC_GPIO_LPSR_10_GPIO_MUX6_IO10 0x028 0x068 0x0 0x5 0x0
> -#define IOMUXC_GPIO_LPSR_10_LPI2C5_SCLS 0x028 0x068 0x0 0x6 0x0
> -#define IOMUXC_GPIO_LPSR_10_SAI4_TX_SYNC 0x028 0x068 0x0DC 0x7 0x1
> -#define IOMUXC_GPIO_LPSR_10_LPUART12_TXD 0x028 0x068 0x0B0 0x8 0x2
> -
> -#define IOMUXC_GPIO_LPSR_11_JTAG_MUX_TDO 0x02C 0x06C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_LPSR_11_LPUART11_RTS_B 0x02C 0x06C 0x0 0x1 0x0
> -#define IOMUXC_GPIO_LPSR_11_LPI2C6_SCL 0x02C 0x06C 0x08C 0x2 0x1
> -#define IOMUXC_GPIO_LPSR_11_MIC_BITSTREAM2 0x02C 0x06C 0x0BC 0x3 0x0
> -#define IOMUXC_GPIO_LPSR_11_LPSPI6_SOUT 0x02C 0x06C 0x0 0x4 0x0
> -#define IOMUXC_GPIO_LPSR_11_GPIO_MUX6_IO11 0x02C 0x06C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_LPSR_11_LPI2C5_SDAS 0x02C 0x06C 0x0 0x6 0x0
> -#define IOMUXC_GPIO_LPSR_11_ARM_TRACE_SWO 0x02C 0x06C 0x0 0x7 0x0
> -#define IOMUXC_GPIO_LPSR_11_LPUART12_RXD 0x02C 0x06C 0x0AC 0x8 0x2
> -#define IOMUXC_GPIO_LPSR_11_GPIO12_IO11 0x02C 0x06C 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_LPSR_12_GPIO12_IO12 0x030 0x070 0x0 0xA 0x0
> -#define IOMUXC_GPIO_LPSR_12_JTAG_MUX_TDI 0x030 0x070 0x0 0x0 0x0
> -#define IOMUXC_GPIO_LPSR_12_PIT2_TRIGGER0 0x030 0x070 0x0 0x1 0x0
> -#define IOMUXC_GPIO_LPSR_12_MIC_BITSTREAM3 0x030 0x070 0x0C0 0x3 0x0
> -#define IOMUXC_GPIO_LPSR_12_LPSPI6_SIN 0x030 0x070 0x0 0x4 0x0
> -#define IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12 0x030 0x070 0x0 0x5 0x0
> -#define IOMUXC_GPIO_LPSR_12_LPI2C5_HREQ 0x030 0x070 0x0 0x6 0x0
> -#define IOMUXC_GPIO_LPSR_12_SAI4_TX_BCLK 0x030 0x070 0x0D8 0x7 0x1
> -#define IOMUXC_GPIO_LPSR_12_LPSPI5_SCK 0x030 0x070 0x098 0x8 0x1
> -
> -#define IOMUXC_GPIO_LPSR_13_GPIO12_IO13 0x034 0x074 0x0 0xA 0x0
> -#define IOMUXC_GPIO_LPSR_13_JTAG_MUX_MOD 0x034 0x074 0x0 0x0 0x0
> -#define IOMUXC_GPIO_LPSR_13_MIC_BITSTREAM1 0x034 0x074 0x0B8 0x1 0x1
> -#define IOMUXC_GPIO_LPSR_13_PIT2_TRIGGER1 0x034 0x074 0x0 0x2 0x0
> -#define IOMUXC_GPIO_LPSR_13_GPIO_MUX6_IO13 0x034 0x074 0x0 0x5 0x0
> -#define IOMUXC_GPIO_LPSR_13_SAI4_RX_DATA 0x034 0x074 0x0D0 0x7 0x1
> -#define IOMUXC_GPIO_LPSR_13_LPSPI5_PCS0 0x034 0x074 0x094 0x8 0x1
> -
> -#define IOMUXC_GPIO_LPSR_14_JTAG_MUX_TCK 0x038 0x078 0x0 0x0 0x0
> -#define IOMUXC_GPIO_LPSR_14_MIC_BITSTREAM2 0x038 0x078 0x0BC 0x1 0x1
> -#define IOMUXC_GPIO_LPSR_14_PIT2_TRIGGER2 0x038 0x078 0x0 0x2 0x0
> -#define IOMUXC_GPIO_LPSR_14_GPIO_MUX6_IO14 0x038 0x078 0x0 0x5 0x0
> -#define IOMUXC_GPIO_LPSR_14_SAI4_RX_BCLK 0x038 0x078 0x0CC 0x7 0x1
> -#define IOMUXC_GPIO_LPSR_14_LPSPI5_SOUT 0x038 0x078 0x0A0 0x8 0x1
> -#define IOMUXC_GPIO_LPSR_14_GPIO12_IO14 0x038 0x078 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_LPSR_15_GPIO12_IO15 0x03C 0x07C 0x0 0xA 0x0
> -#define IOMUXC_GPIO_LPSR_15_JTAG_MUX_TMS 0x03C 0x07C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_LPSR_15_MIC_BITSTREAM3 0x03C 0x07C 0x0C0 0x1 0x1
> -#define IOMUXC_GPIO_LPSR_15_PIT2_TRIGGER3 0x03C 0x07C 0x0 0x2 0x0
> -#define IOMUXC_GPIO_LPSR_15_GPIO_MUX6_IO15 0x03C 0x07C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_LPSR_15_SAI4_RX_SYNC 0x03C 0x07C 0x0D4 0x7 0x1
> -#define IOMUXC_GPIO_LPSR_15_LPSPI5_SIN 0x03C 0x07C 0x09C 0x8 0x1
> -
> -#define IOMUXC_WAKEUP_DIG_GPIO13_IO00 0x40C94000 0x40C94040 0x0 0x5 0x0
> -#define IOMUXC_WAKEUP_DIG_NMI_GLUE_NMI 0x40C94000 0x40C94040 0x0C4 0x7 0x1
> -
> -#define IOMUXC_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ 0x40C94004 0x40C94044 0x0 0x0 0x0
> -#define IOMUXC_PMIC_ON_REQ_DIG_GPIO13_IO01 0x40C94004 0x40C94044 0x0 0x5 0x0
> -
> -#define IOMUXC_PMIC_STBY_REQ_DIG_CCM_PMIC_VSTBY_REQ 0x40C94008 0x40C94048 0x0 0x0 0x0
> -#define IOMUXC_PMIC_STBY_REQ_DIG_GPIO13_IO02 0x40C94008 0x40C94048 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_SNVS_00_DIG_SNVS_TAMPER0 0x40C9400C 0x40C9404C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SNVS_00_DIG_GPIO13_IO03 0x40C9400C 0x40C9404C 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_SNVS_01_DIG_SNVS_TAMPER1 0x40C94010 0x40C94050 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SNVS_01_DIG_GPIO13_IO04 0x40C94010 0x40C94050 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_SNVS_02_DIG_SNVS_TAMPER2 0x40C94014 0x40C94054 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SNVS_02_DIG_GPIO13_IO05 0x40C94014 0x40C94054 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_SNVS_03_DIG_SNVS_TAMPER3 0x40C94018 0x40C94058 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SNVS_03_DIG_GPIO13_IO06 0x40C94018 0x40C94058 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_SNVS_04_DIG_SNVS_TAMPER4 0x40C9401C 0x40C9405C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SNVS_04_DIG_GPIO13_IO07 0x40C9401C 0x40C9405C 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_SNVS_05_DIG_SNVS_TAMPER5 0x40C94020 0x40C94060 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SNVS_05_DIG_GPIO13_IO08 0x40C94020 0x40C94060 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_SNVS_06_DIG_SNVS_TAMPER6 0x40C94024 0x40C94064 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SNVS_06_DIG_GPIO13_IO09 0x40C94024 0x40C94064 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_SNVS_07_DIG_SNVS_TAMPER7 0x40C94028 0x40C94068 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SNVS_07_DIG_GPIO13_IO10 0x40C94028 0x40C94068 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_SNVS_08_DIG_SNVS_TAMPER8 0x40C9402C 0x40C9406C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SNVS_08_DIG_GPIO13_IO11 0x40C9402C 0x40C9406C 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_SNVS_09_DIG_SNVS_TAMPER9 0x40C94030 0x40C94070 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SNVS_09_DIG_GPIO13_IO12 0x40C94030 0x40C94070 0x0 0x5 0x0
> -
> -#define IOMUXC_TEST_MODE_DIG 0x0 0x40C94034 0x0 0x0 0x0
> -
> -#define IOMUXC_POR_B_DIG 0x0 0x40C94038 0x0 0x0 0x0
> -
> -#define IOMUXC_ONOFF_DIG 0x0 0x40C9403C 0x0 0x0 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 0x010 0x254 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A 0x010 0x254 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 0x010 0x254 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_00_FLEXIO1_D00 0x010 0x254 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 0x010 0x254 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01 0x014 0x258 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 0x014 0x258 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B 0x014 0x258 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01 0x014 0x258 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_01_FLEXIO1_D01 0x014 0x258 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 0x018 0x25C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A 0x018 0x25C 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02 0x018 0x25C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_02_FLEXIO1_D02 0x018 0x25C 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02 0x018 0x25C 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 0x01C 0x260 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B 0x01C 0x260 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03 0x01C 0x260 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_03_FLEXIO1_D03 0x01C 0x260 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03 0x01C 0x260 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04 0x020 0x264 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 0x020 0x264 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A 0x020 0x264 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04 0x020 0x264 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_04_FLEXIO1_D04 0x020 0x264 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 0x024 0x268 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B 0x024 0x268 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05 0x024 0x268 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_05_FLEXIO1_D05 0x024 0x268 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05 0x024 0x268 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 0x028 0x26C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A 0x028 0x26C 0x518 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06 0x028 0x26C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_06_FLEXIO1_D06 0x028 0x26C 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06 0x028 0x26C 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07 0x02C 0x270 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 0x02C 0x270 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B 0x02C 0x270 0x524 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07 0x02C 0x270 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_07_FLEXIO1_D07 0x02C 0x270 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 0x030 0x274 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A 0x030 0x274 0x51C 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08 0x030 0x274 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_08_FLEXIO1_D08 0x030 0x274 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08 0x030 0x274 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 0x034 0x278 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B 0x034 0x278 0x528 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1 0x034 0x278 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09 0x034 0x278 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_09_FLEXIO1_D09 0x034 0x278 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09 0x034 0x278 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 0x038 0x27C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A 0x038 0x27C 0x520 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2 0x038 0x27C 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10 0x038 0x27C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_10_FLEXIO1_D10 0x038 0x27C 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10 0x038 0x27C 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11 0x03C 0x280 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 0x03C 0x280 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B 0x03C 0x280 0x52C 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1 0x03C 0x280 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11 0x03C 0x280 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_11_FLEXIO1_D11 0x03C 0x280 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 0x040 0x284 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_12_XBAR1_INOUT04 0x040 0x284 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2 0x040 0x284 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12 0x040 0x284 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_12_FLEXIO1_D12 0x040 0x284 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12 0x040 0x284 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 0x044 0x288 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_13_XBAR1_INOUT05 0x044 0x288 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3 0x044 0x288 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13 0x044 0x288 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_13_FLEXIO1_D13 0x044 0x288 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13 0x044 0x288 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14 0x048 0x28C 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 0x048 0x28C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_14_XBAR1_INOUT06 0x048 0x28C 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_14_GPT5_CLK 0x048 0x28C 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14 0x048 0x28C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_14_FLEXIO1_D14 0x048 0x28C 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 0x04C 0x290 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_15_XBAR1_INOUT07 0x04C 0x290 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15 0x04C 0x290 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_15_FLEXIO1_D15 0x04C 0x290 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15 0x04C 0x290 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 0x050 0x294 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_16_XBAR1_INOUT08 0x050 0x294 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16 0x050 0x294 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_16_FLEXIO1_D16 0x050 0x294 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16 0x050 0x294 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17 0x054 0x298 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 0x054 0x298 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A 0x054 0x298 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_17_TMR1_TIMER0 0x054 0x298 0x63C 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17 0x054 0x298 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_17_FLEXIO1_D17 0x054 0x298 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 0x058 0x29C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B 0x058 0x29C 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_18_TMR2_TIMER0 0x058 0x29C 0x648 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18 0x058 0x29C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_18_FLEXIO1_D18 0x058 0x29C 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18 0x058 0x29C 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 0x05C 0x2A0 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A 0x05C 0x2A0 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_19_TMR3_TIMER0 0x05C 0x2A0 0x654 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19 0x05C 0x2A0 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_19_FLEXIO1_D19 0x05C 0x2A0 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19 0x05C 0x2A0 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 0x060 0x2A4 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B 0x060 0x2A4 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_20_TMR4_TIMER0 0x060 0x2A4 0x660 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20 0x060 0x2A4 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_20_FLEXIO1_D20 0x060 0x2A4 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20 0x060 0x2A4 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21 0x064 0x2A8 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 0x064 0x2A8 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A 0x064 0x2A8 0x53C 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21 0x064 0x2A8 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_21_FLEXIO1_D21 0x064 0x2A8 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22 0x068 0x2AC 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 0x068 0x2AC 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B 0x068 0x2AC 0x54C 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22 0x068 0x2AC 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_22_FLEXIO1_D22 0x068 0x2AC 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 0x06C 0x2B0 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A 0x06C 0x2B0 0x500 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23 0x06C 0x2B0 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_23_FLEXIO1_D23 0x06C 0x2B0 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23 0x06C 0x2B0 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24 0x070 0x2B4 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_24_SEMC_CAS 0x070 0x2B4 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B 0x070 0x2B4 0x50C 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24 0x070 0x2B4 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_24_FLEXIO1_D24 0x070 0x2B4 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25 0x074 0x2B8 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_25_SEMC_RAS 0x074 0x2B8 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A 0x074 0x2B8 0x504 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25 0x074 0x2B8 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_25_FLEXIO1_D25 0x074 0x2B8 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_26_SEMC_CLK 0x078 0x2BC 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B 0x078 0x2BC 0x510 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26 0x078 0x2BC 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_26_FLEXIO1_D26 0x078 0x2BC 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26 0x078 0x2BC 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27 0x07C 0x2C0 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_27_SEMC_CKE 0x07C 0x2C0 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A 0x07C 0x2C0 0x508 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27 0x07C 0x2C0 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_27_FLEXIO1_D27 0x07C 0x2C0 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28 0x080 0x2C4 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_28_SEMC_WE 0x080 0x2C4 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B 0x080 0x2C4 0x514 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28 0x080 0x2C4 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_28_FLEXIO1_D28 0x080 0x2C4 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 0x084 0x2C8 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A 0x084 0x2C8 0x530 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29 0x084 0x2C8 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_29_FLEXIO1_D29 0x084 0x2C8 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29 0x084 0x2C8 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 0x088 0x2CC 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B 0x088 0x2CC 0x540 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30 0x088 0x2CC 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_30_FLEXIO1_D30 0x088 0x2CC 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30 0x088 0x2CC 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31 0x08C 0x2D0 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 0x08C 0x2D0 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A 0x08C 0x2D0 0x534 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31 0x08C 0x2D0 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_31_FLEXIO1_D31 0x08C 0x2D0 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00 0x090 0x2D4 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 0x090 0x2D4 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B 0x090 0x2D4 0x544 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00 0x090 0x2D4 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 0x094 0x2D8 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A 0x094 0x2D8 0x538 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01 0x094 0x2D8 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01 0x094 0x2D8 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02 0x098 0x2DC 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 0x098 0x2DC 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B 0x098 0x2DC 0x548 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02 0x098 0x2DC 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03 0x09C 0x2E0 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 0x09C 0x2E0 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_35_XBAR1_INOUT09 0x09C 0x2E0 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03 0x09C 0x2E0 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 0x0A0 0x2E4 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_36_XBAR1_INOUT10 0x0A0 0x2E4 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04 0x0A0 0x2E4 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04 0x0A0 0x2E4 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05 0x0A4 0x2E8 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 0x0A4 0x2E8 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_37_XBAR1_INOUT11 0x0A4 0x2E8 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05 0x0A4 0x2E8 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06 0x0A8 0x2EC 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 0x0A8 0x2EC 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A 0x0A8 0x2EC 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_38_TMR1_TIMER1 0x0A8 0x2EC 0x640 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06 0x0A8 0x2EC 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_39_SEMC_DQS 0x0AC 0x2F0 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B 0x0AC 0x2F0 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_39_TMR2_TIMER1 0x0AC 0x2F0 0x64C 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07 0x0AC 0x2F0 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07 0x0AC 0x2F0 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_40_SEMC_RDY 0x0B0 0x2F4 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_40_XBAR1_INOUT12 0x0B0 0x2F4 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT 0x0B0 0x2F4 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B1_40_LPUART6_TXD 0x0B0 0x2F4 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08 0x0B0 0x2F4 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC 0x0B0 0x2F4 0x0 0x7 0x0
> -#define IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1 0x0B0 0x2F4 0x0 0x9 0x0
> -#define IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08 0x0B0 0x2F4 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09 0x0B4 0x2F8 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00 0x0B4 0x2F8 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B1_41_XBAR1_INOUT13 0x0B4 0x2F8 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B1_41_MQS_LEFT 0x0B4 0x2F8 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B1_41_LPUART6_RXD 0x0B4 0x2F8 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 0x0B4 0x2F8 0x0 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09 0x0B4 0x2F8 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO 0x0B4 0x2F8 0x4C8 0x7 0x0
> -#define IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2 0x0B4 0x2F8 0x0 0x9 0x0
> -
> -#define IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 0x0B8 0x2FC 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M 0x0B8 0x2FC 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_00_TMR3_TIMER1 0x0B8 0x2FC 0x658 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B 0x0B8 0x2FC 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 0x0B8 0x2FC 0x0 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10 0x0B8 0x2FC 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_00_XBAR1_INOUT20 0x0B8 0x2FC 0x6D8 0x6 0x0
> -#define IOMUXC_GPIO_EMC_B2_00_ENET_QOS_1588_EVENT1_OUT 0x0B8 0x2FC 0x0 0x7 0x0
> -#define IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK 0x0B8 0x2FC 0x5D0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL 0x0B8 0x2FC 0x5B4 0x9 0x0
> -#define IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10 0x0B8 0x2FC 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A 0x0B8 0x2FC 0x530 0xB 0x1
> -
> -#define IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 0x0BC 0x300 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B 0x0BC 0x300 0x6D0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_01_TMR4_TIMER1 0x0BC 0x300 0x664 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B 0x0BC 0x300 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 0x0BC 0x300 0x0 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11 0x0BC 0x300 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_01_XBAR1_INOUT21 0x0BC 0x300 0x6DC 0x6 0x0
> -#define IOMUXC_GPIO_EMC_B2_01_ENET_QOS_1588_EVENT1_IN 0x0BC 0x300 0x0 0x7 0x0
> -#define IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0 0x0BC 0x300 0x5CC 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA 0x0BC 0x300 0x5B8 0x9 0x0
> -#define IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11 0x0BC 0x300 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B 0x0BC 0x300 0x540 0xB 0x1
> -
> -#define IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 0x0C0 0x304 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_02_USDHC2_WP 0x0C0 0x304 0x6D4 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_02_VIDEO_MUX_CSI_DATA23 0x0C0 0x304 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 0x0C0 0x304 0x0 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12 0x0C0 0x304 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_02_XBAR1_INOUT22 0x0C0 0x304 0x6E0 0x6 0x0
> -#define IOMUXC_GPIO_EMC_B2_02_ENET_QOS_1588_EVENT1_AUX_IN 0x0C0 0x304 0x0 0x7 0x0
> -#define IOMUXC_GPIO_EMC_B2_02_LPSPI1_SOUT 0x0C0 0x304 0x5D8 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12 0x0C0 0x304 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A 0x0C0 0x304 0x534 0xB 0x1
> -
> -#define IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 0x0C4 0x308 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT 0x0C4 0x308 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_03_VIDEO_MUX_CSI_DATA22 0x0C4 0x308 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 0x0C4 0x308 0x0 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13 0x0C4 0x308 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_03_XBAR1_INOUT23 0x0C4 0x308 0x6E4 0x6 0x0
> -#define IOMUXC_GPIO_EMC_B2_03_ENET_1G_TX_DATA03 0x0C4 0x308 0x0 0x7 0x0
> -#define IOMUXC_GPIO_EMC_B2_03_LPSPI1_SIN 0x0C4 0x308 0x5D4 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13 0x0C4 0x308 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B 0x0C4 0x308 0x544 0xB 0x1
> -
> -#define IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 0x0C8 0x30C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B 0x0C8 0x30C 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK 0x0C8 0x30C 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_04_VIDEO_MUX_CSI_DATA21 0x0C8 0x30C 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 0x0C8 0x30C 0x0 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14 0x0C8 0x30C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_04_XBAR1_INOUT24 0x0C8 0x30C 0x6E8 0x6 0x0
> -#define IOMUXC_GPIO_EMC_B2_04_ENET_1G_TX_DATA02 0x0C8 0x30C 0x0 0x7 0x0
> -#define IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK 0x0C8 0x30C 0x600 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14 0x0C8 0x30C 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A 0x0C8 0x30C 0x538 0xB 0x1
> -
> -#define IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 0x0CC 0x310 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_05_GPT3_CLK 0x0CC 0x310 0x598 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC 0x0CC 0x310 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_05_VIDEO_MUX_CSI_DATA20 0x0CC 0x310 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 0x0CC 0x310 0x0 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15 0x0CC 0x310 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_05_XBAR1_INOUT25 0x0CC 0x310 0x6EC 0x6 0x0
> -#define IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK 0x0CC 0x310 0x4CC 0x7 0x0
> -#define IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0 0x0CC 0x310 0x5F0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER0 0x0CC 0x310 0x0 0x9 0x0
> -#define IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15 0x0CC 0x310 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B 0x0CC 0x310 0x548 0xB 0x1
> -
> -#define IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 0x0D0 0x314 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1 0x0D0 0x314 0x590 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16 0x0D0 0x314 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK 0x0D0 0x314 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A 0x0D0 0x314 0x53C 0xB 0x1
> -#define IOMUXC_GPIO_EMC_B2_06_VIDEO_MUX_CSI_DATA19 0x0D0 0x314 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 0x0D0 0x314 0x0 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16 0x0D0 0x314 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_06_XBAR1_INOUT26 0x0D0 0x314 0x6F0 0x6 0x0
> -#define IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER 0x0D0 0x314 0x0 0x7 0x0
> -#define IOMUXC_GPIO_EMC_B2_06_LPSPI3_SOUT 0x0D0 0x314 0x608 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER1 0x0D0 0x314 0x0 0x9 0x0
> -
> -#define IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 0x0D4 0x318 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2 0x0D4 0x318 0x594 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA 0x0D4 0x318 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_07_VIDEO_MUX_CSI_DATA18 0x0D4 0x318 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS 0x0D4 0x318 0x0 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17 0x0D4 0x318 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_07_XBAR1_INOUT27 0x0D4 0x318 0x6F4 0x6 0x0
> -#define IOMUXC_GPIO_EMC_B2_07_ENET_1G_RX_DATA03 0x0D4 0x318 0x4DC 0x7 0x0
> -#define IOMUXC_GPIO_EMC_B2_07_LPSPI3_SIN 0x0D4 0x318 0x604 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER2 0x0D4 0x318 0x0 0x9 0x0
> -#define IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17 0x0D4 0x318 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B 0x0D4 0x318 0x54C 0xB 0x1
> -
> -#define IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 0x0D8 0x31C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1 0x0D8 0x31C 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA 0x0D8 0x31C 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_08_VIDEO_MUX_CSI_DATA17 0x0D8 0x31C 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B 0x0D8 0x31C 0x0 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18 0x0D8 0x31C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_08_XBAR1_INOUT28 0x0D8 0x31C 0x6F8 0x6 0x0
> -#define IOMUXC_GPIO_EMC_B2_08_ENET_1G_RX_DATA02 0x0D8 0x31C 0x4D8 0x7 0x0
> -#define IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1 0x0D8 0x31C 0x5F4 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER3 0x0D8 0x31C 0x0 0x9 0x0
> -#define IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18 0x0D8 0x31C 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19 0x0DC 0x320 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 0x0DC 0x320 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2 0x0DC 0x320 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK 0x0DC 0x320 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_09_VIDEO_MUX_CSI_DATA16 0x0DC 0x320 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK 0x0DC 0x320 0x0 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19 0x0DC 0x320 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_09_XBAR1_INOUT29 0x0DC 0x320 0x6FC 0x6 0x0
> -#define IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS 0x0DC 0x320 0x0 0x7 0x0
> -#define IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2 0x0DC 0x320 0x5F8 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_09_TMR1_TIMER0 0x0DC 0x320 0x63C 0x9 0x1
> -
> -#define IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20 0x0E0 0x324 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 0x0E0 0x324 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3 0x0E0 0x324 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC 0x0E0 0x324 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_10_VIDEO_MUX_CSI_FIELD 0x0E0 0x324 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK 0x0E0 0x324 0x58C 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20 0x0E0 0x324 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_10_XBAR1_INOUT30 0x0E0 0x324 0x700 0x6 0x0
> -#define IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL 0x0E0 0x324 0x0 0x7 0x0
> -#define IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3 0x0E0 0x324 0x5FC 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_10_TMR1_TIMER1 0x0E0 0x324 0x640 0x9 0x1
> -
> -#define IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 0x0E4 0x328 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_11_SPDIF_IN 0x0E4 0x328 0x6B4 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_11_ENET_1G_TX_DATA00 0x0E4 0x328 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC 0x0E4 0x328 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B 0x0E4 0x328 0x0 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21 0x0E4 0x328 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_11_XBAR1_INOUT31 0x0E4 0x328 0x704 0x6 0x0
> -#define IOMUXC_GPIO_EMC_B2_11_EMVSIM1_IO 0x0E4 0x328 0x69C 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_11_TMR1_TIMER2 0x0E4 0x328 0x644 0x9 0x0
> -#define IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21 0x0E4 0x328 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 0x0E8 0x32C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT 0x0E8 0x32C 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_12_ENET_1G_TX_DATA01 0x0E8 0x32C 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK 0x0E8 0x32C 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS 0x0E8 0x32C 0x0 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22 0x0E8 0x32C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_12_XBAR1_INOUT32 0x0E8 0x32C 0x708 0x6 0x0
> -#define IOMUXC_GPIO_EMC_B2_12_EMVSIM1_CLK 0x0E8 0x32C 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_12_TMR1_TIMER3 0x0E8 0x32C 0x0 0x9 0x0
> -#define IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22 0x0E8 0x32C 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23 0x0EC 0x330 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 0x0EC 0x330 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN 0x0EC 0x330 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA 0x0EC 0x330 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 0x0EC 0x330 0x57C 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23 0x0EC 0x330 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_13_XBAR1_INOUT33 0x0EC 0x330 0x70C 0x6 0x0
> -#define IOMUXC_GPIO_EMC_B2_13_EMVSIM1_RST 0x0EC 0x330 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_13_TMR2_TIMER0 0x0EC 0x330 0x648 0x9 0x1
> -
> -#define IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 0x0F0 0x334 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO 0x0F0 0x334 0x4E8 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA 0x0F0 0x334 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 0x0F0 0x334 0x580 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24 0x0F0 0x334 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_14_XBAR1_INOUT34 0x0F0 0x334 0x710 0x6 0x0
> -#define IOMUXC_GPIO_EMC_B2_14_SFA_ipp_do_atx_clk_under_test 0x0F0 0x334 0x0 0x7 0x0
> -#define IOMUXC_GPIO_EMC_B2_14_EMVSIM1_SVEN 0x0F0 0x334 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_14_TMR2_TIMER1 0x0F0 0x334 0x64C 0x9 0x1
> -#define IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24 0x0F0 0x334 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 0x0F4 0x338 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_15_ENET_1G_RX_DATA00 0x0F4 0x338 0x4D0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK 0x0F4 0x338 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 0x0F4 0x338 0x584 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25 0x0F4 0x338 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_15_XBAR1_INOUT35 0x0F4 0x338 0x714 0x6 0x0
> -#define IOMUXC_GPIO_EMC_B2_15_EMVSIM1_PD 0x0F4 0x338 0x6A0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_15_TMR2_TIMER2 0x0F4 0x338 0x650 0x9 0x0
> -#define IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25 0x0F4 0x338 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26 0x0F8 0x33C 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 0x0F8 0x33C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_16_XBAR1_INOUT14 0x0F8 0x33C 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_16_ENET_1G_RX_DATA01 0x0F8 0x33C 0x4D4 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC 0x0F8 0x33C 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 0x0F8 0x33C 0x588 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26 0x0F8 0x33C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_16_EMVSIM1_POWER_FAIL 0x0F8 0x33C 0x6A4 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_16_TMR2_TIMER3 0x0F8 0x33C 0x0 0x9 0x0
> -
> -#define IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 0x0FC 0x340 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_17_XBAR1_INOUT15 0x0FC 0x340 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN 0x0FC 0x340 0x4E0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK 0x0FC 0x340 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 0x0FC 0x340 0x0 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27 0x0FC 0x340 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_17_WDOG1_ANY 0x0FC 0x340 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_17_TMR3_TIMER0 0x0FC 0x340 0x654 0x9 0x1
> -#define IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27 0x0FC 0x340 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 0x100 0x344 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_18_XBAR1_INOUT16 0x100 0x344 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER 0x100 0x344 0x4E4 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_18_EWM_OUT_B 0x100 0x344 0x0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 0x100 0x344 0x0 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28 0x100 0x344 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS 0x100 0x344 0x550 0x6 0x0
> -#define IOMUXC_GPIO_EMC_B2_18_WDOG1_B 0x100 0x344 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_18_TMR3_TIMER1 0x100 0x344 0x658 0x9 0x1
> -#define IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28 0x100 0x344 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29 0x104 0x348 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 0x104 0x348 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_19_ENET_MDC 0x104 0x348 0x0 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC 0x104 0x348 0x0 0x2 0x0
> -#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK 0x104 0x348 0x4C4 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 0x104 0x348 0x0 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 0x104 0x348 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_19_ENET_QOS_MDC 0x104 0x348 0x0 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_19_TMR3_TIMER2 0x104 0x348 0x65C 0x9 0x0
> -
> -#define IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30 0x108 0x34C 0x0 0xA 0x0
> -#define IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 0x108 0x34C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_EMC_B2_20_ENET_MDIO 0x108 0x34C 0x4AC 0x1 0x0
> -#define IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO 0x108 0x34C 0x4C8 0x2 0x1
> -#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_REF_CLK 0x108 0x34C 0x4A0 0x3 0x0
> -#define IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 0x108 0x34C 0x0 0x4 0x0
> -#define IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 0x108 0x34C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_MDIO 0x108 0x34C 0x4EC 0x8 0x0
> -#define IOMUXC_GPIO_EMC_B2_20_TMR3_TIMER3 0x108 0x34C 0x0 0x9 0x0
> -
> -#define IOMUXC_GPIO_AD_00_GPIO8_IO31 0x10C 0x350 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_00_EMVSIM1_IO 0x10C 0x350 0x69C 0x0 0x1
> -#define IOMUXC_GPIO_AD_00_FLEXCAN2_TX 0x10C 0x350 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN 0x10C 0x350 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_00_GPT2_CAPTURE1 0x10C 0x350 0x0 0x3 0x0
> -#define IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A 0x10C 0x350 0x500 0x4 0x1
> -#define IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31 0x10C 0x350 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_00_LPUART7_TXD 0x10C 0x350 0x630 0x6 0x0
> -#define IOMUXC_GPIO_AD_00_FLEXIO2_D00 0x10C 0x350 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B 0x10C 0x350 0x0 0x9 0x0
> -
> -#define IOMUXC_GPIO_AD_01_GPIO9_IO00 0x110 0x354 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_01_EMVSIM1_CLK 0x110 0x354 0x0 0x0 0x0
> -#define IOMUXC_GPIO_AD_01_FLEXCAN2_RX 0x110 0x354 0x49C 0x1 0x0
> -#define IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT 0x110 0x354 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_01_GPT2_CAPTURE2 0x110 0x354 0x0 0x3 0x0
> -#define IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B 0x110 0x354 0x50C 0x4 0x1
> -#define IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00 0x110 0x354 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_01_LPUART7_RXD 0x110 0x354 0x62C 0x6 0x0
> -#define IOMUXC_GPIO_AD_01_FLEXIO2_D01 0x110 0x354 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B 0x110 0x354 0x0 0x9 0x0
> -
> -#define IOMUXC_GPIO_AD_02_GPIO9_IO01 0x114 0x358 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_02_EMVSIM1_RST 0x114 0x358 0x0 0x0 0x0
> -#define IOMUXC_GPIO_AD_02_LPUART7_CTS_B 0x114 0x358 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN 0x114 0x358 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_02_GPT2_COMPARE1 0x114 0x358 0x0 0x3 0x0
> -#define IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A 0x114 0x358 0x504 0x4 0x1
> -#define IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01 0x114 0x358 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_02_LPUART8_TXD 0x114 0x358 0x638 0x6 0x0
> -#define IOMUXC_GPIO_AD_02_FLEXIO2_D02 0x114 0x358 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 0x114 0x358 0x0 0x9 0x0
> -
> -#define IOMUXC_GPIO_AD_03_GPIO9_IO02 0x118 0x35C 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_03_EMVSIM1_SVEN 0x118 0x35C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_AD_03_LPUART7_RTS_B 0x118 0x35C 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT 0x118 0x35C 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_03_GPT2_COMPARE2 0x118 0x35C 0x0 0x3 0x0
> -#define IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B 0x118 0x35C 0x510 0x4 0x1
> -#define IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02 0x118 0x35C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_03_LPUART8_RXD 0x118 0x35C 0x634 0x6 0x0
> -#define IOMUXC_GPIO_AD_03_FLEXIO2_D03 0x118 0x35C 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 0x118 0x35C 0x0 0x9 0x0
> -
> -#define IOMUXC_GPIO_AD_04_EMVSIM1_PD 0x11C 0x360 0x6A0 0x0 0x1
> -#define IOMUXC_GPIO_AD_04_LPUART8_CTS_B 0x11C 0x360 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN 0x11C 0x360 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_04_GPT2_COMPARE3 0x11C 0x360 0x0 0x3 0x0
> -#define IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A 0x11C 0x360 0x508 0x4 0x1
> -#define IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03 0x11C 0x360 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_04_WDOG1_B 0x11C 0x360 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_04_FLEXIO2_D04 0x11C 0x360 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_04_TMR4_TIMER0 0x11C 0x360 0x660 0x9 0x1
> -#define IOMUXC_GPIO_AD_04_GPIO9_IO03 0x11C 0x360 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_AD_05_EMVSIM1_POWER_FAIL 0x120 0x364 0x6A4 0x0 0x1
> -#define IOMUXC_GPIO_AD_05_LPUART8_RTS_B 0x120 0x364 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT 0x120 0x364 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_05_GPT2_CLK 0x120 0x364 0x0 0x3 0x0
> -#define IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B 0x120 0x364 0x514 0x4 0x1
> -#define IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04 0x120 0x364 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_05_WDOG2_B 0x120 0x364 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_05_FLEXIO2_D05 0x120 0x364 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_05_TMR4_TIMER1 0x120 0x364 0x664 0x9 0x1
> -#define IOMUXC_GPIO_AD_05_GPIO9_IO04 0x120 0x364 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_AD_06_USB_OTG2_OC 0x124 0x368 0x6B8 0x0 0x0
> -#define IOMUXC_GPIO_AD_06_FLEXCAN1_TX 0x124 0x368 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_06_EMVSIM2_IO 0x124 0x368 0x6A8 0x2 0x0
> -#define IOMUXC_GPIO_AD_06_GPT3_CAPTURE1 0x124 0x368 0x590 0x3 0x1
> -#define IOMUXC_GPIO_AD_06_VIDEO_MUX_CSI_DATA15 0x124 0x368 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05 0x124 0x368 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN 0x124 0x368 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_06_FLEXIO2_D06 0x124 0x368 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_06_TMR4_TIMER2 0x124 0x368 0x668 0x9 0x0
> -#define IOMUXC_GPIO_AD_06_GPIO9_IO05 0x124 0x368 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X 0x124 0x368 0x0 0xB 0x0
> -
> -#define IOMUXC_GPIO_AD_07_USB_OTG2_PWR 0x128 0x36C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_AD_07_FLEXCAN1_RX 0x128 0x36C 0x498 0x1 0x0
> -#define IOMUXC_GPIO_AD_07_EMVSIM2_CLK 0x128 0x36C 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_07_GPT3_CAPTURE2 0x128 0x36C 0x594 0x3 0x1
> -#define IOMUXC_GPIO_AD_07_VIDEO_MUX_CSI_DATA14 0x128 0x36C 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06 0x128 0x36C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT 0x128 0x36C 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_07_FLEXIO2_D07 0x128 0x36C 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_07_TMR4_TIMER3 0x128 0x36C 0x0 0x9 0x0
> -#define IOMUXC_GPIO_AD_07_GPIO9_IO06 0x128 0x36C 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X 0x128 0x36C 0x0 0xB 0x0
> -
> -#define IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID 0x12C 0x370 0x6C4 0x0 0x0
> -#define IOMUXC_GPIO_AD_08_LPI2C1_SCL 0x12C 0x370 0x5AC 0x1 0x0
> -#define IOMUXC_GPIO_AD_08_EMVSIM2_RST 0x12C 0x370 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_08_GPT3_COMPARE1 0x12C 0x370 0x0 0x3 0x0
> -#define IOMUXC_GPIO_AD_08_VIDEO_MUX_CSI_DATA13 0x12C 0x370 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07 0x12C 0x370 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN 0x12C 0x370 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_08_FLEXIO2_D08 0x12C 0x370 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_08_GPIO9_IO07 0x12C 0x370 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X 0x12C 0x370 0x0 0xB 0x0
> -
> -#define IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID 0x130 0x374 0x6C0 0x0 0x0
> -#define IOMUXC_GPIO_AD_09_LPI2C1_SDA 0x130 0x374 0x5B0 0x1 0x0
> -#define IOMUXC_GPIO_AD_09_EMVSIM2_SVEN 0x130 0x374 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_09_GPT3_COMPARE2 0x130 0x374 0x0 0x3 0x0
> -#define IOMUXC_GPIO_AD_09_VIDEO_MUX_CSI_DATA12 0x130 0x374 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08 0x130 0x374 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT 0x130 0x374 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_09_FLEXIO2_D09 0x130 0x374 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_09_GPIO9_IO08 0x130 0x374 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X 0x130 0x374 0x0 0xB 0x0
> -
> -#define IOMUXC_GPIO_AD_10_USB_OTG1_PWR 0x134 0x378 0x0 0x0 0x0
> -#define IOMUXC_GPIO_AD_10_LPI2C1_SCLS 0x134 0x378 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_10_EMVSIM2_PD 0x134 0x378 0x6AC 0x2 0x0
> -#define IOMUXC_GPIO_AD_10_GPT3_COMPARE3 0x134 0x378 0x0 0x3 0x0
> -#define IOMUXC_GPIO_AD_10_VIDEO_MUX_CSI_DATA11 0x134 0x378 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09 0x134 0x378 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN 0x134 0x378 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_10_FLEXIO2_D10 0x134 0x378 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_10_GPIO9_IO09 0x134 0x378 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X 0x134 0x378 0x0 0xB 0x0
> -
> -#define IOMUXC_GPIO_AD_11_USB_OTG1_OC 0x138 0x37C 0x6BC 0x0 0x0
> -#define IOMUXC_GPIO_AD_11_LPI2C1_SDAS 0x138 0x37C 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_11_EMVSIM2_POWER_FAIL 0x138 0x37C 0x6B0 0x2 0x0
> -#define IOMUXC_GPIO_AD_11_GPT3_CLK 0x138 0x37C 0x598 0x3 0x1
> -#define IOMUXC_GPIO_AD_11_VIDEO_MUX_CSI_DATA10 0x138 0x37C 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10 0x138 0x37C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT 0x138 0x37C 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_11_FLEXIO2_D11 0x138 0x37C 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_11_GPIO9_IO10 0x138 0x37C 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X 0x138 0x37C 0x0 0xB 0x0
> -
> -#define IOMUXC_GPIO_AD_12_SPDIF_LOCK 0x13C 0x380 0x0 0x0 0x0
> -#define IOMUXC_GPIO_AD_12_LPI2C1_HREQ 0x13C 0x380 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_12_GPT1_CAPTURE1 0x13C 0x380 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03 0x13C 0x380 0x570 0x3 0x0
> -#define IOMUXC_GPIO_AD_12_VIDEO_MUX_CSI_PIXCLK 0x13C 0x380 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11 0x13C 0x380 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_12_ENET_TX_DATA03 0x13C 0x380 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_12_FLEXIO2_D12 0x13C 0x380 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_12_EWM_OUT_B 0x13C 0x380 0x0 0x9 0x0
> -#define IOMUXC_GPIO_AD_12_GPIO9_IO11 0x13C 0x380 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X 0x13C 0x380 0x0 0xB 0x0
> -
> -#define IOMUXC_GPIO_AD_13_SPDIF_SR_CLK 0x140 0x384 0x0 0x0 0x0
> -#define IOMUXC_GPIO_AD_13_PIT1_TRIGGER0 0x140 0x384 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_13_GPT1_CAPTURE2 0x140 0x384 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02 0x140 0x384 0x56C 0x3 0x0
> -#define IOMUXC_GPIO_AD_13_VIDEO_MUX_CSI_MCLK 0x140 0x384 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12 0x140 0x384 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_13_ENET_TX_DATA02 0x140 0x384 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_13_FLEXIO2_D13 0x140 0x384 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_13_REF_CLK_32K 0x140 0x384 0x0 0x9 0x0
> -#define IOMUXC_GPIO_AD_13_GPIO9_IO12 0x140 0x384 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X 0x140 0x384 0x0 0xB 0x0
> -
> -#define IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK 0x144 0x388 0x0 0x0 0x0
> -#define IOMUXC_GPIO_AD_14_REF_CLK_24M 0x144 0x388 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_14_GPT1_COMPARE1 0x144 0x388 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01 0x144 0x388 0x568 0x3 0x0
> -#define IOMUXC_GPIO_AD_14_VIDEO_MUX_CSI_VSYNC 0x144 0x388 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13 0x144 0x388 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_14_ENET_RX_CLK 0x144 0x388 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_14_FLEXIO2_D14 0x144 0x388 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M 0x144 0x388 0x0 0x9 0x0
> -#define IOMUXC_GPIO_AD_14_GPIO9_IO13 0x144 0x388 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X 0x144 0x388 0x0 0xB 0x0
> -
> -#define IOMUXC_GPIO_AD_15_GPIO9_IO14 0x148 0x38C 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X 0x148 0x38C 0x0 0xB 0x0
> -#define IOMUXC_GPIO_AD_15_SPDIF_IN 0x148 0x38C 0x6B4 0x0 0x1
> -#define IOMUXC_GPIO_AD_15_LPUART10_TXD 0x148 0x38C 0x628 0x1 0x0
> -#define IOMUXC_GPIO_AD_15_GPT1_COMPARE2 0x148 0x38C 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00 0x148 0x38C 0x564 0x3 0x0
> -#define IOMUXC_GPIO_AD_15_VIDEO_MUX_CSI_HSYNC 0x148 0x38C 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14 0x148 0x38C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_15_ENET_TX_ER 0x148 0x38C 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_15_FLEXIO2_D15 0x148 0x38C 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_AD_16_SPDIF_OUT 0x14C 0x390 0x0 0x0 0x0
> -#define IOMUXC_GPIO_AD_16_LPUART10_RXD 0x14C 0x390 0x624 0x1 0x0
> -#define IOMUXC_GPIO_AD_16_GPT1_COMPARE3 0x14C 0x390 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK 0x14C 0x390 0x578 0x3 0x0
> -#define IOMUXC_GPIO_AD_16_VIDEO_MUX_CSI_DATA09 0x14C 0x390 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15 0x14C 0x390 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_16_ENET_RX_DATA03 0x14C 0x390 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_16_FLEXIO2_D16 0x14C 0x390 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_16_ENET_1G_MDC 0x14C 0x390 0x0 0x9 0x0
> -#define IOMUXC_GPIO_AD_16_GPIO9_IO15 0x14C 0x390 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X 0x14C 0x390 0x0 0xB 0x0
> -
> -#define IOMUXC_GPIO_AD_17_SAI1_MCLK 0x150 0x394 0x66C 0x0 0x0
> -#define IOMUXC_GPIO_AD_17_ACMP1_OUT 0x150 0x394 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_17_GPT1_CLK 0x150 0x394 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS 0x150 0x394 0x550 0x3 0x1
> -#define IOMUXC_GPIO_AD_17_VIDEO_MUX_CSI_DATA08 0x150 0x394 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16 0x150 0x394 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_17_ENET_RX_DATA02 0x150 0x394 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_17_FLEXIO2_D17 0x150 0x394 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_17_ENET_1G_MDIO 0x150 0x394 0x4C8 0x9 0x2
> -#define IOMUXC_GPIO_AD_17_GPIO9_IO16 0x150 0x394 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X 0x150 0x394 0x0 0xB 0x0
> -
> -#define IOMUXC_GPIO_AD_18_GPIO9_IO17 0x154 0x398 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X 0x154 0x398 0x0 0xB 0x0
> -#define IOMUXC_GPIO_AD_18_SAI1_RX_SYNC 0x154 0x398 0x678 0x0 0x0
> -#define IOMUXC_GPIO_AD_18_ACMP2_OUT 0x154 0x398 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_18_LPSPI1_PCS1 0x154 0x398 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B 0x154 0x398 0x0 0x3 0x0
> -#define IOMUXC_GPIO_AD_18_VIDEO_MUX_CSI_DATA07 0x154 0x398 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17 0x154 0x398 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_18_ENET_CRS 0x154 0x398 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_18_FLEXIO2_D18 0x154 0x398 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_18_LPI2C2_SCL 0x154 0x398 0x5B4 0x9 0x1
> -
> -#define IOMUXC_GPIO_AD_19_SAI1_RX_BCLK 0x158 0x39C 0x670 0x0 0x0
> -#define IOMUXC_GPIO_AD_19_ACMP3_OUT 0x158 0x39C 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_19_LPSPI1_PCS2 0x158 0x39C 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK 0x158 0x39C 0x574 0x3 0x0
> -#define IOMUXC_GPIO_AD_19_VIDEO_MUX_CSI_DATA06 0x158 0x39C 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18 0x158 0x39C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_19_ENET_COL 0x158 0x39C 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_19_FLEXIO2_D19 0x158 0x39C 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_19_LPI2C2_SDA 0x158 0x39C 0x5B8 0x9 0x1
> -#define IOMUXC_GPIO_AD_19_GPIO9_IO18 0x158 0x39C 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X 0x158 0x39C 0x0 0xB 0x0
> -
> -#define IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 0x15C 0x3A0 0x674 0x0 0x0
> -#define IOMUXC_GPIO_AD_20_ACMP4_OUT 0x15C 0x3A0 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_20_LPSPI1_PCS3 0x15C 0x3A0 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00 0x15C 0x3A0 0x554 0x3 0x0
> -#define IOMUXC_GPIO_AD_20_VIDEO_MUX_CSI_DATA05 0x15C 0x3A0 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19 0x15C 0x3A0 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_20_KPP_ROW07 0x15C 0x3A0 0x5A8 0x6 0x0
> -#define IOMUXC_GPIO_AD_20_FLEXIO2_D20 0x15C 0x3A0 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_20_ENET_QOS_1588_EVENT2_OUT 0x15C 0x3A0 0x0 0x9 0x0
> -#define IOMUXC_GPIO_AD_20_GPIO9_IO19 0x15C 0x3A0 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X 0x15C 0x3A0 0x0 0xB 0x0
> -
> -#define IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 0x160 0x3A4 0x0 0x0 0x0
> -#define IOMUXC_GPIO_AD_21_LPSPI2_PCS1 0x160 0x3A4 0x5E0 0x2 0x0
> -#define IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01 0x160 0x3A4 0x558 0x3 0x0
> -#define IOMUXC_GPIO_AD_21_VIDEO_MUX_CSI_DATA04 0x160 0x3A4 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20 0x160 0x3A4 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_21_KPP_COL07 0x160 0x3A4 0x5A0 0x6 0x0
> -#define IOMUXC_GPIO_AD_21_FLEXIO2_D21 0x160 0x3A4 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_21_ENET_QOS_1588_EVENT2_IN 0x160 0x3A4 0x0 0x9 0x0
> -#define IOMUXC_GPIO_AD_21_GPIO9_IO20 0x160 0x3A4 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X 0x160 0x3A4 0x0 0xB 0x0
> -
> -#define IOMUXC_GPIO_AD_22_GPIO9_IO21 0x164 0x3A8 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_22_SAI1_TX_BCLK 0x164 0x3A8 0x67C 0x0 0x0
> -#define IOMUXC_GPIO_AD_22_LPSPI2_PCS2 0x164 0x3A8 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02 0x164 0x3A8 0x55C 0x3 0x0
> -#define IOMUXC_GPIO_AD_22_VIDEO_MUX_CSI_DATA03 0x164 0x3A8 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21 0x164 0x3A8 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_22_KPP_ROW06 0x164 0x3A8 0x5A4 0x6 0x0
> -#define IOMUXC_GPIO_AD_22_FLEXIO2_D22 0x164 0x3A8 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_22_ENET_QOS_1588_EVENT3_OUT 0x164 0x3A8 0x0 0x9 0x0
> -
> -#define IOMUXC_GPIO_AD_23_SAI1_TX_SYNC 0x168 0x3AC 0x680 0x0 0x0
> -#define IOMUXC_GPIO_AD_23_LPSPI2_PCS3 0x168 0x3AC 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03 0x168 0x3AC 0x560 0x3 0x0
> -#define IOMUXC_GPIO_AD_23_VIDEO_MUX_CSI_DATA02 0x168 0x3AC 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22 0x168 0x3AC 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_23_KPP_COL06 0x168 0x3AC 0x59C 0x6 0x0
> -#define IOMUXC_GPIO_AD_23_FLEXIO2_D23 0x168 0x3AC 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_23_ENET_QOS_1588_EVENT3_IN 0x168 0x3AC 0x0 0x9 0x0
> -#define IOMUXC_GPIO_AD_23_GPIO9_IO22 0x168 0x3AC 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_AD_24_LPUART1_TXD 0x16C 0x3B0 0x620 0x0 0x0
> -#define IOMUXC_GPIO_AD_24_LPSPI2_SCK 0x16C 0x3B0 0x5E4 0x1 0x0
> -#define IOMUXC_GPIO_AD_24_VIDEO_MUX_CSI_DATA00 0x16C 0x3B0 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_24_ENET_RX_EN 0x16C 0x3B0 0x4B8 0x3 0x0
> -#define IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A 0x16C 0x3B0 0x518 0x4 0x1
> -#define IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23 0x16C 0x3B0 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_24_KPP_ROW05 0x16C 0x3B0 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_24_FLEXIO2_D24 0x16C 0x3B0 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_24_LPI2C4_SCL 0x16C 0x3B0 0x5C4 0x9 0x0
> -#define IOMUXC_GPIO_AD_24_GPIO9_IO23 0x16C 0x3B0 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_AD_25_GPIO9_IO24 0x170 0x3B4 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_25_LPUART1_RXD 0x170 0x3B4 0x61C 0x0 0x0
> -#define IOMUXC_GPIO_AD_25_LPSPI2_PCS0 0x170 0x3B4 0x5DC 0x1 0x0
> -#define IOMUXC_GPIO_AD_25_VIDEO_MUX_CSI_DATA01 0x170 0x3B4 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_25_ENET_RX_ER 0x170 0x3B4 0x4BC 0x3 0x0
> -#define IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B 0x170 0x3B4 0x524 0x4 0x1
> -#define IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 0x170 0x3B4 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_25_KPP_COL05 0x170 0x3B4 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_25_FLEXIO2_D25 0x170 0x3B4 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_25_LPI2C4_SDA 0x170 0x3B4 0x5C8 0x9 0x0
> -
> -#define IOMUXC_GPIO_AD_26_LPUART1_CTS_B 0x174 0x3B8 0x0 0x0 0x0
> -#define IOMUXC_GPIO_AD_26_LPSPI2_SOUT 0x174 0x3B8 0x5EC 0x1 0x0
> -#define IOMUXC_GPIO_AD_26_SEMC_CSX01 0x174 0x3B8 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_26_ENET_RX_DATA00 0x174 0x3B8 0x4B0 0x3 0x0
> -#define IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A 0x174 0x3B8 0x51C 0x4 0x1
> -#define IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25 0x174 0x3B8 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_26_KPP_ROW04 0x174 0x3B8 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_26_FLEXIO2_D26 0x174 0x3B8 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_26_ENET_QOS_MDC 0x174 0x3B8 0x0 0x9 0x0
> -#define IOMUXC_GPIO_AD_26_GPIO9_IO25 0x174 0x3B8 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_26_USDHC2_CD_B 0x174 0x3B8 0x6D0 0xB 0x1
> -
> -#define IOMUXC_GPIO_AD_27_LPUART1_RTS_B 0x178 0x3BC 0x0 0x0 0x0
> -#define IOMUXC_GPIO_AD_27_LPSPI2_SIN 0x178 0x3BC 0x5E8 0x1 0x0
> -#define IOMUXC_GPIO_AD_27_SEMC_CSX02 0x178 0x3BC 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_27_ENET_RX_DATA01 0x178 0x3BC 0x4B4 0x3 0x0
> -#define IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B 0x178 0x3BC 0x528 0x4 0x1
> -#define IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 0x178 0x3BC 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_27_KPP_COL04 0x178 0x3BC 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_27_FLEXIO2_D27 0x178 0x3BC 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_27_ENET_QOS_MDIO 0x178 0x3BC 0x4EC 0x9 0x1
> -#define IOMUXC_GPIO_AD_27_GPIO9_IO26 0x178 0x3BC 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_27_USDHC2_WP 0x178 0x3BC 0x6D4 0xB 0x1
> -
> -#define IOMUXC_GPIO_AD_28_GPIO9_IO27 0x17C 0x3C0 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_28_USDHC2_VSELECT 0x17C 0x3C0 0x0 0xB 0x0
> -#define IOMUXC_GPIO_AD_28_LPSPI1_SCK 0x17C 0x3C0 0x5D0 0x0 0x1
> -#define IOMUXC_GPIO_AD_28_LPUART5_TXD 0x17C 0x3C0 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_28_SEMC_CSX03 0x17C 0x3C0 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_28_ENET_TX_EN 0x17C 0x3C0 0x0 0x3 0x0
> -#define IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A 0x17C 0x3C0 0x520 0x4 0x1
> -#define IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27 0x17C 0x3C0 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_28_KPP_ROW03 0x17C 0x3C0 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_28_FLEXIO2_D28 0x17C 0x3C0 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 0x17C 0x3C0 0x0 0x9 0x0
> -
> -#define IOMUXC_GPIO_AD_29_LPSPI1_PCS0 0x180 0x3C4 0x5CC 0x0 0x1
> -#define IOMUXC_GPIO_AD_29_LPUART5_RXD 0x180 0x3C4 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_29_ENET_REF_CLK 0x180 0x3C4 0x4A8 0x2 0x0
> -#define IOMUXC_GPIO_AD_29_ENET_TX_CLK 0x180 0x3C4 0x4C0 0x3 0x0
> -#define IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B 0x180 0x3C4 0x52C 0x4 0x1
> -#define IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 0x180 0x3C4 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_29_KPP_COL03 0x180 0x3C4 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_29_FLEXIO2_D29 0x180 0x3C4 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 0x180 0x3C4 0x0 0x9 0x0
> -#define IOMUXC_GPIO_AD_29_GPIO9_IO28 0x180 0x3C4 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_29_USDHC2_RESET_B 0x180 0x3C4 0x0 0xB 0x0
> -
> -#define IOMUXC_GPIO_AD_30_LPSPI1_SOUT 0x184 0x3C8 0x5D8 0x0 0x1
> -#define IOMUXC_GPIO_AD_30_USB_OTG2_OC 0x184 0x3C8 0x6B8 0x1 0x1
> -#define IOMUXC_GPIO_AD_30_FLEXCAN2_TX 0x184 0x3C8 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_30_ENET_TX_DATA00 0x184 0x3C8 0x0 0x3 0x0
> -#define IOMUXC_GPIO_AD_30_LPUART3_TXD 0x184 0x3C8 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 0x184 0x3C8 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_30_KPP_ROW02 0x184 0x3C8 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_30_FLEXIO2_D30 0x184 0x3C8 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_30_WDOG2_RESET_B_DEB 0x184 0x3C8 0x0 0x9 0x0
> -#define IOMUXC_GPIO_AD_30_GPIO9_IO29 0x184 0x3C8 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_AD_31_LPSPI1_SIN 0x188 0x3CC 0x5D4 0x0 0x1
> -#define IOMUXC_GPIO_AD_31_USB_OTG2_PWR 0x188 0x3CC 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_31_FLEXCAN2_RX 0x188 0x3CC 0x49C 0x2 0x1
> -#define IOMUXC_GPIO_AD_31_ENET_TX_DATA01 0x188 0x3CC 0x0 0x3 0x0
> -#define IOMUXC_GPIO_AD_31_LPUART3_RXD 0x188 0x3CC 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 0x188 0x3CC 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_31_KPP_COL02 0x188 0x3CC 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_31_FLEXIO2_D31 0x188 0x3CC 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_31_WDOG1_RESET_B_DEB 0x188 0x3CC 0x0 0x9 0x0
> -#define IOMUXC_GPIO_AD_31_GPIO9_IO30 0x188 0x3CC 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_AD_32_GPIO9_IO31 0x18C 0x3D0 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_32_LPI2C1_SCL 0x18C 0x3D0 0x5AC 0x0 0x1
> -#define IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID 0x18C 0x3D0 0x6C4 0x1 0x1
> -#define IOMUXC_GPIO_AD_32_PGMC_PMIC_RDY 0x18C 0x3D0 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_32_ENET_MDC 0x18C 0x3D0 0x0 0x3 0x0
> -#define IOMUXC_GPIO_AD_32_USDHC1_CD_B 0x18C 0x3D0 0x6C8 0x4 0x0
> -#define IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31 0x18C 0x3D0 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_32_KPP_ROW01 0x18C 0x3D0 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_32_LPUART10_TXD 0x18C 0x3D0 0x628 0x8 0x1
> -#define IOMUXC_GPIO_AD_32_ENET_1G_MDC 0x18C 0x3D0 0x0 0x9 0x0
> -
> -#define IOMUXC_GPIO_AD_33_LPI2C1_SDA 0x190 0x3D4 0x5B0 0x0 0x1
> -#define IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID 0x190 0x3D4 0x6C0 0x1 0x1
> -#define IOMUXC_GPIO_AD_33_XBAR1_INOUT17 0x190 0x3D4 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_33_ENET_MDIO 0x190 0x3D4 0x4AC 0x3 0x1
> -#define IOMUXC_GPIO_AD_33_USDHC1_WP 0x190 0x3D4 0x6CC 0x4 0x0
> -#define IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00 0x190 0x3D4 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_33_KPP_COL01 0x190 0x3D4 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_33_LPUART10_RXD 0x190 0x3D4 0x624 0x8 0x1
> -#define IOMUXC_GPIO_AD_33_ENET_1G_MDIO 0x190 0x3D4 0x4C8 0x9 0x3
> -#define IOMUXC_GPIO_AD_33_GPIO10_IO00 0x190 0x3D4 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN 0x194 0x3D8 0x0 0x0 0x0
> -#define IOMUXC_GPIO_AD_34_USB_OTG1_PWR 0x194 0x3D8 0x0 0x1 0x0
> -#define IOMUXC_GPIO_AD_34_XBAR1_INOUT18 0x194 0x3D8 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN 0x194 0x3D8 0x0 0x3 0x0
> -#define IOMUXC_GPIO_AD_34_USDHC1_VSELECT 0x194 0x3D8 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01 0x194 0x3D8 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_34_KPP_ROW00 0x194 0x3D8 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_34_LPUART10_CTS_B 0x194 0x3D8 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_34_WDOG1_ANY 0x194 0x3D8 0x0 0x9 0x0
> -#define IOMUXC_GPIO_AD_34_GPIO10_IO01 0x194 0x3D8 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_AD_35_GPIO10_IO02 0x198 0x3DC 0x0 0xA 0x0
> -#define IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x0 0x0
> -#define IOMUXC_GPIO_AD_35_USB_OTG1_OC 0x198 0x3DC 0x6BC 0x1 0x1
> -#define IOMUXC_GPIO_AD_35_XBAR1_INOUT19 0x198 0x3DC 0x0 0x2 0x0
> -#define IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x3 0x0
> -#define IOMUXC_GPIO_AD_35_USDHC1_RESET_B 0x198 0x3DC 0x0 0x4 0x0
> -#define IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02 0x198 0x3DC 0x0 0x5 0x0
> -#define IOMUXC_GPIO_AD_35_KPP_COL00 0x198 0x3DC 0x0 0x6 0x0
> -#define IOMUXC_GPIO_AD_35_LPUART10_RTS_B 0x198 0x3DC 0x0 0x8 0x0
> -#define IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B 0x198 0x3DC 0x0 0x9 0x0
> -
> -#define IOMUXC_GPIO_SD_B1_00_USDHC1_CMD 0x19C 0x3E0 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT20 0x19C 0x3E0 0x6D8 0x2 0x1
> -#define IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 0x19C 0x3E0 0x0 0x3 0x0
> -#define IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 0x19C 0x3E0 0x0 0x5 0x0
> -#define IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B 0x19C 0x3E0 0x0 0x6 0x0
> -#define IOMUXC_GPIO_SD_B1_00_KPP_ROW07 0x19C 0x3E0 0x5A8 0x8 0x1
> -#define IOMUXC_GPIO_SD_B1_00_GPIO10_IO03 0x19C 0x3E0 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_SD_B1_01_USDHC1_CLK 0x1A0 0x3E4 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B1_01_XBAR1_INOUT21 0x1A0 0x3E4 0x6DC 0x2 0x1
> -#define IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 0x1A0 0x3E4 0x0 0x3 0x0
> -#define IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 0x1A0 0x3E4 0x0 0x5 0x0
> -#define IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK 0x1A0 0x3E4 0x58C 0x6 0x1
> -#define IOMUXC_GPIO_SD_B1_01_KPP_COL07 0x1A0 0x3E4 0x5A0 0x8 0x1
> -#define IOMUXC_GPIO_SD_B1_01_GPIO10_IO04 0x1A0 0x3E4 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_SD_B1_02_GPIO10_IO05 0x1A4 0x3E8 0x0 0xA 0x0
> -#define IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 0x1A4 0x3E8 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B1_02_XBAR1_INOUT22 0x1A4 0x3E8 0x6E0 0x2 0x1
> -#define IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 0x1A4 0x3E8 0x0 0x3 0x0
> -#define IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 0x1A4 0x3E8 0x0 0x5 0x0
> -#define IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 0x1A4 0x3E8 0x57C 0x6 0x1
> -#define IOMUXC_GPIO_SD_B1_02_KPP_ROW06 0x1A4 0x3E8 0x5A4 0x8 0x1
> -#define IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B 0x1A4 0x3E8 0x0 0x9 0x0
> -
> -#define IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 0x1A8 0x3EC 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B1_03_XBAR1_INOUT23 0x1A8 0x3EC 0x6E4 0x2 0x1
> -#define IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 0x1A8 0x3EC 0x0 0x3 0x0
> -#define IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 0x1A8 0x3EC 0x0 0x5 0x0
> -#define IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 0x1A8 0x3EC 0x580 0x6 0x1
> -#define IOMUXC_GPIO_SD_B1_03_KPP_COL06 0x1A8 0x3EC 0x59C 0x8 0x1
> -#define IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B 0x1A8 0x3EC 0x0 0x9 0x0
> -#define IOMUXC_GPIO_SD_B1_03_GPIO10_IO06 0x1A8 0x3EC 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 0x1AC 0x3F0 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B1_04_XBAR1_INOUT24 0x1AC 0x3F0 0x6E8 0x2 0x1
> -#define IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 0x1AC 0x3F0 0x0 0x3 0x0
> -#define IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 0x1AC 0x3F0 0x0 0x5 0x0
> -#define IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 0x1AC 0x3F0 0x584 0x6 0x1
> -#define IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B 0x1AC 0x3F0 0x0 0x8 0x0
> -#define IOMUXC_GPIO_SD_B1_04_ENET_QOS_1588_EVENT2_AUX_IN 0x1AC 0x3F0 0x0 0x9 0x0
> -#define IOMUXC_GPIO_SD_B1_04_GPIO10_IO07 0x1AC 0x3F0 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_SD_B1_05_GPIO10_IO08 0x1B0 0x3F4 0x0 0xA 0x0
> -#define IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 0x1B0 0x3F4 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B1_05_XBAR1_INOUT25 0x1B0 0x3F4 0x6EC 0x2 0x1
> -#define IOMUXC_GPIO_SD_B1_05_GPT4_CLK 0x1B0 0x3F4 0x0 0x3 0x0
> -#define IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 0x1B0 0x3F4 0x0 0x5 0x0
> -#define IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 0x1B0 0x3F4 0x588 0x6 0x1
> -#define IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS 0x1B0 0x3F4 0x0 0x8 0x0
> -#define IOMUXC_GPIO_SD_B1_05_ENET_QOS_1588_EVENT3_AUX_IN 0x1B0 0x3F4 0x0 0x9 0x0
> -
> -#define IOMUXC_GPIO_SD_B2_00_GPIO10_IO09 0x1B4 0x3F8 0x0 0xA 0x0
> -#define IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3 0x1B4 0x3F8 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 0x1B4 0x3F8 0x570 0x1 0x1
> -#define IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN 0x1B4 0x3F8 0x4E0 0x2 0x1
> -#define IOMUXC_GPIO_SD_B2_00_LPUART9_TXD 0x1B4 0x3F8 0x0 0x3 0x0
> -#define IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK 0x1B4 0x3F8 0x610 0x4 0x0
> -#define IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09 0x1B4 0x3F8 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2 0x1B8 0x3FC 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 0x1B8 0x3FC 0x56C 0x1 0x1
> -#define IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK 0x1B8 0x3FC 0x4CC 0x2 0x1
> -#define IOMUXC_GPIO_SD_B2_01_LPUART9_RXD 0x1B8 0x3FC 0x0 0x3 0x0
> -#define IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0 0x1B8 0x3FC 0x60C 0x4 0x0
> -#define IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10 0x1B8 0x3FC 0x0 0x5 0x0
> -#define IOMUXC_GPIO_SD_B2_01_GPIO10_IO10 0x1B8 0x3FC 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_SD_B2_02_GPIO10_IO11 0x1BC 0x400 0x0 0xA 0x0
> -#define IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1 0x1BC 0x400 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 0x1BC 0x400 0x568 0x1 0x1
> -#define IOMUXC_GPIO_SD_B2_02_ENET_1G_RX_DATA00 0x1BC 0x400 0x4D0 0x2 0x1
> -#define IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B 0x1BC 0x400 0x0 0x3 0x0
> -#define IOMUXC_GPIO_SD_B2_02_LPSPI4_SOUT 0x1BC 0x400 0x618 0x4 0x0
> -#define IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11 0x1BC 0x400 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_SD_B2_03_GPIO10_IO12 0x1C0 0x404 0x0 0xA 0x0
> -#define IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0 0x1C0 0x404 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 0x1C0 0x404 0x564 0x1 0x1
> -#define IOMUXC_GPIO_SD_B2_03_ENET_1G_RX_DATA01 0x1C0 0x404 0x4D4 0x2 0x1
> -#define IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B 0x1C0 0x404 0x0 0x3 0x0
> -#define IOMUXC_GPIO_SD_B2_03_LPSPI4_SIN 0x1C0 0x404 0x614 0x4 0x0
> -#define IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12 0x1C0 0x404 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_SD_B2_04_USDHC2_CLK 0x1C4 0x408 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK 0x1C4 0x408 0x578 0x1 0x1
> -#define IOMUXC_GPIO_SD_B2_04_ENET_1G_RX_DATA02 0x1C4 0x408 0x4D8 0x2 0x1
> -#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B 0x1C4 0x408 0x0 0x3 0x0
> -#define IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1 0x1C4 0x408 0x0 0x4 0x0
> -#define IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13 0x1C4 0x408 0x0 0x5 0x0
> -#define IOMUXC_GPIO_SD_B2_04_GPIO10_IO13 0x1C4 0x408 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_SD_B2_05_GPIO10_IO14 0x1C8 0x40C 0x0 0xA 0x0
> -#define IOMUXC_GPIO_SD_B2_05_USDHC2_CMD 0x1C8 0x40C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS 0x1C8 0x40C 0x550 0x1 0x2
> -#define IOMUXC_GPIO_SD_B2_05_ENET_1G_RX_DATA03 0x1C8 0x40C 0x4DC 0x2 0x1
> -#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B 0x1C8 0x40C 0x0 0x3 0x0
> -#define IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2 0x1C8 0x40C 0x0 0x4 0x0
> -#define IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14 0x1C8 0x40C 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_SD_B2_06_GPIO10_IO15 0x1CC 0x410 0x0 0xA 0x0
> -#define IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B 0x1CC 0x410 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B 0x1CC 0x410 0x0 0x1 0x0
> -#define IOMUXC_GPIO_SD_B2_06_ENET_1G_TX_DATA03 0x1CC 0x410 0x0 0x2 0x0
> -#define IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3 0x1CC 0x410 0x0 0x3 0x0
> -#define IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1 0x1CC 0x410 0x0 0x4 0x0
> -#define IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15 0x1CC 0x410 0x0 0x5 0x0
> -
> -#define IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE 0x1D0 0x414 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK 0x1D0 0x414 0x574 0x1 0x1
> -#define IOMUXC_GPIO_SD_B2_07_ENET_1G_TX_DATA02 0x1D0 0x414 0x0 0x2 0x0
> -#define IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B 0x1D0 0x414 0x0 0x3 0x0
> -#define IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2 0x1D0 0x414 0x0 0x4 0x0
> -#define IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 0x1D0 0x414 0x0 0x5 0x0
> -#define IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK 0x1D0 0x414 0x5E4 0x6 0x1
> -#define IOMUXC_GPIO_SD_B2_07_ENET_TX_ER 0x1D0 0x414 0x0 0x8 0x0
> -#define IOMUXC_GPIO_SD_B2_07_ENET_QOS_REF_CLK 0x1D0 0x414 0x4A0 0x9 0x1
> -#define IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 0x1D0 0x414 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 0x1D4 0x418 0x0 0xA 0x0
> -#define IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4 0x1D4 0x418 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 0x1D4 0x418 0x554 0x1 0x1
> -#define IOMUXC_GPIO_SD_B2_08_ENET_1G_TX_DATA01 0x1D4 0x418 0x0 0x2 0x0
> -#define IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B 0x1D4 0x418 0x0 0x3 0x0
> -#define IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1 0x1D4 0x418 0x0 0x4 0x0
> -#define IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17 0x1D4 0x418 0x0 0x5 0x0
> -#define IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0 0x1D4 0x418 0x5DC 0x6 0x1
> -
> -#define IOMUXC_GPIO_SD_B2_09_GPIO10_IO18 0x1D8 0x41C 0x0 0xA 0x0
> -#define IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5 0x1D8 0x41C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 0x1D8 0x41C 0x558 0x1 0x1
> -#define IOMUXC_GPIO_SD_B2_09_ENET_1G_TX_DATA00 0x1D8 0x41C 0x0 0x2 0x0
> -#define IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B 0x1D8 0x41C 0x0 0x3 0x0
> -#define IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2 0x1D8 0x41C 0x0 0x4 0x0
> -#define IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18 0x1D8 0x41C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_SD_B2_09_LPSPI2_SOUT 0x1D8 0x41C 0x5EC 0x6 0x1
> -
> -#define IOMUXC_GPIO_SD_B2_10_GPIO10_IO19 0x1DC 0x420 0x0 0xA 0x0
> -#define IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6 0x1DC 0x420 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 0x1DC 0x420 0x55C 0x1 0x1
> -#define IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN 0x1DC 0x420 0x0 0x2 0x0
> -#define IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B 0x1DC 0x420 0x0 0x3 0x0
> -#define IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3 0x1DC 0x420 0x0 0x4 0x0
> -#define IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19 0x1DC 0x420 0x0 0x5 0x0
> -#define IOMUXC_GPIO_SD_B2_10_LPSPI2_SIN 0x1DC 0x420 0x5E8 0x6 0x1
> -
> -#define IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 0x1E0 0x424 0x0 0x0 0x0
> -#define IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0x1E0 0x424 0x560 0x1 0x1
> -#define IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO 0x1E0 0x424 0x4E8 0x2 0x1
> -#define IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK 0x1E0 0x424 0x4C4 0x3 0x1
> -#define IOMUXC_GPIO_SD_B2_11_GPT6_CLK 0x1E0 0x424 0x0 0x4 0x0
> -#define IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 0x1E0 0x424 0x0 0x5 0x0
> -#define IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 0x1E0 0x424 0x5E0 0x6 0x1
> -#define IOMUXC_GPIO_SD_B2_11_GPIO10_IO20 0x1E0 0x424 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK 0x1E4 0x428 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN 0x1E4 0x428 0x4E0 0x1 0x2
> -#define IOMUXC_GPIO_DISP_B1_00_TMR1_TIMER0 0x1E4 0x428 0x63C 0x3 0x2
> -#define IOMUXC_GPIO_DISP_B1_00_XBAR1_INOUT26 0x1E4 0x428 0x6F0 0x4 0x1
> -#define IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 0x1E4 0x428 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B1_00_ENET_QOS_RX_EN 0x1E4 0x428 0x4F8 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 0x1E4 0x428 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE 0x1E8 0x42C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK 0x1E8 0x42C 0x4CC 0x1 0x2
> -#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER 0x1E8 0x42C 0x4E4 0x2 0x1
> -#define IOMUXC_GPIO_DISP_B1_01_TMR1_TIMER1 0x1E8 0x42C 0x640 0x3 0x2
> -#define IOMUXC_GPIO_DISP_B1_01_XBAR1_INOUT27 0x1E8 0x42C 0x6F4 0x4 0x1
> -#define IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 0x1E8 0x42C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_CLK 0x1E8 0x42C 0x0 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_ER 0x1E8 0x42C 0x4FC 0x9 0x0
> -#define IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 0x1E8 0x42C 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23 0x1EC 0x430 0x0 0xA 0x0
> -#define IOMUXC_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC 0x1EC 0x430 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00 0x1EC 0x430 0x4D0 0x1 0x2
> -#define IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL 0x1EC 0x430 0x5BC 0x2 0x0
> -#define IOMUXC_GPIO_DISP_B1_02_TMR1_TIMER2 0x1EC 0x430 0x644 0x3 0x1
> -#define IOMUXC_GPIO_DISP_B1_02_XBAR1_INOUT28 0x1EC 0x430 0x6F8 0x4 0x1
> -#define IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 0x1EC 0x430 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B1_02_ENET_QOS_RX_DATA00 0x1EC 0x430 0x4F0 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B1_02_LPUART1_TXD 0x1EC 0x430 0x620 0x9 0x1
> -
> -#define IOMUXC_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC 0x1F0 0x434 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01 0x1F0 0x434 0x4D4 0x1 0x2
> -#define IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA 0x1F0 0x434 0x5C0 0x2 0x0
> -#define IOMUXC_GPIO_DISP_B1_03_TMR2_TIMER0 0x1F0 0x434 0x648 0x3 0x2
> -#define IOMUXC_GPIO_DISP_B1_03_XBAR1_INOUT29 0x1F0 0x434 0x6FC 0x4 0x1
> -#define IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 0x1F0 0x434 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B1_03_ENET_QOS_RX_DATA01 0x1F0 0x434 0x4F4 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B1_03_LPUART1_RXD 0x1F0 0x434 0x61C 0x9 0x1
> -#define IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 0x1F0 0x434 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00 0x1F4 0x438 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02 0x1F4 0x438 0x4D8 0x1 0x2
> -#define IOMUXC_GPIO_DISP_B1_04_LPUART4_RXD 0x1F4 0x438 0x0 0x2 0x0
> -#define IOMUXC_GPIO_DISP_B1_04_TMR2_TIMER1 0x1F4 0x438 0x64C 0x3 0x2
> -#define IOMUXC_GPIO_DISP_B1_04_XBAR1_INOUT30 0x1F4 0x438 0x700 0x4 0x1
> -#define IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 0x1F4 0x438 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B1_04_ENET_QOS_RX_DATA02 0x1F4 0x438 0x0 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK 0x1F4 0x438 0x600 0x9 0x1
> -#define IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 0x1F4 0x438 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26 0x1F8 0x43C 0x0 0xA 0x0
> -#define IOMUXC_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01 0x1F8 0x43C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03 0x1F8 0x43C 0x4DC 0x1 0x2
> -#define IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B 0x1F8 0x43C 0x0 0x2 0x0
> -#define IOMUXC_GPIO_DISP_B1_05_TMR2_TIMER2 0x1F8 0x43C 0x650 0x3 0x1
> -#define IOMUXC_GPIO_DISP_B1_05_XBAR1_INOUT31 0x1F8 0x43C 0x704 0x4 0x1
> -#define IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 0x1F8 0x43C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B1_05_ENET_QOS_RX_DATA03 0x1F8 0x43C 0x0 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B1_05_LPSPI3_SIN 0x1F8 0x43C 0x604 0x9 0x1
> -
> -#define IOMUXC_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02 0x1FC 0x440 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03 0x1FC 0x440 0x0 0x1 0x0
> -#define IOMUXC_GPIO_DISP_B1_06_LPUART4_TXD 0x1FC 0x440 0x0 0x2 0x0
> -#define IOMUXC_GPIO_DISP_B1_06_TMR3_TIMER0 0x1FC 0x440 0x654 0x3 0x2
> -#define IOMUXC_GPIO_DISP_B1_06_XBAR1_INOUT32 0x1FC 0x440 0x708 0x4 0x1
> -#define IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27 0x1FC 0x440 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00 0x1FC 0x440 0x0 0x6 0x0
> -#define IOMUXC_GPIO_DISP_B1_06_ENET_QOS_TX_DATA03 0x1FC 0x440 0x0 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B1_06_LPSPI3_SOUT 0x1FC 0x440 0x608 0x9 0x1
> -#define IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27 0x1FC 0x440 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03 0x200 0x444 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02 0x200 0x444 0x0 0x1 0x0
> -#define IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B 0x200 0x444 0x0 0x2 0x0
> -#define IOMUXC_GPIO_DISP_B1_07_TMR3_TIMER1 0x200 0x444 0x658 0x3 0x2
> -#define IOMUXC_GPIO_DISP_B1_07_XBAR1_INOUT33 0x200 0x444 0x70C 0x4 0x1
> -#define IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28 0x200 0x444 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01 0x200 0x444 0x0 0x6 0x0
> -#define IOMUXC_GPIO_DISP_B1_07_ENET_QOS_TX_DATA02 0x200 0x444 0x0 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0 0x200 0x444 0x5F0 0x9 0x1
> -#define IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28 0x200 0x444 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29 0x204 0x448 0x0 0xA 0x0
> -#define IOMUXC_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04 0x204 0x448 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01 0x204 0x448 0x0 0x1 0x0
> -#define IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B 0x204 0x448 0x6C8 0x2 0x1
> -#define IOMUXC_GPIO_DISP_B1_08_TMR3_TIMER2 0x204 0x448 0x65C 0x3 0x1
> -#define IOMUXC_GPIO_DISP_B1_08_XBAR1_INOUT34 0x204 0x448 0x710 0x4 0x1
> -#define IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29 0x204 0x448 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02 0x204 0x448 0x0 0x6 0x0
> -#define IOMUXC_GPIO_DISP_B1_08_ENET_QOS_TX_DATA01 0x204 0x448 0x0 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1 0x204 0x448 0x5F4 0x9 0x1
> -
> -#define IOMUXC_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05 0x208 0x44C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00 0x208 0x44C 0x0 0x1 0x0
> -#define IOMUXC_GPIO_DISP_B1_09_USDHC1_WP 0x208 0x44C 0x6CC 0x2 0x1
> -#define IOMUXC_GPIO_DISP_B1_09_TMR4_TIMER0 0x208 0x44C 0x660 0x3 0x2
> -#define IOMUXC_GPIO_DISP_B1_09_XBAR1_INOUT35 0x208 0x44C 0x714 0x4 0x1
> -#define IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30 0x208 0x44C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03 0x208 0x44C 0x0 0x6 0x0
> -#define IOMUXC_GPIO_DISP_B1_09_ENET_QOS_TX_DATA00 0x208 0x44C 0x0 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2 0x208 0x44C 0x5F8 0x9 0x1
> -#define IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30 0x208 0x44C 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06 0x20C 0x450 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN 0x20C 0x450 0x0 0x1 0x0
> -#define IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B 0x20C 0x450 0x0 0x2 0x0
> -#define IOMUXC_GPIO_DISP_B1_10_TMR4_TIMER1 0x20C 0x450 0x664 0x3 0x2
> -#define IOMUXC_GPIO_DISP_B1_10_XBAR1_INOUT36 0x20C 0x450 0x0 0x4 0x0
> -#define IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31 0x20C 0x450 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04 0x20C 0x450 0x0 0x6 0x0
> -#define IOMUXC_GPIO_DISP_B1_10_ENET_QOS_TX_EN 0x20C 0x450 0x0 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3 0x20C 0x450 0x5FC 0x9 0x1
> -#define IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31 0x20C 0x450 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 0x210 0x454 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO 0x210 0x454 0x4E8 0x1 0x2
> -#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK 0x210 0x454 0x4C4 0x2 0x2
> -#define IOMUXC_GPIO_DISP_B1_11_TMR4_TIMER2 0x210 0x454 0x668 0x3 0x1
> -#define IOMUXC_GPIO_DISP_B1_11_XBAR1_INOUT37 0x210 0x454 0x0 0x4 0x0
> -#define IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 0x210 0x454 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 0x210 0x454 0x0 0x6 0x0
> -#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_TX_CLK 0x210 0x454 0x4A4 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_REF_CLK 0x210 0x454 0x4A0 0x9 0x2
> -#define IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 0x210 0x454 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 0x214 0x458 0x0 0xA 0x0
> -#define IOMUXC_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08 0x214 0x458 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B2_00_WDOG1_B 0x214 0x458 0x0 0x1 0x0
> -#define IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT 0x214 0x458 0x0 0x2 0x0
> -#define IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER 0x214 0x458 0x0 0x3 0x0
> -#define IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03 0x214 0x458 0x0 0x4 0x0
> -#define IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01 0x214 0x458 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06 0x214 0x458 0x0 0x6 0x0
> -#define IOMUXC_GPIO_DISP_B2_00_ENET_QOS_TX_ER 0x214 0x458 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09 0x218 0x45C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT 0x218 0x45C 0x0 0x1 0x0
> -#define IOMUXC_GPIO_DISP_B2_01_MQS_LEFT 0x218 0x45C 0x0 0x2 0x0
> -#define IOMUXC_GPIO_DISP_B2_01_WDOG2_B 0x218 0x45C 0x0 0x3 0x0
> -#define IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02 0x218 0x45C 0x0 0x4 0x0
> -#define IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02 0x218 0x45C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07 0x218 0x45C 0x0 0x6 0x0
> -#define IOMUXC_GPIO_DISP_B2_01_EWM_OUT_B 0x218 0x45C 0x0 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M 0x218 0x45C 0x0 0x9 0x0
> -#define IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02 0x218 0x45C 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03 0x21C 0x460 0x0 0xA 0x0
> -#define IOMUXC_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 0x21C 0x460 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00 0x21C 0x460 0x0 0x1 0x0
> -#define IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER3 0x21C 0x460 0x0 0x2 0x0
> -#define IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 0x21C 0x460 0x0 0x3 0x0
> -#define IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 0x21C 0x460 0x0 0x4 0x0
> -#define IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 0x21C 0x460 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 0x21C 0x460 0x0 0x6 0x0
> -#define IOMUXC_GPIO_DISP_B2_02_ENET_QOS_TX_DATA00 0x21C 0x460 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04 0x220 0x464 0x0 0xA 0x0
> -#define IOMUXC_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 0x220 0x464 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01 0x220 0x464 0x0 0x1 0x0
> -#define IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER2 0x220 0x464 0x0 0x2 0x0
> -#define IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 0x220 0x464 0x0 0x3 0x0
> -#define IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK 0x220 0x464 0x66C 0x4 0x1
> -#define IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 0x220 0x464 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 0x220 0x464 0x0 0x6 0x0
> -#define IOMUXC_GPIO_DISP_B2_03_ENET_QOS_TX_DATA01 0x220 0x464 0x0 0x8 0x0
> -
> -#define IOMUXC_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 0x224 0x468 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN 0x224 0x468 0x0 0x1 0x0
> -#define IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER1 0x224 0x468 0x0 0x2 0x0
> -#define IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 0x224 0x468 0x0 0x3 0x0
> -#define IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC 0x224 0x468 0x678 0x4 0x1
> -#define IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 0x224 0x468 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 0x224 0x468 0x0 0x6 0x0
> -#define IOMUXC_GPIO_DISP_B2_04_ENET_QOS_TX_EN 0x224 0x468 0x0 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05 0x224 0x468 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 0x228 0x46C 0x0 0xA 0x0
> -#define IOMUXC_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 0x228 0x46C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK 0x228 0x46C 0x4C0 0x1 0x1
> -#define IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK 0x228 0x46C 0x4A8 0x2 0x1
> -#define IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 0x228 0x46C 0x0 0x3 0x0
> -#define IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK 0x228 0x46C 0x670 0x4 0x1
> -#define IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 0x228 0x46C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 0x228 0x46C 0x0 0x6 0x0
> -#define IOMUXC_GPIO_DISP_B2_05_ENET_QOS_TX_CLK 0x228 0x46C 0x4A4 0x8 0x1
> -
> -#define IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07 0x22C 0x470 0x0 0xA 0x0
> -#define IOMUXC_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 0x22C 0x470 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00 0x22C 0x470 0x4B0 0x1 0x1
> -#define IOMUXC_GPIO_DISP_B2_06_LPUART7_TXD 0x22C 0x470 0x630 0x2 0x1
> -#define IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK 0x22C 0x470 0x0 0x3 0x0
> -#define IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 0x22C 0x470 0x674 0x4 0x1
> -#define IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 0x22C 0x470 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B2_06_ENET_QOS_RX_DATA00 0x22C 0x470 0x4F0 0x8 0x1
> -
> -#define IOMUXC_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 0x230 0x474 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01 0x230 0x474 0x4B4 0x1 0x1
> -#define IOMUXC_GPIO_DISP_B2_07_LPUART7_RXD 0x230 0x474 0x62C 0x2 0x1
> -#define IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO 0x230 0x474 0x0 0x3 0x0
> -#define IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 0x230 0x474 0x0 0x4 0x0
> -#define IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 0x230 0x474 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B2_07_ENET_QOS_RX_DATA01 0x230 0x474 0x4F4 0x8 0x1
> -#define IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 0x230 0x474 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 0x234 0x478 0x0 0xA 0x0
> -#define IOMUXC_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 0x234 0x478 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN 0x234 0x478 0x4B8 0x1 0x1
> -#define IOMUXC_GPIO_DISP_B2_08_LPUART8_TXD 0x234 0x478 0x638 0x2 0x1
> -#define IOMUXC_GPIO_DISP_B2_08_ARM_CM7_EVENTO 0x234 0x478 0x0 0x3 0x0
> -#define IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK 0x234 0x478 0x67C 0x4 0x1
> -#define IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09 0x234 0x478 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B2_08_ENET_QOS_RX_EN 0x234 0x478 0x4F8 0x8 0x1
> -#define IOMUXC_GPIO_DISP_B2_08_LPUART1_TXD 0x234 0x478 0x620 0x9 0x2
> -
> -#define IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 0x238 0x47C 0x0 0xA 0x0
> -#define IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 0x238 0x47C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER 0x238 0x47C 0x4BC 0x1 0x1
> -#define IOMUXC_GPIO_DISP_B2_09_LPUART8_RXD 0x238 0x47C 0x634 0x2 0x1
> -#define IOMUXC_GPIO_DISP_B2_09_ARM_CM7_EVENTI 0x238 0x47C 0x0 0x3 0x0
> -#define IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC 0x238 0x47C 0x680 0x4 0x1
> -#define IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 0x238 0x47C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B2_09_ENET_QOS_RX_ER 0x238 0x47C 0x4FC 0x8 0x1
> -#define IOMUXC_GPIO_DISP_B2_09_LPUART1_RXD 0x238 0x47C 0x61C 0x9 0x2
> -
> -#define IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 0x23C 0x480 0x0 0xA 0x0
> -#define IOMUXC_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 0x23C 0x480 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B2_10_EMVSIM2_IO 0x23C 0x480 0x6A8 0x1 0x1
> -#define IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD 0x23C 0x480 0x0 0x2 0x0
> -#define IOMUXC_GPIO_DISP_B2_10_WDOG2_RESET_B_DEB 0x23C 0x480 0x0 0x3 0x0
> -#define IOMUXC_GPIO_DISP_B2_10_XBAR1_INOUT38 0x23C 0x480 0x0 0x4 0x0
> -#define IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 0x23C 0x480 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL 0x23C 0x480 0x5BC 0x6 0x1
> -#define IOMUXC_GPIO_DISP_B2_10_ENET_QOS_RX_ER 0x23C 0x480 0x4FC 0x8 0x2
> -#define IOMUXC_GPIO_DISP_B2_10_SPDIF_IN 0x23C 0x480 0x6B4 0x9 0x2
> -
> -#define IOMUXC_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 0x240 0x484 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B2_11_EMVSIM2_CLK 0x240 0x484 0x0 0x1 0x0
> -#define IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD 0x240 0x484 0x0 0x2 0x0
> -#define IOMUXC_GPIO_DISP_B2_11_WDOG1_RESET_B_DEB 0x240 0x484 0x0 0x3 0x0
> -#define IOMUXC_GPIO_DISP_B2_11_XBAR1_INOUT39 0x240 0x484 0x0 0x4 0x0
> -#define IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 0x240 0x484 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA 0x240 0x484 0x5C0 0x6 0x1
> -#define IOMUXC_GPIO_DISP_B2_11_ENET_QOS_CRS 0x240 0x484 0x0 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT 0x240 0x484 0x0 0x9 0x0
> -#define IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 0x240 0x484 0x0 0xA 0x0
> -
> -#define IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 0x244 0x488 0x0 0xA 0x0
> -#define IOMUXC_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 0x244 0x488 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B2_12_EMVSIM2_RST 0x244 0x488 0x0 0x1 0x0
> -#define IOMUXC_GPIO_DISP_B2_12_FLEXCAN1_TX 0x244 0x488 0x0 0x2 0x0
> -#define IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B 0x244 0x488 0x0 0x3 0x0
> -#define IOMUXC_GPIO_DISP_B2_12_XBAR1_INOUT40 0x244 0x488 0x0 0x4 0x0
> -#define IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13 0x244 0x488 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL 0x244 0x488 0x5C4 0x6 0x1
> -#define IOMUXC_GPIO_DISP_B2_12_ENET_QOS_COL 0x244 0x488 0x0 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK 0x244 0x488 0x610 0x9 0x1
> -
> -#define IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 0x248 0x48C 0x0 0xA 0x0
> -#define IOMUXC_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 0x248 0x48C 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B2_13_EMVSIM2_SVEN 0x248 0x48C 0x0 0x1 0x0
> -#define IOMUXC_GPIO_DISP_B2_13_FLEXCAN1_RX 0x248 0x48C 0x498 0x2 0x1
> -#define IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B 0x248 0x48C 0x0 0x3 0x0
> -#define IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK 0x248 0x48C 0x4A8 0x4 0x2
> -#define IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 0x248 0x48C 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA 0x248 0x48C 0x5C8 0x6 0x1
> -#define IOMUXC_GPIO_DISP_B2_13_ENET_QOS_1588_EVENT0_OUT 0x248 0x48C 0x0 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B2_13_LPSPI4_SIN 0x248 0x48C 0x614 0x9 0x1
> -
> -#define IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15 0x24C 0x490 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B2_14_FLEXCAN1_TX 0x24C 0x490 0x0 0x6 0x0
> -#define IOMUXC_GPIO_DISP_B2_14_ENET_QOS_1588_EVENT0_IN 0x24C 0x490 0x0 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B2_14_LPSPI4_SOUT 0x24C 0x490 0x618 0x9 0x1
> -#define IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15 0x24C 0x490 0x0 0xA 0x0
> -#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22 0x24C 0x490 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B2_14_EMVSIM2_PD 0x24C 0x490 0x6AC 0x1 0x1
> -#define IOMUXC_GPIO_DISP_B2_14_WDOG2_B 0x24C 0x490 0x0 0x2 0x0
> -#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 0x24C 0x490 0x0 0x3 0x0
> -#define IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK 0x24C 0x490 0x4C4 0x4 0x3
> -
> -#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 0x250 0x494 0x0 0x0 0x0
> -#define IOMUXC_GPIO_DISP_B2_15_EMVSIM2_POWER_FAIL 0x250 0x494 0x6B0 0x1 0x1
> -#define IOMUXC_GPIO_DISP_B2_15_WDOG1_B 0x250 0x494 0x0 0x2 0x0
> -#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 0x250 0x494 0x0 0x3 0x0
> -#define IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER0 0x250 0x494 0x0 0x4 0x0
> -#define IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16 0x250 0x494 0x0 0x5 0x0
> -#define IOMUXC_GPIO_DISP_B2_15_FLEXCAN1_RX 0x250 0x494 0x498 0x6 0x2
> -#define IOMUXC_GPIO_DISP_B2_15_ENET_QOS_1588_EVENT0_AUX_IN 0x250 0x494 0x0 0x8 0x0
> -#define IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 0x250 0x494 0x60C 0x9 0x1
> -#define IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 0x250 0x494 0x0 0xA 0x0
> -
> -#endif /* _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H */
> diff --git a/arch/arm/boot/dts/nxp/vf/Makefile b/arch/arm/boot/dts/nxp/vf/Makefile
> index 0a4a7f9dd43e..1733506c0c72 100644
> --- a/arch/arm/boot/dts/nxp/vf/Makefile
> +++ b/arch/arm/boot/dts/nxp/vf/Makefile
> @@ -3,9 +3,7 @@ dtb-$(CONFIG_SOC_VF610) += \
> vf500-colibri-eval-v3.dtb \
> vf610-bk4.dtb \
> vf610-colibri-eval-v3.dtb \
> - vf610m4-colibri.dtb \
> vf610-cosmic.dtb \
> - vf610m4-cosmic.dtb \
> vf610-twr.dtb \
> vf610-zii-cfu1.dtb \
> vf610-zii-dev-rev-b.dtb \
> diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts b/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts
> deleted file mode 100644
> index 86d32f54c250..000000000000
> --- a/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts
> +++ /dev/null
> @@ -1,61 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+ OR MIT
> -/*
> - * Device tree for Colibri VF61 Cortex-M4 support
> - *
> - * Copyright (C) 2015 Stefan Agner
> - */
> -
> -/dts-v1/;
> -#include "vf610m4.dtsi"
> -
> -/ {
> - model = "VF610 Cortex-M4";
> - compatible = "fsl,vf610m4";
> -
> - chosen {
> - bootargs = "clk_ignore_unused init=/linuxrc rw";
> - stdout-path = "serial2:115200";
> - };
> -
> - memory@8c000000 {
> - device_type = "memory";
> - reg = <0x8c000000 0x3000000>;
> - };
> -};
> -
> -&gpio0 {
> - status = "disabled";
> -};
> -
> -&gpio1 {
> - status = "disabled";
> -};
> -
> -&gpio2 {
> - status = "disabled";
> -};
> -
> -&gpio3 {
> - status = "disabled";
> -};
> -
> -&gpio4 {
> - status = "disabled";
> -};
> -
> -&uart2 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_uart2>;
> - status = "okay";
> -};
> -
> -&iomuxc {
> - pinctrl_uart2: uart2grp {
> - fsl,pins = <
> - VF610_PAD_PTD0__UART2_TX 0x21a2
> - VF610_PAD_PTD1__UART2_RX 0x21a1
> - VF610_PAD_PTD2__UART2_RTS 0x21a2
> - VF610_PAD_PTD3__UART2_CTS 0x21a1
> - >;
> - };
> -};
> diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts b/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts
> deleted file mode 100644
> index 454b484368cb..000000000000
> --- a/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts
> +++ /dev/null
> @@ -1,88 +0,0 @@
> -/*
> - * Device tree for Cosmic+ VF6xx Cortex-M4 support
> - *
> - * Copyright (C) 2015
> - *
> - * Based on vf610m4 Colibri
> - *
> - * This file is dual-licensed: you can use it either under the terms
> - * of the GPL or the X11 license, at your option. Note that this dual
> - * licensing only applies to this file, and not this project as a
> - * whole.
> - *
> - * a) This file is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of the
> - * License, or (at your option) any later version.
> - *
> - * This file is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * Or, alternatively,
> - *
> - * b) Permission is hereby granted, free of charge, to any person
> - * obtaining a copy of this software and associated documentation
> - * files (the "Software"), to deal in the Software without
> - * restriction, including without limitation the rights to use,
> - * copy, modify, merge, publish, distribute, sublicense, and/or
> - * sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following
> - * conditions:
> - *
> - * The above copyright notice and this permission notice shall be
> - * included in all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - */
> -
> -/dts-v1/;
> -#include "vf610m4.dtsi"
> -
> -/ {
> - model = "VF610 Cortex-M4";
> - compatible = "fsl,vf610m4";
> -};
> -
> -&gpio0 {
> - status = "disabled";
> -};
> -
> -&gpio1 {
> - status = "disabled";
> -};
> -
> -&gpio2 {
> - status = "disabled";
> -};
> -
> -&gpio3 {
> - status = "disabled";
> -};
> -
> -&gpio4 {
> - status = "disabled";
> -};
> -
> -&uart3 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_uart3>;
> - status = "okay";
> -};
> -
> -&iomuxc {
> - pinctrl_uart3: uart3grp {
> - fsl,pins = <
> - VF610_PAD_PTA20__UART3_TX 0x21a2
> - VF610_PAD_PTA21__UART3_RX 0x21a1
> - >;
> - };
> -};
> diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi b/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi
> deleted file mode 100644
> index 648d219e1d0e..000000000000
> --- a/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi
> +++ /dev/null
> @@ -1,61 +0,0 @@
> -/*
> - * Device tree for VF6xx Cortex-M4 support
> - *
> - * Copyright (C) 2015 Stefan Agner
> - *
> - * This file is dual-licensed: you can use it either under the terms
> - * of the GPL or the X11 license, at your option. Note that this dual
> - * licensing only applies to this file, and not this project as a
> - * whole.
> - *
> - * a) This file is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of the
> - * License, or (at your option) any later version.
> - *
> - * This file is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * Or, alternatively,
> - *
> - * b) Permission is hereby granted, free of charge, to any person
> - * obtaining a copy of this software and associated documentation
> - * files (the "Software"), to deal in the Software without
> - * restriction, including without limitation the rights to use,
> - * copy, modify, merge, publish, distribute, sublicense, and/or
> - * sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following
> - * conditions:
> - *
> - * The above copyright notice and this permission notice shall be
> - * included in all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - */
> -
> -#include "../../armv7-m.dtsi"
> -#include "vfxxx.dtsi"
> -
> -/ {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - chosen { };
> - aliases { };
> -};
> -
> -&mscm_ir {
> - interrupt-parent = <&nvic>;
> -};
> -
> -&nvic {
> - arm,num-irq-priority-bits = <4>;
> -};
> diff --git a/arch/arm/configs/imxrt_defconfig b/arch/arm/configs/imxrt_defconfig
> deleted file mode 100644
> index 52dba3762996..000000000000
> --- a/arch/arm/configs/imxrt_defconfig
> +++ /dev/null
> @@ -1,35 +0,0 @@
> -# CONFIG_LOCALVERSION_AUTO is not set
> -CONFIG_BPF_SYSCALL=y
> -CONFIG_SCHED_AUTOGROUP=y
> -# CONFIG_MMU is not set
> -CONFIG_ARCH_MXC=y
> -CONFIG_SOC_IMXRT=y
> -CONFIG_SET_MEM_PARAM=y
> -CONFIG_DRAM_BASE=0x80000000
> -CONFIG_DRAM_SIZE=0x02000000
> -CONFIG_BINFMT_FLAT=y
> -CONFIG_UEVENT_HELPER=y
> -CONFIG_DEVTMPFS=y
> -CONFIG_DEVTMPFS_MOUNT=y
> -CONFIG_IMX_WEIM=y
> -CONFIG_LEGACY_PTY_COUNT=2
> -CONFIG_SERIAL_FSL_LPUART=y
> -CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
> -CONFIG_SERIAL_DEV_BUS=y
> -CONFIG_PINCTRL_IMXRT1050=y
> -CONFIG_GPIO_MXC=y
> -CONFIG_MMC=y
> -CONFIG_MMC_SDHCI=y
> -CONFIG_MMC_SDHCI_PLTFM=y
> -CONFIG_MMC_SDHCI_ESDHC_IMX=y
> -CONFIG_DMADEVICES=y
> -CONFIG_FSL_EDMA=y
> -CONFIG_CLK_IMXRT1050=y
> -CONFIG_EXT4_FS=y
> -CONFIG_EXT4_FS_POSIX_ACL=y
> -CONFIG_EXT4_FS_SECURITY=y
> -CONFIG_VFAT_FS=y
> -CONFIG_FAT_DEFAULT_UTF8=y
> -CONFIG_EXFAT_FS=y
> -CONFIG_NLS_ASCII=y
> -CONFIG_NLS_UTF8=y
> diff --git a/arch/arm/configs/vf610m4_defconfig b/arch/arm/configs/vf610m4_defconfig
> deleted file mode 100644
> index a5609cbfdfb3..000000000000
> --- a/arch/arm/configs/vf610m4_defconfig
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -CONFIG_NAMESPACES=y
> -CONFIG_BLK_DEV_INITRD=y
> -# CONFIG_RD_BZIP2 is not set
> -# CONFIG_RD_LZMA is not set
> -# CONFIG_RD_XZ is not set
> -# CONFIG_RD_LZ4 is not set
> -CONFIG_EXPERT=y
> -CONFIG_KALLSYMS_ALL=y
> -# CONFIG_MMU is not set
> -CONFIG_ARCH_MXC=y
> -CONFIG_SOC_VF610=y
> -CONFIG_SET_MEM_PARAM=y
> -CONFIG_DRAM_BASE=0x8c000000
> -CONFIG_FLASH_MEM_BASE=0x8f000000
> -CONFIG_FLASH_SIZE=0x01000000
> -CONFIG_CMDLINE="console=/dev/ttyLP2"
> -CONFIG_XIP_KERNEL=y
> -CONFIG_XIP_PHYS_ADDR=0x0f000080
> -# CONFIG_SUSPEND is not set
> -CONFIG_BINFMT_FLAT=y
> -CONFIG_BINFMT_ZFLAT=y
> -# CONFIG_UEVENT_HELPER is not set
> -# CONFIG_STANDALONE is not set
> -# CONFIG_PREVENT_FIRMWARE_BUILD is not set
> -# CONFIG_ALLOW_DEV_COREDUMP is not set
> -CONFIG_BLK_DEV_RAM=y
> -CONFIG_BLK_DEV_RAM_COUNT=4
> -# CONFIG_INPUT_MOUSEDEV is not set
> -# CONFIG_KEYBOARD_ATKBD is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_SERIO is not set
> -CONFIG_SERIAL_FSL_LPUART=y
> -CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
> -# CONFIG_HW_RANDOM is not set
> -CONFIG_MFD_SYSCON=y
> -# CONFIG_HID is not set
> -# CONFIG_USB_SUPPORT is not set
> -CONFIG_EXT4_FS=y
> -# CONFIG_MISC_FILESYSTEMS is not set
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 77704c6a70ba..cdc1b31fe573 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -2,7 +2,7 @@
> menuconfig ARCH_MXC
> bool "Freescale i.MX family"
> depends on ((ARCH_MULTI_V4T || ARCH_MULTI_V5) && CPU_LITTLE_ENDIAN) || \
> - ARCH_MULTI_V6_V7 || ARM_SINGLE_ARMV7M
> + ARCH_MULTI_V6_V7
> select CLKSRC_IMX_GPT
> select GENERIC_IRQ_CHIP
> select GPIOLIB
> @@ -174,7 +174,7 @@ config SOC_LS1021A
>
> endif
>
> -if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
> +if ARCH_MULTI_V7
>
> comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
>
> @@ -187,38 +187,23 @@ config SOC_IMX7D_CA7
> select HAVE_IMX_SRC
> select IMX_GPCV2
>
> -config SOC_IMX7D_CM4
> - bool
> - select ARMV7M_SYSTICK
> -
> config SOC_IMX7D
> bool "i.MX7 Dual support"
> - select SOC_IMX7D_CA7 if ARCH_MULTI_V7
> - select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
> - select ARM_ERRATA_814220 if ARCH_MULTI_V7
> + select SOC_IMX7D_CA7
> + select ARM_ERRATA_814220
> help
> This enables support for Freescale i.MX7 Dual processor.
>
> config SOC_IMX7ULP
> bool "i.MX7ULP support"
> select CLKSRC_IMX_TPM
> - select SOC_IMX7D_CA7 if ARCH_MULTI_V7
> - select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
> + select SOC_IMX7D_CA7
> help
> This enables support for Freescale i.MX7 Ultra Low Power processor.
>
> -config SOC_IMXRT
> - bool "i.MXRT support (DEPRECATED)"
> - depends on ARM_SINGLE_ARMV7M
> - select ARMV7M_SYSTICK if ARM_SINGLE_ARMV7M
> - help
> - This enables support for Freescale i.MXRT Crossover processor.
> -
> - This platform is scheduled for removal in early 2027
> -
> config SOC_VF610
> bool "Vybrid Family VF610 support"
> - select ARM_GIC if ARCH_MULTI_V7
> + select ARM_GIC
>
> help
> This enables support for Freescale Vybrid VF610 processor.
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index fa0144f0882d..135079340428 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -42,7 +42,6 @@ obj-$(CONFIG_SOC_IMX6SLL) += mach-imx6sl.o
> obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
> obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
> obj-$(CONFIG_SOC_IMX7D_CA7) += mach-imx7d.o
> -obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o
> obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o
>
> ifeq ($(CONFIG_SUSPEND),y)
> @@ -59,8 +58,6 @@ obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
> obj-$(CONFIG_SOC_IMX51) += mach-imx51.o
> obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
>
> -obj-$(CONFIG_SOC_IMXRT) += mach-imxrt.o
> -
> obj-$(CONFIG_SOC_VF610) += mach-vf610.o
>
> obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
> diff --git a/arch/arm/mach-imx/mach-imx7d-cm4.c b/arch/arm/mach-imx/mach-imx7d-cm4.c
> deleted file mode 100644
> index 0800b5891d2a..000000000000
> --- a/arch/arm/mach-imx/mach-imx7d-cm4.c
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
> - */
> -
> -#include <linux/kernel.h>
> -#include <asm/v7m.h>
> -#include <asm/mach/arch.h>
> -
> -static const char * const imx7d_cm4_dt_compat[] __initconst = {
> - "fsl,imx7d-cm4",
> - NULL,
> -};
> -
> -DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual Cortex-M4 (Device Tree)")
> - .dt_compat = imx7d_cm4_dt_compat,
> - .restart = armv7m_restart,
> -MACHINE_END
> diff --git a/arch/arm/mach-imx/mach-imxrt.c b/arch/arm/mach-imx/mach-imxrt.c
> deleted file mode 100644
> index 2063a3059c84..000000000000
> --- a/arch/arm/mach-imx/mach-imxrt.c
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * Copyright (C) 2019
> - * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> - */
> -
> -#include <linux/kernel.h>
> -#include <asm/mach/arch.h>
> -#include <asm/v7m.h>
> -
> -static const char *const imxrt_compat[] __initconst = {
> - "fsl,imxrt1050",
> - NULL
> -};
> -
> -DT_MACHINE_START(IMXRTDT, "IMXRT (Device Tree Support)")
> - .dt_compat = imxrt_compat,
> - .restart = armv7m_restart,
> -MACHINE_END
> diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
> index 208ff640698d..f77565381097 100644
> --- a/arch/arm/mach-imx/mach-vf610.c
> +++ b/arch/arm/mach-imx/mach-vf610.c
> @@ -59,7 +59,6 @@ static const char * const vf610_dt_compat[] __initconst = {
> "fsl,vf510",
> "fsl,vf600",
> "fsl,vf610",
> - "fsl,vf610m4",
> NULL,
> };
>
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH 09/13] ARM: lpc18xx: remove entire platform
2026-09-08 15:27 [PATCH 00/13] ARM: deprecated platform removal Arnd Bergmann
` (7 preceding siblings ...)
2026-09-08 15:27 ` [PATCH 08/13] ARM: imx: remove nommu support Arnd Bergmann
@ 2026-09-08 15:27 ` Arnd Bergmann
2026-09-08 17:36 ` Linus Walleij
2026-09-09 8:28 ` Vladimir Zapolskiy
2026-09-08 15:28 ` [PATCH 10/13] ARM: stm32: remove stm32f4/f7/h7 MCU support Arnd Bergmann
` (4 subsequent siblings)
13 siblings, 2 replies; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 15:27 UTC (permalink / raw)
To: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski
From: Arnd Bergmann <arnd@arndb.de>
The NXP LPC18xx and LPC43xx microcontrollers are the more modern
version of the classic LPC32xx line, but they lack memory management
units.
These microcontrollers all remain in production as of 2026, but
there are no known users running Linux on them.
The platform was marked deprecated in the 7.3-LTS release, which
will remain supported for a few more years.
Remove support for both LPC18xx and LPC43xx.
Cc: Frank Li <Frank.Li@nxp.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: imx@lists.linux.dev
Cc: devicetree@vger.kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
MAINTAINERS | 12 -
arch/arm/Kconfig | 14 -
arch/arm/Kconfig.debug | 9 -
arch/arm/Makefile | 1 -
arch/arm/boot/dts/nxp/lpc/Makefile | 5 -
arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 543 ---------------
arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts | 221 -------
.../boot/dts/nxp/lpc/lpc4350-hitex-eval.dts | 485 --------------
arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi | 48 --
.../dts/nxp/lpc/lpc4357-ea4357-devkit.dts | 624 ------------------
.../boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts | 621 -----------------
arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi | 52 --
arch/arm/configs/lpc18xx_defconfig | 158 -----
arch/arm/mach-lpc18xx/Makefile | 2 -
arch/arm/mach-lpc18xx/board-dt.c | 19 -
15 files changed, 2814 deletions(-)
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi
delete mode 100644 arch/arm/configs/lpc18xx_defconfig
delete mode 100644 arch/arm/mach-lpc18xx/Makefile
delete mode 100644 arch/arm/mach-lpc18xx/board-dt.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 0d10f778800d..292327185a08 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3032,18 +3032,6 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm64/boot/dts/lg/
-ARM/LPC18XX ARCHITECTURE
-M: Vladimir Zapolskiy <vz@mleia.com>
-L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-S: Maintained
-F: Documentation/devicetree/bindings/i2c/nxp,lpc1788-i2c.yaml
-F: arch/arm/boot/dts/nxp/lpc/lpc43*
-F: drivers/i2c/busses/i2c-lpc2k.c
-F: drivers/memory/pl172.c
-F: drivers/mtd/spi-nor/controllers/nxp-spifi.c
-F: drivers/rtc/rtc-lpc24xx.c
-N: lpc18xx
-
ARM/LPC32XX SOC SUPPORT
M: Vladimir Zapolskiy <vz@mleia.com>
M: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index da29afce309f..13b38be3353a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -443,20 +443,6 @@ source "arch/arm/mach-zte/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
-# ARMv7-M architecture
-config ARCH_LPC18XX
- bool "NXP LPC18xx/LPC43xx (DEPRECATED)"
- depends on ARM_SINGLE_ARMV7M
- select ARCH_HAS_RESET_CONTROLLER
- select ARM_AMBA
- select CLKSRC_LPC32XX
- select PINCTRL
- help
- Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
- high performance microcontrollers.
-
- This platform is scheduled for removal in early 2027
-
config ARCH_MPS2
bool "ARM MPS2 platform (DEPRECATED)"
depends on ARM_SINGLE_ARMV7M
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 52387fe2a057..e4910cf865da 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -511,14 +511,6 @@ choice
Say Y here if you want the debug print routines to direct
their output to UART1 serial port on KEYSTONE2 devices.
- config DEBUG_LPC18XX_UART0
- bool "Kernel low-level debugging via LPC18xx/43xx UART0"
- depends on ARCH_LPC18XX
- select DEBUG_UART_8250
- help
- Say Y here if you want kernel low-level debugging support
- on NXP LPC18xx/43xx UART0.
-
config DEBUG_LPC32XX
bool "Kernel low-level debugging messages via NXP LPC32xx UART"
depends on ARCH_LPC32XX
@@ -1551,7 +1543,6 @@ config DEBUG_UART_PHYS
default 0x40011000 if STM32F4_DEBUG_UART || STM32F7_DEBUG_UART || \
STM32H7_DEBUG_UART
default 0x40028000 if DEBUG_AT91_SAMV7_USART1
- default 0x40081000 if DEBUG_LPC18XX_UART0
default 0x40090000 if DEBUG_LPC32XX
default 0x40100000 if DEBUG_PXA_UART1
default 0x42000000 if DEBUG_GEMINI
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5421a3ec3825..d3479e374c6f 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -185,7 +185,6 @@ machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_HISI) += hisi
machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
-machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MMP) += mmp
diff --git a/arch/arm/boot/dts/nxp/lpc/Makefile b/arch/arm/boot/dts/nxp/lpc/Makefile
index 56b9a0ebb917..3f82628f3ff9 100644
--- a/arch/arm/boot/dts/nxp/lpc/Makefile
+++ b/arch/arm/boot/dts/nxp/lpc/Makefile
@@ -1,9 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_ARCH_LPC18XX) += \
- lpc4337-ciaa.dtb \
- lpc4350-hitex-eval.dtb \
- lpc4357-ea4357-devkit.dtb \
- lpc4357-myd-lpc4357.dtb
dtb-$(CONFIG_ARCH_LPC32XX) += \
lpc3250-ea3250.dtb \
lpc3250-phy3250.dtb
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi
deleted file mode 100644
index 152e98cf0c4e..000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi
+++ /dev/null
@@ -1,543 +0,0 @@
-/*
- * Common base for NXP LPC18xx and LPC43xx devices.
- *
- * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- *
- */
-
-#include "../../armv7-m.dtsi"
-
-#include "dt-bindings/clock/lpc18xx-cgu.h"
-#include "dt-bindings/clock/lpc18xx-ccu.h"
-
-#define LPC_PIN(port, pin) (0x##port * 32 + pin)
-#define LPC_GPIO(port, pin) (port * 32 + pin)
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- compatible = "arm,cortex-m3";
- device_type = "cpu";
- reg = <0x0>;
- clocks = <&ccu1 CLK_CPU_CORE>;
- };
- };
-
- clocks {
- xtal: xtal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <12000000>;
- };
-
- xtal32: xtal32 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
-
- enet_rx_clk: enet_rx_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- clock-output-names = "enet_rx_clk";
- };
-
- enet_tx_clk: enet_tx_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- clock-output-names = "enet_tx_clk";
- };
-
- gp_clkin: gp_clkin {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- clock-output-names = "gp_clkin";
- };
- };
-
- soc {
- sct_pwm: pwm@40000000 {
- compatible = "nxp,lpc1850-sct-pwm";
- reg = <0x40000000 0x1000>;
- clocks = <&ccu1 CLK_CPU_SCT>;
- clock-names = "pwm";
- resets = <&rgu 37>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- dmac: dma-controller@40002000 {
- compatible = "arm,pl080", "arm,primecell";
- arm,primecell-periphid = <0x00041080>;
- reg = <0x40002000 0x1000>;
- interrupts = <2>;
- clocks = <&ccu1 CLK_CPU_DMA>;
- clock-names = "apb_pclk";
- resets = <&rgu 19>;
- #dma-cells = <2>;
- dma-channels = <8>;
- dma-requests = <16>;
- lli-bus-interface-ahb1;
- lli-bus-interface-ahb2;
- mem-bus-interface-ahb1;
- mem-bus-interface-ahb2;
- memcpy-burst-size = <256>;
- memcpy-bus-width = <32>;
- };
-
- spifi: spi@40003000 {
- compatible = "nxp,lpc1773-spifi";
- reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
- reg-names = "spifi", "flash";
- interrupts = <30>;
- clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
- clock-names = "spifi", "reg";
- #address-cells = <1>;
- #size-cells = <0>;
- resets = <&rgu 53>;
- status = "disabled";
- };
-
- mmcsd: mmc@40004000 {
- compatible = "snps,dw-mshc";
- reg = <0x40004000 0x1000>;
- interrupts = <6>;
- clocks = <&ccu1 CLK_CPU_SDIO>, <&ccu2 CLK_SDIO>;
- clock-names = "biu", "ciu";
- resets = <&rgu 20>;
- status = "disabled";
- };
-
- usb0: usb@40006100 {
- compatible = "nxp,lpc1850-ehci", "generic-ehci";
- reg = <0x40006100 0x100>;
- interrupts = <8>;
- clocks = <&ccu1 CLK_CPU_USB0>;
- resets = <&rgu 17>;
- phys = <&usb0_otg_phy>;
- phy-names = "usb";
- has-transaction-translator;
- status = "disabled";
- };
-
- usb1: usb@40007100 {
- compatible = "nxp,lpc1850-ehci", "generic-ehci";
- reg = <0x40007100 0x100>;
- interrupts = <9>;
- clocks = <&ccu1 CLK_CPU_USB1>;
- resets = <&rgu 18>;
- status = "disabled";
- };
-
- emc: memory-controller@40005000 {
- compatible = "arm,pl172", "arm,primecell";
- reg = <0x40005000 0x1000>;
- clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
- clock-names = "mpmcclk", "apb_pclk";
- resets = <&rgu 21>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0x1c000000 0x1000000
- 1 0 0x1d000000 0x1000000
- 2 0 0x1e000000 0x1000000
- 3 0 0x1f000000 0x1000000>;
- status = "disabled";
- };
-
- lcdc: lcd-controller@40008000 {
- compatible = "arm,pl111", "arm,primecell";
- reg = <0x40008000 0x1000>;
- interrupts = <7>;
- interrupt-names = "combined";
- clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
- clock-names = "clcdclk", "apb_pclk";
- resets = <&rgu 16>;
- status = "disabled";
- };
-
- eeprom: eeprom@4000e000 {
- compatible = "nxp,lpc1857-eeprom";
- reg = <0x4000e000 0x1000>, <0x20040000 0x4000>;
- reg-names = "reg", "mem";
- clocks = <&ccu1 CLK_CPU_EEPROM>;
- clock-names = "eeprom";
- resets = <&rgu 27>;
- interrupts = <4>;
- status = "disabled";
- };
-
- mac: ethernet@40010000 {
- compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
- reg = <0x40010000 0x2000>;
- interrupts = <5>;
- interrupt-names = "macirq";
- clocks = <&ccu1 CLK_CPU_ETHERNET>;
- clock-names = "stmmaceth";
- resets = <&rgu 22>;
- reset-names = "stmmaceth";
- rx-fifo-depth = <256>;
- tx-fifo-depth = <256>;
- snps,pbl = <4>; /* 32 (8x mode) */
- snps,force_thresh_dma_mode;
- status = "disabled";
- };
-
- creg: syscon@40043000 {
- compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
- reg = <0x40043000 0x1000>;
- clocks = <&ccu1 CLK_CPU_CREG>;
- resets = <&rgu 5>;
-
- creg_clk: clock-controller {
- compatible = "nxp,lpc1850-creg-clk";
- clocks = <&xtal32>;
- #clock-cells = <1>;
- };
-
- usb0_otg_phy: phy {
- compatible = "nxp,lpc1850-usb-otg-phy";
- clocks = <&ccu1 CLK_USB0>;
- #phy-cells = <0>;
- };
-
- dmamux: dma-mux {
- compatible = "nxp,lpc1850-dmamux";
- #dma-cells = <3>;
- dma-requests = <64>;
- dma-masters = <&dmac>;
- };
- };
-
- rtc: rtc@40046000 {
- compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc";
- reg = <0x40046000 0x1000>;
- interrupts = <47>;
- clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
- clock-names = "rtc", "reg";
- };
-
- cgu: clock-controller@40050000 {
- compatible = "nxp,lpc1850-cgu";
- reg = <0x40050000 0x1000>;
- #clock-cells = <1>;
- clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
- };
-
- ccu1: clock-controller@40051000 {
- compatible = "nxp,lpc1850-ccu";
- reg = <0x40051000 0x1000>;
- #clock-cells = <1>;
- clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
- <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
- <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
- <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
- clock-names = "base_apb3_clk", "base_apb1_clk",
- "base_spifi_clk", "base_cpu_clk",
- "base_periph_clk", "base_usb0_clk",
- "base_usb1_clk", "base_spi_clk";
- };
-
- ccu2: clock-controller@40052000 {
- compatible = "nxp,lpc1850-ccu";
- reg = <0x40052000 0x1000>;
- #clock-cells = <1>;
- clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
- <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
- <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
- <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
- clock-names = "base_audio_clk", "base_uart3_clk",
- "base_uart2_clk", "base_uart1_clk",
- "base_uart0_clk", "base_ssp1_clk",
- "base_ssp0_clk", "base_sdio_clk";
- };
-
- rgu: reset-controller@40053000 {
- compatible = "nxp,lpc1850-rgu";
- reg = <0x40053000 0x1000>;
- clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
- clock-names = "delay", "reg";
- #reset-cells = <1>;
- };
-
- watchdog@40080000 {
- compatible = "nxp,lpc1850-wwdt";
- reg = <0x40080000 0x24>;
- interrupts = <49>;
- clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>;
- clock-names = "wdtclk", "reg";
- };
-
- uart0: serial@40081000 {
- compatible = "nxp,lpc1850-uart", "ns16550a";
- reg = <0x40081000 0x1000>;
- reg-shift = <2>;
- interrupts = <24>;
- clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
- clock-names = "uartclk", "reg";
- resets = <&rgu 44>;
- dmas = <&dmamux 1 1 2
- &dmamux 2 1 2
- &dmamux 11 2 2
- &dmamux 12 2 2>;
- dma-names = "tx", "rx", "tx", "rx";
- status = "disabled";
- };
-
- uart1: serial@40082000 {
- compatible = "nxp,lpc1850-uart", "ns16550a";
- reg = <0x40082000 0x1000>;
- reg-shift = <2>;
- interrupts = <25>;
- clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
- clock-names = "uartclk", "reg";
- resets = <&rgu 45>;
- dmas = <&dmamux 3 1 2
- &dmamux 4 1 2>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- ssp0: spi@40083000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x40083000 0x1000>;
- interrupts = <22>;
- clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
- clock-names = "sspclk", "apb_pclk";
- resets = <&rgu 50>;
- dmas = <&dmamux 9 0 2
- &dmamux 10 0 2>;
- dma-names = "rx", "tx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- timer0: timer@40084000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x40084000 0x1000>;
- interrupts = <12>;
- clocks = <&ccu1 CLK_CPU_TIMER0>;
- clock-names = "timerclk";
- resets = <&rgu 32>;
- };
-
- timer1: timer@40085000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x40085000 0x1000>;
- interrupts = <13>;
- clocks = <&ccu1 CLK_CPU_TIMER1>;
- clock-names = "timerclk";
- resets = <&rgu 33>;
- };
-
- pinctrl: pinctrl@40086000 {
- compatible = "nxp,lpc1850-scu";
- reg = <0x40086000 0x1000>;
- clocks = <&ccu1 CLK_CPU_SCU>;
- };
-
- i2c0: i2c@400a1000 {
- compatible = "nxp,lpc1788-i2c";
- reg = <0x400a1000 0x1000>;
- interrupts = <18>;
- clocks = <&ccu1 CLK_APB1_I2C0>;
- resets = <&rgu 48>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can1: can@400a4000 {
- compatible = "bosch,c_can";
- reg = <0x400a4000 0x1000>;
- interrupts = <43>;
- clocks = <&ccu1 CLK_APB1_CAN1>;
- resets = <&rgu 54>;
- status = "disabled";
- };
-
- uart2: serial@400c1000 {
- compatible = "nxp,lpc1850-uart", "ns16550a";
- reg = <0x400c1000 0x1000>;
- reg-shift = <2>;
- interrupts = <26>;
- clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
- clock-names = "uartclk", "reg";
- resets = <&rgu 46>;
- dmas = <&dmamux 5 1 2
- &dmamux 6 1 2>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- uart3: serial@400c2000 {
- compatible = "nxp,lpc1850-uart", "ns16550a";
- reg = <0x400c2000 0x1000>;
- reg-shift = <2>;
- interrupts = <27>;
- clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
- clock-names = "uartclk", "reg";
- resets = <&rgu 47>;
- dmas = <&dmamux 7 1 2
- &dmamux 8 1 2
- &dmamux 13 3 2
- &dmamux 14 3 2>;
- dma-names = "tx", "rx", "rx", "tx";
- status = "disabled";
- };
-
- timer2: timer@400c3000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x400c3000 0x1000>;
- interrupts = <14>;
- clocks = <&ccu1 CLK_CPU_TIMER2>;
- clock-names = "timerclk";
- resets = <&rgu 34>;
- };
-
- timer3: timer@400c4000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x400c4000 0x1000>;
- interrupts = <15>;
- clocks = <&ccu1 CLK_CPU_TIMER3>;
- clock-names = "timerclk";
- resets = <&rgu 35>;
- };
-
- ssp1: spi@400c5000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x400c5000 0x1000>;
- interrupts = <23>;
- clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
- clock-names = "sspclk", "apb_pclk";
- resets = <&rgu 51>;
- dmas = <&dmamux 11 2 2
- &dmamux 12 2 2
- &dmamux 3 3 2
- &dmamux 4 3 2
- &dmamux 5 2 2
- &dmamux 6 2 2
- &dmamux 13 2 2
- &dmamux 14 2 2>;
- dma-names = "rx", "tx", "tx", "rx",
- "tx", "rx", "rx", "tx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@400e0000 {
- compatible = "nxp,lpc1788-i2c";
- reg = <0x400e0000 0x1000>;
- interrupts = <19>;
- clocks = <&ccu1 CLK_APB3_I2C1>;
- resets = <&rgu 49>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- dac: dac@400e1000 {
- compatible = "nxp,lpc1850-dac";
- reg = <0x400e1000 0x1000>;
- interrupts = <0>;
- clocks = <&ccu1 CLK_APB3_DAC>;
- resets = <&rgu 42>;
- status = "disabled";
- };
-
- can0: can@400e2000 {
- compatible = "bosch,c_can";
- reg = <0x400e2000 0x1000>;
- interrupts = <51>;
- clocks = <&ccu1 CLK_APB3_CAN0>;
- resets = <&rgu 55>;
- status = "disabled";
- };
-
- adc0: adc@400e3000 {
- compatible = "nxp,lpc1850-adc";
- reg = <0x400e3000 0x1000>;
- interrupts = <17>;
- clocks = <&ccu1 CLK_APB3_ADC0>;
- resets = <&rgu 40>;
- status = "disabled";
- };
-
- adc1: adc@400e4000 {
- compatible = "nxp,lpc1850-adc";
- reg = <0x400e4000 0x1000>;
- interrupts = <21>;
- clocks = <&ccu1 CLK_APB3_ADC1>;
- resets = <&rgu 41>;
- status = "disabled";
- };
-
- gpio: gpio@400f4000 {
- compatible = "nxp,lpc1850-gpio";
- reg = <0x400f4000 0x4000>;
- clocks = <&ccu1 CLK_CPU_GPIO>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>,
- <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>,
- <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>,
- <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>,
- <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>,
- <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>,
- <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
- <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
- <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>,
- <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>,
- <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>,
- <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>,
- <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
- <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
- <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>,
- <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>,
- <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>,
- <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>,
- <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>,
- <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>,
- <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>,
- <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>,
- <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>,
- <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>,
- <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>,
- <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>,
- <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>,
- <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>,
- <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>,
- <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>,
- <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>,
- <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>,
- <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>,
- <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>,
- <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>,
- <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>,
- <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
- <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>,
- <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>,
- <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>;
- };
- };
-};
-
-&nvic {
- arm,num-irq-priority-bits = <3>;
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts b/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts
deleted file mode 100644
index 5ff43c825944..000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * CIAA NXP LPC4337 (http://www.proyecto-ciaa.com.ar)
- *
- * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- */
-/dts-v1/;
-
-#include "lpc18xx.dtsi"
-#include "lpc4357.dtsi"
-
-#include "dt-bindings/gpio/gpio.h"
-
-/ {
- model = "CIAA NXP LPC4337";
- compatible = "ciaa,lpc4337", "nxp,lpc4337", "nxp,lpc4350";
-
- aliases {
- serial0 = &uart2;
- serial1 = &uart3;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200 earlyprintk";
- stdout-path = &uart2;
- };
-
- memory@28000000 {
- device_type = "memory";
- reg = <0x28000000 0x0800000>; /* 8 MB */
- };
-};
-
-&pinctrl {
- enet_rmii_pins: enet-rmii-pins {
- enet_rmii_rxd_cfg {
- pins = "p1_15", "p0_0";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_txd_cfg {
- pins = "p1_18", "p1_20";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_rx_dv_cfg {
- pins = "p1_16";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_tx_en_cfg {
- pins = "p0_1";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_ref_clk_cfg {
- pins = "p1_19";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_mdio_cfg {
- pins = "p1_17";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_mdc_cfg {
- pins = "p7_7";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
- };
-
- i2c0_pins: i2c0-pins {
- i2c0_pins_cfg {
- pins = "i2c0_scl", "i2c0_sda";
- function = "i2c0";
- input-enable;
- };
- };
-
- ssp_pins: ssp-pins {
- ssp1_cs_cfg {
- pins = "p6_7";
- function = "gpio";
- bias-pull-up;
- bias-disable;
- };
-
- ssp1_miso_mosi_cfg {
- pins = "p1_3", "p1_4";
- function = "ssp1";
- slew-rate = <1>;
- bias-pull-down;
- input-enable;
- input-schmitt-disable;
- };
-
- ssp1_sck_cfg {
- pins = "pf_4";
- function = "ssp1";
- slew-rate = <1>;
- bias-disable;
- };
- };
-
- uart2_pins: uart2-pins {
- uart2_rx_cfg {
- pins = "p7_2";
- function = "uart2";
- bias-disable;
- input-enable;
- };
-
- uart2_tx_cfg {
- pins = "p7_1";
- function = "uart2";
- bias-disable;
- };
- };
-
- uart3_pins: uart3-pins {
- uart3_rx_cfg {
- pins = "p2_4";
- function = "uart3";
- bias-disable;
- input-enable;
- };
-
- uart3_tx_cfg {
- pins = "p2_3";
- function = "uart3";
- bias-disable;
- };
- };
-};
-
-&enet_tx_clk {
- clock-frequency = <50000000>;
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- clock-frequency = <400000>;
-
- eeprom@50 {
- compatible = "microchip,24c512", "atmel,24c512";
- reg = <0x50>;
- };
-
- eeprom@51 {
- compatible = "microchip,24c02", "atmel,24c02";
- reg = <0x51>;
- };
-
- eeprom@54 {
- compatible = "microchip,24c512", "atmel,24c512";
- reg = <0x54>;
- };
-};
-
-&mac {
- status = "okay";
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&enet_rmii_pins>;
-};
-
-&sct_pwm {
- status = "okay";
-};
-
-&ssp1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ssp_pins>;
- cs-gpios = <&gpio LPC_GPIO(5,15) GPIO_ACTIVE_HIGH>;
- num-cs = <1>;
-};
-
-&uart2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
-};
-
-&uart3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts
deleted file mode 100644
index 18f757c56905..000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts
+++ /dev/null
@@ -1,485 +0,0 @@
-/*
- * Hitex LPC4350 Evaluation Board
- *
- * Copyright 2015 Ariel D'Alessandro <ariel.dalessandro@gmail.com>
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- *
- */
-/dts-v1/;
-
-#include "lpc18xx.dtsi"
-#include "lpc4350.dtsi"
-
-#include "dt-bindings/input/input.h"
-#include "dt-bindings/gpio/gpio.h"
-
-/ {
- model = "Hitex LPC4350 Evaluation Board";
- compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- };
-
- chosen {
- stdout-path = &uart0;
- };
-
- memory@28000000 {
- device_type = "memory";
- reg = <0x28000000 0x800000>; /* 8 MB */
- };
-
- pca_buttons {
- compatible = "gpio-keys-polled";
- poll-interval = <100>;
- autorepeat;
-
- button-0 {
- label = "joy:right";
- linux,code = <KEY_RIGHT>;
- gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>;
- };
-
- button-1 {
- label = "joy:up";
- linux,code = <KEY_UP>;
- gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>;
- };
-
-
- button-2 {
- label = "joy:enter";
- linux,code = <KEY_ENTER>;
- gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>;
- };
-
- button-3 {
- label = "joy:left";
- linux,code = <KEY_LEFT>;
- gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>;
- };
-
- button-4 {
- label = "joy:down";
- linux,code = <KEY_DOWN>;
- gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>;
- };
-
- button-5 {
- label = "user:sw3";
- linux,code = <KEY_F1>;
- gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>;
- };
-
- button-6 {
- label = "user:sw4";
- linux,code = <KEY_F2>;
- gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>;
- };
-
- button-7 {
- label = "user:sw5";
- linux,code = <KEY_F3>;
- gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>;
- };
- };
-
- pca_leds {
- compatible = "gpio-leds";
-
- led0 {
- label = "ext:led0";
- gpios = <&pca_gpio 0 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
-
- led1 {
- label = "ext:led1";
- gpios = <&pca_gpio 1 GPIO_ACTIVE_LOW>;
- };
-
- led2 {
- label = "ext:led2";
- gpios = <&pca_gpio 2 GPIO_ACTIVE_LOW>;
- };
-
- led3 {
- label = "ext:led3";
- gpios = <&pca_gpio 3 GPIO_ACTIVE_LOW>;
- };
- };
-
- vcc: vcc_fixed {
- compatible = "regulator-fixed";
- regulator-name = "3v3io";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&pinctrl {
- adc1_pins: adc1-pins {
- adc1_pins_cfg {
- pins = "pf_9";
- function = "adc";
- input-disable;
- bias-disable;
- };
- };
-
- emc_pins: emc-pins {
- emc_addr0_23_cfg {
- pins = "p2_9", "p2_10", "p2_11", "p2_12",
- "p2_13", "p1_0", "p1_1", "p1_2",
- "p2_8", "p2_7", "p2_6", "p2_2",
- "p2_1", "p2_0", "p6_8", "p6_7",
- "pd_16", "pd_15", "pe_0", "pe_1",
- "pe_2", "pe_3", "pe_4", "pa_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_data0_15_cfg {
- pins = "p1_7", "p1_8", "p1_9", "p1_10",
- "p1_11", "p1_12", "p1_13", "p1_14",
- "p5_4", "p5_5", "p5_6", "p5_7",
- "p5_0", "p5_1", "p5_2", "p5_3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_we_oe_cfg {
- pins = "p1_6", "p1_3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_bls0_3_cfg {
- pins = "p1_4", "p6_6", "pd_13", "pd_10";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_cs0_cs2_cfg {
- pins = "p1_5", "pd_12";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_dqm0_3_cfg {
- pins = "p6_12", "p6_10", "pd_0", "pe_13";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_ras_cas_cfg {
- pins = "p6_5", "p6_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_dycs0_cfg {
- pins = "p6_9";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_cke_cfg {
- pins = "p6_11";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_clock_cfg {
- pins = "clk0", "clk1", "clk2", "clk3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
- };
-
- enet_mii_pins: enet-mii-pins {
- enet_mii_rxd0_3_cfg {
- pins = "p1_15", "p0_0", "p9_3", "p9_2";
- function = "enet";
- bias-disable;
- input-enable;
- };
-
- enet_mii_txd0_3_cfg {
- pins = "p1_18", "p1_20", "p9_4", "p9_5";
- function = "enet";
- bias-disable;
- };
-
- enet_mii_crs_col_cfg {
- pins = "p9_0", "p9_6";
- function = "enet";
- bias-disable;
- input-enable;
- };
-
- enet_mii_rx_clk_dv_er_cfg {
- pins = "pc_0", "p1_16", "p9_1";
- function = "enet";
- bias-disable;
- input-enable;
- };
-
- enet_mii_tx_clk_en_cfg {
- pins = "p1_19", "p0_1";
- function = "enet";
- bias-disable;
- input-enable;
- };
-
- enet_mdio_cfg {
- pins = "p1_17";
- function = "enet";
- bias-disable;
- input-enable;
- };
-
- enet_mdc_cfg {
- pins = "pc_1";
- function = "enet";
- bias-disable;
- };
- };
-
- i2c0_pins: i2c0-pins {
- i2c0_pins_cfg {
- pins = "i2c0_scl", "i2c0_sda";
- function = "i2c0";
- input-enable;
- };
- };
-
- spifi_pins: spifi-pins {
- spifi_clk_cfg {
- pins = "p3_3";
- function = "spifi";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- spifi_mosi_miso_sio2_3_cfg {
- pins = "p3_7", "p3_6", "p3_5", "p3_4";
- function = "spifi";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- spifi_cs_cfg {
- pins = "p3_8";
- function = "spifi";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
- };
-
- uart0_pins: uart0-pins {
- uart0_rx_cfg {
- pins = "pf_11";
- function = "uart0";
- input-schmitt-disable;
- bias-disable;
- input-enable;
- };
-
- uart0_tx_cfg {
- pins = "pf_10";
- function = "uart0";
- bias-pull-down;
- };
- };
-};
-
-&adc1 {
- status = "okay";
- vref-supply = <&vcc>;
- pinctrl-names = "default";
- pinctrl-0 = <&adc1_pins>;
-};
-
-&emc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&emc_pins>;
-
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- mpmc,cs = <0>;
- mpmc,memory-width = <16>;
- mpmc,byte-lane-low;
- mpmc,write-enable-delay = <0>;
- mpmc,output-enable-delay = <0>;
- mpmc,read-access-delay = <70>;
- mpmc,page-mode-read-delay = <70>;
-
- flash@0,0 {
- compatible = "sst,sst39vf320", "cfi-flash";
- reg = <0 0 0x400000>;
- bank-width = <2>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "bootloader";
- reg = <0x000000 0x040000>; /* 256 KiB */
- };
-
- partition@1 {
- label = "kernel";
- reg = <0x040000 0x2C0000>; /* 2.75 MiB */
- };
-
- partition@2 {
- label = "rootfs";
- reg = <0x300000 0x100000>; /* 1 MiB */
- };
- };
- };
-
- cs2 {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- mpmc,cs = <2>;
- mpmc,memory-width = <16>;
- mpmc,byte-lane-low;
- mpmc,write-enable-delay = <0>;
- mpmc,output-enable-delay = <30>;
- mpmc,read-access-delay = <90>;
- mpmc,page-mode-read-delay = <55>;
- mpmc,write-access-delay = <55>;
- mpmc,turn-round-delay = <55>;
-
- ext_sram: sram@2,0 {
- compatible = "mmio-sram";
- reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 2 0 0x80000>;
- };
- };
-};
-
-&enet_tx_clk {
- clock-frequency = <25000000>;
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- clock-frequency = <400000>;
-
- /* NXP SE97BTP with temperature sensor + eeprom */
- sensor@18 {
- compatible = "nxp,se97", "jedec,jc-42.4-temp";
- reg = <0x18>;
- };
-
- eeprom@50 {
- compatible = "nxp,24c02", "atmel,24c02";
- reg = <0x50>;
- };
-
- pca_gpio: gpio@24 {
- compatible = "nxp,pca9673";
- reg = <0x24>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&mac {
- status = "okay";
- phy-mode = "mii";
- pinctrl-names = "default";
- pinctrl-0 = <&enet_mii_pins>;
-};
-
-&spifi {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spifi_pins>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-rx-bus-width = <4>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "bootloader";
- reg = <0x000000 0x040000>; /* 256 KiB */
- };
-
- partition@1 {
- label = "kernel";
- reg = <0x040000 0x2c0000>; /* 2.75 MiB */
- };
-
- partition@2 {
- label = "rootfs";
- reg = <0x300000 0x500000>; /* 5 MiB */
- };
- };
-};
-
-&uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi
deleted file mode 100644
index 707d22a219d8..000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * NXP LPC4350 and LPC4330 SoC
- *
- * Copyright 2015 Ariel D'Alessandro <ariel.dalessandro@gmail.com>
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- *
- */
-
-/ {
- compatible = "nxp,lpc4350", "nxp,lpc4330";
-
- cpus {
- cpu@0 {
- compatible = "arm,cortex-m4";
- };
- };
-
- soc {
- sram0: sram@10000000 {
- compatible = "mmio-sram";
- reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
-
- sram1: sram@10080000 {
- compatible = "mmio-sram";
- reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
-
- sram2: sram@20000000 {
- compatible = "mmio-sram";
- reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
- };
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts
deleted file mode 100644
index 7ccb4c2ca571..000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts
+++ /dev/null
@@ -1,624 +0,0 @@
-/*
- * Embedded Artist LPC4357 Developer's Kit
- *
- * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- *
- */
-/dts-v1/;
-
-#include "lpc18xx.dtsi"
-#include "lpc4357.dtsi"
-
-#include "dt-bindings/input/input.h"
-#include "dt-bindings/gpio/gpio.h"
-
-/ {
- model = "Embedded Artists' LPC4357 Developer's Kit";
- compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350";
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- };
-
- chosen {
- stdout-path = &uart0;
- };
-
- memory@28000000 {
- device_type = "memory";
- reg = <0x28000000 0x2000000>; /* 32 MB */
- };
-
- vcc: vcc_fixed {
- compatible = "regulator-fixed";
- regulator-name = "3v3-supply";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- /* vmmc is controlled by sdmmc host internally */
- vmmc: vmmc_fixed {
- compatible = "regulator-fixed";
- regulator-name = "vmmc-supply";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- gpio_joystick {
- compatible = "gpio-keys-polled";
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_joystick_pins>;
- poll-interval = <100>;
- autorepeat;
-
- button-0 {
- label = "joy_enter";
- linux,code = <KEY_ENTER>;
- gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>;
- };
-
- button-1 {
- label = "joy_left";
- linux,code = <KEY_LEFT>;
- gpios = <&gpio LPC_GPIO(4,9) GPIO_ACTIVE_LOW>;
- };
-
- button-2 {
- label = "joy_up";
- linux,code = <KEY_UP>;
- gpios = <&gpio LPC_GPIO(4,10) GPIO_ACTIVE_LOW>;
- };
-
- button-3 {
- label = "joy_right";
- linux,code = <KEY_RIGHT>;
- gpios = <&gpio LPC_GPIO(4,12) GPIO_ACTIVE_LOW>;
- };
-
- button-4 {
- label = "joy_down";
- linux,code = <KEY_DOWN>;
- gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>;
- };
- };
-
- leds_mmio {
- compatible = "gpio-leds";
-
- led1 {
- gpios = <&mmio_leds 15 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
-
- led2 {
- gpios = <&mmio_leds 14 GPIO_ACTIVE_HIGH>;
- };
-
- led3 {
- gpios = <&mmio_leds 13 GPIO_ACTIVE_HIGH>;
- };
-
- led4 {
- gpios = <&mmio_leds 12 GPIO_ACTIVE_HIGH>;
- };
-
- led5 {
- gpios = <&mmio_leds 11 GPIO_ACTIVE_HIGH>;
- };
-
- led6 {
- gpios = <&mmio_leds 10 GPIO_ACTIVE_HIGH>;
- };
-
- led7 {
- gpios = <&mmio_leds 9 GPIO_ACTIVE_HIGH>;
- };
-
- led8 {
- gpios = <&mmio_leds 8 GPIO_ACTIVE_HIGH>;
- };
-
- led9 {
- gpios = <&mmio_leds 7 GPIO_ACTIVE_HIGH>;
- };
-
- led10 {
- gpios = <&mmio_leds 6 GPIO_ACTIVE_HIGH>;
- };
-
- led11 {
- gpios = <&mmio_leds 5 GPIO_ACTIVE_HIGH>;
- };
-
- led12 {
- gpios = <&mmio_leds 4 GPIO_ACTIVE_HIGH>;
- };
-
- led13 {
- gpios = <&mmio_leds 3 GPIO_ACTIVE_HIGH>;
- };
-
- led14 {
- gpios = <&mmio_leds 2 GPIO_ACTIVE_HIGH>;
- };
-
- led15 {
- gpios = <&mmio_leds 1 GPIO_ACTIVE_HIGH>;
- };
-
- led16 {
- gpios = <&mmio_leds 0 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&pinctrl {
- emc_pins: emc-pins {
- emc_addr0_23_cfg {
- pins = "p2_9", "p2_10", "p2_11", "p2_12",
- "p2_13", "p1_0", "p1_1", "p1_2",
- "p2_8", "p2_7", "p2_6", "p2_2",
- "p2_1", "p2_0", "p6_8", "p6_7",
- "pd_16", "pd_15", "pe_0", "pe_1",
- "pe_2", "pe_3", "pe_4", "pa_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_data0_31_cfg {
- pins = "p1_7", "p1_8", "p1_9", "p1_10",
- "p1_11", "p1_12", "p1_13", "p1_14",
- "p5_4", "p5_5", "p5_6", "p5_7",
- "p5_0", "p5_1", "p5_2", "p5_3",
- "pd_2", "pd_3", "pd_4", "pd_5",
- "pd_6", "pd_7", "pd_8", "pd_9",
- "pe_5", "pe_6", "pe_7", "pe_8",
- "pe_9", "pe_10", "pe_11", "pe_12";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_we_oe_cfg {
- pins = "p1_6", "p1_3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_bls0_3_cfg {
- pins = "p1_4", "p6_6", "pd_13", "pd_10";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_cs0_3_cfg {
- pins = "p1_5", "p6_3", "pd_12", "pd_11";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_dqm0_3_cfg {
- pins = "p6_12", "p6_10", "pd_0", "pe_13";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_ras_cas_cfg {
- pins = "p6_5", "p6_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_dycs0_cfg {
- pins = "p6_9";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_cke_cfg {
- pins = "p6_11";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_clock_cfg {
- pins = "clk0", "clk1", "clk2", "clk3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
- };
-
- enet_rmii_pins: enet-rmii-pins {
- enet_rmii_rxd_cfg {
- pins = "p1_15", "p0_0";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_txd_cfg {
- pins = "p1_18", "p1_20";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_rx_dv_cfg {
- pins = "p1_16";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_tx_en_cfg {
- pins = "p0_1";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_ref_clk_cfg {
- pins = "p1_19";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_mdio_cfg {
- pins = "p1_17";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_mdc_cfg {
- pins = "pc_1";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
- };
-
- gpio_joystick_pins: gpio-joystick-pins {
- gpio_joystick_cfg {
- pins = "p9_0", "p9_1", "pa_1", "pa_2", "pa_3";
- function = "gpio";
- input-enable;
- bias-disable;
- };
- };
-
- i2c0_pins: i2c0-pins {
- i2c0_pins_cfg {
- pins = "i2c0_scl", "i2c0_sda";
- function = "i2c0";
- input-enable;
- };
- };
-
- sdmmc_pins: sdmmc-pins {
- sdmmc_clk_cfg {
- pins = "pc_0";
- function = "sdmmc";
- slew-rate = <1>;
- bias-pull-down;
- };
-
- sdmmc_cmd_dat0_3_cfg {
- pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10";
- function = "sdmmc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- sdmmc_cd_cfg {
- pins = "pc_8";
- function = "sdmmc";
- bias-pull-down;
- input-enable;
- };
-
- sdmmc_pow_cfg {
- pins = "pc_9";
- function = "sdmmc";
- bias-pull-down;
- };
- };
-
- spifi_pins: spifi-pins {
- spifi_clk_cfg {
- pins = "p3_3";
- function = "spifi";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- spifi_mosi_miso_sio2_3_cfg {
- pins = "p3_7", "p3_6", "p3_5", "p3_4";
- function = "spifi";
- slew-rate = <0>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- spifi_cs_cfg {
- pins = "p3_8";
- function = "spifi";
- bias-disable;
- };
- };
-
- ssp0_pins: ssp0-pins {
- ssp0_sck_miso_mosi_cfg {
- pins = "pf_0", "pf_2", "pf_3";
- function = "ssp0";
- slew-rate = <1>;
- bias-pull-down;
- input-enable;
- input-schmitt-disable;
- };
-
- ssp0_ssel_cfg {
- pins = "pf_1";
- function = "ssp0";
- bias-pull-up;
- };
- };
-
- uart0_pins: uart0-pins {
- uart0_rx_cfg {
- pins = "pf_11";
- function = "uart0";
- input-schmitt-disable;
- bias-disable;
- input-enable;
- };
-
- uart0_tx_cfg {
- pins = "pf_10";
- function = "uart0";
- bias-pull-down;
- };
- };
-
- uart3_pins: uart3-pins {
- uart3_rx_cfg {
- pins = "p2_4";
- function = "uart3";
- input-schmitt-disable;
- bias-disable;
- input-enable;
- };
-
- uart3_tx_cfg {
- pins = "p9_3";
- function = "uart3";
- bias-pull-down;
- };
- };
-
- usb0_pins: usb0-pins {
- usb0_pwr_enable_cfg {
- pins = "p2_3";
- function = "usb0";
- };
-
- usb0_pwr_fault_cfg {
- pins = "p8_0";
- function = "usb0";
- bias-disable;
- input-enable;
- };
- };
-};
-
-&adc0 {
- status = "okay";
- vref-supply = <&vcc>;
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- clock-frequency = <400000>;
-
- mma7455@1d {
- compatible = "fsl,mma7455";
- reg = <0x1d>;
- };
-
- temperature-sensor@48 {
- compatible = "national,lm75b";
- reg = <0x48>;
- };
-
- eeprom@57 {
- compatible = "microchip,24c64", "atmel,24c64";
- reg = <0x57>;
- };
-};
-
-&dac {
- status = "okay";
- vref-supply = <&vcc>;
-};
-
-&emc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&emc_pins>;
-
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- mpmc,cs = <0>;
- mpmc,memory-width = <16>;
- mpmc,byte-lane-low;
- mpmc,write-enable-delay = <0>;
- mpmc,output-enable-delay = <0>;
- mpmc,read-access-delay = <70>;
- mpmc,page-mode-read-delay = <70>;
-
- flash@0,0 {
- compatible = "sst,sst39vf320", "cfi-flash";
- reg = <0 0 0x400000>;
- bank-width = <2>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "bootloader";
- reg = <0x000000 0x040000>; /* 256 KiB */
- };
-
- partition@1 {
- label = "kernel";
- reg = <0x040000 0x2c0000>; /* 2.75 MiB */
- };
-
- partition@2 {
- label = "rootfs";
- reg = <0x300000 0x100000>; /* 1 MiB */
- };
- };
- };
-
- cs2 {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- mpmc,cs = <2>;
- mpmc,memory-width = <16>;
-
- mmio_leds: gpio@2,0 {
- compatible = "ti,7416374";
- reg = <2 0 0x2>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- };
-};
-
-&enet_tx_clk {
- clock-frequency = <50000000>;
-};
-
-&mac {
- status = "okay";
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&enet_rmii_pins>;
-};
-
-&mmcsd {
- status = "okay";
- bus-width = <4>;
- vmmc-supply = <&vmmc>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_pins>;
-};
-
-&spifi {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spifi_pins>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-cpol;
- spi-cpha;
- spi-rx-bus-width = <4>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "data";
- reg = <0 0x200000>;
- };
- };
-};
-
-&ssp0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ssp0_pins>;
- num-cs = <1>;
-};
-
-&uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
-};
-
-&uart3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
-};
-
-&usb0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins>;
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts
deleted file mode 100644
index d18f2b2caf68..000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts
+++ /dev/null
@@ -1,621 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel
- *
- * Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
- */
-
-/dts-v1/;
-
-#include "lpc18xx.dtsi"
-#include "lpc4357.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "MYIR Tech LPC4357 Development Board";
- compatible = "myir,myd-lpc4357", "nxp,lpc4357";
-
- chosen {
- stdout-path = "serial3:115200n8";
- };
-
- memory@28000000 {
- device_type = "memory";
- reg = <0x28000000 0x2000000>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins>;
-
- led1 {
- gpios = <&gpio LPC_GPIO(6,15) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led2 {
- gpios = <&gpio LPC_GPIO(6,16) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led3 {
- gpios = <&gpio LPC_GPIO(6,17) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led4 {
- gpios = <&gpio LPC_GPIO(6,10) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led5 {
- gpios = <&gpio LPC_GPIO(7,14) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led6 {
- gpios = <&gpio LPC_GPIO(6,14) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
- };
-
- panel: panel {
- compatible = "innolux,at070tn92";
- power-supply = <&vcc>;
-
- port {
- panel_input: endpoint {
- remote-endpoint = <&lcdc_output>;
- };
- };
- };
-
- vcc: vcc_fixed {
- compatible = "regulator-fixed";
- regulator-name = "vcc-supply";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vmmc: vmmc_fixed {
- compatible = "regulator-fixed";
- regulator-name = "vmmc-supply";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&pinctrl {
- can0_pins: can0-pins {
- can_rd_cfg {
- pins = "p3_1";
- function = "can0";
- input-enable;
- };
-
- can_td_cfg {
- pins = "p3_2";
- function = "can0";
- };
- };
-
- can1_pins: can1-pins {
- can_rd_cfg {
- pins = "pe_1";
- function = "can1";
- input-enable;
- };
-
- can_td_cfg {
- pins = "pe_0";
- function = "can1";
- };
- };
-
- emc_pins: emc-pins {
- emc_addr0_22_cfg {
- pins = "p2_9", "p2_10", "p2_11", "p2_12",
- "p2_13", "p1_0", "p1_1", "p1_2",
- "p2_8", "p2_7", "p2_6", "p2_2",
- "p2_1", "p2_0", "p6_8", "p6_7",
- "pd_16", "pd_15", "pe_0", "pe_1",
- "pe_2", "pe_3", "pe_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_data0_15_cfg {
- pins = "p1_7", "p1_8", "p1_9", "p1_10",
- "p1_11", "p1_12", "p1_13", "p1_14",
- "p5_4", "p5_5", "p5_6", "p5_7",
- "p5_0", "p5_1", "p5_2", "p5_3";
- function = "emc";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_we_oe_cfg {
- pins = "p1_6", "p1_3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_cs0_cfg {
- pins = "p1_5";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_sdram_dqm0_1_cfg {
- pins = "p6_12", "p6_10";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_sdram_ras_cas_cfg {
- pins = "p6_5", "p6_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_sdram_dycs0_cfg {
- pins = "p6_9";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_sdram_cke_cfg {
- pins = "p6_11";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_sdram_clock_cfg {
- pins = "clk0";
- function = "emc";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
- };
-
- enet_rmii_pins: enet-rmii-pins {
- enet_rmii_rxd_cfg {
- pins = "p1_15", "p0_0";
- function = "enet";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
-
- enet_rmii_txd_cfg {
- pins = "p1_18", "p1_20";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- };
-
- enet_rmii_rx_dv_cfg {
- pins = "p1_16";
- function = "enet";
- input-enable;
- input-schmitt-disable;
- bias-disable;
- };
-
- enet_mdio_cfg {
- pins = "p1_17";
- function = "enet";
- input-enable;
- input-schmitt-disable;
- bias-disable;
- };
-
- enet_mdc_cfg {
- pins = "pc_1";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- };
-
- enet_rmii_tx_en_cfg {
- pins = "p0_1";
- function = "enet";
- bias-disable;
- };
-
- enet_ref_clk_cfg {
- pins = "p1_19";
- function = "enet";
- slew-rate = <1>;
- input-enable;
- input-schmitt-disable;
- bias-disable;
- };
- };
-
- i2c0_pins: i2c0-pins {
- i2c0_pins_cfg {
- pins = "i2c0_scl", "i2c0_sda";
- function = "i2c0";
- input-enable;
- };
- };
-
- i2c1_pins: i2c1-pins {
- i2c1_pins_cfg {
- pins = "pe_15", "pe_13";
- function = "i2c1";
- input-enable;
- };
- };
-
- lcd_pins: lcd-pins {
- lcd_vd0_23_cfg {
- pins = "p4_1", "p4_4", "p4_3", "p4_2",
- "p8_7", "p8_6", "p8_5", "p8_4",
- "p7_5", "p4_8", "p4_10", "p4_9",
- "p8_3", "pb_6", "pb_5", "pb_4",
- "p7_4", "p7_3", "p7_2", "p7_1",
- "pb_3", "pb_2", "pb_1", "pb_0";
- function = "lcd";
- };
-
- lcd_vsync_en_dclk_lp_pwr_cfg {
- pins = "p4_5", "p4_6", "p4_7", "p7_6", "p7_7";
- function = "lcd";
- };
- };
-
- led_pins: led-pins {
- led_1_6_cfg {
- pins = "pd_1", "pd_2", "pd_3", "pc_11", "pe_14", "pd_0";
- function = "gpio";
- bias-pull-down;
- };
- };
-
- sdmmc_pins: sdmmc-pins {
- sdmmc_clk_cfg {
- pins = "pc_0";
- function = "sdmmc";
- slew-rate = <1>;
- bias-pull-down;
- };
-
- sdmmc_cmd_dat0_3_cfg {
- pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10";
- function = "sdmmc";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
-
- sdmmc_cd_cfg {
- pins = "pc_8";
- function = "sdmmc";
- input-enable;
- bias-pull-down;
- };
- };
-
- spifi_pins: spifi-pins {
- spifi_sck_cfg {
- pins = "p3_3";
- function = "spifi";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
-
- spifi_mosi_miso_sio2_sio3_cfg {
- pins = "p3_7", "p3_6", "p3_5", "p3_4";
- function = "spifi";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
-
- spifi_cs_cfg {
- pins = "p3_8";
- function = "spifi";
- bias-disable;
- };
- };
-
- ssp1_pins: ssp1-pins {
- ssp1_sck_cfg {
- pins = "pf_4";
- function = "ssp1";
- slew-rate = <1>;
- bias-pull-down;
- };
-
- ssp1_miso_cfg {
- pins = "pf_6";
- function = "ssp1";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-pull-down;
- };
-
- ssp1_mosi_cfg {
- pins = "pf_7";
- function = "ssp1";
- slew-rate = <1>;
- bias-pull-down;
- };
-
- ssp1_ssel_cfg {
- pins = "pf_5";
- function = "gpio";
- bias-disable;
- };
- };
-
- uart0_pins: uart0-pins {
- uart0_rxd_cfg {
- pins = "pf_11";
- function = "uart0";
- input-enable;
- input-schmitt-disable;
- bias-disable;
- };
-
- uart0_clk_dir_txd_cfg {
- pins = "pf_8", "pf_9", "pf_10";
- function = "uart0";
- bias-pull-down;
- };
- };
-
- uart1_pins: uart1-pins {
- uart1_rxd_cfg {
- pins = "pc_14";
- function = "uart1";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- uart1_dtr_txd_cfg {
- pins = "pc_12", "pc_13";
- function = "uart1";
- bias-pull-down;
- };
- };
-
- uart2_pins: uart2-pins {
- uart2_rxd_cfg {
- pins = "pa_2";
- function = "uart2";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- uart2_txd_cfg {
- pins = "pa_1";
- function = "uart2";
- bias-pull-down;
- };
- };
-
- uart3_pins: uart3-pins {
- uart3_rx_cfg {
- pins = "p2_4";
- function = "uart3";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- uart3_tx_cfg {
- pins = "p2_3";
- function = "uart3";
- bias-pull-down;
- };
- };
-
- usb0_pins: usb0-pins {
- usb0_pwr_enable_cfg {
- pins = "p6_3";
- function = "usb0";
- };
-
- usb0_pwr_fault_cfg {
- pins = "p8_0";
- function = "usb0";
- bias-disable;
- input-enable;
- };
- };
-};
-
-&adc1 {
- status = "okay";
- vref-supply = <&vcc>;
-};
-
-&can0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&can0_pins>;
-};
-
-/* Pin conflict with EMC, muxed by JP5 and JP6 */
-&can1 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&can1_pins>;
-};
-
-&emc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&emc_pins>;
-
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- mpmc,cs = <0>;
- mpmc,memory-width = <16>;
- mpmc,byte-lane-low;
- mpmc,write-enable-delay = <0>;
- mpmc,output-enable-delay = <0>;
- mpmc,read-access-delay = <70>;
- mpmc,page-mode-read-delay = <70>;
-
- /* SST/Microchip SST39VF1601 */
- flash@0,0 {
- compatible = "cfi-flash";
- reg = <0 0 0x400000>;
- bank-width = <2>;
- };
- };
-};
-
-&enet_tx_clk {
- clock-frequency = <50000000>;
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- clock-frequency = <400000>;
-};
-
-&i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- clock-frequency = <400000>;
-
- sensor@49 {
- compatible = "national,lm75";
- reg = <0x49>;
- };
-
- eeprom@50 {
- compatible = "atmel,24c512";
- reg = <0x50>;
- };
-};
-
-&lcdc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_pins>;
-
- max-memory-bandwidth = <92240000>;
-
- port {
- lcdc_output: endpoint {
- remote-endpoint = <&panel_input>;
- arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
- };
- };
-};
-
-&mac {
- status = "okay";
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&enet_rmii_pins>;
- phy-handle = <&phy1>;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
-};
-
-&mmcsd {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_pins>;
- bus-width = <4>;
- vmmc-supply = <&vmmc>;
-};
-
-/* Pin conflict with SSP0, the latter is routed to J17 pin header */
-&spifi {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spifi_pins>;
-
- /* Atmel AT25DF321A */
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <51000000>;
- spi-cpol;
- spi-cpha;
- };
-};
-
-&ssp1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ssp1_pins>;
- num-cs = <1>;
- cs-gpios = <&gpio LPC_GPIO(7,19) GPIO_ACTIVE_LOW>;
-};
-
-/* Routed to J17 pin header */
-&uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
-};
-
-/* RS485 */
-&uart1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
-};
-
-/* Routed to J17 pin header */
-&uart2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
-};
-
-&uart3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
-};
-
-&usb0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins>;
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi
deleted file mode 100644
index d138ee7869ff..000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * NXP LPC435x, LPC433x, LPC4327, LPC4325, LPC4317 and LPC4315 SoC
- *
- * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- *
- */
-
-/ {
- compatible = "nxp,lpc4357";
-
- cpus {
- cpu@0 {
- compatible = "arm,cortex-m4";
- };
- };
-
- soc {
- sram0: sram@10000000 {
- compatible = "mmio-sram";
- reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
-
- sram1: sram@10080000 {
- compatible = "mmio-sram";
- reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
-
- sram2: sram@20000000 {
- compatible = "mmio-sram";
- reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
- };
-};
-
-&eeprom {
- status = "okay";
-};
diff --git a/arch/arm/configs/lpc18xx_defconfig b/arch/arm/configs/lpc18xx_defconfig
deleted file mode 100644
index f142a6637ede..000000000000
--- a/arch/arm/configs/lpc18xx_defconfig
+++ /dev/null
@@ -1,158 +0,0 @@
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-# CONFIG_RD_XZ is not set
-# CONFIG_RD_LZO is not set
-# CONFIG_RD_LZ4 is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_UID16 is not set
-CONFIG_BASE_SMALL=y
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_EXPERT=y
-# CONFIG_MMU is not set
-CONFIG_ARCH_LPC18XX=y
-CONFIG_SET_MEM_PARAM=y
-CONFIG_DRAM_BASE=0x28000000
-CONFIG_DRAM_SIZE=0x02000000
-CONFIG_FLASH_MEM_BASE=0x1b000000
-CONFIG_FLASH_SIZE=0x00080000
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-# CONFIG_COREDUMP is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_SPI_NOR=y
-# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
-CONFIG_SPI_NXP_SPIFI=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SRAM=y
-CONFIG_EEPROM_AT24=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_ARC is not set
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CIRRUS is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-# CONFIG_NET_VENDOR_HISILICON is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_QUALCOMM is not set
-# CONFIG_NET_VENDOR_ROCKER is not set
-# CONFIG_NET_VENDOR_SAMSUNG is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-CONFIG_STMMAC_ETH=y
-# CONFIG_NET_VENDOR_VIA is not set
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_SMSC_PHY=y
-# CONFIG_USB_NET_DRIVERS is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_GPIO_POLLED=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_UNIX98_PTYS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C_LPC2K=y
-CONFIG_SPI=y
-CONFIG_SPI_PL022=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_74XX_MMIO=y
-CONFIG_GPIO_PCF857X=y
-CONFIG_SENSORS_JC42=y
-CONFIG_SENSORS_LM75=y
-CONFIG_WATCHDOG=y
-CONFIG_LPC18XX_WATCHDOG=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_DRM=y
-CONFIG_DRM_PL111=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=y
-CONFIG_MMC_DW=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_PCA9532=y
-CONFIG_LEDS_PCA9532_GPIO=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_LPC24XX=y
-CONFIG_DMADEVICES=y
-CONFIG_AMBA_PL08X=y
-CONFIG_LPC18XX_DMAMUX=y
-CONFIG_MEMORY=y
-CONFIG_ARM_PL172_MPMC=y
-CONFIG_IIO=y
-CONFIG_MMA7455_I2C=y
-CONFIG_LPC18XX_ADC=y
-CONFIG_LPC18XX_DAC=y
-CONFIG_IIO_SYSFS_TRIGGER=y
-CONFIG_PWM=y
-CONFIG_PWM_LPC18XX_SCT=y
-CONFIG_PHY_LPC18XX_USB_OTG=y
-CONFIG_NVMEM_LPC18XX_EEPROM=y
-CONFIG_EXT2_FS=y
-# CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-CONFIG_JFFS2_FS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PRINTK_TIME=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/mach-lpc18xx/Makefile b/arch/arm/mach-lpc18xx/Makefile
deleted file mode 100644
index c80d80c199d3..000000000000
--- a/arch/arm/mach-lpc18xx/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-obj-y += board-dt.o
diff --git a/arch/arm/mach-lpc18xx/board-dt.c b/arch/arm/mach-lpc18xx/board-dt.c
deleted file mode 100644
index 4729eb83401a..000000000000
--- a/arch/arm/mach-lpc18xx/board-dt.c
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree board file for NXP LPC18xx/43xx
- *
- * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
- */
-
-#include <asm/mach/arch.h>
-
-static const char *const lpc18xx_43xx_compat[] __initconst = {
- "nxp,lpc1850",
- "nxp,lpc4350",
- "nxp,lpc4370",
- NULL
-};
-
-DT_MACHINE_START(LPC18XXDT, "NXP LPC18xx/43xx (Device Tree)")
- .dt_compat = lpc18xx_43xx_compat,
-MACHINE_END
--
2.53.0
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 09/13] ARM: lpc18xx: remove entire platform
2026-09-08 15:27 ` [PATCH 09/13] ARM: lpc18xx: remove entire platform Arnd Bergmann
@ 2026-09-08 17:36 ` Linus Walleij
2026-09-09 8:28 ` Vladimir Zapolskiy
1 sibling, 0 replies; 70+ messages in thread
From: Linus Walleij @ 2026-09-08 17:36 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Russell King,
Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski
On Tue, Sep 8, 2026 at 5:30 PM Arnd Bergmann <arnd@kernel.org> wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The NXP LPC18xx and LPC43xx microcontrollers are the more modern
> version of the classic LPC32xx line, but they lack memory management
> units.
>
> These microcontrollers all remain in production as of 2026, but
> there are no known users running Linux on them.
>
> The platform was marked deprecated in the 7.3-LTS release, which
> will remain supported for a few more years.
>
> Remove support for both LPC18xx and LPC43xx.
Acked-by: Linus Walleij <linusw@kernel.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 09/13] ARM: lpc18xx: remove entire platform
2026-09-08 15:27 ` [PATCH 09/13] ARM: lpc18xx: remove entire platform Arnd Bergmann
2026-09-08 17:36 ` Linus Walleij
@ 2026-09-09 8:28 ` Vladimir Zapolskiy
1 sibling, 0 replies; 70+ messages in thread
From: Vladimir Zapolskiy @ 2026-09-09 8:28 UTC (permalink / raw)
To: Arnd Bergmann, Krzysztof Kozlowski, Alexandre Belloni,
Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Stefan Agner, Maxime Coquelin, Alexandre Torgue, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Nicolas Ferre, Claudiu Beznea, Andrew Lunn,
Sebastian Hesselbarth, Gregory Clement, Robert Jarzmik,
Kristoffer Ericson, Ethan Nelson-Moore, Geert Uytterhoeven,
Alexander Sverdlin, Shawn Guo, Karl Mehltretter,
David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski
On 9/8/26 18:27, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The NXP LPC18xx and LPC43xx microcontrollers are the more modern
> version of the classic LPC32xx line, but they lack memory management
> units.
>
> These microcontrollers all remain in production as of 2026, but
> there are no known users running Linux on them.
>
> The platform was marked deprecated in the 7.3-LTS release, which
> will remain supported for a few more years.
>
> Remove support for both LPC18xx and LPC43xx.
>
> Cc: Frank Li <Frank.Li@nxp.com>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Vladimir Zapolskiy <vz@mleia.com>
> Cc: imx@lists.linux.dev
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Since there is no known users of these pretty old NOMMU platforms in
the Linux kernel, it should be safe to drop them from maintenance.
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH 10/13] ARM: stm32: remove stm32f4/f7/h7 MCU support
2026-09-08 15:27 [PATCH 00/13] ARM: deprecated platform removal Arnd Bergmann
` (8 preceding siblings ...)
2026-09-08 15:27 ` [PATCH 09/13] ARM: lpc18xx: remove entire platform Arnd Bergmann
@ 2026-09-08 15:28 ` Arnd Bergmann
2026-09-08 17:36 ` Linus Walleij
2026-09-08 15:28 ` [PATCH 11/13] ARM: versatile: remove mps2 support Arnd Bergmann
` (3 subsequent siblings)
13 siblings, 1 reply; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 15:28 UTC (permalink / raw)
To: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski,
Christophe Parant, Benjamin Gaignard, Dario Binacchi
From: Arnd Bergmann <arnd@arndb.de>
The stm32 platform started out as a Cortex-M based microcontoller
platform in 2007, with a few of the older products gaining Linux kernel
support in 2016. These days, the only relevant chips for Linux are the
stm32mp1 (Cortex-A7) and stm32mp2 (Cortex-A35) product lines, with the
microcontrollers running smaller RTOSs on new products.
The microcontrollers were marked as deprecated in the linux-7.3LTS
release, which will remain supported for a few more years and
is expected to be sufficient for any of the remaining original users.
Remove the MCU support now, leaving only the stm32mp SoCs in the platform.
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Christophe Parant <c.parant@phytec.fr>
Cc: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Cc: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Cc: devicetree@vger.kernel.org
Cc: linux-stm32@st-md-mailman.stormreply.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
Documentation/arch/arm/index.rst | 5 -
Documentation/arch/arm/stm32/overview.rst | 8 +-
.../arch/arm/stm32/stm32f429-overview.rst | 25 -
.../arch/arm/stm32/stm32f746-overview.rst | 32 -
.../arch/arm/stm32/stm32f769-overview.rst | 34 -
.../arch/arm/stm32/stm32h743-overview.rst | 33 -
.../arch/arm/stm32/stm32h750-overview.rst | 34 -
arch/arm/Kconfig.debug | 38 -
arch/arm/boot/dts/st/Makefile | 11 -
arch/arm/boot/dts/st/stm32429i-eval.dts | 349 --------
arch/arm/boot/dts/st/stm32746g-eval.dts | 236 ------
arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi | 482 -----------
arch/arm/boot/dts/st/stm32f429-disco.dts | 243 ------
arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi | 91 --
arch/arm/boot/dts/st/stm32f429.dtsi | 800 ------------------
arch/arm/boot/dts/st/stm32f469-disco.dts | 260 ------
arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi | 92 --
arch/arm/boot/dts/st/stm32f469.dtsi | 18 -
arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi | 436 ----------
arch/arm/boot/dts/st/stm32f746-disco.dts | 234 -----
arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi | 55 --
arch/arm/boot/dts/st/stm32f746.dtsi | 727 ----------------
.../dts/st/stm32f769-disco-mb1166-reva09.dts | 13 -
arch/arm/boot/dts/st/stm32f769-disco.dts | 243 ------
arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi | 55 --
arch/arm/boot/dts/st/stm32f769.dtsi | 37 -
arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi | 301 -------
arch/arm/boot/dts/st/stm32h743.dtsi | 738 ----------------
arch/arm/boot/dts/st/stm32h743i-disco.dts | 145 ----
arch/arm/boot/dts/st/stm32h743i-eval.dts | 185 ----
arch/arm/boot/dts/st/stm32h747i-disco.dts | 149 ----
arch/arm/boot/dts/st/stm32h750.dtsi | 6 -
arch/arm/boot/dts/st/stm32h750i-art-pi.dts | 229 -----
arch/arm/configs/stm32_defconfig | 80 --
arch/arm/mach-stm32/Kconfig | 38 +-
arch/arm/mach-stm32/board-dt.c | 7 -
36 files changed, 7 insertions(+), 6462 deletions(-)
delete mode 100644 Documentation/arch/arm/stm32/stm32f429-overview.rst
delete mode 100644 Documentation/arch/arm/stm32/stm32f746-overview.rst
delete mode 100644 Documentation/arch/arm/stm32/stm32f769-overview.rst
delete mode 100644 Documentation/arch/arm/stm32/stm32h743-overview.rst
delete mode 100644 Documentation/arch/arm/stm32/stm32h750-overview.rst
delete mode 100644 arch/arm/boot/dts/st/stm32429i-eval.dts
delete mode 100644 arch/arm/boot/dts/st/stm32746g-eval.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f429-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f429.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f469-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f469.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f746-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f746.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f769-disco-mb1166-reva09.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f769-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f769.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32h743.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32h743i-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32h743i-eval.dts
delete mode 100644 arch/arm/boot/dts/st/stm32h747i-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32h750.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32h750i-art-pi.dts
delete mode 100644 arch/arm/configs/stm32_defconfig
diff --git a/Documentation/arch/arm/index.rst b/Documentation/arch/arm/index.rst
index 17d6a5bbfc26..70bc418fdb38 100644
--- a/Documentation/arch/arm/index.rst
+++ b/Documentation/arch/arm/index.rst
@@ -47,12 +47,7 @@ SoC-specific documents
pxa/mfp
- stm32/stm32f746-overview
stm32/overview
- stm32/stm32h743-overview
- stm32/stm32h750-overview
- stm32/stm32f769-overview
- stm32/stm32f429-overview
stm32/stm32mp13-overview
stm32/stm32mp151-overview
stm32/stm32mp157-overview
diff --git a/Documentation/arch/arm/stm32/overview.rst b/Documentation/arch/arm/stm32/overview.rst
index 85cfc8410798..b63aa875cb48 100644
--- a/Documentation/arch/arm/stm32/overview.rst
+++ b/Documentation/arch/arm/stm32/overview.rst
@@ -5,15 +5,13 @@ STM32 ARM Linux Overview
Introduction
------------
-The STMicroelectronics STM32 family of Cortex-A microprocessors (MPUs) and
-Cortex-M microcontrollers (MCUs) are supported by the 'STM32' platform of
-ARM Linux.
+The STMicroelectronics STM32 family of Cortex-A microprocessors (MPUs) is
+supported by the 'STM32' platform of ARM Linux, support for the Cortex-M
+based MCUs is has been removed.
Configuration
-------------
-For MCUs, use the provided default configuration:
- make stm32_defconfig
For MPUs, use multi_v7 configuration:
make multi_v7_defconfig
diff --git a/Documentation/arch/arm/stm32/stm32f429-overview.rst b/Documentation/arch/arm/stm32/stm32f429-overview.rst
deleted file mode 100644
index a7ebe8ea6697..000000000000
--- a/Documentation/arch/arm/stm32/stm32f429-overview.rst
+++ /dev/null
@@ -1,25 +0,0 @@
-==================
-STM32F429 Overview
-==================
-
-Introduction
-------------
-
-The STM32F429 is a Cortex-M4 MCU aimed at various applications.
-It features:
-
-- ARM Cortex-M4 up to 180MHz with FPU
-- 2MB internal Flash Memory
-- External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
-- I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers
-- LCD controller & Camera interface
-- Cryptographic processor
-
-Resources
----------
-
-Datasheet and reference manual are publicly available on ST website (STM32F429_).
-
-.. _STM32F429: http://www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013
-
-:Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
diff --git a/Documentation/arch/arm/stm32/stm32f746-overview.rst b/Documentation/arch/arm/stm32/stm32f746-overview.rst
deleted file mode 100644
index 335f0855a858..000000000000
--- a/Documentation/arch/arm/stm32/stm32f746-overview.rst
+++ /dev/null
@@ -1,32 +0,0 @@
-==================
-STM32F746 Overview
-==================
-
-Introduction
-------------
-
-The STM32F746 is a Cortex-M7 MCU aimed at various applications.
-It features:
-
-- Cortex-M7 core running up to @216MHz
-- 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM)
-- FMC controller to connect SDRAM, NOR and NAND memories
-- Dual mode QSPI
-- SD/MMC/SDIO support
-- Ethernet controller
-- USB OTFG FS & HS controllers
-- I2C, SPI, CAN buses support
-- Several 16 & 32 bits general purpose timers
-- Serial Audio interface
-- LCD controller
-- HDMI-CEC
-- SPDIFRX
-
-Resources
----------
-
-Datasheet and reference manual are publicly available on ST website (STM32F746_).
-
-.. _STM32F746: http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32f7-series/stm32f7x6/stm32f746ng.html
-
-:Authors: Alexandre Torgue <alexandre.torgue@st.com>
diff --git a/Documentation/arch/arm/stm32/stm32f769-overview.rst b/Documentation/arch/arm/stm32/stm32f769-overview.rst
deleted file mode 100644
index ef31aadee68f..000000000000
--- a/Documentation/arch/arm/stm32/stm32f769-overview.rst
+++ /dev/null
@@ -1,34 +0,0 @@
-==================
-STM32F769 Overview
-==================
-
-Introduction
-------------
-
-The STM32F769 is a Cortex-M7 MCU aimed at various applications.
-It features:
-
-- Cortex-M7 core running up to @216MHz
-- 2MB internal flash, 512KBytes internal RAM (+4KB of backup SRAM)
-- FMC controller to connect SDRAM, NOR and NAND memories
-- Dual mode QSPI
-- SD/MMC/SDIO support*2
-- Ethernet controller
-- USB OTFG FS & HS controllers
-- I2C*4, SPI*6, CAN*3 buses support
-- Several 16 & 32 bits general purpose timers
-- Serial Audio interface*2
-- LCD controller
-- HDMI-CEC
-- DSI
-- SPDIFRX
-- MDIO salave interface
-
-Resources
----------
-
-Datasheet and reference manual are publicly available on ST website (STM32F769_).
-
-.. _STM32F769: http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x9/stm32f769ni.html
-
-:Authors: Alexandre Torgue <alexandre.torgue@st.com>
diff --git a/Documentation/arch/arm/stm32/stm32h743-overview.rst b/Documentation/arch/arm/stm32/stm32h743-overview.rst
deleted file mode 100644
index 7659df24d362..000000000000
--- a/Documentation/arch/arm/stm32/stm32h743-overview.rst
+++ /dev/null
@@ -1,33 +0,0 @@
-==================
-STM32H743 Overview
-==================
-
-Introduction
-------------
-
-The STM32H743 is a Cortex-M7 MCU aimed at various applications.
-It features:
-
-- Cortex-M7 core running up to @400MHz
-- 2MB internal flash, 1MBytes internal RAM
-- FMC controller to connect SDRAM, NOR and NAND memories
-- Dual mode QSPI
-- SD/MMC/SDIO support
-- Ethernet controller
-- USB OTFG FS & HS controllers
-- I2C, SPI, CAN buses support
-- Several 16 & 32 bits general purpose timers
-- Serial Audio interface
-- LCD controller
-- HDMI-CEC
-- SPDIFRX
-- DFSDM
-
-Resources
----------
-
-Datasheet and reference manual are publicly available on ST website (STM32H743_).
-
-.. _STM32H743: http://www.st.com/en/microcontrollers/stm32h7x3.html?querycriteria=productId=LN2033
-
-:Authors: Alexandre Torgue <alexandre.torgue@st.com>
diff --git a/Documentation/arch/arm/stm32/stm32h750-overview.rst b/Documentation/arch/arm/stm32/stm32h750-overview.rst
deleted file mode 100644
index be032b77d1f1..000000000000
--- a/Documentation/arch/arm/stm32/stm32h750-overview.rst
+++ /dev/null
@@ -1,34 +0,0 @@
-==================
-STM32H750 Overview
-==================
-
-Introduction
-------------
-
-The STM32H750 is a Cortex-M7 MCU aimed at various applications.
-It features:
-
-- Cortex-M7 core running up to @480MHz
-- 128K internal flash, 1MBytes internal RAM
-- FMC controller to connect SDRAM, NOR and NAND memories
-- Dual mode QSPI
-- SD/MMC/SDIO support
-- Ethernet controller
-- USB OTFG FS & HS controllers
-- I2C, SPI, CAN buses support
-- Several 16 & 32 bits general purpose timers
-- Serial Audio interface
-- LCD controller
-- HDMI-CEC
-- SPDIFRX
-- DFSDM
-
-Resources
----------
-
-Datasheet and reference manual are publicly available on ST website (STM32H750_).
-
-.. _STM32H750: https://www.st.com/en/microcontrollers-microprocessors/stm32h750-value-line.html
-
-:Authors: Dillon Min <dillon.minfei@gmail.com>
-
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index e4910cf865da..3d5f2e41eef1 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1128,42 +1128,6 @@ choice
If unsure, say N.
- config STM32F4_DEBUG_UART
- bool "Use STM32F4 UART for low-level debug"
- depends on MACH_STM32F429 || MACH_STM32F469
- select DEBUG_STM32_UART
- help
- Say Y here if you want kernel low-level debugging support
- on STM32F4 based platforms, which default UART is wired on
- USART1, but another UART instance can be selected by modifying
- CONFIG_DEBUG_UART_PHYS.
-
- If unsure, say N.
-
- config STM32F7_DEBUG_UART
- bool "Use STM32F7 UART for low-level debug"
- depends on MACH_STM32F746 || MACH_STM32F769
- select DEBUG_STM32_UART
- help
- Say Y here if you want kernel low-level debugging support
- on STM32F7 based platforms, which default UART is wired on
- USART1, but another UART instance can be selected by modifying
- CONFIG_DEBUG_UART_PHYS.
-
- If unsure, say N.
-
- config STM32H7_DEBUG_UART
- bool "Use STM32H7 UART for low-level debug"
- depends on MACH_STM32H743
- select DEBUG_STM32_UART
- help
- Say Y here if you want kernel low-level debugging support
- on STM32H7 based platforms, which default UART is wired on
- USART1, but another UART instance can be selected by modifying
- CONFIG_DEBUG_UART_PHYS.
-
- If unsure, say N.
-
config STM32MP1_DEBUG_UART
bool "Use STM32MP1 UART for low-level debug"
depends on MACH_STM32MP157
@@ -1540,8 +1504,6 @@ config DEBUG_UART_PHYS
default 0x3e000000 if DEBUG_BCM_KONA_UART
default 0x3f201000 if DEBUG_BCM2836
default 0x40010000 if STM32MP1_DEBUG_UART
- default 0x40011000 if STM32F4_DEBUG_UART || STM32F7_DEBUG_UART || \
- STM32H7_DEBUG_UART
default 0x40028000 if DEBUG_AT91_SAMV7_USART1
default 0x40090000 if DEBUG_LPC32XX
default 0x40100000 if DEBUG_PXA_UART1
diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile
index 10c5d75f6169..733ae4cc418b 100644
--- a/arch/arm/boot/dts/st/Makefile
+++ b/arch/arm/boot/dts/st/Makefile
@@ -102,17 +102,6 @@ stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh-dtbs := \
stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo \
dtb-$(CONFIG_ARCH_STM32) += \
- stm32f429-disco.dtb \
- stm32f469-disco.dtb \
- stm32f746-disco.dtb \
- stm32f769-disco.dtb \
- stm32f769-disco-mb1166-reva09.dtb \
- stm32429i-eval.dtb \
- stm32746g-eval.dtb \
- stm32h743i-eval.dtb \
- stm32h743i-disco.dtb \
- stm32h747i-disco.dtb \
- stm32h750i-art-pi.dtb \
stm32mp133c-prihmb.dtb \
stm32mp135f-dhcor-dhsbc.dtb \
stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtb \
diff --git a/arch/arm/boot/dts/st/stm32429i-eval.dts b/arch/arm/boot/dts/st/stm32429i-eval.dts
deleted file mode 100644
index f4b1c4eb64f2..000000000000
--- a/arch/arm/boot/dts/st/stm32429i-eval.dts
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32f429.dtsi"
-#include "stm32f429-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/media/video-interfaces.h>
-
-/ {
- model = "STMicroelectronics STM32429i-EVAL board";
- compatible = "st,stm32429i-eval", "st,stm32f429";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- clocks {
- clk_ext_camera: clk-ext-camera {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
- };
-
- soc {
- dma-ranges = <0xc0000000 0x0 0x10000000>;
- };
-
- leds {
- compatible = "gpio-leds";
- led_green: led-green {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpiog 6 1>;
- linux,default-trigger = "heartbeat";
- };
- led-orange {
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&gpiog 7 1>;
- };
- led-red {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpiog 10 1>;
- };
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpiog 12 1>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "Wake up";
- linux,code = <KEY_WAKEUP>;
- gpios = <&gpioa 0 0>;
- };
- button-1 {
- label = "Tamper";
- linux,code = <KEY_RESTART>;
- gpios = <&gpioc 13 0>;
- };
- };
-
- mmc_vcard: mmc_vcard {
- compatible = "regulator-fixed";
- regulator-name = "mmc_vcard";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_green>;
- };
- };
-
- panel_rgb: panel-rgb {
- compatible = "ampire,am-480272h3tmqw-t01h";
- power-supply = <&vdd_panel>;
- status = "okay";
- port {
- panel_in_rgb: endpoint {
- remote-endpoint = <<dc_out_rgb>;
- };
- };
- };
-
- vdda: regulator-vdda {
- compatible = "regulator-fixed";
- regulator-name = "vdda";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vref: regulator-vref {
- compatible = "regulator-fixed";
- regulator-name = "vref";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- usbotg_hs_phy: usbphy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>;
- clock-names = "main_clk";
- };
-
- vdd_panel: vdd-panel {
- compatible = "regulator-fixed";
- regulator-name = "vdd_panel";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&adc {
- pinctrl-names = "default";
- pinctrl-0 = <&adc3_in8_pin>;
- vdda-supply = <&vdda>;
- vref-supply = <&vref>;
- status = "okay";
- adc3: adc@200 {
- st,adc-channels = <8>;
- status = "okay";
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&crc {
- status = "okay";
-};
-
-&dcmi {
- status = "okay";
-
- port {
- dcmi_0: endpoint {
- remote-endpoint = <&ov2640_0>;
- bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
- bus-width = <8>;
- hsync-active = <0>;
- vsync-active = <0>;
- pclk-sample = <1>;
- };
- };
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- ov2640: camera@30 {
- compatible = "ovti,ov2640";
- reg = <0x30>;
- resetb-gpios = <&stmpegpio 2 GPIO_ACTIVE_HIGH>;
- pwdn-gpios = <&stmpegpio 0 GPIO_ACTIVE_LOW>;
- clocks = <&clk_ext_camera>;
- clock-names = "xvclk";
- status = "okay";
-
- port {
- ov2640_0: endpoint {
- remote-endpoint = <&dcmi_0>;
- };
- };
- };
-
- stmpe1600: stmpe1600@42 {
- compatible = "st,stmpe1600";
- reg = <0x42>;
- interrupts = <8 3>;
- interrupt-parent = <&gpioi>;
- wakeup-source;
-
- stmpegpio: stmpe_gpio {
- compatible = "st,stmpe-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- };
- };
-};
-
-&iwdg {
- status = "okay";
- timeout-sec = <32>;
-};
-
-<dc {
- status = "okay";
- pinctrl-0 = <<dc_pins_a>;
- pinctrl-names = "default";
-
- port {
- ltdc_out_rgb: endpoint {
- remote-endpoint = <&panel_in_rgb>;
- };
- };
-};
-
-&mac {
- status = "okay";
- pinctrl-0 = <ðernet_mii>;
- pinctrl-names = "default";
- phy-mode = "mii";
- phy-handle = <&phy1>;
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdio {
- status = "okay";
- vmmc-supply = <&mmc_vcard>;
- cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default", "opendrain";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_pins_od>;
- bus-width = <4>;
- max-frequency = <12500000>;
-};
-
-&timers1 {
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- timer@0 {
- status = "okay";
- };
-};
-
-&timers3 {
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm3_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- timer@2 {
- status = "okay";
- };
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "host";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32746g-eval.dts b/arch/arm/boot/dts/st/stm32746g-eval.dts
deleted file mode 100644
index 6772c1f9d03e..000000000000
--- a/arch/arm/boot/dts/st/stm32746g-eval.dts
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32f746.dtsi"
-#include "stm32f746-pinctrl.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "STMicroelectronics STM32746g-EVAL board";
- compatible = "st,stm32746g-eval", "st,stm32f746";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xc0000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- leds {
- compatible = "gpio-leds";
- led_green: led-green {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpiof 10 1>;
- linux,default-trigger = "heartbeat";
- };
- led-orange {
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&stmfx_pinctrl 17 1>;
- };
- led-red {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpiob 7 1>;
- };
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&stmfx_pinctrl 19 1>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "Wake up";
- linux,code = <KEY_WAKEUP>;
- gpios = <&gpioc 13 0>;
- };
- };
-
- joystick {
- compatible = "gpio-keys";
- pinctrl-0 = <&joystick_pins>;
- pinctrl-names = "default";
- button-0 {
- label = "JoySel";
- linux,code = <KEY_ENTER>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
- };
- button-1 {
- label = "JoyDown";
- linux,code = <KEY_DOWN>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- };
- button-2 {
- label = "JoyLeft";
- linux,code = <KEY_LEFT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
- };
- button-3 {
- label = "JoyRight";
- linux,code = <KEY_RIGHT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
- };
- button-4 {
- label = "JoyUp";
- linux,code = <KEY_UP>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
- };
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_green>;
- };
- };
-
- usbotg_hs_phy: usb-phy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
- clock-names = "main_clk";
- };
-
- mmc_vcard: mmc_vcard {
- compatible = "regulator-fixed";
- regulator-name = "mmc_vcard";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&crc {
- status = "okay";
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins_b>;
- pinctrl-names = "default";
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-
- stmfx: stmfx@42 {
- compatible = "st,stmfx-0300";
- reg = <0x42>;
- interrupts = <8 IRQ_TYPE_EDGE_RISING>;
- interrupt-parent = <&gpioi>;
-
- stmfx_pinctrl: pinctrl {
- compatible = "st,stmfx-0300-pinctrl";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&stmfx_pinctrl 0 0 24>;
-
- joystick_pins: joystick {
- pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
- drive-push-pull;
- bias-pull-up;
- };
- };
- };
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdio1 {
- status = "okay";
- vmmc-supply = <&mmc_vcard>;
- broken-cd;
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdio_pins_a>;
- pinctrl-1 = <&sdio_pins_od_a>;
- pinctrl-2 = <&sdio_pins_sleep_a>;
- bus-width = <4>;
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "otg";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi
deleted file mode 100644
index 3bb812d6399e..000000000000
--- a/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi
+++ /dev/null
@@ -1,482 +0,0 @@
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-#include <dt-bindings/mfd/stm32f4-rcc.h>
-
-/ {
- soc {
- pinctrl: pinctrl@40020000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x40020000 0x3000>;
- interrupt-parent = <&exti>;
- st,syscfg = <&syscfg 0x8>;
-
- gpioa: gpio@40020000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
- st,bank-name = "GPIOA";
- };
-
- gpiob: gpio@40020400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x400 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
- st,bank-name = "GPIOB";
- };
-
- gpioc: gpio@40020800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x800 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
- st,bank-name = "GPIOC";
- };
-
- gpiod: gpio@40020c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0xc00 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
- st,bank-name = "GPIOD";
- };
-
- gpioe: gpio@40021000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
- st,bank-name = "GPIOE";
- };
-
- gpiof: gpio@40021400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1400 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
- st,bank-name = "GPIOF";
- };
-
- gpiog: gpio@40021800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1800 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
- st,bank-name = "GPIOG";
- };
-
- gpioh: gpio@40021c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1c00 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
- st,bank-name = "GPIOH";
- };
-
- gpioi: gpio@40022000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
- st,bank-name = "GPIOI";
- };
-
- gpioj: gpio@40022400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2400 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
- st,bank-name = "GPIOJ";
- };
-
- gpiok: gpio@40022800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2800 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
- st,bank-name = "GPIOK";
- };
-
- usart1_pins_a: usart1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart3_pins_a: usart3-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
- bias-disable;
- };
- };
-
- usbotg_fs_pins_a: usbotg-fs-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
- <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
- <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_fs_pins_b: usbotg-fs-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
- <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
- <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_hs_pins_a: usbotg-hs-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
- <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
- <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
- <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
- <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
- <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
- <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
- <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
- <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
- <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
- <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
- <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- ethernet_mii: mii-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */
- <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
- <STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */
- <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
- <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
- <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
- <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
- <STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */
- <STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */
- <STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */
- slew-rate = <2>;
- };
- };
-
- adc3_in8_pin: adc-200 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
- };
- };
-
- pwm1_pins: pwm1-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
- <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
- <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
- };
- };
-
- pwm3_pins: pwm3-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
- <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
- };
- };
-
- i2c1_pins: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
- <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <3>;
- };
- };
-
- ltdc_pins_a: ltdc-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
- <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/
- <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/
- <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
- <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
- <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
- <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
- <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
- slew-rate = <2>;
- };
- };
-
- ltdc_pins_b: ltdc-1 {
- pins {
- pinmux = <STM32_PINMUX('C', 6, AF14)>,
- /* LCD_HSYNC */
- <STM32_PINMUX('A', 4, AF14)>,
- /* LCD_VSYNC */
- <STM32_PINMUX('G', 7, AF14)>,
- /* LCD_CLK */
- <STM32_PINMUX('C', 10, AF14)>,
- /* LCD_R2 */
- <STM32_PINMUX('B', 0, AF9)>,
- /* LCD_R3 */
- <STM32_PINMUX('A', 11, AF14)>,
- /* LCD_R4 */
- <STM32_PINMUX('A', 12, AF14)>,
- /* LCD_R5 */
- <STM32_PINMUX('B', 1, AF9)>,
- /* LCD_R6*/
- <STM32_PINMUX('G', 6, AF14)>,
- /* LCD_R7 */
- <STM32_PINMUX('A', 6, AF14)>,
- /* LCD_G2 */
- <STM32_PINMUX('G', 10, AF9)>,
- /* LCD_G3 */
- <STM32_PINMUX('B', 10, AF14)>,
- /* LCD_G4 */
- <STM32_PINMUX('D', 6, AF14)>,
- /* LCD_B2 */
- <STM32_PINMUX('G', 11, AF14)>,
- /* LCD_B3*/
- <STM32_PINMUX('B', 11, AF14)>,
- /* LCD_G5 */
- <STM32_PINMUX('C', 7, AF14)>,
- /* LCD_G6 */
- <STM32_PINMUX('D', 3, AF14)>,
- /* LCD_G7 */
- <STM32_PINMUX('G', 12, AF9)>,
- /* LCD_B4 */
- <STM32_PINMUX('A', 3, AF14)>,
- /* LCD_B5 */
- <STM32_PINMUX('B', 8, AF14)>,
- /* LCD_B6 */
- <STM32_PINMUX('B', 9, AF14)>,
- /* LCD_B7 */
- <STM32_PINMUX('F', 10, AF14)>;
- /* LCD_DE */
- slew-rate = <2>;
- };
- };
-
- spi5_pins: spi5-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 7, AF5)>,
- /* SPI5_CLK */
- <STM32_PINMUX('F', 9, AF5)>;
- /* SPI5_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 8, AF5)>;
- /* SPI5_MISO */
- bias-disable;
- };
- };
-
- i2c3_pins: i2c3-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 9, AF4)>,
- /* I2C3_SDA */
- <STM32_PINMUX('A', 8, AF4)>;
- /* I2C3_SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <3>;
- };
- };
-
- dcmi_pins: dcmi-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
- <STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */
- <STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */
- <STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */
- <STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */
- <STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */
- <STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */
- <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
- <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
- <STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */
- <STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */
- <STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */
- <STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- };
-
- sdio_pins: sdio-pins-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
- <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
- <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_od: sdio-pins-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
- <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
- drive-push-pull;
- slew-rate = <2>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
- drive-open-drain;
- slew-rate = <2>;
- };
- };
-
- can1_pins_a: can1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
- bias-pull-up;
- };
- };
-
- can2_pins_a: can2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
- bias-pull-up;
- };
- };
-
- can2_pins_b: can2-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
- bias-pull-up;
- };
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/st/stm32f429-disco.dts b/arch/arm/boot/dts/st/stm32f429-disco.dts
deleted file mode 100644
index ded369abee4f..000000000000
--- a/arch/arm/boot/dts/st/stm32f429-disco.dts
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32f429.dtsi"
-#include "stm32f429-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "STMicroelectronics STM32F429i-DISCO board";
- compatible = "st,stm32f429i-disco", "st,stm32f429";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@90000000 {
- device_type = "memory";
- reg = <0x90000000 0x800000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- leds {
- compatible = "gpio-leds";
- led-red {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpiog 14 0>;
- };
- led_green: led-green {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpiog 13 0>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "User";
- linux,code = <KEY_HOME>;
- gpios = <&gpioa 0 0>;
- };
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_green>;
- };
- };
-
- /* This turns on vbus for otg for host mode (dwc2) */
- vcc5v_otg: vcc5v-otg-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpioc 4 0>;
- regulator-name = "vcc5_host1";
- regulator-always-on;
- };
-};
-
-&clk_hse {
- clock-frequency = <8000000>;
-};
-
-&crc {
- status = "okay";
-};
-
-&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins>;
- clock-frequency = <100000>;
- status = "okay";
-
- stmpe811@41 {
- compatible = "st,stmpe811";
- reg = <0x41>;
- interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
- interrupt-parent = <&gpioa>;
- /* 3.25 MHz ADC clock speed */
- st,adc-freq = <1>;
- /* 12-bit ADC */
- st,mod-12b = <1>;
- /* internal ADC reference */
- st,ref-sel = <0>;
- /* ADC converstion time: 80 clocks */
- st,sample-time = <4>;
-
- stmpe_touchscreen {
- compatible = "st,stmpe-ts";
- /* 8 sample average control */
- st,ave-ctrl = <3>;
- /* 7 length fractional part in z */
- st,fraction-z = <7>;
- /*
- * 50 mA typical 80 mA max touchscreen drivers
- * current limit value
- */
- st,i-drive = <1>;
- /* 1 ms panel driver settling time */
- st,settling = <3>;
- /* 5 ms touch detect interrupt delay */
- st,touch-det-delay = <5>;
- };
-
- stmpe_adc {
- compatible = "st,stmpe-adc";
- /* forbid to use ADC channels 3-0 (touch) */
- st,norequest-mask = <0x0F>;
- };
- };
-};
-
-<dc {
- status = "okay";
- pinctrl-0 = <<dc_pins_b>;
- pinctrl-names = "default";
-
- port {
- ltdc_out_rgb: endpoint {
- remote-endpoint = <&panel_in_rgb>;
- };
- };
-};
-
-&rtc {
- assigned-clocks = <&rcc 1 CLK_RTC>;
- assigned-clock-parents = <&rcc 1 CLK_LSI>;
- status = "okay";
-};
-
-&spi5 {
- status = "okay";
- pinctrl-0 = <&spi5_pins>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>, <&gpioc 2 GPIO_ACTIVE_LOW>;
-
- l3gd20: l3gd20@0 {
- compatible = "st,l3gd20-gyro";
- spi-max-frequency = <10000000>;
- st,drdy-int-pin = <2>;
- interrupt-parent = <&gpioa>;
- interrupts = <1 IRQ_TYPE_EDGE_RISING>,
- <2 IRQ_TYPE_EDGE_RISING>;
- reg = <0>;
- status = "okay";
- };
-
- display: display@1 {
- /* Connect panel-ilitek-9341 to ltdc */
- compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341";
- reg = <1>;
- spi-3wire;
- spi-max-frequency = <10000000>;
- dc-gpios = <&gpiod 13 0>;
- port {
- panel_in_rgb: endpoint {
- remote-endpoint = <<dc_out_rgb>;
- };
- };
- };
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- compatible = "st,stm32f4x9-fsotg";
- dr_mode = "host";
- pinctrl-0 = <&usbotg_fs_pins_b>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi
deleted file mode 100644
index e10d7a1f3207..000000000000
--- a/arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "stm32f4-pinctrl.dtsi"
-
-&pinctrl {
- compatible = "st,stm32f429-pinctrl";
-
- gpioa: gpio@40020000 {
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@40020400 {
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@40020800 {
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@40020c00 {
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@40021000 {
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@40021400 {
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@40021800 {
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@40021c00 {
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@40022000 {
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@40022400 {
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@40022800 {
- gpio-ranges = <&pinctrl 0 160 8>;
- };
-};
diff --git a/arch/arm/boot/dts/st/stm32f429.dtsi b/arch/arm/boot/dts/st/stm32f429.dtsi
deleted file mode 100644
index ad91b74ddd0d..000000000000
--- a/arch/arm/boot/dts/st/stm32f429.dtsi
+++ /dev/null
@@ -1,800 +0,0 @@
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "../armv7-m.dtsi"
-#include <dt-bindings/clock/stm32fx-clock.h>
-#include <dt-bindings/mfd/stm32f4-rcc.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- clocks {
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clk_lse: clk-lse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- clk_lsi: clk-lsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- clk_i2s_ckin: i2s-ckin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
- };
-
- soc {
- romem: efuse@1fff7800 {
- compatible = "st,stm32f4-otp";
- reg = <0x1fff7800 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
- ts_cal1: calib@22c {
- reg = <0x22c 0x2>;
- };
- ts_cal2: calib@22e {
- reg = <0x22e 0x2>;
- };
- };
-
- timers2: timers@40000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000000 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@1 {
- compatible = "st,stm32-timer-trigger";
- reg = <1>;
- status = "disabled";
- };
- };
-
- timers3: timers@40000400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000400 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@2 {
- compatible = "st,stm32-timer-trigger";
- reg = <2>;
- status = "disabled";
- };
- };
-
- timers4: timers@40000800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000800 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@3 {
- compatible = "st,stm32-timer-trigger";
- reg = <3>;
- status = "disabled";
- };
- };
-
- timers5: timers@40000c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000C00 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@4 {
- compatible = "st,stm32-timer-trigger";
- reg = <4>;
- status = "disabled";
- };
- };
-
- timers6: timers@40001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001000 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
- clock-names = "int";
- status = "disabled";
-
- timer@5 {
- compatible = "st,stm32-timer-trigger";
- reg = <5>;
- status = "disabled";
- };
- };
-
- timers7: timers@40001400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001400 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
- clock-names = "int";
- status = "disabled";
-
- timer@6 {
- compatible = "st,stm32-timer-trigger";
- reg = <6>;
- status = "disabled";
- };
- };
-
- timers12: timers@40001800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001800 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@11 {
- compatible = "st,stm32-timer-trigger";
- reg = <11>;
- status = "disabled";
- };
- };
-
- timers13: timers@40001c00 {
- compatible = "st,stm32-timers";
- reg = <0x40001C00 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- timers14: timers@40002000 {
- compatible = "st,stm32-timers";
- reg = <0x40002000 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- rtc: rtc@40002800 {
- compatible = "st,stm32-rtc";
- reg = <0x40002800 0x400>;
- clocks = <&rcc 1 CLK_RTC>;
- assigned-clocks = <&rcc 1 CLK_RTC>;
- assigned-clock-parents = <&rcc 1 CLK_LSE>;
- interrupt-parent = <&exti>;
- interrupts = <17 1>;
- st,syscfg = <&pwrcfg 0x00 0x100>;
- status = "disabled";
- };
-
- iwdg: watchdog@40003000 {
- compatible = "st,stm32-iwdg";
- reg = <0x40003000 0x400>;
- clocks = <&clk_lsi>;
- clock-names = "lsi";
- status = "disabled";
- };
-
- spi2: spi@40003800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40003800 0x400>;
- interrupts = <36>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
- status = "disabled";
- };
-
- spi3: spi@40003c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40003c00 0x400>;
- interrupts = <51>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
- status = "disabled";
- };
-
- usart2: serial@40004400 {
- compatible = "st,stm32-uart";
- reg = <0x40004400 0x400>;
- interrupts = <38>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
- status = "disabled";
- };
-
- usart3: serial@40004800 {
- compatible = "st,stm32-uart";
- reg = <0x40004800 0x400>;
- interrupts = <39>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
- status = "disabled";
- dmas = <&dma1 1 4 0x400 0x0>,
- <&dma1 3 4 0x400 0x0>;
- dma-names = "rx", "tx";
- };
-
- usart4: serial@40004c00 {
- compatible = "st,stm32-uart";
- reg = <0x40004c00 0x400>;
- interrupts = <52>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
- status = "disabled";
- };
-
- usart5: serial@40005000 {
- compatible = "st,stm32-uart";
- reg = <0x40005000 0x400>;
- interrupts = <53>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
- status = "disabled";
- };
-
- i2c1: i2c@40005400 {
- compatible = "st,stm32f4-i2c";
- reg = <0x40005400 0x400>;
- interrupts = <31>,
- <32>;
- resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@40005c00 {
- compatible = "st,stm32f4-i2c";
- reg = <0x40005c00 0x400>;
- interrupts = <72>,
- <73>;
- resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can1: can@40006400 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40006400 0x200>;
- interrupts = <19>, <20>, <21>, <22>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
- st,can-primary;
- st,gcan = <&gcan>;
- status = "disabled";
- };
-
- gcan: gcan@40006600 {
- compatible = "st,stm32f4-gcan", "syscon";
- reg = <0x40006600 0x200>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
- };
-
- can2: can@40006800 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40006800 0x200>;
- interrupts = <63>, <64>, <65>, <66>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
- st,can-secondary;
- st,gcan = <&gcan>;
- status = "disabled";
- };
-
- dac: dac@40007400 {
- compatible = "st,stm32f4-dac-core";
- reg = <0x40007400 0x400>;
- resets = <&rcc STM32F4_APB1_RESET(DAC)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
- clock-names = "pclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- dac1: dac@1 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <1>;
- status = "disabled";
- };
-
- dac2: dac@2 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <2>;
- status = "disabled";
- };
- };
-
- usart7: serial@40007800 {
- compatible = "st,stm32-uart";
- reg = <0x40007800 0x400>;
- interrupts = <82>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
- status = "disabled";
- };
-
- usart8: serial@40007c00 {
- compatible = "st,stm32-uart";
- reg = <0x40007c00 0x400>;
- interrupts = <83>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
- status = "disabled";
- };
-
- timers1: timers@40010000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40010000 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@0 {
- compatible = "st,stm32-timer-trigger";
- reg = <0>;
- status = "disabled";
- };
- };
-
- timers8: timers@40010400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40010400 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@7 {
- compatible = "st,stm32-timer-trigger";
- reg = <7>;
- status = "disabled";
- };
- };
-
- usart1: serial@40011000 {
- compatible = "st,stm32-uart";
- reg = <0x40011000 0x400>;
- interrupts = <37>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
- status = "disabled";
- dmas = <&dma2 2 4 0x400 0x0>,
- <&dma2 7 4 0x400 0x0>;
- dma-names = "rx", "tx";
- };
-
- usart6: serial@40011400 {
- compatible = "st,stm32-uart";
- reg = <0x40011400 0x400>;
- interrupts = <71>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
- status = "disabled";
- };
-
- adc: adc@40012000 {
- compatible = "st,stm32f4-adc-core";
- reg = <0x40012000 0x400>;
- interrupts = <18>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
- clock-names = "adc";
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc1: adc@0 {
- compatible = "st,stm32f4-adc";
- #io-channel-cells = <1>;
- reg = <0x0>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
- interrupt-parent = <&adc>;
- interrupts = <0>;
- dmas = <&dma2 0 0 0x400 0x0>;
- dma-names = "rx";
- status = "disabled";
- };
-
- adc2: adc@100 {
- compatible = "st,stm32f4-adc";
- #io-channel-cells = <1>;
- reg = <0x100>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
- interrupt-parent = <&adc>;
- interrupts = <1>;
- dmas = <&dma2 3 1 0x400 0x0>;
- dma-names = "rx";
- status = "disabled";
- };
-
- adc3: adc@200 {
- compatible = "st,stm32f4-adc";
- #io-channel-cells = <1>;
- reg = <0x200>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
- interrupt-parent = <&adc>;
- interrupts = <2>;
- dmas = <&dma2 1 2 0x400 0x0>;
- dma-names = "rx";
- status = "disabled";
- };
- };
-
- sdio: mmc@40012c00 {
- compatible = "arm,pl180", "arm,primecell";
- arm,primecell-periphid = <0x00880180>;
- reg = <0x40012c00 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
- clock-names = "apb_pclk";
- interrupts = <49>;
- max-frequency = <48000000>;
- status = "disabled";
- };
-
- spi1: spi@40013000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40013000 0x400>;
- interrupts = <35>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
- status = "disabled";
- };
-
- spi4: spi@40013400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40013400 0x400>;
- interrupts = <84>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
- status = "disabled";
- };
-
- syscfg: syscon@40013800 {
- compatible = "st,stm32-syscfg", "syscon";
- reg = <0x40013800 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SYSCFG)>;
- };
-
- exti: interrupt-controller@40013c00 {
- compatible = "st,stm32-exti";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x40013C00 0x400>;
- interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
- };
-
- timers9: timers@40014000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40014000 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@8 {
- compatible = "st,stm32-timer-trigger";
- reg = <8>;
- status = "disabled";
- };
- };
-
- timers10: timers@40014400 {
- compatible = "st,stm32-timers";
- reg = <0x40014400 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- timers11: timers@40014800 {
- compatible = "st,stm32-timers";
- reg = <0x40014800 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- spi5: spi@40015000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40015000 0x400>;
- interrupts = <85>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
- dmas = <&dma2 3 2 0x400 0x0>,
- <&dma2 4 2 0x400 0x0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi6: spi@40015400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40015400 0x400>;
- interrupts = <86>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
- status = "disabled";
- };
-
- pwrcfg: power-config@40007000 {
- compatible = "st,stm32-power-config", "syscon";
- reg = <0x40007000 0x400>;
- };
-
- ltdc: display-controller@40016800 {
- compatible = "st,stm32-ltdc";
- reg = <0x40016800 0x200>;
- interrupts = <88>, <89>;
- resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
- clocks = <&rcc 1 CLK_LCD>;
- clock-names = "lcd";
- status = "disabled";
- };
-
- crc: crc@40023000 {
- compatible = "st,stm32f4-crc";
- reg = <0x40023000 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
- status = "disabled";
- };
-
- rcc: rcc@40023800 {
- #reset-cells = <1>;
- #clock-cells = <2>;
- compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
- reg = <0x40023800 0x400>;
- clocks = <&clk_hse>, <&clk_i2s_ckin>;
- st,syscfg = <&pwrcfg>;
- assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
- assigned-clock-rates = <1000000>;
- };
-
- dma1: dma-controller@40026000 {
- compatible = "st,stm32-dma";
- reg = <0x40026000 0x400>;
- interrupts = <11>,
- <12>,
- <13>,
- <14>,
- <15>,
- <16>,
- <17>,
- <47>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
- #dma-cells = <4>;
- };
-
- dma2: dma-controller@40026400 {
- compatible = "st,stm32-dma";
- reg = <0x40026400 0x400>;
- interrupts = <56>,
- <57>,
- <58>,
- <59>,
- <60>,
- <68>,
- <69>,
- <70>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
- #dma-cells = <4>;
- st,mem2mem;
- };
-
- mac: ethernet@40028000 {
- compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
- reg = <0x40028000 0x8000>;
- reg-names = "stmmaceth";
- interrupts = <61>;
- interrupt-names = "macirq";
- clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
- <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
- <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
- st,syscon = <&syscfg 0x4>;
- snps,pbl = <8>;
- snps,mixed-burst;
- status = "disabled";
- };
-
- dma2d: dma2d@4002b000 {
- compatible = "st,stm32-dma2d";
- reg = <0x4002b000 0xc00>;
- interrupts = <90>;
- resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
- clock-names = "dma2d";
- status = "disabled";
- };
-
- usbotg_hs: usb@40040000 {
- compatible = "snps,dwc2";
- reg = <0x40040000 0x40000>;
- interrupts = <77>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
- clock-names = "otg";
- status = "disabled";
- };
-
- usbotg_fs: usb@50000000 {
- compatible = "st,stm32f4x9-fsotg";
- reg = <0x50000000 0x40000>;
- interrupts = <67>;
- clocks = <&rcc 0 39>;
- clock-names = "otg";
- status = "disabled";
- };
-
- dcmi: dcmi@50050000 {
- compatible = "st,stm32-dcmi";
- reg = <0x50050000 0x400>;
- interrupts = <78>;
- resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
- clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
- clock-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&dcmi_pins>;
- dmas = <&dma2 1 1 0x414 0x3>;
- dma-names = "tx";
- status = "disabled";
- };
-
- rng: rng@50060800 {
- compatible = "st,stm32-rng";
- reg = <0x50060800 0x400>;
- clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
-
- };
- };
-};
-
-&systick {
- clocks = <&rcc 1 SYSTICK>;
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32f469-disco.dts b/arch/arm/boot/dts/st/stm32f469-disco.dts
deleted file mode 100644
index 943afba06b5f..000000000000
--- a/arch/arm/boot/dts/st/stm32f469-disco.dts
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32f469.dtsi"
-#include "stm32f469-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "STMicroelectronics STM32F469i-DISCO board";
- compatible = "st,stm32f469i-disco", "st,stm32f469";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x1000000>;
- };
-
- aliases {
- serial0 = &usart3;
- };
-
- vcc_3v3: vcc-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- soc {
- dma-ranges = <0xc0000000 0x0 0x10000000>;
- };
-
- leds {
- compatible = "gpio-leds";
- led_green: led-green {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
- led-orange {
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
- };
- led-red {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
- };
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpiok 3 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "User";
- linux,code = <KEY_WAKEUP>;
- gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
- };
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_green>;
- };
- };
-
- /* This turns on vbus for otg for host mode (dwc2) */
- vcc5v_otg: vcc5v-otg-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpiob 2 GPIO_ACTIVE_HIGH>;
- regulator-name = "vcc5_host1";
- regulator-always-on;
- };
-};
-
-&rcc {
- compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc";
-};
-
-&clk_hse {
- clock-frequency = <8000000>;
-};
-
-&dma2d {
- status = "okay";
-};
-
-&dsi {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi_in: endpoint {
- remote-endpoint = <<dc_out_dsi>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi_out: endpoint {
- remote-endpoint = <&dsi_panel_in>;
- };
- };
- };
-
- panel@0 {
- compatible = "orisetech,otm8009a";
- reg = <0>; /* dsi virtual channel (0..3) */
- reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
- power-supply = <&vcc_3v3>;
- status = "okay";
-
- port {
- dsi_panel_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
- };
-};
-
-<dc {
- status = "okay";
-
- port {
- ltdc_out_dsi: endpoint {
- remote-endpoint = <&dsi_in>;
- };
- };
-};
-
-&rtc {
- status = "okay";
-};
-
-&timers1 {
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- timer@0 {
- status = "okay";
- };
-};
-
-&timers3 {
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm3_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- timer@2 {
- status = "okay";
- };
-};
-
-&sdio {
- status = "okay";
- vmmc-supply = <&vcc_3v3>;
- cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
- broken-cd;
- pinctrl-names = "default", "opendrain";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_pins_od>;
- bus-width = <4>;
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart3 {
- pinctrl-0 = <&usart3_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_fs {
- dr_mode = "host";
- pinctrl-0 = <&usbotg_fs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi
deleted file mode 100644
index 6bf60263dff8..000000000000
--- a/arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "stm32f4-pinctrl.dtsi"
-
-&pinctrl {
- compatible = "st,stm32f469-pinctrl";
-
- gpioa: gpio@40020000 {
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@40020400 {
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@40020800 {
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@40020c00 {
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@40021000 {
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@40021400 {
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@40021800 {
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@40021c00 {
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@40022000 {
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@40022400 {
- gpio-ranges = <&pinctrl 0 144 6>,
- <&pinctrl 12 156 4>;
- };
-
- gpiok: gpio@40022800 {
- gpio-ranges = <&pinctrl 3 163 5>;
- };
-};
diff --git a/arch/arm/boot/dts/st/stm32f469.dtsi b/arch/arm/boot/dts/st/stm32f469.dtsi
deleted file mode 100644
index be002e8a78ac..000000000000
--- a/arch/arm/boot/dts/st/stm32f469.dtsi
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-/* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */
-
-#include "stm32f429.dtsi"
-
-/ {
- soc {
- dsi: dsi@40016c00 {
- compatible = "st,stm32-dsi";
- reg = <0x40016c00 0x800>;
- resets = <&rcc STM32F4_APB2_RESET(DSI)>;
- reset-names = "apb";
- clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
- clock-names = "pclk", "ref";
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi
deleted file mode 100644
index 97fc3fb5a9ca..000000000000
--- a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi
+++ /dev/null
@@ -1,436 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-#include <dt-bindings/mfd/stm32f7-rcc.h>
-
-/ {
- soc {
- pinctrl: pinctrl@40020000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x40020000 0x3000>;
- interrupt-parent = <&exti>;
- st,syscfg = <&syscfg 0x8>;
-
- gpioa: gpio@40020000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
- st,bank-name = "GPIOA";
- };
-
- gpiob: gpio@40020400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x400 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
- st,bank-name = "GPIOB";
- };
-
- gpioc: gpio@40020800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x800 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
- st,bank-name = "GPIOC";
- };
-
- gpiod: gpio@40020c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0xc00 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
- st,bank-name = "GPIOD";
- };
-
- gpioe: gpio@40021000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
- st,bank-name = "GPIOE";
- };
-
- gpiof: gpio@40021400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1400 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
- st,bank-name = "GPIOF";
- };
-
- gpiog: gpio@40021800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1800 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
- st,bank-name = "GPIOG";
- };
-
- gpioh: gpio@40021c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1c00 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
- st,bank-name = "GPIOH";
- };
-
- gpioi: gpio@40022000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
- st,bank-name = "GPIOI";
- };
-
- gpioj: gpio@40022400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2400 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
- st,bank-name = "GPIOJ";
- };
-
- gpiok: gpio@40022800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2800 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
- st,bank-name = "GPIOK";
- };
-
- cec_pins_a: cec-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
- slew-rate = <0>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- usart1_pins_a: usart1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart1_pins_b: usart1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- i2c1_pins_b: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
- <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c3_pins_a: i2c3-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 8, AF4)>, /* I2C3_SDA */
- <STM32_PINMUX('H', 7, AF4)>; /* I2C3_SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- usbotg_hs_pins_a: usbotg-hs-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
- <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
- <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
- <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
- <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
- <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
- <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
- <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
- <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
- <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
- <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
- <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_hs_pins_b: usbotg-hs-1 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
- <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
- <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
- <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
- <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
- <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
- <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
- <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
- <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
- <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
- <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
- <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_fs_pins_a: usbotg-fs-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
- <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
- <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_a: sdio-pins-a-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
- <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_od_a: sdio-pins-od-a-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
- <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
- drive-push-pull;
- slew-rate = <2>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
- drive-open-drain;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_sleep_a: sdio-pins-sleep-a-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1 D0 */
- <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1 D1 */
- <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1 D2 */
- <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1 D3 */
- <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1 CLK */
- <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1 CMD */
- };
- };
-
- sdio_pins_b: sdio-pins-b-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
- <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
- <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
- <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
- <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
- <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_od_b: sdio-pins-od-b-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
- <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
- <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
- <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
- <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
- drive-push-pull;
- slew-rate = <2>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
- drive-open-drain;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_sleep_b: sdio-pins-sleep-b-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 9, ANALOG)>, /* SDMMC2 D0 */
- <STM32_PINMUX('G', 10, ANALOG)>, /* SDMMC2 D1 */
- <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2 D2 */
- <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2 D3 */
- <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC2 CLK */
- <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC2 CMD */
- };
- };
-
- can1_pins_a: can1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
- bias-pull-up;
- };
- };
-
- can1_pins_b: can1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
- bias-pull-up;
- };
- };
-
- can1_pins_c: can1-2 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 1, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
- bias-pull-up;
-
- };
- };
-
- can1_pins_d: can1-3 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
- bias-pull-up;
-
- };
- };
-
- can2_pins_a: can2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
- bias-pull-up;
- };
- };
-
- can2_pins_b: can2-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
- bias-pull-up;
- };
- };
-
- can3_pins_a: can3-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 15, AF11)>; /* CAN3_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 8, AF11)>; /* CAN3_RX */
- bias-pull-up;
- };
- };
-
- can3_pins_b: can3-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 4, AF11)>; /* CAN3_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 3, AF11)>; /* CAN3_RX */
- bias-pull-up;
- };
- };
-
- ltdc_pins_a: ltdc-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 4, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('G',12, AF9)>, /* LCD_B4 */
- <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('I',10, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I',14, AF14)>, /* LCD_CLK */
- <STM32_PINMUX('I',15, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
- <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('J',10, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('J',11, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('J',13, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('J',14, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('J',15, AF14)>, /* LCD_B3 */
- <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
- <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
- <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
- <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
- slew-rate = <2>;
- };
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts
deleted file mode 100644
index 61ca41ea523e..000000000000
--- a/arch/arm/boot/dts/st/stm32f746-disco.dts
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32f746.dtsi"
-#include "stm32f746-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "STMicroelectronics STM32F746-DISCO board";
- compatible = "st,stm32f746-disco", "st,stm32f746";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xC0000000 0x800000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- linux,cma {
- compatible = "shared-dma-pool";
- no-map;
- size = <0x80000>;
- linux,dma-default;
- };
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- leds {
- compatible = "gpio-leds";
- led_usr: led-usr {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpioi 1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "User";
- linux,code = <KEY_HOME>;
- gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>;
- };
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_usr>;
- };
- };
-
- usbotg_hs_phy: usb-phy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
- clock-names = "main_clk";
- };
-
- /* This turns on vbus for otg fs for host mode (dwc2) */
- vcc5v_otg_fs: vcc5v-otg-fs-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpiod 5 0>;
- regulator-name = "vcc5_host1";
- regulator-always-on;
- };
-
- vcc_3v3: vcc-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- backlight: backlight {
- compatible = "gpio-backlight";
- gpios = <&gpiok 3 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
-
- panel_rgb: panel-rgb {
- compatible = "rocktech,rk043fn48h";
- power-supply = <&vcc_3v3>;
- backlight = <&backlight>;
- enable-gpios = <&gpioi 12 GPIO_ACTIVE_HIGH>;
- status = "okay";
- port {
- panel_in_rgb: endpoint {
- remote-endpoint = <<dc_out_rgb>;
- };
- };
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins_b>;
- pinctrl-names = "default";
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
-&i2c3 {
- pinctrl-0 = <&i2c3_pins_a>;
- pinctrl-names = "default";
- clock-frequency = <400000>;
- status = "okay";
-
- touchscreen@38 {
- compatible = "edt,edt-ft5306";
- reg = <0x38>;
- interrupt-parent = <&gpioi>;
- interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
- touchscreen-size-x = <480>;
- touchscreen-size-y = <272>;
- };
-};
-
-<dc {
- pinctrl-0 = <<dc_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-
- port {
- ltdc_out_rgb: endpoint {
- remote-endpoint = <&panel_in_rgb>;
- };
- };
-};
-
-&sdio1 {
- status = "okay";
- vmmc-supply = <&vcc_3v3>;
- cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdio_pins_a>;
- pinctrl-1 = <&sdio_pins_od_a>;
- pinctrl-2 = <&sdio_pins_sleep_a>;
- bus-width = <4>;
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_b>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_fs {
- dr_mode = "host";
- pinctrl-0 = <&usbotg_fs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "host";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- pinctrl-0 = <&usbotg_hs_pins_b>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi
deleted file mode 100644
index 139f72b790c0..000000000000
--- a/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include "stm32f7-pinctrl.dtsi"
-
-&pinctrl {
- compatible = "st,stm32f746-pinctrl";
-
- gpioa: gpio@40020000 {
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@40020400 {
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@40020800 {
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@40020c00 {
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@40021000 {
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@40021400 {
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@40021800 {
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@40021c00 {
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@40022000 {
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@40022400 {
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@40022800 {
- gpio-ranges = <&pinctrl 0 160 8>;
- };
-};
diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi
deleted file mode 100644
index 208f8c6dfc9d..000000000000
--- a/arch/arm/boot/dts/st/stm32f746.dtsi
+++ /dev/null
@@ -1,727 +0,0 @@
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "../armv7-m.dtsi"
-#include <dt-bindings/clock/stm32fx-clock.h>
-#include <dt-bindings/mfd/stm32f7-rcc.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- clocks {
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clk-lse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- clk-lsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- clk_i2s_ckin: clk-i2s-ckin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <48000000>;
- };
- };
-
- soc {
- timers2: timers@40000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000000 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@1 {
- compatible = "st,stm32-timer-trigger";
- reg = <1>;
- status = "disabled";
- };
- };
-
- timers3: timers@40000400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000400 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@2 {
- compatible = "st,stm32-timer-trigger";
- reg = <2>;
- status = "disabled";
- };
- };
-
- timers4: timers@40000800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000800 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@3 {
- compatible = "st,stm32-timer-trigger";
- reg = <3>;
- status = "disabled";
- };
- };
-
- timers5: timers@40000c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000C00 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@4 {
- compatible = "st,stm32-timer-trigger";
- reg = <4>;
- status = "disabled";
- };
- };
-
- timers6: timers@40001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001000 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
- clock-names = "int";
- status = "disabled";
-
- timer@5 {
- compatible = "st,stm32-timer-trigger";
- reg = <5>;
- status = "disabled";
- };
- };
-
- timers7: timers@40001400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001400 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
- clock-names = "int";
- status = "disabled";
-
- timer@6 {
- compatible = "st,stm32-timer-trigger";
- reg = <6>;
- status = "disabled";
- };
- };
-
- timers12: timers@40001800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001800 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@11 {
- compatible = "st,stm32-timer-trigger";
- reg = <11>;
- status = "disabled";
- };
- };
-
- timers13: timers@40001c00 {
- compatible = "st,stm32-timers";
- reg = <0x40001C00 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- timers14: timers@40002000 {
- compatible = "st,stm32-timers";
- reg = <0x40002000 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- lptimer1: timer@40002400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x40002400 0x400>;
- interrupts-extended = <&exti 23 IRQ_TYPE_EDGE_RISING>;
- clocks = <&rcc 1 CLK_LPTIMER>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@0 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <0>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
-
- timer {
- compatible = "st,stm32-lptimer-timer";
- status = "disabled";
- };
- };
-
- rtc: rtc@40002800 {
- compatible = "st,stm32-rtc";
- reg = <0x40002800 0x400>;
- clocks = <&rcc 1 CLK_RTC>;
- assigned-clocks = <&rcc 1 CLK_RTC>;
- assigned-clock-parents = <&rcc 1 CLK_LSE>;
- interrupt-parent = <&exti>;
- interrupts = <17 1>;
- st,syscfg = <&pwrcfg 0x00 0x100>;
- status = "disabled";
- };
-
- spi2: spi@40003800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f7-spi";
- reg = <0x40003800 0x400>;
- interrupts = <36>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>;
- status = "disabled";
- };
-
- spi3: spi@40003c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f7-spi";
- reg = <0x40003c00 0x400>;
- interrupts = <51>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>;
- status = "disabled";
- };
-
- usart2: serial@40004400 {
- compatible = "st,stm32f7-uart";
- reg = <0x40004400 0x400>;
- interrupts = <38>;
- clocks = <&rcc 1 CLK_USART2>;
- status = "disabled";
- };
-
- usart3: serial@40004800 {
- compatible = "st,stm32f7-uart";
- reg = <0x40004800 0x400>;
- interrupts = <39>;
- clocks = <&rcc 1 CLK_USART3>;
- status = "disabled";
- };
-
- usart4: serial@40004c00 {
- compatible = "st,stm32f7-uart";
- reg = <0x40004c00 0x400>;
- interrupts = <52>;
- clocks = <&rcc 1 CLK_UART4>;
- status = "disabled";
- };
-
- usart5: serial@40005000 {
- compatible = "st,stm32f7-uart";
- reg = <0x40005000 0x400>;
- interrupts = <53>;
- clocks = <&rcc 1 CLK_UART5>;
- status = "disabled";
- };
-
- i2c1: i2c@40005400 {
- compatible = "st,stm32f7-i2c";
- reg = <0x40005400 0x400>;
- interrupts = <31>,
- <32>;
- resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
- clocks = <&rcc 1 CLK_I2C1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@40005800 {
- compatible = "st,stm32f7-i2c";
- reg = <0x40005800 0x400>;
- interrupts = <33>,
- <34>;
- resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
- clocks = <&rcc 1 CLK_I2C2>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@40005c00 {
- compatible = "st,stm32f7-i2c";
- reg = <0x40005c00 0x400>;
- interrupts = <72>,
- <73>;
- resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
- clocks = <&rcc 1 CLK_I2C3>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@40006000 {
- compatible = "st,stm32f7-i2c";
- reg = <0x40006000 0x400>;
- interrupts = <95>,
- <96>;
- resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
- clocks = <&rcc 1 CLK_I2C4>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can1: can@40006400 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40006400 0x200>;
- interrupts = <19>, <20>, <21>, <22>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
- st,can-primary;
- st,gcan = <&gcan1>;
- status = "disabled";
- };
-
- gcan1: gcan@40006600 {
- compatible = "st,stm32f4-gcan", "syscon";
- reg = <0x40006600 0x200>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
- };
-
- can2: can@40006800 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40006800 0x200>;
- interrupts = <63>, <64>, <65>, <66>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
- st,can-secondary;
- st,gcan = <&gcan1>;
- status = "disabled";
- };
-
- cec: cec@40006c00 {
- compatible = "st,stm32-cec";
- reg = <0x40006C00 0x400>;
- interrupts = <94>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
- clock-names = "cec", "hdmi-cec";
- status = "disabled";
- };
-
- usart7: serial@40007800 {
- compatible = "st,stm32f7-uart";
- reg = <0x40007800 0x400>;
- interrupts = <82>;
- clocks = <&rcc 1 CLK_UART7>;
- status = "disabled";
- };
-
- usart8: serial@40007c00 {
- compatible = "st,stm32f7-uart";
- reg = <0x40007c00 0x400>;
- interrupts = <83>;
- clocks = <&rcc 1 CLK_UART8>;
- status = "disabled";
- };
-
- timers1: timers@40010000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40010000 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@0 {
- compatible = "st,stm32-timer-trigger";
- reg = <0>;
- status = "disabled";
- };
- };
-
- timers8: timers@40010400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40010400 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@7 {
- compatible = "st,stm32-timer-trigger";
- reg = <7>;
- status = "disabled";
- };
- };
-
- usart1: serial@40011000 {
- compatible = "st,stm32f7-uart";
- reg = <0x40011000 0x400>;
- interrupts = <37>;
- clocks = <&rcc 1 CLK_USART1>;
- status = "disabled";
- };
-
- usart6: serial@40011400 {
- compatible = "st,stm32f7-uart";
- reg = <0x40011400 0x400>;
- interrupts = <71>;
- clocks = <&rcc 1 CLK_USART6>;
- status = "disabled";
- };
-
- sdio2: mmc@40011c00 {
- compatible = "arm,pl180", "arm,primecell";
- arm,primecell-periphid = <0x00880180>;
- reg = <0x40011c00 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
- clock-names = "apb_pclk";
- interrupts = <103>;
- max-frequency = <48000000>;
- status = "disabled";
- };
-
- sdio1: mmc@40012c00 {
- compatible = "arm,pl180", "arm,primecell";
- arm,primecell-periphid = <0x00880180>;
- reg = <0x40012c00 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
- clock-names = "apb_pclk";
- interrupts = <49>;
- max-frequency = <48000000>;
- status = "disabled";
- };
-
- spi1: spi@40013000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f7-spi";
- reg = <0x40013000 0x400>;
- interrupts = <35>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>;
- status = "disabled";
- };
-
- spi4: spi@40013400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f7-spi";
- reg = <0x40013400 0x400>;
- interrupts = <84>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>;
- status = "disabled";
- };
-
- syscfg: syscon@40013800 {
- compatible = "st,stm32-syscfg", "syscon";
- reg = <0x40013800 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SYSCFG)>;
- };
-
- exti: interrupt-controller@40013c00 {
- compatible = "st,stm32-exti";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x40013C00 0x400>;
- interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
- };
-
- timers9: timers@40014000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40014000 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@8 {
- compatible = "st,stm32-timer-trigger";
- reg = <8>;
- status = "disabled";
- };
- };
-
- timers10: timers@40014400 {
- compatible = "st,stm32-timers";
- reg = <0x40014400 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- timers11: timers@40014800 {
- compatible = "st,stm32-timers";
- reg = <0x40014800 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- spi5: spi@40015000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f7-spi";
- reg = <0x40015000 0x400>;
- interrupts = <85>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>;
- status = "disabled";
- };
-
- spi6: spi@40015400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f7-spi";
- reg = <0x40015400 0x400>;
- interrupts = <86>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>;
- status = "disabled";
- };
-
- ltdc: display-controller@40016800 {
- compatible = "st,stm32-ltdc";
- reg = <0x40016800 0x200>;
- interrupts = <88>, <89>;
- resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
- clocks = <&rcc 1 CLK_LCD>;
- clock-names = "lcd";
- status = "disabled";
- };
-
- pwrcfg: power-config@40007000 {
- compatible = "st,stm32-power-config", "syscon";
- reg = <0x40007000 0x400>;
- };
-
- crc: crc@40023000 {
- compatible = "st,stm32f7-crc";
- reg = <0x40023000 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
- status = "disabled";
- };
-
- rcc: rcc@40023800 {
- #reset-cells = <1>;
- #clock-cells = <2>;
- compatible = "st,stm32f746-rcc", "st,stm32-rcc";
- reg = <0x40023800 0x400>;
- clocks = <&clk_hse>, <&clk_i2s_ckin>;
- st,syscfg = <&pwrcfg>;
- assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
- assigned-clock-rates = <1000000>;
- };
-
- dma1: dma-controller@40026000 {
- compatible = "st,stm32-dma";
- reg = <0x40026000 0x400>;
- interrupts = <11>,
- <12>,
- <13>,
- <14>,
- <15>,
- <16>,
- <17>,
- <47>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
- #dma-cells = <4>;
- status = "disabled";
- };
-
- dma2: dma-controller@40026400 {
- compatible = "st,stm32-dma";
- reg = <0x40026400 0x400>;
- interrupts = <56>,
- <57>,
- <58>,
- <59>,
- <60>,
- <68>,
- <69>,
- <70>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
- #dma-cells = <4>;
- st,mem2mem;
- status = "disabled";
- };
-
- usbotg_hs: usb@40040000 {
- compatible = "st,stm32f7-hsotg";
- reg = <0x40040000 0x40000>;
- interrupts = <77>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
- clock-names = "otg";
- g-rx-fifo-size = <256>;
- g-np-tx-fifo-size = <32>;
- g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- usbotg_fs: usb@50000000 {
- compatible = "st,stm32f4x9-fsotg";
- reg = <0x50000000 0x40000>;
- interrupts = <67>;
- clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
- clock-names = "otg";
- status = "disabled";
- };
- };
-};
-
-&systick {
- clocks = <&rcc 1 0>;
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32f769-disco-mb1166-reva09.dts b/arch/arm/boot/dts/st/stm32f769-disco-mb1166-reva09.dts
deleted file mode 100644
index ff7ff32371d0..000000000000
--- a/arch/arm/boot/dts/st/stm32f769-disco-mb1166-reva09.dts
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 Dario Binacchi <dario.binacchi@amarulasolutions.com>
- */
-
-#include "stm32f769-disco.dts"
-
-&panel0 {
- compatible = "frida,frd400b25025", "novatek,nt35510";
- vddi-supply = <&vcc_3v3>;
- vdd-supply = <&vcc_3v3>;
- /delete-property/power-supply;
-};
diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts
deleted file mode 100644
index e5854fa1071b..000000000000
--- a/arch/arm/boot/dts/st/stm32f769-disco.dts
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32f769.dtsi"
-#include "stm32f769-pinctrl.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "STMicroelectronics STM32F769-DISCO board";
- compatible = "st,stm32f769-disco", "st,stm32f769";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xC0000000 0x1000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- linux,dma {
- compatible = "shared-dma-pool";
- linux,dma-default;
- no-map;
- size = <0x100000>;
- };
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- leds {
- compatible = "gpio-leds";
- led_usr2: led-usr2 {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- led-usr1 {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>;
- };
- led-usr3 {
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpioa 12 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "User";
- linux,code = <KEY_HOME>;
- gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
- };
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_usr2>;
- };
- };
-
- usbotg_hs_phy: usb-phy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
- clock-names = "main_clk";
- };
-
- vcc_3v3: vcc-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&rcc {
- compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc";
-};
-
-&cec {
- pinctrl-0 = <&cec_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&dsi {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi_in: endpoint {
- remote-endpoint = <<dc_out_dsi>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi_out: endpoint {
- remote-endpoint = <&dsi_panel_in>;
- };
- };
- };
-
- panel0: panel@0 {
- compatible = "orisetech,otm8009a";
- reg = <0>; /* dsi virtual channel (0..3) */
- reset-gpios = <&gpioj 15 GPIO_ACTIVE_LOW>;
- power-supply = <&vcc_3v3>;
- status = "okay";
-
- port {
- dsi_panel_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
- };
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins_b>;
- pinctrl-names = "default";
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
-<dc {
- status = "okay";
-
- port {
- ltdc_out_dsi: endpoint {
- remote-endpoint = <&dsi_in>;
- };
- };
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdio2 {
- status = "okay";
- vmmc-supply = <&vcc_3v3>;
- cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
- broken-cd;
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdio_pins_b>;
- pinctrl-1 = <&sdio_pins_od_b>;
- pinctrl-2 = <&sdio_pins_sleep_b>;
- bus-width = <4>;
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "otg";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi
deleted file mode 100644
index 02c2a8b08468..000000000000
--- a/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include "stm32f7-pinctrl.dtsi"
-
-&pinctrl {
- compatible = "st,stm32f769-pinctrl";
-
- gpioa: gpio@40020000 {
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@40020400 {
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@40020800 {
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@40020c00 {
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@40021000 {
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@40021400 {
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@40021800 {
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@40021c00 {
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@40022000 {
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@40022400 {
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@40022800 {
- gpio-ranges = <&pinctrl 0 160 8>;
- };
-};
diff --git a/arch/arm/boot/dts/st/stm32f769.dtsi b/arch/arm/boot/dts/st/stm32f769.dtsi
deleted file mode 100644
index e8cbb99e81a6..000000000000
--- a/arch/arm/boot/dts/st/stm32f769.dtsi
+++ /dev/null
@@ -1,37 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 Dario Binacchi <dario.binacchi@amarulasolutions.com>
- */
-
-#include "stm32f746.dtsi"
-
-/ {
- soc {
- can3: can@40003400 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40003400 0x200>;
- interrupts = <104>, <105>, <106>, <107>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
- st,gcan = <&gcan3>;
- status = "disabled";
- };
-
- gcan3: gcan@40003600 {
- compatible = "st,stm32f4-gcan", "syscon";
- reg = <0x40003600 0x200>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
- };
-
- dsi: dsi@40016c00 {
- compatible = "st,stm32-dsi";
- reg = <0x40016c00 0x800>;
- clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>;
- clock-names = "pclk", "ref";
- resets = <&rcc STM32F7_APB2_RESET(DSI)>;
- reset-names = "apb";
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi
deleted file mode 100644
index 8a6db484383d..000000000000
--- a/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-
-&pinctrl {
-
- i2c1_pins_a: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
- <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- ethernet_rmii: rmii-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 11, AF11)>,
- <STM32_PINMUX('G', 13, AF11)>,
- <STM32_PINMUX('G', 12, AF11)>,
- <STM32_PINMUX('C', 4, AF11)>,
- <STM32_PINMUX('C', 5, AF11)>,
- <STM32_PINMUX('A', 7, AF11)>,
- <STM32_PINMUX('C', 1, AF11)>,
- <STM32_PINMUX('A', 2, AF11)>,
- <STM32_PINMUX('A', 1, AF11)>;
- slew-rate = <2>;
- };
- };
-
- sdmmc1_b4_pins_a: sdmmc1-b4-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
- };
- };
-
- sdmmc1_dir_pins_a: sdmmc1-dir-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
- slew-rate = <3>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
- bias-pull-up;
- };
- };
-
- sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
- <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
- };
- };
-
- sdmmc2_b4_pins_a: sdmmc2-b4-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC1_D0 */
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
- <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 6, AF11)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
- <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 6, AF11)>; /* SDMMC1_CK */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC1_D0 */
- <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC1_D1 */
- <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC1_D2 */
- <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC1_CMD */
- };
- };
-
- spi1_pins: spi1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 5, AF5)>,
- /* SPI1_CLK */
- <STM32_PINMUX('B', 5, AF5)>;
- /* SPI1_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 9, AF5)>;
- /* SPI1_MISO */
- bias-disable;
- };
- };
-
- uart4_pins_a: uart4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('I', 9, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart8_pins_a: uart8-0 {
- pins1 {
- pinmux = <STM32_PINMUX('J', 8, AF8)>; /* UART8_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('J', 9, AF8)>; /* UART8_RX */
- bias-disable;
- };
- };
-
- usart1_pins_a: usart1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart1_pins_b: usart1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart2_pins_a: usart2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
- bias-disable;
- };
- };
-
- usart3_pins_a: usart3-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
- <STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS_DE */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */
- <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
- bias-disable;
- };
- };
-
- usbotg_hs_pins_a: usbotg-hs-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */
- <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
- <STM32_PINMUX('C', 0, AF10)>, /* ULPI_STP> */
- <STM32_PINMUX('A', 5, AF10)>, /* ULPI_CK> */
- <STM32_PINMUX('A', 3, AF10)>, /* ULPI_D0> */
- <STM32_PINMUX('B', 0, AF10)>, /* ULPI_D1> */
- <STM32_PINMUX('B', 1, AF10)>, /* ULPI_D2> */
- <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
- <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
- <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
- <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
- <STM32_PINMUX('B', 5, AF10)>; /* ULPI_D7> */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-};
-
diff --git a/arch/arm/boot/dts/st/stm32h743.dtsi b/arch/arm/boot/dts/st/stm32h743.dtsi
deleted file mode 100644
index 2f19cfbc57ad..000000000000
--- a/arch/arm/boot/dts/st/stm32h743.dtsi
+++ /dev/null
@@ -1,738 +0,0 @@
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "../armv7-m.dtsi"
-#include <dt-bindings/clock/stm32h7-clks.h>
-#include <dt-bindings/mfd/stm32h7-rcc.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- clocks {
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clk_lse: clk-lse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- clk_i2s: i2s_ckin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
- };
-
- soc {
- timer5: timer@40000c00 {
- compatible = "st,stm32-timer";
- reg = <0x40000c00 0x400>;
- interrupts = <50>;
- clocks = <&rcc TIM5_CK>;
- };
-
- lptimer1: timer@40002400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x40002400 0x400>;
- clocks = <&rcc LPTIM1_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@0 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <0>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
- };
-
- spi2: spi@40003800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40003800 0x400>;
- interrupts = <36>;
- resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
- clocks = <&rcc SPI2_CK>;
- status = "disabled";
-
- };
-
- spi3: spi@40003c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40003c00 0x400>;
- interrupts = <51>;
- resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
- clocks = <&rcc SPI3_CK>;
- status = "disabled";
- };
-
- usart2: serial@40004400 {
- compatible = "st,stm32h7-uart";
- reg = <0x40004400 0x400>;
- interrupts = <38>;
- status = "disabled";
- clocks = <&rcc USART2_CK>;
- };
-
- usart3: serial@40004800 {
- compatible = "st,stm32h7-uart";
- reg = <0x40004800 0x400>;
- interrupts = <39>;
- status = "disabled";
- clocks = <&rcc USART3_CK>;
- };
-
- uart4: serial@40004c00 {
- compatible = "st,stm32h7-uart";
- reg = <0x40004c00 0x400>;
- interrupts = <52>;
- status = "disabled";
- clocks = <&rcc UART4_CK>;
- };
-
- i2c1: i2c@40005400 {
- compatible = "st,stm32f7-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x40005400 0x400>;
- interrupts = <31>,
- <32>;
- resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
- clocks = <&rcc I2C1_CK>;
- status = "disabled";
- };
-
- i2c2: i2c@40005800 {
- compatible = "st,stm32f7-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x40005800 0x400>;
- interrupts = <33>,
- <34>;
- resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
- clocks = <&rcc I2C2_CK>;
- status = "disabled";
- };
-
- i2c3: i2c@40005c00 {
- compatible = "st,stm32f7-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x40005C00 0x400>;
- interrupts = <72>,
- <73>;
- resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
- clocks = <&rcc I2C3_CK>;
- status = "disabled";
- };
-
- dac: dac@40007400 {
- compatible = "st,stm32h7-dac-core";
- reg = <0x40007400 0x400>;
- clocks = <&rcc DAC12_CK>;
- clock-names = "pclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- dac1: dac@1 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <1>;
- status = "disabled";
- };
-
- dac2: dac@2 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <2>;
- status = "disabled";
- };
- };
-
- uart8: serial@40007c00 {
- compatible = "st,stm32h7-uart";
- reg = <0x40007c00 0x400>;
- interrupts = <83>;
- status = "disabled";
- clocks = <&rcc UART8_CK>;
- };
-
- usart1: serial@40011000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40011000 0x400>;
- interrupts = <37>;
- status = "disabled";
- clocks = <&rcc USART1_CK>;
- };
-
- spi1: spi@40013000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40013000 0x400>;
- interrupts = <35>;
- resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
- clocks = <&rcc SPI1_CK>;
- status = "disabled";
- };
-
- spi4: spi@40013400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40013400 0x400>;
- interrupts = <84>;
- resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
- clocks = <&rcc SPI4_CK>;
- status = "disabled";
- };
-
- spi5: spi@40015000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40015000 0x400>;
- interrupts = <85>;
- resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
- clocks = <&rcc SPI5_CK>;
- status = "disabled";
- };
-
- dma1: dma-controller@40020000 {
- compatible = "st,stm32-dma";
- reg = <0x40020000 0x400>;
- interrupts = <11>,
- <12>,
- <13>,
- <14>,
- <15>,
- <16>,
- <17>,
- <47>;
- clocks = <&rcc DMA1_CK>;
- #dma-cells = <4>;
- st,mem2mem;
- dma-requests = <8>;
- status = "disabled";
- };
-
- dma2: dma-controller@40020400 {
- compatible = "st,stm32-dma";
- reg = <0x40020400 0x400>;
- interrupts = <56>,
- <57>,
- <58>,
- <59>,
- <60>,
- <68>,
- <69>,
- <70>;
- clocks = <&rcc DMA2_CK>;
- #dma-cells = <4>;
- st,mem2mem;
- dma-requests = <8>;
- status = "disabled";
- };
-
- dmamux1: dma-router@40020800 {
- compatible = "st,stm32h7-dmamux";
- reg = <0x40020800 0x40>;
- #dma-cells = <3>;
- dma-channels = <16>;
- dma-requests = <128>;
- dma-masters = <&dma1 &dma2>;
- clocks = <&rcc DMA1_CK>;
- };
-
- adc_12: adc@40022000 {
- compatible = "st,stm32h7-adc-core";
- reg = <0x40022000 0x400>;
- interrupts = <18>;
- clocks = <&rcc ADC12_CK>;
- clock-names = "bus";
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc1: adc@0 {
- compatible = "st,stm32h7-adc";
- #io-channel-cells = <1>;
- reg = <0x0>;
- interrupt-parent = <&adc_12>;
- interrupts = <0>;
- status = "disabled";
- };
-
- adc2: adc@100 {
- compatible = "st,stm32h7-adc";
- #io-channel-cells = <1>;
- reg = <0x100>;
- interrupt-parent = <&adc_12>;
- interrupts = <1>;
- status = "disabled";
- };
- };
-
- usbotg_hs: usb@40040000 {
- compatible = "st,stm32f7-hsotg";
- reg = <0x40040000 0x40000>;
- interrupts = <77>;
- clocks = <&rcc USB1OTG_CK>;
- clock-names = "otg";
- g-rx-fifo-size = <256>;
- g-np-tx-fifo-size = <32>;
- g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- usbotg_fs: usb@40080000 {
- compatible = "st,stm32f4x9-fsotg";
- reg = <0x40080000 0x40000>;
- interrupts = <101>;
- clocks = <&rcc USB2OTG_CK>;
- clock-names = "otg";
- status = "disabled";
- };
-
- ltdc: display-controller@50001000 {
- compatible = "st,stm32-ltdc";
- reg = <0x50001000 0x200>;
- interrupts = <88>, <89>;
- resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
- clocks = <&rcc LTDC_CK>;
- clock-names = "lcd";
- status = "disabled";
- };
-
- mdma1: dma-controller@52000000 {
- compatible = "st,stm32h7-mdma";
- reg = <0x52000000 0x1000>;
- interrupts = <122>;
- clocks = <&rcc MDMA_CK>;
- #dma-cells = <5>;
- dma-channels = <16>;
- dma-requests = <32>;
- };
-
- sdmmc1: mmc@52007000 {
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x10153180>;
- reg = <0x52007000 0x1000>;
- interrupts = <49>;
- clocks = <&rcc SDMMC1_CK>;
- clock-names = "apb_pclk";
- resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <120000000>;
- };
-
- sdmmc2: mmc@48022400 {
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x10153180>;
- reg = <0x48022400 0x400>;
- interrupts = <124>;
- clocks = <&rcc SDMMC2_CK>;
- clock-names = "apb_pclk";
- resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <120000000>;
- status = "disabled";
- };
-
- exti: interrupt-controller@58000000 {
- compatible = "st,stm32h7-exti";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x58000000 0x400>;
- interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
- };
-
- syscfg: syscon@58000400 {
- compatible = "st,stm32-syscfg", "syscon";
- reg = <0x58000400 0x400>;
- };
-
- spi6: spi@58001400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x58001400 0x400>;
- interrupts = <86>;
- resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
- clocks = <&rcc SPI6_CK>;
- status = "disabled";
- };
-
- i2c4: i2c@58001c00 {
- compatible = "st,stm32f7-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x58001C00 0x400>;
- interrupts = <95>,
- <96>;
- resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
- clocks = <&rcc I2C4_CK>;
- status = "disabled";
- };
-
- lptimer2: timer@58002400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x58002400 0x400>;
- clocks = <&rcc LPTIM2_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@1 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <1>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
- };
-
- lptimer3: timer@58002800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x58002800 0x400>;
- clocks = <&rcc LPTIM3_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@2 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <2>;
- status = "disabled";
- };
- };
-
- lptimer4: timer@58002c00 {
- compatible = "st,stm32-lptimer";
- reg = <0x58002c00 0x400>;
- clocks = <&rcc LPTIM4_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- lptimer5: timer@58003000 {
- compatible = "st,stm32-lptimer";
- reg = <0x58003000 0x400>;
- clocks = <&rcc LPTIM5_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- vrefbuf: regulator@58003c00 {
- compatible = "st,stm32-vrefbuf";
- reg = <0x58003C00 0x8>;
- clocks = <&rcc VREF_CK>;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <2500000>;
- status = "disabled";
- };
-
- rtc: rtc@58004000 {
- compatible = "st,stm32h7-rtc";
- reg = <0x58004000 0x400>;
- clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
- clock-names = "pclk", "rtc_ck";
- assigned-clocks = <&rcc RTC_CK>;
- assigned-clock-parents = <&rcc LSE_CK>;
- interrupt-parent = <&exti>;
- interrupts = <17 IRQ_TYPE_EDGE_RISING>;
- st,syscfg = <&pwrcfg 0x00 0x100>;
- status = "disabled";
- };
-
- rcc: reset-clock-controller@58024400 {
- compatible = "st,stm32h743-rcc", "st,stm32-rcc";
- reg = <0x58024400 0x400>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
- st,syscfg = <&pwrcfg>;
- };
-
- pwrcfg: power-config@58024800 {
- compatible = "st,stm32-power-config", "syscon";
- reg = <0x58024800 0x400>;
- };
-
- adc_3: adc@58026000 {
- compatible = "st,stm32h7-adc-core";
- reg = <0x58026000 0x400>;
- interrupts = <127>;
- clocks = <&rcc ADC3_CK>;
- clock-names = "bus";
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc3: adc@0 {
- compatible = "st,stm32h7-adc";
- #io-channel-cells = <1>;
- reg = <0x0>;
- interrupt-parent = <&adc_3>;
- interrupts = <0>;
- status = "disabled";
- };
- };
-
- mac: ethernet@40028000 {
- compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
- reg = <0x40028000 0x8000>;
- reg-names = "stmmaceth";
- interrupts = <61>;
- interrupt-names = "macirq";
- clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
- clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
- st,syscon = <&syscfg 0x4>;
- snps,pbl = <8>;
- status = "disabled";
- };
-
- pinctrl: pinctrl@58020000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32h743-pinctrl";
- ranges = <0 0x58020000 0x3000>;
- interrupt-parent = <&exti>;
- st,syscfg = <&syscfg 0x8>;
-
- gpioa: gpio@58020000 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc GPIOA_CK>;
- st,bank-name = "GPIOA";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@58020400 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x400 0x400>;
- clocks = <&rcc GPIOB_CK>;
- st,bank-name = "GPIOB";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@58020800 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x800 0x400>;
- clocks = <&rcc GPIOC_CK>;
- st,bank-name = "GPIOC";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@58020c00 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0xc00 0x400>;
- clocks = <&rcc GPIOD_CK>;
- st,bank-name = "GPIOD";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@58021000 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc GPIOE_CK>;
- st,bank-name = "GPIOE";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@58021400 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x1400 0x400>;
- clocks = <&rcc GPIOF_CK>;
- st,bank-name = "GPIOF";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@58021800 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x1800 0x400>;
- clocks = <&rcc GPIOG_CK>;
- st,bank-name = "GPIOG";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@58021c00 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x1c00 0x400>;
- clocks = <&rcc GPIOH_CK>;
- st,bank-name = "GPIOH";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@58022000 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc GPIOI_CK>;
- st,bank-name = "GPIOI";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@58022400 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x2400 0x400>;
- clocks = <&rcc GPIOJ_CK>;
- st,bank-name = "GPIOJ";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@58022800 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x2800 0x400>;
- clocks = <&rcc GPIOK_CK>;
- st,bank-name = "GPIOK";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <8>;
- gpio-ranges = <&pinctrl 0 160 8>;
- };
- };
- };
-};
-
-&systick {
- clock-frequency = <250000000>;
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32h743i-disco.dts b/arch/arm/boot/dts/st/stm32h743i-disco.dts
deleted file mode 100644
index 78d55b77db7c..000000000000
--- a/arch/arm/boot/dts/st/stm32h743i-disco.dts
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright 2017 - Patrice Chotard <patrice.chotard@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32h743.dtsi"
-#include "stm32h7-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "STMicroelectronics STM32H743i-Discovery board";
- compatible = "st,stm32h743i-disco", "st,stm32h743";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@d0000000 {
- device_type = "memory";
- reg = <0xd0000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart2;
- };
-
- v3v3: regulator-v3v3 {
- compatible = "regulator-fixed";
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- leds {
- compatible = "gpio-leds";
- led_green: led-green {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpioi 12 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
-
- led-orange {
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&gpioi 13 GPIO_ACTIVE_LOW>;
- };
-
- led-red {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpioi 14 GPIO_ACTIVE_LOW>;
- };
-
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
- };
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_green>;
- };
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&mac {
- status = "disabled";
- pinctrl-0 = <ðernet_rmii>;
- pinctrl-names = "default";
- phy-mode = "rmii";
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&usart2 {
- pinctrl-0 = <&usart2_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32h743i-eval.dts b/arch/arm/boot/dts/st/stm32h743i-eval.dts
deleted file mode 100644
index e5e10b0758ee..000000000000
--- a/arch/arm/boot/dts/st/stm32h743i-eval.dts
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32h743.dtsi"
-#include "stm32h7-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "STMicroelectronics STM32H743i-EVAL board";
- compatible = "st,stm32h743i-eval", "st,stm32h743";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@d0000000 {
- device_type = "memory";
- reg = <0xd0000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- led {
- compatible = "gpio-leds";
- led_green: led-green {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpiof 10 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
-
- led-red {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
- };
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_green>;
- };
- };
-
- vdda: regulator-vdda {
- compatible = "regulator-fixed";
- regulator-name = "vdda";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- v2v9_sd: regulator-v2v9_sd {
- compatible = "regulator-fixed";
- regulator-name = "v2v9_sd";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- regulator-always-on;
- };
-
- usbotg_hs_phy: usb-phy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc USB1ULPI_CK>;
- clock-names = "main_clk";
- };
-};
-
-&adc_12 {
- vdda-supply = <&vdda>;
- vref-supply = <&vdda>;
- status = "okay";
- adc1: adc@0 {
- /* potentiometer */
- st,adc-channels = <0>;
- status = "okay";
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins_a>;
- pinctrl-names = "default";
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&mac {
- status = "disabled";
- pinctrl-0 = <ðernet_rmii>;
- pinctrl-names = "default";
- phy-mode = "rmii";
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
- broken-cd;
- st,sig-dir;
- st,neg-edge;
- st,use-ckin;
- bus-width = <4>;
- vmmc-supply = <&v2v9_sd>;
- status = "okay";
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- dr_mode = "otg";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32h747i-disco.dts b/arch/arm/boot/dts/st/stm32h747i-disco.dts
deleted file mode 100644
index c9dcc680e26d..000000000000
--- a/arch/arm/boot/dts/st/stm32h747i-disco.dts
+++ /dev/null
@@ -1,149 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2025 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com>
- */
-
-/dts-v1/;
-#include "stm32h743.dtsi"
-#include "stm32h7-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "STMicroelectronics STM32H747i-Discovery board";
- compatible = "st,stm32h747i-disco", "st,stm32h747";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@d0000000 {
- device_type = "memory";
- reg = <0xd0000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart1;
- serial1 = &uart8;
- };
-
- v3v3: regulator-v3v3 {
- compatible = "regulator-fixed";
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- leds {
- compatible = "gpio-leds";
- led_green: led-green {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpioi 12 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
- led-orange {
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&gpioi 13 GPIO_ACTIVE_LOW>;
- };
- led-red {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpioi 14 GPIO_ACTIVE_LOW>;
- };
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "User";
- linux,code = <KEY_WAKEUP>;
- gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
- };
- button-1 {
- label = "JoySel";
- linux,code = <KEY_ENTER>;
- gpios = <&gpiok 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- };
- button-2 {
- label = "JoyDown";
- linux,code = <KEY_DOWN>;
- gpios = <&gpiok 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- };
- button-3 {
- label = "JoyUp";
- linux,code = <KEY_UP>;
- gpios = <&gpiok 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- };
- button-4 {
- label = "JoyLeft";
- linux,code = <KEY_LEFT>;
- gpios = <&gpiok 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- };
- button-5 {
- label = "JoyRight";
- linux,code = <KEY_RIGHT>;
- gpios = <&gpiok 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- };
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_green>;
- };
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&mac {
- status = "disabled";
- pinctrl-0 = <ðernet_rmii>;
- pinctrl-names = "default";
- phy-mode = "rmii";
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_b>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&uart8 {
- pinctrl-0 = <&uart8_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32h750.dtsi b/arch/arm/boot/dts/st/stm32h750.dtsi
deleted file mode 100644
index 41e3b1e3a874..000000000000
--- a/arch/arm/boot/dts/st/stm32h750.dtsi
+++ /dev/null
@@ -1,6 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */
-
-#include "stm32h743.dtsi"
-
-
diff --git a/arch/arm/boot/dts/st/stm32h750i-art-pi.dts b/arch/arm/boot/dts/st/stm32h750i-art-pi.dts
deleted file mode 100644
index 56c53e262da7..000000000000
--- a/arch/arm/boot/dts/st/stm32h750i-art-pi.dts
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * For art-pi board resources, you can refer to link:
- * https://art-pi.gitee.io/website/
- */
-
-/dts-v1/;
-#include "stm32h750.dtsi"
-#include "stm32h7-pinctrl.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "RT-Thread STM32H750i-ART-PI board";
- compatible = "st,stm32h750i-art-pi", "st,stm32h750";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:2000000n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xc0000000 0x2000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- linux,cma {
- compatible = "shared-dma-pool";
- no-map;
- size = <0x100000>;
- linux,dma-default;
- };
- };
-
- aliases {
- serial0 = &uart4;
- serial1 = &usart3;
- };
-
- leds {
- compatible = "gpio-leds";
- led-red {
- gpios = <&gpioi 8 0>;
- };
- led-green {
- gpios = <&gpioc 15 0>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- v3v3: regulator-v3v3 {
- compatible = "regulator-fixed";
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- wlan_pwr: regulator-wlan {
- compatible = "regulator-fixed";
-
- regulator-name = "wl-reg";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&dma1 {
- status = "okay";
-};
-
-&dma2 {
- status = "okay";
-};
-
-&mac {
- status = "disabled";
- pinctrl-0 = <ðernet_rmii>;
- pinctrl-names = "default";
- phy-mode = "rmii";
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&sdmmc2 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc2_b4_pins_a>;
- pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
- broken-cd;
- non-removable;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&wlan_pwr>;
- status = "okay";
-
- #address-cells = <1>;
- #size-cells = <0>;
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-&spi1 {
- status = "okay";
- pinctrl-0 = <&spi1_pins>;
- pinctrl-names = "default";
- cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
- dmas = <&dmamux1 37 0x400 0x05>,
- <&dmamux1 38 0x400 0x05>;
- dma-names = "rx", "tx";
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "winbond,w25q128", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <80000000>;
-
- partition@0 {
- label = "root filesystem";
- reg = <0 0x1000000>;
- };
- };
-};
-
-&usart2 {
- pinctrl-0 = <&usart2_pins_a>;
- pinctrl-names = "default";
- status = "disabled";
-};
-
-&usart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&usart3_pins_a>;
- dmas = <&dmamux1 45 0x400 0x05>,
- <&dmamux1 46 0x400 0x05>;
- dma-names = "rx", "tx";
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- host-wakeup-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>;
- device-wakeup-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>;
- max-speed = <115200>;
- };
-};
-
-&uart4 {
- pinctrl-0 = <&uart4_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
deleted file mode 100644
index 7366aade19ad..000000000000
--- a/arch/arm/configs/stm32_defconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-CONFIG_NO_HZ_IDLE=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_POSIX_TIMERS is not set
-CONFIG_BASE_SMALL=y
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-# CONFIG_IO_URING is not set
-# CONFIG_ADVISE_SYSCALLS is not set
-# CONFIG_MMU is not set
-CONFIG_ARCH_STM32=y
-CONFIG_CPU_V7M_NUM_IRQ=240
-CONFIG_SET_MEM_PARAM=y
-CONFIG_DRAM_BASE=0x90000000
-CONFIG_XIP_KERNEL=y
-CONFIG_XIP_PHYS_ADDR=0x08008000
-# CONFIG_SUSPEND is not set
-# CONFIG_GCC_PLUGINS is not set
-CONFIG_BINFMT_FLAT=y
-# CONFIG_COREDUMP is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_BLK_DEV is not set
-CONFIG_EEPROM_93CX6=y
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_VT is not set
-# CONFIG_UNIX98_PTYS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_STM32=y
-CONFIG_SERIAL_STM32_CONSOLE=y
-CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_STM32F4=y
-CONFIG_I2C_STM32F7=y
-CONFIG_GPIO_STMPE=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_MFD_STMPE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_ARMMMCI=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_STM32=y
-CONFIG_DMADEVICES=y
-CONFIG_STM32_DMA=y
-CONFIG_STM32_DMAMUX=y
-CONFIG_STM32_MDMA=y
-# CONFIG_COMMON_CLK_STM32MP is not set
-CONFIG_IIO=y
-CONFIG_STM32_ADC_CORE=y
-CONFIG_STM32_ADC=y
-CONFIG_EXT4_FS=y
-# CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-CONFIG_NLS=y
-CONFIG_PRINTK_TIME=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_SLUB_DEBUG is not set
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index 4ac3384e397a..6ca8507f9451 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -1,17 +1,15 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_STM32
bool "STMicroelectronics STM32 family"
- depends on ARM_SINGLE_ARMV7M || ARCH_MULTI_V7
- select ARMV7M_SYSTICK if ARM_SINGLE_ARMV7M
- select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7
- select ARM_GIC if ARCH_MULTI_V7
- select ARM_PSCI if ARCH_MULTI_V7
+ depends on ARCH_MULTI_V7
+ select HAVE_ARM_ARCH_TIMER
+ select ARM_GIC
+ select ARM_PSCI
select ARM_AMBA
select ARCH_HAS_RESET_CONTROLLER
select CLKSRC_STM32
select PINCTRL
select RESET_CONTROLLER
- select STM32_EXTI if ARM_SINGLE_ARMV7M
select STM32_FIREWALL
help
Support for STMicroelectronics STM32MP1 processors using Cortex-A7
@@ -20,32 +18,6 @@ menuconfig ARCH_STM32
if ARCH_STM32
-if ARM_SINGLE_ARMV7M
-
-config MACH_STM32F429
- bool "STMicroelectronics STM32F429 (DEPRECATED)"
- default y
-
-config MACH_STM32F469
- bool "STMicroelectronics STM32F469 (DEPRECATED)"
- default y
-
-config MACH_STM32F746
- bool "STMicroelectronics STM32F746 (DEPRECATED)"
- default y
-
-config MACH_STM32F769
- bool "STMicroelectronics STM32F769 (DEPRECATED)"
- default y
-
-config MACH_STM32H743
- bool "STMicroelectronics STM32H743 (DEPRECATED)"
- default y
-
-endif # ARMv7-M
-
-if ARCH_MULTI_V7
-
config MACH_STM32MP157
bool "STMicroelectronics STM32MP157"
select ARM_ERRATA_814220
@@ -59,6 +31,4 @@ config MACH_STM32MP13
Support for STM32MP13 SoCs:
STM32MP131, STM32MP133, STM32MP135
-endif # ARMv7-A
-
endif
diff --git a/arch/arm/mach-stm32/board-dt.c b/arch/arm/mach-stm32/board-dt.c
index e6233c8725ae..3d32ce2c1333 100644
--- a/arch/arm/mach-stm32/board-dt.c
+++ b/arch/arm/mach-stm32/board-dt.c
@@ -12,13 +12,6 @@
#endif
static const char *const stm32_compat[] __initconst = {
- "st,stm32f429",
- "st,stm32f469",
- "st,stm32f746",
- "st,stm32f769",
- "st,stm32h743",
- "st,stm32h747",
- "st,stm32h750",
"st,stm32mp131",
"st,stm32mp133",
"st,stm32mp135",
--
2.53.0
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 10/13] ARM: stm32: remove stm32f4/f7/h7 MCU support
2026-09-08 15:28 ` [PATCH 10/13] ARM: stm32: remove stm32f4/f7/h7 MCU support Arnd Bergmann
@ 2026-09-08 17:36 ` Linus Walleij
0 siblings, 0 replies; 70+ messages in thread
From: Linus Walleij @ 2026-09-08 17:36 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Russell King,
Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski,
Christophe Parant, Benjamin Gaignard, Dario Binacchi
On Tue, Sep 8, 2026 at 5:30 PM Arnd Bergmann <arnd@kernel.org> wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The stm32 platform started out as a Cortex-M based microcontoller
> platform in 2007, with a few of the older products gaining Linux kernel
> support in 2016. These days, the only relevant chips for Linux are the
> stm32mp1 (Cortex-A7) and stm32mp2 (Cortex-A35) product lines, with the
> microcontrollers running smaller RTOSs on new products.
>
> The microcontrollers were marked as deprecated in the linux-7.3LTS
> release, which will remain supported for a few more years and
> is expected to be sufficient for any of the remaining original users.
>
> Remove the MCU support now, leaving only the stm32mp SoCs in the platform.
>
> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Christophe Parant <c.parant@phytec.fr>
> Cc: Benjamin Gaignard <benjamin.gaignard@collabora.com>
> Cc: Dario Binacchi <dario.binacchi@amarulasolutions.com>
> Cc: devicetree@vger.kernel.org
> Cc: linux-stm32@st-md-mailman.stormreply.com
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linusw@kernel.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH 11/13] ARM: versatile: remove mps2 support
2026-09-08 15:27 [PATCH 00/13] ARM: deprecated platform removal Arnd Bergmann
` (9 preceding siblings ...)
2026-09-08 15:28 ` [PATCH 10/13] ARM: stm32: remove stm32f4/f7/h7 MCU support Arnd Bergmann
@ 2026-09-08 15:28 ` Arnd Bergmann
2026-09-08 15:41 ` Vladimir Murzin
` (2 more replies)
2026-09-08 15:28 ` [PATCH 12/13] ARM: at91: remove samv7 support Arnd Bergmann
` (2 subsequent siblings)
13 siblings, 3 replies; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 15:28 UTC (permalink / raw)
To: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski,
Andi Shyti, linux-i2c
From: Arnd Bergmann <arnd@arndb.de>
The Arm mps2 platform is the reference implementation for Arm
microcontrollers and is useful for testing but not expected to be used
as a production device.
With all the Cortex-M based products gone, there is no longer a need
for a reference platform either, so remove it as well.
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Sudeep Holla <sudeep.holla@kernel.org>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Linus Walleij <linusw@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Andi Shyti <andi.shyti@kernel.org>
Cc: Ethan Nelson-Moore <enelsonmoore@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linux-i2c@vger.kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/Kconfig | 14 --
arch/arm/boot/dts/arm/Makefile | 3 -
arch/arm/boot/dts/arm/mps2-an385.dts | 92 -----------
arch/arm/boot/dts/arm/mps2-an399.dts | 92 -----------
arch/arm/boot/dts/arm/mps2.dtsi | 220 ---------------------------
arch/arm/configs/mps2_defconfig | 102 -------------
arch/arm/mach-versatile/Makefile | 3 -
arch/arm/mach-versatile/v2m-mps2.c | 17 ---
drivers/i2c/busses/Kconfig | 2 +-
9 files changed, 1 insertion(+), 544 deletions(-)
delete mode 100644 arch/arm/boot/dts/arm/mps2-an385.dts
delete mode 100644 arch/arm/boot/dts/arm/mps2-an399.dts
delete mode 100644 arch/arm/boot/dts/arm/mps2.dtsi
delete mode 100644 arch/arm/configs/mps2_defconfig
delete mode 100644 arch/arm/mach-versatile/v2m-mps2.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 13b38be3353a..cf380b686867 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -443,20 +443,6 @@ source "arch/arm/mach-zte/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
-config ARCH_MPS2
- bool "ARM MPS2 platform (DEPRECATED)"
- depends on ARM_SINGLE_ARMV7M
- select ARM_AMBA
- select CLKSRC_MPS2
- help
- Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
- with a range of available cores like Cortex-M3/M4/M7.
-
- Please, note that depends which Application Note is used memory map
- for the platform may vary, so adjustment of RAM base might be needed.
-
- This platform is scheduled for removal in early 2027
-
# Definitions to make life easier
config PLAT_ORION
bool
diff --git a/arch/arm/boot/dts/arm/Makefile b/arch/arm/boot/dts/arm/Makefile
index 07ebb64e2cd0..c01593dd197d 100644
--- a/arch/arm/boot/dts/arm/Makefile
+++ b/arch/arm/boot/dts/arm/Makefile
@@ -3,9 +3,6 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += \
integratorap.dtb \
integratorap-im-pd1.dtb \
integratorcp.dtb
-dtb-$(CONFIG_ARCH_MPS2) += \
- mps2-an385.dtb \
- mps2-an399.dtb
dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pb1176.dtb \
arm-realview-pb11mp.dtb \
diff --git a/arch/arm/boot/dts/arm/mps2-an385.dts b/arch/arm/boot/dts/arm/mps2-an385.dts
deleted file mode 100644
index aebbebfc25d1..000000000000
--- a/arch/arm/boot/dts/arm/mps2-an385.dts
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright (C) 2015 ARM Limited
- *
- * Author: Vladimir Murzin <vladimir.murzin@arm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include "mps2.dtsi"
-
-/ {
- model = "ARM MPS2 Application Note 385/386";
- compatible = "arm,mps2";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- bootargs = "earlycon";
- stdout-path = "serial0:9600n8";
- };
-
- memory@21000000 {
- device_type = "memory";
- reg = <0x21000000 0x1000000>;
- };
-
- smb {
- ethernet@0,0 {
- compatible = "smsc,lan9220", "smsc,lan9115";
- reg = <0 0x0 0x10000>;
- interrupts = <13>;
- interrupt-parent = <&nvic>;
- smsc,irq-active-high;
- };
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-&timer0 {
- status = "okay";
-};
-
-&timer1 {
- status = "okay";
-};
-
-&wdt {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/arm/mps2-an399.dts b/arch/arm/boot/dts/arm/mps2-an399.dts
deleted file mode 100644
index 349abf70b2a5..000000000000
--- a/arch/arm/boot/dts/arm/mps2-an399.dts
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright (C) 2015 ARM Limited
- *
- * Author: Vladimir Murzin <vladimir.murzin@arm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include "mps2.dtsi"
-
-/ {
- model = "ARM MPS2 Application Note 399/400";
- compatible = "arm,mps2";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- bootargs = "earlycon";
- stdout-path = "serial0:9600n8";
- };
-
- memory@60000000 {
- device_type = "memory";
- reg = <0x60000000 0x1000000>;
- };
-
- smb {
- ethernet@1,0 {
- compatible = "smsc,lan9220", "smsc,lan9115";
- reg = <1 0x0 0x10000>;
- interrupts = <13>;
- interrupt-parent = <&nvic>;
- smsc,irq-active-high;
- };
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-&timer0 {
- status = "okay";
-};
-
-&timer1 {
- status = "okay";
-};
-
-&wdt {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/arm/mps2.dtsi b/arch/arm/boot/dts/arm/mps2.dtsi
deleted file mode 100644
index e240bc8aa605..000000000000
--- a/arch/arm/boot/dts/arm/mps2.dtsi
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright (C) 2015 ARM Limited
- *
- * Author: Vladimir Murzin <vladimir.murzin@arm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "../armv7-m.dtsi"
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- oscclk0: clock-50000000 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- };
-
- oscclk1: clock-24576000 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24576000>;
- };
-
- oscclk2: clock-25000000 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-
- cfgclk: clock-5000000 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <5000000>;
- };
-
- spicfgclk: clock-75000000 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <75000000>;
- };
-
- sysclk: spiclcd: spicon: i2cclcd: i2caud: clock-sys {
- compatible = "fixed-factor-clock";
- clocks = <&oscclk0>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- audmclk: clk-12388000 {
- compatible = "fixed-factor-clock";
- clocks = <&oscclk1>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- audsclk: clk-3072000 {
- compatible = "fixed-factor-clock";
- clocks = <&oscclk1>;
- #clock-cells = <0>;
- clock-div = <8>;
- clock-mult = <1>;
- };
-
- soc {
- compatible = "simple-bus";
- ranges;
-
- apb@40000000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x40000000 0x10000>;
-
- timer0: mps2-timer0@0 {
- compatible = "arm,mps2-timer";
- reg = <0x0 0x1000>;
- interrupts = <8>;
- clocks = <&sysclk>;
- status = "disabled";
- };
-
- timer1: mps2-timer1@1000 {
- compatible = "arm,mps2-timer";
- reg = <0x1000 0x1000>;
- interrupts = <9>;
- clocks = <&sysclk>;
- status = "disabled";
- };
-
- timer2: dual-timer@2000 {
- compatible = "arm,sp804", "arm,primecell";
- reg = <0x2000 0x1000>;
- clocks = <&sysclk>, <&sysclk>, <&sysclk>;
- clock-names = "timer0clk", "timer1clk",
- "apb_pclk";
- interrupts = <10>;
- status = "disabled";
- };
-
- uart0: serial@4000 {
- compatible = "arm,mps2-uart";
- reg = <0x4000 0x1000>;
- interrupts = <0>, <1>, <12>;
- clocks = <&sysclk>;
- status = "disabled";
- };
-
- uart1: serial@5000 {
- compatible = "arm,mps2-uart";
- reg = <0x5000 0x1000>;
- interrupts = <2>, <3>, <12>;
- clocks = <&sysclk>;
- status = "disabled";
- };
-
- uart2: serial@6000 {
- compatible = "arm,mps2-uart";
- reg = <0x6000 0x1000>;
- interrupts = <4>, <5>, <12>;
- clocks = <&sysclk>;
- status = "disabled";
- };
-
- wdt: watchdog@8000 {
- compatible = "arm,sp805", "arm,primecell";
- arm,primecell-periphid = <0x00141805>;
- reg = <0x8000 0x1000>;
- interrupts = <0>;
- clocks = <&sysclk>, <&sysclk>;
- clock-names = "wdog_clk", "apb_pclk";
- status = "disabled";
- };
- };
- };
-
- fpga@40020000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x40020000 0x10000>;
-
- fpgaio@8000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x8000 0x10>;
-
- ranges = <0x0 0x8000 0x10>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- led@0,0 {
- compatible = "register-bit-led";
- reg = <0x00 0x04>;
- offset = <0x0>;
- mask = <0x01>;
- label = "userled:0";
- linux,default-trigger = "heartbeat";
- default-state = "on";
- };
-
- led@0,1 {
- compatible = "register-bit-led";
- reg = <0x00 0x04>;
- offset = <0x0>;
- mask = <0x02>;
- label = "userled:1";
- linux,default-trigger = "usr";
- default-state = "off";
- };
- };
- };
-
- smb {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0x40200000 0x10000>,
- <1 0 0xa0000000 0x10000>;
- };
-};
diff --git a/arch/arm/configs/mps2_defconfig b/arch/arm/configs/mps2_defconfig
deleted file mode 100644
index cacf3876f6e4..000000000000
--- a/arch/arm/configs/mps2_defconfig
+++ /dev/null
@@ -1,102 +0,0 @@
-CONFIG_NO_HZ_IDLE=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-CONFIG_BASE_SMALL=y
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-# CONFIG_MMU is not set
-CONFIG_ARCH_MPS2=y
-CONFIG_SET_MEM_PARAM=y
-CONFIG_DRAM_BASE=0x21000000
-CONFIG_DRAM_SIZE=0x1000000
-# CONFIG_SUSPEND is not set
-# CONFIG_BLOCK is not set
-CONFIG_BINFMT_FLAT=y
-# CONFIG_COREDUMP is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FW_LOADER is not set
-CONFIG_NETDEVICES=y
-# CONFIG_NET_CORE is not set
-# CONFIG_NET_VENDOR_ARC is not set
-# CONFIG_NET_CADENCE is not set
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CIRRUS is not set
-# CONFIG_NET_VENDOR_EZCHIP is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-# CONFIG_NET_VENDOR_HISILICON is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_QUALCOMM is not set
-# CONFIG_NET_VENDOR_RENESAS is not set
-# CONFIG_NET_VENDOR_ROCKER is not set
-# CONFIG_NET_VENDOR_SAMSUNG is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMSC911X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_NET_VENDOR_VIA is not set
-# CONFIG_NET_VENDOR_WIZNET is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_MPS2_UART_CONSOLE=y
-CONFIG_SERIAL_MPS2_UART=y
-CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_ARM_SP805_WATCHDOG=y
-CONFIG_MFD_SYSCON=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_SYSCON=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_ONESHOT=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_ARM_TIMER_SP804=y
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_NFS_FS=y
-CONFIG_NFS_V4=y
-CONFIG_NFS_V4_1=y
-CONFIG_NFS_V4_2=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
-CONFIG_PRINTK_TIME=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-CONFIG_DEBUG_FS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_MEMTEST=y
diff --git a/arch/arm/mach-versatile/Makefile b/arch/arm/mach-versatile/Makefile
index d819fb2fc450..07171ef1d6a7 100644
--- a/arch/arm/mach-versatile/Makefile
+++ b/arch/arm/mach-versatile/Makefile
@@ -22,9 +22,6 @@ obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o
CFLAGS_tc2_pm.o += -march=armv7-a
CFLAGS_REMOVE_tc2_pm.o = -pg
-# mps2
-obj-$(CONFIG_ARCH_MPS2) += v2m-mps2.o
-
ifdef CONFIG_SMP
obj-y += headsmp.o platsmp.o
obj-$(CONFIG_ARCH_REALVIEW) += platsmp-realview.o
diff --git a/arch/arm/mach-versatile/v2m-mps2.c b/arch/arm/mach-versatile/v2m-mps2.c
deleted file mode 100644
index 5b50d8e95cd7..000000000000
--- a/arch/arm/mach-versatile/v2m-mps2.c
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2015 ARM Limited
- *
- * Author: Vladimir Murzin <vladimir.murzin@arm.com>
- */
-
-#include <asm/mach/arch.h>
-
-static const char *const mps2_compat[] __initconst = {
- "arm,mps2",
- NULL
-};
-
-DT_MACHINE_START(MPS2DT, "MPS2 (Device Tree Support)")
- .dt_compat = mps2_compat,
-MACHINE_END
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index d7b89508311f..9d60d4b650ec 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1260,7 +1260,7 @@ config I2C_UNIPHIER_F
config I2C_VERSATILE
tristate "ARM Versatile/Realview I2C bus support"
- depends on ARCH_MPS2 || ARCH_VERSATILE || ARCH_REALVIEW || ARCH_VEXPRESS || COMPILE_TEST
+ depends on ARCH_VERSATILE || ARCH_REALVIEW || ARCH_VEXPRESS || COMPILE_TEST
select I2C_ALGOBIT
help
Say yes if you want to support the I2C serial bus on ARMs Versatile
--
2.53.0
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 11/13] ARM: versatile: remove mps2 support
2026-09-08 15:28 ` [PATCH 11/13] ARM: versatile: remove mps2 support Arnd Bergmann
@ 2026-09-08 15:41 ` Vladimir Murzin
2026-09-08 17:37 ` Linus Walleij
2026-09-08 19:49 ` Sudeep Holla
2 siblings, 0 replies; 70+ messages in thread
From: Vladimir Murzin @ 2026-09-08 15:41 UTC (permalink / raw)
To: Arnd Bergmann, Krzysztof Kozlowski, Alexandre Belloni,
Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski,
Andi Shyti, linux-i2c
On 9/8/26 16:28, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The Arm mps2 platform is the reference implementation for Arm
> microcontrollers and is useful for testing but not expected to be used
> as a production device.
>
> With all the Cortex-M based products gone, there is no longer a need
> for a reference platform either, so remove it as well.
>
> Cc: Liviu Dudau <liviu.dudau@arm.com>
> Cc: Sudeep Holla <sudeep.holla@kernel.org>
> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Cc: Linus Walleij <linusw@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Andi Shyti <andi.shyti@kernel.org>
> Cc: Ethan Nelson-Moore <enelsonmoore@gmail.com>
> Cc: devicetree@vger.kernel.org
> Cc: linux-i2c@vger.kernel.org
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> arch/arm/Kconfig | 14 --
> arch/arm/boot/dts/arm/Makefile | 3 -
> arch/arm/boot/dts/arm/mps2-an385.dts | 92 -----------
> arch/arm/boot/dts/arm/mps2-an399.dts | 92 -----------
> arch/arm/boot/dts/arm/mps2.dtsi | 220 ---------------------------
> arch/arm/configs/mps2_defconfig | 102 -------------
> arch/arm/mach-versatile/Makefile | 3 -
> arch/arm/mach-versatile/v2m-mps2.c | 17 ---
> drivers/i2c/busses/Kconfig | 2 +-
> 9 files changed, 1 insertion(+), 544 deletions(-)
> delete mode 100644 arch/arm/boot/dts/arm/mps2-an385.dts
> delete mode 100644 arch/arm/boot/dts/arm/mps2-an399.dts
> delete mode 100644 arch/arm/boot/dts/arm/mps2.dtsi
> delete mode 100644 arch/arm/configs/mps2_defconfig
> delete mode 100644 arch/arm/mach-versatile/v2m-mps2.c
Acked-by: Vladimir Murzin <vladimir.murzin@arm.com>
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 11/13] ARM: versatile: remove mps2 support
2026-09-08 15:28 ` [PATCH 11/13] ARM: versatile: remove mps2 support Arnd Bergmann
2026-09-08 15:41 ` Vladimir Murzin
@ 2026-09-08 17:37 ` Linus Walleij
2026-09-08 19:49 ` Sudeep Holla
2 siblings, 0 replies; 70+ messages in thread
From: Linus Walleij @ 2026-09-08 17:37 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Russell King,
Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski,
Andi Shyti, linux-i2c
On Tue, Sep 8, 2026 at 5:30 PM Arnd Bergmann <arnd@kernel.org> wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The Arm mps2 platform is the reference implementation for Arm
> microcontrollers and is useful for testing but not expected to be used
> as a production device.
>
> With all the Cortex-M based products gone, there is no longer a need
> for a reference platform either, so remove it as well.
>
> Cc: Liviu Dudau <liviu.dudau@arm.com>
> Cc: Sudeep Holla <sudeep.holla@kernel.org>
> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Cc: Linus Walleij <linusw@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Andi Shyti <andi.shyti@kernel.org>
> Cc: Ethan Nelson-Moore <enelsonmoore@gmail.com>
> Cc: devicetree@vger.kernel.org
> Cc: linux-i2c@vger.kernel.org
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linusw@kernel.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 11/13] ARM: versatile: remove mps2 support
2026-09-08 15:28 ` [PATCH 11/13] ARM: versatile: remove mps2 support Arnd Bergmann
2026-09-08 15:41 ` Vladimir Murzin
2026-09-08 17:37 ` Linus Walleij
@ 2026-09-08 19:49 ` Sudeep Holla
2026-09-08 19:51 ` Arnd Bergmann
2026-09-08 19:54 ` Sudeep Holla
2 siblings, 2 replies; 70+ messages in thread
From: Sudeep Holla @ 2026-09-08 19:49 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Sudeep Holla, Alexandre Belloni,
Linus Walleij, Russell King, Drew Fustini, Arnd Bergmann,
Rob Herring, Conor Dooley, Liviu Dudau, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski,
Andi Shyti, linux-i2c
On Tue, Sep 08, 2026 at 05:28:01PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The Arm mps2 platform is the reference implementation for Arm
> microcontrollers and is useful for testing but not expected to be used
> as a production device.
>
> With all the Cortex-M based products gone, there is no longer a need
> for a reference platform either, so remove it as well.
>
> Cc: Liviu Dudau <liviu.dudau@arm.com>
> Cc: Sudeep Holla <sudeep.holla@kernel.org>
Acked-by: Sudeep Holla <sudeep.holla@kernel.org>
While at it, should we also remove
drivers/tty/serial/mps2-uart.c and related Makefile/Kconfig entries ?
--
Regards,
Sudeep
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 11/13] ARM: versatile: remove mps2 support
2026-09-08 19:49 ` Sudeep Holla
@ 2026-09-08 19:51 ` Arnd Bergmann
2026-09-08 19:58 ` Sudeep Holla
2026-09-08 19:54 ` Sudeep Holla
1 sibling, 1 reply; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 19:51 UTC (permalink / raw)
To: Sudeep Holla, Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Rob Herring, Conor Dooley,
Liviu Dudau, Lorenzo Pieralisi, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Vladimir Zapolskiy,
Stefan Agner, Maxime Coquelin, Alexandre Torgue, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Nicolas Ferre, Claudiu Beznea, Andrew Lunn,
Sebastian Hesselbarth, Gregory Clement, Robert Jarzmik,
Kristoffer Ericson, Ethan Nelson-Moore, Geert Uytterhoeven,
A. Sverdlin, Shawn Guo, Karl Mehltretter,
David Hildenbrand (Red Hat),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, Linux-OMAP, Krzysztof Kozlowski,
Andi Shyti, linux-i2c
On Tue, Sep 8, 2026, at 21:49, Sudeep Holla wrote:
> On Tue, Sep 08, 2026 at 05:28:01PM +0200, Arnd Bergmann wrote:
>> From: Arnd Bergmann <arnd@arndb.de>
>>
>> The Arm mps2 platform is the reference implementation for Arm
>> microcontrollers and is useful for testing but not expected to be used
>> as a production device.
>>
>> With all the Cortex-M based products gone, there is no longer a need
>> for a reference platform either, so remove it as well.
>>
>> Cc: Liviu Dudau <liviu.dudau@arm.com>
>> Cc: Sudeep Holla <sudeep.holla@kernel.org>
>
> Acked-by: Sudeep Holla <sudeep.holla@kernel.org>
Thanks!
> While at it, should we also remove
>
> drivers/tty/serial/mps2-uart.c and related Makefile/Kconfig entries ?
Yes, I have a patch for that in
https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/log/?h=board-remove-7.3 and will post that once this series has progressed enough.
Arnd
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 11/13] ARM: versatile: remove mps2 support
2026-09-08 19:51 ` Arnd Bergmann
@ 2026-09-08 19:58 ` Sudeep Holla
0 siblings, 0 replies; 70+ messages in thread
From: Sudeep Holla @ 2026-09-08 19:58 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Arnd Bergmann, Krzysztof Kozlowski, Alexandre Belloni,
Sudeep Holla, Linus Walleij, Russell King, Drew Fustini,
Rob Herring, Conor Dooley, Liviu Dudau, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, A. Sverdlin, Shawn Guo, Karl Mehltretter,
David Hildenbrand (Red Hat),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, Linux-OMAP, Krzysztof Kozlowski,
Andi Shyti, linux-i2c
On Tue, Sep 08, 2026 at 09:51:22PM +0200, Arnd Bergmann wrote:
> On Tue, Sep 8, 2026, at 21:49, Sudeep Holla wrote:
> > On Tue, Sep 08, 2026 at 05:28:01PM +0200, Arnd Bergmann wrote:
> >> From: Arnd Bergmann <arnd@arndb.de>
> >>
> >> The Arm mps2 platform is the reference implementation for Arm
> >> microcontrollers and is useful for testing but not expected to be used
> >> as a production device.
> >>
> >> With all the Cortex-M based products gone, there is no longer a need
> >> for a reference platform either, so remove it as well.
> >>
> >> Cc: Liviu Dudau <liviu.dudau@arm.com>
> >> Cc: Sudeep Holla <sudeep.holla@kernel.org>
> >
> > Acked-by: Sudeep Holla <sudeep.holla@kernel.org>
>
> Thanks!
>
> > While at it, should we also remove
> >
> > drivers/tty/serial/mps2-uart.c and related Makefile/Kconfig entries ?
>
> Yes, I have a patch for that in
> https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/log/?h=board-remove-7.3 and will post that once this series has progressed enough.
>
Ah ok, then discard my followup message. I assume you would have the timer
driver as well. Thanks for the deprecation.
--
Regards,
Sudeep
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 11/13] ARM: versatile: remove mps2 support
2026-09-08 19:49 ` Sudeep Holla
2026-09-08 19:51 ` Arnd Bergmann
@ 2026-09-08 19:54 ` Sudeep Holla
1 sibling, 0 replies; 70+ messages in thread
From: Sudeep Holla @ 2026-09-08 19:54 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Sudeep Holla,
Linus Walleij, Russell King, Drew Fustini, Arnd Bergmann,
Rob Herring, Conor Dooley, Liviu Dudau, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Krzysztof Kozlowski,
Andi Shyti, linux-i2c
On Tue, Sep 08, 2026 at 08:49:09PM +0100, Sudeep Holla wrote:
> On Tue, Sep 08, 2026 at 05:28:01PM +0200, Arnd Bergmann wrote:
> > From: Arnd Bergmann <arnd@arndb.de>
> >
> > The Arm mps2 platform is the reference implementation for Arm
> > microcontrollers and is useful for testing but not expected to be used
> > as a production device.
> >
> > With all the Cortex-M based products gone, there is no longer a need
> > for a reference platform either, so remove it as well.
> >
> > Cc: Liviu Dudau <liviu.dudau@arm.com>
> > Cc: Sudeep Holla <sudeep.holla@kernel.org>
>
> Acked-by: Sudeep Holla <sudeep.holla@kernel.org>
>
> While at it, should we also remove
>
> drivers/tty/serial/mps2-uart.c and related Makefile/Kconfig entries ?
>
My initial search was incomplete(used _MPS2_ instead of _MPS2).
We also have timer/clocksource driver:
drivers/clocksource/mps2-timer.c
--
Regards,
Sudeep
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH 12/13] ARM: at91: remove samv7 support
2026-09-08 15:27 [PATCH 00/13] ARM: deprecated platform removal Arnd Bergmann
` (10 preceding siblings ...)
2026-09-08 15:28 ` [PATCH 11/13] ARM: versatile: remove mps2 support Arnd Bergmann
@ 2026-09-08 15:28 ` Arnd Bergmann
2026-09-08 17:39 ` Linus Walleij
` (4 more replies)
2026-09-08 15:28 ` [PATCH 13/13] ARM: axxia: remove entire platform Arnd Bergmann
2026-09-08 16:53 ` [PATCH 00/13] ARM: deprecated platform removal Randy Dunlap
13 siblings, 5 replies; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 15:28 UTC (permalink / raw)
To: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap
From: Arnd Bergmann <arnd@arndb.de>
The Atmel at91 line, now known as Microchip SAM contains both
SoCs using ARM926 and Cortex-A CPUs as well as a number of
microcontrollers. Only a single one of those MCUs currently
has Linux support, and has no known users.
The samv7 platform was deprecated in Linux-7.3LTS, which will
remain supported a while longer after it is gone from mainline.
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/Kconfig.debug | 10 ----------
arch/arm/mach-at91/Kconfig | 11 +----------
arch/arm/mach-at91/Makefile | 1 -
arch/arm/mach-at91/samv7.c | 17 -----------------
drivers/soc/atmel/soc.c | 36 ------------------------------------
5 files changed, 1 insertion(+), 74 deletions(-)
delete mode 100644 arch/arm/mach-at91/samv7.c
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 3d5f2e41eef1..b27e581a53d4 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -190,15 +190,6 @@ choice
Say Y here if you want kernel low-level debugging support
on the USART3 port of sama5d4.
- config DEBUG_AT91_SAMV7_USART1
- bool "Kernel low-level debugging via SAMV7 USART1"
- select DEBUG_AT91_UART
- depends on SOC_SAMV7
- help
- Say Y here if you want the debug print routines to direct
- their output to the USART1 port on SAMV7 based
- machines.
-
config DEBUG_AT91_SAMA7G5_FLEXCOM3
bool "Kernel low-level debugging on SAMA7G5 FLEXCOM3"
select DEBUG_AT91_UART
@@ -1504,7 +1495,6 @@ config DEBUG_UART_PHYS
default 0x3e000000 if DEBUG_BCM_KONA_UART
default 0x3f201000 if DEBUG_BCM2836
default 0x40010000 if STM32MP1_DEBUG_UART
- default 0x40028000 if DEBUG_AT91_SAMV7_USART1
default 0x40090000 if DEBUG_LPC32XX
default 0x40100000 if DEBUG_PXA_UART1
default 0x42000000 if DEBUG_GEMINI
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index cb0e3ff8e0ca..3df1165d159b 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -5,7 +5,7 @@ config ARCH_MICROCHIP
menuconfig ARCH_AT91
bool "AT91/Microchip SoCs"
depends on (CPU_LITTLE_ENDIAN && (ARCH_MULTI_V4T || ARCH_MULTI_V5)) || \
- ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
+ ARCH_MULTI_V7
select ARM_CPU_SUSPEND if PM && ARCH_MULTI_V7
select COMMON_CLK_AT91
select GPIOLIB
@@ -14,15 +14,6 @@ menuconfig ARCH_AT91
select ARCH_MICROCHIP
if ARCH_AT91
-config SOC_SAMV7
- bool "SAM Cortex-M7 family (DEPRECATED)" if ARM_SINGLE_ARMV7M
- select COMMON_CLK_AT91
- select PINCTRL_AT91
- help
- Select this if you are using an SoC from Microchip's SAME7, SAMS7 or SAMV7
- families.
-
- This platform is scheduled for removal in early 2027
config SOC_SAMA5D2
bool "SAMA5D2 family"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 7d8a7bc44e65..8c964e182284 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -10,7 +10,6 @@ obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o
obj-$(CONFIG_SOC_SAM9X7) += sam9x7.o
obj-$(CONFIG_SOC_SAMA5) += sama5.o sam_secure.o
obj-$(CONFIG_SOC_SAMA7) += sama7.o
-obj-$(CONFIG_SOC_SAMV7) += samv7.o
# Power Management
obj-$(CONFIG_ATMEL_PM) += pm.o pm_suspend.o
diff --git a/arch/arm/mach-at91/samv7.c b/arch/arm/mach-at91/samv7.c
deleted file mode 100644
index 22d00005ec09..000000000000
--- a/arch/arm/mach-at91/samv7.c
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Setup code for SAMv7x
- *
- * Copyright (C) 2013 Atmel,
- * 2016 Andras Szemzo <szemzo.andras@gmail.com>
- */
-#include <asm/mach/arch.h>
-
-static const char *const samv7_dt_board_compat[] __initconst = {
- "atmel,samv7",
- NULL
-};
-
-DT_MACHINE_START(samv7_dt, "Atmel SAMV7")
- .dt_compat = samv7_dt_board_compat,
-MACHINE_END
diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
index d89f9dcade7d..e276f86326ec 100644
--- a/drivers/soc/atmel/soc.c
+++ b/drivers/soc/atmel/soc.c
@@ -210,41 +210,6 @@ static const struct at91_soc socs[] __initconst = {
AT91_CIDR_VERSION_MASK, SAMA5D44_EXID_MATCH,
"sama5d44", "sama5d4"),
#endif
-#ifdef CONFIG_SOC_SAMV7
- AT91_SOC(SAME70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
- AT91_CIDR_VERSION_MASK, SAME70Q21_EXID_MATCH,
- "same70q21", "same7"),
- AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
- AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH,
- "same70q20", "same7"),
- AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
- AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH,
- "same70q19", "same7"),
- AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
- AT91_CIDR_VERSION_MASK, SAMS70Q21_EXID_MATCH,
- "sams70q21", "sams7"),
- AT91_SOC(SAMS70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
- AT91_CIDR_VERSION_MASK, SAMS70Q20_EXID_MATCH,
- "sams70q20", "sams7"),
- AT91_SOC(SAMS70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
- AT91_CIDR_VERSION_MASK, SAMS70Q19_EXID_MATCH,
- "sams70q19", "sams7"),
- AT91_SOC(SAMV71Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
- AT91_CIDR_VERSION_MASK, SAMV71Q21_EXID_MATCH,
- "samv71q21", "samv7"),
- AT91_SOC(SAMV71Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
- AT91_CIDR_VERSION_MASK, SAMV71Q20_EXID_MATCH,
- "samv71q20", "samv7"),
- AT91_SOC(SAMV71Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
- AT91_CIDR_VERSION_MASK, SAMV71Q19_EXID_MATCH,
- "samv71q19", "samv7"),
- AT91_SOC(SAMV70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
- AT91_CIDR_VERSION_MASK, SAMV70Q20_EXID_MATCH,
- "samv70q20", "samv7"),
- AT91_SOC(SAMV70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
- AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH,
- "samv70q19", "samv7"),
-#endif
#ifdef CONFIG_SOC_SAMA7
AT91_SOC(SAMA7D65_CIDR_MATCH, AT91_CIDR_MASK_SAMA7G5,
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7D65_EXID_MATCH,
@@ -396,7 +361,6 @@ static const struct of_device_id at91_soc_allowed_list[] __initconst = {
{ .compatible = "atmel,at91rm9200", },
{ .compatible = "atmel,at91sam9", },
{ .compatible = "atmel,sama5", },
- { .compatible = "atmel,samv7", },
{ .compatible = "microchip,sama7d65", },
{ .compatible = "microchip,sama7g5", },
{ }
--
2.53.0
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 12/13] ARM: at91: remove samv7 support
2026-09-08 15:28 ` [PATCH 12/13] ARM: at91: remove samv7 support Arnd Bergmann
@ 2026-09-08 17:39 ` Linus Walleij
2026-09-08 19:58 ` Sverdlin, Alexander
` (3 subsequent siblings)
4 siblings, 0 replies; 70+ messages in thread
From: Linus Walleij @ 2026-09-08 17:39 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Russell King,
Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap
On Tue, Sep 8, 2026 at 5:30 PM Arnd Bergmann <arnd@kernel.org> wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The Atmel at91 line, now known as Microchip SAM contains both
> SoCs using ARM926 and Cortex-A CPUs as well as a number of
> microcontrollers. Only a single one of those MCUs currently
> has Linux support, and has no known users.
>
> The samv7 platform was deprecated in Linux-7.3LTS, which will
> remain supported a while longer after it is gone from mainline.
>
> Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Cc: Claudiu Beznea <claudiu.beznea@tuxon.dev>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linusw@kernel.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 12/13] ARM: at91: remove samv7 support
2026-09-08 15:28 ` [PATCH 12/13] ARM: at91: remove samv7 support Arnd Bergmann
2026-09-08 17:39 ` Linus Walleij
@ 2026-09-08 19:58 ` Sverdlin, Alexander
2026-09-08 21:09 ` Rob Herring
` (2 subsequent siblings)
4 siblings, 0 replies; 70+ messages in thread
From: Sverdlin, Alexander @ 2026-09-08 19:58 UTC (permalink / raw)
To: arnd; +Cc: linux-arm-kernel, linux-kernel, arnd
On Tue, 2026-09-08 at 17:28 +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The Atmel at91 line, now known as Microchip SAM contains both
> SoCs using ARM926 and Cortex-A CPUs as well as a number of
> microcontrollers. Only a single one of those MCUs currently
> has Linux support, and has no known users.
>
> The samv7 platform was deprecated in Linux-7.3LTS, which will
> remain supported a while longer after it is gone from mainline.
>
> Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Cc: Claudiu Beznea <claudiu.beznea@tuxon.dev>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
> ---
> arch/arm/Kconfig.debug | 10 ----------
> arch/arm/mach-at91/Kconfig | 11 +----------
> arch/arm/mach-at91/Makefile | 1 -
> arch/arm/mach-at91/samv7.c | 17 -----------------
> drivers/soc/atmel/soc.c | 36 ------------------------------------
> 5 files changed, 1 insertion(+), 74 deletions(-)
> delete mode 100644 arch/arm/mach-at91/samv7.c
--
Alexander Sverdlin
Siemens AG
www.siemens.com
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 12/13] ARM: at91: remove samv7 support
2026-09-08 15:28 ` [PATCH 12/13] ARM: at91: remove samv7 support Arnd Bergmann
2026-09-08 17:39 ` Linus Walleij
2026-09-08 19:58 ` Sverdlin, Alexander
@ 2026-09-08 21:09 ` Rob Herring
2026-09-08 21:30 ` Arnd Bergmann
2026-09-09 12:41 ` Alexandre Belloni
2026-09-10 12:23 ` Nicolas Ferre
4 siblings, 1 reply; 70+ messages in thread
From: Rob Herring @ 2026-09-08 21:09 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Arnd Bergmann, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap
On Tue, Sep 08, 2026 at 05:28:02PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The Atmel at91 line, now known as Microchip SAM contains both
> SoCs using ARM926 and Cortex-A CPUs as well as a number of
> microcontrollers. Only a single one of those MCUs currently
> has Linux support, and has no known users.
>
> The samv7 platform was deprecated in Linux-7.3LTS, which will
> remain supported a while longer after it is gone from mainline.
>
> Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Cc: Claudiu Beznea <claudiu.beznea@tuxon.dev>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> arch/arm/Kconfig.debug | 10 ----------
> arch/arm/mach-at91/Kconfig | 11 +----------
> arch/arm/mach-at91/Makefile | 1 -
> arch/arm/mach-at91/samv7.c | 17 -----------------
> drivers/soc/atmel/soc.c | 36 ------------------------------------
> 5 files changed, 1 insertion(+), 74 deletions(-)
> delete mode 100644 arch/arm/mach-at91/samv7.c
Do you want to drop all the samv7 platform compatibles from at91.yaml?
Are there non-Linux users using DT?
Rob
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 12/13] ARM: at91: remove samv7 support
2026-09-08 21:09 ` Rob Herring
@ 2026-09-08 21:30 ` Arnd Bergmann
2026-09-10 12:25 ` Nicolas Ferre
0 siblings, 1 reply; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 21:30 UTC (permalink / raw)
To: Rob Herring, Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Conor Dooley, Liviu Dudau,
Sudeep Holla, Lorenzo Pieralisi, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Vladimir Zapolskiy,
Stefan Agner, Maxime Coquelin, Alexandre Torgue, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Nicolas Ferre, Claudiu Beznea, Andrew Lunn,
Sebastian Hesselbarth, Gregory Clement, Robert Jarzmik,
Kristoffer Ericson, Ethan Nelson-Moore, Geert Uytterhoeven,
A. Sverdlin, Shawn Guo, Karl Mehltretter,
David Hildenbrand (Red Hat),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, Linux-OMAP
On Tue, Sep 8, 2026, at 23:09, Rob Herring wrote:
>
> Do you want to drop all the samv7 platform compatibles from at91.yaml?
> Are there non-Linux users using DT?
I see that zephyr uses DT here, but it uses an incompatible
set of bindings, see
https://github.com/zephyrproject-rtos/zephyr/tree/main/dts/arm/atmel
I'm dropping the references from the binding now, and also from
Documentation/arch/arm/microchip.rst, which I had missed earlier.
Arnd
diff --git a/Documentation/arch/arm/microchip.rst b/Documentation/arch/arm/microchip.rst
index e721d855f2c9..b776a6656717 100644
--- a/Documentation/arch/arm/microchip.rst
+++ b/Documentation/arch/arm/microchip.rst
@@ -157,45 +157,6 @@ the Microchip website: http://www.microchip.com.
Coming soon
- * ARM Cortex-M7 MCUs
- - sams70 family
-
- - sams70j19
- - sams70j20
- - sams70j21
- - sams70n19
- - sams70n20
- - sams70n21
- - sams70q19
- - sams70q20
- - sams70q21
-
- - samv70 family
-
- - samv70j19
- - samv70j20
- - samv70n19
- - samv70n20
- - samv70q19
- - samv70q20
-
- - samv71 family
-
- - samv71j19
- - samv71j20
- - samv71j21
- - samv71n19
- - samv71n20
- - samv71n21
- - samv71q19
- - samv71q20
- - samv71q21
-
- * Datasheet
-
- http://ww1.microchip.com/downloads/en/DeviceDoc/SAM-E70-S70-V70-V71-Family-Data-Sheet-DS60001527D.pdf
-
-
Linux kernel information
------------------------
Linux kernel mach directory: arch/arm/mach-at91
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
index bf161e0950ea..d9b32a95b136 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
@@ -258,45 +258,6 @@ properties:
- const: microchip,lan9668
- const: microchip,lan966
- - items:
- - enum:
- - atmel,sams70j19
- - atmel,sams70j20
- - atmel,sams70j21
- - atmel,sams70n19
- - atmel,sams70n20
- - atmel,sams70n21
- - atmel,sams70q19
- - atmel,sams70q20
- - atmel,sams70q21
- - const: atmel,sams70
- - const: atmel,samv7
-
- - items:
- - enum:
- - atmel,samv70j19
- - atmel,samv70j20
- - atmel,samv70n19
- - atmel,samv70n20
- - atmel,samv70q19
- - atmel,samv70q20
- - const: atmel,samv70
- - const: atmel,samv7
-
- - items:
- - enum:
- - atmel,samv71j19
- - atmel,samv71j20
- - atmel,samv71j21
- - atmel,samv71n19
- - atmel,samv71n20
- - atmel,samv71n21
- - atmel,samv71q19
- - atmel,samv71q20
- - atmel,samv71q21
- - const: atmel,samv71
- - const: atmel,samv7
-
additionalProperties: true
...
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 12/13] ARM: at91: remove samv7 support
2026-09-08 21:30 ` Arnd Bergmann
@ 2026-09-10 12:25 ` Nicolas Ferre
0 siblings, 0 replies; 70+ messages in thread
From: Nicolas Ferre @ 2026-09-10 12:25 UTC (permalink / raw)
To: Arnd Bergmann, Rob Herring, Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij,
Russell King, Drew Fustini, Conor Dooley, Liviu Dudau,
Sudeep Holla, Lorenzo Pieralisi, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Vladimir Zapolskiy,
Stefan Agner, Maxime Coquelin, Alexandre Torgue, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Claudiu Beznea, Andrew Lunn, Sebastian Hesselbarth,
Gregory Clement, Robert Jarzmik, Kristoffer Ericson,
Ethan Nelson-Moore, Geert Uytterhoeven, A. Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Red Hat),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, Linux-OMAP
On 08/09/2026 at 23:30, Arnd Bergmann wrote:
> On Tue, Sep 8, 2026, at 23:09, Rob Herring wrote:
>>
>> Do you want to drop all the samv7 platform compatibles from at91.yaml?
>> Are there non-Linux users using DT?
>
> I see that zephyr uses DT here, but it uses an incompatible
> set of bindings, see
> https://github.com/zephyrproject-rtos/zephyr/tree/main/dts/arm/atmel
>
> I'm dropping the references from the binding now, and also from
> Documentation/arch/arm/microchip.rst, which I had missed earlier.
Very good, thanks for having handling that Arnd.
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Best regards,
Nicolas
> diff --git a/Documentation/arch/arm/microchip.rst b/Documentation/arch/arm/microchip.rst
> index e721d855f2c9..b776a6656717 100644
> --- a/Documentation/arch/arm/microchip.rst
> +++ b/Documentation/arch/arm/microchip.rst
> @@ -157,45 +157,6 @@ the Microchip website: http://www.microchip.com.
>
> Coming soon
>
> - * ARM Cortex-M7 MCUs
> - - sams70 family
> -
> - - sams70j19
> - - sams70j20
> - - sams70j21
> - - sams70n19
> - - sams70n20
> - - sams70n21
> - - sams70q19
> - - sams70q20
> - - sams70q21
> -
> - - samv70 family
> -
> - - samv70j19
> - - samv70j20
> - - samv70n19
> - - samv70n20
> - - samv70q19
> - - samv70q20
> -
> - - samv71 family
> -
> - - samv71j19
> - - samv71j20
> - - samv71j21
> - - samv71n19
> - - samv71n20
> - - samv71n21
> - - samv71q19
> - - samv71q20
> - - samv71q21
> -
> - * Datasheet
> -
> - http://ww1.microchip.com/downloads/en/DeviceDoc/SAM-E70-S70-V70-V71-Family-Data-Sheet-DS60001527D.pdf
> -
> -
> Linux kernel information
> ------------------------
> Linux kernel mach directory: arch/arm/mach-at91
> diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
> index bf161e0950ea..d9b32a95b136 100644
> --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml
> +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
> @@ -258,45 +258,6 @@ properties:
> - const: microchip,lan9668
> - const: microchip,lan966
>
> - - items:
> - - enum:
> - - atmel,sams70j19
> - - atmel,sams70j20
> - - atmel,sams70j21
> - - atmel,sams70n19
> - - atmel,sams70n20
> - - atmel,sams70n21
> - - atmel,sams70q19
> - - atmel,sams70q20
> - - atmel,sams70q21
> - - const: atmel,sams70
> - - const: atmel,samv7
> -
> - - items:
> - - enum:
> - - atmel,samv70j19
> - - atmel,samv70j20
> - - atmel,samv70n19
> - - atmel,samv70n20
> - - atmel,samv70q19
> - - atmel,samv70q20
> - - const: atmel,samv70
> - - const: atmel,samv7
> -
> - - items:
> - - enum:
> - - atmel,samv71j19
> - - atmel,samv71j20
> - - atmel,samv71j21
> - - atmel,samv71n19
> - - atmel,samv71n20
> - - atmel,samv71n21
> - - atmel,samv71q19
> - - atmel,samv71q20
> - - atmel,samv71q21
> - - const: atmel,samv71
> - - const: atmel,samv7
> -
> additionalProperties: true
>
> ...
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 12/13] ARM: at91: remove samv7 support
2026-09-08 15:28 ` [PATCH 12/13] ARM: at91: remove samv7 support Arnd Bergmann
` (2 preceding siblings ...)
2026-09-08 21:09 ` Rob Herring
@ 2026-09-09 12:41 ` Alexandre Belloni
2026-09-10 12:23 ` Nicolas Ferre
4 siblings, 0 replies; 70+ messages in thread
From: Alexandre Belloni @ 2026-09-09 12:41 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Linus Walleij, Russell King, Drew Fustini,
Arnd Bergmann, Rob Herring, Conor Dooley, Liviu Dudau,
Sudeep Holla, Lorenzo Pieralisi, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Vladimir Zapolskiy,
Stefan Agner, Maxime Coquelin, Alexandre Torgue, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Nicolas Ferre, Claudiu Beznea, Andrew Lunn,
Sebastian Hesselbarth, Gregory Clement, Robert Jarzmik,
Kristoffer Ericson, Ethan Nelson-Moore, Geert Uytterhoeven,
Alexander Sverdlin, Shawn Guo, Karl Mehltretter,
David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap
On 08/09/2026 17:28:02+0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The Atmel at91 line, now known as Microchip SAM contains both
> SoCs using ARM926 and Cortex-A CPUs as well as a number of
> microcontrollers. Only a single one of those MCUs currently
> has Linux support, and has no known users.
>
> The samv7 platform was deprecated in Linux-7.3LTS, which will
> remain supported a while longer after it is gone from mainline.
>
> Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Cc: Claudiu Beznea <claudiu.beznea@tuxon.dev>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 12/13] ARM: at91: remove samv7 support
2026-09-08 15:28 ` [PATCH 12/13] ARM: at91: remove samv7 support Arnd Bergmann
` (3 preceding siblings ...)
2026-09-09 12:41 ` Alexandre Belloni
@ 2026-09-10 12:23 ` Nicolas Ferre
4 siblings, 0 replies; 70+ messages in thread
From: Nicolas Ferre @ 2026-09-10 12:23 UTC (permalink / raw)
To: Arnd Bergmann, Krzysztof Kozlowski, Alexandre Belloni,
Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Claudiu Beznea, Andrew Lunn,
Sebastian Hesselbarth, Gregory Clement, Robert Jarzmik,
Kristoffer Ericson, Ethan Nelson-Moore, Geert Uytterhoeven,
Alexander Sverdlin, Shawn Guo, Karl Mehltretter,
David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap
On 08/09/2026 at 17:28, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The Atmel at91 line, now known as Microchip SAM contains both
> SoCs using ARM926 and Cortex-A CPUs as well as a number of
> microcontrollers. Only a single one of those MCUs currently
> has Linux support, and has no known users.
>
> The samv7 platform was deprecated in Linux-7.3LTS, which will
> remain supported a while longer after it is gone from mainline.
>
> Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Regards,
Nicolas
> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Cc: Claudiu Beznea <claudiu.beznea@tuxon.dev>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> arch/arm/Kconfig.debug | 10 ----------
> arch/arm/mach-at91/Kconfig | 11 +----------
> arch/arm/mach-at91/Makefile | 1 -
> arch/arm/mach-at91/samv7.c | 17 -----------------
> drivers/soc/atmel/soc.c | 36 ------------------------------------
> 5 files changed, 1 insertion(+), 74 deletions(-)
> delete mode 100644 arch/arm/mach-at91/samv7.c
[..]
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH 13/13] ARM: axxia: remove entire platform
2026-09-08 15:27 [PATCH 00/13] ARM: deprecated platform removal Arnd Bergmann
` (11 preceding siblings ...)
2026-09-08 15:28 ` [PATCH 12/13] ARM: at91: remove samv7 support Arnd Bergmann
@ 2026-09-08 15:28 ` Arnd Bergmann
2026-09-08 17:40 ` Linus Walleij
` (2 more replies)
2026-09-08 16:53 ` [PATCH 00/13] ARM: deprecated platform removal Randy Dunlap
13 siblings, 3 replies; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 15:28 UTC (permalink / raw)
To: Krzysztof Kozlowski, Alexandre Belloni, Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Anders Berg
From: Arnd Bergmann <arnd@arndb.de>
The initial Axxia port was contributed by LSI in 2014, but never completed
after the sale of the business unit to Intel, which kept supporting the
bulk of the drivers in their own downstream BSP.
The downstream work has also ended now, and there is no realistic chance
that anyone would rewrite it all into an upstreamable port.
Remove it now that the 7.3LTS release is out and can be used as the
base for one more downstream rebase of the downstream patches if needed.
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Cc: Ethan Nelson-Moore <enelsonmoore@gmail.com>
Cc: Anders Berg <anders.berg@lsi.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
.../devicetree/bindings/arm/axxia.yaml | 23 --
MAINTAINERS | 8 -
arch/arm/Kconfig | 2 -
arch/arm/Makefile | 2 -
arch/arm/boot/dts/intel/Makefile | 1 -
arch/arm/boot/dts/intel/axm/Makefile | 5 -
.../boot/dts/intel/axm/axm5516-amarillo.dts | 47 ----
arch/arm/boot/dts/intel/axm/axm5516-cpus.dtsi | 200 ---------------
arch/arm/boot/dts/intel/axm/axm55xx.dtsi | 200 ---------------
arch/arm/configs/axm55xx_defconfig | 231 ------------------
arch/arm/mach-axxia/Kconfig | 17 --
arch/arm/mach-axxia/Makefile | 3 -
arch/arm/mach-axxia/axxia.c | 19 --
arch/arm/mach-axxia/platsmp.c | 87 -------
14 files changed, 845 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/axxia.yaml
delete mode 100644 arch/arm/boot/dts/intel/axm/Makefile
delete mode 100644 arch/arm/boot/dts/intel/axm/axm5516-amarillo.dts
delete mode 100644 arch/arm/boot/dts/intel/axm/axm5516-cpus.dtsi
delete mode 100644 arch/arm/boot/dts/intel/axm/axm55xx.dtsi
delete mode 100644 arch/arm/configs/axm55xx_defconfig
delete mode 100644 arch/arm/mach-axxia/Kconfig
delete mode 100644 arch/arm/mach-axxia/Makefile
delete mode 100644 arch/arm/mach-axxia/axxia.c
delete mode 100644 arch/arm/mach-axxia/platsmp.c
diff --git a/Documentation/devicetree/bindings/arm/axxia.yaml b/Documentation/devicetree/bindings/arm/axxia.yaml
deleted file mode 100644
index d60907e43efc..000000000000
--- a/Documentation/devicetree/bindings/arm/axxia.yaml
+++ /dev/null
@@ -1,23 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/arm/axxia.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Axxia AXM55xx
-
-maintainers:
- - Anders Berg <anders.berg@lsi.com>
-
-properties:
- $nodename:
- const: "/"
- compatible:
- description: LSI AXM5516 Validation board (Amarillo)
- items:
- - const: lsi,axm5516-amarillo
- - const: lsi,axm5516
-
-additionalProperties: true
-
-...
diff --git a/MAINTAINERS b/MAINTAINERS
index 292327185a08..74657b35c577 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2742,14 +2742,6 @@ F: Documentation/devicetree/bindings/arm/axiado.yaml
F: arch/arm64/boot/dts/axiado/
N: axiado
-ARM/AXM LSI SOC
-M: Krzysztof Kozlowski <krzk@kernel.org>
-L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-S: Odd Fixes
-F: Documentation/devicetree/bindings/arm/axxia.yaml
-F: arch/arm/boot/dts/intel/axm/
-F: arch/arm/mach-axxia/
-
ARM/BITMAIN ARCHITECTURE
M: Manivannan Sadhasivam <mani@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cf380b686867..760c4bfcc33a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -353,8 +353,6 @@ source "arch/arm/mach-aspeed/Kconfig"
source "arch/arm/mach-at91/Kconfig"
-source "arch/arm/mach-axxia/Kconfig"
-
source "arch/arm/mach-bcm/Kconfig"
source "arch/arm/mach-berlin/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index d3479e374c6f..f41b3f6ab82e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -164,7 +164,6 @@ textofs-y := 0x00008000
textofs-$(CONFIG_ARCH_REALTEK) := 0x00108000
textofs-$(CONFIG_ARCH_QCOM_RESERVE_SMEM) := 0x00208000
textofs-$(CONFIG_ARCH_MESON) := 0x00208000
-textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
@@ -173,7 +172,6 @@ machine-$(CONFIG_ARCH_ALPINE) += alpine
machine-$(CONFIG_ARCH_ARTPEC) += artpec
machine-$(CONFIG_ARCH_ASPEED) += aspeed
machine-$(CONFIG_ARCH_AT91) += at91
-machine-$(CONFIG_ARCH_AXXIA) += axxia
machine-$(CONFIG_ARCH_BCM) += bcm
machine-$(CONFIG_ARCH_BERLIN) += berlin
machine-$(CONFIG_ARCH_CLPS711X) += clps711x
diff --git a/arch/arm/boot/dts/intel/Makefile b/arch/arm/boot/dts/intel/Makefile
index c5fc845deb61..3e871d10b7f5 100644
--- a/arch/arm/boot/dts/intel/Makefile
+++ b/arch/arm/boot/dts/intel/Makefile
@@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-subdir-y += axm
subdir-y += ixp
subdir-y += pxa
subdir-y += socfpga
diff --git a/arch/arm/boot/dts/intel/axm/Makefile b/arch/arm/boot/dts/intel/axm/Makefile
deleted file mode 100644
index 7c7dc679964d..000000000000
--- a/arch/arm/boot/dts/intel/axm/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_ARCH_AXXIA) += \
- axm5516-amarillo.dtb
-dtb-$(CONFIG_ARCH_AXXIA) += \
- axm5516-amarillo.dtb
diff --git a/arch/arm/boot/dts/intel/axm/axm5516-amarillo.dts b/arch/arm/boot/dts/intel/axm/axm5516-amarillo.dts
deleted file mode 100644
index 2e2ad3c7ee77..000000000000
--- a/arch/arm/boot/dts/intel/axm/axm5516-amarillo.dts
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/boot/dts/axm5516-amarillo.dts
- *
- * Copyright (C) 2013 LSI
- */
-
-/dts-v1/;
-
-/memreserve/ 0x00000000 0x00400000;
-
-#include "axm55xx.dtsi"
-#include "axm5516-cpus.dtsi"
-
-/ {
- model = "Amarillo AXM5516";
- compatible = "lsi,axm5516-amarillo", "lsi,axm5516";
-
- memory {
- device_type = "memory";
- reg = <0 0x00000000 0x02 0x00000000>;
- };
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial1 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&serial3 {
- status = "okay";
-};
-
-&gpio0 {
- status = "okay";
-};
-
-&gpio1 {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/intel/axm/axm5516-cpus.dtsi b/arch/arm/boot/dts/intel/axm/axm5516-cpus.dtsi
deleted file mode 100644
index f13ef80b6637..000000000000
--- a/arch/arm/boot/dts/intel/axm/axm5516-cpus.dtsi
+++ /dev/null
@@ -1,200 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/boot/dts/axm5516-cpus.dtsi
- *
- * Copyright (C) 2013 LSI
- */
-
-/ {
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&CPU0>;
- };
- core1 {
- cpu = <&CPU1>;
- };
- core2 {
- cpu = <&CPU2>;
- };
- core3 {
- cpu = <&CPU3>;
- };
- };
- cluster1 {
- core0 {
- cpu = <&CPU4>;
- };
- core1 {
- cpu = <&CPU5>;
- };
- core2 {
- cpu = <&CPU6>;
- };
- core3 {
- cpu = <&CPU7>;
- };
- };
- cluster2 {
- core0 {
- cpu = <&CPU8>;
- };
- core1 {
- cpu = <&CPU9>;
- };
- core2 {
- cpu = <&CPU10>;
- };
- core3 {
- cpu = <&CPU11>;
- };
- };
- cluster3 {
- core0 {
- cpu = <&CPU12>;
- };
- core1 {
- cpu = <&CPU13>;
- };
- core2 {
- cpu = <&CPU14>;
- };
- core3 {
- cpu = <&CPU15>;
- };
- };
- };
-
- CPU0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x00>;
- clock-frequency = <1400000000>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
-
- CPU1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x01>;
- clock-frequency = <1400000000>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
-
- CPU2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x02>;
- clock-frequency = <1400000000>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
-
- CPU3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x03>;
- clock-frequency = <1400000000>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
-
- CPU4: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x100>;
- clock-frequency = <1400000000>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
-
- CPU5: cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x101>;
- clock-frequency = <1400000000>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
-
- CPU6: cpu@102 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x102>;
- clock-frequency = <1400000000>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
-
- CPU7: cpu@103 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x103>;
- clock-frequency = <1400000000>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
-
- CPU8: cpu@200 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x200>;
- clock-frequency = <1400000000>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
-
- CPU9: cpu@201 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x201>;
- clock-frequency = <1400000000>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
-
- CPU10: cpu@202 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x202>;
- clock-frequency = <1400000000>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
-
- CPU11: cpu@203 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x203>;
- clock-frequency = <1400000000>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
-
- CPU12: cpu@300 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x300>;
- clock-frequency = <1400000000>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
-
- CPU13: cpu@301 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x301>;
- clock-frequency = <1400000000>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
-
- CPU14: cpu@302 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x302>;
- clock-frequency = <1400000000>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
-
- CPU15: cpu@303 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x303>;
- clock-frequency = <1400000000>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
- };
-};
diff --git a/arch/arm/boot/dts/intel/axm/axm55xx.dtsi b/arch/arm/boot/dts/intel/axm/axm55xx.dtsi
deleted file mode 100644
index 5277890cfad2..000000000000
--- a/arch/arm/boot/dts/intel/axm/axm55xx.dtsi
+++ /dev/null
@@ -1,200 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/boot/dts/axm55xx.dtsi
- *
- * Copyright (C) 2013 LSI
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/lsi,axm5516-clks.h>
-
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&gic>;
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
- timer = &timer0;
- };
-
- clocks {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- clk_ref0: clk_ref0 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <125000000>;
- };
-
- clk_ref1: clk_ref1 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <125000000>;
- };
-
- clk_ref2: clk_ref2 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <125000000>;
- };
-
- clks: clock-controller@2010020000 {
- compatible = "lsi,axm5516-clks";
- #clock-cells = <1>;
- reg = <0x20 0x10020000 0 0x20000>;
- };
- };
-
- gic: interrupt-controller@2001001000 {
- compatible = "arm,cortex-a15-gic";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x20 0x01001000 0 0x1000>,
- <0x20 0x01002000 0 0x2000>,
- <0x20 0x01004000 0 0x2000>,
- <0x20 0x01006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
- IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts =
- <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
-
- pmu {
- compatible = "arm,cortex-a15-pmu";
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- soc {
- compatible = "simple-bus";
- device_type = "soc";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&gic>;
- ranges;
-
- syscon: syscon@2010030000 {
- compatible = "lsi,axxia-syscon", "syscon";
- reg = <0x20 0x10030000 0 0x2000>;
- };
-
- reset: reset@2010031000 {
- compatible = "lsi,axm55xx-reset";
- syscon = <&syscon>;
- };
-
- amba {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- serial0: serial@2010080000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x20 0x10080000 0 0x1000>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
-
- serial1: serial@2010081000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x20 0x10081000 0 0x1000>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
-
- serial2: serial@2010082000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x20 0x10082000 0 0x1000>;
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
-
- serial3: serial@2010083000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x20 0x10083000 0 0x1000>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
-
- timer0: timer@2010091000 {
- compatible = "arm,sp804", "arm,primecell";
- reg = <0x20 0x10091000 0 0x1000>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
- clock-names = "apb_pclk";
- status = "okay";
- };
-
- gpio0: gpio@2010092000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x20 0x10092000 0x00 0x1000>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
-
- gpio1: gpio@2010093000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x20 0x10093000 0x00 0x1000>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- };
- };
-};
-
-/*
- Local Variables:
- mode: C
- End:
-*/
diff --git a/arch/arm/configs/axm55xx_defconfig b/arch/arm/configs/axm55xx_defconfig
deleted file mode 100644
index 541e38e2205b..000000000000
--- a/arch/arm/configs/axm55xx_defconfig
+++ /dev/null
@@ -1,231 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_FHANDLE=y
-CONFIG_AUDIT=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_XACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
-# CONFIG_IPC_NS is not set
-# CONFIG_PID_NS is not set
-# CONFIG_NET_NS is not set
-CONFIG_SCHED_AUTOGROUP=y
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_PROFILING=y
-CONFIG_ARCH_AXXIA=y
-CONFIG_ARM_LPAE=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_ARM_ERRATA_430973=y
-CONFIG_ARM_ERRATA_643719=y
-CONFIG_ARM_ERRATA_720789=y
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_ARM_ERRATA_754327=y
-CONFIG_ARM_ERRATA_764369=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_ARM_ERRATA_798181=y
-CONFIG_PCIE_AXXIA=y
-CONFIG_SMP=y
-CONFIG_NR_CPUS=16
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HIGHMEM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-# CONFIG_SUSPEND is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_BINFMT_MISC=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_KSM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_XFRM_SUB_POLICY=y
-CONFIG_XFRM_MIGRATE=y
-CONFIG_XFRM_STATISTICS=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_INET_AH=y
-CONFIG_INET_ESP=y
-CONFIG_INET_IPCOMP=y
-# CONFIG_IPV6 is not set
-CONFIG_NETWORK_PHY_TIMESTAMPING=y
-CONFIG_BRIDGE=y
-# CONFIG_WIRELESS is not set
-CONFIG_PCI=y
-CONFIG_PCI_MSI=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_AFS_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_M25P80=y
-CONFIG_PROC_DEVICETREE=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EEPROM_AT25=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_ATA=y
-CONFIG_PATA_PLATFORM=y
-CONFIG_PATA_OF_PLATFORM=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_TUN=y
-CONFIG_VETH=y
-CONFIG_VIRTIO_NET=y
-# CONFIG_NET_CADENCE is not set
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CIRRUS is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_NET_VENDOR_VIA is not set
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_BROADCOM_PHY=y
-# CONFIG_WLAN is not set
-# CONFIG_MOUSE_PS2_ALPS is not set
-# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
-# CONFIG_MOUSE_PS2_SYNAPTICS is not set
-# CONFIG_MOUSE_PS2_TRACKPOINT is not set
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_AMBAKMI=y
-CONFIG_LEGACY_PTY_COUNT=16
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_VIRTIO_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_AXXIA=y
-CONFIG_SPI=y
-CONFIG_SPI_PL022=y
-CONFIG_DP83640_PHY=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_PL061=y
-CONFIG_GPIO_PCA953X=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_AXXIA=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_SENSORS_ADT7475=y
-CONFIG_SENSORS_JC42=y
-CONFIG_SENSORS_LM75=y
-CONFIG_PMBUS=y
-CONFIG_SENSORS_LTC2978=y
-CONFIG_WATCHDOG=y
-CONFIG_ARM_SP805_WATCHDOG=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KYE=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-CONFIG_USB_EHCI_HCD_AXXIA=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=y
-CONFIG_MMC_ARMMMCI=y
-CONFIG_DMADEVICES=y
-CONFIG_PL330_DMA=y
-CONFIG_VIRT_DRIVERS=y
-CONFIG_VIRTIO_MMIO=y
-CONFIG_MAILBOX=y
-CONFIG_PL320_MBOX=y
-# CONFIG_IOMMU_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT4_FS=y
-CONFIG_AUTOFS_FS=y
-CONFIG_FUSE_FS=y
-CONFIG_CUSE=y
-CONFIG_FSCACHE=y
-CONFIG_FSCACHE_STATS=y
-CONFIG_FSCACHE_HISTOGRAM=y
-CONFIG_FSCACHE_DEBUG=y
-CONFIG_FSCACHE_OBJECT_LIST=y
-CONFIG_CACHEFILES=y
-CONFIG_CACHEFILES_HISTOGRAM=y
-CONFIG_ISO9660_FS=y
-CONFIG_UDF_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_NTFS_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFS_FSCACHE=y
-CONFIG_SUNRPC_DEBUG=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_CRYPTO_XCBC=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-CONFIG_DEBUG_FS=y
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_RCU_CPU_STALL_TIMEOUT=60
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_USER=y
-CONFIG_CRYPTO_GCM=y
-CONFIG_CRYPTO_SHA256=y
diff --git a/arch/arm/mach-axxia/Kconfig b/arch/arm/mach-axxia/Kconfig
deleted file mode 100644
index f773a66c1402..000000000000
--- a/arch/arm/mach-axxia/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config ARCH_AXXIA
- bool "LSI Axxia platforms (DEPRECATED)"
- depends on ARCH_MULTI_V7 && ARM_LPAE
- select ARM_AMBA
- select ARM_GIC
- select ARM_TIMER_SP804
- select HAVE_ARM_ARCH_TIMER
- select MFD_SYSCON
- select ZONE_DMA
- help
- This enables support for the LSI Axxia devices.
-
- The LSI Axxia platforms require a Flattened Device Tree to be passed
- to the kernel.
-
- This platform is scheduled for removal in early 2027
diff --git a/arch/arm/mach-axxia/Makefile b/arch/arm/mach-axxia/Makefile
deleted file mode 100644
index 8df8fe76ad47..000000000000
--- a/arch/arm/mach-axxia/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-obj-y += axxia.o
-obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-axxia/axxia.c b/arch/arm/mach-axxia/axxia.c
deleted file mode 100644
index e21582a7fa11..000000000000
--- a/arch/arm/mach-axxia/axxia.c
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Support for the LSI Axxia SoC devices based on ARM cores.
- *
- * Copyright (C) 2012 LSI
- */
-#include <linux/init.h>
-#include <asm/mach/arch.h>
-
-static const char *const axxia_dt_match[] __initconst = {
- "lsi,axm5516",
- "lsi,axm5516-sim",
- "lsi,axm5516-emu",
- NULL
-};
-
-DT_MACHINE_START(AXXIA_DT, "LSI Axxia AXM55XX")
- .dt_compat = axxia_dt_match,
-MACHINE_END
diff --git a/arch/arm/mach-axxia/platsmp.c b/arch/arm/mach-axxia/platsmp.c
deleted file mode 100644
index 2e203626eda5..000000000000
--- a/arch/arm/mach-axxia/platsmp.c
+++ /dev/null
@@ -1,87 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-axxia/platsmp.c
- *
- * Copyright (C) 2012 LSI Corporation
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/smp.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <asm/cacheflush.h>
-
-/* Syscon register offsets for releasing cores from reset */
-#define SC_CRIT_WRITE_KEY 0x1000
-#define SC_RST_CPU_HOLD 0x1010
-
-/*
- * Write the kernel entry point for secondary CPUs to the specified address
- */
-static void write_release_addr(u32 release_phys)
-{
- u32 *virt = (u32 *) phys_to_virt(release_phys);
- writel_relaxed(__pa_symbol(secondary_startup), virt);
- /* Make sure this store is visible to other CPUs */
- smp_wmb();
- __cpuc_flush_dcache_area(virt, sizeof(u32));
-}
-
-static int axxia_boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
- struct device_node *syscon_np;
- void __iomem *syscon;
- u32 tmp;
-
- syscon_np = of_find_compatible_node(NULL, NULL, "lsi,axxia-syscon");
- if (!syscon_np)
- return -ENOENT;
-
- syscon = of_iomap(syscon_np, 0);
- of_node_put(syscon_np);
- if (!syscon)
- return -ENOMEM;
-
- tmp = readl(syscon + SC_RST_CPU_HOLD);
- writel(0xab, syscon + SC_CRIT_WRITE_KEY);
- tmp &= ~(1 << cpu);
- writel(tmp, syscon + SC_RST_CPU_HOLD);
-
- return 0;
-}
-
-static void __init axxia_smp_prepare_cpus(unsigned int max_cpus)
-{
- int cpu_count = 0;
- int cpu;
-
- /*
- * Initialise the present map, which describes the set of CPUs actually
- * populated at the present time.
- */
- for_each_possible_cpu(cpu) {
- struct device_node *np;
- u32 release_phys;
-
- np = of_get_cpu_node(cpu, NULL);
- if (!np)
- continue;
- if (of_property_read_u32(np, "cpu-release-addr", &release_phys))
- continue;
-
- if (cpu_count < max_cpus) {
- set_cpu_present(cpu, true);
- cpu_count++;
- }
-
- if (release_phys != 0)
- write_release_addr(release_phys);
- }
-}
-
-static const struct smp_operations axxia_smp_ops __initconst = {
- .smp_prepare_cpus = axxia_smp_prepare_cpus,
- .smp_boot_secondary = axxia_boot_secondary,
-};
-CPU_METHOD_OF_DECLARE(axxia_smp, "lsi,syscon-release", &axxia_smp_ops);
--
2.53.0
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 13/13] ARM: axxia: remove entire platform
2026-09-08 15:28 ` [PATCH 13/13] ARM: axxia: remove entire platform Arnd Bergmann
@ 2026-09-08 17:40 ` Linus Walleij
2026-09-08 18:23 ` Krzysztof Kozlowski
2026-09-08 20:02 ` Sverdlin, Alexander
2 siblings, 0 replies; 70+ messages in thread
From: Linus Walleij @ 2026-09-08 17:40 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Alexandre Belloni, Russell King,
Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Anders Berg
On Tue, Sep 8, 2026 at 5:30 PM Arnd Bergmann <arnd@kernel.org> wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The initial Axxia port was contributed by LSI in 2014, but never completed
> after the sale of the business unit to Intel, which kept supporting the
> bulk of the drivers in their own downstream BSP.
>
> The downstream work has also ended now, and there is no realistic chance
> that anyone would rewrite it all into an upstreamable port.
>
> Remove it now that the 7.3LTS release is out and can be used as the
> base for one more downstream rebase of the downstream patches if needed.
>
> Cc: Krzysztof Kozlowski <krzk@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Alexander Sverdlin <alexander.sverdlin@siemens.com>
> Cc: Ethan Nelson-Moore <enelsonmoore@gmail.com>
> Cc: Anders Berg <anders.berg@lsi.com>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linusw@kernel.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 13/13] ARM: axxia: remove entire platform
2026-09-08 15:28 ` [PATCH 13/13] ARM: axxia: remove entire platform Arnd Bergmann
2026-09-08 17:40 ` Linus Walleij
@ 2026-09-08 18:23 ` Krzysztof Kozlowski
2026-09-08 20:02 ` Sverdlin, Alexander
2 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2026-09-08 18:23 UTC (permalink / raw)
To: Arnd Bergmann, Alexandre Belloni, Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap, Anders Berg
On 08/09/2026 17:28, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The initial Axxia port was contributed by LSI in 2014, but never completed
> after the sale of the business unit to Intel, which kept supporting the
> bulk of the drivers in their own downstream BSP.
>
> The downstream work has also ended now, and there is no realistic chance
> that anyone would rewrite it all into an upstreamable port.
>
> Remove it now that the 7.3LTS release is out and can be used as the
> base for one more downstream rebase of the downstream patches if needed.
>
> Cc: Krzysztof Kozlowski <krzk@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Alexander Sverdlin <alexander.sverdlin@siemens.com>
> Cc: Ethan Nelson-Moore <enelsonmoore@gmail.com>
> Cc: Anders Berg <anders.berg@lsi.com>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 13/13] ARM: axxia: remove entire platform
2026-09-08 15:28 ` [PATCH 13/13] ARM: axxia: remove entire platform Arnd Bergmann
2026-09-08 17:40 ` Linus Walleij
2026-09-08 18:23 ` Krzysztof Kozlowski
@ 2026-09-08 20:02 ` Sverdlin, Alexander
2 siblings, 0 replies; 70+ messages in thread
From: Sverdlin, Alexander @ 2026-09-08 20:02 UTC (permalink / raw)
To: arnd; +Cc: linux-arm-kernel, devicetree, linux-kernel, anders.berg, arnd
On Tue, 2026-09-08 at 17:28 +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The initial Axxia port was contributed by LSI in 2014, but never completed
> after the sale of the business unit to Intel, which kept supporting the
> bulk of the drivers in their own downstream BSP.
>
> The downstream work has also ended now, and there is no realistic chance
> that anyone would rewrite it all into an upstreamable port.
>
> Remove it now that the 7.3LTS release is out and can be used as the
> base for one more downstream rebase of the downstream patches if needed.
>
> Cc: Krzysztof Kozlowski <krzk@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Alexander Sverdlin <alexander.sverdlin@siemens.com>
> Cc: Ethan Nelson-Moore <enelsonmoore@gmail.com>
> Cc: Anders Berg <anders.berg@lsi.com>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
> ---
> .../devicetree/bindings/arm/axxia.yaml | 23 --
> MAINTAINERS | 8 -
> arch/arm/Kconfig | 2 -
> arch/arm/Makefile | 2 -
> arch/arm/boot/dts/intel/Makefile | 1 -
> arch/arm/boot/dts/intel/axm/Makefile | 5 -
> .../boot/dts/intel/axm/axm5516-amarillo.dts | 47 ----
> arch/arm/boot/dts/intel/axm/axm5516-cpus.dtsi | 200 ---------------
> arch/arm/boot/dts/intel/axm/axm55xx.dtsi | 200 ---------------
> arch/arm/configs/axm55xx_defconfig | 231 ------------------
> arch/arm/mach-axxia/Kconfig | 17 --
> arch/arm/mach-axxia/Makefile | 3 -
> arch/arm/mach-axxia/axxia.c | 19 --
> arch/arm/mach-axxia/platsmp.c | 87 -------
> 14 files changed, 845 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/axxia.yaml
> delete mode 100644 arch/arm/boot/dts/intel/axm/Makefile
> delete mode 100644 arch/arm/boot/dts/intel/axm/axm5516-amarillo.dts
> delete mode 100644 arch/arm/boot/dts/intel/axm/axm5516-cpus.dtsi
> delete mode 100644 arch/arm/boot/dts/intel/axm/axm55xx.dtsi
> delete mode 100644 arch/arm/configs/axm55xx_defconfig
> delete mode 100644 arch/arm/mach-axxia/Kconfig
> delete mode 100644 arch/arm/mach-axxia/Makefile
> delete mode 100644 arch/arm/mach-axxia/axxia.c
> delete mode 100644 arch/arm/mach-axxia/platsmp.c
--
Alexander Sverdlin
Siemens AG
www.siemens.com
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 00/13] ARM: deprecated platform removal
2026-09-08 15:27 [PATCH 00/13] ARM: deprecated platform removal Arnd Bergmann
` (12 preceding siblings ...)
2026-09-08 15:28 ` [PATCH 13/13] ARM: axxia: remove entire platform Arnd Bergmann
@ 2026-09-08 16:53 ` Randy Dunlap
2026-09-08 16:56 ` Randy Dunlap
2026-09-08 18:33 ` Arnd Bergmann
13 siblings, 2 replies; 70+ messages in thread
From: Randy Dunlap @ 2026-09-08 16:53 UTC (permalink / raw)
To: Arnd Bergmann, Krzysztof Kozlowski, Alexandre Belloni,
Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap
On 9/8/26 8:27 AM, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> In the 7.3 kernel, I marked a number of platforms and features as
> deprecated, with the plan to keep these around for the LTS kernel, but
> remove them in 7.4, see [1].
>
> Cleaning out the deprecated platform code has turned into a larger effort
> than I expected, currently standing at 300 patches, with a lot of them
> still in need of being split up into smaller ones, see [2] for a current
> snapshot.
>
> The first series here removes just the bits in arch/arm/mach-*/, plus
> the portions that directly depend on the removed Kconfig symbols where
> these are trivial to remove.
>
> The parts that are not included are those that remove architectural
> features and device drivers that become unused after this part. Some of
> those may also make their way into 7.4, but at this point I would target
> 7.5 for most of them, to keep the dependencies simple.
>
> This also gives everyone a chance to voice their objections in case
> that some of the removed platform code does have active users after all,
> before all the corresponding drivers are gone.
>
> Arnd
>
> Links:
> [1] https://lore.kernel.org/all/20260701212353.2196041-1-arnd@kernel.org/
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/log/?h=board-remove-7.3
>
> Arnd Bergmann (13):
> ARM: remove sa1100 platform
> ARM: remove footbridge
> ARM: remove riscpc
> ARM: remove legacy pxa board files
> ARM: orion/dove/mv78xx0: remove all board files
> ARM: omap2: remove omap24xx support
> ARM: imx: remove i.MX31 SoC support
> ARM: imx: remove nommu support
> ARM: lpc18xx: remove entire platform
> ARM: stm32: remove stm32f4/f7/h7 MCU support
> ARM: versatile: remove mps2 support
> ARM: at91: remove samv7 support
> ARM: axxia: remove entire platform
>
> Documentation/arch/arm/index.rst | 1 -
> Documentation/arch/arm/netwinder.rst | 85 -
I don't see netwinder.rst in any of the single patches.
Should it be in one of them?
[snip]
> arch/arm/configs/netwinder_defconfig | 88 -
Same for netwinder_defconfig.
If netwinder is going away, can all of
Documentation/arch/arm/nwfpe/ also go away?
Or do all of these come later (in phase 2 or 3)?
thanks.
--
~Randy
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 00/13] ARM: deprecated platform removal
2026-09-08 16:53 ` [PATCH 00/13] ARM: deprecated platform removal Randy Dunlap
@ 2026-09-08 16:56 ` Randy Dunlap
2026-09-08 18:33 ` Arnd Bergmann
1 sibling, 0 replies; 70+ messages in thread
From: Randy Dunlap @ 2026-09-08 16:56 UTC (permalink / raw)
To: Arnd Bergmann, Krzysztof Kozlowski, Alexandre Belloni,
Linus Walleij, Russell King
Cc: Drew Fustini, Arnd Bergmann, Rob Herring, Conor Dooley,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Claudiu Beznea,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
Robert Jarzmik, Kristoffer Ericson, Ethan Nelson-Moore,
Geert Uytterhoeven, Alexander Sverdlin, Shawn Guo,
Karl Mehltretter, David Hildenbrand (Arm),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, linux-omap
On 9/8/26 9:53 AM, Randy Dunlap wrote:
>
>
> On 9/8/26 8:27 AM, Arnd Bergmann wrote:
>> From: Arnd Bergmann <arnd@arndb.de>
>>
>> In the 7.3 kernel, I marked a number of platforms and features as
>> deprecated, with the plan to keep these around for the LTS kernel, but
>> remove them in 7.4, see [1].
>>
>> Cleaning out the deprecated platform code has turned into a larger effort
>> than I expected, currently standing at 300 patches, with a lot of them
>> still in need of being split up into smaller ones, see [2] for a current
>> snapshot.
>>
>> The first series here removes just the bits in arch/arm/mach-*/, plus
>> the portions that directly depend on the removed Kconfig symbols where
>> these are trivial to remove.
>>
>> The parts that are not included are those that remove architectural
>> features and device drivers that become unused after this part. Some of
>> those may also make their way into 7.4, but at this point I would target
>> 7.5 for most of them, to keep the dependencies simple.
>>
>> This also gives everyone a chance to voice their objections in case
>> that some of the removed platform code does have active users after all,
>> before all the corresponding drivers are gone.
>>
>> Arnd
>>
>> Links:
>> [1] https://lore.kernel.org/all/20260701212353.2196041-1-arnd@kernel.org/
>> [2] https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/log/?h=board-remove-7.3
>>
>> Arnd Bergmann (13):
>> ARM: remove sa1100 platform
>> ARM: remove footbridge
>> ARM: remove riscpc
>> ARM: remove legacy pxa board files
>> ARM: orion/dove/mv78xx0: remove all board files
>> ARM: omap2: remove omap24xx support
>> ARM: imx: remove i.MX31 SoC support
>> ARM: imx: remove nommu support
>> ARM: lpc18xx: remove entire platform
>> ARM: stm32: remove stm32f4/f7/h7 MCU support
>> ARM: versatile: remove mps2 support
>> ARM: at91: remove samv7 support
>> ARM: axxia: remove entire platform
>>
>> Documentation/arch/arm/index.rst | 1 -
>> Documentation/arch/arm/netwinder.rst | 85 -
>
> I don't see netwinder.rst in any of the single patches.
> Should it be in one of them?
>
>
> [snip]
>
>> arch/arm/configs/netwinder_defconfig | 88 -
>
> Same for netwinder_defconfig.
>
> If netwinder is going away, can all of
> Documentation/arch/arm/nwfpe/ also go away?
>
> Or do all of these come later (in phase 2 or 3)?
gag. I hadn't received patch 02/13 yet. Didn't realize that. :(
Only the nwfpe/ question remains.
--
~Randy
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH 00/13] ARM: deprecated platform removal
2026-09-08 16:53 ` [PATCH 00/13] ARM: deprecated platform removal Randy Dunlap
2026-09-08 16:56 ` Randy Dunlap
@ 2026-09-08 18:33 ` Arnd Bergmann
2026-09-08 18:39 ` Randy Dunlap
1 sibling, 1 reply; 70+ messages in thread
From: Arnd Bergmann @ 2026-09-08 18:33 UTC (permalink / raw)
To: Randy Dunlap, Arnd Bergmann, Krzysztof Kozlowski,
Alexandre Belloni, Linus Walleij, Russell King
Cc: Drew Fustini, Rob Herring, Conor Dooley, Liviu Dudau,
Sudeep Holla, Lorenzo Pieralisi, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Vladimir Zapolskiy,
Stefan Agner, Maxime Coquelin, Alexandre Torgue, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Nicolas Ferre, Claudiu Beznea, Andrew Lunn,
Sebastian Hesselbarth, Gregory Clement, Robert Jarzmik,
Kristoffer Ericson, Ethan Nelson-Moore, Geert Uytterhoeven,
A. Sverdlin, Shawn Guo, Karl Mehltretter,
David Hildenbrand (Red Hat),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, Linux-OMAP
On Tue, Sep 8, 2026, at 18:53, Randy Dunlap wrote:
>
> If netwinder is going away, can all of
> Documentation/arch/arm/nwfpe/ also go away?
>
> Or do all of these come later (in phase 2 or 3)?
nwfpe is used on all OABI platforms, not just netwinder, so
the patch to remove that comes in the next series after removing
OABI. See
https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/commit/?id=ff375183fe225b79de700f004181405ff6a739cc
for the draft patch.
Arnd
^ permalink raw reply [flat|nested] 70+ messages in thread* Re: [PATCH 00/13] ARM: deprecated platform removal
2026-09-08 18:33 ` Arnd Bergmann
@ 2026-09-08 18:39 ` Randy Dunlap
0 siblings, 0 replies; 70+ messages in thread
From: Randy Dunlap @ 2026-09-08 18:39 UTC (permalink / raw)
To: Arnd Bergmann, Arnd Bergmann, Krzysztof Kozlowski,
Alexandre Belloni, Linus Walleij, Russell King
Cc: Drew Fustini, Rob Herring, Conor Dooley, Liviu Dudau,
Sudeep Holla, Lorenzo Pieralisi, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Vladimir Zapolskiy,
Stefan Agner, Maxime Coquelin, Alexandre Torgue, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Nicolas Ferre, Claudiu Beznea, Andrew Lunn,
Sebastian Hesselbarth, Gregory Clement, Robert Jarzmik,
Kristoffer Ericson, Ethan Nelson-Moore, Geert Uytterhoeven,
A. Sverdlin, Shawn Guo, Karl Mehltretter,
David Hildenbrand (Red Hat),
Nicolas Pitre, linux-doc, linux-kernel, linux-arm-kernel,
devicetree, imx, linux-stm32, Linux-OMAP
On 9/8/26 11:33 AM, Arnd Bergmann wrote:
> On Tue, Sep 8, 2026, at 18:53, Randy Dunlap wrote:
>>
>> If netwinder is going away, can all of
>> Documentation/arch/arm/nwfpe/ also go away?
>>
>> Or do all of these come later (in phase 2 or 3)?
>
> nwfpe is used on all OABI platforms, not just netwinder, so
> the patch to remove that comes in the next series after removing
> OABI. See
>
> https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/commit/?id=ff375183fe225b79de700f004181405ff6a739cc
>
> for the draft patch.
Got it. Thanks.
--
~Randy
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