[PATCH] drm/amdgpu/smu: Enable UCLK after init in AMD Radeon Pro 5300

[PATCH] drm/amdgpu/smu: Enable UCLK after init in AMD Radeon Pro 5300

[Atharva Tiwari]

On the AMD Radeon PRO 5300, enabling UCLK_BIT in
navi10_init_allowed_features causes errors such as:

SMU: No response msg_reg: 6 resp_reg: 0

or:

SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x00000006 SMN_C2PMSG_82:0x00000000

To work around this issue, we use smu_set_pp_feature_mask() to enable UCLK_BIT instead.

Fixes:
https://gitlab.freedesktop.org/drm/amd/-/work_items/4895

Tested-by: Guna R. Bharati <062bel313@gmail.com>
Signed-off-by: Atharva Tiwari <atharvatiwarilinuxdev@gmail.com>
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c     | 33 +++++++++++++++++++
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   |  7 +++-
 2 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 3969a7670..c05ceb0be 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -905,6 +905,33 @@ static int smu_apply_default_config_table_settings(struct smu_context *smu)
 	return smu_set_config_table(smu, &adev->pm.config_table);
 }
 
+static int smu_apply_late_quirks(struct smu_context *smu)
+{
+	struct pci_dev *pdev = smu->adev->pdev;
+	int ret = 0;
+	uint32_t features[2];
+	struct smu_feature_bits feature_mask;
+	uint64_t mask;
+
+	if (pdev->device == 0x7340 &&
+			pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
+			pdev->subsystem_device == 0x0219) {
+		ret = smu_feature_get_enabled_mask(smu, &feature_mask);
+		if (ret)
+			return ret;
+
+		smu_feature_bits_to_arr32(&feature_mask, features, 64);
+		features[0] |= BIT(3);
+		mask = ((uint64_t)features[1] << 32) | features[0];
+
+		ret = smu_set_pp_feature_mask(smu, mask);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
 static int smu_late_init(struct amdgpu_ip_block *ip_block)
 {
 	struct amdgpu_device *adev = ip_block->adev;
@@ -977,6 +1004,12 @@ static int smu_late_init(struct amdgpu_ip_block *ip_block)
 
 	smu_restore_dpm_user_profile(smu);
 
+	ret = smu_apply_late_quirks(smu);
+	if (ret) {
+		dev_err(adev->dev, "Unable to apply late quirks\n");
+		return ret;
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 6dfc3b585..ed67e4bfc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -349,7 +349,12 @@ navi10_init_allowed_features(struct smu_context *smu)
 	      (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
 	      (adev->rev_id == 0)) &&
 	    (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
-		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT);
+		if (!(adev->pdev->device == 0x7340 &&
+				adev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
+				adev->pdev->subsystem_device == 0x0219))
+			smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED,
+					FEATURE_DPM_UCLK_BIT);
+
 		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT);
 		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT);
 	}
-- 
2.43.0

RE: [PATCH] drm/amdgpu/smu: Enable UCLK after init in AMD Radeon Pro 5300

[Feng, Kenneth]

AMD General

This issue is also addressed in the thread: [RFC PATCH] drm/amd/pm: defer UCLK DPM enablement on Apple Navi 14 0218.
I think the workaround can be merged for Apple specifically between this patch and that patch from Ed Schofield.
The same questions:
1. can this workaround setting be put right after the SMU_MSG_EnableAllSmuFeatures is acked?
2. Does Apple accept this workaround instead of a root cause on how SMU_MSG_EnableAllSmuFeatures is not acked back?
Thanks.


-----Original Message-----
From: Atharva Tiwari <atharvatiwarilinuxdev@gmail.com>
Sent: Tuesday, August 25, 2026 3:04 AM
Cc: Atharva Tiwari <atharvatiwarilinuxdev@gmail.com>; Guna R . Bharati <062bel313@gmail.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; David Airlie <airlied@gmail.com>; Simona Vetter <simona@ffwll.ch>; amd-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; linux-kernel@vger.kernel.org
Subject: [PATCH] drm/amdgpu/smu: Enable UCLK after init in AMD Radeon Pro 5300

[You don't often get email from atharvatiwarilinuxdev@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]

On the AMD Radeon PRO 5300, enabling UCLK_BIT in navi10_init_allowed_features causes errors such as:

SMU: No response msg_reg: 6 resp_reg: 0

or:

SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x00000006 SMN_C2PMSG_82:0x00000000

To work around this issue, we use smu_set_pp_feature_mask() to enable UCLK_BIT instead.

Fixes:
https://gitlab.freedesktop.org/drm/amd/-/work_items/4895

Tested-by: Guna R. Bharati <062bel313@gmail.com>
Signed-off-by: Atharva Tiwari <atharvatiwarilinuxdev@gmail.com>
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c     | 33 +++++++++++++++++++
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   |  7 +++-
 2 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 3969a7670..c05ceb0be 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -905,6 +905,33 @@ static int smu_apply_default_config_table_settings(struct smu_context *smu)
        return smu_set_config_table(smu, &adev->pm.config_table);  }

+static int smu_apply_late_quirks(struct smu_context *smu) {
+       struct pci_dev *pdev = smu->adev->pdev;
+       int ret = 0;
+       uint32_t features[2];
+       struct smu_feature_bits feature_mask;
+       uint64_t mask;
+
+       if (pdev->device == 0x7340 &&
+                       pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
+                       pdev->subsystem_device == 0x0219) {
+               ret = smu_feature_get_enabled_mask(smu, &feature_mask);
+               if (ret)
+                       return ret;
+
+               smu_feature_bits_to_arr32(&feature_mask, features, 64);
+               features[0] |= BIT(3);
+               mask = ((uint64_t)features[1] << 32) | features[0];
+
+               ret = smu_set_pp_feature_mask(smu, mask);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
 static int smu_late_init(struct amdgpu_ip_block *ip_block)  {
        struct amdgpu_device *adev = ip_block->adev; @@ -977,6 +1004,12 @@ static int smu_late_init(struct amdgpu_ip_block *ip_block)

        smu_restore_dpm_user_profile(smu);

+       ret = smu_apply_late_quirks(smu);
+       if (ret) {
+               dev_err(adev->dev, "Unable to apply late quirks\n");
+               return ret;
+       }
+
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 6dfc3b585..ed67e4bfc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -349,7 +349,12 @@ navi10_init_allowed_features(struct smu_context *smu)
              (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
              (adev->rev_id == 0)) &&
            (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
-               smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT);
+               if (!(adev->pdev->device == 0x7340 &&
+                               adev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
+                               adev->pdev->subsystem_device == 0x0219))
+                       smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED,
+                                       FEATURE_DPM_UCLK_BIT);
+
                smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT);
                smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT);
        }
--
2.43.0

Re: [PATCH] drm/amdgpu/smu: Enable UCLK after init in AMD Radeon Pro 5300

[Ed Schofield]

Hi Kenneth, hi Atharva,

Thanks for bringing the two threads together. I've tried your suggestion on my iMac20,1 (1002:7340 / 106b:0218, revision 0x41), with SMU firmware 53.38.0. I tried two warm boots and both failed.

On the same AMD staging base as my RFC, I moved UCLK enablement to the beginning of navi10_set_default_dpm_table(), along with the readback check and supported-feature update. I removed the later enable and refresh from post-init. UCLK was still excluded from enable-all, and both memory-voltage features stayed the same. I didn't add any delay or extra mailbox tracing.

Both boots reported:

    SMU: No response msg_reg: 8 resp_reg: 0
    in params:00000008
    Apple 0218 default-table UCLK enable failed: -62

AMDGPU failed to bind in both cases. I checked that the experimental module was loaded and the firmware files hadn't changed.

This also fits an earlier test with T2 7.1.8. With UCLK excluded from enable-all, I tried enabling it separately immediately after smu_v11_0_system_features_control(smu, true) returned successfully. The trace shows EnableAllSmuFeatures returning 0x1, then EnableSmuFeaturesLow with argument 0x8 timing out with response 0 and -ETIME.

The default-table function is reached only after enable-all returns successfully, so waiting for that acknowledgement doesn't seem to be enough on this board. I don't yet know whether it needs more time or some other initialization step. I'd keep post-init for now: that version passed the ten recorded AMD staging warm boots. These tests don't establish the earliest safe point.

As for Apple, I can't speak for Apple or confirm their approval. I'm testing this as a Linux user. Do we need their input before merging an Apple-specific workaround? If so, could AMD help find the right contact? I'd still welcome a fix for the underlying firmware problem.

I agree we should coordinate the two patches. Mine covers only 0218/rev 0x41; Atharva's covers 0219. We'd need to test the combined change on both boards before broadening the match.

Thanks!
    Ed

RE: [PATCH] drm/amdgpu/smu: Enable UCLK after init in AMD Radeon Pro 5300

[Feng, Kenneth]

AMD General

Oh ok, thanks a lot, Ed.
Since it is Linux, I assume that Apple does not pay much attention to it.
Once your patch is merged with Atharva's and tested, then we can review and get them checked in.


-----Original Message-----
From: Ed Schofield <ed@aicharmers.com>
Sent: Wednesday, September 9, 2026 4:02 PM
To: Feng, Kenneth <Kenneth.Feng@amd.com>
Cc: Atharva Tiwari <atharvatiwarilinuxdev@gmail.com>; Guna R . Bharati <062bel313@gmail.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; airlied@gmail.com; simona@ffwll.ch; amd-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; linux-kernel@vger.kernel.org
Subject: Re: [PATCH] drm/amdgpu/smu: Enable UCLK after init in AMD Radeon Pro 5300

Hi Kenneth, hi Atharva,

Thanks for bringing the two threads together. I've tried your suggestion on my iMac20,1 (1002:7340 / 106b:0218, revision 0x41), with SMU firmware 53.38.0. I tried two warm boots and both failed.

On the same AMD staging base as my RFC, I moved UCLK enablement to the beginning of navi10_set_default_dpm_table(), along with the readback check and supported-feature update. I removed the later enable and refresh from post-init. UCLK was still excluded from enable-all, and both memory-voltage features stayed the same. I didn't add any delay or extra mailbox tracing.

Both boots reported:

    SMU: No response msg_reg: 8 resp_reg: 0
    in params:00000008
    Apple 0218 default-table UCLK enable failed: -62

AMDGPU failed to bind in both cases. I checked that the experimental module was loaded and the firmware files hadn't changed.

This also fits an earlier test with T2 7.1.8. With UCLK excluded from enable-all, I tried enabling it separately immediately after smu_v11_0_system_features_control(smu, true) returned successfully. The trace shows EnableAllSmuFeatures returning 0x1, then EnableSmuFeaturesLow with argument 0x8 timing out with response 0 and -ETIME.

The default-table function is reached only after enable-all returns successfully, so waiting for that acknowledgement doesn't seem to be enough on this board. I don't yet know whether it needs more time or some other initialization step. I'd keep post-init for now: that version passed the ten recorded AMD staging warm boots. These tests don't establish the earliest safe point.

As for Apple, I can't speak for Apple or confirm their approval. I'm testing this as a Linux user. Do we need their input before merging an Apple-specific workaround? If so, could AMD help find the right contact? I'd still welcome a fix for the underlying firmware problem.

I agree we should coordinate the two patches. Mine covers only 0218/rev 0x41; Atharva's covers 0219. We'd need to test the combined change on both boards before broadening the match.

Thanks!
    Ed

[PATCH v2] drm/amd/pm: defer UCLK DPM enablement on Apple Navi 14

[Ed Schofield]

Apple Navi 14 boards 1002:7340/106b:0218 (revision 0x41) and
1002:7340/106b:0219 can time out when EnableAllSmuFeatures includes
UCLK DPM, leaving amdgpu without a DRM device.

Exclude only UCLK DPM from the initial allowed features and enable it
separately in the Navi post-init callback. On 0218, enabling UCLK just
after EnableAllSmuFeatures or at the start of default DPM table setup
still timed out. The earlier 0218-only patch passed ten warm boots with
UCLK enabled in post-init. The earliest safe point remains unknown.

Check the enabled firmware bit, update the supported-feature bit and
rebuild the memory DPM table and sustainable clock limits before the
UMC workaround and UMD clock setup. Validate the PPT memory states that
DCN20 consumes before post-init. Preserve both memory-voltage features
and honor PP_MCLK_DPM_MASK.

Combine Atharva Tiwari's delayed-UCLK proposal for 0219 with the Navi
post-init implementation for 0218. Retain the revision restriction for
0218 and the revision-independent 0219 match from Atharva's proposal.

The combined patch passed ten warm boots on 0218, with rendering and
H.264 video decoding checks on every boot. Testing on 0219 is still
pending.

Link: https://www.mail-archive.com/amd-gfx@lists.freedesktop.org/msg149770.html
Link: https://github.com/t2linux/kernel/issues/19#issuecomment-5537823876
Assisted-by: Codex:GPT-6
Signed-off-by: Ed Schofield <ed@aicharmers.com>
---
Changes since the 0218-only RFC:
- Add the 0219 board match from Atharva's proposal, without a revision
  restriction. Keep the 0218 match limited to revision 0x41.
- Keep the Navi post-init implementation and clock-state updates from
  the RFC. Atharva's proposal enabled UCLK at the end of smu_late_init().
- Record the failed tests at the start of default DPM table setup and
  ten successful warm boots of the combined patch on 0218.

 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 82 +++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index f8ca5eb9a..d7cc41a5d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -60,6 +60,19 @@
 
 static int navi10_init_ppt_limits(struct smu_context *smu);
 
+static bool navi14_needs_late_uclk(struct amdgpu_device *adev)
+{
+	struct pci_dev *pdev = adev->pdev;
+
+	return pdev->vendor == PCI_VENDOR_ID_ATI &&
+		pdev->device == 0x7340 &&
+		pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
+		((pdev->subsystem_device == 0x0218 &&
+		  pdev->revision == 0x41) ||
+		 pdev->subsystem_device == 0x0219) &&
+		(adev->pm.pp_feature & PP_MCLK_DPM_MASK);
+}
+
 static const struct smu_feature_bits navi10_dpm_features = {
 	.bits = {
 		SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT),
@@ -356,6 +369,11 @@ navi10_init_allowed_features(struct smu_context *smu)
 		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT);
 	}
 
+	/* These boards time out if EnableAllSmuFeatures includes UCLK DPM. */
+	if (navi14_needs_late_uclk(adev))
+		smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED,
+					   FEATURE_DPM_UCLK_BIT);
+
 	if (is_asic_secure(smu) &&
 	    (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
 	    (adev->rev_id == 0))
@@ -470,6 +488,25 @@ static int navi10_store_powerplay_table(struct smu_context *smu)
 	return 0;
 }
 
+/* DCN20 consumes these PPT states before the post-init UCLK enable. */
+static int navi14_imac_check_uclk_states(struct smu_context *smu)
+{
+	PPTable_t *ppt = smu->smu_table.driver_pptable;
+	unsigned int count, i;
+
+	if (!navi14_needs_late_uclk(smu->adev))
+		return 0;
+
+	count = ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
+	if (!count || count > ARRAY_SIZE(ppt->FreqTableUclk))
+		return -EINVAL;
+	for (i = 0; i < count; i++) {
+		if (!ppt->FreqTableUclk[i])
+			return -EINVAL;
+	}
+	return 0;
+}
+
 static int navi10_setup_pptable(struct smu_context *smu)
 {
 	int ret = 0;
@@ -490,6 +527,10 @@ static int navi10_setup_pptable(struct smu_context *smu)
 	if (ret)
 		return ret;
 
+	ret = navi14_imac_check_uclk_states(smu);
+	if (ret)
+		return ret;
+
 	return navi10_init_ppt_limits(smu);
 }
 
@@ -3219,6 +3260,41 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
 					       NULL);
 }
 
+/* Rebuild memory clocks before the UMC workaround and UMD clock setup. */
+static int navi14_imac_late_uclk_enable(struct smu_context *smu)
+{
+	struct smu_11_0_dpm_context *dpm = smu->smu_dpm.dpm_context;
+	struct smu_dpm_table *table = &dpm->dpm_tables.uclk_table;
+	PPTable_t *ppt = smu->smu_table.driver_pptable;
+	struct smu_feature_bits enabled;
+	int ret;
+
+	if (!navi14_needs_late_uclk(smu->adev))
+		return 0;
+
+	ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT, true);
+	if (ret)
+		return ret;
+	ret = smu_cmn_get_enabled_mask(smu, &enabled);
+	if (ret)
+		return ret;
+	if (!smu_feature_bits_is_set(&enabled, FEATURE_DPM_UCLK_BIT))
+		return -EIO;
+
+	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_SUPPORTED,
+				 FEATURE_DPM_UCLK_BIT);
+	table->clk_type = SMU_UCLK;
+	ret = smu_v11_0_set_single_dpm_table(smu, SMU_UCLK, table);
+	if (ret)
+		return ret;
+	if (!table->count)
+		return -EINVAL;
+	if (!ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete)
+		table->flags |= SMU_DPM_TABLE_FINE_GRAINED;
+
+	return smu_v11_0_init_max_sustainable_clocks(smu);
+}
+
 static int navi10_post_smu_init(struct smu_context *smu)
 {
 	struct amdgpu_device *adev = smu->adev;
@@ -3227,6 +3303,12 @@ static int navi10_post_smu_init(struct smu_context *smu)
 	if (amdgpu_sriov_vf(adev))
 		return 0;
 
+	ret = navi14_imac_late_uclk_enable(smu);
+	if (ret) {
+		dev_err(adev->dev, "Failed to enable late UCLK DPM: %d\n", ret);
+		return ret;
+	}
+
 	ret = navi10_run_umc_cdr_workaround(smu);
 	if (ret)
 		dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");

base-commit: c22f9a61e288580824edbbc3ae5a29c9a338594f
-- 
2.55.0

RE: [PATCH v2] drm/amd/pm: defer UCLK DPM enablement on Apple Navi 14

[Feng, Kenneth]

AMD General

Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>

-----Original Message-----
From: Ed Schofield <ed@aicharmers.com>
Sent: Wednesday, September 9, 2026 8:35 PM
To: Feng, Kenneth <Kenneth.Feng@amd.com>
Cc: atharvatiwarilinuxdev@gmail.com; 062bel313@gmail.com; amd-gfx@lists.freedesktop.org; Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; airlied@gmail.com; simona@ffwll.ch; dri-devel@lists.freedesktop.org; linux-kernel@vger.kernel.org
Subject: [PATCH v2] drm/amd/pm: defer UCLK DPM enablement on Apple Navi 14

Apple Navi 14 boards 1002:7340/106b:0218 (revision 0x41) and
1002:7340/106b:0219 can time out when EnableAllSmuFeatures includes UCLK DPM, leaving amdgpu without a DRM device.

Exclude only UCLK DPM from the initial allowed features and enable it separately in the Navi post-init callback. On 0218, enabling UCLK just after EnableAllSmuFeatures or at the start of default DPM table setup still timed out. The earlier 0218-only patch passed ten warm boots with UCLK enabled in post-init. The earliest safe point remains unknown.

Check the enabled firmware bit, update the supported-feature bit and rebuild the memory DPM table and sustainable clock limits before the UMC workaround and UMD clock setup. Validate the PPT memory states that
DCN20 consumes before post-init. Preserve both memory-voltage features and honor PP_MCLK_DPM_MASK.

Combine Atharva Tiwari's delayed-UCLK proposal for 0219 with the Navi post-init implementation for 0218. Retain the revision restriction for
0218 and the revision-independent 0219 match from Atharva's proposal.

The combined patch passed ten warm boots on 0218, with rendering and
H.264 video decoding checks on every boot. Testing on 0219 is still pending.

Link: https://www.mail-archive.com/amd-gfx@lists.freedesktop.org/msg149770.html
Link: https://github.com/t2linux/kernel/issues/19#issuecomment-5537823876
Assisted-by: Codex:GPT-6
Signed-off-by: Ed Schofield <ed@aicharmers.com>
---
Changes since the 0218-only RFC:
- Add the 0219 board match from Atharva's proposal, without a revision
  restriction. Keep the 0218 match limited to revision 0x41.
- Keep the Navi post-init implementation and clock-state updates from
  the RFC. Atharva's proposal enabled UCLK at the end of smu_late_init().
- Record the failed tests at the start of default DPM table setup and
  ten successful warm boots of the combined patch on 0218.

 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 82 +++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index f8ca5eb9a..d7cc41a5d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -60,6 +60,19 @@

 static int navi10_init_ppt_limits(struct smu_context *smu);

+static bool navi14_needs_late_uclk(struct amdgpu_device *adev) {
+       struct pci_dev *pdev = adev->pdev;
+
+       return pdev->vendor == PCI_VENDOR_ID_ATI &&
+               pdev->device == 0x7340 &&
+               pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
+               ((pdev->subsystem_device == 0x0218 &&
+                 pdev->revision == 0x41) ||
+                pdev->subsystem_device == 0x0219) &&
+               (adev->pm.pp_feature & PP_MCLK_DPM_MASK); }
+
 static const struct smu_feature_bits navi10_dpm_features = {
        .bits = {
                SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT),
@@ -356,6 +369,11 @@ navi10_init_allowed_features(struct smu_context *smu)
                smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT);
        }

+       /* These boards time out if EnableAllSmuFeatures includes UCLK DPM. */
+       if (navi14_needs_late_uclk(adev))
+               smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED,
+                                          FEATURE_DPM_UCLK_BIT);
+
        if (is_asic_secure(smu) &&
            (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
            (adev->rev_id == 0))
@@ -470,6 +488,25 @@ static int navi10_store_powerplay_table(struct smu_context *smu)
        return 0;
 }

+/* DCN20 consumes these PPT states before the post-init UCLK enable. */
+static int navi14_imac_check_uclk_states(struct smu_context *smu) {
+       PPTable_t *ppt = smu->smu_table.driver_pptable;
+       unsigned int count, i;
+
+       if (!navi14_needs_late_uclk(smu->adev))
+               return 0;
+
+       count = ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
+       if (!count || count > ARRAY_SIZE(ppt->FreqTableUclk))
+               return -EINVAL;
+       for (i = 0; i < count; i++) {
+               if (!ppt->FreqTableUclk[i])
+                       return -EINVAL;
+       }
+       return 0;
+}
+
 static int navi10_setup_pptable(struct smu_context *smu)  {
        int ret = 0;
@@ -490,6 +527,10 @@ static int navi10_setup_pptable(struct smu_context *smu)
        if (ret)
                return ret;

+       ret = navi14_imac_check_uclk_states(smu);
+       if (ret)
+               return ret;
+
        return navi10_init_ppt_limits(smu);
 }

@@ -3219,6 +3260,41 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
                                               NULL);
 }

+/* Rebuild memory clocks before the UMC workaround and UMD clock setup.
+*/ static int navi14_imac_late_uclk_enable(struct smu_context *smu) {
+       struct smu_11_0_dpm_context *dpm = smu->smu_dpm.dpm_context;
+       struct smu_dpm_table *table = &dpm->dpm_tables.uclk_table;
+       PPTable_t *ppt = smu->smu_table.driver_pptable;
+       struct smu_feature_bits enabled;
+       int ret;
+
+       if (!navi14_needs_late_uclk(smu->adev))
+               return 0;
+
+       ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT, true);
+       if (ret)
+               return ret;
+       ret = smu_cmn_get_enabled_mask(smu, &enabled);
+       if (ret)
+               return ret;
+       if (!smu_feature_bits_is_set(&enabled, FEATURE_DPM_UCLK_BIT))
+               return -EIO;
+
+       smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_SUPPORTED,
+                                FEATURE_DPM_UCLK_BIT);
+       table->clk_type = SMU_UCLK;
+       ret = smu_v11_0_set_single_dpm_table(smu, SMU_UCLK, table);
+       if (ret)
+               return ret;
+       if (!table->count)
+               return -EINVAL;
+       if (!ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete)
+               table->flags |= SMU_DPM_TABLE_FINE_GRAINED;
+
+       return smu_v11_0_init_max_sustainable_clocks(smu);
+}
+
 static int navi10_post_smu_init(struct smu_context *smu)  {
        struct amdgpu_device *adev = smu->adev; @@ -3227,6 +3303,12 @@ static int navi10_post_smu_init(struct smu_context *smu)
        if (amdgpu_sriov_vf(adev))
                return 0;

+       ret = navi14_imac_late_uclk_enable(smu);
+       if (ret) {
+               dev_err(adev->dev, "Failed to enable late UCLK DPM: %d\n", ret);
+               return ret;
+       }
+
        ret = navi10_run_umc_cdr_workaround(smu);
        if (ret)
                dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");

base-commit: c22f9a61e288580824edbbc3ae5a29c9a338594f
--
2.55.0

Re: [PATCH v2] drm/amd/pm: defer UCLK DPM enablement on Apple Navi 14

[Alex Deucher]

Applied.  Thanks!

On Thu, Sep 10, 2026 at 6:40 AM Feng, Kenneth <Kenneth.Feng@amd.com> wrote:
>
> AMD General
>
> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
>
> -----Original Message-----
> From: Ed Schofield <ed@aicharmers.com>
> Sent: Wednesday, September 9, 2026 8:35 PM
> To: Feng, Kenneth <Kenneth.Feng@amd.com>
> Cc: atharvatiwarilinuxdev@gmail.com; 062bel313@gmail.com; amd-gfx@lists.freedesktop.org; Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; airlied@gmail.com; simona@ffwll.ch; dri-devel@lists.freedesktop.org; linux-kernel@vger.kernel.org
> Subject: [PATCH v2] drm/amd/pm: defer UCLK DPM enablement on Apple Navi 14
>
> Apple Navi 14 boards 1002:7340/106b:0218 (revision 0x41) and
> 1002:7340/106b:0219 can time out when EnableAllSmuFeatures includes UCLK DPM, leaving amdgpu without a DRM device.
>
> Exclude only UCLK DPM from the initial allowed features and enable it separately in the Navi post-init callback. On 0218, enabling UCLK just after EnableAllSmuFeatures or at the start of default DPM table setup still timed out. The earlier 0218-only patch passed ten warm boots with UCLK enabled in post-init. The earliest safe point remains unknown.
>
> Check the enabled firmware bit, update the supported-feature bit and rebuild the memory DPM table and sustainable clock limits before the UMC workaround and UMD clock setup. Validate the PPT memory states that
> DCN20 consumes before post-init. Preserve both memory-voltage features and honor PP_MCLK_DPM_MASK.
>
> Combine Atharva Tiwari's delayed-UCLK proposal for 0219 with the Navi post-init implementation for 0218. Retain the revision restriction for
> 0218 and the revision-independent 0219 match from Atharva's proposal.
>
> The combined patch passed ten warm boots on 0218, with rendering and
> H.264 video decoding checks on every boot. Testing on 0219 is still pending.
>
> Link: https://www.mail-archive.com/amd-gfx@lists.freedesktop.org/msg149770.html
> Link: https://github.com/t2linux/kernel/issues/19#issuecomment-5537823876
> Assisted-by: Codex:GPT-6
> Signed-off-by: Ed Schofield <ed@aicharmers.com>
> ---
> Changes since the 0218-only RFC:
> - Add the 0219 board match from Atharva's proposal, without a revision
>   restriction. Keep the 0218 match limited to revision 0x41.
> - Keep the Navi post-init implementation and clock-state updates from
>   the RFC. Atharva's proposal enabled UCLK at the end of smu_late_init().
> - Record the failed tests at the start of default DPM table setup and
>   ten successful warm boots of the combined patch on 0218.
>
>  .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 82 +++++++++++++++++++
>  1 file changed, 82 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index f8ca5eb9a..d7cc41a5d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -60,6 +60,19 @@
>
>  static int navi10_init_ppt_limits(struct smu_context *smu);
>
> +static bool navi14_needs_late_uclk(struct amdgpu_device *adev) {
> +       struct pci_dev *pdev = adev->pdev;
> +
> +       return pdev->vendor == PCI_VENDOR_ID_ATI &&
> +               pdev->device == 0x7340 &&
> +               pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
> +               ((pdev->subsystem_device == 0x0218 &&
> +                 pdev->revision == 0x41) ||
> +                pdev->subsystem_device == 0x0219) &&
> +               (adev->pm.pp_feature & PP_MCLK_DPM_MASK); }
> +
>  static const struct smu_feature_bits navi10_dpm_features = {
>         .bits = {
>                 SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT),
> @@ -356,6 +369,11 @@ navi10_init_allowed_features(struct smu_context *smu)
>                 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT);
>         }
>
> +       /* These boards time out if EnableAllSmuFeatures includes UCLK DPM. */
> +       if (navi14_needs_late_uclk(adev))
> +               smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED,
> +                                          FEATURE_DPM_UCLK_BIT);
> +
>         if (is_asic_secure(smu) &&
>             (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
>             (adev->rev_id == 0))
> @@ -470,6 +488,25 @@ static int navi10_store_powerplay_table(struct smu_context *smu)
>         return 0;
>  }
>
> +/* DCN20 consumes these PPT states before the post-init UCLK enable. */
> +static int navi14_imac_check_uclk_states(struct smu_context *smu) {
> +       PPTable_t *ppt = smu->smu_table.driver_pptable;
> +       unsigned int count, i;
> +
> +       if (!navi14_needs_late_uclk(smu->adev))
> +               return 0;
> +
> +       count = ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
> +       if (!count || count > ARRAY_SIZE(ppt->FreqTableUclk))
> +               return -EINVAL;
> +       for (i = 0; i < count; i++) {
> +               if (!ppt->FreqTableUclk[i])
> +                       return -EINVAL;
> +       }
> +       return 0;
> +}
> +
>  static int navi10_setup_pptable(struct smu_context *smu)  {
>         int ret = 0;
> @@ -490,6 +527,10 @@ static int navi10_setup_pptable(struct smu_context *smu)
>         if (ret)
>                 return ret;
>
> +       ret = navi14_imac_check_uclk_states(smu);
> +       if (ret)
> +               return ret;
> +
>         return navi10_init_ppt_limits(smu);
>  }
>
> @@ -3219,6 +3260,41 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
>                                                NULL);
>  }
>
> +/* Rebuild memory clocks before the UMC workaround and UMD clock setup.
> +*/ static int navi14_imac_late_uclk_enable(struct smu_context *smu) {
> +       struct smu_11_0_dpm_context *dpm = smu->smu_dpm.dpm_context;
> +       struct smu_dpm_table *table = &dpm->dpm_tables.uclk_table;
> +       PPTable_t *ppt = smu->smu_table.driver_pptable;
> +       struct smu_feature_bits enabled;
> +       int ret;
> +
> +       if (!navi14_needs_late_uclk(smu->adev))
> +               return 0;
> +
> +       ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT, true);
> +       if (ret)
> +               return ret;
> +       ret = smu_cmn_get_enabled_mask(smu, &enabled);
> +       if (ret)
> +               return ret;
> +       if (!smu_feature_bits_is_set(&enabled, FEATURE_DPM_UCLK_BIT))
> +               return -EIO;
> +
> +       smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_SUPPORTED,
> +                                FEATURE_DPM_UCLK_BIT);
> +       table->clk_type = SMU_UCLK;
> +       ret = smu_v11_0_set_single_dpm_table(smu, SMU_UCLK, table);
> +       if (ret)
> +               return ret;
> +       if (!table->count)
> +               return -EINVAL;
> +       if (!ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete)
> +               table->flags |= SMU_DPM_TABLE_FINE_GRAINED;
> +
> +       return smu_v11_0_init_max_sustainable_clocks(smu);
> +}
> +
>  static int navi10_post_smu_init(struct smu_context *smu)  {
>         struct amdgpu_device *adev = smu->adev; @@ -3227,6 +3303,12 @@ static int navi10_post_smu_init(struct smu_context *smu)
>         if (amdgpu_sriov_vf(adev))
>                 return 0;
>
> +       ret = navi14_imac_late_uclk_enable(smu);
> +       if (ret) {
> +               dev_err(adev->dev, "Failed to enable late UCLK DPM: %d\n", ret);
> +               return ret;
> +       }
> +
>         ret = navi10_run_umc_cdr_workaround(smu);
>         if (ret)
>                 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");
>
> base-commit: c22f9a61e288580824edbbc3ae5a29c9a338594f
> --
> 2.55.0

Re: [PATCH v2] drm/amd/pm: defer UCLK DPM enablement on Apple Navi 14

[Atharva Tiwari]

> Applied.  Thanks!

Hey, so im the author of the original patch:

https://github.com/t2linux/wiki/issues/743#issuecomment-5347204171

The author of the patch mentions this:
> Combine Atharva Tiwari's delayed-UCLK proposal for 0219 with the Navi post-init implementation for 0218. Retain the revision restriction for
> 0218 and the revision-independent 0219 match from Atharva's proposal.

So as the main developer of the patch, i would like you to remove this patch,
as it dosent give me credit, and also this is not the solution to this problem
as i have mentioned here:

https://github.com/t2linux/wiki/issues/743#issuecomment-5608044095

thanks