* [PATCH v2 1/3] dt-bindings: arm: rockchip: Add FriendlyElec NanoPi R28S
2026-09-07 14:13 [PATCH v2 0/3] arm64: dts: rockchip: Add FriendlyElec NanoPi R28S 安容 via B4 Relay
@ 2026-09-07 14:13 ` 安容 via B4 Relay
2026-09-07 14:13 ` [PATCH v2 2/3] arm64: dts: rockchip: Split out the common NanoPi RK3528 parts 安容 via B4 Relay
2026-09-07 14:13 ` [PATCH v2 3/3] arm64: dts: rockchip: Add devicetree for the FriendlyElec NanoPi R28S 安容 via B4 Relay
2 siblings, 0 replies; 7+ messages in thread
From: 安容 via B4 Relay @ 2026-09-07 14:13 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel,
Chukun Pan, jensen, 安容
From: 安容 <HystericalDragons@proton.me>
The NanoPi R28S is a dual gigabit Ethernet router board based on the
Rockchip RK3528 SoC.
Signed-off-by: 安容 <HystericalDragons@proton.me>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 81744fbee9..709e2cc44d 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -347,6 +347,11 @@ properties:
- friendlyarm,nanopi-r2s-plus
- const: rockchip,rk3328
+ - description: FriendlyElec NanoPi R28S
+ items:
+ - const: friendlyarm,nanopi-r28s
+ - const: rockchip,rk3528
+
- description: FriendlyElec NanoPi R3S
items:
- const: friendlyarm,nanopi-r3s
--
2.55.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v2 2/3] arm64: dts: rockchip: Split out the common NanoPi RK3528 parts
2026-09-07 14:13 [PATCH v2 0/3] arm64: dts: rockchip: Add FriendlyElec NanoPi R28S 安容 via B4 Relay
2026-09-07 14:13 ` [PATCH v2 1/3] dt-bindings: arm: " 安容 via B4 Relay
@ 2026-09-07 14:13 ` 安容 via B4 Relay
2026-09-09 13:47 ` Andrey Korshunov
2026-09-07 14:13 ` [PATCH v2 3/3] arm64: dts: rockchip: Add devicetree for the FriendlyElec NanoPi R28S 安容 via B4 Relay
2 siblings, 1 reply; 7+ messages in thread
From: 安容 via B4 Relay @ 2026-09-07 14:13 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel,
Chukun Pan, jensen, 安容
From: 安容 <HystericalDragons@proton.me>
The FriendlyElec NanoPi Zero2 and the NanoPi R28S share their power
tree, storage, RGMII Ethernet, RTC and debug console. Move those parts
into rk3528-nanopi.dtsi so the NanoPi R28S can reuse them, and leave
only the board specific nodes in the NanoPi Zero2 devicetree.
Suggested-by: Chukun Pan <amadeus@jmu.edu.cn>
Signed-off-by: 安容 <HystericalDragons@proton.me>
---
.../boot/dts/rockchip/rk3528-nanopi-zero2.dts | 271 +-------------------
arch/arm64/boot/dts/rockchip/rk3528-nanopi.dtsi | 279 +++++++++++++++++++++
2 files changed, 280 insertions(+), 270 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts
index 97d85124d2..48e4273872 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts
@@ -2,41 +2,13 @@
/dts-v1/;
-#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pwm/pwm.h>
-#include "rk3528.dtsi"
+#include "rk3528-nanopi.dtsi"
/ {
model = "FriendlyElec NanoPi Zero2";
compatible = "friendlyarm,nanopi-zero2", "rockchip,rk3528";
- aliases {
- ethernet0 = &gmac1;
- i2c1 = &i2c1;
- mmc0 = &sdhci;
- mmc1 = &sdmmc;
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:1500000n8";
- };
-
- adc-keys-0 {
- compatible = "adc-keys";
- io-channels = <&saradc 0>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <100>;
-
- button-maskrom {
- label = "MASK";
- linux,code = <KEY_SETUP>;
- press-threshold-microvolt = <0>;
- };
- };
-
adc-keys-1 {
compatible = "adc-keys";
io-channels = <&saradc 1>;
@@ -83,66 +55,6 @@ vcc0v6_ddr: regulator-0v6-vcc-ddr {
vin-supply = <&vcc5v0_sys>;
};
- vdd_0v9: regulator-0v9-vdd {
- compatible = "regulator-fixed";
- regulator-name = "vdd_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc_ddr: regulator-1v1-vcc-ddr {
- compatible = "regulator-fixed";
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc_1v8: regulator-1v8-vcc {
- compatible = "regulator-fixed";
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- };
-
- vcc_3v3: regulator-3v3-vcc {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_sd: regulator-3v3-vcc-sd {
- compatible = "regulator-fixed";
- gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_pwren_l>;
- regulator-name = "vcc3v3_sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_3v3>;
- };
-
- vcc5v0_sys: regulator-5v0-vcc-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
usb2_host_5v: regulator-5v0-usb2-host {
compatible = "regulator-fixed";
enable-active-high;
@@ -154,112 +66,9 @@ usb2_host_5v: regulator-5v0-usb2-host {
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
-
- vccio_sd: regulator-vccio-sd {
- compatible = "regulator-gpio";
- gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_vol_ctrl_h>;
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- states = <1800000 0x0>, <3300000 0x1>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vdd_arm: regulator-vdd-arm {
- compatible = "pwm-regulator";
- pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
- pwm-supply = <&vcc5v0_sys>;
- regulator-name = "vdd_arm";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <746000>;
- regulator-max-microvolt = <1201000>;
- regulator-settling-time-up-us = <250>;
- };
-
- vdd_logic: regulator-vdd-logic {
- compatible = "pwm-regulator";
- pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>;
- pwm-supply = <&vcc5v0_sys>;
- regulator-name = "vdd_logic";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <705000>;
- regulator-max-microvolt = <1006000>;
- regulator-settling-time-up-us = <250>;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
-
-&gmac1 {
- clock_in_out = "output";
- phy-handle = <&rgmii_phy>;
- phy-mode = "rgmii-id";
- phy-supply = <&vcc_3v3>;
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>,
- <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>;
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_logic>;
- status = "okay";
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1m0_xfer>;
- status = "okay";
-
- hym8563: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- interrupt-parent = <&gpio4>;
- interrupts = <RK_PC1 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&rtc_int_l>;
- wakeup-source;
- };
-};
-
-&mdio1 {
- rgmii_phy: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x1>;
- pinctrl-names = "default";
- pinctrl-0 = <&gmac1_rstn_l>;
- reset-assert-us = <20000>;
- reset-deassert-us = <100000>;
- reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
- };
};
&pinctrl {
- ethernet {
- gmac1_rstn_l: gmac1-rstn-l {
- rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
leds {
led1: led1 {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -270,22 +79,6 @@ led_sys: led-sys {
};
};
- rtc {
- rtc_int_l: rtc-int-l {
- rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- sdmmc {
- sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h {
- rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- sdmmc_pwren_l: sdmmc-pwren-l {
- rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
usb {
usb20_host1_pwren: usb20-host1-pwren {
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -293,52 +86,6 @@ usb20_host1_pwren: usb20-host1-pwren {
};
};
-&pwm1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm1m0_pins>;
- status = "okay";
-};
-
-&pwm2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm2m0_pins>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- no-sd;
- no-sdio;
- non-removable;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v3_sd>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0m0_xfer>;
- status = "okay";
-};
-
&usb_host0_ehci {
status = "okay";
};
@@ -347,23 +94,7 @@ &usb_host0_ohci {
status = "okay";
};
-&usb_host0_xhci {
- extcon = <&usb2phy>;
- maximum-speed = "high-speed";
- phys = <&usb2phy_otg>;
- phy-names = "usb2-phy";
- status = "okay";
-};
-
-&usb2phy {
- status = "okay";
-};
-
&usb2phy_host {
phy-supply = <&usb2_host_5v>;
status = "okay";
};
-
-&usb2phy_otg {
- status = "okay";
-};
diff --git a/arch/arm64/boot/dts/rockchip/rk3528-nanopi.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-nanopi.dtsi
new file mode 100644
index 0000000000..8d9d0056a0
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3528-nanopi.dtsi
@@ -0,0 +1,279 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Common parts of the FriendlyElec RK3528 boards: NanoPi Zero2 and NanoPi R28S.
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3528.dtsi"
+
+/ {
+ aliases {
+ ethernet0 = &gmac1;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:1500000n8";
+ };
+
+ adc-keys-0 {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-maskrom {
+ label = "MASK";
+ linux,code = <KEY_SETUP>;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ vdd_0v9: regulator-0v9-vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_ddr: regulator-1v1-vcc-ddr {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_1v8: regulator-1v8-vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ };
+
+ vcc_3v3: regulator-3v3-vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_sd: regulator-3v3-vcc-sd {
+ compatible = "regulator-fixed";
+ gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_pwren_l>;
+ regulator-name = "vcc3v3_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3>;
+ };
+
+ vcc5v0_sys: regulator-5v0-vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vccio_sd: regulator-vccio-sd {
+ compatible = "regulator-gpio";
+ gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_vol_ctrl_h>;
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ states = <1800000 0x0>, <3300000 0x1>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vdd_arm: regulator-vdd-arm {
+ compatible = "pwm-regulator";
+ pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
+ pwm-supply = <&vcc5v0_sys>;
+ regulator-name = "vdd_arm";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <746000>;
+ regulator-max-microvolt = <1201000>;
+ regulator-settling-time-up-us = <250>;
+ };
+
+ vdd_logic: regulator-vdd-logic {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>;
+ pwm-supply = <&vcc5v0_sys>;
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <705000>;
+ regulator-max-microvolt = <1006000>;
+ regulator-settling-time-up-us = <250>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&gmac1 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>,
+ <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_logic>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1m0_xfer>;
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <RK_PC1 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtc_int_l>;
+ wakeup-source;
+ };
+};
+
+&mdio1 {
+ rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1_rstn_l>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ ethernet {
+ gmac1_rstn_l: gmac1-rstn-l {
+ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ rtc {
+ rtc_int_l: rtc-int-l {
+ rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_pwren_l: sdmmc-pwren-l {
+ rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h {
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1m0_pins>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2m0_pins>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m0_xfer>;
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ extcon = <&usb2phy>;
+ maximum-speed = "high-speed";
+ phys = <&usb2phy_otg>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
+
+&usb2phy {
+ status = "okay";
+};
+
+&usb2phy_otg {
+ status = "okay";
+};
--
2.55.0
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v2 2/3] arm64: dts: rockchip: Split out the common NanoPi RK3528 parts
2026-09-07 14:13 ` [PATCH v2 2/3] arm64: dts: rockchip: Split out the common NanoPi RK3528 parts 安容 via B4 Relay
@ 2026-09-09 13:47 ` Andrey Korshunov
2026-09-09 14:47 ` 安容
0 siblings, 1 reply; 7+ messages in thread
From: Andrey Korshunov @ 2026-09-09 13:47 UTC (permalink / raw)
To: devnull+hystericaldragons.proton.me
Cc: HystericalDragons, amadeus, jensenhuang, heiko, robh, krzk+dt,
conor+dt, linux-rockchip, linux-arm-kernel, devicetree,
linux-kernel
On Mon Sep 7, 2026 at 4:13 PM CEST, 安容 via B4 Relay wrote:
> +&mdio1 {
> + rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0x1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac1_rstn_l>;
> + reset-assert-us = <20000>;
> + reset-deassert-us = <100000>;
> + reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
> + };
> +};
This is carried over unchanged from the NanoPi Zero2, so not something
this patch introduces, but it is worth fixing while the node is being
moved, because as written the port depends on the bootloader.
of_mdio_bus_register() reads the PHY ID with get_phy_device() before
phy_device_register() fetches the PHY node's reset-gpios, so a PHY that
the bootloader left in reset is simply not found:
mdio_bus stmmac-0: MDIO device at address 1 is missing.
I hit exactly that on a NanoPi R28S booted with mainline U-Boot
(generic-rk3528), which does not touch that pin - the RGMII port never
came up. Describing the reset on the MAC instead makes stmmac install it
as mii_bus->reset, which runs before the bus is scanned:
&gmac1 {
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>;
snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
};
with &gmac1_rstn_l moved to the MAC's pinctrl-0 and the three reset
properties dropped from the PHY node. Then the port comes up whatever
the bootloader did, on both boards. Armbian carries the same change for
the NanoPi Zero2, for the same reason.
I had an R28S series of my own out before I saw yours; I am dropping it.
Happy to test this one on the hardware and send a Tested-by.
Andrey
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v2 2/3] arm64: dts: rockchip: Split out the common NanoPi RK3528 parts
2026-09-09 13:47 ` Andrey Korshunov
@ 2026-09-09 14:47 ` 安容
0 siblings, 0 replies; 7+ messages in thread
From: 安容 @ 2026-09-09 14:47 UTC (permalink / raw)
To: Andrey Korshunov
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel,
Chukun Pan, jensen
On Wed, Sep 09, 2026 at 04:47:16PM +0300, Andrey Korshunov wrote:
> of_mdio_bus_register() reads the PHY ID with get_phy_device() before
> phy_device_register() fetches the PHY node's reset-gpios, so a PHY that
> the bootloader left in reset is simply not found:
>
> mdio_bus stmmac-0: MDIO device at address 1 is missing.
Thanks, the diagnosis is right and I have reproduced the ordering in
the code: `__of_mdiobus_register()` registers the bus before it walks the
children. And for a PHY node with only the generic c22 compatible,
`fwnode_mdiobus_register_phy()` reads the PHY ID via `get_phy_device()`
before `phy_device_register()` gets as far as requesting reset-gpios.
> Describing the reset on the MAC instead makes stmmac install it
> as mii_bus->reset, which runs before the bus is scanned:
>
> &gmac1 {
> snps,reset-active-low;
> snps,reset-delays-us = <0 20000 100000>;
> snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
> };
But I would rather not use those: snps,reset-gpio, snps,reset-active-low
and snps,reset-delays-us are all deprecated in snps,dwmac.yaml,
so a new DTS using them is unlikely to get through netdev.
The MDIO bus level reset in mdio.yaml solves the same ordering problem
without using deprecated property. `__mdiobus_register()` asserts and
releases it before any device on the bus is registered, so it also
covers the DT described case where the bus is not scanned at all:
&mdio1 {
reset-delay-us = <20000>;
reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
reset-post-delay-us = <100000>;
rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
};
};
with gmac1_rstn_l moved to the MAC's pinctrl-0, since the MDIO bus has
no device of its own for pinctrl to bind to. There is only one PHY on
mdio1, so a bus wide reset is equivalent to the per-PHY one.
v3 carries this as patch 1, against the NanoPi Zero2 and ahead of the
move, so it can be backported:
<https://lore.kernel.org/r/20260909-r28s-upstream-v3-0-ee3e1a34a353@proton.me>
A `Tested-by` on that form would be very welcome, since it is not the
variant you tested.
> I had an R28S series of my own out before I saw yours; I am dropping it.
Sorry about the duplicated effort.
Thanks,
Rong An.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 3/3] arm64: dts: rockchip: Add devicetree for the FriendlyElec NanoPi R28S
2026-09-07 14:13 [PATCH v2 0/3] arm64: dts: rockchip: Add FriendlyElec NanoPi R28S 安容 via B4 Relay
2026-09-07 14:13 ` [PATCH v2 1/3] dt-bindings: arm: " 安容 via B4 Relay
2026-09-07 14:13 ` [PATCH v2 2/3] arm64: dts: rockchip: Split out the common NanoPi RK3528 parts 安容 via B4 Relay
@ 2026-09-07 14:13 ` 安容 via B4 Relay
2026-09-09 10:53 ` Diederik de Haas
2 siblings, 1 reply; 7+ messages in thread
From: 安容 via B4 Relay @ 2026-09-07 14:13 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel,
Chukun Pan, jensen, 安容
From: 安容 <HystericalDragons@proton.me>
The NanoPi R28S is a dual gigabit Ethernet router board based on the
Rockchip RK3528 SoC, designed and developed by FriendlyElec. It shares
most of its design with the NanoPi Zero2, so it builds on the common
rk3528-nanopi.dtsi.
Specification:
- Rockchip RK3528
- 1GB RAM
- eMMC socket (optional)
- MicroSD slot
- 1x 1000Base-T (GMAC1, Realtek RTL8211F)
- 1x 1000Base-T (PCIe, Realtek RTL8111H)
- AICSemi AIC8800D80 SDIO WiFi
- 3x LEDs (SYS, LAN, WAN)
- 1x USB 2.0 Type-C, peripheral only, shared with the 5V power input
- User and MaskROM buttons
- Haoyu HYM8563 RTC
- 1x USB Type-C debug UART (onboard WCH CH340E)
Assisted-by: LLM
Signed-off-by: 安容 <HystericalDragons@proton.me>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../arm64/boot/dts/rockchip/rk3528-nanopi-r28s.dts | 142 +++++++++++++++++++++
2 files changed, 143 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index b677914cd3..51a9889088 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -94,6 +94,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-vicharak-vaaman.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-armsom-sige1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-hinlink-h28k.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-nanopi-r28s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-nanopi-zero2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-radxa-e20c.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-rock-2a.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3528-nanopi-r28s.dts b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-r28s.dts
new file mode 100644
index 0000000000..b9e9f5af4e
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-r28s.dts
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2026 FriendlyElec Computer Tech. Co., Ltd.
+ * Copyright (c) 2026 安容 <HystericalDragons@proton.me>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "rk3528-nanopi.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPi R28S";
+ compatible = "friendlyarm,nanopi-r28s", "rockchip,rk3528";
+
+ aliases {
+ mmc2 = &sdio0;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usr_btn>;
+
+ button-user {
+ debounce-interval = <50>;
+ gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
+ label = "USER";
+ linux,code = <KEY_RESTART>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led1>, <&led2>, <&led_sys>;
+
+ led-lan {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "netdev";
+ };
+
+ led-sys {
+ color = <LED_COLOR_ID_RED>;
+ default-state = "on";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-wan {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_WAN;
+ gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "netdev";
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_wf>;
+ post-power-on-delay-ms = <100>;
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&combphy {
+ status = "okay";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_eth_perstb>;
+ reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&pinctrl {
+ gpio-keys {
+ usr_btn: usr-btn {
+ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ led1: led1 {
+ rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ led2: led2 {
+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ led_sys: led-sys {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie_eth_perstb: pcie-eth-perstb {
+ rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifi {
+ pwr_wf: pwr-wf {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdio0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m1_xfer>, <&uart2m1_ctsn>, <&uart2m1_rtsn>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ /* Type-C port, shared with the 5V power input */
+ dr_mode = "peripheral";
+};
--
2.55.0
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v2 3/3] arm64: dts: rockchip: Add devicetree for the FriendlyElec NanoPi R28S
2026-09-07 14:13 ` [PATCH v2 3/3] arm64: dts: rockchip: Add devicetree for the FriendlyElec NanoPi R28S 安容 via B4 Relay
@ 2026-09-09 10:53 ` Diederik de Haas
0 siblings, 0 replies; 7+ messages in thread
From: Diederik de Haas @ 2026-09-09 10:53 UTC (permalink / raw)
To: HystericalDragons, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner
Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel,
Chukun Pan, jensen
On Mon Sep 7, 2026 at 4:13 PM CEST, 安容 via B4 Relay wrote:
> From: 安容 <HystericalDragons@proton.me>
>
> The NanoPi R28S is a dual gigabit Ethernet router board based on the
> Rockchip RK3528 SoC, designed and developed by FriendlyElec. It shares
> most of its design with the NanoPi Zero2, so it builds on the common
> rk3528-nanopi.dtsi.
>
> Specification:
> - Rockchip RK3528
> - 1GB RAM
> - eMMC socket (optional)
> - MicroSD slot
> - 1x 1000Base-T (GMAC1, Realtek RTL8211F)
> - 1x 1000Base-T (PCIe, Realtek RTL8111H)
> - AICSemi AIC8800D80 SDIO WiFi
> - 3x LEDs (SYS, LAN, WAN)
> - 1x USB 2.0 Type-C, peripheral only, shared with the 5V power input
> - User and MaskROM buttons
> - Haoyu HYM8563 RTC
> - 1x USB Type-C debug UART (onboard WCH CH340E)
>
> Assisted-by: LLM
> Signed-off-by: 安容 <HystericalDragons@proton.me>
> ---
> arch/arm64/boot/dts/rockchip/Makefile | 1 +
> .../arm64/boot/dts/rockchip/rk3528-nanopi-r28s.dts | 142 +++++++++++++++++++++
> 2 files changed, 143 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> index b677914cd3..51a9889088 100644
> --- a/arch/arm64/boot/dts/rockchip/Makefile
> +++ b/arch/arm64/boot/dts/rockchip/Makefile
> @@ -94,6 +94,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-vicharak-vaaman.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-armsom-sige1.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-hinlink-h28k.dtb
> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-nanopi-r28s.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-nanopi-zero2.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-radxa-e20c.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-rock-2a.dtb
> diff --git a/arch/arm64/boot/dts/rockchip/rk3528-nanopi-r28s.dts b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-r28s.dts
If you run
``scripts/dtc/dt-check-style --mode=strict arch/arm64/boot/dts/rockchip/rk3528-nanopi-r28s.dts``
it will find a few (IMO) false-positives, but the property order of
pinctrl-0/pinctrl-names is valid and a blank line preceeding ``status`` too.
Cheers,
Diederik
> new file mode 100644
> index 0000000000..b9e9f5af4e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-r28s.dts
> @@ -0,0 +1,142 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
> + * Copyright (c) 2026 FriendlyElec Computer Tech. Co., Ltd.
> + * Copyright (c) 2026 安容 <HystericalDragons@proton.me>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/leds/common.h>
> +#include "rk3528-nanopi.dtsi"
> +
> +/ {
> + model = "FriendlyElec NanoPi R28S";
> + compatible = "friendlyarm,nanopi-r28s", "rockchip,rk3528";
> +
> + aliases {
> + mmc2 = &sdio0;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&usr_btn>;
> +
> + button-user {
> + debounce-interval = <50>;
> + gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
> + label = "USER";
> + linux,code = <KEY_RESTART>;
> + wakeup-source;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&led1>, <&led2>, <&led_sys>;
> +
> + led-lan {
> + color = <LED_COLOR_ID_GREEN>;
> + default-state = "off";
> + function = LED_FUNCTION_LAN;
> + gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "netdev";
> + };
> +
> + led-sys {
> + color = <LED_COLOR_ID_RED>;
> + default-state = "on";
> + function = LED_FUNCTION_HEARTBEAT;
> + gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> +
> + led-wan {
> + color = <LED_COLOR_ID_GREEN>;
> + default-state = "off";
> + function = LED_FUNCTION_WAN;
> + gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "netdev";
> + };
> + };
> +
> + sdio_pwrseq: sdio-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwr_wf>;
> + post-power-on-delay-ms = <100>;
> + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +&combphy {
> + status = "okay";
> +};
> +
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie_eth_perstb>;
> + reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>;
> + vpcie3v3-supply = <&vcc_3v3>;
> + status = "okay";
> +};
> +
> +&pinctrl {
> + gpio-keys {
> + usr_btn: usr-btn {
> + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
> + };
> + };
> +
> + leds {
> + led1: led1 {
> + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + led2: led2 {
> + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + led_sys: led-sys {
> + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + pcie {
> + pcie_eth_perstb: pcie-eth-perstb {
> + rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + wifi {
> + pwr_wf: pwr-wf {
> + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +};
> +
> +&sdio0 {
> + bus-width = <4>;
> + cap-sd-highspeed;
> + cap-sdio-irq;
> + keep-power-in-suspend;
> + mmc-pwrseq = <&sdio_pwrseq>;
> + non-removable;
> + sd-uhs-sdr104;
> + vqmmc-supply = <&vcc_1v8>;
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2m1_xfer>, <&uart2m1_ctsn>, <&uart2m1_rtsn>;
> + uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&usb_host0_xhci {
> + /* Type-C port, shared with the 5V power input */
> + dr_mode = "peripheral";
> +};
^ permalink raw reply [flat|nested] 7+ messages in thread